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TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/stm32f3xx_ll_bus.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_bus.h@168:b9e159c1930a
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 163:e59c8e839560 | 1 | /** |
| AnnaBridge | 163:e59c8e839560 | 2 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 3 | * @file stm32f3xx_ll_bus.h |
| AnnaBridge | 163:e59c8e839560 | 4 | * @author MCD Application Team |
| AnnaBridge | 163:e59c8e839560 | 5 | * @brief Header file of BUS LL module. |
| AnnaBridge | 163:e59c8e839560 | 6 | |
| AnnaBridge | 163:e59c8e839560 | 7 | @verbatim |
| AnnaBridge | 163:e59c8e839560 | 8 | ##### RCC Limitations ##### |
| AnnaBridge | 163:e59c8e839560 | 9 | ============================================================================== |
| AnnaBridge | 163:e59c8e839560 | 10 | [..] |
| AnnaBridge | 163:e59c8e839560 | 11 | A delay between an RCC peripheral clock enable and the effective peripheral |
| AnnaBridge | 163:e59c8e839560 | 12 | enabling should be taken into account in order to manage the peripheral read/write |
| AnnaBridge | 163:e59c8e839560 | 13 | from/to registers. |
| AnnaBridge | 163:e59c8e839560 | 14 | (+) This delay depends on the peripheral mapping. |
| AnnaBridge | 163:e59c8e839560 | 15 | (++) AHB & APB peripherals, 1 dummy read is necessary |
| AnnaBridge | 163:e59c8e839560 | 16 | |
| AnnaBridge | 163:e59c8e839560 | 17 | [..] |
| AnnaBridge | 163:e59c8e839560 | 18 | Workarounds: |
| AnnaBridge | 163:e59c8e839560 | 19 | (#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
| AnnaBridge | 163:e59c8e839560 | 20 | inserted in each LL_{BUS}_GRP{x}_EnableClock() function. |
| AnnaBridge | 163:e59c8e839560 | 21 | |
| AnnaBridge | 163:e59c8e839560 | 22 | @endverbatim |
| AnnaBridge | 163:e59c8e839560 | 23 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 24 | * @attention |
| AnnaBridge | 163:e59c8e839560 | 25 | * |
| AnnaBridge | 163:e59c8e839560 | 26 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 163:e59c8e839560 | 27 | * |
| AnnaBridge | 163:e59c8e839560 | 28 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 163:e59c8e839560 | 29 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 163:e59c8e839560 | 30 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 163:e59c8e839560 | 31 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 163:e59c8e839560 | 32 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 163:e59c8e839560 | 33 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 163:e59c8e839560 | 34 | * and/or other materials provided with the distribution. |
| AnnaBridge | 163:e59c8e839560 | 35 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 163:e59c8e839560 | 36 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 163:e59c8e839560 | 37 | * without specific prior written permission. |
| AnnaBridge | 163:e59c8e839560 | 38 | * |
| AnnaBridge | 163:e59c8e839560 | 39 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 163:e59c8e839560 | 40 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 163:e59c8e839560 | 41 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 163:e59c8e839560 | 42 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 163:e59c8e839560 | 43 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 163:e59c8e839560 | 44 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 163:e59c8e839560 | 45 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 163:e59c8e839560 | 46 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 163:e59c8e839560 | 47 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 163:e59c8e839560 | 48 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 163:e59c8e839560 | 49 | * |
| AnnaBridge | 163:e59c8e839560 | 50 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 51 | */ |
| AnnaBridge | 163:e59c8e839560 | 52 | |
| AnnaBridge | 163:e59c8e839560 | 53 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 54 | #ifndef __STM32F3xx_LL_BUS_H |
| AnnaBridge | 163:e59c8e839560 | 55 | #define __STM32F3xx_LL_BUS_H |
| AnnaBridge | 163:e59c8e839560 | 56 | |
| AnnaBridge | 163:e59c8e839560 | 57 | #ifdef __cplusplus |
| AnnaBridge | 163:e59c8e839560 | 58 | extern "C" { |
| AnnaBridge | 163:e59c8e839560 | 59 | #endif |
| AnnaBridge | 163:e59c8e839560 | 60 | |
| AnnaBridge | 163:e59c8e839560 | 61 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 62 | #include "stm32f3xx.h" |
| AnnaBridge | 163:e59c8e839560 | 63 | |
| AnnaBridge | 163:e59c8e839560 | 64 | /** @addtogroup STM32F3xx_LL_Driver |
| AnnaBridge | 163:e59c8e839560 | 65 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 66 | */ |
| AnnaBridge | 163:e59c8e839560 | 67 | |
| AnnaBridge | 163:e59c8e839560 | 68 | #if defined(RCC) |
| AnnaBridge | 163:e59c8e839560 | 69 | |
| AnnaBridge | 163:e59c8e839560 | 70 | /** @defgroup BUS_LL BUS |
| AnnaBridge | 163:e59c8e839560 | 71 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 72 | */ |
| AnnaBridge | 163:e59c8e839560 | 73 | |
| AnnaBridge | 163:e59c8e839560 | 74 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 75 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 76 | |
| AnnaBridge | 163:e59c8e839560 | 77 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 78 | |
| AnnaBridge | 163:e59c8e839560 | 79 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 80 | |
| AnnaBridge | 163:e59c8e839560 | 81 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 82 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 83 | /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants |
| AnnaBridge | 163:e59c8e839560 | 84 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 85 | */ |
| AnnaBridge | 163:e59c8e839560 | 86 | |
| AnnaBridge | 163:e59c8e839560 | 87 | /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH |
| AnnaBridge | 163:e59c8e839560 | 88 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 89 | */ |
| AnnaBridge | 163:e59c8e839560 | 90 | #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| AnnaBridge | 163:e59c8e839560 | 91 | #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN |
| AnnaBridge | 163:e59c8e839560 | 92 | #if defined(DMA2) |
| AnnaBridge | 163:e59c8e839560 | 93 | #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN |
| AnnaBridge | 163:e59c8e839560 | 94 | #endif /*DMA2*/ |
| AnnaBridge | 163:e59c8e839560 | 95 | #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN |
| AnnaBridge | 163:e59c8e839560 | 96 | #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN |
| AnnaBridge | 163:e59c8e839560 | 97 | #if defined(FMC_Bank1) |
| AnnaBridge | 163:e59c8e839560 | 98 | #define LL_AHB1_GRP1_PERIPH_FMC RCC_AHBENR_FMCEN |
| AnnaBridge | 163:e59c8e839560 | 99 | #endif /*FMC_Bank1*/ |
| AnnaBridge | 163:e59c8e839560 | 100 | #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN |
| AnnaBridge | 163:e59c8e839560 | 101 | #if defined(GPIOH) |
| AnnaBridge | 163:e59c8e839560 | 102 | #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN |
| AnnaBridge | 163:e59c8e839560 | 103 | #endif /*GPIOH*/ |
| AnnaBridge | 163:e59c8e839560 | 104 | #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN |
| AnnaBridge | 163:e59c8e839560 | 105 | #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN |
| AnnaBridge | 163:e59c8e839560 | 106 | #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN |
| AnnaBridge | 163:e59c8e839560 | 107 | #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN |
| AnnaBridge | 163:e59c8e839560 | 108 | #if defined(GPIOE) |
| AnnaBridge | 163:e59c8e839560 | 109 | #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN |
| AnnaBridge | 163:e59c8e839560 | 110 | #endif /*GPIOE*/ |
| AnnaBridge | 163:e59c8e839560 | 111 | #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN |
| AnnaBridge | 163:e59c8e839560 | 112 | #if defined(GPIOG) |
| AnnaBridge | 163:e59c8e839560 | 113 | #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN |
| AnnaBridge | 163:e59c8e839560 | 114 | #endif /*GPIOH*/ |
| AnnaBridge | 163:e59c8e839560 | 115 | #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN |
| AnnaBridge | 163:e59c8e839560 | 116 | #if defined(RCC_AHBENR_ADC1EN) |
| AnnaBridge | 163:e59c8e839560 | 117 | #define LL_AHB1_GRP1_PERIPH_ADC1 RCC_AHBENR_ADC1EN |
| AnnaBridge | 163:e59c8e839560 | 118 | #endif /*RCC_AHBENR_ADC1EN*/ |
| AnnaBridge | 163:e59c8e839560 | 119 | #if defined(ADC1_2_COMMON) |
| AnnaBridge | 163:e59c8e839560 | 120 | #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHBENR_ADC12EN |
| AnnaBridge | 163:e59c8e839560 | 121 | #endif /*ADC1_2_COMMON*/ |
| AnnaBridge | 163:e59c8e839560 | 122 | #if defined(ADC3_4_COMMON) |
| AnnaBridge | 163:e59c8e839560 | 123 | #define LL_AHB1_GRP1_PERIPH_ADC34 RCC_AHBENR_ADC34EN |
| AnnaBridge | 163:e59c8e839560 | 124 | #endif /*ADC3_4_COMMON*/ |
| AnnaBridge | 163:e59c8e839560 | 125 | /** |
| AnnaBridge | 163:e59c8e839560 | 126 | * @} |
| AnnaBridge | 163:e59c8e839560 | 127 | */ |
| AnnaBridge | 163:e59c8e839560 | 128 | |
| AnnaBridge | 163:e59c8e839560 | 129 | /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH |
| AnnaBridge | 163:e59c8e839560 | 130 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 131 | */ |
| AnnaBridge | 163:e59c8e839560 | 132 | #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| AnnaBridge | 163:e59c8e839560 | 133 | #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN |
| AnnaBridge | 163:e59c8e839560 | 134 | #if defined(TIM3) |
| AnnaBridge | 163:e59c8e839560 | 135 | #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN |
| AnnaBridge | 163:e59c8e839560 | 136 | #endif /*TIM3*/ |
| AnnaBridge | 163:e59c8e839560 | 137 | #if defined(TIM4) |
| AnnaBridge | 163:e59c8e839560 | 138 | #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN |
| AnnaBridge | 163:e59c8e839560 | 139 | #endif /*TIM4*/ |
| AnnaBridge | 163:e59c8e839560 | 140 | #if defined(TIM5) |
| AnnaBridge | 163:e59c8e839560 | 141 | #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN |
| AnnaBridge | 163:e59c8e839560 | 142 | #endif /*TIM5*/ |
| AnnaBridge | 163:e59c8e839560 | 143 | #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN |
| AnnaBridge | 163:e59c8e839560 | 144 | #if defined(TIM7) |
| AnnaBridge | 163:e59c8e839560 | 145 | #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN |
| AnnaBridge | 163:e59c8e839560 | 146 | #endif /*TIM7*/ |
| AnnaBridge | 163:e59c8e839560 | 147 | #if defined(TIM12) |
| AnnaBridge | 163:e59c8e839560 | 148 | #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN |
| AnnaBridge | 163:e59c8e839560 | 149 | #endif /*TIM12*/ |
| AnnaBridge | 163:e59c8e839560 | 150 | #if defined(TIM13) |
| AnnaBridge | 163:e59c8e839560 | 151 | #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN |
| AnnaBridge | 163:e59c8e839560 | 152 | #endif /*TIM13*/ |
| AnnaBridge | 163:e59c8e839560 | 153 | #if defined(TIM14) |
| AnnaBridge | 163:e59c8e839560 | 154 | #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN |
| AnnaBridge | 163:e59c8e839560 | 155 | #endif /*TIM14*/ |
| AnnaBridge | 163:e59c8e839560 | 156 | #if defined(TIM18) |
| AnnaBridge | 163:e59c8e839560 | 157 | #define LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN |
| AnnaBridge | 163:e59c8e839560 | 158 | #endif /*TIM18*/ |
| AnnaBridge | 163:e59c8e839560 | 159 | #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN |
| AnnaBridge | 163:e59c8e839560 | 160 | #if defined(SPI2) |
| AnnaBridge | 163:e59c8e839560 | 161 | #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN |
| AnnaBridge | 163:e59c8e839560 | 162 | #endif /*SPI2*/ |
| AnnaBridge | 163:e59c8e839560 | 163 | #if defined(SPI3) |
| AnnaBridge | 163:e59c8e839560 | 164 | #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN |
| AnnaBridge | 163:e59c8e839560 | 165 | #endif /*SPI3*/ |
| AnnaBridge | 163:e59c8e839560 | 166 | #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN |
| AnnaBridge | 163:e59c8e839560 | 167 | #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN |
| AnnaBridge | 163:e59c8e839560 | 168 | #if defined(UART4) |
| AnnaBridge | 163:e59c8e839560 | 169 | #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN |
| AnnaBridge | 163:e59c8e839560 | 170 | #endif /*UART4*/ |
| AnnaBridge | 163:e59c8e839560 | 171 | #if defined(UART5) |
| AnnaBridge | 163:e59c8e839560 | 172 | #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN |
| AnnaBridge | 163:e59c8e839560 | 173 | #endif /*UART5*/ |
| AnnaBridge | 163:e59c8e839560 | 174 | #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN |
| AnnaBridge | 163:e59c8e839560 | 175 | #if defined(I2C2) |
| AnnaBridge | 163:e59c8e839560 | 176 | #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN |
| AnnaBridge | 163:e59c8e839560 | 177 | #endif /*I2C2*/ |
| AnnaBridge | 163:e59c8e839560 | 178 | #if defined(USB) |
| AnnaBridge | 163:e59c8e839560 | 179 | #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN |
| AnnaBridge | 163:e59c8e839560 | 180 | #endif /*USB*/ |
| AnnaBridge | 163:e59c8e839560 | 181 | #if defined(CAN) |
| AnnaBridge | 163:e59c8e839560 | 182 | #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN |
| AnnaBridge | 163:e59c8e839560 | 183 | #endif /*CAN*/ |
| AnnaBridge | 163:e59c8e839560 | 184 | #if defined(DAC2) |
| AnnaBridge | 163:e59c8e839560 | 185 | #define LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN |
| AnnaBridge | 163:e59c8e839560 | 186 | #endif /*DAC2*/ |
| AnnaBridge | 163:e59c8e839560 | 187 | #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN |
| AnnaBridge | 163:e59c8e839560 | 188 | #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN |
| AnnaBridge | 163:e59c8e839560 | 189 | #if defined(CEC) |
| AnnaBridge | 163:e59c8e839560 | 190 | #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN |
| AnnaBridge | 163:e59c8e839560 | 191 | #endif /*CEC*/ |
| AnnaBridge | 163:e59c8e839560 | 192 | #if defined(I2C3) |
| AnnaBridge | 163:e59c8e839560 | 193 | #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN |
| AnnaBridge | 163:e59c8e839560 | 194 | #endif /*I2C3*/ |
| AnnaBridge | 163:e59c8e839560 | 195 | /** |
| AnnaBridge | 163:e59c8e839560 | 196 | * @} |
| AnnaBridge | 163:e59c8e839560 | 197 | */ |
| AnnaBridge | 163:e59c8e839560 | 198 | |
| AnnaBridge | 163:e59c8e839560 | 199 | /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH |
| AnnaBridge | 163:e59c8e839560 | 200 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 201 | */ |
| AnnaBridge | 163:e59c8e839560 | 202 | #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| AnnaBridge | 163:e59c8e839560 | 203 | #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN |
| AnnaBridge | 163:e59c8e839560 | 204 | #if defined(RCC_APB2ENR_ADC1EN) |
| AnnaBridge | 163:e59c8e839560 | 205 | #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN |
| AnnaBridge | 163:e59c8e839560 | 206 | #endif /*RCC_APB2ENR_ADC1EN*/ |
| AnnaBridge | 163:e59c8e839560 | 207 | #if defined(TIM1) |
| AnnaBridge | 163:e59c8e839560 | 208 | #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN |
| AnnaBridge | 163:e59c8e839560 | 209 | #endif /*TIM1*/ |
| AnnaBridge | 163:e59c8e839560 | 210 | #if defined(SPI1) |
| AnnaBridge | 163:e59c8e839560 | 211 | #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN |
| AnnaBridge | 163:e59c8e839560 | 212 | #endif /*SPI1*/ |
| AnnaBridge | 163:e59c8e839560 | 213 | #if defined(TIM8) |
| AnnaBridge | 163:e59c8e839560 | 214 | #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN |
| AnnaBridge | 163:e59c8e839560 | 215 | #endif /*TIM8*/ |
| AnnaBridge | 163:e59c8e839560 | 216 | #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN |
| AnnaBridge | 163:e59c8e839560 | 217 | #if defined(SPI4) |
| AnnaBridge | 163:e59c8e839560 | 218 | #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN |
| AnnaBridge | 163:e59c8e839560 | 219 | #endif /*SPI4*/ |
| AnnaBridge | 163:e59c8e839560 | 220 | #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN |
| AnnaBridge | 163:e59c8e839560 | 221 | #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN |
| AnnaBridge | 163:e59c8e839560 | 222 | #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN |
| AnnaBridge | 163:e59c8e839560 | 223 | #if defined(TIM19) |
| AnnaBridge | 163:e59c8e839560 | 224 | #define LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN |
| AnnaBridge | 163:e59c8e839560 | 225 | #endif /*TIM19*/ |
| AnnaBridge | 163:e59c8e839560 | 226 | #if defined(TIM20) |
| AnnaBridge | 163:e59c8e839560 | 227 | #define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN |
| AnnaBridge | 163:e59c8e839560 | 228 | #endif /*TIM20*/ |
| AnnaBridge | 163:e59c8e839560 | 229 | #if defined(HRTIM1) |
| AnnaBridge | 163:e59c8e839560 | 230 | #define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN |
| AnnaBridge | 163:e59c8e839560 | 231 | #endif /*HRTIM1*/ |
| AnnaBridge | 163:e59c8e839560 | 232 | #if defined(SDADC1) |
| AnnaBridge | 163:e59c8e839560 | 233 | #define LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN |
| AnnaBridge | 163:e59c8e839560 | 234 | #endif /*SDADC1*/ |
| AnnaBridge | 163:e59c8e839560 | 235 | #if defined(SDADC2) |
| AnnaBridge | 163:e59c8e839560 | 236 | #define LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN |
| AnnaBridge | 163:e59c8e839560 | 237 | #endif /*SDADC2*/ |
| AnnaBridge | 163:e59c8e839560 | 238 | #if defined(SDADC3) |
| AnnaBridge | 163:e59c8e839560 | 239 | #define LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN |
| AnnaBridge | 163:e59c8e839560 | 240 | #endif /*SDADC3*/ |
| AnnaBridge | 163:e59c8e839560 | 241 | /** |
| AnnaBridge | 163:e59c8e839560 | 242 | * @} |
| AnnaBridge | 163:e59c8e839560 | 243 | */ |
| AnnaBridge | 163:e59c8e839560 | 244 | |
| AnnaBridge | 163:e59c8e839560 | 245 | /** |
| AnnaBridge | 163:e59c8e839560 | 246 | * @} |
| AnnaBridge | 163:e59c8e839560 | 247 | */ |
| AnnaBridge | 163:e59c8e839560 | 248 | |
| AnnaBridge | 163:e59c8e839560 | 249 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 250 | |
| AnnaBridge | 163:e59c8e839560 | 251 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 252 | /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions |
| AnnaBridge | 163:e59c8e839560 | 253 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 254 | */ |
| AnnaBridge | 163:e59c8e839560 | 255 | |
| AnnaBridge | 163:e59c8e839560 | 256 | /** @defgroup BUS_LL_EF_AHB1 AHB1 |
| AnnaBridge | 163:e59c8e839560 | 257 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 258 | */ |
| AnnaBridge | 163:e59c8e839560 | 259 | |
| AnnaBridge | 163:e59c8e839560 | 260 | /** |
| AnnaBridge | 163:e59c8e839560 | 261 | * @brief Enable AHB1 peripherals clock. |
| AnnaBridge | 163:e59c8e839560 | 262 | * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 263 | * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 264 | * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 265 | * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 266 | * AHBENR FMCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 267 | * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 268 | * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 269 | * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 270 | * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 271 | * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 272 | * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 273 | * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 274 | * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 275 | * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 276 | * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 277 | * AHBENR ADC1EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 278 | * AHBENR ADC12EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 279 | * AHBENR ADC34EN LL_AHB1_GRP1_EnableClock |
| AnnaBridge | 163:e59c8e839560 | 280 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 281 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 163:e59c8e839560 | 282 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 163:e59c8e839560 | 283 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| AnnaBridge | 163:e59c8e839560 | 284 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 163:e59c8e839560 | 285 | * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 163:e59c8e839560 | 286 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 163:e59c8e839560 | 287 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 163:e59c8e839560 | 288 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 163:e59c8e839560 | 289 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 163:e59c8e839560 | 290 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 163:e59c8e839560 | 291 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 163:e59c8e839560 | 292 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 163:e59c8e839560 | 293 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 163:e59c8e839560 | 294 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 163:e59c8e839560 | 295 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 163:e59c8e839560 | 296 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 297 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) |
| AnnaBridge | 163:e59c8e839560 | 298 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) |
| AnnaBridge | 163:e59c8e839560 | 299 | * |
| AnnaBridge | 163:e59c8e839560 | 300 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 301 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 302 | */ |
| AnnaBridge | 163:e59c8e839560 | 303 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 304 | { |
| AnnaBridge | 163:e59c8e839560 | 305 | __IO uint32_t tmpreg; |
| AnnaBridge | 163:e59c8e839560 | 306 | SET_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 307 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 163:e59c8e839560 | 308 | tmpreg = READ_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 309 | (void)tmpreg; |
| AnnaBridge | 163:e59c8e839560 | 310 | } |
| AnnaBridge | 163:e59c8e839560 | 311 | |
| AnnaBridge | 163:e59c8e839560 | 312 | /** |
| AnnaBridge | 163:e59c8e839560 | 313 | * @brief Check if AHB1 peripheral clock is enabled or not |
| AnnaBridge | 163:e59c8e839560 | 314 | * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 315 | * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 316 | * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 317 | * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 318 | * AHBENR FMCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 319 | * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 320 | * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 321 | * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 322 | * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 323 | * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 324 | * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 325 | * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 326 | * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 327 | * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 328 | * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 329 | * AHBENR ADC1EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 330 | * AHBENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 331 | * AHBENR ADC34EN LL_AHB1_GRP1_IsEnabledClock |
| AnnaBridge | 163:e59c8e839560 | 332 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 333 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 163:e59c8e839560 | 334 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 163:e59c8e839560 | 335 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| AnnaBridge | 163:e59c8e839560 | 336 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 163:e59c8e839560 | 337 | * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 163:e59c8e839560 | 338 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 163:e59c8e839560 | 339 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 163:e59c8e839560 | 340 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 163:e59c8e839560 | 341 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 163:e59c8e839560 | 342 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 163:e59c8e839560 | 343 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 163:e59c8e839560 | 344 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 163:e59c8e839560 | 345 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 163:e59c8e839560 | 346 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 163:e59c8e839560 | 347 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 163:e59c8e839560 | 348 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 349 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) |
| AnnaBridge | 163:e59c8e839560 | 350 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) |
| AnnaBridge | 163:e59c8e839560 | 351 | * |
| AnnaBridge | 163:e59c8e839560 | 352 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 353 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 163:e59c8e839560 | 354 | */ |
| AnnaBridge | 163:e59c8e839560 | 355 | __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 356 | { |
| AnnaBridge | 163:e59c8e839560 | 357 | return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); |
| AnnaBridge | 163:e59c8e839560 | 358 | } |
| AnnaBridge | 163:e59c8e839560 | 359 | |
| AnnaBridge | 163:e59c8e839560 | 360 | /** |
| AnnaBridge | 163:e59c8e839560 | 361 | * @brief Disable AHB1 peripherals clock. |
| AnnaBridge | 163:e59c8e839560 | 362 | * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 363 | * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 364 | * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 365 | * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 366 | * AHBENR FMCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 367 | * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 368 | * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 369 | * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 370 | * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 371 | * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 372 | * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 373 | * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 374 | * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 375 | * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 376 | * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 377 | * AHBENR ADC1EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 378 | * AHBENR ADC12EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 379 | * AHBENR ADC34EN LL_AHB1_GRP1_DisableClock |
| AnnaBridge | 163:e59c8e839560 | 380 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 381 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 163:e59c8e839560 | 382 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 163:e59c8e839560 | 383 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| AnnaBridge | 163:e59c8e839560 | 384 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 163:e59c8e839560 | 385 | * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 163:e59c8e839560 | 386 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 163:e59c8e839560 | 387 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 163:e59c8e839560 | 388 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 163:e59c8e839560 | 389 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 163:e59c8e839560 | 390 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 163:e59c8e839560 | 391 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 163:e59c8e839560 | 392 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 163:e59c8e839560 | 393 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 163:e59c8e839560 | 394 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 163:e59c8e839560 | 395 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 163:e59c8e839560 | 396 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 397 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) |
| AnnaBridge | 163:e59c8e839560 | 398 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) |
| AnnaBridge | 163:e59c8e839560 | 399 | * |
| AnnaBridge | 163:e59c8e839560 | 400 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 401 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 402 | */ |
| AnnaBridge | 163:e59c8e839560 | 403 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 404 | { |
| AnnaBridge | 163:e59c8e839560 | 405 | CLEAR_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 406 | } |
| AnnaBridge | 163:e59c8e839560 | 407 | |
| AnnaBridge | 163:e59c8e839560 | 408 | /** |
| AnnaBridge | 163:e59c8e839560 | 409 | * @brief Force AHB1 peripherals reset. |
| AnnaBridge | 163:e59c8e839560 | 410 | * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 411 | * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 412 | * AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 413 | * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 414 | * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 415 | * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 416 | * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 417 | * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 418 | * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 419 | * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 420 | * AHBRSTR ADC1RST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 421 | * AHBRSTR ADC12RST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 422 | * AHBRSTR ADC34RST LL_AHB1_GRP1_ForceReset |
| AnnaBridge | 163:e59c8e839560 | 423 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 424 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 163:e59c8e839560 | 425 | * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 163:e59c8e839560 | 426 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 163:e59c8e839560 | 427 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 163:e59c8e839560 | 428 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 163:e59c8e839560 | 429 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 163:e59c8e839560 | 430 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 163:e59c8e839560 | 431 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 163:e59c8e839560 | 432 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 163:e59c8e839560 | 433 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 163:e59c8e839560 | 434 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 163:e59c8e839560 | 435 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 436 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) |
| AnnaBridge | 163:e59c8e839560 | 437 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) |
| AnnaBridge | 163:e59c8e839560 | 438 | * |
| AnnaBridge | 163:e59c8e839560 | 439 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 440 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 441 | */ |
| AnnaBridge | 163:e59c8e839560 | 442 | __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 443 | { |
| AnnaBridge | 163:e59c8e839560 | 444 | SET_BIT(RCC->AHBRSTR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 445 | } |
| AnnaBridge | 163:e59c8e839560 | 446 | |
| AnnaBridge | 163:e59c8e839560 | 447 | /** |
| AnnaBridge | 163:e59c8e839560 | 448 | * @brief Release AHB1 peripherals reset. |
| AnnaBridge | 163:e59c8e839560 | 449 | * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 450 | * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 451 | * AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 452 | * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 453 | * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 454 | * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 455 | * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 456 | * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 457 | * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 458 | * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 459 | * AHBRSTR ADC1RST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 460 | * AHBRSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 461 | * AHBRSTR ADC34RST LL_AHB1_GRP1_ReleaseReset |
| AnnaBridge | 163:e59c8e839560 | 462 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 463 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 163:e59c8e839560 | 464 | * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 163:e59c8e839560 | 465 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 163:e59c8e839560 | 466 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 163:e59c8e839560 | 467 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 163:e59c8e839560 | 468 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 163:e59c8e839560 | 469 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 163:e59c8e839560 | 470 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 163:e59c8e839560 | 471 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 163:e59c8e839560 | 472 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 163:e59c8e839560 | 473 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 163:e59c8e839560 | 474 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 475 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) |
| AnnaBridge | 163:e59c8e839560 | 476 | * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) |
| AnnaBridge | 163:e59c8e839560 | 477 | * |
| AnnaBridge | 163:e59c8e839560 | 478 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 479 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 480 | */ |
| AnnaBridge | 163:e59c8e839560 | 481 | __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 482 | { |
| AnnaBridge | 163:e59c8e839560 | 483 | CLEAR_BIT(RCC->AHBRSTR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 484 | } |
| AnnaBridge | 163:e59c8e839560 | 485 | |
| AnnaBridge | 163:e59c8e839560 | 486 | /** |
| AnnaBridge | 163:e59c8e839560 | 487 | * @} |
| AnnaBridge | 163:e59c8e839560 | 488 | */ |
| AnnaBridge | 163:e59c8e839560 | 489 | |
| AnnaBridge | 163:e59c8e839560 | 490 | /** @defgroup BUS_LL_EF_APB1 APB1 |
| AnnaBridge | 163:e59c8e839560 | 491 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 492 | */ |
| AnnaBridge | 163:e59c8e839560 | 493 | |
| AnnaBridge | 163:e59c8e839560 | 494 | /** |
| AnnaBridge | 163:e59c8e839560 | 495 | * @brief Enable APB1 peripherals clock. |
| AnnaBridge | 163:e59c8e839560 | 496 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 497 | * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 498 | * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 499 | * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 500 | * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 501 | * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 502 | * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 503 | * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 504 | * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 505 | * APB1ENR TIM18EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 506 | * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 507 | * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 508 | * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 509 | * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 510 | * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 511 | * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 512 | * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 513 | * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 514 | * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 515 | * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 516 | * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 517 | * APB1ENR DAC2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 518 | * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 519 | * APB1ENR DAC1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 520 | * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 521 | * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock |
| AnnaBridge | 163:e59c8e839560 | 522 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 523 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 163:e59c8e839560 | 524 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 163:e59c8e839560 | 525 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 163:e59c8e839560 | 526 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 163:e59c8e839560 | 527 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 163:e59c8e839560 | 528 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 163:e59c8e839560 | 529 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| AnnaBridge | 163:e59c8e839560 | 530 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| AnnaBridge | 163:e59c8e839560 | 531 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| AnnaBridge | 163:e59c8e839560 | 532 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) |
| AnnaBridge | 163:e59c8e839560 | 533 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 163:e59c8e839560 | 534 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 163:e59c8e839560 | 535 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 163:e59c8e839560 | 536 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 163:e59c8e839560 | 537 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 163:e59c8e839560 | 538 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 163:e59c8e839560 | 539 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 163:e59c8e839560 | 540 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 163:e59c8e839560 | 541 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 163:e59c8e839560 | 542 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 163:e59c8e839560 | 543 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
| AnnaBridge | 163:e59c8e839560 | 544 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) |
| AnnaBridge | 163:e59c8e839560 | 545 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 163:e59c8e839560 | 546 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 163:e59c8e839560 | 547 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 163:e59c8e839560 | 548 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 163:e59c8e839560 | 549 | * |
| AnnaBridge | 163:e59c8e839560 | 550 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 551 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 552 | */ |
| AnnaBridge | 163:e59c8e839560 | 553 | __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 554 | { |
| AnnaBridge | 163:e59c8e839560 | 555 | __IO uint32_t tmpreg; |
| AnnaBridge | 163:e59c8e839560 | 556 | SET_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 557 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 163:e59c8e839560 | 558 | tmpreg = READ_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 559 | (void)tmpreg; |
| AnnaBridge | 163:e59c8e839560 | 560 | } |
| AnnaBridge | 163:e59c8e839560 | 561 | |
| AnnaBridge | 163:e59c8e839560 | 562 | /** |
| AnnaBridge | 163:e59c8e839560 | 563 | * @brief Check if APB1 peripheral clock is enabled or not |
| AnnaBridge | 163:e59c8e839560 | 564 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 565 | * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 566 | * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 567 | * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 568 | * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 569 | * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 570 | * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 571 | * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 572 | * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 573 | * APB1ENR TIM18EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 574 | * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 575 | * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 576 | * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 577 | * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 578 | * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 579 | * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 580 | * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 581 | * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 582 | * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 583 | * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 584 | * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 585 | * APB1ENR DAC2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 586 | * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 587 | * APB1ENR DAC1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 588 | * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 589 | * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock |
| AnnaBridge | 163:e59c8e839560 | 590 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 591 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 163:e59c8e839560 | 592 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 163:e59c8e839560 | 593 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 163:e59c8e839560 | 594 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 163:e59c8e839560 | 595 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 163:e59c8e839560 | 596 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 163:e59c8e839560 | 597 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| AnnaBridge | 163:e59c8e839560 | 598 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| AnnaBridge | 163:e59c8e839560 | 599 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| AnnaBridge | 163:e59c8e839560 | 600 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) |
| AnnaBridge | 163:e59c8e839560 | 601 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 163:e59c8e839560 | 602 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 163:e59c8e839560 | 603 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 163:e59c8e839560 | 604 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 163:e59c8e839560 | 605 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 163:e59c8e839560 | 606 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 163:e59c8e839560 | 607 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 163:e59c8e839560 | 608 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 163:e59c8e839560 | 609 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 163:e59c8e839560 | 610 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 163:e59c8e839560 | 611 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
| AnnaBridge | 163:e59c8e839560 | 612 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) |
| AnnaBridge | 163:e59c8e839560 | 613 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 163:e59c8e839560 | 614 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 163:e59c8e839560 | 615 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 163:e59c8e839560 | 616 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 163:e59c8e839560 | 617 | * |
| AnnaBridge | 163:e59c8e839560 | 618 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 619 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 163:e59c8e839560 | 620 | */ |
| AnnaBridge | 163:e59c8e839560 | 621 | __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 622 | { |
| AnnaBridge | 163:e59c8e839560 | 623 | return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); |
| AnnaBridge | 163:e59c8e839560 | 624 | } |
| AnnaBridge | 163:e59c8e839560 | 625 | |
| AnnaBridge | 163:e59c8e839560 | 626 | /** |
| AnnaBridge | 163:e59c8e839560 | 627 | * @brief Disable APB1 peripherals clock. |
| AnnaBridge | 163:e59c8e839560 | 628 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 629 | * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 630 | * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 631 | * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 632 | * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 633 | * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 634 | * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 635 | * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 636 | * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 637 | * APB1ENR TIM18EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 638 | * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 639 | * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 640 | * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 641 | * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 642 | * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 643 | * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 644 | * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 645 | * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 646 | * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 647 | * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 648 | * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 649 | * APB1ENR DAC2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 650 | * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 651 | * APB1ENR DAC1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 652 | * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 653 | * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock |
| AnnaBridge | 163:e59c8e839560 | 654 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 655 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 163:e59c8e839560 | 656 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 163:e59c8e839560 | 657 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 163:e59c8e839560 | 658 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 163:e59c8e839560 | 659 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 163:e59c8e839560 | 660 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 163:e59c8e839560 | 661 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| AnnaBridge | 163:e59c8e839560 | 662 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| AnnaBridge | 163:e59c8e839560 | 663 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| AnnaBridge | 163:e59c8e839560 | 664 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) |
| AnnaBridge | 163:e59c8e839560 | 665 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 163:e59c8e839560 | 666 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 163:e59c8e839560 | 667 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 163:e59c8e839560 | 668 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 163:e59c8e839560 | 669 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 163:e59c8e839560 | 670 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 163:e59c8e839560 | 671 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 163:e59c8e839560 | 672 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 163:e59c8e839560 | 673 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 163:e59c8e839560 | 674 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 163:e59c8e839560 | 675 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
| AnnaBridge | 163:e59c8e839560 | 676 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) |
| AnnaBridge | 163:e59c8e839560 | 677 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 163:e59c8e839560 | 678 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 163:e59c8e839560 | 679 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 163:e59c8e839560 | 680 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 163:e59c8e839560 | 681 | * |
| AnnaBridge | 163:e59c8e839560 | 682 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 683 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 684 | */ |
| AnnaBridge | 163:e59c8e839560 | 685 | __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 686 | { |
| AnnaBridge | 163:e59c8e839560 | 687 | CLEAR_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 688 | } |
| AnnaBridge | 163:e59c8e839560 | 689 | |
| AnnaBridge | 163:e59c8e839560 | 690 | /** |
| AnnaBridge | 163:e59c8e839560 | 691 | * @brief Force APB1 peripherals reset. |
| AnnaBridge | 163:e59c8e839560 | 692 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 693 | * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 694 | * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 695 | * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 696 | * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 697 | * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 698 | * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 699 | * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 700 | * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 701 | * APB1RSTR TIM18RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 702 | * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 703 | * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 704 | * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 705 | * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 706 | * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 707 | * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 708 | * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 709 | * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 710 | * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 711 | * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 712 | * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 713 | * APB1RSTR DAC2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 714 | * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 715 | * APB1RSTR DAC1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 716 | * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 717 | * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset |
| AnnaBridge | 163:e59c8e839560 | 718 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 719 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 163:e59c8e839560 | 720 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 163:e59c8e839560 | 721 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 163:e59c8e839560 | 722 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 163:e59c8e839560 | 723 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 163:e59c8e839560 | 724 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 163:e59c8e839560 | 725 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 163:e59c8e839560 | 726 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| AnnaBridge | 163:e59c8e839560 | 727 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| AnnaBridge | 163:e59c8e839560 | 728 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| AnnaBridge | 163:e59c8e839560 | 729 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) |
| AnnaBridge | 163:e59c8e839560 | 730 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 163:e59c8e839560 | 731 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 163:e59c8e839560 | 732 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 163:e59c8e839560 | 733 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 163:e59c8e839560 | 734 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 163:e59c8e839560 | 735 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 163:e59c8e839560 | 736 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 163:e59c8e839560 | 737 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 163:e59c8e839560 | 738 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 163:e59c8e839560 | 739 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 163:e59c8e839560 | 740 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
| AnnaBridge | 163:e59c8e839560 | 741 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) |
| AnnaBridge | 163:e59c8e839560 | 742 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 163:e59c8e839560 | 743 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 163:e59c8e839560 | 744 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 163:e59c8e839560 | 745 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 163:e59c8e839560 | 746 | * |
| AnnaBridge | 163:e59c8e839560 | 747 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 748 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 749 | */ |
| AnnaBridge | 163:e59c8e839560 | 750 | __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 751 | { |
| AnnaBridge | 163:e59c8e839560 | 752 | SET_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 753 | } |
| AnnaBridge | 163:e59c8e839560 | 754 | |
| AnnaBridge | 163:e59c8e839560 | 755 | /** |
| AnnaBridge | 163:e59c8e839560 | 756 | * @brief Release APB1 peripherals reset. |
| AnnaBridge | 163:e59c8e839560 | 757 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 758 | * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 759 | * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 760 | * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 761 | * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 762 | * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 763 | * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 764 | * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 765 | * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 766 | * APB1RSTR TIM18RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 767 | * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 768 | * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 769 | * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 770 | * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 771 | * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 772 | * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 773 | * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 774 | * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 775 | * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 776 | * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 777 | * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 778 | * APB1RSTR DAC2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 779 | * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 780 | * APB1RSTR DAC1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 781 | * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 782 | * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset |
| AnnaBridge | 163:e59c8e839560 | 783 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 784 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 163:e59c8e839560 | 785 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 163:e59c8e839560 | 786 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 163:e59c8e839560 | 787 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 163:e59c8e839560 | 788 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 163:e59c8e839560 | 789 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 163:e59c8e839560 | 790 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 163:e59c8e839560 | 791 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| AnnaBridge | 163:e59c8e839560 | 792 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| AnnaBridge | 163:e59c8e839560 | 793 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| AnnaBridge | 163:e59c8e839560 | 794 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) |
| AnnaBridge | 163:e59c8e839560 | 795 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 163:e59c8e839560 | 796 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 163:e59c8e839560 | 797 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 163:e59c8e839560 | 798 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 163:e59c8e839560 | 799 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 163:e59c8e839560 | 800 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 163:e59c8e839560 | 801 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 163:e59c8e839560 | 802 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 163:e59c8e839560 | 803 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 163:e59c8e839560 | 804 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 163:e59c8e839560 | 805 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
| AnnaBridge | 163:e59c8e839560 | 806 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) |
| AnnaBridge | 163:e59c8e839560 | 807 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 163:e59c8e839560 | 808 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 163:e59c8e839560 | 809 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 163:e59c8e839560 | 810 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 163:e59c8e839560 | 811 | * |
| AnnaBridge | 163:e59c8e839560 | 812 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 813 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 814 | */ |
| AnnaBridge | 163:e59c8e839560 | 815 | __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 816 | { |
| AnnaBridge | 163:e59c8e839560 | 817 | CLEAR_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 818 | } |
| AnnaBridge | 163:e59c8e839560 | 819 | |
| AnnaBridge | 163:e59c8e839560 | 820 | /** |
| AnnaBridge | 163:e59c8e839560 | 821 | * @} |
| AnnaBridge | 163:e59c8e839560 | 822 | */ |
| AnnaBridge | 163:e59c8e839560 | 823 | |
| AnnaBridge | 163:e59c8e839560 | 824 | /** @defgroup BUS_LL_EF_APB2 APB2 |
| AnnaBridge | 163:e59c8e839560 | 825 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 826 | */ |
| AnnaBridge | 163:e59c8e839560 | 827 | |
| AnnaBridge | 163:e59c8e839560 | 828 | /** |
| AnnaBridge | 163:e59c8e839560 | 829 | * @brief Enable APB2 peripherals clock. |
| AnnaBridge | 163:e59c8e839560 | 830 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 831 | * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 832 | * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 833 | * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 834 | * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 835 | * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 836 | * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 837 | * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 838 | * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 839 | * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 840 | * APB2ENR TIM19EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 841 | * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 842 | * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 843 | * APB2ENR SDADC1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 844 | * APB2ENR SDADC2EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 163:e59c8e839560 | 845 | * APB2ENR SDADC3EN LL_APB2_GRP1_EnableClock |
| AnnaBridge | 163:e59c8e839560 | 846 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 847 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 163:e59c8e839560 | 848 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 849 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) |
| AnnaBridge | 163:e59c8e839560 | 850 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) |
| AnnaBridge | 163:e59c8e839560 | 851 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 163:e59c8e839560 | 852 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 163:e59c8e839560 | 853 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| AnnaBridge | 163:e59c8e839560 | 854 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 163:e59c8e839560 | 855 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 163:e59c8e839560 | 856 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 |
| AnnaBridge | 163:e59c8e839560 | 857 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) |
| AnnaBridge | 163:e59c8e839560 | 858 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) |
| AnnaBridge | 163:e59c8e839560 | 859 | * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) |
| AnnaBridge | 163:e59c8e839560 | 860 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 861 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) |
| AnnaBridge | 163:e59c8e839560 | 862 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) |
| AnnaBridge | 163:e59c8e839560 | 863 | * |
| AnnaBridge | 163:e59c8e839560 | 864 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 865 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 866 | */ |
| AnnaBridge | 163:e59c8e839560 | 867 | __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 868 | { |
| AnnaBridge | 163:e59c8e839560 | 869 | __IO uint32_t tmpreg; |
| AnnaBridge | 163:e59c8e839560 | 870 | SET_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 871 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 163:e59c8e839560 | 872 | tmpreg = READ_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 873 | (void)tmpreg; |
| AnnaBridge | 163:e59c8e839560 | 874 | } |
| AnnaBridge | 163:e59c8e839560 | 875 | |
| AnnaBridge | 163:e59c8e839560 | 876 | /** |
| AnnaBridge | 163:e59c8e839560 | 877 | * @brief Check if APB2 peripheral clock is enabled or not |
| AnnaBridge | 163:e59c8e839560 | 878 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 879 | * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 880 | * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 881 | * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 882 | * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 883 | * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 884 | * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 885 | * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 886 | * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 887 | * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 888 | * APB2ENR TIM19EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 889 | * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 890 | * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 891 | * APB2ENR SDADC1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 892 | * APB2ENR SDADC2EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 163:e59c8e839560 | 893 | * APB2ENR SDADC3EN LL_APB2_GRP1_IsEnabledClock |
| AnnaBridge | 163:e59c8e839560 | 894 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 895 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 163:e59c8e839560 | 896 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 897 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) |
| AnnaBridge | 163:e59c8e839560 | 898 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) |
| AnnaBridge | 163:e59c8e839560 | 899 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 163:e59c8e839560 | 900 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 163:e59c8e839560 | 901 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| AnnaBridge | 163:e59c8e839560 | 902 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 163:e59c8e839560 | 903 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 163:e59c8e839560 | 904 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 |
| AnnaBridge | 163:e59c8e839560 | 905 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) |
| AnnaBridge | 163:e59c8e839560 | 906 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) |
| AnnaBridge | 163:e59c8e839560 | 907 | * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) |
| AnnaBridge | 163:e59c8e839560 | 908 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 909 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) |
| AnnaBridge | 163:e59c8e839560 | 910 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) |
| AnnaBridge | 163:e59c8e839560 | 911 | * |
| AnnaBridge | 163:e59c8e839560 | 912 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 913 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 163:e59c8e839560 | 914 | */ |
| AnnaBridge | 163:e59c8e839560 | 915 | __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 916 | { |
| AnnaBridge | 163:e59c8e839560 | 917 | return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); |
| AnnaBridge | 163:e59c8e839560 | 918 | } |
| AnnaBridge | 163:e59c8e839560 | 919 | |
| AnnaBridge | 163:e59c8e839560 | 920 | /** |
| AnnaBridge | 163:e59c8e839560 | 921 | * @brief Disable APB2 peripherals clock. |
| AnnaBridge | 163:e59c8e839560 | 922 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 923 | * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 924 | * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 925 | * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 926 | * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 927 | * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 928 | * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 929 | * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 930 | * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 931 | * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 932 | * APB2ENR TIM19EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 933 | * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 934 | * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 935 | * APB2ENR SDADC1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 936 | * APB2ENR SDADC2EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 163:e59c8e839560 | 937 | * APB2ENR SDADC3EN LL_APB2_GRP1_DisableClock |
| AnnaBridge | 163:e59c8e839560 | 938 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 939 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 163:e59c8e839560 | 940 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 941 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) |
| AnnaBridge | 163:e59c8e839560 | 942 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) |
| AnnaBridge | 163:e59c8e839560 | 943 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 163:e59c8e839560 | 944 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 163:e59c8e839560 | 945 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| AnnaBridge | 163:e59c8e839560 | 946 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 163:e59c8e839560 | 947 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 163:e59c8e839560 | 948 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 |
| AnnaBridge | 163:e59c8e839560 | 949 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) |
| AnnaBridge | 163:e59c8e839560 | 950 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) |
| AnnaBridge | 163:e59c8e839560 | 951 | * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) |
| AnnaBridge | 163:e59c8e839560 | 952 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 953 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) |
| AnnaBridge | 163:e59c8e839560 | 954 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) |
| AnnaBridge | 163:e59c8e839560 | 955 | * |
| AnnaBridge | 163:e59c8e839560 | 956 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 957 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 958 | */ |
| AnnaBridge | 163:e59c8e839560 | 959 | __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 960 | { |
| AnnaBridge | 163:e59c8e839560 | 961 | CLEAR_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 962 | } |
| AnnaBridge | 163:e59c8e839560 | 963 | |
| AnnaBridge | 163:e59c8e839560 | 964 | /** |
| AnnaBridge | 163:e59c8e839560 | 965 | * @brief Force APB2 peripherals reset. |
| AnnaBridge | 163:e59c8e839560 | 966 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 967 | * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 968 | * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 969 | * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 970 | * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 971 | * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 972 | * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 973 | * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 974 | * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 975 | * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 976 | * APB2RSTR TIM19RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 977 | * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 978 | * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 979 | * APB2RSTR SDADC1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 980 | * APB2RSTR SDADC2RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 163:e59c8e839560 | 981 | * APB2RSTR SDADC3RST LL_APB2_GRP1_ForceReset |
| AnnaBridge | 163:e59c8e839560 | 982 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 983 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 163:e59c8e839560 | 984 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 163:e59c8e839560 | 985 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 986 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) |
| AnnaBridge | 163:e59c8e839560 | 987 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) |
| AnnaBridge | 163:e59c8e839560 | 988 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 163:e59c8e839560 | 989 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 163:e59c8e839560 | 990 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| AnnaBridge | 163:e59c8e839560 | 991 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 163:e59c8e839560 | 992 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 163:e59c8e839560 | 993 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 |
| AnnaBridge | 163:e59c8e839560 | 994 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) |
| AnnaBridge | 163:e59c8e839560 | 995 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) |
| AnnaBridge | 163:e59c8e839560 | 996 | * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) |
| AnnaBridge | 163:e59c8e839560 | 997 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 998 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) |
| AnnaBridge | 163:e59c8e839560 | 999 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) |
| AnnaBridge | 163:e59c8e839560 | 1000 | * |
| AnnaBridge | 163:e59c8e839560 | 1001 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 1002 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 1003 | */ |
| AnnaBridge | 163:e59c8e839560 | 1004 | __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 1005 | { |
| AnnaBridge | 163:e59c8e839560 | 1006 | SET_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 1007 | } |
| AnnaBridge | 163:e59c8e839560 | 1008 | |
| AnnaBridge | 163:e59c8e839560 | 1009 | /** |
| AnnaBridge | 163:e59c8e839560 | 1010 | * @brief Release APB2 peripherals reset. |
| AnnaBridge | 163:e59c8e839560 | 1011 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1012 | * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1013 | * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1014 | * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1015 | * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1016 | * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1017 | * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1018 | * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1019 | * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1020 | * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1021 | * APB2RSTR TIM19RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1022 | * APB2RSTR TIM20RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1023 | * APB2RSTR HRTIM1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1024 | * APB2RSTR SDADC1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1025 | * APB2RSTR SDADC2RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 163:e59c8e839560 | 1026 | * APB2RSTR SDADC3RST LL_APB2_GRP1_ReleaseReset |
| AnnaBridge | 163:e59c8e839560 | 1027 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 1028 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 163:e59c8e839560 | 1029 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 163:e59c8e839560 | 1030 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 1031 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) |
| AnnaBridge | 163:e59c8e839560 | 1032 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) |
| AnnaBridge | 163:e59c8e839560 | 1033 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 163:e59c8e839560 | 1034 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 163:e59c8e839560 | 1035 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| AnnaBridge | 163:e59c8e839560 | 1036 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 163:e59c8e839560 | 1037 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 163:e59c8e839560 | 1038 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 |
| AnnaBridge | 163:e59c8e839560 | 1039 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) |
| AnnaBridge | 163:e59c8e839560 | 1040 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) |
| AnnaBridge | 163:e59c8e839560 | 1041 | * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) |
| AnnaBridge | 163:e59c8e839560 | 1042 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) |
| AnnaBridge | 163:e59c8e839560 | 1043 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) |
| AnnaBridge | 163:e59c8e839560 | 1044 | * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) |
| AnnaBridge | 163:e59c8e839560 | 1045 | * |
| AnnaBridge | 163:e59c8e839560 | 1046 | * (*) value not defined in all devices. |
| AnnaBridge | 163:e59c8e839560 | 1047 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 1048 | */ |
| AnnaBridge | 163:e59c8e839560 | 1049 | __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 163:e59c8e839560 | 1050 | { |
| AnnaBridge | 163:e59c8e839560 | 1051 | CLEAR_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 163:e59c8e839560 | 1052 | } |
| AnnaBridge | 163:e59c8e839560 | 1053 | |
| AnnaBridge | 163:e59c8e839560 | 1054 | /** |
| AnnaBridge | 163:e59c8e839560 | 1055 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1056 | */ |
| AnnaBridge | 163:e59c8e839560 | 1057 | |
| AnnaBridge | 163:e59c8e839560 | 1058 | |
| AnnaBridge | 163:e59c8e839560 | 1059 | /** |
| AnnaBridge | 163:e59c8e839560 | 1060 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1061 | */ |
| AnnaBridge | 163:e59c8e839560 | 1062 | |
| AnnaBridge | 163:e59c8e839560 | 1063 | /** |
| AnnaBridge | 163:e59c8e839560 | 1064 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1065 | */ |
| AnnaBridge | 163:e59c8e839560 | 1066 | |
| AnnaBridge | 163:e59c8e839560 | 1067 | #endif /* defined(RCC) */ |
| AnnaBridge | 163:e59c8e839560 | 1068 | |
| AnnaBridge | 163:e59c8e839560 | 1069 | /** |
| AnnaBridge | 163:e59c8e839560 | 1070 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1071 | */ |
| AnnaBridge | 163:e59c8e839560 | 1072 | |
| AnnaBridge | 163:e59c8e839560 | 1073 | #ifdef __cplusplus |
| AnnaBridge | 163:e59c8e839560 | 1074 | } |
| AnnaBridge | 163:e59c8e839560 | 1075 | #endif |
| AnnaBridge | 163:e59c8e839560 | 1076 | |
| AnnaBridge | 163:e59c8e839560 | 1077 | #endif /* __STM32F3xx_LL_BUS_H */ |
| AnnaBridge | 163:e59c8e839560 | 1078 | |
| AnnaBridge | 163:e59c8e839560 | 1079 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
