mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_rcc_ex.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc_ex.h@168:b9e159c1930a

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	163:e59c8e839560	1	/**
AnnaBridge	163:e59c8e839560	2	******************************************************************************
AnnaBridge	163:e59c8e839560	3	* @file stm32f3xx_hal_rcc_ex.h
AnnaBridge	163:e59c8e839560	4	* @author MCD Application Team
AnnaBridge	163:e59c8e839560	5	* @brief Header file of RCC HAL Extension module.
AnnaBridge	163:e59c8e839560	6	******************************************************************************
AnnaBridge	163:e59c8e839560	7	* @attention
AnnaBridge	163:e59c8e839560	8	*
AnnaBridge	163:e59c8e839560	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	163:e59c8e839560	10	*
AnnaBridge	163:e59c8e839560	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	163:e59c8e839560	12	* are permitted provided that the following conditions are met:
AnnaBridge	163:e59c8e839560	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	163:e59c8e839560	14	* this list of conditions and the following disclaimer.
AnnaBridge	163:e59c8e839560	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	163:e59c8e839560	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	163:e59c8e839560	17	* and/or other materials provided with the distribution.
AnnaBridge	163:e59c8e839560	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	163:e59c8e839560	19	* may be used to endorse or promote products derived from this software
AnnaBridge	163:e59c8e839560	20	* without specific prior written permission.
AnnaBridge	163:e59c8e839560	21	*
AnnaBridge	163:e59c8e839560	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	163:e59c8e839560	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	163:e59c8e839560	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	163:e59c8e839560	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	163:e59c8e839560	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	163:e59c8e839560	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	163:e59c8e839560	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	163:e59c8e839560	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	163:e59c8e839560	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	163:e59c8e839560	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	163:e59c8e839560	32	*
AnnaBridge	163:e59c8e839560	33	******************************************************************************
AnnaBridge	163:e59c8e839560	34	*/
AnnaBridge	163:e59c8e839560	35
AnnaBridge	163:e59c8e839560	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	163:e59c8e839560	37	#ifndef __STM32F3xx_HAL_RCC_EX_H
AnnaBridge	163:e59c8e839560	38	#define __STM32F3xx_HAL_RCC_EX_H
AnnaBridge	163:e59c8e839560	39
AnnaBridge	163:e59c8e839560	40	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	41	extern "C" {
AnnaBridge	163:e59c8e839560	42	#endif
AnnaBridge	163:e59c8e839560	43
AnnaBridge	163:e59c8e839560	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	45	#include "stm32f3xx_hal_def.h"
AnnaBridge	163:e59c8e839560	46
AnnaBridge	163:e59c8e839560	47	/** @addtogroup STM32F3xx_HAL_Driver
AnnaBridge	163:e59c8e839560	48	* @{
AnnaBridge	163:e59c8e839560	49	*/
AnnaBridge	163:e59c8e839560	50
AnnaBridge	163:e59c8e839560	51	/** @addtogroup RCCEx
AnnaBridge	163:e59c8e839560	52	* @{
AnnaBridge	163:e59c8e839560	53	*/
AnnaBridge	163:e59c8e839560	54
AnnaBridge	163:e59c8e839560	55	/** @addtogroup RCCEx_Private_Macros
AnnaBridge	163:e59c8e839560	56	* @{
AnnaBridge	163:e59c8e839560	57	*/
AnnaBridge	163:e59c8e839560	58
AnnaBridge	163:e59c8e839560	59	#if defined(RCC_CFGR_PLLNODIV)
AnnaBridge	163:e59c8e839560	60	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
AnnaBridge	163:e59c8e839560	61	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| \
AnnaBridge	163:e59c8e839560	62	((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	63	((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	64	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	65	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| \
AnnaBridge	163:e59c8e839560	66	((SOURCE) == RCC_MCO1SOURCE_PLLCLK) \|\| \
AnnaBridge	163:e59c8e839560	67	((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
AnnaBridge	163:e59c8e839560	68	#else
AnnaBridge	163:e59c8e839560	69	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
AnnaBridge	163:e59c8e839560	70	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| \
AnnaBridge	163:e59c8e839560	71	((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	72	((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	73	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	74	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| \
AnnaBridge	163:e59c8e839560	75	((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
AnnaBridge	163:e59c8e839560	76	#endif /* RCC_CFGR_PLLNODIV */
AnnaBridge	163:e59c8e839560	77
AnnaBridge	163:e59c8e839560	78	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	79	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| \
AnnaBridge	163:e59c8e839560	80	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
AnnaBridge	163:e59c8e839560	81	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
AnnaBridge	163:e59c8e839560	82	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
AnnaBridge	163:e59c8e839560	83	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
AnnaBridge	163:e59c8e839560	84	RCC_PERIPHCLK_TIM17 \| RCC_PERIPHCLK_RTC))
AnnaBridge	163:e59c8e839560	85	#endif /* STM32F301x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	86	#if defined(STM32F302x8)
AnnaBridge	163:e59c8e839560	87	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| \
AnnaBridge	163:e59c8e839560	88	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
AnnaBridge	163:e59c8e839560	89	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
AnnaBridge	163:e59c8e839560	90	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
AnnaBridge	163:e59c8e839560	91	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB \| \
AnnaBridge	163:e59c8e839560	92	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
AnnaBridge	163:e59c8e839560	93	RCC_PERIPHCLK_TIM17))
AnnaBridge	163:e59c8e839560	94	#endif /* STM32F302x8 */
AnnaBridge	163:e59c8e839560	95	#if defined(STM32F302xC)
AnnaBridge	163:e59c8e839560	96	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
AnnaBridge	163:e59c8e839560	97	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
AnnaBridge	163:e59c8e839560	98	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
AnnaBridge	163:e59c8e839560	99	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_I2S \| \
AnnaBridge	163:e59c8e839560	100	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	163:e59c8e839560	101	RCC_PERIPHCLK_USB))
AnnaBridge	163:e59c8e839560	102	#endif /* STM32F302xC */
AnnaBridge	163:e59c8e839560	103	#if defined(STM32F303xC)
AnnaBridge	163:e59c8e839560	104	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
AnnaBridge	163:e59c8e839560	105	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
AnnaBridge	163:e59c8e839560	106	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
AnnaBridge	163:e59c8e839560	107	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
AnnaBridge	163:e59c8e839560	108	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
AnnaBridge	163:e59c8e839560	109	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	163:e59c8e839560	110	RCC_PERIPHCLK_USB))
AnnaBridge	163:e59c8e839560	111	#endif /* STM32F303xC */
AnnaBridge	163:e59c8e839560	112	#if defined(STM32F302xE)
AnnaBridge	163:e59c8e839560	113	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
AnnaBridge	163:e59c8e839560	114	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
AnnaBridge	163:e59c8e839560	115	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
AnnaBridge	163:e59c8e839560	116	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_I2S \| \
AnnaBridge	163:e59c8e839560	117	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	163:e59c8e839560	118	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_I2C3 \| \
AnnaBridge	163:e59c8e839560	119	RCC_PERIPHCLK_TIM2 \| RCC_PERIPHCLK_TIM34 \| \
AnnaBridge	163:e59c8e839560	120	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
AnnaBridge	163:e59c8e839560	121	RCC_PERIPHCLK_TIM17))
AnnaBridge	163:e59c8e839560	122	#endif /* STM32F302xE */
AnnaBridge	163:e59c8e839560	123	#if defined(STM32F303xE)
AnnaBridge	163:e59c8e839560	124	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
AnnaBridge	163:e59c8e839560	125	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
AnnaBridge	163:e59c8e839560	126	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
AnnaBridge	163:e59c8e839560	127	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
AnnaBridge	163:e59c8e839560	128	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
AnnaBridge	163:e59c8e839560	129	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	163:e59c8e839560	130	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_I2C3 \| \
AnnaBridge	163:e59c8e839560	131	RCC_PERIPHCLK_TIM2 \| RCC_PERIPHCLK_TIM34 \| \
AnnaBridge	163:e59c8e839560	132	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
AnnaBridge	163:e59c8e839560	133	RCC_PERIPHCLK_TIM17 \| RCC_PERIPHCLK_TIM20))
AnnaBridge	163:e59c8e839560	134	#endif /* STM32F303xE */
AnnaBridge	163:e59c8e839560	135	#if defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	136	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
AnnaBridge	163:e59c8e839560	137	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
AnnaBridge	163:e59c8e839560	138	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
AnnaBridge	163:e59c8e839560	139	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
AnnaBridge	163:e59c8e839560	140	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
AnnaBridge	163:e59c8e839560	141	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	163:e59c8e839560	142	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM2 \| \
AnnaBridge	163:e59c8e839560	143	RCC_PERIPHCLK_TIM34 \| RCC_PERIPHCLK_TIM15 \| \
AnnaBridge	163:e59c8e839560	144	RCC_PERIPHCLK_TIM16 \| RCC_PERIPHCLK_TIM17 \| \
AnnaBridge	163:e59c8e839560	145	RCC_PERIPHCLK_TIM20))
AnnaBridge	163:e59c8e839560	146	#endif /* STM32F398xx */
AnnaBridge	163:e59c8e839560	147	#if defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	148	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
AnnaBridge	163:e59c8e839560	149	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
AnnaBridge	163:e59c8e839560	150	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
AnnaBridge	163:e59c8e839560	151	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
AnnaBridge	163:e59c8e839560	152	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
AnnaBridge	163:e59c8e839560	153	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC))
AnnaBridge	163:e59c8e839560	154	#endif /* STM32F358xx */
AnnaBridge	163:e59c8e839560	155	#if defined(STM32F303x8)
AnnaBridge	163:e59c8e839560	156	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| \
AnnaBridge	163:e59c8e839560	157	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
AnnaBridge	163:e59c8e839560	158	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
AnnaBridge	163:e59c8e839560	159	#endif /* STM32F303x8 */
AnnaBridge	163:e59c8e839560	160	#if defined(STM32F334x8)
AnnaBridge	163:e59c8e839560	161	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| \
AnnaBridge	163:e59c8e839560	162	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
AnnaBridge	163:e59c8e839560	163	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_HRTIM1 \| \
AnnaBridge	163:e59c8e839560	164	RCC_PERIPHCLK_RTC))
AnnaBridge	163:e59c8e839560	165	#endif /* STM32F334x8 */
AnnaBridge	163:e59c8e839560	166	#if defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	167	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| \
AnnaBridge	163:e59c8e839560	168	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
AnnaBridge	163:e59c8e839560	169	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
AnnaBridge	163:e59c8e839560	170	#endif /* STM32F328xx */
AnnaBridge	163:e59c8e839560	171	#if defined(STM32F373xC)
AnnaBridge	163:e59c8e839560	172	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
AnnaBridge	163:e59c8e839560	173	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
AnnaBridge	163:e59c8e839560	174	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
AnnaBridge	163:e59c8e839560	175	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	163:e59c8e839560	176	RCC_PERIPHCLK_USB))
AnnaBridge	163:e59c8e839560	177	#endif /* STM32F373xC */
AnnaBridge	163:e59c8e839560	178	#if defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	179	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
AnnaBridge	163:e59c8e839560	180	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
AnnaBridge	163:e59c8e839560	181	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
AnnaBridge	163:e59c8e839560	182	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
AnnaBridge	163:e59c8e839560	183	#endif /* STM32F378xx */
AnnaBridge	163:e59c8e839560	184
AnnaBridge	163:e59c8e839560	185	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	186	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
AnnaBridge	163:e59c8e839560	187	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	188	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	189	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	190	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	191	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	192	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	193	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	194	#define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) \|\| \
AnnaBridge	163:e59c8e839560	195	((ADCCLK) == RCC_ADC1PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) \|\| \
AnnaBridge	163:e59c8e839560	196	((ADCCLK) == RCC_ADC1PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) \|\| \
AnnaBridge	163:e59c8e839560	197	((ADCCLK) == RCC_ADC1PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) \|\| \
AnnaBridge	163:e59c8e839560	198	((ADCCLK) == RCC_ADC1PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) \|\| \
AnnaBridge	163:e59c8e839560	199	((ADCCLK) == RCC_ADC1PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) \|\| \
AnnaBridge	163:e59c8e839560	200	((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
AnnaBridge	163:e59c8e839560	201	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	202	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
AnnaBridge	163:e59c8e839560	203	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	204	((SOURCE) == RCC_TIM1CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	205	#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	206	((SOURCE) == RCC_TIM15CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	207	#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	208	((SOURCE) == RCC_TIM16CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	209	#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	210	((SOURCE) == RCC_TIM17CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	211	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	212	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	213	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
AnnaBridge	163:e59c8e839560	214	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	215	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	216	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	217	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	218	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	219	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
AnnaBridge	163:e59c8e839560	220	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
AnnaBridge	163:e59c8e839560	221	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
AnnaBridge	163:e59c8e839560	222	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
AnnaBridge	163:e59c8e839560	223	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
AnnaBridge	163:e59c8e839560	224	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
AnnaBridge	163:e59c8e839560	225	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
AnnaBridge	163:e59c8e839560	226	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	227	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
AnnaBridge	163:e59c8e839560	228	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	229	((SOURCE) == RCC_TIM1CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	230	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
AnnaBridge	163:e59c8e839560	231	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	232	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	233	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	234	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
AnnaBridge	163:e59c8e839560	235	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	236	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	237	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	238	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	239	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	240	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
AnnaBridge	163:e59c8e839560	241	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	242	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	243	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	244	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	245	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	246	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	247	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	248	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
AnnaBridge	163:e59c8e839560	249	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
AnnaBridge	163:e59c8e839560	250	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
AnnaBridge	163:e59c8e839560	251	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
AnnaBridge	163:e59c8e839560	252	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
AnnaBridge	163:e59c8e839560	253	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
AnnaBridge	163:e59c8e839560	254	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
AnnaBridge	163:e59c8e839560	255	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	256	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
AnnaBridge	163:e59c8e839560	257	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	258	((SOURCE) == RCC_TIM1CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	259	#define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	260	((SOURCE) == RCC_TIM2CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	261	#define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	262	((SOURCE) == RCC_TIM34CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	263	#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	264	((SOURCE) == RCC_TIM15CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	265	#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	266	((SOURCE) == RCC_TIM16CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	267	#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	268	((SOURCE) == RCC_TIM17CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	269	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
AnnaBridge	163:e59c8e839560	270	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	271	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	272	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	273	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
AnnaBridge	163:e59c8e839560	274	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	275	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	276	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	277	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	278	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	279	#define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	280	((SOURCE) == RCC_TIM20CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	281	#endif /* STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	282	#if defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	283	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	284	#define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) \|\| \
AnnaBridge	163:e59c8e839560	285	((ADCCLK) == RCC_ADC34PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) \|\| \
AnnaBridge	163:e59c8e839560	286	((ADCCLK) == RCC_ADC34PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) \|\| \
AnnaBridge	163:e59c8e839560	287	((ADCCLK) == RCC_ADC34PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) \|\| \
AnnaBridge	163:e59c8e839560	288	((ADCCLK) == RCC_ADC34PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) \|\| \
AnnaBridge	163:e59c8e839560	289	((ADCCLK) == RCC_ADC34PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) \|\| \
AnnaBridge	163:e59c8e839560	290	((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
AnnaBridge	163:e59c8e839560	291	#define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	292	((SOURCE) == RCC_TIM8CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	293	#endif /* STM32F303xC \|\| STM32F303xE \|\| STM32F398xx \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	294	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	295	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
AnnaBridge	163:e59c8e839560	296	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	297	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	298	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	299	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
AnnaBridge	163:e59c8e839560	300	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
AnnaBridge	163:e59c8e839560	301	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
AnnaBridge	163:e59c8e839560	302	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
AnnaBridge	163:e59c8e839560	303	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
AnnaBridge	163:e59c8e839560	304	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
AnnaBridge	163:e59c8e839560	305	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
AnnaBridge	163:e59c8e839560	306	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	307	((SOURCE) == RCC_TIM1CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	308	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	309	#if defined(STM32F334x8)
AnnaBridge	163:e59c8e839560	310	#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	311	((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
AnnaBridge	163:e59c8e839560	312	#endif /* STM32F334x8 */
AnnaBridge	163:e59c8e839560	313	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	314	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
AnnaBridge	163:e59c8e839560	315	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	316	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	317	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	318	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	319	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	320	#define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV4) \|\| \
AnnaBridge	163:e59c8e839560	321	((ADCCLK) == RCC_ADC1PCLK2_DIV6) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
AnnaBridge	163:e59c8e839560	322	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	323	((SOURCE) == RCC_CECCLKSOURCE_LSE))
AnnaBridge	163:e59c8e839560	324	#define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV2) \|\| \
AnnaBridge	163:e59c8e839560	325	((DIV) == RCC_SDADCSYSCLK_DIV4) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV6) \|\| \
AnnaBridge	163:e59c8e839560	326	((DIV) == RCC_SDADCSYSCLK_DIV8) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV10) \|\| \
AnnaBridge	163:e59c8e839560	327	((DIV) == RCC_SDADCSYSCLK_DIV12) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV14) \|\| \
AnnaBridge	163:e59c8e839560	328	((DIV) == RCC_SDADCSYSCLK_DIV16) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV20) \|\| \
AnnaBridge	163:e59c8e839560	329	((DIV) == RCC_SDADCSYSCLK_DIV24) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV28) \|\| \
AnnaBridge	163:e59c8e839560	330	((DIV) == RCC_SDADCSYSCLK_DIV32) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV36) \|\| \
AnnaBridge	163:e59c8e839560	331	((DIV) == RCC_SDADCSYSCLK_DIV40) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV44) \|\| \
AnnaBridge	163:e59c8e839560	332	((DIV) == RCC_SDADCSYSCLK_DIV48))
AnnaBridge	163:e59c8e839560	333	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	334	#if defined(STM32F302xE) \|\| defined(STM32F303xE)\
AnnaBridge	163:e59c8e839560	335	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC)\
AnnaBridge	163:e59c8e839560	336	\|\| defined(STM32F302x8) \
AnnaBridge	163:e59c8e839560	337	\|\| defined(STM32F373xC)
AnnaBridge	163:e59c8e839560	338	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) \|\| \
AnnaBridge	163:e59c8e839560	339	((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5))
AnnaBridge	163:e59c8e839560	340	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
AnnaBridge	163:e59c8e839560	341	/* STM32F302xC \|\| STM32F303xC \|\| */
AnnaBridge	163:e59c8e839560	342	/* STM32F302x8 \|\| */
AnnaBridge	163:e59c8e839560	343	/* STM32F373xC */
AnnaBridge	163:e59c8e839560	344	#if defined(RCC_CFGR_MCOPRE)
AnnaBridge	163:e59c8e839560	345	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
AnnaBridge	163:e59c8e839560	346	((DIV) == RCC_MCODIV_4) \|\| ((DIV) == RCC_MCODIV_8) \|\| \
AnnaBridge	163:e59c8e839560	347	((DIV) == RCC_MCODIV_16) \|\| ((DIV) == RCC_MCODIV_32) \|\| \
AnnaBridge	163:e59c8e839560	348	((DIV) == RCC_MCODIV_64) \|\| ((DIV) == RCC_MCODIV_128))
AnnaBridge	163:e59c8e839560	349	#else
AnnaBridge	163:e59c8e839560	350	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
AnnaBridge	163:e59c8e839560	351	#endif /* RCC_CFGR_MCOPRE */
AnnaBridge	163:e59c8e839560	352
AnnaBridge	163:e59c8e839560	353	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| \
AnnaBridge	163:e59c8e839560	354	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
AnnaBridge	163:e59c8e839560	355	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
AnnaBridge	163:e59c8e839560	356	((__DRIVE__) == RCC_LSEDRIVE_HIGH))
AnnaBridge	163:e59c8e839560	357
AnnaBridge	163:e59c8e839560	358	/**
AnnaBridge	163:e59c8e839560	359	* @}
AnnaBridge	163:e59c8e839560	360	*/
AnnaBridge	163:e59c8e839560	361
AnnaBridge	163:e59c8e839560	362	/* Exported types ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	363	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge	163:e59c8e839560	364	* @{
AnnaBridge	163:e59c8e839560	365	*/
AnnaBridge	163:e59c8e839560	366
AnnaBridge	163:e59c8e839560	367	/**
AnnaBridge	163:e59c8e839560	368	* @brief RCC extended clocks structure definition
AnnaBridge	163:e59c8e839560	369	*/
AnnaBridge	163:e59c8e839560	370	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	371	typedef struct
AnnaBridge	163:e59c8e839560	372	{
AnnaBridge	163:e59c8e839560	373	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	374	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	375
AnnaBridge	163:e59c8e839560	376	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	377	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	378
AnnaBridge	163:e59c8e839560	379	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	380	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	381
AnnaBridge	163:e59c8e839560	382	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	383	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	384
AnnaBridge	163:e59c8e839560	385	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge	163:e59c8e839560	386	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	163:e59c8e839560	387
AnnaBridge	163:e59c8e839560	388	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge	163:e59c8e839560	389	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge	163:e59c8e839560	390
AnnaBridge	163:e59c8e839560	391	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
AnnaBridge	163:e59c8e839560	392	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
AnnaBridge	163:e59c8e839560	393
AnnaBridge	163:e59c8e839560	394	uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge	163:e59c8e839560	395	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge	163:e59c8e839560	396
AnnaBridge	163:e59c8e839560	397	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge	163:e59c8e839560	398	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	399
AnnaBridge	163:e59c8e839560	400	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
AnnaBridge	163:e59c8e839560	401	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
AnnaBridge	163:e59c8e839560	402
AnnaBridge	163:e59c8e839560	403	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
AnnaBridge	163:e59c8e839560	404	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
AnnaBridge	163:e59c8e839560	405
AnnaBridge	163:e59c8e839560	406	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
AnnaBridge	163:e59c8e839560	407	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
AnnaBridge	163:e59c8e839560	408	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	409	#endif /* STM32F301x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	410
AnnaBridge	163:e59c8e839560	411	#if defined(STM32F302x8)
AnnaBridge	163:e59c8e839560	412	typedef struct
AnnaBridge	163:e59c8e839560	413	{
AnnaBridge	163:e59c8e839560	414	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	415	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	416
AnnaBridge	163:e59c8e839560	417	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	418	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	419
AnnaBridge	163:e59c8e839560	420	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	421	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	422
AnnaBridge	163:e59c8e839560	423	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	424	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	425
AnnaBridge	163:e59c8e839560	426	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge	163:e59c8e839560	427	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	163:e59c8e839560	428
AnnaBridge	163:e59c8e839560	429	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge	163:e59c8e839560	430	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge	163:e59c8e839560	431
AnnaBridge	163:e59c8e839560	432	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
AnnaBridge	163:e59c8e839560	433	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
AnnaBridge	163:e59c8e839560	434
AnnaBridge	163:e59c8e839560	435	uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge	163:e59c8e839560	436	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge	163:e59c8e839560	437
AnnaBridge	163:e59c8e839560	438	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge	163:e59c8e839560	439	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	440
AnnaBridge	163:e59c8e839560	441	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
AnnaBridge	163:e59c8e839560	442	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
AnnaBridge	163:e59c8e839560	443
AnnaBridge	163:e59c8e839560	444	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
AnnaBridge	163:e59c8e839560	445	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
AnnaBridge	163:e59c8e839560	446
AnnaBridge	163:e59c8e839560	447	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
AnnaBridge	163:e59c8e839560	448	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
AnnaBridge	163:e59c8e839560	449
AnnaBridge	163:e59c8e839560	450	uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge	163:e59c8e839560	451	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	163:e59c8e839560	452
AnnaBridge	163:e59c8e839560	453	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	454	#endif /* STM32F302x8 */
AnnaBridge	163:e59c8e839560	455
AnnaBridge	163:e59c8e839560	456	#if defined(STM32F302xC)
AnnaBridge	163:e59c8e839560	457	typedef struct
AnnaBridge	163:e59c8e839560	458	{
AnnaBridge	163:e59c8e839560	459	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	460	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	461
AnnaBridge	163:e59c8e839560	462	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	463	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	464
AnnaBridge	163:e59c8e839560	465	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	466	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	467
AnnaBridge	163:e59c8e839560	468	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	163:e59c8e839560	469	This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge	163:e59c8e839560	470
AnnaBridge	163:e59c8e839560	471	uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge	163:e59c8e839560	472	This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge	163:e59c8e839560	473
AnnaBridge	163:e59c8e839560	474	uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge	163:e59c8e839560	475	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge	163:e59c8e839560	476
AnnaBridge	163:e59c8e839560	477	uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge	163:e59c8e839560	478	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge	163:e59c8e839560	479
AnnaBridge	163:e59c8e839560	480	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	481	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	482
AnnaBridge	163:e59c8e839560	483	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge	163:e59c8e839560	484	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	163:e59c8e839560	485
AnnaBridge	163:e59c8e839560	486	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge	163:e59c8e839560	487	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge	163:e59c8e839560	488
AnnaBridge	163:e59c8e839560	489	uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge	163:e59c8e839560	490	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge	163:e59c8e839560	491
AnnaBridge	163:e59c8e839560	492	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge	163:e59c8e839560	493	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	494
AnnaBridge	163:e59c8e839560	495	uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge	163:e59c8e839560	496	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	163:e59c8e839560	497
AnnaBridge	163:e59c8e839560	498	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	499	#endif /* STM32F302xC */
AnnaBridge	163:e59c8e839560	500
AnnaBridge	163:e59c8e839560	501	#if defined(STM32F303xC)
AnnaBridge	163:e59c8e839560	502	typedef struct
AnnaBridge	163:e59c8e839560	503	{
AnnaBridge	163:e59c8e839560	504	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	505	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	506
AnnaBridge	163:e59c8e839560	507	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	508	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	509
AnnaBridge	163:e59c8e839560	510	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	511	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	512
AnnaBridge	163:e59c8e839560	513	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	163:e59c8e839560	514	This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge	163:e59c8e839560	515
AnnaBridge	163:e59c8e839560	516	uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge	163:e59c8e839560	517	This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge	163:e59c8e839560	518
AnnaBridge	163:e59c8e839560	519	uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge	163:e59c8e839560	520	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge	163:e59c8e839560	521
AnnaBridge	163:e59c8e839560	522	uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge	163:e59c8e839560	523	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge	163:e59c8e839560	524
AnnaBridge	163:e59c8e839560	525	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	526	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	527
AnnaBridge	163:e59c8e839560	528	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge	163:e59c8e839560	529	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	163:e59c8e839560	530
AnnaBridge	163:e59c8e839560	531	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge	163:e59c8e839560	532	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge	163:e59c8e839560	533
AnnaBridge	163:e59c8e839560	534	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
AnnaBridge	163:e59c8e839560	535	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
AnnaBridge	163:e59c8e839560	536
AnnaBridge	163:e59c8e839560	537	uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge	163:e59c8e839560	538	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge	163:e59c8e839560	539
AnnaBridge	163:e59c8e839560	540	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge	163:e59c8e839560	541	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	542
AnnaBridge	163:e59c8e839560	543	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
AnnaBridge	163:e59c8e839560	544	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
AnnaBridge	163:e59c8e839560	545
AnnaBridge	163:e59c8e839560	546	uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge	163:e59c8e839560	547	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	163:e59c8e839560	548
AnnaBridge	163:e59c8e839560	549	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	550	#endif /* STM32F303xC */
AnnaBridge	163:e59c8e839560	551
AnnaBridge	163:e59c8e839560	552	#if defined(STM32F302xE)
AnnaBridge	163:e59c8e839560	553	typedef struct
AnnaBridge	163:e59c8e839560	554	{
AnnaBridge	163:e59c8e839560	555	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	556	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	557
AnnaBridge	163:e59c8e839560	558	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	559	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	560
AnnaBridge	163:e59c8e839560	561	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	562	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	563
AnnaBridge	163:e59c8e839560	564	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	163:e59c8e839560	565	This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge	163:e59c8e839560	566
AnnaBridge	163:e59c8e839560	567	uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge	163:e59c8e839560	568	This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge	163:e59c8e839560	569
AnnaBridge	163:e59c8e839560	570	uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge	163:e59c8e839560	571	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge	163:e59c8e839560	572
AnnaBridge	163:e59c8e839560	573	uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge	163:e59c8e839560	574	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge	163:e59c8e839560	575
AnnaBridge	163:e59c8e839560	576	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	577	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	578
AnnaBridge	163:e59c8e839560	579	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge	163:e59c8e839560	580	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	163:e59c8e839560	581
AnnaBridge	163:e59c8e839560	582	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge	163:e59c8e839560	583	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge	163:e59c8e839560	584
AnnaBridge	163:e59c8e839560	585	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge	163:e59c8e839560	586	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge	163:e59c8e839560	587
AnnaBridge	163:e59c8e839560	588	uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge	163:e59c8e839560	589	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge	163:e59c8e839560	590
AnnaBridge	163:e59c8e839560	591	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge	163:e59c8e839560	592	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	593
AnnaBridge	163:e59c8e839560	594	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
AnnaBridge	163:e59c8e839560	595	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
AnnaBridge	163:e59c8e839560	596
AnnaBridge	163:e59c8e839560	597	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
AnnaBridge	163:e59c8e839560	598	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
AnnaBridge	163:e59c8e839560	599
AnnaBridge	163:e59c8e839560	600	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
AnnaBridge	163:e59c8e839560	601	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
AnnaBridge	163:e59c8e839560	602
AnnaBridge	163:e59c8e839560	603	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
AnnaBridge	163:e59c8e839560	604	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
AnnaBridge	163:e59c8e839560	605
AnnaBridge	163:e59c8e839560	606	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
AnnaBridge	163:e59c8e839560	607	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
AnnaBridge	163:e59c8e839560	608
AnnaBridge	163:e59c8e839560	609	uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge	163:e59c8e839560	610	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	163:e59c8e839560	611
AnnaBridge	163:e59c8e839560	612	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	613	#endif /* STM32F302xE */
AnnaBridge	163:e59c8e839560	614
AnnaBridge	163:e59c8e839560	615	#if defined(STM32F303xE)
AnnaBridge	163:e59c8e839560	616	typedef struct
AnnaBridge	163:e59c8e839560	617	{
AnnaBridge	163:e59c8e839560	618	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	619	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	620
AnnaBridge	163:e59c8e839560	621	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	622	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	623
AnnaBridge	163:e59c8e839560	624	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	625	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	626
AnnaBridge	163:e59c8e839560	627	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	163:e59c8e839560	628	This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge	163:e59c8e839560	629
AnnaBridge	163:e59c8e839560	630	uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge	163:e59c8e839560	631	This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge	163:e59c8e839560	632
AnnaBridge	163:e59c8e839560	633	uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge	163:e59c8e839560	634	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge	163:e59c8e839560	635
AnnaBridge	163:e59c8e839560	636	uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge	163:e59c8e839560	637	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge	163:e59c8e839560	638
AnnaBridge	163:e59c8e839560	639	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	640	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	641
AnnaBridge	163:e59c8e839560	642	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge	163:e59c8e839560	643	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	163:e59c8e839560	644
AnnaBridge	163:e59c8e839560	645	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge	163:e59c8e839560	646	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge	163:e59c8e839560	647
AnnaBridge	163:e59c8e839560	648	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge	163:e59c8e839560	649	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge	163:e59c8e839560	650
AnnaBridge	163:e59c8e839560	651	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
AnnaBridge	163:e59c8e839560	652	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
AnnaBridge	163:e59c8e839560	653
AnnaBridge	163:e59c8e839560	654	uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge	163:e59c8e839560	655	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge	163:e59c8e839560	656
AnnaBridge	163:e59c8e839560	657	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge	163:e59c8e839560	658	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	659
AnnaBridge	163:e59c8e839560	660	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
AnnaBridge	163:e59c8e839560	661	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
AnnaBridge	163:e59c8e839560	662
AnnaBridge	163:e59c8e839560	663	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
AnnaBridge	163:e59c8e839560	664	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
AnnaBridge	163:e59c8e839560	665
AnnaBridge	163:e59c8e839560	666	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
AnnaBridge	163:e59c8e839560	667	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
AnnaBridge	163:e59c8e839560	668
AnnaBridge	163:e59c8e839560	669	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
AnnaBridge	163:e59c8e839560	670	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
AnnaBridge	163:e59c8e839560	671
AnnaBridge	163:e59c8e839560	672	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
AnnaBridge	163:e59c8e839560	673	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
AnnaBridge	163:e59c8e839560	674
AnnaBridge	163:e59c8e839560	675	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
AnnaBridge	163:e59c8e839560	676	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
AnnaBridge	163:e59c8e839560	677
AnnaBridge	163:e59c8e839560	678	uint32_t Tim20ClockSelection; /*!< TIM20 clock source
AnnaBridge	163:e59c8e839560	679	This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
AnnaBridge	163:e59c8e839560	680
AnnaBridge	163:e59c8e839560	681	uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge	163:e59c8e839560	682	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	163:e59c8e839560	683
AnnaBridge	163:e59c8e839560	684	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	685	#endif /* STM32F303xE */
AnnaBridge	163:e59c8e839560	686
AnnaBridge	163:e59c8e839560	687	#if defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	688	typedef struct
AnnaBridge	163:e59c8e839560	689	{
AnnaBridge	163:e59c8e839560	690	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	691	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	692
AnnaBridge	163:e59c8e839560	693	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	694	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	695
AnnaBridge	163:e59c8e839560	696	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	697	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	698
AnnaBridge	163:e59c8e839560	699	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	163:e59c8e839560	700	This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge	163:e59c8e839560	701
AnnaBridge	163:e59c8e839560	702	uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge	163:e59c8e839560	703	This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge	163:e59c8e839560	704
AnnaBridge	163:e59c8e839560	705	uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge	163:e59c8e839560	706	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge	163:e59c8e839560	707
AnnaBridge	163:e59c8e839560	708	uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge	163:e59c8e839560	709	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge	163:e59c8e839560	710
AnnaBridge	163:e59c8e839560	711	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	712	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	713
AnnaBridge	163:e59c8e839560	714	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge	163:e59c8e839560	715	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	163:e59c8e839560	716
AnnaBridge	163:e59c8e839560	717	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge	163:e59c8e839560	718	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge	163:e59c8e839560	719
AnnaBridge	163:e59c8e839560	720	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge	163:e59c8e839560	721	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge	163:e59c8e839560	722
AnnaBridge	163:e59c8e839560	723	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
AnnaBridge	163:e59c8e839560	724	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
AnnaBridge	163:e59c8e839560	725
AnnaBridge	163:e59c8e839560	726	uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge	163:e59c8e839560	727	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge	163:e59c8e839560	728
AnnaBridge	163:e59c8e839560	729	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge	163:e59c8e839560	730	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	731
AnnaBridge	163:e59c8e839560	732	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
AnnaBridge	163:e59c8e839560	733	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
AnnaBridge	163:e59c8e839560	734
AnnaBridge	163:e59c8e839560	735	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
AnnaBridge	163:e59c8e839560	736	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
AnnaBridge	163:e59c8e839560	737
AnnaBridge	163:e59c8e839560	738	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
AnnaBridge	163:e59c8e839560	739	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
AnnaBridge	163:e59c8e839560	740
AnnaBridge	163:e59c8e839560	741	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
AnnaBridge	163:e59c8e839560	742	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
AnnaBridge	163:e59c8e839560	743
AnnaBridge	163:e59c8e839560	744	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
AnnaBridge	163:e59c8e839560	745	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
AnnaBridge	163:e59c8e839560	746
AnnaBridge	163:e59c8e839560	747	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
AnnaBridge	163:e59c8e839560	748	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
AnnaBridge	163:e59c8e839560	749
AnnaBridge	163:e59c8e839560	750	uint32_t Tim20ClockSelection; /*!< TIM20 clock source
AnnaBridge	163:e59c8e839560	751	This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
AnnaBridge	163:e59c8e839560	752
AnnaBridge	163:e59c8e839560	753	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	754	#endif /* STM32F398xx */
AnnaBridge	163:e59c8e839560	755
AnnaBridge	163:e59c8e839560	756	#if defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	757	typedef struct
AnnaBridge	163:e59c8e839560	758	{
AnnaBridge	163:e59c8e839560	759	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	760	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	761
AnnaBridge	163:e59c8e839560	762	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	763	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	764
AnnaBridge	163:e59c8e839560	765	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	766	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	767
AnnaBridge	163:e59c8e839560	768	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	163:e59c8e839560	769	This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge	163:e59c8e839560	770
AnnaBridge	163:e59c8e839560	771	uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge	163:e59c8e839560	772	This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge	163:e59c8e839560	773
AnnaBridge	163:e59c8e839560	774	uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge	163:e59c8e839560	775	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge	163:e59c8e839560	776
AnnaBridge	163:e59c8e839560	777	uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge	163:e59c8e839560	778	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge	163:e59c8e839560	779
AnnaBridge	163:e59c8e839560	780	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	781	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	782
AnnaBridge	163:e59c8e839560	783	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge	163:e59c8e839560	784	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	163:e59c8e839560	785
AnnaBridge	163:e59c8e839560	786	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge	163:e59c8e839560	787	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge	163:e59c8e839560	788
AnnaBridge	163:e59c8e839560	789	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
AnnaBridge	163:e59c8e839560	790	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
AnnaBridge	163:e59c8e839560	791
AnnaBridge	163:e59c8e839560	792	uint32_t I2sClockSelection; /*!< I2S clock source
AnnaBridge	163:e59c8e839560	793	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge	163:e59c8e839560	794
AnnaBridge	163:e59c8e839560	795	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge	163:e59c8e839560	796	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	797
AnnaBridge	163:e59c8e839560	798	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
AnnaBridge	163:e59c8e839560	799	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
AnnaBridge	163:e59c8e839560	800
AnnaBridge	163:e59c8e839560	801	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	802	#endif /* STM32F358xx */
AnnaBridge	163:e59c8e839560	803
AnnaBridge	163:e59c8e839560	804	#if defined(STM32F303x8)
AnnaBridge	163:e59c8e839560	805	typedef struct
AnnaBridge	163:e59c8e839560	806	{
AnnaBridge	163:e59c8e839560	807	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	808	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	809
AnnaBridge	163:e59c8e839560	810	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	811	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	812
AnnaBridge	163:e59c8e839560	813	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	814	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	815
AnnaBridge	163:e59c8e839560	816	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	817	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	818
AnnaBridge	163:e59c8e839560	819	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge	163:e59c8e839560	820	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge	163:e59c8e839560	821
AnnaBridge	163:e59c8e839560	822	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge	163:e59c8e839560	823	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	824
AnnaBridge	163:e59c8e839560	825	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	826	#endif /* STM32F303x8 */
AnnaBridge	163:e59c8e839560	827
AnnaBridge	163:e59c8e839560	828	#if defined(STM32F334x8)
AnnaBridge	163:e59c8e839560	829	typedef struct
AnnaBridge	163:e59c8e839560	830	{
AnnaBridge	163:e59c8e839560	831	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	832	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	833
AnnaBridge	163:e59c8e839560	834	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	835	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	836
AnnaBridge	163:e59c8e839560	837	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	838	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	839
AnnaBridge	163:e59c8e839560	840	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	841	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	842
AnnaBridge	163:e59c8e839560	843	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge	163:e59c8e839560	844	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge	163:e59c8e839560	845
AnnaBridge	163:e59c8e839560	846	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge	163:e59c8e839560	847	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	848
AnnaBridge	163:e59c8e839560	849	uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
AnnaBridge	163:e59c8e839560	850	This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	851
AnnaBridge	163:e59c8e839560	852	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	853	#endif /* STM32F334x8 */
AnnaBridge	163:e59c8e839560	854
AnnaBridge	163:e59c8e839560	855	#if defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	856	typedef struct
AnnaBridge	163:e59c8e839560	857	{
AnnaBridge	163:e59c8e839560	858	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	859	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	860
AnnaBridge	163:e59c8e839560	861	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	862	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	863
AnnaBridge	163:e59c8e839560	864	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	865	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	866
AnnaBridge	163:e59c8e839560	867	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	868	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	869
AnnaBridge	163:e59c8e839560	870	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
AnnaBridge	163:e59c8e839560	871	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
AnnaBridge	163:e59c8e839560	872
AnnaBridge	163:e59c8e839560	873	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
AnnaBridge	163:e59c8e839560	874	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
AnnaBridge	163:e59c8e839560	875
AnnaBridge	163:e59c8e839560	876	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	877	#endif /* STM32F328xx */
AnnaBridge	163:e59c8e839560	878
AnnaBridge	163:e59c8e839560	879	#if defined(STM32F373xC)
AnnaBridge	163:e59c8e839560	880	typedef struct
AnnaBridge	163:e59c8e839560	881	{
AnnaBridge	163:e59c8e839560	882	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	883	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	884
AnnaBridge	163:e59c8e839560	885	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	886	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	887
AnnaBridge	163:e59c8e839560	888	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	889	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	890
AnnaBridge	163:e59c8e839560	891	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	163:e59c8e839560	892	This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge	163:e59c8e839560	893
AnnaBridge	163:e59c8e839560	894	uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge	163:e59c8e839560	895	This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge	163:e59c8e839560	896
AnnaBridge	163:e59c8e839560	897	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	898	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	899
AnnaBridge	163:e59c8e839560	900	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge	163:e59c8e839560	901	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	163:e59c8e839560	902
AnnaBridge	163:e59c8e839560	903	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
AnnaBridge	163:e59c8e839560	904	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
AnnaBridge	163:e59c8e839560	905
AnnaBridge	163:e59c8e839560	906	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
AnnaBridge	163:e59c8e839560	907	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
AnnaBridge	163:e59c8e839560	908
AnnaBridge	163:e59c8e839560	909	uint32_t CecClockSelection; /*!< HDMI CEC clock source
AnnaBridge	163:e59c8e839560	910	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	163:e59c8e839560	911
AnnaBridge	163:e59c8e839560	912	uint32_t USBClockSelection; /*!< USB clock source
AnnaBridge	163:e59c8e839560	913	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	163:e59c8e839560	914
AnnaBridge	163:e59c8e839560	915	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	916	#endif /* STM32F373xC */
AnnaBridge	163:e59c8e839560	917
AnnaBridge	163:e59c8e839560	918	#if defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	919	typedef struct
AnnaBridge	163:e59c8e839560	920	{
AnnaBridge	163:e59c8e839560	921	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	163:e59c8e839560	922	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	163:e59c8e839560	923
AnnaBridge	163:e59c8e839560	924	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	163:e59c8e839560	925	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	163:e59c8e839560	926
AnnaBridge	163:e59c8e839560	927	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	163:e59c8e839560	928	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	163:e59c8e839560	929
AnnaBridge	163:e59c8e839560	930	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	163:e59c8e839560	931	This parameter can be a value of @ref RCC_USART2_Clock_Source */
AnnaBridge	163:e59c8e839560	932
AnnaBridge	163:e59c8e839560	933	uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge	163:e59c8e839560	934	This parameter can be a value of @ref RCC_USART3_Clock_Source */
AnnaBridge	163:e59c8e839560	935
AnnaBridge	163:e59c8e839560	936	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	163:e59c8e839560	937	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	163:e59c8e839560	938
AnnaBridge	163:e59c8e839560	939	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge	163:e59c8e839560	940	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	163:e59c8e839560	941
AnnaBridge	163:e59c8e839560	942	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
AnnaBridge	163:e59c8e839560	943	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
AnnaBridge	163:e59c8e839560	944
AnnaBridge	163:e59c8e839560	945	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
AnnaBridge	163:e59c8e839560	946	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
AnnaBridge	163:e59c8e839560	947
AnnaBridge	163:e59c8e839560	948	uint32_t CecClockSelection; /*!< HDMI CEC clock source
AnnaBridge	163:e59c8e839560	949	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	163:e59c8e839560	950
AnnaBridge	163:e59c8e839560	951	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	163:e59c8e839560	952	#endif /* STM32F378xx */
AnnaBridge	163:e59c8e839560	953
AnnaBridge	163:e59c8e839560	954	/**
AnnaBridge	163:e59c8e839560	955	* @}
AnnaBridge	163:e59c8e839560	956	*/
AnnaBridge	163:e59c8e839560	957
AnnaBridge	163:e59c8e839560	958	/* Exported constants --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	959	/** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
AnnaBridge	163:e59c8e839560	960	* @{
AnnaBridge	163:e59c8e839560	961	*/
AnnaBridge	163:e59c8e839560	962	/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
AnnaBridge	163:e59c8e839560	963	* @{
AnnaBridge	163:e59c8e839560	964	*/
AnnaBridge	163:e59c8e839560	965	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
AnnaBridge	163:e59c8e839560	966	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
AnnaBridge	163:e59c8e839560	967	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
AnnaBridge	163:e59c8e839560	968	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
AnnaBridge	163:e59c8e839560	969	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
AnnaBridge	163:e59c8e839560	970	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
AnnaBridge	163:e59c8e839560	971	#if defined(RCC_CFGR_PLLNODIV)
AnnaBridge	163:e59c8e839560	972	#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_PLLNODIV \| RCC_CFGR_MCO_PLL)
AnnaBridge	163:e59c8e839560	973	#endif /* RCC_CFGR_PLLNODIV */
AnnaBridge	163:e59c8e839560	974	#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
AnnaBridge	163:e59c8e839560	975
AnnaBridge	163:e59c8e839560	976	/**
AnnaBridge	163:e59c8e839560	977	* @}
AnnaBridge	163:e59c8e839560	978	*/
AnnaBridge	163:e59c8e839560	979
AnnaBridge	163:e59c8e839560	980	/** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
AnnaBridge	163:e59c8e839560	981	* @{
AnnaBridge	163:e59c8e839560	982	*/
AnnaBridge	163:e59c8e839560	983	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	984	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	985	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	986	#define RCC_PERIPHCLK_I2C2 (0x00000040U)
AnnaBridge	163:e59c8e839560	987	#define RCC_PERIPHCLK_ADC1 (0x00000080U)
AnnaBridge	163:e59c8e839560	988	#define RCC_PERIPHCLK_I2S (0x00000200U)
AnnaBridge	163:e59c8e839560	989	#define RCC_PERIPHCLK_TIM1 (0x00001000U)
AnnaBridge	163:e59c8e839560	990	#define RCC_PERIPHCLK_I2C3 (0x00008000U)
AnnaBridge	163:e59c8e839560	991	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	992	#define RCC_PERIPHCLK_TIM15 (0x00040000U)
AnnaBridge	163:e59c8e839560	993	#define RCC_PERIPHCLK_TIM16 (0x00080000U)
AnnaBridge	163:e59c8e839560	994	#define RCC_PERIPHCLK_TIM17 (0x00100000U)
AnnaBridge	163:e59c8e839560	995
AnnaBridge	163:e59c8e839560	996	#endif /* STM32F301x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	997
AnnaBridge	163:e59c8e839560	998	#if defined(STM32F302x8)
AnnaBridge	163:e59c8e839560	999	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1000	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1001	#define RCC_PERIPHCLK_I2C2 (0x00000040U)
AnnaBridge	163:e59c8e839560	1002	#define RCC_PERIPHCLK_ADC1 (0x00000080U)
AnnaBridge	163:e59c8e839560	1003	#define RCC_PERIPHCLK_I2S (0x00000200U)
AnnaBridge	163:e59c8e839560	1004	#define RCC_PERIPHCLK_TIM1 (0x00001000U)
AnnaBridge	163:e59c8e839560	1005	#define RCC_PERIPHCLK_I2C3 (0x00008000U)
AnnaBridge	163:e59c8e839560	1006	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1007	#define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge	163:e59c8e839560	1008	#define RCC_PERIPHCLK_TIM15 (0x00040000U)
AnnaBridge	163:e59c8e839560	1009	#define RCC_PERIPHCLK_TIM16 (0x00080000U)
AnnaBridge	163:e59c8e839560	1010	#define RCC_PERIPHCLK_TIM17 (0x00100000U)
AnnaBridge	163:e59c8e839560	1011
AnnaBridge	163:e59c8e839560	1012
AnnaBridge	163:e59c8e839560	1013	#endif /* STM32F302x8 */
AnnaBridge	163:e59c8e839560	1014
AnnaBridge	163:e59c8e839560	1015	#if defined(STM32F302xC)
AnnaBridge	163:e59c8e839560	1016	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1017	#define RCC_PERIPHCLK_USART2 (0x00000002U)
AnnaBridge	163:e59c8e839560	1018	#define RCC_PERIPHCLK_USART3 (0x00000004U)
AnnaBridge	163:e59c8e839560	1019	#define RCC_PERIPHCLK_UART4 (0x00000008U)
AnnaBridge	163:e59c8e839560	1020	#define RCC_PERIPHCLK_UART5 (0x00000010U)
AnnaBridge	163:e59c8e839560	1021	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1022	#define RCC_PERIPHCLK_I2C2 (0x00000040U)
AnnaBridge	163:e59c8e839560	1023	#define RCC_PERIPHCLK_ADC12 (0x00000080U)
AnnaBridge	163:e59c8e839560	1024	#define RCC_PERIPHCLK_I2S (0x00000200U)
AnnaBridge	163:e59c8e839560	1025	#define RCC_PERIPHCLK_TIM1 (0x00001000U)
AnnaBridge	163:e59c8e839560	1026	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1027	#define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge	163:e59c8e839560	1028
AnnaBridge	163:e59c8e839560	1029	#endif /* STM32F302xC */
AnnaBridge	163:e59c8e839560	1030
AnnaBridge	163:e59c8e839560	1031	#if defined(STM32F303xC)
AnnaBridge	163:e59c8e839560	1032	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1033	#define RCC_PERIPHCLK_USART2 (0x00000002U)
AnnaBridge	163:e59c8e839560	1034	#define RCC_PERIPHCLK_USART3 (0x00000004U)
AnnaBridge	163:e59c8e839560	1035	#define RCC_PERIPHCLK_UART4 (0x00000008U)
AnnaBridge	163:e59c8e839560	1036	#define RCC_PERIPHCLK_UART5 (0x00000010U)
AnnaBridge	163:e59c8e839560	1037	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1038	#define RCC_PERIPHCLK_I2C2 (0x00000040U)
AnnaBridge	163:e59c8e839560	1039	#define RCC_PERIPHCLK_ADC12 (0x00000080U)
AnnaBridge	163:e59c8e839560	1040	#define RCC_PERIPHCLK_ADC34 (0x00000100U)
AnnaBridge	163:e59c8e839560	1041	#define RCC_PERIPHCLK_I2S (0x00000200U)
AnnaBridge	163:e59c8e839560	1042	#define RCC_PERIPHCLK_TIM1 (0x00001000U)
AnnaBridge	163:e59c8e839560	1043	#define RCC_PERIPHCLK_TIM8 (0x00002000U)
AnnaBridge	163:e59c8e839560	1044	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1045	#define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge	163:e59c8e839560	1046
AnnaBridge	163:e59c8e839560	1047	#endif /* STM32F303xC */
AnnaBridge	163:e59c8e839560	1048
AnnaBridge	163:e59c8e839560	1049	#if defined(STM32F302xE)
AnnaBridge	163:e59c8e839560	1050	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1051	#define RCC_PERIPHCLK_USART2 (0x00000002U)
AnnaBridge	163:e59c8e839560	1052	#define RCC_PERIPHCLK_USART3 (0x00000004U)
AnnaBridge	163:e59c8e839560	1053	#define RCC_PERIPHCLK_UART4 (0x00000008U)
AnnaBridge	163:e59c8e839560	1054	#define RCC_PERIPHCLK_UART5 (0x00000010U)
AnnaBridge	163:e59c8e839560	1055	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1056	#define RCC_PERIPHCLK_I2C2 (0x00000040U)
AnnaBridge	163:e59c8e839560	1057	#define RCC_PERIPHCLK_ADC12 (0x00000080U)
AnnaBridge	163:e59c8e839560	1058	#define RCC_PERIPHCLK_I2S (0x00000200U)
AnnaBridge	163:e59c8e839560	1059	#define RCC_PERIPHCLK_TIM1 (0x00001000U)
AnnaBridge	163:e59c8e839560	1060	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1061	#define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge	163:e59c8e839560	1062	#define RCC_PERIPHCLK_I2C3 (0x00040000U)
AnnaBridge	163:e59c8e839560	1063	#define RCC_PERIPHCLK_TIM2 (0x00100000U)
AnnaBridge	163:e59c8e839560	1064	#define RCC_PERIPHCLK_TIM34 (0x00200000U)
AnnaBridge	163:e59c8e839560	1065	#define RCC_PERIPHCLK_TIM15 (0x00400000U)
AnnaBridge	163:e59c8e839560	1066	#define RCC_PERIPHCLK_TIM16 (0x00800000U)
AnnaBridge	163:e59c8e839560	1067	#define RCC_PERIPHCLK_TIM17 (0x01000000U)
AnnaBridge	163:e59c8e839560	1068
AnnaBridge	163:e59c8e839560	1069	#endif /* STM32F302xE */
AnnaBridge	163:e59c8e839560	1070
AnnaBridge	163:e59c8e839560	1071	#if defined(STM32F303xE)
AnnaBridge	163:e59c8e839560	1072	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1073	#define RCC_PERIPHCLK_USART2 (0x00000002U)
AnnaBridge	163:e59c8e839560	1074	#define RCC_PERIPHCLK_USART3 (0x00000004U)
AnnaBridge	163:e59c8e839560	1075	#define RCC_PERIPHCLK_UART4 (0x00000008U)
AnnaBridge	163:e59c8e839560	1076	#define RCC_PERIPHCLK_UART5 (0x00000010U)
AnnaBridge	163:e59c8e839560	1077	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1078	#define RCC_PERIPHCLK_I2C2 (0x00000040U)
AnnaBridge	163:e59c8e839560	1079	#define RCC_PERIPHCLK_ADC12 (0x00000080U)
AnnaBridge	163:e59c8e839560	1080	#define RCC_PERIPHCLK_ADC34 (0x00000100U)
AnnaBridge	163:e59c8e839560	1081	#define RCC_PERIPHCLK_I2S (0x00000200U)
AnnaBridge	163:e59c8e839560	1082	#define RCC_PERIPHCLK_TIM1 (0x00001000U)
AnnaBridge	163:e59c8e839560	1083	#define RCC_PERIPHCLK_TIM8 (0x00002000U)
AnnaBridge	163:e59c8e839560	1084	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1085	#define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge	163:e59c8e839560	1086	#define RCC_PERIPHCLK_I2C3 (0x00040000U)
AnnaBridge	163:e59c8e839560	1087	#define RCC_PERIPHCLK_TIM2 (0x00100000U)
AnnaBridge	163:e59c8e839560	1088	#define RCC_PERIPHCLK_TIM34 (0x00200000U)
AnnaBridge	163:e59c8e839560	1089	#define RCC_PERIPHCLK_TIM15 (0x00400000U)
AnnaBridge	163:e59c8e839560	1090	#define RCC_PERIPHCLK_TIM16 (0x00800000U)
AnnaBridge	163:e59c8e839560	1091	#define RCC_PERIPHCLK_TIM17 (0x01000000U)
AnnaBridge	163:e59c8e839560	1092	#define RCC_PERIPHCLK_TIM20 (0x02000000U)
AnnaBridge	163:e59c8e839560	1093
AnnaBridge	163:e59c8e839560	1094	#endif /* STM32F303xE */
AnnaBridge	163:e59c8e839560	1095
AnnaBridge	163:e59c8e839560	1096	#if defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	1097	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1098	#define RCC_PERIPHCLK_USART2 (0x00000002U)
AnnaBridge	163:e59c8e839560	1099	#define RCC_PERIPHCLK_USART3 (0x00000004U)
AnnaBridge	163:e59c8e839560	1100	#define RCC_PERIPHCLK_UART4 (0x00000008U)
AnnaBridge	163:e59c8e839560	1101	#define RCC_PERIPHCLK_UART5 (0x00000010U)
AnnaBridge	163:e59c8e839560	1102	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1103	#define RCC_PERIPHCLK_I2C2 (0x00000040U)
AnnaBridge	163:e59c8e839560	1104	#define RCC_PERIPHCLK_ADC12 (0x00000080U)
AnnaBridge	163:e59c8e839560	1105	#define RCC_PERIPHCLK_ADC34 (0x00000100U)
AnnaBridge	163:e59c8e839560	1106	#define RCC_PERIPHCLK_I2S (0x00000200U)
AnnaBridge	163:e59c8e839560	1107	#define RCC_PERIPHCLK_TIM1 (0x00001000U)
AnnaBridge	163:e59c8e839560	1108	#define RCC_PERIPHCLK_TIM8 (0x00002000U)
AnnaBridge	163:e59c8e839560	1109	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1110	#define RCC_PERIPHCLK_I2C3 (0x00040000U)
AnnaBridge	163:e59c8e839560	1111	#define RCC_PERIPHCLK_TIM2 (0x00100000U)
AnnaBridge	163:e59c8e839560	1112	#define RCC_PERIPHCLK_TIM34 (0x00200000U)
AnnaBridge	163:e59c8e839560	1113	#define RCC_PERIPHCLK_TIM15 (0x00400000U)
AnnaBridge	163:e59c8e839560	1114	#define RCC_PERIPHCLK_TIM16 (0x00800000U)
AnnaBridge	163:e59c8e839560	1115	#define RCC_PERIPHCLK_TIM17 (0x01000000U)
AnnaBridge	163:e59c8e839560	1116	#define RCC_PERIPHCLK_TIM20 (0x02000000U)
AnnaBridge	163:e59c8e839560	1117
AnnaBridge	163:e59c8e839560	1118
AnnaBridge	163:e59c8e839560	1119	#endif /* STM32F398xx */
AnnaBridge	163:e59c8e839560	1120
AnnaBridge	163:e59c8e839560	1121	#if defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	1122	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1123	#define RCC_PERIPHCLK_USART2 (0x00000002U)
AnnaBridge	163:e59c8e839560	1124	#define RCC_PERIPHCLK_USART3 (0x00000004U)
AnnaBridge	163:e59c8e839560	1125	#define RCC_PERIPHCLK_UART4 (0x00000008U)
AnnaBridge	163:e59c8e839560	1126	#define RCC_PERIPHCLK_UART5 (0x00000010U)
AnnaBridge	163:e59c8e839560	1127	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1128	#define RCC_PERIPHCLK_I2C2 (0x00000040U)
AnnaBridge	163:e59c8e839560	1129	#define RCC_PERIPHCLK_ADC12 (0x00000080U)
AnnaBridge	163:e59c8e839560	1130	#define RCC_PERIPHCLK_ADC34 (0x00000100U)
AnnaBridge	163:e59c8e839560	1131	#define RCC_PERIPHCLK_I2S (0x00000200U)
AnnaBridge	163:e59c8e839560	1132	#define RCC_PERIPHCLK_TIM1 (0x00001000U)
AnnaBridge	163:e59c8e839560	1133	#define RCC_PERIPHCLK_TIM8 (0x00002000U)
AnnaBridge	163:e59c8e839560	1134	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1135
AnnaBridge	163:e59c8e839560	1136	#endif /* STM32F358xx */
AnnaBridge	163:e59c8e839560	1137
AnnaBridge	163:e59c8e839560	1138	#if defined(STM32F303x8)
AnnaBridge	163:e59c8e839560	1139	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1140	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1141	#define RCC_PERIPHCLK_ADC12 (0x00000080U)
AnnaBridge	163:e59c8e839560	1142	#define RCC_PERIPHCLK_TIM1 (0x00001000U)
AnnaBridge	163:e59c8e839560	1143	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1144
AnnaBridge	163:e59c8e839560	1145	#endif /* STM32F303x8 */
AnnaBridge	163:e59c8e839560	1146
AnnaBridge	163:e59c8e839560	1147	#if defined(STM32F334x8)
AnnaBridge	163:e59c8e839560	1148	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1149	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1150	#define RCC_PERIPHCLK_ADC12 (0x00000080U)
AnnaBridge	163:e59c8e839560	1151	#define RCC_PERIPHCLK_TIM1 (0x00001000U)
AnnaBridge	163:e59c8e839560	1152	#define RCC_PERIPHCLK_HRTIM1 (0x00004000U)
AnnaBridge	163:e59c8e839560	1153	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1154
AnnaBridge	163:e59c8e839560	1155
AnnaBridge	163:e59c8e839560	1156	#endif /* STM32F334x8 */
AnnaBridge	163:e59c8e839560	1157
AnnaBridge	163:e59c8e839560	1158	#if defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	1159	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1160	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1161	#define RCC_PERIPHCLK_ADC12 (0x00000080U)
AnnaBridge	163:e59c8e839560	1162	#define RCC_PERIPHCLK_TIM1 (0x00001000U)
AnnaBridge	163:e59c8e839560	1163	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1164
AnnaBridge	163:e59c8e839560	1165	#endif /* STM32F328xx */
AnnaBridge	163:e59c8e839560	1166
AnnaBridge	163:e59c8e839560	1167	#if defined(STM32F373xC)
AnnaBridge	163:e59c8e839560	1168	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1169	#define RCC_PERIPHCLK_USART2 (0x00000002U)
AnnaBridge	163:e59c8e839560	1170	#define RCC_PERIPHCLK_USART3 (0x00000004U)
AnnaBridge	163:e59c8e839560	1171	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1172	#define RCC_PERIPHCLK_I2C2 (0x00000040U)
AnnaBridge	163:e59c8e839560	1173	#define RCC_PERIPHCLK_ADC1 (0x00000080U)
AnnaBridge	163:e59c8e839560	1174	#define RCC_PERIPHCLK_CEC (0x00000400U)
AnnaBridge	163:e59c8e839560	1175	#define RCC_PERIPHCLK_SDADC (0x00000800U)
AnnaBridge	163:e59c8e839560	1176	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1177	#define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge	163:e59c8e839560	1178
AnnaBridge	163:e59c8e839560	1179	#endif /* STM32F373xC */
AnnaBridge	163:e59c8e839560	1180
AnnaBridge	163:e59c8e839560	1181	#if defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	1182	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	163:e59c8e839560	1183	#define RCC_PERIPHCLK_USART2 (0x00000002U)
AnnaBridge	163:e59c8e839560	1184	#define RCC_PERIPHCLK_USART3 (0x00000004U)
AnnaBridge	163:e59c8e839560	1185	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	163:e59c8e839560	1186	#define RCC_PERIPHCLK_I2C2 (0x00000040U)
AnnaBridge	163:e59c8e839560	1187	#define RCC_PERIPHCLK_ADC1 (0x00000080U)
AnnaBridge	163:e59c8e839560	1188	#define RCC_PERIPHCLK_CEC (0x00000400U)
AnnaBridge	163:e59c8e839560	1189	#define RCC_PERIPHCLK_SDADC (0x00000800U)
AnnaBridge	163:e59c8e839560	1190	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	163:e59c8e839560	1191
AnnaBridge	163:e59c8e839560	1192	#endif /* STM32F378xx */
AnnaBridge	163:e59c8e839560	1193	/**
AnnaBridge	163:e59c8e839560	1194	* @}
AnnaBridge	163:e59c8e839560	1195	*/
AnnaBridge	163:e59c8e839560	1196
AnnaBridge	163:e59c8e839560	1197	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	1198
AnnaBridge	163:e59c8e839560	1199	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
AnnaBridge	163:e59c8e839560	1200	* @{
AnnaBridge	163:e59c8e839560	1201	*/
AnnaBridge	163:e59c8e839560	1202	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
AnnaBridge	163:e59c8e839560	1203	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
AnnaBridge	163:e59c8e839560	1204	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
AnnaBridge	163:e59c8e839560	1205	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
AnnaBridge	163:e59c8e839560	1206
AnnaBridge	163:e59c8e839560	1207	/**
AnnaBridge	163:e59c8e839560	1208	* @}
AnnaBridge	163:e59c8e839560	1209	*/
AnnaBridge	163:e59c8e839560	1210
AnnaBridge	163:e59c8e839560	1211	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
AnnaBridge	163:e59c8e839560	1212	* @{
AnnaBridge	163:e59c8e839560	1213	*/
AnnaBridge	163:e59c8e839560	1214	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
AnnaBridge	163:e59c8e839560	1215	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
AnnaBridge	163:e59c8e839560	1216
AnnaBridge	163:e59c8e839560	1217	/**
AnnaBridge	163:e59c8e839560	1218	* @}
AnnaBridge	163:e59c8e839560	1219	*/
AnnaBridge	163:e59c8e839560	1220
AnnaBridge	163:e59c8e839560	1221	/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
AnnaBridge	163:e59c8e839560	1222	* @{
AnnaBridge	163:e59c8e839560	1223	*/
AnnaBridge	163:e59c8e839560	1224	#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
AnnaBridge	163:e59c8e839560	1225	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
AnnaBridge	163:e59c8e839560	1226
AnnaBridge	163:e59c8e839560	1227	/**
AnnaBridge	163:e59c8e839560	1228	* @}
AnnaBridge	163:e59c8e839560	1229	*/
AnnaBridge	163:e59c8e839560	1230
AnnaBridge	163:e59c8e839560	1231	/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
AnnaBridge	163:e59c8e839560	1232	* @{
AnnaBridge	163:e59c8e839560	1233	*/
AnnaBridge	163:e59c8e839560	1234	#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
AnnaBridge	163:e59c8e839560	1235	#define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
AnnaBridge	163:e59c8e839560	1236	#define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
AnnaBridge	163:e59c8e839560	1237	#define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
AnnaBridge	163:e59c8e839560	1238	#define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
AnnaBridge	163:e59c8e839560	1239	#define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
AnnaBridge	163:e59c8e839560	1240	#define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
AnnaBridge	163:e59c8e839560	1241	#define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
AnnaBridge	163:e59c8e839560	1242	#define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
AnnaBridge	163:e59c8e839560	1243	#define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
AnnaBridge	163:e59c8e839560	1244	#define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
AnnaBridge	163:e59c8e839560	1245	#define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
AnnaBridge	163:e59c8e839560	1246	#define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
AnnaBridge	163:e59c8e839560	1247
AnnaBridge	163:e59c8e839560	1248	/**
AnnaBridge	163:e59c8e839560	1249	* @}
AnnaBridge	163:e59c8e839560	1250	*/
AnnaBridge	163:e59c8e839560	1251
AnnaBridge	163:e59c8e839560	1252	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
AnnaBridge	163:e59c8e839560	1253	* @{
AnnaBridge	163:e59c8e839560	1254	*/
AnnaBridge	163:e59c8e839560	1255	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
AnnaBridge	163:e59c8e839560	1256	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
AnnaBridge	163:e59c8e839560	1257
AnnaBridge	163:e59c8e839560	1258	/**
AnnaBridge	163:e59c8e839560	1259	* @}
AnnaBridge	163:e59c8e839560	1260	*/
AnnaBridge	163:e59c8e839560	1261
AnnaBridge	163:e59c8e839560	1262	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
AnnaBridge	163:e59c8e839560	1263	* @{
AnnaBridge	163:e59c8e839560	1264	*/
AnnaBridge	163:e59c8e839560	1265	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
AnnaBridge	163:e59c8e839560	1266	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
AnnaBridge	163:e59c8e839560	1267
AnnaBridge	163:e59c8e839560	1268	/**
AnnaBridge	163:e59c8e839560	1269	* @}
AnnaBridge	163:e59c8e839560	1270	*/
AnnaBridge	163:e59c8e839560	1271
AnnaBridge	163:e59c8e839560	1272	/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
AnnaBridge	163:e59c8e839560	1273	* @{
AnnaBridge	163:e59c8e839560	1274	*/
AnnaBridge	163:e59c8e839560	1275	#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
AnnaBridge	163:e59c8e839560	1276	#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
AnnaBridge	163:e59c8e839560	1277
AnnaBridge	163:e59c8e839560	1278	/**
AnnaBridge	163:e59c8e839560	1279	* @}
AnnaBridge	163:e59c8e839560	1280	*/
AnnaBridge	163:e59c8e839560	1281
AnnaBridge	163:e59c8e839560	1282	/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
AnnaBridge	163:e59c8e839560	1283	* @{
AnnaBridge	163:e59c8e839560	1284	*/
AnnaBridge	163:e59c8e839560	1285	#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
AnnaBridge	163:e59c8e839560	1286	#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
AnnaBridge	163:e59c8e839560	1287
AnnaBridge	163:e59c8e839560	1288	/**
AnnaBridge	163:e59c8e839560	1289	* @}
AnnaBridge	163:e59c8e839560	1290	*/
AnnaBridge	163:e59c8e839560	1291
AnnaBridge	163:e59c8e839560	1292	/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
AnnaBridge	163:e59c8e839560	1293	* @{
AnnaBridge	163:e59c8e839560	1294	*/
AnnaBridge	163:e59c8e839560	1295	#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
AnnaBridge	163:e59c8e839560	1296	#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
AnnaBridge	163:e59c8e839560	1297
AnnaBridge	163:e59c8e839560	1298	/**
AnnaBridge	163:e59c8e839560	1299	* @}
AnnaBridge	163:e59c8e839560	1300	*/
AnnaBridge	163:e59c8e839560	1301
AnnaBridge	163:e59c8e839560	1302	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	1303
AnnaBridge	163:e59c8e839560	1304	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	1305
AnnaBridge	163:e59c8e839560	1306	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
AnnaBridge	163:e59c8e839560	1307	* @{
AnnaBridge	163:e59c8e839560	1308	*/
AnnaBridge	163:e59c8e839560	1309	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
AnnaBridge	163:e59c8e839560	1310	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
AnnaBridge	163:e59c8e839560	1311	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
AnnaBridge	163:e59c8e839560	1312	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
AnnaBridge	163:e59c8e839560	1313
AnnaBridge	163:e59c8e839560	1314	/**
AnnaBridge	163:e59c8e839560	1315	* @}
AnnaBridge	163:e59c8e839560	1316	*/
AnnaBridge	163:e59c8e839560	1317
AnnaBridge	163:e59c8e839560	1318	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
AnnaBridge	163:e59c8e839560	1319	* @{
AnnaBridge	163:e59c8e839560	1320	*/
AnnaBridge	163:e59c8e839560	1321	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
AnnaBridge	163:e59c8e839560	1322	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
AnnaBridge	163:e59c8e839560	1323
AnnaBridge	163:e59c8e839560	1324	/**
AnnaBridge	163:e59c8e839560	1325	* @}
AnnaBridge	163:e59c8e839560	1326	*/
AnnaBridge	163:e59c8e839560	1327
AnnaBridge	163:e59c8e839560	1328	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
AnnaBridge	163:e59c8e839560	1329	* @{
AnnaBridge	163:e59c8e839560	1330	*/
AnnaBridge	163:e59c8e839560	1331
AnnaBridge	163:e59c8e839560	1332	/* ADC1 & ADC2 */
AnnaBridge	163:e59c8e839560	1333	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
AnnaBridge	163:e59c8e839560	1334	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
AnnaBridge	163:e59c8e839560	1335	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
AnnaBridge	163:e59c8e839560	1336	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
AnnaBridge	163:e59c8e839560	1337	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
AnnaBridge	163:e59c8e839560	1338	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
AnnaBridge	163:e59c8e839560	1339	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
AnnaBridge	163:e59c8e839560	1340	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
AnnaBridge	163:e59c8e839560	1341	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
AnnaBridge	163:e59c8e839560	1342	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
AnnaBridge	163:e59c8e839560	1343	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
AnnaBridge	163:e59c8e839560	1344	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
AnnaBridge	163:e59c8e839560	1345	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
AnnaBridge	163:e59c8e839560	1346
AnnaBridge	163:e59c8e839560	1347	/**
AnnaBridge	163:e59c8e839560	1348	* @}
AnnaBridge	163:e59c8e839560	1349	*/
AnnaBridge	163:e59c8e839560	1350
AnnaBridge	163:e59c8e839560	1351	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
AnnaBridge	163:e59c8e839560	1352	* @{
AnnaBridge	163:e59c8e839560	1353	*/
AnnaBridge	163:e59c8e839560	1354	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
AnnaBridge	163:e59c8e839560	1355	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
AnnaBridge	163:e59c8e839560	1356
AnnaBridge	163:e59c8e839560	1357	/**
AnnaBridge	163:e59c8e839560	1358	* @}
AnnaBridge	163:e59c8e839560	1359	*/
AnnaBridge	163:e59c8e839560	1360	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
AnnaBridge	163:e59c8e839560	1361	* @{
AnnaBridge	163:e59c8e839560	1362	*/
AnnaBridge	163:e59c8e839560	1363	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
AnnaBridge	163:e59c8e839560	1364	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
AnnaBridge	163:e59c8e839560	1365
AnnaBridge	163:e59c8e839560	1366	/**
AnnaBridge	163:e59c8e839560	1367	* @}
AnnaBridge	163:e59c8e839560	1368	*/
AnnaBridge	163:e59c8e839560	1369
AnnaBridge	163:e59c8e839560	1370	/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
AnnaBridge	163:e59c8e839560	1371	* @{
AnnaBridge	163:e59c8e839560	1372	*/
AnnaBridge	163:e59c8e839560	1373	#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
AnnaBridge	163:e59c8e839560	1374	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
AnnaBridge	163:e59c8e839560	1375	#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
AnnaBridge	163:e59c8e839560	1376	#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
AnnaBridge	163:e59c8e839560	1377
AnnaBridge	163:e59c8e839560	1378	/**
AnnaBridge	163:e59c8e839560	1379	* @}
AnnaBridge	163:e59c8e839560	1380	*/
AnnaBridge	163:e59c8e839560	1381
AnnaBridge	163:e59c8e839560	1382	/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
AnnaBridge	163:e59c8e839560	1383	* @{
AnnaBridge	163:e59c8e839560	1384	*/
AnnaBridge	163:e59c8e839560	1385	#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
AnnaBridge	163:e59c8e839560	1386	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
AnnaBridge	163:e59c8e839560	1387	#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
AnnaBridge	163:e59c8e839560	1388	#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
AnnaBridge	163:e59c8e839560	1389
AnnaBridge	163:e59c8e839560	1390	/**
AnnaBridge	163:e59c8e839560	1391	* @}
AnnaBridge	163:e59c8e839560	1392	*/
AnnaBridge	163:e59c8e839560	1393
AnnaBridge	163:e59c8e839560	1394	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	1395
AnnaBridge	163:e59c8e839560	1396	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	1397
AnnaBridge	163:e59c8e839560	1398	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
AnnaBridge	163:e59c8e839560	1399	* @{
AnnaBridge	163:e59c8e839560	1400	*/
AnnaBridge	163:e59c8e839560	1401	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
AnnaBridge	163:e59c8e839560	1402	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
AnnaBridge	163:e59c8e839560	1403	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
AnnaBridge	163:e59c8e839560	1404	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
AnnaBridge	163:e59c8e839560	1405
AnnaBridge	163:e59c8e839560	1406	/**
AnnaBridge	163:e59c8e839560	1407	* @}
AnnaBridge	163:e59c8e839560	1408	*/
AnnaBridge	163:e59c8e839560	1409
AnnaBridge	163:e59c8e839560	1410	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
AnnaBridge	163:e59c8e839560	1411	* @{
AnnaBridge	163:e59c8e839560	1412	*/
AnnaBridge	163:e59c8e839560	1413	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
AnnaBridge	163:e59c8e839560	1414	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
AnnaBridge	163:e59c8e839560	1415
AnnaBridge	163:e59c8e839560	1416	/**
AnnaBridge	163:e59c8e839560	1417	* @}
AnnaBridge	163:e59c8e839560	1418	*/
AnnaBridge	163:e59c8e839560	1419
AnnaBridge	163:e59c8e839560	1420	/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
AnnaBridge	163:e59c8e839560	1421	* @{
AnnaBridge	163:e59c8e839560	1422	*/
AnnaBridge	163:e59c8e839560	1423	#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
AnnaBridge	163:e59c8e839560	1424	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
AnnaBridge	163:e59c8e839560	1425
AnnaBridge	163:e59c8e839560	1426	/**
AnnaBridge	163:e59c8e839560	1427	* @}
AnnaBridge	163:e59c8e839560	1428	*/
AnnaBridge	163:e59c8e839560	1429
AnnaBridge	163:e59c8e839560	1430	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
AnnaBridge	163:e59c8e839560	1431	* @{
AnnaBridge	163:e59c8e839560	1432	*/
AnnaBridge	163:e59c8e839560	1433
AnnaBridge	163:e59c8e839560	1434	/* ADC1 & ADC2 */
AnnaBridge	163:e59c8e839560	1435	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
AnnaBridge	163:e59c8e839560	1436	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
AnnaBridge	163:e59c8e839560	1437	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
AnnaBridge	163:e59c8e839560	1438	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
AnnaBridge	163:e59c8e839560	1439	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
AnnaBridge	163:e59c8e839560	1440	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
AnnaBridge	163:e59c8e839560	1441	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
AnnaBridge	163:e59c8e839560	1442	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
AnnaBridge	163:e59c8e839560	1443	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
AnnaBridge	163:e59c8e839560	1444	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
AnnaBridge	163:e59c8e839560	1445	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
AnnaBridge	163:e59c8e839560	1446	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
AnnaBridge	163:e59c8e839560	1447	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
AnnaBridge	163:e59c8e839560	1448
AnnaBridge	163:e59c8e839560	1449	/**
AnnaBridge	163:e59c8e839560	1450	* @}
AnnaBridge	163:e59c8e839560	1451	*/
AnnaBridge	163:e59c8e839560	1452
AnnaBridge	163:e59c8e839560	1453	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
AnnaBridge	163:e59c8e839560	1454	* @{
AnnaBridge	163:e59c8e839560	1455	*/
AnnaBridge	163:e59c8e839560	1456	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
AnnaBridge	163:e59c8e839560	1457	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
AnnaBridge	163:e59c8e839560	1458
AnnaBridge	163:e59c8e839560	1459	/**
AnnaBridge	163:e59c8e839560	1460	* @}
AnnaBridge	163:e59c8e839560	1461	*/
AnnaBridge	163:e59c8e839560	1462
AnnaBridge	163:e59c8e839560	1463	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
AnnaBridge	163:e59c8e839560	1464	* @{
AnnaBridge	163:e59c8e839560	1465	*/
AnnaBridge	163:e59c8e839560	1466	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
AnnaBridge	163:e59c8e839560	1467	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
AnnaBridge	163:e59c8e839560	1468
AnnaBridge	163:e59c8e839560	1469	/**
AnnaBridge	163:e59c8e839560	1470	* @}
AnnaBridge	163:e59c8e839560	1471	*/
AnnaBridge	163:e59c8e839560	1472
AnnaBridge	163:e59c8e839560	1473	/** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
AnnaBridge	163:e59c8e839560	1474	* @{
AnnaBridge	163:e59c8e839560	1475	*/
AnnaBridge	163:e59c8e839560	1476	#define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
AnnaBridge	163:e59c8e839560	1477	#define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
AnnaBridge	163:e59c8e839560	1478
AnnaBridge	163:e59c8e839560	1479	/**
AnnaBridge	163:e59c8e839560	1480	* @}
AnnaBridge	163:e59c8e839560	1481	*/
AnnaBridge	163:e59c8e839560	1482
AnnaBridge	163:e59c8e839560	1483	/** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
AnnaBridge	163:e59c8e839560	1484	* @{
AnnaBridge	163:e59c8e839560	1485	*/
AnnaBridge	163:e59c8e839560	1486	#define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
AnnaBridge	163:e59c8e839560	1487	#define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
AnnaBridge	163:e59c8e839560	1488
AnnaBridge	163:e59c8e839560	1489	/**
AnnaBridge	163:e59c8e839560	1490	* @}
AnnaBridge	163:e59c8e839560	1491	*/
AnnaBridge	163:e59c8e839560	1492
AnnaBridge	163:e59c8e839560	1493	/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
AnnaBridge	163:e59c8e839560	1494	* @{
AnnaBridge	163:e59c8e839560	1495	*/
AnnaBridge	163:e59c8e839560	1496	#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
AnnaBridge	163:e59c8e839560	1497	#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
AnnaBridge	163:e59c8e839560	1498
AnnaBridge	163:e59c8e839560	1499	/**
AnnaBridge	163:e59c8e839560	1500	* @}
AnnaBridge	163:e59c8e839560	1501	*/
AnnaBridge	163:e59c8e839560	1502
AnnaBridge	163:e59c8e839560	1503	/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
AnnaBridge	163:e59c8e839560	1504	* @{
AnnaBridge	163:e59c8e839560	1505	*/
AnnaBridge	163:e59c8e839560	1506	#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
AnnaBridge	163:e59c8e839560	1507	#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
AnnaBridge	163:e59c8e839560	1508
AnnaBridge	163:e59c8e839560	1509	/**
AnnaBridge	163:e59c8e839560	1510	* @}
AnnaBridge	163:e59c8e839560	1511	*/
AnnaBridge	163:e59c8e839560	1512
AnnaBridge	163:e59c8e839560	1513	/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
AnnaBridge	163:e59c8e839560	1514	* @{
AnnaBridge	163:e59c8e839560	1515	*/
AnnaBridge	163:e59c8e839560	1516	#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
AnnaBridge	163:e59c8e839560	1517	#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
AnnaBridge	163:e59c8e839560	1518
AnnaBridge	163:e59c8e839560	1519	/**
AnnaBridge	163:e59c8e839560	1520	* @}
AnnaBridge	163:e59c8e839560	1521	*/
AnnaBridge	163:e59c8e839560	1522
AnnaBridge	163:e59c8e839560	1523	/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
AnnaBridge	163:e59c8e839560	1524	* @{
AnnaBridge	163:e59c8e839560	1525	*/
AnnaBridge	163:e59c8e839560	1526	#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
AnnaBridge	163:e59c8e839560	1527	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
AnnaBridge	163:e59c8e839560	1528	#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
AnnaBridge	163:e59c8e839560	1529	#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
AnnaBridge	163:e59c8e839560	1530
AnnaBridge	163:e59c8e839560	1531	/**
AnnaBridge	163:e59c8e839560	1532	* @}
AnnaBridge	163:e59c8e839560	1533	*/
AnnaBridge	163:e59c8e839560	1534
AnnaBridge	163:e59c8e839560	1535	/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
AnnaBridge	163:e59c8e839560	1536	* @{
AnnaBridge	163:e59c8e839560	1537	*/
AnnaBridge	163:e59c8e839560	1538	#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
AnnaBridge	163:e59c8e839560	1539	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
AnnaBridge	163:e59c8e839560	1540	#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
AnnaBridge	163:e59c8e839560	1541	#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
AnnaBridge	163:e59c8e839560	1542
AnnaBridge	163:e59c8e839560	1543	/**
AnnaBridge	163:e59c8e839560	1544	* @}
AnnaBridge	163:e59c8e839560	1545	*/
AnnaBridge	163:e59c8e839560	1546
AnnaBridge	163:e59c8e839560	1547	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	1548
AnnaBridge	163:e59c8e839560	1549	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	1550	/** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
AnnaBridge	163:e59c8e839560	1551	* @{
AnnaBridge	163:e59c8e839560	1552	*/
AnnaBridge	163:e59c8e839560	1553	#define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
AnnaBridge	163:e59c8e839560	1554	#define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
AnnaBridge	163:e59c8e839560	1555
AnnaBridge	163:e59c8e839560	1556	/**
AnnaBridge	163:e59c8e839560	1557	* @}
AnnaBridge	163:e59c8e839560	1558	*/
AnnaBridge	163:e59c8e839560	1559	#endif /* STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	1560
AnnaBridge	163:e59c8e839560	1561	#if defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	1562	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	1563
AnnaBridge	163:e59c8e839560	1564	/** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
AnnaBridge	163:e59c8e839560	1565	* @{
AnnaBridge	163:e59c8e839560	1566	*/
AnnaBridge	163:e59c8e839560	1567
AnnaBridge	163:e59c8e839560	1568	/* ADC3 & ADC4 */
AnnaBridge	163:e59c8e839560	1569	#define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
AnnaBridge	163:e59c8e839560	1570	#define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
AnnaBridge	163:e59c8e839560	1571	#define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
AnnaBridge	163:e59c8e839560	1572	#define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
AnnaBridge	163:e59c8e839560	1573	#define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
AnnaBridge	163:e59c8e839560	1574	#define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
AnnaBridge	163:e59c8e839560	1575	#define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
AnnaBridge	163:e59c8e839560	1576	#define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
AnnaBridge	163:e59c8e839560	1577	#define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
AnnaBridge	163:e59c8e839560	1578	#define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
AnnaBridge	163:e59c8e839560	1579	#define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
AnnaBridge	163:e59c8e839560	1580	#define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
AnnaBridge	163:e59c8e839560	1581	#define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
AnnaBridge	163:e59c8e839560	1582
AnnaBridge	163:e59c8e839560	1583	/**
AnnaBridge	163:e59c8e839560	1584	* @}
AnnaBridge	163:e59c8e839560	1585	*/
AnnaBridge	163:e59c8e839560	1586
AnnaBridge	163:e59c8e839560	1587	/** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
AnnaBridge	163:e59c8e839560	1588	* @{
AnnaBridge	163:e59c8e839560	1589	*/
AnnaBridge	163:e59c8e839560	1590	#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
AnnaBridge	163:e59c8e839560	1591	#define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
AnnaBridge	163:e59c8e839560	1592
AnnaBridge	163:e59c8e839560	1593	/**
AnnaBridge	163:e59c8e839560	1594	* @}
AnnaBridge	163:e59c8e839560	1595	*/
AnnaBridge	163:e59c8e839560	1596
AnnaBridge	163:e59c8e839560	1597	#endif /* STM32F303xC \|\| STM32F303xE \|\| STM32F398xx \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	1598
AnnaBridge	163:e59c8e839560	1599	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	1600
AnnaBridge	163:e59c8e839560	1601	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
AnnaBridge	163:e59c8e839560	1602	* @{
AnnaBridge	163:e59c8e839560	1603	*/
AnnaBridge	163:e59c8e839560	1604	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
AnnaBridge	163:e59c8e839560	1605	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
AnnaBridge	163:e59c8e839560	1606	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
AnnaBridge	163:e59c8e839560	1607	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
AnnaBridge	163:e59c8e839560	1608
AnnaBridge	163:e59c8e839560	1609	/**
AnnaBridge	163:e59c8e839560	1610	* @}
AnnaBridge	163:e59c8e839560	1611	*/
AnnaBridge	163:e59c8e839560	1612
AnnaBridge	163:e59c8e839560	1613	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
AnnaBridge	163:e59c8e839560	1614	* @{
AnnaBridge	163:e59c8e839560	1615	*/
AnnaBridge	163:e59c8e839560	1616	/* ADC1 & ADC2 */
AnnaBridge	163:e59c8e839560	1617	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
AnnaBridge	163:e59c8e839560	1618	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
AnnaBridge	163:e59c8e839560	1619	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
AnnaBridge	163:e59c8e839560	1620	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
AnnaBridge	163:e59c8e839560	1621	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
AnnaBridge	163:e59c8e839560	1622	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
AnnaBridge	163:e59c8e839560	1623	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
AnnaBridge	163:e59c8e839560	1624	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
AnnaBridge	163:e59c8e839560	1625	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
AnnaBridge	163:e59c8e839560	1626	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
AnnaBridge	163:e59c8e839560	1627	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
AnnaBridge	163:e59c8e839560	1628	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
AnnaBridge	163:e59c8e839560	1629	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
AnnaBridge	163:e59c8e839560	1630
AnnaBridge	163:e59c8e839560	1631	/**
AnnaBridge	163:e59c8e839560	1632	* @}
AnnaBridge	163:e59c8e839560	1633	*/
AnnaBridge	163:e59c8e839560	1634
AnnaBridge	163:e59c8e839560	1635	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
AnnaBridge	163:e59c8e839560	1636	* @{
AnnaBridge	163:e59c8e839560	1637	*/
AnnaBridge	163:e59c8e839560	1638	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
AnnaBridge	163:e59c8e839560	1639	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
AnnaBridge	163:e59c8e839560	1640
AnnaBridge	163:e59c8e839560	1641	/**
AnnaBridge	163:e59c8e839560	1642	* @}
AnnaBridge	163:e59c8e839560	1643	*/
AnnaBridge	163:e59c8e839560	1644
AnnaBridge	163:e59c8e839560	1645	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	1646
AnnaBridge	163:e59c8e839560	1647	#if defined(STM32F334x8)
AnnaBridge	163:e59c8e839560	1648
AnnaBridge	163:e59c8e839560	1649	/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
AnnaBridge	163:e59c8e839560	1650	* @{
AnnaBridge	163:e59c8e839560	1651	*/
AnnaBridge	163:e59c8e839560	1652	#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
AnnaBridge	163:e59c8e839560	1653	#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
AnnaBridge	163:e59c8e839560	1654
AnnaBridge	163:e59c8e839560	1655	/**
AnnaBridge	163:e59c8e839560	1656	* @}
AnnaBridge	163:e59c8e839560	1657	*/
AnnaBridge	163:e59c8e839560	1658
AnnaBridge	163:e59c8e839560	1659	#endif /* STM32F334x8 */
AnnaBridge	163:e59c8e839560	1660
AnnaBridge	163:e59c8e839560	1661	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	1662
AnnaBridge	163:e59c8e839560	1663	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
AnnaBridge	163:e59c8e839560	1664	* @{
AnnaBridge	163:e59c8e839560	1665	*/
AnnaBridge	163:e59c8e839560	1666	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
AnnaBridge	163:e59c8e839560	1667	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
AnnaBridge	163:e59c8e839560	1668	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
AnnaBridge	163:e59c8e839560	1669	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
AnnaBridge	163:e59c8e839560	1670
AnnaBridge	163:e59c8e839560	1671	/**
AnnaBridge	163:e59c8e839560	1672	* @}
AnnaBridge	163:e59c8e839560	1673	*/
AnnaBridge	163:e59c8e839560	1674
AnnaBridge	163:e59c8e839560	1675	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
AnnaBridge	163:e59c8e839560	1676	* @{
AnnaBridge	163:e59c8e839560	1677	*/
AnnaBridge	163:e59c8e839560	1678	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
AnnaBridge	163:e59c8e839560	1679	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
AnnaBridge	163:e59c8e839560	1680
AnnaBridge	163:e59c8e839560	1681	/**
AnnaBridge	163:e59c8e839560	1682	* @}
AnnaBridge	163:e59c8e839560	1683	*/
AnnaBridge	163:e59c8e839560	1684
AnnaBridge	163:e59c8e839560	1685	/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
AnnaBridge	163:e59c8e839560	1686	* @{
AnnaBridge	163:e59c8e839560	1687	*/
AnnaBridge	163:e59c8e839560	1688
AnnaBridge	163:e59c8e839560	1689	/* ADC1 */
AnnaBridge	163:e59c8e839560	1690	#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
AnnaBridge	163:e59c8e839560	1691	#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
AnnaBridge	163:e59c8e839560	1692	#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
AnnaBridge	163:e59c8e839560	1693	#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
AnnaBridge	163:e59c8e839560	1694
AnnaBridge	163:e59c8e839560	1695	/**
AnnaBridge	163:e59c8e839560	1696	* @}
AnnaBridge	163:e59c8e839560	1697	*/
AnnaBridge	163:e59c8e839560	1698
AnnaBridge	163:e59c8e839560	1699	/** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
AnnaBridge	163:e59c8e839560	1700	* @{
AnnaBridge	163:e59c8e839560	1701	*/
AnnaBridge	163:e59c8e839560	1702	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
AnnaBridge	163:e59c8e839560	1703	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
AnnaBridge	163:e59c8e839560	1704
AnnaBridge	163:e59c8e839560	1705	/**
AnnaBridge	163:e59c8e839560	1706	* @}
AnnaBridge	163:e59c8e839560	1707	*/
AnnaBridge	163:e59c8e839560	1708
AnnaBridge	163:e59c8e839560	1709	/** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
AnnaBridge	163:e59c8e839560	1710	* @{
AnnaBridge	163:e59c8e839560	1711	*/
AnnaBridge	163:e59c8e839560	1712	#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1
AnnaBridge	163:e59c8e839560	1713	#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2
AnnaBridge	163:e59c8e839560	1714	#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4
AnnaBridge	163:e59c8e839560	1715	#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6
AnnaBridge	163:e59c8e839560	1716	#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8
AnnaBridge	163:e59c8e839560	1717	#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10
AnnaBridge	163:e59c8e839560	1718	#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12
AnnaBridge	163:e59c8e839560	1719	#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14
AnnaBridge	163:e59c8e839560	1720	#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16
AnnaBridge	163:e59c8e839560	1721	#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20
AnnaBridge	163:e59c8e839560	1722	#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24
AnnaBridge	163:e59c8e839560	1723	#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28
AnnaBridge	163:e59c8e839560	1724	#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32
AnnaBridge	163:e59c8e839560	1725	#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36
AnnaBridge	163:e59c8e839560	1726	#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40
AnnaBridge	163:e59c8e839560	1727	#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44
AnnaBridge	163:e59c8e839560	1728	#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48
AnnaBridge	163:e59c8e839560	1729
AnnaBridge	163:e59c8e839560	1730	/**
AnnaBridge	163:e59c8e839560	1731	* @}
AnnaBridge	163:e59c8e839560	1732	*/
AnnaBridge	163:e59c8e839560	1733
AnnaBridge	163:e59c8e839560	1734	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	1735
AnnaBridge	163:e59c8e839560	1736	#if defined(STM32F302xE) \|\| defined(STM32F303xE)\
AnnaBridge	163:e59c8e839560	1737	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC)\
AnnaBridge	163:e59c8e839560	1738	\|\| defined(STM32F302x8) \
AnnaBridge	163:e59c8e839560	1739	\|\| defined(STM32F373xC)
AnnaBridge	163:e59c8e839560	1740	/** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
AnnaBridge	163:e59c8e839560	1741	* @{
AnnaBridge	163:e59c8e839560	1742	*/
AnnaBridge	163:e59c8e839560	1743
AnnaBridge	163:e59c8e839560	1744	#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
AnnaBridge	163:e59c8e839560	1745	#define RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
AnnaBridge	163:e59c8e839560	1746
AnnaBridge	163:e59c8e839560	1747	/**
AnnaBridge	163:e59c8e839560	1748	* @}
AnnaBridge	163:e59c8e839560	1749	*/
AnnaBridge	163:e59c8e839560	1750
AnnaBridge	163:e59c8e839560	1751	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
AnnaBridge	163:e59c8e839560	1752	/* STM32F302xC \|\| STM32F303xC \|\| */
AnnaBridge	163:e59c8e839560	1753	/* STM32F302x8 \|\| */
AnnaBridge	163:e59c8e839560	1754	/* STM32F373xC */
AnnaBridge	163:e59c8e839560	1755
AnnaBridge	163:e59c8e839560	1756
AnnaBridge	163:e59c8e839560	1757	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
AnnaBridge	163:e59c8e839560	1758	* @{
AnnaBridge	163:e59c8e839560	1759	*/
AnnaBridge	163:e59c8e839560	1760	#if defined(RCC_CFGR_MCOPRE)
AnnaBridge	163:e59c8e839560	1761
AnnaBridge	163:e59c8e839560	1762	#define RCC_MCODIV_1 (0x00000000U)
AnnaBridge	163:e59c8e839560	1763	#define RCC_MCODIV_2 (0x10000000U)
AnnaBridge	163:e59c8e839560	1764	#define RCC_MCODIV_4 (0x20000000U)
AnnaBridge	163:e59c8e839560	1765	#define RCC_MCODIV_8 (0x30000000U)
AnnaBridge	163:e59c8e839560	1766	#define RCC_MCODIV_16 (0x40000000U)
AnnaBridge	163:e59c8e839560	1767	#define RCC_MCODIV_32 (0x50000000U)
AnnaBridge	163:e59c8e839560	1768	#define RCC_MCODIV_64 (0x60000000U)
AnnaBridge	163:e59c8e839560	1769	#define RCC_MCODIV_128 (0x70000000U)
AnnaBridge	163:e59c8e839560	1770
AnnaBridge	163:e59c8e839560	1771	#else
AnnaBridge	163:e59c8e839560	1772
AnnaBridge	163:e59c8e839560	1773	#define RCC_MCODIV_1 (0x00000000U)
AnnaBridge	163:e59c8e839560	1774
AnnaBridge	163:e59c8e839560	1775	#endif /* RCC_CFGR_MCOPRE */
AnnaBridge	163:e59c8e839560	1776
AnnaBridge	163:e59c8e839560	1777	/**
AnnaBridge	163:e59c8e839560	1778	* @}
AnnaBridge	163:e59c8e839560	1779	*/
AnnaBridge	163:e59c8e839560	1780
AnnaBridge	163:e59c8e839560	1781	/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
AnnaBridge	163:e59c8e839560	1782	* @{
AnnaBridge	163:e59c8e839560	1783	*/
AnnaBridge	163:e59c8e839560	1784
AnnaBridge	163:e59c8e839560	1785	#define RCC_LSEDRIVE_LOW (0x00000000U) /!< Xtal mode lower driving capability /
AnnaBridge	163:e59c8e839560	1786	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /!< Xtal mode medium low driving capability /
AnnaBridge	163:e59c8e839560	1787	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /!< Xtal mode medium high driving capability /
AnnaBridge	163:e59c8e839560	1788	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
AnnaBridge	163:e59c8e839560	1789
AnnaBridge	163:e59c8e839560	1790	/**
AnnaBridge	163:e59c8e839560	1791	* @}
AnnaBridge	163:e59c8e839560	1792	*/
AnnaBridge	163:e59c8e839560	1793
AnnaBridge	163:e59c8e839560	1794	/**
AnnaBridge	163:e59c8e839560	1795	* @}
AnnaBridge	163:e59c8e839560	1796	*/
AnnaBridge	163:e59c8e839560	1797
AnnaBridge	163:e59c8e839560	1798	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1799	/** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
AnnaBridge	163:e59c8e839560	1800	* @{
AnnaBridge	163:e59c8e839560	1801	*/
AnnaBridge	163:e59c8e839560	1802
AnnaBridge	163:e59c8e839560	1803	/** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
AnnaBridge	163:e59c8e839560	1804	* @{
AnnaBridge	163:e59c8e839560	1805	*/
AnnaBridge	163:e59c8e839560	1806	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	1807	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
AnnaBridge	163:e59c8e839560	1808	* @note This macro must be used only when the PLL is disabled.
AnnaBridge	163:e59c8e839560	1809	*
AnnaBridge	163:e59c8e839560	1810	* @param __RCC_PLLSource__ specifies the PLL entry clock source.
AnnaBridge	163:e59c8e839560	1811	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1812	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge	163:e59c8e839560	1813	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge	163:e59c8e839560	1814	* @param __PREDIV__ specifies the predivider factor for PLL VCO input clock
AnnaBridge	163:e59c8e839560	1815	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
AnnaBridge	163:e59c8e839560	1816	* @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
AnnaBridge	163:e59c8e839560	1817	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
AnnaBridge	163:e59c8e839560	1818	*
AnnaBridge	163:e59c8e839560	1819	*/
AnnaBridge	163:e59c8e839560	1820	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
AnnaBridge	163:e59c8e839560	1821	do { \
AnnaBridge	163:e59c8e839560	1822	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
AnnaBridge	163:e59c8e839560	1823	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__))); \
AnnaBridge	163:e59c8e839560	1824	} while(0U)
AnnaBridge	163:e59c8e839560	1825	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	1826
AnnaBridge	163:e59c8e839560	1827	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)\
AnnaBridge	163:e59c8e839560	1828	\|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)\
AnnaBridge	163:e59c8e839560	1829	\|\| defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)\
AnnaBridge	163:e59c8e839560	1830	\|\| defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	1831	/** @brief Macro to configure the PLL clock source and multiplication factor.
AnnaBridge	163:e59c8e839560	1832	* @note This macro must be used only when the PLL is disabled.
AnnaBridge	163:e59c8e839560	1833	*
AnnaBridge	163:e59c8e839560	1834	* @param __RCC_PLLSource__ specifies the PLL entry clock source.
AnnaBridge	163:e59c8e839560	1835	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1836	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge	163:e59c8e839560	1837	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge	163:e59c8e839560	1838	* @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
AnnaBridge	163:e59c8e839560	1839	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
AnnaBridge	163:e59c8e839560	1840	*
AnnaBridge	163:e59c8e839560	1841	*/
AnnaBridge	163:e59c8e839560	1842	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
AnnaBridge	163:e59c8e839560	1843	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__)))
AnnaBridge	163:e59c8e839560	1844	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
AnnaBridge	163:e59c8e839560	1845	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
AnnaBridge	163:e59c8e839560	1846	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	1847	/* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	1848	/**
AnnaBridge	163:e59c8e839560	1849	* @}
AnnaBridge	163:e59c8e839560	1850	*/
AnnaBridge	163:e59c8e839560	1851
AnnaBridge	163:e59c8e839560	1852	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)\
AnnaBridge	163:e59c8e839560	1853	\|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)\
AnnaBridge	163:e59c8e839560	1854	\|\| defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)\
AnnaBridge	163:e59c8e839560	1855	\|\| defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	1856	/** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
AnnaBridge	163:e59c8e839560	1857	* @{
AnnaBridge	163:e59c8e839560	1858	*/
AnnaBridge	163:e59c8e839560	1859
AnnaBridge	163:e59c8e839560	1860	/**
AnnaBridge	163:e59c8e839560	1861	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
AnnaBridge	163:e59c8e839560	1862	* @note Predivision factor can not be changed if PLL is used as system clock
AnnaBridge	163:e59c8e839560	1863	* In this case, you have to select another source of the system clock, disable the PLL and
AnnaBridge	163:e59c8e839560	1864	* then change the HSE predivision factor.
AnnaBridge	163:e59c8e839560	1865	* @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
AnnaBridge	163:e59c8e839560	1866	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
AnnaBridge	163:e59c8e839560	1867	*/
AnnaBridge	163:e59c8e839560	1868	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
AnnaBridge	163:e59c8e839560	1869	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
AnnaBridge	163:e59c8e839560	1870
AnnaBridge	163:e59c8e839560	1871	/**
AnnaBridge	163:e59c8e839560	1872	* @brief Macro to get prediv1 factor for PLL.
AnnaBridge	163:e59c8e839560	1873	*/
AnnaBridge	163:e59c8e839560	1874	#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)
AnnaBridge	163:e59c8e839560	1875
AnnaBridge	163:e59c8e839560	1876	/**
AnnaBridge	163:e59c8e839560	1877	* @}
AnnaBridge	163:e59c8e839560	1878	*/
AnnaBridge	163:e59c8e839560	1879	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
AnnaBridge	163:e59c8e839560	1880	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
AnnaBridge	163:e59c8e839560	1881	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	1882	/* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	1883
AnnaBridge	163:e59c8e839560	1884	/** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
AnnaBridge	163:e59c8e839560	1885	* @brief Enable or disable the AHB peripheral clock.
AnnaBridge	163:e59c8e839560	1886	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	1887	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	1888	* using it.
AnnaBridge	163:e59c8e839560	1889	* @{
AnnaBridge	163:e59c8e839560	1890	*/
AnnaBridge	163:e59c8e839560	1891	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	1892	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1893	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	1894	SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
AnnaBridge	163:e59c8e839560	1895	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1896	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
AnnaBridge	163:e59c8e839560	1897	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1898	} while(0U)
AnnaBridge	163:e59c8e839560	1899
AnnaBridge	163:e59c8e839560	1900	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
AnnaBridge	163:e59c8e839560	1901	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	1902
AnnaBridge	163:e59c8e839560	1903	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	1904	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	1905	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1906	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	1907	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge	163:e59c8e839560	1908	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1909	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge	163:e59c8e839560	1910	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1911	} while(0U)
AnnaBridge	163:e59c8e839560	1912	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1913	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	1914	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	1915	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1916	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	1917	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1918	} while(0U)
AnnaBridge	163:e59c8e839560	1919	#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1920	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	1921	SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
AnnaBridge	163:e59c8e839560	1922	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1923	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
AnnaBridge	163:e59c8e839560	1924	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1925	} while(0U)
AnnaBridge	163:e59c8e839560	1926	/* Aliases for STM32 F3 compatibility */
AnnaBridge	163:e59c8e839560	1927	#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
AnnaBridge	163:e59c8e839560	1928	#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
AnnaBridge	163:e59c8e839560	1929
AnnaBridge	163:e59c8e839560	1930	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
AnnaBridge	163:e59c8e839560	1931	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
AnnaBridge	163:e59c8e839560	1932	#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
AnnaBridge	163:e59c8e839560	1933	/* Aliases for STM32 F3 compatibility */
AnnaBridge	163:e59c8e839560	1934	#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
AnnaBridge	163:e59c8e839560	1935	#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
AnnaBridge	163:e59c8e839560	1936	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	1937	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	1938
AnnaBridge	163:e59c8e839560	1939	#if defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	1940	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	1941	#define __HAL_RCC_ADC34_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1942	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	1943	SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
AnnaBridge	163:e59c8e839560	1944	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1945	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
AnnaBridge	163:e59c8e839560	1946	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1947	} while(0U)
AnnaBridge	163:e59c8e839560	1948	#define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
AnnaBridge	163:e59c8e839560	1949	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	1950	/* STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	1951
AnnaBridge	163:e59c8e839560	1952	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	1953	#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1954	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	1955	SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
AnnaBridge	163:e59c8e839560	1956	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1957	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
AnnaBridge	163:e59c8e839560	1958	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1959	} while(0U)
AnnaBridge	163:e59c8e839560	1960	/* Aliases for STM32 F3 compatibility */
AnnaBridge	163:e59c8e839560	1961	#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
AnnaBridge	163:e59c8e839560	1962	#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
AnnaBridge	163:e59c8e839560	1963
AnnaBridge	163:e59c8e839560	1964	#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
AnnaBridge	163:e59c8e839560	1965	/* Aliases for STM32 F3 compatibility */
AnnaBridge	163:e59c8e839560	1966	#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
AnnaBridge	163:e59c8e839560	1967	#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
AnnaBridge	163:e59c8e839560	1968	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	1969
AnnaBridge	163:e59c8e839560	1970	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	1971	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1972	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	1973	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge	163:e59c8e839560	1974	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1975	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge	163:e59c8e839560	1976	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1977	} while(0U)
AnnaBridge	163:e59c8e839560	1978	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1979	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	1980	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	1981	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1982	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
AnnaBridge	163:e59c8e839560	1983	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1984	} while(0U)
AnnaBridge	163:e59c8e839560	1985
AnnaBridge	163:e59c8e839560	1986	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
AnnaBridge	163:e59c8e839560	1987	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
AnnaBridge	163:e59c8e839560	1988	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	1989
AnnaBridge	163:e59c8e839560	1990	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	1991	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1992	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	1993	SET_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
AnnaBridge	163:e59c8e839560	1994	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	1995	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
AnnaBridge	163:e59c8e839560	1996	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	1997	} while(0U)
AnnaBridge	163:e59c8e839560	1998	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	1999	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2000	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
AnnaBridge	163:e59c8e839560	2001	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2002	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
AnnaBridge	163:e59c8e839560	2003	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2004	} while(0U)
AnnaBridge	163:e59c8e839560	2005	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2006	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2007	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
AnnaBridge	163:e59c8e839560	2008	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2009	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
AnnaBridge	163:e59c8e839560	2010	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2011	} while(0U)
AnnaBridge	163:e59c8e839560	2012
AnnaBridge	163:e59c8e839560	2013	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
AnnaBridge	163:e59c8e839560	2014	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
AnnaBridge	163:e59c8e839560	2015	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
AnnaBridge	163:e59c8e839560	2016	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2017	/**
AnnaBridge	163:e59c8e839560	2018	* @}
AnnaBridge	163:e59c8e839560	2019	*/
AnnaBridge	163:e59c8e839560	2020
AnnaBridge	163:e59c8e839560	2021	/** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
AnnaBridge	163:e59c8e839560	2022	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	163:e59c8e839560	2023	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2024	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2025	* using it.
AnnaBridge	163:e59c8e839560	2026	* @{
AnnaBridge	163:e59c8e839560	2027	*/
AnnaBridge	163:e59c8e839560	2028	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	2029	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2030	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2031	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	163:e59c8e839560	2032	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2033	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	163:e59c8e839560	2034	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2035	} while(0U)
AnnaBridge	163:e59c8e839560	2036	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2037	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2038	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	2039	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2040	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	2041	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2042	} while(0U)
AnnaBridge	163:e59c8e839560	2043	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2044	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2045	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	163:e59c8e839560	2046	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2047	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	163:e59c8e839560	2048	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2049	} while(0U)
AnnaBridge	163:e59c8e839560	2050	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2051	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2052	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	2053	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2054	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	2055	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2056	} while(0U)
AnnaBridge	163:e59c8e839560	2057
AnnaBridge	163:e59c8e839560	2058	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge	163:e59c8e839560	2059	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	163:e59c8e839560	2060	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge	163:e59c8e839560	2061	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	163:e59c8e839560	2062	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	2063
AnnaBridge	163:e59c8e839560	2064	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2065	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2066	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2067	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2068	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	2069	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2070	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	2071	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2072	} while(0U)
AnnaBridge	163:e59c8e839560	2073	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2074	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2075	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	2076	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2077	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	2078	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2079	} while(0U)
AnnaBridge	163:e59c8e839560	2080	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2081	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2082	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	163:e59c8e839560	2083	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2084	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	163:e59c8e839560	2085	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2086	} while(0U)
AnnaBridge	163:e59c8e839560	2087	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2088	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2089	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	2090	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2091	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	2092	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2093	} while(0U)
AnnaBridge	163:e59c8e839560	2094	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2095	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2096	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	163:e59c8e839560	2097	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2098	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	163:e59c8e839560	2099	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2100	} while(0U)
AnnaBridge	163:e59c8e839560	2101	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2102	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2103	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	163:e59c8e839560	2104	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2105	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	163:e59c8e839560	2106	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2107	} while(0U)
AnnaBridge	163:e59c8e839560	2108	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2109	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2110	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	163:e59c8e839560	2111	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2112	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	163:e59c8e839560	2113	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2114	} while(0U)
AnnaBridge	163:e59c8e839560	2115
AnnaBridge	163:e59c8e839560	2116	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	163:e59c8e839560	2117	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	163:e59c8e839560	2118	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge	163:e59c8e839560	2119	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	163:e59c8e839560	2120	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	163:e59c8e839560	2121	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	163:e59c8e839560	2122	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge	163:e59c8e839560	2123	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2124	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2125
AnnaBridge	163:e59c8e839560	2126	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	2127	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2128	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2129	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	2130	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2131	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	2132	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2133	} while(0U)
AnnaBridge	163:e59c8e839560	2134	#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2135	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2136	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
AnnaBridge	163:e59c8e839560	2137	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2138	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
AnnaBridge	163:e59c8e839560	2139	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2140	} while(0U)
AnnaBridge	163:e59c8e839560	2141
AnnaBridge	163:e59c8e839560	2142	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	163:e59c8e839560	2143	#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
AnnaBridge	163:e59c8e839560	2144	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	2145
AnnaBridge	163:e59c8e839560	2146	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	2147	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2148	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2149	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	2150	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2151	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	163:e59c8e839560	2152	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2153	} while(0U)
AnnaBridge	163:e59c8e839560	2154	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2155	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2156	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	2157	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2158	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	163:e59c8e839560	2159	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2160	} while(0U)
AnnaBridge	163:e59c8e839560	2161	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2162	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2163	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge	163:e59c8e839560	2164	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2165	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge	163:e59c8e839560	2166	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2167	} while(0U)
AnnaBridge	163:e59c8e839560	2168	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2169	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2170	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	163:e59c8e839560	2171	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2172	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	163:e59c8e839560	2173	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2174	} while(0U)
AnnaBridge	163:e59c8e839560	2175	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2176	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2177	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	163:e59c8e839560	2178	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2179	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	163:e59c8e839560	2180	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2181	} while(0U)
AnnaBridge	163:e59c8e839560	2182	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2183	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2184	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	2185	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2186	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	163:e59c8e839560	2187	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2188	} while(0U)
AnnaBridge	163:e59c8e839560	2189	#define __HAL_RCC_TIM18_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2190	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2191	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
AnnaBridge	163:e59c8e839560	2192	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2193	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
AnnaBridge	163:e59c8e839560	2194	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2195	} while(0U)
AnnaBridge	163:e59c8e839560	2196	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2197	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2198	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	163:e59c8e839560	2199	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2200	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	163:e59c8e839560	2201	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2202	} while(0U)
AnnaBridge	163:e59c8e839560	2203	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2204	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2205	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	2206	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2207	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	163:e59c8e839560	2208	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2209	} while(0U)
AnnaBridge	163:e59c8e839560	2210	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2211	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2212	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	163:e59c8e839560	2213	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2214	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	163:e59c8e839560	2215	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2216	} while(0U)
AnnaBridge	163:e59c8e839560	2217	#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2218	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2219	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
AnnaBridge	163:e59c8e839560	2220	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2221	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
AnnaBridge	163:e59c8e839560	2222	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2223	} while(0U)
AnnaBridge	163:e59c8e839560	2224	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2225	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2226	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	163:e59c8e839560	2227	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2228	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	163:e59c8e839560	2229	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2230	} while(0U)
AnnaBridge	163:e59c8e839560	2231
AnnaBridge	163:e59c8e839560	2232	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	163:e59c8e839560	2233	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	163:e59c8e839560	2234	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
AnnaBridge	163:e59c8e839560	2235	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	163:e59c8e839560	2236	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	163:e59c8e839560	2237	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	163:e59c8e839560	2238	#define __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
AnnaBridge	163:e59c8e839560	2239	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge	163:e59c8e839560	2240	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	163:e59c8e839560	2241	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge	163:e59c8e839560	2242	#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
AnnaBridge	163:e59c8e839560	2243	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
AnnaBridge	163:e59c8e839560	2244	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	2245
AnnaBridge	163:e59c8e839560	2246	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \
AnnaBridge	163:e59c8e839560	2247	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \
AnnaBridge	163:e59c8e839560	2248	\|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)\
AnnaBridge	163:e59c8e839560	2249	\|\| defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	2250	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2251	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2252	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	163:e59c8e839560	2253	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2254	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	163:e59c8e839560	2255	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2256	} while(0U)
AnnaBridge	163:e59c8e839560	2257
AnnaBridge	163:e59c8e839560	2258	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	163:e59c8e839560	2259	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2260	/* STM32F303xC \|\| STM32F358xx \|\| */
AnnaBridge	163:e59c8e839560	2261	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
AnnaBridge	163:e59c8e839560	2262	/* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	2263
AnnaBridge	163:e59c8e839560	2264	#if defined(STM32F302xE) \|\| defined(STM32F303xE)\
AnnaBridge	163:e59c8e839560	2265	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC)\
AnnaBridge	163:e59c8e839560	2266	\|\| defined(STM32F302x8) \
AnnaBridge	163:e59c8e839560	2267	\|\| defined(STM32F373xC)
AnnaBridge	163:e59c8e839560	2268	#define __HAL_RCC_USB_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2269	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2270	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
AnnaBridge	163:e59c8e839560	2271	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2272	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
AnnaBridge	163:e59c8e839560	2273	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2274	} while(0U)
AnnaBridge	163:e59c8e839560	2275
AnnaBridge	163:e59c8e839560	2276	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
AnnaBridge	163:e59c8e839560	2277	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
AnnaBridge	163:e59c8e839560	2278	/* STM32F302xC \|\| STM32F303xC \|\| */
AnnaBridge	163:e59c8e839560	2279	/* STM32F302x8 \|\| */
AnnaBridge	163:e59c8e839560	2280	/* STM32F373xC */
AnnaBridge	163:e59c8e839560	2281
AnnaBridge	163:e59c8e839560	2282	#if !defined(STM32F301x8)
AnnaBridge	163:e59c8e839560	2283	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2284	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2285	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
AnnaBridge	163:e59c8e839560	2286	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2287	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
AnnaBridge	163:e59c8e839560	2288	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2289	} while(0U)
AnnaBridge	163:e59c8e839560	2290
AnnaBridge	163:e59c8e839560	2291	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
AnnaBridge	163:e59c8e839560	2292	#endif /* STM32F301x8*/
AnnaBridge	163:e59c8e839560	2293
AnnaBridge	163:e59c8e839560	2294	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	2295	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2296	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2297	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	2298	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2299	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	163:e59c8e839560	2300	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2301	} while(0U)
AnnaBridge	163:e59c8e839560	2302
AnnaBridge	163:e59c8e839560	2303	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	163:e59c8e839560	2304	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2305	/**
AnnaBridge	163:e59c8e839560	2306	* @}
AnnaBridge	163:e59c8e839560	2307	*/
AnnaBridge	163:e59c8e839560	2308
AnnaBridge	163:e59c8e839560	2309	/** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
AnnaBridge	163:e59c8e839560	2310	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	163:e59c8e839560	2311	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2312	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2313	* using it.
AnnaBridge	163:e59c8e839560	2314	* @{
AnnaBridge	163:e59c8e839560	2315	*/
AnnaBridge	163:e59c8e839560	2316	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2317	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2318	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2319	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2320	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	163:e59c8e839560	2321	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2322	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	163:e59c8e839560	2323	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2324	} while(0U)
AnnaBridge	163:e59c8e839560	2325
AnnaBridge	163:e59c8e839560	2326	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge	163:e59c8e839560	2327	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2328	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2329
AnnaBridge	163:e59c8e839560	2330	#if defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2331	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2332	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2333	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2334	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	163:e59c8e839560	2335	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2336	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	163:e59c8e839560	2337	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2338	} while(0U)
AnnaBridge	163:e59c8e839560	2339
AnnaBridge	163:e59c8e839560	2340	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	163:e59c8e839560	2341	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2342	/* STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2343
AnnaBridge	163:e59c8e839560	2344	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	2345	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2346	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2347	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	163:e59c8e839560	2348	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2349	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	163:e59c8e839560	2350	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2351	} while(0U)
AnnaBridge	163:e59c8e839560	2352
AnnaBridge	163:e59c8e839560	2353	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge	163:e59c8e839560	2354	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	2355
AnnaBridge	163:e59c8e839560	2356	#if defined(STM32F334x8)
AnnaBridge	163:e59c8e839560	2357	#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2358	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2359	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
AnnaBridge	163:e59c8e839560	2360	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2361	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
AnnaBridge	163:e59c8e839560	2362	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2363	} while(0U)
AnnaBridge	163:e59c8e839560	2364
AnnaBridge	163:e59c8e839560	2365	#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
AnnaBridge	163:e59c8e839560	2366	#endif /* STM32F334x8 */
AnnaBridge	163:e59c8e839560	2367
AnnaBridge	163:e59c8e839560	2368	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	2369	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2370	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2371	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge	163:e59c8e839560	2372	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2373	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge	163:e59c8e839560	2374	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2375	} while(0U)
AnnaBridge	163:e59c8e839560	2376	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2377	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2378	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	163:e59c8e839560	2379	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2380	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	163:e59c8e839560	2381	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2382	} while(0U)
AnnaBridge	163:e59c8e839560	2383	#define __HAL_RCC_TIM19_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2384	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2385	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
AnnaBridge	163:e59c8e839560	2386	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2387	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
AnnaBridge	163:e59c8e839560	2388	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2389	} while(0U)
AnnaBridge	163:e59c8e839560	2390	#define __HAL_RCC_SDADC1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2391	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2392	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
AnnaBridge	163:e59c8e839560	2393	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2394	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
AnnaBridge	163:e59c8e839560	2395	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2396	} while(0U)
AnnaBridge	163:e59c8e839560	2397	#define __HAL_RCC_SDADC2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2398	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2399	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
AnnaBridge	163:e59c8e839560	2400	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2401	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
AnnaBridge	163:e59c8e839560	2402	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2403	} while(0U)
AnnaBridge	163:e59c8e839560	2404	#define __HAL_RCC_SDADC3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2405	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2406	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
AnnaBridge	163:e59c8e839560	2407	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2408	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
AnnaBridge	163:e59c8e839560	2409	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2410	} while(0U)
AnnaBridge	163:e59c8e839560	2411
AnnaBridge	163:e59c8e839560	2412	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
AnnaBridge	163:e59c8e839560	2413	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge	163:e59c8e839560	2414	#define __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
AnnaBridge	163:e59c8e839560	2415	#define __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
AnnaBridge	163:e59c8e839560	2416	#define __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
AnnaBridge	163:e59c8e839560	2417	#define __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
AnnaBridge	163:e59c8e839560	2418	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	2419
AnnaBridge	163:e59c8e839560	2420	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2421	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)\
AnnaBridge	163:e59c8e839560	2422	\|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)\
AnnaBridge	163:e59c8e839560	2423	\|\| defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	2424	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2425	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2426	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge	163:e59c8e839560	2427	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2428	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge	163:e59c8e839560	2429	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2430	} while(0U)
AnnaBridge	163:e59c8e839560	2431
AnnaBridge	163:e59c8e839560	2432	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
AnnaBridge	163:e59c8e839560	2433	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2434	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
AnnaBridge	163:e59c8e839560	2435	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
AnnaBridge	163:e59c8e839560	2436	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	2437
AnnaBridge	163:e59c8e839560	2438	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	2439	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2440	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2441	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	2442	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2443	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	163:e59c8e839560	2444	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2445	} while(0U)
AnnaBridge	163:e59c8e839560	2446
AnnaBridge	163:e59c8e839560	2447	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	163:e59c8e839560	2448	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2449
AnnaBridge	163:e59c8e839560	2450	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	2451	#define __HAL_RCC_TIM20_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	2452	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	2453	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
AnnaBridge	163:e59c8e839560	2454	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	2455	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
AnnaBridge	163:e59c8e839560	2456	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	2457	} while(0U)
AnnaBridge	163:e59c8e839560	2458	#define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
AnnaBridge	163:e59c8e839560	2459	#endif /* STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2460
AnnaBridge	163:e59c8e839560	2461	/**
AnnaBridge	163:e59c8e839560	2462	* @}
AnnaBridge	163:e59c8e839560	2463	*/
AnnaBridge	163:e59c8e839560	2464
AnnaBridge	163:e59c8e839560	2465	/** @defgroup RCCEx_AHB_Peripheral_Clock_Enable_Disable_Status RCC Extended AHB Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	2466	* @brief Get the enable or disable status of the AHB peripheral clock.
AnnaBridge	163:e59c8e839560	2467	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2468	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2469	* using it.
AnnaBridge	163:e59c8e839560	2470	* @{
AnnaBridge	163:e59c8e839560	2471	*/
AnnaBridge	163:e59c8e839560	2472	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	2473	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET)
AnnaBridge	163:e59c8e839560	2474
AnnaBridge	163:e59c8e839560	2475	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) == RESET)
AnnaBridge	163:e59c8e839560	2476	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	2477
AnnaBridge	163:e59c8e839560	2478	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2479	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2480	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2481	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
AnnaBridge	163:e59c8e839560	2482	#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
AnnaBridge	163:e59c8e839560	2483
AnnaBridge	163:e59c8e839560	2484	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2485	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
AnnaBridge	163:e59c8e839560	2486	#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
AnnaBridge	163:e59c8e839560	2487	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2488	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2489
AnnaBridge	163:e59c8e839560	2490	#if defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2491	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2492	#define __HAL_RCC_ADC34_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) != RESET)
AnnaBridge	163:e59c8e839560	2493
AnnaBridge	163:e59c8e839560	2494	#define __HAL_RCC_ADC34_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) == RESET)
AnnaBridge	163:e59c8e839560	2495	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2496	/* STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2497
AnnaBridge	163:e59c8e839560	2498	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	2499	#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
AnnaBridge	163:e59c8e839560	2500
AnnaBridge	163:e59c8e839560	2501	#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
AnnaBridge	163:e59c8e839560	2502	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	2503
AnnaBridge	163:e59c8e839560	2504	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	2505	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2506	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
AnnaBridge	163:e59c8e839560	2507
AnnaBridge	163:e59c8e839560	2508	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2509	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
AnnaBridge	163:e59c8e839560	2510	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	2511
AnnaBridge	163:e59c8e839560	2512	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	2513	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) != RESET)
AnnaBridge	163:e59c8e839560	2514	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET)
AnnaBridge	163:e59c8e839560	2515	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET)
AnnaBridge	163:e59c8e839560	2516
AnnaBridge	163:e59c8e839560	2517	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) == RESET)
AnnaBridge	163:e59c8e839560	2518	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET)
AnnaBridge	163:e59c8e839560	2519	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET)
AnnaBridge	163:e59c8e839560	2520	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2521	/**
AnnaBridge	163:e59c8e839560	2522	* @}
AnnaBridge	163:e59c8e839560	2523	*/
AnnaBridge	163:e59c8e839560	2524
AnnaBridge	163:e59c8e839560	2525	/** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status RCC Extended APB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	2526	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	163:e59c8e839560	2527	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2528	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2529	* using it.
AnnaBridge	163:e59c8e839560	2530	* @{
AnnaBridge	163:e59c8e839560	2531	*/
AnnaBridge	163:e59c8e839560	2532	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	2533	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2534	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2535	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2536	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2537
AnnaBridge	163:e59c8e839560	2538	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2539	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2540	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2541	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2542	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	2543
AnnaBridge	163:e59c8e839560	2544	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2545	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2546	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2547	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	163:e59c8e839560	2548	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2549	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2550	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	163:e59c8e839560	2551	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	163:e59c8e839560	2552	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2553
AnnaBridge	163:e59c8e839560	2554	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2555	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	163:e59c8e839560	2556	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2557	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2558	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	163:e59c8e839560	2559	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	163:e59c8e839560	2560	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2561	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2562	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2563
AnnaBridge	163:e59c8e839560	2564	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	2565	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2566	#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2567
AnnaBridge	163:e59c8e839560	2568	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2569	#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2570	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	2571
AnnaBridge	163:e59c8e839560	2572	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	2573	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2574	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	163:e59c8e839560	2575	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
AnnaBridge	163:e59c8e839560	2576	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	163:e59c8e839560	2577	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	163:e59c8e839560	2578	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	163:e59c8e839560	2579	#define __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET)
AnnaBridge	163:e59c8e839560	2580	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2581	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2582	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2583	#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2584	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
AnnaBridge	163:e59c8e839560	2585
AnnaBridge	163:e59c8e839560	2586	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2587	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	163:e59c8e839560	2588	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
AnnaBridge	163:e59c8e839560	2589	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	163:e59c8e839560	2590	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	163:e59c8e839560	2591	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	163:e59c8e839560	2592	#define __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET)
AnnaBridge	163:e59c8e839560	2593	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2594	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2595	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2596	#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2597	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
AnnaBridge	163:e59c8e839560	2598	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	2599
AnnaBridge	163:e59c8e839560	2600	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \
AnnaBridge	163:e59c8e839560	2601	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \
AnnaBridge	163:e59c8e839560	2602	\|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)\
AnnaBridge	163:e59c8e839560	2603	\|\| defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	2604	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	163:e59c8e839560	2605
AnnaBridge	163:e59c8e839560	2606	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	163:e59c8e839560	2607	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2608	/* STM32F303xC \|\| STM32F358xx \|\| */
AnnaBridge	163:e59c8e839560	2609	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
AnnaBridge	163:e59c8e839560	2610	/* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	2611
AnnaBridge	163:e59c8e839560	2612	#if defined(STM32F302xE) \|\| defined(STM32F303xE)\
AnnaBridge	163:e59c8e839560	2613	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC)\
AnnaBridge	163:e59c8e839560	2614	\|\| defined(STM32F302x8) \
AnnaBridge	163:e59c8e839560	2615	\|\| defined(STM32F373xC)
AnnaBridge	163:e59c8e839560	2616	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
AnnaBridge	163:e59c8e839560	2617
AnnaBridge	163:e59c8e839560	2618	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
AnnaBridge	163:e59c8e839560	2619	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
AnnaBridge	163:e59c8e839560	2620	/* STM32F302xC \|\| STM32F303xC \|\| */
AnnaBridge	163:e59c8e839560	2621	/* STM32F302x8 \|\| */
AnnaBridge	163:e59c8e839560	2622	/* STM32F373xC */
AnnaBridge	163:e59c8e839560	2623
AnnaBridge	163:e59c8e839560	2624	#if !defined(STM32F301x8)
AnnaBridge	163:e59c8e839560	2625	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET)
AnnaBridge	163:e59c8e839560	2626
AnnaBridge	163:e59c8e839560	2627	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET)
AnnaBridge	163:e59c8e839560	2628	#endif /* STM32F301x8*/
AnnaBridge	163:e59c8e839560	2629
AnnaBridge	163:e59c8e839560	2630	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	2631	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2632
AnnaBridge	163:e59c8e839560	2633	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2634	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2635	/**
AnnaBridge	163:e59c8e839560	2636	* @}
AnnaBridge	163:e59c8e839560	2637	*/
AnnaBridge	163:e59c8e839560	2638
AnnaBridge	163:e59c8e839560	2639	/** @defgroup RCCEx_APB2_Clock_Enable_Disable_Status RCC Extended APB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	2640	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	163:e59c8e839560	2641	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	2642	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	2643	* using it.
AnnaBridge	163:e59c8e839560	2644	* @{
AnnaBridge	163:e59c8e839560	2645	*/
AnnaBridge	163:e59c8e839560	2646	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2647	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2648	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge	163:e59c8e839560	2649
AnnaBridge	163:e59c8e839560	2650	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge	163:e59c8e839560	2651	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2652	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2653
AnnaBridge	163:e59c8e839560	2654	#if defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2655	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2656	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	163:e59c8e839560	2657
AnnaBridge	163:e59c8e839560	2658	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	163:e59c8e839560	2659	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2660	/* STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2661
AnnaBridge	163:e59c8e839560	2662	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	2663	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge	163:e59c8e839560	2664
AnnaBridge	163:e59c8e839560	2665	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge	163:e59c8e839560	2666	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	2667
AnnaBridge	163:e59c8e839560	2668	#if defined(STM32F334x8)
AnnaBridge	163:e59c8e839560	2669	#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) != RESET)
AnnaBridge	163:e59c8e839560	2670
AnnaBridge	163:e59c8e839560	2671	#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) == RESET)
AnnaBridge	163:e59c8e839560	2672	#endif /* STM32F334x8 */
AnnaBridge	163:e59c8e839560	2673
AnnaBridge	163:e59c8e839560	2674	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	2675	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
AnnaBridge	163:e59c8e839560	2676	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge	163:e59c8e839560	2677	#define __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET)
AnnaBridge	163:e59c8e839560	2678	#define __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET)
AnnaBridge	163:e59c8e839560	2679	#define __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET)
AnnaBridge	163:e59c8e839560	2680	#define __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET)
AnnaBridge	163:e59c8e839560	2681
AnnaBridge	163:e59c8e839560	2682	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
AnnaBridge	163:e59c8e839560	2683	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge	163:e59c8e839560	2684	#define __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET)
AnnaBridge	163:e59c8e839560	2685	#define __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET)
AnnaBridge	163:e59c8e839560	2686	#define __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET)
AnnaBridge	163:e59c8e839560	2687	#define __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET)
AnnaBridge	163:e59c8e839560	2688	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	2689
AnnaBridge	163:e59c8e839560	2690	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2691	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)\
AnnaBridge	163:e59c8e839560	2692	\|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)\
AnnaBridge	163:e59c8e839560	2693	\|\| defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	2694	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
AnnaBridge	163:e59c8e839560	2695
AnnaBridge	163:e59c8e839560	2696	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
AnnaBridge	163:e59c8e839560	2697	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2698	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
AnnaBridge	163:e59c8e839560	2699	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
AnnaBridge	163:e59c8e839560	2700	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	2701
AnnaBridge	163:e59c8e839560	2702	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	2703	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	163:e59c8e839560	2704
AnnaBridge	163:e59c8e839560	2705	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	163:e59c8e839560	2706	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2707
AnnaBridge	163:e59c8e839560	2708	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	2709	#define __HAL_RCC_TIM20_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET)
AnnaBridge	163:e59c8e839560	2710
AnnaBridge	163:e59c8e839560	2711	#define __HAL_RCC_TIM20_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) == RESET)
AnnaBridge	163:e59c8e839560	2712	#endif /* STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2713	/**
AnnaBridge	163:e59c8e839560	2714	* @}
AnnaBridge	163:e59c8e839560	2715	*/
AnnaBridge	163:e59c8e839560	2716
AnnaBridge	163:e59c8e839560	2717	/** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
AnnaBridge	163:e59c8e839560	2718	* @brief Force or release AHB peripheral reset.
AnnaBridge	163:e59c8e839560	2719	* @{
AnnaBridge	163:e59c8e839560	2720	*/
AnnaBridge	163:e59c8e839560	2721	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	2722	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC1RST))
AnnaBridge	163:e59c8e839560	2723
AnnaBridge	163:e59c8e839560	2724	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
AnnaBridge	163:e59c8e839560	2725	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	2726
AnnaBridge	163:e59c8e839560	2727	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2728	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2729	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	2730	#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
AnnaBridge	163:e59c8e839560	2731	/* Aliases for STM32 F3 compatibility */
AnnaBridge	163:e59c8e839560	2732	#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
AnnaBridge	163:e59c8e839560	2733	#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
AnnaBridge	163:e59c8e839560	2734
AnnaBridge	163:e59c8e839560	2735	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	2736	#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
AnnaBridge	163:e59c8e839560	2737	/* Aliases for STM32 F3 compatibility */
AnnaBridge	163:e59c8e839560	2738	#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
AnnaBridge	163:e59c8e839560	2739	#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
AnnaBridge	163:e59c8e839560	2740	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2741	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2742
AnnaBridge	163:e59c8e839560	2743	#if defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2744	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2745	#define __HAL_RCC_ADC34_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC34RST))
AnnaBridge	163:e59c8e839560	2746
AnnaBridge	163:e59c8e839560	2747	#define __HAL_RCC_ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
AnnaBridge	163:e59c8e839560	2748	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2749	/* STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2750
AnnaBridge	163:e59c8e839560	2751	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	2752	#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
AnnaBridge	163:e59c8e839560	2753	/* Aliases for STM32 F3 compatibility */
AnnaBridge	163:e59c8e839560	2754	#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
AnnaBridge	163:e59c8e839560	2755	#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
AnnaBridge	163:e59c8e839560	2756
AnnaBridge	163:e59c8e839560	2757	#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
AnnaBridge	163:e59c8e839560	2758	/* Aliases for STM32 F3 compatibility */
AnnaBridge	163:e59c8e839560	2759	#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
AnnaBridge	163:e59c8e839560	2760	#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
AnnaBridge	163:e59c8e839560	2761	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	2762
AnnaBridge	163:e59c8e839560	2763	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	2764	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	2765
AnnaBridge	163:e59c8e839560	2766	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
AnnaBridge	163:e59c8e839560	2767	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	2768
AnnaBridge	163:e59c8e839560	2769	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	2770	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_FMCRST))
AnnaBridge	163:e59c8e839560	2771	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOGRST))
AnnaBridge	163:e59c8e839560	2772	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOHRST))
AnnaBridge	163:e59c8e839560	2773
AnnaBridge	163:e59c8e839560	2774	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
AnnaBridge	163:e59c8e839560	2775	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
AnnaBridge	163:e59c8e839560	2776	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
AnnaBridge	163:e59c8e839560	2777	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2778	/**
AnnaBridge	163:e59c8e839560	2779	* @}
AnnaBridge	163:e59c8e839560	2780	*/
AnnaBridge	163:e59c8e839560	2781
AnnaBridge	163:e59c8e839560	2782	/** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
AnnaBridge	163:e59c8e839560	2783	* @brief Force or release APB1 peripheral reset.
AnnaBridge	163:e59c8e839560	2784	* @{
AnnaBridge	163:e59c8e839560	2785	*/
AnnaBridge	163:e59c8e839560	2786	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	2787	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
AnnaBridge	163:e59c8e839560	2788	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	2789	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
AnnaBridge	163:e59c8e839560	2790	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	2791
AnnaBridge	163:e59c8e839560	2792	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge	163:e59c8e839560	2793	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	2794	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge	163:e59c8e839560	2795	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	2796	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	2797
AnnaBridge	163:e59c8e839560	2798	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2799	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2800	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	2801	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	2802	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
AnnaBridge	163:e59c8e839560	2803	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	2804	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	163:e59c8e839560	2805	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	163:e59c8e839560	2806	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
AnnaBridge	163:e59c8e839560	2807
AnnaBridge	163:e59c8e839560	2808	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	2809	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	2810	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge	163:e59c8e839560	2811	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	2812	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	163:e59c8e839560	2813	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	163:e59c8e839560	2814	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge	163:e59c8e839560	2815	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2816	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2817
AnnaBridge	163:e59c8e839560	2818	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	2819	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	2820	#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
AnnaBridge	163:e59c8e839560	2821
AnnaBridge	163:e59c8e839560	2822	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	2823	#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
AnnaBridge	163:e59c8e839560	2824	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	2825
AnnaBridge	163:e59c8e839560	2826	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	2827	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	2828	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	2829	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
AnnaBridge	163:e59c8e839560	2830	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	163:e59c8e839560	2831	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	163:e59c8e839560	2832	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	163:e59c8e839560	2833	#define __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM18RST))
AnnaBridge	163:e59c8e839560	2834	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
AnnaBridge	163:e59c8e839560	2835	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	2836	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
AnnaBridge	163:e59c8e839560	2837	#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
AnnaBridge	163:e59c8e839560	2838	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
AnnaBridge	163:e59c8e839560	2839
AnnaBridge	163:e59c8e839560	2840	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	163:e59c8e839560	2841	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	163:e59c8e839560	2842	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
AnnaBridge	163:e59c8e839560	2843	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	163:e59c8e839560	2844	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	163:e59c8e839560	2845	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	163:e59c8e839560	2846	#define __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
AnnaBridge	163:e59c8e839560	2847	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge	163:e59c8e839560	2848	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	163:e59c8e839560	2849	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge	163:e59c8e839560	2850	#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
AnnaBridge	163:e59c8e839560	2851	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
AnnaBridge	163:e59c8e839560	2852	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	2853
AnnaBridge	163:e59c8e839560	2854	#if defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2855	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx)\
AnnaBridge	163:e59c8e839560	2856	\|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)\
AnnaBridge	163:e59c8e839560	2857	\|\| defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	2858	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	163:e59c8e839560	2859
AnnaBridge	163:e59c8e839560	2860	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	163:e59c8e839560	2861	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2862	/* STM32F303xC \|\| STM32F358xx \|\| */
AnnaBridge	163:e59c8e839560	2863	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
AnnaBridge	163:e59c8e839560	2864	/* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	2865
AnnaBridge	163:e59c8e839560	2866	#if defined(STM32F302xE) \|\| defined(STM32F303xE)\
AnnaBridge	163:e59c8e839560	2867	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC)\
AnnaBridge	163:e59c8e839560	2868	\|\| defined(STM32F302x8) \
AnnaBridge	163:e59c8e839560	2869	\|\| defined(STM32F373xC)
AnnaBridge	163:e59c8e839560	2870	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
AnnaBridge	163:e59c8e839560	2871
AnnaBridge	163:e59c8e839560	2872	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
AnnaBridge	163:e59c8e839560	2873	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
AnnaBridge	163:e59c8e839560	2874	/* STM32F302xC \|\| STM32F303xC \|\| */
AnnaBridge	163:e59c8e839560	2875	/* STM32F302x8 \|\| */
AnnaBridge	163:e59c8e839560	2876	/* STM32F373xC */
AnnaBridge	163:e59c8e839560	2877
AnnaBridge	163:e59c8e839560	2878	#if !defined(STM32F301x8)
AnnaBridge	163:e59c8e839560	2879	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
AnnaBridge	163:e59c8e839560	2880
AnnaBridge	163:e59c8e839560	2881	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
AnnaBridge	163:e59c8e839560	2882	#endif /* STM32F301x8*/
AnnaBridge	163:e59c8e839560	2883
AnnaBridge	163:e59c8e839560	2884	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	2885	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	2886
AnnaBridge	163:e59c8e839560	2887	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	163:e59c8e839560	2888	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2889	/**
AnnaBridge	163:e59c8e839560	2890	* @}
AnnaBridge	163:e59c8e839560	2891	*/
AnnaBridge	163:e59c8e839560	2892
AnnaBridge	163:e59c8e839560	2893	/** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
AnnaBridge	163:e59c8e839560	2894	* @brief Force or release APB2 peripheral reset.
AnnaBridge	163:e59c8e839560	2895	* @{
AnnaBridge	163:e59c8e839560	2896	*/
AnnaBridge	163:e59c8e839560	2897	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2898	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2899	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
AnnaBridge	163:e59c8e839560	2900
AnnaBridge	163:e59c8e839560	2901	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge	163:e59c8e839560	2902	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2903	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2904
AnnaBridge	163:e59c8e839560	2905	#if defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2906	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	2907	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	163:e59c8e839560	2908
AnnaBridge	163:e59c8e839560	2909	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	163:e59c8e839560	2910	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2911	/* STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	2912
AnnaBridge	163:e59c8e839560	2913	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	2914	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
AnnaBridge	163:e59c8e839560	2915
AnnaBridge	163:e59c8e839560	2916	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge	163:e59c8e839560	2917	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	2918
AnnaBridge	163:e59c8e839560	2919	#if defined(STM32F334x8)
AnnaBridge	163:e59c8e839560	2920	#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_HRTIM1RST))
AnnaBridge	163:e59c8e839560	2921
AnnaBridge	163:e59c8e839560	2922	#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
AnnaBridge	163:e59c8e839560	2923	#endif /* STM32F334x8 */
AnnaBridge	163:e59c8e839560	2924
AnnaBridge	163:e59c8e839560	2925	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	2926	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
AnnaBridge	163:e59c8e839560	2927	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
AnnaBridge	163:e59c8e839560	2928	#define __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM19RST))
AnnaBridge	163:e59c8e839560	2929	#define __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC1RST))
AnnaBridge	163:e59c8e839560	2930	#define __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC2RST))
AnnaBridge	163:e59c8e839560	2931	#define __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC3RST))
AnnaBridge	163:e59c8e839560	2932
AnnaBridge	163:e59c8e839560	2933	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
AnnaBridge	163:e59c8e839560	2934	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge	163:e59c8e839560	2935	#define __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
AnnaBridge	163:e59c8e839560	2936	#define __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
AnnaBridge	163:e59c8e839560	2937	#define __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
AnnaBridge	163:e59c8e839560	2938	#define __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
AnnaBridge	163:e59c8e839560	2939	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	2940
AnnaBridge	163:e59c8e839560	2941	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	2942	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)\
AnnaBridge	163:e59c8e839560	2943	\|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)\
AnnaBridge	163:e59c8e839560	2944	\|\| defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	2945	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
AnnaBridge	163:e59c8e839560	2946
AnnaBridge	163:e59c8e839560	2947	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
AnnaBridge	163:e59c8e839560	2948	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	2949	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
AnnaBridge	163:e59c8e839560	2950	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
AnnaBridge	163:e59c8e839560	2951	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	2952
AnnaBridge	163:e59c8e839560	2953	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	2954	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	2955
AnnaBridge	163:e59c8e839560	2956	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	163:e59c8e839560	2957	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2958
AnnaBridge	163:e59c8e839560	2959	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	2960	#define __HAL_RCC_TIM20_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM20RST))
AnnaBridge	163:e59c8e839560	2961
AnnaBridge	163:e59c8e839560	2962	#define __HAL_RCC_TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
AnnaBridge	163:e59c8e839560	2963	#endif /* STM32F303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	2964
AnnaBridge	163:e59c8e839560	2965	/**
AnnaBridge	163:e59c8e839560	2966	* @}
AnnaBridge	163:e59c8e839560	2967	*/
AnnaBridge	163:e59c8e839560	2968
AnnaBridge	163:e59c8e839560	2969	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
AnnaBridge	163:e59c8e839560	2970	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
AnnaBridge	163:e59c8e839560	2971	* @{
AnnaBridge	163:e59c8e839560	2972	*/
AnnaBridge	163:e59c8e839560	2973
AnnaBridge	163:e59c8e839560	2974	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge	163:e59c8e839560	2975	* @param __I2C2CLKSource__ specifies the I2C2 clock source.
AnnaBridge	163:e59c8e839560	2976	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2977	* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge	163:e59c8e839560	2978	* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge	163:e59c8e839560	2979	*/
AnnaBridge	163:e59c8e839560	2980	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
AnnaBridge	163:e59c8e839560	2981	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
AnnaBridge	163:e59c8e839560	2982
AnnaBridge	163:e59c8e839560	2983	/** @brief Macro to get the I2C2 clock source.
AnnaBridge	163:e59c8e839560	2984	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	2985	* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge	163:e59c8e839560	2986	* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge	163:e59c8e839560	2987	*/
AnnaBridge	163:e59c8e839560	2988	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
AnnaBridge	163:e59c8e839560	2989
AnnaBridge	163:e59c8e839560	2990	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge	163:e59c8e839560	2991	* @param __I2C3CLKSource__ specifies the I2C3 clock source.
AnnaBridge	163:e59c8e839560	2992	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	2993	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge	163:e59c8e839560	2994	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge	163:e59c8e839560	2995	*/
AnnaBridge	163:e59c8e839560	2996	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
AnnaBridge	163:e59c8e839560	2997	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
AnnaBridge	163:e59c8e839560	2998
AnnaBridge	163:e59c8e839560	2999	/** @brief Macro to get the I2C3 clock source.
AnnaBridge	163:e59c8e839560	3000	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3001	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge	163:e59c8e839560	3002	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge	163:e59c8e839560	3003	*/
AnnaBridge	163:e59c8e839560	3004	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
AnnaBridge	163:e59c8e839560	3005
AnnaBridge	163:e59c8e839560	3006	/**
AnnaBridge	163:e59c8e839560	3007	* @}
AnnaBridge	163:e59c8e839560	3008	*/
AnnaBridge	163:e59c8e839560	3009
AnnaBridge	163:e59c8e839560	3010	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge	163:e59c8e839560	3011	* @{
AnnaBridge	163:e59c8e839560	3012	*/
AnnaBridge	163:e59c8e839560	3013	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
AnnaBridge	163:e59c8e839560	3014	* @param __TIM1CLKSource__ specifies the TIM1 clock source.
AnnaBridge	163:e59c8e839560	3015	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3016	* @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3017	* @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3018	*/
AnnaBridge	163:e59c8e839560	3019	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
AnnaBridge	163:e59c8e839560	3020	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
AnnaBridge	163:e59c8e839560	3021
AnnaBridge	163:e59c8e839560	3022	/** @brief Macro to get the TIM1 clock (TIM1CLK).
AnnaBridge	163:e59c8e839560	3023	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3024	* @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3025	* @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3026	*/
AnnaBridge	163:e59c8e839560	3027	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
AnnaBridge	163:e59c8e839560	3028
AnnaBridge	163:e59c8e839560	3029	/** @brief Macro to configure the TIM15 clock (TIM15CLK).
AnnaBridge	163:e59c8e839560	3030	* @param __TIM15CLKSource__ specifies the TIM15 clock source.
AnnaBridge	163:e59c8e839560	3031	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3032	* @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
AnnaBridge	163:e59c8e839560	3033	* @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
AnnaBridge	163:e59c8e839560	3034	*/
AnnaBridge	163:e59c8e839560	3035	#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
AnnaBridge	163:e59c8e839560	3036	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
AnnaBridge	163:e59c8e839560	3037
AnnaBridge	163:e59c8e839560	3038	/** @brief Macro to get the TIM15 clock (TIM15CLK).
AnnaBridge	163:e59c8e839560	3039	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3040	* @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
AnnaBridge	163:e59c8e839560	3041	* @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
AnnaBridge	163:e59c8e839560	3042	*/
AnnaBridge	163:e59c8e839560	3043	#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
AnnaBridge	163:e59c8e839560	3044
AnnaBridge	163:e59c8e839560	3045	/** @brief Macro to configure the TIM16 clock (TIM16CLK).
AnnaBridge	163:e59c8e839560	3046	* @param __TIM16CLKSource__ specifies the TIM16 clock source.
AnnaBridge	163:e59c8e839560	3047	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3048	* @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
AnnaBridge	163:e59c8e839560	3049	* @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
AnnaBridge	163:e59c8e839560	3050	*/
AnnaBridge	163:e59c8e839560	3051	#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
AnnaBridge	163:e59c8e839560	3052	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
AnnaBridge	163:e59c8e839560	3053
AnnaBridge	163:e59c8e839560	3054	/** @brief Macro to get the TIM16 clock (TIM16CLK).
AnnaBridge	163:e59c8e839560	3055	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3056	* @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
AnnaBridge	163:e59c8e839560	3057	* @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
AnnaBridge	163:e59c8e839560	3058	*/
AnnaBridge	163:e59c8e839560	3059	#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
AnnaBridge	163:e59c8e839560	3060
AnnaBridge	163:e59c8e839560	3061	/** @brief Macro to configure the TIM17 clock (TIM17CLK).
AnnaBridge	163:e59c8e839560	3062	* @param __TIM17CLKSource__ specifies the TIM17 clock source.
AnnaBridge	163:e59c8e839560	3063	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3064	* @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
AnnaBridge	163:e59c8e839560	3065	* @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
AnnaBridge	163:e59c8e839560	3066	*/
AnnaBridge	163:e59c8e839560	3067	#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
AnnaBridge	163:e59c8e839560	3068	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
AnnaBridge	163:e59c8e839560	3069
AnnaBridge	163:e59c8e839560	3070	/** @brief Macro to get the TIM17 clock (TIM17CLK).
AnnaBridge	163:e59c8e839560	3071	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3072	* @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
AnnaBridge	163:e59c8e839560	3073	* @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
AnnaBridge	163:e59c8e839560	3074	*/
AnnaBridge	163:e59c8e839560	3075	#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
AnnaBridge	163:e59c8e839560	3076
AnnaBridge	163:e59c8e839560	3077	/**
AnnaBridge	163:e59c8e839560	3078	* @}
AnnaBridge	163:e59c8e839560	3079	*/
AnnaBridge	163:e59c8e839560	3080
AnnaBridge	163:e59c8e839560	3081	/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
AnnaBridge	163:e59c8e839560	3082	* @{
AnnaBridge	163:e59c8e839560	3083	*/
AnnaBridge	163:e59c8e839560	3084	/** @brief Macro to configure the I2S clock source (I2SCLK).
AnnaBridge	163:e59c8e839560	3085	* @note This function must be called before enabling the I2S APB clock.
AnnaBridge	163:e59c8e839560	3086	* @param __I2SCLKSource__ specifies the I2S clock source.
AnnaBridge	163:e59c8e839560	3087	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3088	* @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
AnnaBridge	163:e59c8e839560	3089	* @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
AnnaBridge	163:e59c8e839560	3090	* used as I2S clock source
AnnaBridge	163:e59c8e839560	3091	*/
AnnaBridge	163:e59c8e839560	3092	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
AnnaBridge	163:e59c8e839560	3093	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
AnnaBridge	163:e59c8e839560	3094
AnnaBridge	163:e59c8e839560	3095	/** @brief Macro to get the I2S clock source (I2SCLK).
AnnaBridge	163:e59c8e839560	3096	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3097	* @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
AnnaBridge	163:e59c8e839560	3098	* @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
AnnaBridge	163:e59c8e839560	3099	* used as I2S clock source
AnnaBridge	163:e59c8e839560	3100	*/
AnnaBridge	163:e59c8e839560	3101	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
AnnaBridge	163:e59c8e839560	3102	/**
AnnaBridge	163:e59c8e839560	3103	* @}
AnnaBridge	163:e59c8e839560	3104	*/
AnnaBridge	163:e59c8e839560	3105
AnnaBridge	163:e59c8e839560	3106	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
AnnaBridge	163:e59c8e839560	3107	* @{
AnnaBridge	163:e59c8e839560	3108	*/
AnnaBridge	163:e59c8e839560	3109
AnnaBridge	163:e59c8e839560	3110	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
AnnaBridge	163:e59c8e839560	3111	* @param __ADC1CLKSource__ specifies the ADC1 clock source.
AnnaBridge	163:e59c8e839560	3112	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3113	* @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
AnnaBridge	163:e59c8e839560	3114	* @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3115	* @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3116	* @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3117	* @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3118	* @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3119	* @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3120	* @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3121	* @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3122	* @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3123	* @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3124	* @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3125	* @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3126	*/
AnnaBridge	163:e59c8e839560	3127	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
AnnaBridge	163:e59c8e839560	3128	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
AnnaBridge	163:e59c8e839560	3129
AnnaBridge	163:e59c8e839560	3130	/** @brief Macro to get the ADC1 clock
AnnaBridge	163:e59c8e839560	3131	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3132	* @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
AnnaBridge	163:e59c8e839560	3133	* @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3134	* @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3135	* @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3136	* @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3137	* @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3138	* @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3139	* @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3140	* @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3141	* @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3142	* @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3143	* @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3144	* @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3145	*/
AnnaBridge	163:e59c8e839560	3146	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
AnnaBridge	163:e59c8e839560	3147	/**
AnnaBridge	163:e59c8e839560	3148	* @}
AnnaBridge	163:e59c8e839560	3149	*/
AnnaBridge	163:e59c8e839560	3150
AnnaBridge	163:e59c8e839560	3151	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
AnnaBridge	163:e59c8e839560	3152
AnnaBridge	163:e59c8e839560	3153	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	3154	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	3155	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
AnnaBridge	163:e59c8e839560	3156	* @{
AnnaBridge	163:e59c8e839560	3157	*/
AnnaBridge	163:e59c8e839560	3158
AnnaBridge	163:e59c8e839560	3159	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge	163:e59c8e839560	3160	* @param __I2C2CLKSource__ specifies the I2C2 clock source.
AnnaBridge	163:e59c8e839560	3161	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3162	* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge	163:e59c8e839560	3163	* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge	163:e59c8e839560	3164	*/
AnnaBridge	163:e59c8e839560	3165	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
AnnaBridge	163:e59c8e839560	3166	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
AnnaBridge	163:e59c8e839560	3167
AnnaBridge	163:e59c8e839560	3168	/** @brief Macro to get the I2C2 clock source.
AnnaBridge	163:e59c8e839560	3169	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3170	* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge	163:e59c8e839560	3171	* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge	163:e59c8e839560	3172	*/
AnnaBridge	163:e59c8e839560	3173	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
AnnaBridge	163:e59c8e839560	3174	/**
AnnaBridge	163:e59c8e839560	3175	* @}
AnnaBridge	163:e59c8e839560	3176	*/
AnnaBridge	163:e59c8e839560	3177
AnnaBridge	163:e59c8e839560	3178	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
AnnaBridge	163:e59c8e839560	3179	* @{
AnnaBridge	163:e59c8e839560	3180	*/
AnnaBridge	163:e59c8e839560	3181
AnnaBridge	163:e59c8e839560	3182	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
AnnaBridge	163:e59c8e839560	3183	* @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
AnnaBridge	163:e59c8e839560	3184	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3185	* @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
AnnaBridge	163:e59c8e839560	3186	* @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3187	* @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3188	* @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3189	* @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3190	* @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3191	* @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3192	* @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3193	* @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3194	* @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3195	* @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3196	* @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3197	* @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3198	*/
AnnaBridge	163:e59c8e839560	3199	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
AnnaBridge	163:e59c8e839560	3200	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
AnnaBridge	163:e59c8e839560	3201
AnnaBridge	163:e59c8e839560	3202	/** @brief Macro to get the ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3203	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3204	* @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
AnnaBridge	163:e59c8e839560	3205	* @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3206	* @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3207	* @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3208	* @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3209	* @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3210	* @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3211	* @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3212	* @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3213	* @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3214	* @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3215	* @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3216	* @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3217	*/
AnnaBridge	163:e59c8e839560	3218	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
AnnaBridge	163:e59c8e839560	3219	/**
AnnaBridge	163:e59c8e839560	3220	* @}
AnnaBridge	163:e59c8e839560	3221	*/
AnnaBridge	163:e59c8e839560	3222
AnnaBridge	163:e59c8e839560	3223	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge	163:e59c8e839560	3224	* @{
AnnaBridge	163:e59c8e839560	3225	*/
AnnaBridge	163:e59c8e839560	3226
AnnaBridge	163:e59c8e839560	3227	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
AnnaBridge	163:e59c8e839560	3228	* @param __TIM1CLKSource__ specifies the TIM1 clock source.
AnnaBridge	163:e59c8e839560	3229	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3230	* @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3231	* @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3232	*/
AnnaBridge	163:e59c8e839560	3233	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
AnnaBridge	163:e59c8e839560	3234	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
AnnaBridge	163:e59c8e839560	3235
AnnaBridge	163:e59c8e839560	3236	/** @brief Macro to get the TIM1 clock (TIM1CLK).
AnnaBridge	163:e59c8e839560	3237	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3238	* @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3239	* @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3240	*/
AnnaBridge	163:e59c8e839560	3241	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
AnnaBridge	163:e59c8e839560	3242	/**
AnnaBridge	163:e59c8e839560	3243	* @}
AnnaBridge	163:e59c8e839560	3244	*/
AnnaBridge	163:e59c8e839560	3245
AnnaBridge	163:e59c8e839560	3246	/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
AnnaBridge	163:e59c8e839560	3247	* @{
AnnaBridge	163:e59c8e839560	3248	*/
AnnaBridge	163:e59c8e839560	3249
AnnaBridge	163:e59c8e839560	3250	/** @brief Macro to configure the I2S clock source (I2SCLK).
AnnaBridge	163:e59c8e839560	3251	* @note This function must be called before enabling the I2S APB clock.
AnnaBridge	163:e59c8e839560	3252	* @param __I2SCLKSource__ specifies the I2S clock source.
AnnaBridge	163:e59c8e839560	3253	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3254	* @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
AnnaBridge	163:e59c8e839560	3255	* @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
AnnaBridge	163:e59c8e839560	3256	* used as I2S clock source
AnnaBridge	163:e59c8e839560	3257	*/
AnnaBridge	163:e59c8e839560	3258	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
AnnaBridge	163:e59c8e839560	3259	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
AnnaBridge	163:e59c8e839560	3260
AnnaBridge	163:e59c8e839560	3261	/** @brief Macro to get the I2S clock source (I2SCLK).
AnnaBridge	163:e59c8e839560	3262	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3263	* @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
AnnaBridge	163:e59c8e839560	3264	* @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
AnnaBridge	163:e59c8e839560	3265	* used as I2S clock source
AnnaBridge	163:e59c8e839560	3266	*/
AnnaBridge	163:e59c8e839560	3267	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
AnnaBridge	163:e59c8e839560	3268	/**
AnnaBridge	163:e59c8e839560	3269	* @}
AnnaBridge	163:e59c8e839560	3270	*/
AnnaBridge	163:e59c8e839560	3271
AnnaBridge	163:e59c8e839560	3272	/** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
AnnaBridge	163:e59c8e839560	3273	* @{
AnnaBridge	163:e59c8e839560	3274	*/
AnnaBridge	163:e59c8e839560	3275
AnnaBridge	163:e59c8e839560	3276	/** @brief Macro to configure the UART4 clock (UART4CLK).
AnnaBridge	163:e59c8e839560	3277	* @param __UART4CLKSource__ specifies the UART4 clock source.
AnnaBridge	163:e59c8e839560	3278	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3279	* @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
AnnaBridge	163:e59c8e839560	3280	* @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
AnnaBridge	163:e59c8e839560	3281	* @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
AnnaBridge	163:e59c8e839560	3282	* @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
AnnaBridge	163:e59c8e839560	3283	*/
AnnaBridge	163:e59c8e839560	3284	#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
AnnaBridge	163:e59c8e839560	3285	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
AnnaBridge	163:e59c8e839560	3286
AnnaBridge	163:e59c8e839560	3287	/** @brief Macro to get the UART4 clock source.
AnnaBridge	163:e59c8e839560	3288	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3289	* @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
AnnaBridge	163:e59c8e839560	3290	* @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
AnnaBridge	163:e59c8e839560	3291	* @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
AnnaBridge	163:e59c8e839560	3292	* @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
AnnaBridge	163:e59c8e839560	3293	*/
AnnaBridge	163:e59c8e839560	3294	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
AnnaBridge	163:e59c8e839560	3295
AnnaBridge	163:e59c8e839560	3296	/** @brief Macro to configure the UART5 clock (UART5CLK).
AnnaBridge	163:e59c8e839560	3297	* @param __UART5CLKSource__ specifies the UART5 clock source.
AnnaBridge	163:e59c8e839560	3298	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3299	* @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
AnnaBridge	163:e59c8e839560	3300	* @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
AnnaBridge	163:e59c8e839560	3301	* @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
AnnaBridge	163:e59c8e839560	3302	* @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
AnnaBridge	163:e59c8e839560	3303	*/
AnnaBridge	163:e59c8e839560	3304	#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
AnnaBridge	163:e59c8e839560	3305	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
AnnaBridge	163:e59c8e839560	3306
AnnaBridge	163:e59c8e839560	3307	/** @brief Macro to get the UART5 clock source.
AnnaBridge	163:e59c8e839560	3308	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3309	* @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
AnnaBridge	163:e59c8e839560	3310	* @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
AnnaBridge	163:e59c8e839560	3311	* @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
AnnaBridge	163:e59c8e839560	3312	* @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
AnnaBridge	163:e59c8e839560	3313	*/
AnnaBridge	163:e59c8e839560	3314	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
AnnaBridge	163:e59c8e839560	3315	/**
AnnaBridge	163:e59c8e839560	3316	* @}
AnnaBridge	163:e59c8e839560	3317	*/
AnnaBridge	163:e59c8e839560	3318	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	3319	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	3320
AnnaBridge	163:e59c8e839560	3321	#if defined(STM32F303xE) \|\| defined(STM32F398xx)\
AnnaBridge	163:e59c8e839560	3322	\|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	3323	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
AnnaBridge	163:e59c8e839560	3324	* @{
AnnaBridge	163:e59c8e839560	3325	*/
AnnaBridge	163:e59c8e839560	3326
AnnaBridge	163:e59c8e839560	3327	/** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
AnnaBridge	163:e59c8e839560	3328	* @param __ADC34CLKSource__ specifies the ADC3 & ADC4 clock source.
AnnaBridge	163:e59c8e839560	3329	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3330	* @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
AnnaBridge	163:e59c8e839560	3331	* @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3332	* @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3333	* @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3334	* @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3335	* @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3336	* @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3337	* @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3338	* @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3339	* @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3340	* @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3341	* @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3342	* @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3343	*/
AnnaBridge	163:e59c8e839560	3344	#define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
AnnaBridge	163:e59c8e839560	3345	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
AnnaBridge	163:e59c8e839560	3346
AnnaBridge	163:e59c8e839560	3347	/** @brief Macro to get the ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3348	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3349	* @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
AnnaBridge	163:e59c8e839560	3350	* @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3351	* @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3352	* @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3353	* @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3354	* @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3355	* @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3356	* @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3357	* @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3358	* @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3359	* @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3360	* @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3361	* @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
AnnaBridge	163:e59c8e839560	3362	*/
AnnaBridge	163:e59c8e839560	3363	#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
AnnaBridge	163:e59c8e839560	3364	/**
AnnaBridge	163:e59c8e839560	3365	* @}
AnnaBridge	163:e59c8e839560	3366	*/
AnnaBridge	163:e59c8e839560	3367
AnnaBridge	163:e59c8e839560	3368	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge	163:e59c8e839560	3369	* @{
AnnaBridge	163:e59c8e839560	3370	*/
AnnaBridge	163:e59c8e839560	3371
AnnaBridge	163:e59c8e839560	3372	/** @brief Macro to configure the TIM8 clock (TIM8CLK).
AnnaBridge	163:e59c8e839560	3373	* @param __TIM8CLKSource__ specifies the TIM8 clock source.
AnnaBridge	163:e59c8e839560	3374	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3375	* @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
AnnaBridge	163:e59c8e839560	3376	* @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
AnnaBridge	163:e59c8e839560	3377	*/
AnnaBridge	163:e59c8e839560	3378	#define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
AnnaBridge	163:e59c8e839560	3379	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
AnnaBridge	163:e59c8e839560	3380
AnnaBridge	163:e59c8e839560	3381	/** @brief Macro to get the TIM8 clock (TIM8CLK).
AnnaBridge	163:e59c8e839560	3382	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3383	* @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
AnnaBridge	163:e59c8e839560	3384	* @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
AnnaBridge	163:e59c8e839560	3385	*/
AnnaBridge	163:e59c8e839560	3386	#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
AnnaBridge	163:e59c8e839560	3387
AnnaBridge	163:e59c8e839560	3388	/**
AnnaBridge	163:e59c8e839560	3389	* @}
AnnaBridge	163:e59c8e839560	3390	*/
AnnaBridge	163:e59c8e839560	3391	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
AnnaBridge	163:e59c8e839560	3392	/* STM32F303xC \|\| STM32F358xx */
AnnaBridge	163:e59c8e839560	3393
AnnaBridge	163:e59c8e839560	3394	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	3395	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
AnnaBridge	163:e59c8e839560	3396	* @{
AnnaBridge	163:e59c8e839560	3397	*/
AnnaBridge	163:e59c8e839560	3398
AnnaBridge	163:e59c8e839560	3399	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
AnnaBridge	163:e59c8e839560	3400	* @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
AnnaBridge	163:e59c8e839560	3401	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3402	* @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
AnnaBridge	163:e59c8e839560	3403	* @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3404	* @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3405	* @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3406	* @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3407	* @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3408	* @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3409	* @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3410	* @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3411	* @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3412	* @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3413	* @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3414	* @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3415	*/
AnnaBridge	163:e59c8e839560	3416	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
AnnaBridge	163:e59c8e839560	3417	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
AnnaBridge	163:e59c8e839560	3418
AnnaBridge	163:e59c8e839560	3419	/** @brief Macro to get the ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3420	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3421	* @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
AnnaBridge	163:e59c8e839560	3422	* @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3423	* @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3424	* @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3425	* @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3426	* @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3427	* @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3428	* @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3429	* @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3430	* @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3431	* @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3432	* @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3433	* @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
AnnaBridge	163:e59c8e839560	3434	*/
AnnaBridge	163:e59c8e839560	3435	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
AnnaBridge	163:e59c8e839560	3436	/**
AnnaBridge	163:e59c8e839560	3437	* @}
AnnaBridge	163:e59c8e839560	3438	*/
AnnaBridge	163:e59c8e839560	3439
AnnaBridge	163:e59c8e839560	3440	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge	163:e59c8e839560	3441	* @{
AnnaBridge	163:e59c8e839560	3442	*/
AnnaBridge	163:e59c8e839560	3443	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
AnnaBridge	163:e59c8e839560	3444	* @param __TIM1CLKSource__ specifies the TIM1 clock source.
AnnaBridge	163:e59c8e839560	3445	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3446	* @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3447	* @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3448	*/
AnnaBridge	163:e59c8e839560	3449	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
AnnaBridge	163:e59c8e839560	3450	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
AnnaBridge	163:e59c8e839560	3451
AnnaBridge	163:e59c8e839560	3452	/** @brief Macro to get the TIM1 clock (TIM1CLK).
AnnaBridge	163:e59c8e839560	3453	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3454	* @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3455	* @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
AnnaBridge	163:e59c8e839560	3456	*/
AnnaBridge	163:e59c8e839560	3457	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
AnnaBridge	163:e59c8e839560	3458	/**
AnnaBridge	163:e59c8e839560	3459	* @}
AnnaBridge	163:e59c8e839560	3460	*/
AnnaBridge	163:e59c8e839560	3461	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
AnnaBridge	163:e59c8e839560	3462
AnnaBridge	163:e59c8e839560	3463	#if defined(STM32F334x8)
AnnaBridge	163:e59c8e839560	3464	/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
AnnaBridge	163:e59c8e839560	3465	* @{
AnnaBridge	163:e59c8e839560	3466	*/
AnnaBridge	163:e59c8e839560	3467	/** @brief Macro to configure the HRTIM1 clock.
AnnaBridge	163:e59c8e839560	3468	* @param __HRTIM1CLKSource__ specifies the HRTIM1 clock source.
AnnaBridge	163:e59c8e839560	3469	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3470	* @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
AnnaBridge	163:e59c8e839560	3471	* @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
AnnaBridge	163:e59c8e839560	3472	*/
AnnaBridge	163:e59c8e839560	3473	#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
AnnaBridge	163:e59c8e839560	3474	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
AnnaBridge	163:e59c8e839560	3475
AnnaBridge	163:e59c8e839560	3476	/** @brief Macro to get the HRTIM1 clock source.
AnnaBridge	163:e59c8e839560	3477	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3478	* @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
AnnaBridge	163:e59c8e839560	3479	* @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
AnnaBridge	163:e59c8e839560	3480	*/
AnnaBridge	163:e59c8e839560	3481	#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
AnnaBridge	163:e59c8e839560	3482	/**
AnnaBridge	163:e59c8e839560	3483	* @}
AnnaBridge	163:e59c8e839560	3484	*/
AnnaBridge	163:e59c8e839560	3485	#endif /* STM32F334x8 */
AnnaBridge	163:e59c8e839560	3486
AnnaBridge	163:e59c8e839560	3487	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	3488	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
AnnaBridge	163:e59c8e839560	3489	* @{
AnnaBridge	163:e59c8e839560	3490	*/
AnnaBridge	163:e59c8e839560	3491	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge	163:e59c8e839560	3492	* @param __I2C2CLKSource__ specifies the I2C2 clock source.
AnnaBridge	163:e59c8e839560	3493	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3494	* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge	163:e59c8e839560	3495	* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge	163:e59c8e839560	3496	*/
AnnaBridge	163:e59c8e839560	3497	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
AnnaBridge	163:e59c8e839560	3498	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
AnnaBridge	163:e59c8e839560	3499
AnnaBridge	163:e59c8e839560	3500	/** @brief Macro to get the I2C2 clock source.
AnnaBridge	163:e59c8e839560	3501	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3502	* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge	163:e59c8e839560	3503	* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge	163:e59c8e839560	3504	*/
AnnaBridge	163:e59c8e839560	3505	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
AnnaBridge	163:e59c8e839560	3506	/**
AnnaBridge	163:e59c8e839560	3507	* @}
AnnaBridge	163:e59c8e839560	3508	*/
AnnaBridge	163:e59c8e839560	3509
AnnaBridge	163:e59c8e839560	3510	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
AnnaBridge	163:e59c8e839560	3511	* @{
AnnaBridge	163:e59c8e839560	3512	*/
AnnaBridge	163:e59c8e839560	3513	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
AnnaBridge	163:e59c8e839560	3514	* @param __ADC1CLKSource__ specifies the ADC1 clock source.
AnnaBridge	163:e59c8e839560	3515	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3516	* @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3517	* @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3518	* @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3519	* @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3520	*/
AnnaBridge	163:e59c8e839560	3521	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
AnnaBridge	163:e59c8e839560	3522	MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
AnnaBridge	163:e59c8e839560	3523
AnnaBridge	163:e59c8e839560	3524	/** @brief Macro to get the ADC1 clock (ADC1CLK).
AnnaBridge	163:e59c8e839560	3525	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3526	* @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3527	* @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3528	* @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3529	* @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
AnnaBridge	163:e59c8e839560	3530	*/
AnnaBridge	163:e59c8e839560	3531	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
AnnaBridge	163:e59c8e839560	3532	/**
AnnaBridge	163:e59c8e839560	3533	* @}
AnnaBridge	163:e59c8e839560	3534	*/
AnnaBridge	163:e59c8e839560	3535
AnnaBridge	163:e59c8e839560	3536	/** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
AnnaBridge	163:e59c8e839560	3537	* @{
AnnaBridge	163:e59c8e839560	3538	*/
AnnaBridge	163:e59c8e839560	3539	/** @brief Macro to configure the SDADCx clock (SDADCxCLK).
AnnaBridge	163:e59c8e839560	3540	* @param __SDADCPrescaler__ specifies the SDADCx system clock prescaler.
AnnaBridge	163:e59c8e839560	3541	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3542	* @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3543	* @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3544	* @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3545	* @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3546	* @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3547	* @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3548	* @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3549	* @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3550	* @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3551	* @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3552	* @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3553	* @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3554	* @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3555	* @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3556	* @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3557	* @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3558	* @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3559	*/
AnnaBridge	163:e59c8e839560	3560	#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
AnnaBridge	163:e59c8e839560	3561	MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__))
AnnaBridge	163:e59c8e839560	3562
AnnaBridge	163:e59c8e839560	3563	/** @brief Macro to get the SDADCx clock prescaler.
AnnaBridge	163:e59c8e839560	3564	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3565	* @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3566	* @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3567	* @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3568	* @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3569	* @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3570	* @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3571	* @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3572	* @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3573	* @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3574	* @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3575	* @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3576	* @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3577	* @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3578	* @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3579	* @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3580	* @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3581	* @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
AnnaBridge	163:e59c8e839560	3582	*/
AnnaBridge	163:e59c8e839560	3583	#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE)))
AnnaBridge	163:e59c8e839560	3584	/**
AnnaBridge	163:e59c8e839560	3585	* @}
AnnaBridge	163:e59c8e839560	3586	*/
AnnaBridge	163:e59c8e839560	3587
AnnaBridge	163:e59c8e839560	3588	/** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
AnnaBridge	163:e59c8e839560	3589	* @{
AnnaBridge	163:e59c8e839560	3590	*/
AnnaBridge	163:e59c8e839560	3591	/** @brief Macro to configure the CEC clock.
AnnaBridge	163:e59c8e839560	3592	* @param __CECCLKSource__ specifies the CEC clock source.
AnnaBridge	163:e59c8e839560	3593	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3594	* @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
AnnaBridge	163:e59c8e839560	3595	* @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
AnnaBridge	163:e59c8e839560	3596	*/
AnnaBridge	163:e59c8e839560	3597	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
AnnaBridge	163:e59c8e839560	3598	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
AnnaBridge	163:e59c8e839560	3599
AnnaBridge	163:e59c8e839560	3600	/** @brief Macro to get the HDMI CEC clock source.
AnnaBridge	163:e59c8e839560	3601	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3602	* @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
AnnaBridge	163:e59c8e839560	3603	* @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
AnnaBridge	163:e59c8e839560	3604	*/
AnnaBridge	163:e59c8e839560	3605	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
AnnaBridge	163:e59c8e839560	3606	/**
AnnaBridge	163:e59c8e839560	3607	* @}
AnnaBridge	163:e59c8e839560	3608	*/
AnnaBridge	163:e59c8e839560	3609
AnnaBridge	163:e59c8e839560	3610	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	3611
AnnaBridge	163:e59c8e839560	3612	#if defined(STM32F302xE) \|\| defined(STM32F303xE)\
AnnaBridge	163:e59c8e839560	3613	\|\| defined(STM32F302xC) \|\| defined(STM32F303xC)\
AnnaBridge	163:e59c8e839560	3614	\|\| defined(STM32F302x8) \
AnnaBridge	163:e59c8e839560	3615	\|\| defined(STM32F373xC)
AnnaBridge	163:e59c8e839560	3616
AnnaBridge	163:e59c8e839560	3617	/** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
AnnaBridge	163:e59c8e839560	3618	* @{
AnnaBridge	163:e59c8e839560	3619	*/
AnnaBridge	163:e59c8e839560	3620	/** @brief Macro to configure the USB clock (USBCLK).
AnnaBridge	163:e59c8e839560	3621	* @param __USBCLKSource__ specifies the USB clock source.
AnnaBridge	163:e59c8e839560	3622	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3623	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
AnnaBridge	163:e59c8e839560	3624	* @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
AnnaBridge	163:e59c8e839560	3625	*/
AnnaBridge	163:e59c8e839560	3626	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
AnnaBridge	163:e59c8e839560	3627	MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
AnnaBridge	163:e59c8e839560	3628
AnnaBridge	163:e59c8e839560	3629	/** @brief Macro to get the USB clock source.
AnnaBridge	163:e59c8e839560	3630	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3631	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
AnnaBridge	163:e59c8e839560	3632	* @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
AnnaBridge	163:e59c8e839560	3633	*/
AnnaBridge	163:e59c8e839560	3634	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
AnnaBridge	163:e59c8e839560	3635	/**
AnnaBridge	163:e59c8e839560	3636	* @}
AnnaBridge	163:e59c8e839560	3637	*/
AnnaBridge	163:e59c8e839560	3638
AnnaBridge	163:e59c8e839560	3639	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
AnnaBridge	163:e59c8e839560	3640	/* STM32F302xC \|\| STM32F303xC \|\| */
AnnaBridge	163:e59c8e839560	3641	/* STM32F302x8 \|\| */
AnnaBridge	163:e59c8e839560	3642	/* STM32F373xC */
AnnaBridge	163:e59c8e839560	3643
AnnaBridge	163:e59c8e839560	3644	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	3645
AnnaBridge	163:e59c8e839560	3646	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
AnnaBridge	163:e59c8e839560	3647	* @{
AnnaBridge	163:e59c8e839560	3648	*/
AnnaBridge	163:e59c8e839560	3649	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge	163:e59c8e839560	3650	* @param __I2C3CLKSource__ specifies the I2C3 clock source.
AnnaBridge	163:e59c8e839560	3651	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3652	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge	163:e59c8e839560	3653	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge	163:e59c8e839560	3654	*/
AnnaBridge	163:e59c8e839560	3655	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
AnnaBridge	163:e59c8e839560	3656	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
AnnaBridge	163:e59c8e839560	3657
AnnaBridge	163:e59c8e839560	3658	/** @brief Macro to get the I2C3 clock source.
AnnaBridge	163:e59c8e839560	3659	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3660	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge	163:e59c8e839560	3661	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge	163:e59c8e839560	3662	*/
AnnaBridge	163:e59c8e839560	3663	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
AnnaBridge	163:e59c8e839560	3664	/**
AnnaBridge	163:e59c8e839560	3665	* @}
AnnaBridge	163:e59c8e839560	3666	*/
AnnaBridge	163:e59c8e839560	3667
AnnaBridge	163:e59c8e839560	3668	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge	163:e59c8e839560	3669	* @{
AnnaBridge	163:e59c8e839560	3670	*/
AnnaBridge	163:e59c8e839560	3671	/** @brief Macro to configure the TIM2 clock (TIM2CLK).
AnnaBridge	163:e59c8e839560	3672	* @param __TIM2CLKSource__ specifies the TIM2 clock source.
AnnaBridge	163:e59c8e839560	3673	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3674	* @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
AnnaBridge	163:e59c8e839560	3675	* @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
AnnaBridge	163:e59c8e839560	3676	*/
AnnaBridge	163:e59c8e839560	3677	#define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
AnnaBridge	163:e59c8e839560	3678	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
AnnaBridge	163:e59c8e839560	3679
AnnaBridge	163:e59c8e839560	3680	/** @brief Macro to get the TIM2 clock (TIM2CLK).
AnnaBridge	163:e59c8e839560	3681	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3682	* @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
AnnaBridge	163:e59c8e839560	3683	* @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
AnnaBridge	163:e59c8e839560	3684	*/
AnnaBridge	163:e59c8e839560	3685	#define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
AnnaBridge	163:e59c8e839560	3686
AnnaBridge	163:e59c8e839560	3687	/** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
AnnaBridge	163:e59c8e839560	3688	* @param __TIM34CLKSource__ specifies the TIM3 & TIM4 clock source.
AnnaBridge	163:e59c8e839560	3689	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3690	* @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
AnnaBridge	163:e59c8e839560	3691	* @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
AnnaBridge	163:e59c8e839560	3692	*/
AnnaBridge	163:e59c8e839560	3693	#define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
AnnaBridge	163:e59c8e839560	3694	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
AnnaBridge	163:e59c8e839560	3695
AnnaBridge	163:e59c8e839560	3696	/** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
AnnaBridge	163:e59c8e839560	3697	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3698	* @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
AnnaBridge	163:e59c8e839560	3699	* @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
AnnaBridge	163:e59c8e839560	3700	*/
AnnaBridge	163:e59c8e839560	3701	#define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
AnnaBridge	163:e59c8e839560	3702
AnnaBridge	163:e59c8e839560	3703	/** @brief Macro to configure the TIM15 clock (TIM15CLK).
AnnaBridge	163:e59c8e839560	3704	* @param __TIM15CLKSource__ specifies the TIM15 clock source.
AnnaBridge	163:e59c8e839560	3705	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3706	* @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
AnnaBridge	163:e59c8e839560	3707	* @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
AnnaBridge	163:e59c8e839560	3708	*/
AnnaBridge	163:e59c8e839560	3709	#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
AnnaBridge	163:e59c8e839560	3710	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
AnnaBridge	163:e59c8e839560	3711
AnnaBridge	163:e59c8e839560	3712	/** @brief Macro to get the TIM15 clock (TIM15CLK).
AnnaBridge	163:e59c8e839560	3713	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3714	* @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
AnnaBridge	163:e59c8e839560	3715	* @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
AnnaBridge	163:e59c8e839560	3716	*/
AnnaBridge	163:e59c8e839560	3717	#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
AnnaBridge	163:e59c8e839560	3718
AnnaBridge	163:e59c8e839560	3719	/** @brief Macro to configure the TIM16 clock (TIM16CLK).
AnnaBridge	163:e59c8e839560	3720	* @param __TIM16CLKSource__ specifies the TIM16 clock source.
AnnaBridge	163:e59c8e839560	3721	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3722	* @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
AnnaBridge	163:e59c8e839560	3723	* @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
AnnaBridge	163:e59c8e839560	3724	*/
AnnaBridge	163:e59c8e839560	3725	#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
AnnaBridge	163:e59c8e839560	3726	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
AnnaBridge	163:e59c8e839560	3727
AnnaBridge	163:e59c8e839560	3728	/** @brief Macro to get the TIM16 clock (TIM16CLK).
AnnaBridge	163:e59c8e839560	3729	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3730	* @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
AnnaBridge	163:e59c8e839560	3731	* @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
AnnaBridge	163:e59c8e839560	3732	*/
AnnaBridge	163:e59c8e839560	3733	#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
AnnaBridge	163:e59c8e839560	3734
AnnaBridge	163:e59c8e839560	3735	/** @brief Macro to configure the TIM17 clock (TIM17CLK).
AnnaBridge	163:e59c8e839560	3736	* @param __TIM17CLKSource__ specifies the TIM17 clock source.
AnnaBridge	163:e59c8e839560	3737	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3738	* @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
AnnaBridge	163:e59c8e839560	3739	* @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
AnnaBridge	163:e59c8e839560	3740	*/
AnnaBridge	163:e59c8e839560	3741	#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
AnnaBridge	163:e59c8e839560	3742	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
AnnaBridge	163:e59c8e839560	3743
AnnaBridge	163:e59c8e839560	3744	/** @brief Macro to get the TIM17 clock (TIM17CLK).
AnnaBridge	163:e59c8e839560	3745	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3746	* @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
AnnaBridge	163:e59c8e839560	3747	* @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
AnnaBridge	163:e59c8e839560	3748	*/
AnnaBridge	163:e59c8e839560	3749	#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
AnnaBridge	163:e59c8e839560	3750
AnnaBridge	163:e59c8e839560	3751	/**
AnnaBridge	163:e59c8e839560	3752	* @}
AnnaBridge	163:e59c8e839560	3753	*/
AnnaBridge	163:e59c8e839560	3754
AnnaBridge	163:e59c8e839560	3755	#endif /* STM32f302xE \|\| STM32f303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	3756
AnnaBridge	163:e59c8e839560	3757	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
AnnaBridge	163:e59c8e839560	3758	/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
AnnaBridge	163:e59c8e839560	3759	* @{
AnnaBridge	163:e59c8e839560	3760	*/
AnnaBridge	163:e59c8e839560	3761	/** @brief Macro to configure the TIM20 clock (TIM20CLK).
AnnaBridge	163:e59c8e839560	3762	* @param __TIM20CLKSource__ specifies the TIM20 clock source.
AnnaBridge	163:e59c8e839560	3763	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3764	* @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
AnnaBridge	163:e59c8e839560	3765	* @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
AnnaBridge	163:e59c8e839560	3766	*/
AnnaBridge	163:e59c8e839560	3767	#define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
AnnaBridge	163:e59c8e839560	3768	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
AnnaBridge	163:e59c8e839560	3769
AnnaBridge	163:e59c8e839560	3770	/** @brief Macro to get the TIM20 clock (TIM20CLK).
AnnaBridge	163:e59c8e839560	3771	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	3772	* @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
AnnaBridge	163:e59c8e839560	3773	* @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
AnnaBridge	163:e59c8e839560	3774	*/
AnnaBridge	163:e59c8e839560	3775	#define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
AnnaBridge	163:e59c8e839560	3776
AnnaBridge	163:e59c8e839560	3777	/**
AnnaBridge	163:e59c8e839560	3778	* @}
AnnaBridge	163:e59c8e839560	3779	*/
AnnaBridge	163:e59c8e839560	3780	#endif /* STM32f303xE \|\| STM32F398xx */
AnnaBridge	163:e59c8e839560	3781
AnnaBridge	163:e59c8e839560	3782	/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
AnnaBridge	163:e59c8e839560	3783	* @{
AnnaBridge	163:e59c8e839560	3784	*/
AnnaBridge	163:e59c8e839560	3785
AnnaBridge	163:e59c8e839560	3786	/**
AnnaBridge	163:e59c8e839560	3787	* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
AnnaBridge	163:e59c8e839560	3788	* @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
AnnaBridge	163:e59c8e839560	3789	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	3790	* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
AnnaBridge	163:e59c8e839560	3791	* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
AnnaBridge	163:e59c8e839560	3792	* @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
AnnaBridge	163:e59c8e839560	3793	* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
AnnaBridge	163:e59c8e839560	3794	* @retval None
AnnaBridge	163:e59c8e839560	3795	*/
AnnaBridge	163:e59c8e839560	3796	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
AnnaBridge	163:e59c8e839560	3797	RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
AnnaBridge	163:e59c8e839560	3798
AnnaBridge	163:e59c8e839560	3799	/**
AnnaBridge	163:e59c8e839560	3800	* @}
AnnaBridge	163:e59c8e839560	3801	*/
AnnaBridge	163:e59c8e839560	3802
AnnaBridge	163:e59c8e839560	3803	/**
AnnaBridge	163:e59c8e839560	3804	* @}
AnnaBridge	163:e59c8e839560	3805	*/
AnnaBridge	163:e59c8e839560	3806
AnnaBridge	163:e59c8e839560	3807	/* Exported functions --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	3808	/** @addtogroup RCCEx_Exported_Functions
AnnaBridge	163:e59c8e839560	3809	* @{
AnnaBridge	163:e59c8e839560	3810	*/
AnnaBridge	163:e59c8e839560	3811
AnnaBridge	163:e59c8e839560	3812	/** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge	163:e59c8e839560	3813	* @{
AnnaBridge	163:e59c8e839560	3814	*/
AnnaBridge	163:e59c8e839560	3815
AnnaBridge	163:e59c8e839560	3816	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	163:e59c8e839560	3817	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	163:e59c8e839560	3818	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge	163:e59c8e839560	3819
AnnaBridge	163:e59c8e839560	3820	/**
AnnaBridge	163:e59c8e839560	3821	* @}
AnnaBridge	163:e59c8e839560	3822	*/
AnnaBridge	163:e59c8e839560	3823
AnnaBridge	163:e59c8e839560	3824	/**
AnnaBridge	163:e59c8e839560	3825	* @}
AnnaBridge	163:e59c8e839560	3826	*/
AnnaBridge	163:e59c8e839560	3827
AnnaBridge	163:e59c8e839560	3828	/**
AnnaBridge	163:e59c8e839560	3829	* @}
AnnaBridge	163:e59c8e839560	3830	*/
AnnaBridge	163:e59c8e839560	3831
AnnaBridge	163:e59c8e839560	3832	/**
AnnaBridge	163:e59c8e839560	3833	* @}
AnnaBridge	163:e59c8e839560	3834	*/
AnnaBridge	163:e59c8e839560	3835
AnnaBridge	163:e59c8e839560	3836	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	3837	}
AnnaBridge	163:e59c8e839560	3838	#endif
AnnaBridge	163:e59c8e839560	3839
AnnaBridge	163:e59c8e839560	3840	#endif /* __STM32F3xx_HAL_RCC_EX_H */
AnnaBridge	163:e59c8e839560	3841
AnnaBridge	163:e59c8e839560	3842	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	163:e59c8e839560	3843