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TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_rcc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc.h@168:b9e159c1930a

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	163:e59c8e839560	1	/**
AnnaBridge	163:e59c8e839560	2	******************************************************************************
AnnaBridge	163:e59c8e839560	3	* @file stm32f3xx_hal_rcc.h
AnnaBridge	163:e59c8e839560	4	* @author MCD Application Team
AnnaBridge	163:e59c8e839560	5	* @brief Header file of RCC HAL module.
AnnaBridge	163:e59c8e839560	6	******************************************************************************
AnnaBridge	163:e59c8e839560	7	* @attention
AnnaBridge	163:e59c8e839560	8	*
AnnaBridge	163:e59c8e839560	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	163:e59c8e839560	10	*
AnnaBridge	163:e59c8e839560	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	163:e59c8e839560	12	* are permitted provided that the following conditions are met:
AnnaBridge	163:e59c8e839560	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	163:e59c8e839560	14	* this list of conditions and the following disclaimer.
AnnaBridge	163:e59c8e839560	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	163:e59c8e839560	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	163:e59c8e839560	17	* and/or other materials provided with the distribution.
AnnaBridge	163:e59c8e839560	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	163:e59c8e839560	19	* may be used to endorse or promote products derived from this software
AnnaBridge	163:e59c8e839560	20	* without specific prior written permission.
AnnaBridge	163:e59c8e839560	21	*
AnnaBridge	163:e59c8e839560	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	163:e59c8e839560	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	163:e59c8e839560	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	163:e59c8e839560	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	163:e59c8e839560	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	163:e59c8e839560	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	163:e59c8e839560	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	163:e59c8e839560	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	163:e59c8e839560	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	163:e59c8e839560	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	163:e59c8e839560	32	*
AnnaBridge	163:e59c8e839560	33	******************************************************************************
AnnaBridge	163:e59c8e839560	34	*/
AnnaBridge	163:e59c8e839560	35
AnnaBridge	163:e59c8e839560	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	163:e59c8e839560	37	#ifndef __STM32F3xx_HAL_RCC_H
AnnaBridge	163:e59c8e839560	38	#define __STM32F3xx_HAL_RCC_H
AnnaBridge	163:e59c8e839560	39
AnnaBridge	163:e59c8e839560	40	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	41	extern "C" {
AnnaBridge	163:e59c8e839560	42	#endif
AnnaBridge	163:e59c8e839560	43
AnnaBridge	163:e59c8e839560	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	45	#include "stm32f3xx_hal_def.h"
AnnaBridge	163:e59c8e839560	46
AnnaBridge	163:e59c8e839560	47	/** @addtogroup STM32F3xx_HAL_Driver
AnnaBridge	163:e59c8e839560	48	* @{
AnnaBridge	163:e59c8e839560	49	*/
AnnaBridge	163:e59c8e839560	50
AnnaBridge	163:e59c8e839560	51	/** @addtogroup RCC
AnnaBridge	163:e59c8e839560	52	* @{
AnnaBridge	163:e59c8e839560	53	*/
AnnaBridge	163:e59c8e839560	54
AnnaBridge	163:e59c8e839560	55	/** @addtogroup RCC_Private_Constants
AnnaBridge	163:e59c8e839560	56	* @{
AnnaBridge	163:e59c8e839560	57	*/
AnnaBridge	163:e59c8e839560	58
AnnaBridge	163:e59c8e839560	59	/** @defgroup RCC_Timeout RCC Timeout
AnnaBridge	163:e59c8e839560	60	* @{
AnnaBridge	163:e59c8e839560	61	*/
AnnaBridge	163:e59c8e839560	62
AnnaBridge	163:e59c8e839560	63	/* Disable Backup domain write protection state change timeout */
AnnaBridge	163:e59c8e839560	64	#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
AnnaBridge	163:e59c8e839560	65	/* LSE state change timeout */
AnnaBridge	163:e59c8e839560	66	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge	163:e59c8e839560	67	#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
AnnaBridge	163:e59c8e839560	68	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge	163:e59c8e839560	69	#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	163:e59c8e839560	70	#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	163:e59c8e839560	71	#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	163:e59c8e839560	72	/**
AnnaBridge	163:e59c8e839560	73	* @}
AnnaBridge	163:e59c8e839560	74	*/
AnnaBridge	163:e59c8e839560	75
AnnaBridge	163:e59c8e839560	76	/** @defgroup RCC_Register_Offset Register offsets
AnnaBridge	163:e59c8e839560	77	* @{
AnnaBridge	163:e59c8e839560	78	*/
AnnaBridge	163:e59c8e839560	79	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
AnnaBridge	163:e59c8e839560	80	#define RCC_CR_OFFSET 0x00
AnnaBridge	163:e59c8e839560	81	#define RCC_CFGR_OFFSET 0x04
AnnaBridge	163:e59c8e839560	82	#define RCC_CIR_OFFSET 0x08
AnnaBridge	163:e59c8e839560	83	#define RCC_BDCR_OFFSET 0x20
AnnaBridge	163:e59c8e839560	84	#define RCC_CSR_OFFSET 0x24
AnnaBridge	163:e59c8e839560	85
AnnaBridge	163:e59c8e839560	86	/**
AnnaBridge	163:e59c8e839560	87	* @}
AnnaBridge	163:e59c8e839560	88	*/
AnnaBridge	163:e59c8e839560	89
AnnaBridge	163:e59c8e839560	90	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
AnnaBridge	163:e59c8e839560	91	* @brief RCC registers bit address in the alias region
AnnaBridge	163:e59c8e839560	92	* @{
AnnaBridge	163:e59c8e839560	93	*/
AnnaBridge	163:e59c8e839560	94	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
AnnaBridge	163:e59c8e839560	95	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
AnnaBridge	163:e59c8e839560	96	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
AnnaBridge	163:e59c8e839560	97	#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
AnnaBridge	163:e59c8e839560	98	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
AnnaBridge	163:e59c8e839560	99
AnnaBridge	163:e59c8e839560	100	/* --- CR Register ---*/
AnnaBridge	163:e59c8e839560	101	/* Alias word address of HSION bit */
AnnaBridge	163:e59c8e839560	102	#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
AnnaBridge	163:e59c8e839560	103	#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
AnnaBridge	163:e59c8e839560	104	/* Alias word address of HSEON bit */
AnnaBridge	163:e59c8e839560	105	#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
AnnaBridge	163:e59c8e839560	106	#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
AnnaBridge	163:e59c8e839560	107	/* Alias word address of CSSON bit */
AnnaBridge	163:e59c8e839560	108	#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
AnnaBridge	163:e59c8e839560	109	#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
AnnaBridge	163:e59c8e839560	110	/* Alias word address of PLLON bit */
AnnaBridge	163:e59c8e839560	111	#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
AnnaBridge	163:e59c8e839560	112	#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
AnnaBridge	163:e59c8e839560	113
AnnaBridge	163:e59c8e839560	114	/* --- CSR Register ---*/
AnnaBridge	163:e59c8e839560	115	/* Alias word address of LSION bit */
AnnaBridge	163:e59c8e839560	116	#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
AnnaBridge	163:e59c8e839560	117	#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
AnnaBridge	163:e59c8e839560	118
AnnaBridge	163:e59c8e839560	119	/* Alias word address of RMVF bit */
AnnaBridge	163:e59c8e839560	120	#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
AnnaBridge	163:e59c8e839560	121	#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
AnnaBridge	163:e59c8e839560	122
AnnaBridge	163:e59c8e839560	123	/* --- BDCR Registers ---*/
AnnaBridge	163:e59c8e839560	124	/* Alias word address of LSEON bit */
AnnaBridge	163:e59c8e839560	125	#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
AnnaBridge	163:e59c8e839560	126	#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
AnnaBridge	163:e59c8e839560	127
AnnaBridge	163:e59c8e839560	128	/* Alias word address of LSEON bit */
AnnaBridge	163:e59c8e839560	129	#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
AnnaBridge	163:e59c8e839560	130	#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
AnnaBridge	163:e59c8e839560	131
AnnaBridge	163:e59c8e839560	132	/* Alias word address of RTCEN bit */
AnnaBridge	163:e59c8e839560	133	#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
AnnaBridge	163:e59c8e839560	134	#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
AnnaBridge	163:e59c8e839560	135
AnnaBridge	163:e59c8e839560	136	/* Alias word address of BDRST bit */
AnnaBridge	163:e59c8e839560	137	#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
AnnaBridge	163:e59c8e839560	138	#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
AnnaBridge	163:e59c8e839560	139
AnnaBridge	163:e59c8e839560	140	/**
AnnaBridge	163:e59c8e839560	141	* @}
AnnaBridge	163:e59c8e839560	142	*/
AnnaBridge	163:e59c8e839560	143
AnnaBridge	163:e59c8e839560	144	/* CR register byte 2 (Bits[23:16]) base address */
AnnaBridge	163:e59c8e839560	145	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
AnnaBridge	163:e59c8e839560	146
AnnaBridge	163:e59c8e839560	147	/* CIR register byte 1 (Bits[15:8]) base address */
AnnaBridge	163:e59c8e839560	148	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
AnnaBridge	163:e59c8e839560	149
AnnaBridge	163:e59c8e839560	150	/* CIR register byte 2 (Bits[23:16]) base address */
AnnaBridge	163:e59c8e839560	151	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
AnnaBridge	163:e59c8e839560	152
AnnaBridge	163:e59c8e839560	153	/* Defines used for Flags */
AnnaBridge	163:e59c8e839560	154	#define CR_REG_INDEX ((uint8_t)1U)
AnnaBridge	163:e59c8e839560	155	#define BDCR_REG_INDEX ((uint8_t)2U)
AnnaBridge	163:e59c8e839560	156	#define CSR_REG_INDEX ((uint8_t)3U)
AnnaBridge	163:e59c8e839560	157	#define CFGR_REG_INDEX ((uint8_t)4U)
AnnaBridge	163:e59c8e839560	158
AnnaBridge	163:e59c8e839560	159	#define RCC_FLAG_MASK ((uint8_t)0x1FU)
AnnaBridge	163:e59c8e839560	160
AnnaBridge	163:e59c8e839560	161	/**
AnnaBridge	163:e59c8e839560	162	* @}
AnnaBridge	163:e59c8e839560	163	*/
AnnaBridge	163:e59c8e839560	164
AnnaBridge	163:e59c8e839560	165	/** @addtogroup RCC_Private_Macros
AnnaBridge	163:e59c8e839560	166	* @{
AnnaBridge	163:e59c8e839560	167	*/
AnnaBridge	163:e59c8e839560	168	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	169	((__SOURCE__) == RCC_PLLSOURCE_HSE))
AnnaBridge	163:e59c8e839560	170	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
AnnaBridge	163:e59c8e839560	171	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
AnnaBridge	163:e59c8e839560	172	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	173	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
AnnaBridge	163:e59c8e839560	174	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
AnnaBridge	163:e59c8e839560	175	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
AnnaBridge	163:e59c8e839560	176	((__HSE__) == RCC_HSE_BYPASS))
AnnaBridge	163:e59c8e839560	177	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
AnnaBridge	163:e59c8e839560	178	((__LSE__) == RCC_LSE_BYPASS))
AnnaBridge	163:e59c8e839560	179	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
AnnaBridge	163:e59c8e839560	180	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
AnnaBridge	163:e59c8e839560	181	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
AnnaBridge	163:e59c8e839560	182	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
AnnaBridge	163:e59c8e839560	183	((__PLL__) == RCC_PLL_ON))
AnnaBridge	163:e59c8e839560	184	#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
AnnaBridge	163:e59c8e839560	185	#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) \|\| ((__PREDIV__) == RCC_PREDIV_DIV2) \|\| \
AnnaBridge	163:e59c8e839560	186	((__PREDIV__) == RCC_PREDIV_DIV3) \|\| ((__PREDIV__) == RCC_PREDIV_DIV4) \|\| \
AnnaBridge	163:e59c8e839560	187	((__PREDIV__) == RCC_PREDIV_DIV5) \|\| ((__PREDIV__) == RCC_PREDIV_DIV6) \|\| \
AnnaBridge	163:e59c8e839560	188	((__PREDIV__) == RCC_PREDIV_DIV7) \|\| ((__PREDIV__) == RCC_PREDIV_DIV8) \|\| \
AnnaBridge	163:e59c8e839560	189	((__PREDIV__) == RCC_PREDIV_DIV9) \|\| ((__PREDIV__) == RCC_PREDIV_DIV10) \|\| \
AnnaBridge	163:e59c8e839560	190	((__PREDIV__) == RCC_PREDIV_DIV11) \|\| ((__PREDIV__) == RCC_PREDIV_DIV12) \|\| \
AnnaBridge	163:e59c8e839560	191	((__PREDIV__) == RCC_PREDIV_DIV13) \|\| ((__PREDIV__) == RCC_PREDIV_DIV14) \|\| \
AnnaBridge	163:e59c8e839560	192	((__PREDIV__) == RCC_PREDIV_DIV15) \|\| ((__PREDIV__) == RCC_PREDIV_DIV16))
AnnaBridge	163:e59c8e839560	193	#else
AnnaBridge	163:e59c8e839560	194	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) \|\| \
AnnaBridge	163:e59c8e839560	195	((__DIV__) == RCC_PLL_DIV3) \|\| ((__DIV__) == RCC_PLL_DIV4))
AnnaBridge	163:e59c8e839560	196	#endif
AnnaBridge	163:e59c8e839560	197	#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
AnnaBridge	163:e59c8e839560	198	#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) \|\| ((DIV) == RCC_HSE_PREDIV_DIV2) \|\| \
AnnaBridge	163:e59c8e839560	199	((DIV) == RCC_HSE_PREDIV_DIV3) \|\| ((DIV) == RCC_HSE_PREDIV_DIV4) \|\| \
AnnaBridge	163:e59c8e839560	200	((DIV) == RCC_HSE_PREDIV_DIV5) \|\| ((DIV) == RCC_HSE_PREDIV_DIV6) \|\| \
AnnaBridge	163:e59c8e839560	201	((DIV) == RCC_HSE_PREDIV_DIV7) \|\| ((DIV) == RCC_HSE_PREDIV_DIV8) \|\| \
AnnaBridge	163:e59c8e839560	202	((DIV) == RCC_HSE_PREDIV_DIV9) \|\| ((DIV) == RCC_HSE_PREDIV_DIV10) \|\| \
AnnaBridge	163:e59c8e839560	203	((DIV) == RCC_HSE_PREDIV_DIV11) \|\| ((DIV) == RCC_HSE_PREDIV_DIV12) \|\| \
AnnaBridge	163:e59c8e839560	204	((DIV) == RCC_HSE_PREDIV_DIV13) \|\| ((DIV) == RCC_HSE_PREDIV_DIV14) \|\| \
AnnaBridge	163:e59c8e839560	205	((DIV) == RCC_HSE_PREDIV_DIV15) \|\| ((DIV) == RCC_HSE_PREDIV_DIV16))
AnnaBridge	163:e59c8e839560	206	#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
AnnaBridge	163:e59c8e839560	207
AnnaBridge	163:e59c8e839560	208	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) \|\| ((__MUL__) == RCC_PLL_MUL3) \|\| \
AnnaBridge	163:e59c8e839560	209	((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
AnnaBridge	163:e59c8e839560	210	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
AnnaBridge	163:e59c8e839560	211	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
AnnaBridge	163:e59c8e839560	212	((__MUL__) == RCC_PLL_MUL10) \|\| ((__MUL__) == RCC_PLL_MUL11) \|\| \
AnnaBridge	163:e59c8e839560	213	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL13) \|\| \
AnnaBridge	163:e59c8e839560	214	((__MUL__) == RCC_PLL_MUL14) \|\| ((__MUL__) == RCC_PLL_MUL15) \|\| \
AnnaBridge	163:e59c8e839560	215	((__MUL__) == RCC_PLL_MUL16))
AnnaBridge	163:e59c8e839560	216	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	217	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
AnnaBridge	163:e59c8e839560	218	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \|\| \
AnnaBridge	163:e59c8e839560	219	(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
AnnaBridge	163:e59c8e839560	220	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	221	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
AnnaBridge	163:e59c8e839560	222	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge	163:e59c8e839560	223	#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
AnnaBridge	163:e59c8e839560	224	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
AnnaBridge	163:e59c8e839560	225	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
AnnaBridge	163:e59c8e839560	226	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
AnnaBridge	163:e59c8e839560	227	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
AnnaBridge	163:e59c8e839560	228	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
AnnaBridge	163:e59c8e839560	229	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
AnnaBridge	163:e59c8e839560	230	((__HCLK__) == RCC_SYSCLK_DIV512))
AnnaBridge	163:e59c8e839560	231	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
AnnaBridge	163:e59c8e839560	232	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
AnnaBridge	163:e59c8e839560	233	((__PCLK__) == RCC_HCLK_DIV16))
AnnaBridge	163:e59c8e839560	234	#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
AnnaBridge	163:e59c8e839560	235	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
AnnaBridge	163:e59c8e839560	236	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	237	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
AnnaBridge	163:e59c8e839560	238	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
AnnaBridge	163:e59c8e839560	239	#if defined(RCC_CFGR3_USART2SW)
AnnaBridge	163:e59c8e839560	240	#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
AnnaBridge	163:e59c8e839560	241	((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	242	((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	243	((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	244	#endif /* RCC_CFGR3_USART2SW */
AnnaBridge	163:e59c8e839560	245	#if defined(RCC_CFGR3_USART3SW)
AnnaBridge	163:e59c8e839560	246	#define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
AnnaBridge	163:e59c8e839560	247	((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	163:e59c8e839560	248	((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) \|\| \
AnnaBridge	163:e59c8e839560	249	((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
AnnaBridge	163:e59c8e839560	250	#endif /* RCC_CFGR3_USART3SW */
AnnaBridge	163:e59c8e839560	251	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) \|\| \
AnnaBridge	163:e59c8e839560	252	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
AnnaBridge	163:e59c8e839560	253
AnnaBridge	163:e59c8e839560	254	/**
AnnaBridge	163:e59c8e839560	255	* @}
AnnaBridge	163:e59c8e839560	256	*/
AnnaBridge	163:e59c8e839560	257
AnnaBridge	163:e59c8e839560	258	/* Exported types ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	259
AnnaBridge	163:e59c8e839560	260	/** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge	163:e59c8e839560	261	* @{
AnnaBridge	163:e59c8e839560	262	*/
AnnaBridge	163:e59c8e839560	263
AnnaBridge	163:e59c8e839560	264	/**
AnnaBridge	163:e59c8e839560	265	* @brief RCC PLL configuration structure definition
AnnaBridge	163:e59c8e839560	266	*/
AnnaBridge	163:e59c8e839560	267	typedef struct
AnnaBridge	163:e59c8e839560	268	{
AnnaBridge	163:e59c8e839560	269	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
AnnaBridge	163:e59c8e839560	270	This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge	163:e59c8e839560	271
AnnaBridge	163:e59c8e839560	272	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
AnnaBridge	163:e59c8e839560	273	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	163:e59c8e839560	274
AnnaBridge	163:e59c8e839560	275	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
AnnaBridge	163:e59c8e839560	276	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
AnnaBridge	163:e59c8e839560	277
AnnaBridge	163:e59c8e839560	278	#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
AnnaBridge	163:e59c8e839560	279	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
AnnaBridge	163:e59c8e839560	280	This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
AnnaBridge	163:e59c8e839560	281
AnnaBridge	163:e59c8e839560	282	#endif
AnnaBridge	163:e59c8e839560	283	} RCC_PLLInitTypeDef;
AnnaBridge	163:e59c8e839560	284
AnnaBridge	163:e59c8e839560	285	/**
AnnaBridge	163:e59c8e839560	286	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
AnnaBridge	163:e59c8e839560	287	*/
AnnaBridge	163:e59c8e839560	288	typedef struct
AnnaBridge	163:e59c8e839560	289	{
AnnaBridge	163:e59c8e839560	290	uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge	163:e59c8e839560	291	This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge	163:e59c8e839560	292
AnnaBridge	163:e59c8e839560	293	uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge	163:e59c8e839560	294	This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge	163:e59c8e839560	295
AnnaBridge	163:e59c8e839560	296	#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
AnnaBridge	163:e59c8e839560	297	uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
AnnaBridge	163:e59c8e839560	298	This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */
AnnaBridge	163:e59c8e839560	299
AnnaBridge	163:e59c8e839560	300	#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
AnnaBridge	163:e59c8e839560	301	uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge	163:e59c8e839560	302	This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge	163:e59c8e839560	303
AnnaBridge	163:e59c8e839560	304	uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge	163:e59c8e839560	305	This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge	163:e59c8e839560	306
AnnaBridge	163:e59c8e839560	307	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	163:e59c8e839560	308	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
AnnaBridge	163:e59c8e839560	309
AnnaBridge	163:e59c8e839560	310	uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge	163:e59c8e839560	311	This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge	163:e59c8e839560	312
AnnaBridge	163:e59c8e839560	313	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
AnnaBridge	163:e59c8e839560	314
AnnaBridge	163:e59c8e839560	315	} RCC_OscInitTypeDef;
AnnaBridge	163:e59c8e839560	316
AnnaBridge	163:e59c8e839560	317	/**
AnnaBridge	163:e59c8e839560	318	* @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge	163:e59c8e839560	319	*/
AnnaBridge	163:e59c8e839560	320	typedef struct
AnnaBridge	163:e59c8e839560	321	{
AnnaBridge	163:e59c8e839560	322	uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge	163:e59c8e839560	323	This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge	163:e59c8e839560	324
AnnaBridge	163:e59c8e839560	325	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
AnnaBridge	163:e59c8e839560	326	This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge	163:e59c8e839560	327
AnnaBridge	163:e59c8e839560	328	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge	163:e59c8e839560	329	This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge	163:e59c8e839560	330
AnnaBridge	163:e59c8e839560	331	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	163:e59c8e839560	332	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	163:e59c8e839560	333
AnnaBridge	163:e59c8e839560	334	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	163:e59c8e839560	335	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	163:e59c8e839560	336	} RCC_ClkInitTypeDef;
AnnaBridge	163:e59c8e839560	337
AnnaBridge	163:e59c8e839560	338	/**
AnnaBridge	163:e59c8e839560	339	* @}
AnnaBridge	163:e59c8e839560	340	*/
AnnaBridge	163:e59c8e839560	341
AnnaBridge	163:e59c8e839560	342	/* Exported constants --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	343	/** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge	163:e59c8e839560	344	* @{
AnnaBridge	163:e59c8e839560	345	*/
AnnaBridge	163:e59c8e839560	346
AnnaBridge	163:e59c8e839560	347	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge	163:e59c8e839560	348	* @{
AnnaBridge	163:e59c8e839560	349	*/
AnnaBridge	163:e59c8e839560	350
AnnaBridge	163:e59c8e839560	351	#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
AnnaBridge	163:e59c8e839560	352	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /!< HSI clock selected as PLL entry clock source /
AnnaBridge	163:e59c8e839560	353	#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
AnnaBridge	163:e59c8e839560	354	#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
AnnaBridge	163:e59c8e839560	355	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 /!< HSI clock divided by 2 selected as PLL entry clock source /
AnnaBridge	163:e59c8e839560	356	#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
AnnaBridge	163:e59c8e839560	357	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /!< HSE clock selected as PLL entry clock source /
AnnaBridge	163:e59c8e839560	358
AnnaBridge	163:e59c8e839560	359	/**
AnnaBridge	163:e59c8e839560	360	* @}
AnnaBridge	163:e59c8e839560	361	*/
AnnaBridge	163:e59c8e839560	362
AnnaBridge	163:e59c8e839560	363	/** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge	163:e59c8e839560	364	* @{
AnnaBridge	163:e59c8e839560	365	*/
AnnaBridge	163:e59c8e839560	366	#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
AnnaBridge	163:e59c8e839560	367	#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
AnnaBridge	163:e59c8e839560	368	#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
AnnaBridge	163:e59c8e839560	369	#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
AnnaBridge	163:e59c8e839560	370	#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
AnnaBridge	163:e59c8e839560	371	/**
AnnaBridge	163:e59c8e839560	372	* @}
AnnaBridge	163:e59c8e839560	373	*/
AnnaBridge	163:e59c8e839560	374
AnnaBridge	163:e59c8e839560	375	/** @defgroup RCC_HSE_Config HSE Config
AnnaBridge	163:e59c8e839560	376	* @{
AnnaBridge	163:e59c8e839560	377	*/
AnnaBridge	163:e59c8e839560	378	#define RCC_HSE_OFF (0x00000000U) /!< HSE clock deactivation /
AnnaBridge	163:e59c8e839560	379	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
AnnaBridge	163:e59c8e839560	380	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
AnnaBridge	163:e59c8e839560	381	/**
AnnaBridge	163:e59c8e839560	382	* @}
AnnaBridge	163:e59c8e839560	383	*/
AnnaBridge	163:e59c8e839560	384
AnnaBridge	163:e59c8e839560	385	/** @defgroup RCC_LSE_Config LSE Config
AnnaBridge	163:e59c8e839560	386	* @{
AnnaBridge	163:e59c8e839560	387	*/
AnnaBridge	163:e59c8e839560	388	#define RCC_LSE_OFF (0x00000000U) /!< LSE clock deactivation /
AnnaBridge	163:e59c8e839560	389	#define RCC_LSE_ON RCC_BDCR_LSEON /!< LSE clock activation /
AnnaBridge	163:e59c8e839560	390	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON)) /!< External clock source for LSE clock /
AnnaBridge	163:e59c8e839560	391
AnnaBridge	163:e59c8e839560	392	/**
AnnaBridge	163:e59c8e839560	393	* @}
AnnaBridge	163:e59c8e839560	394	*/
AnnaBridge	163:e59c8e839560	395
AnnaBridge	163:e59c8e839560	396	/** @defgroup RCC_HSI_Config HSI Config
AnnaBridge	163:e59c8e839560	397	* @{
AnnaBridge	163:e59c8e839560	398	*/
AnnaBridge	163:e59c8e839560	399	#define RCC_HSI_OFF (0x00000000U) /!< HSI clock deactivation /
AnnaBridge	163:e59c8e839560	400	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
AnnaBridge	163:e59c8e839560	401
AnnaBridge	163:e59c8e839560	402	#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
AnnaBridge	163:e59c8e839560	403
AnnaBridge	163:e59c8e839560	404	/**
AnnaBridge	163:e59c8e839560	405	* @}
AnnaBridge	163:e59c8e839560	406	*/
AnnaBridge	163:e59c8e839560	407
AnnaBridge	163:e59c8e839560	408	/** @defgroup RCC_LSI_Config LSI Config
AnnaBridge	163:e59c8e839560	409	* @{
AnnaBridge	163:e59c8e839560	410	*/
AnnaBridge	163:e59c8e839560	411	#define RCC_LSI_OFF (0x00000000U) /!< LSI clock deactivation /
AnnaBridge	163:e59c8e839560	412	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
AnnaBridge	163:e59c8e839560	413
AnnaBridge	163:e59c8e839560	414	/**
AnnaBridge	163:e59c8e839560	415	* @}
AnnaBridge	163:e59c8e839560	416	*/
AnnaBridge	163:e59c8e839560	417
AnnaBridge	163:e59c8e839560	418	/** @defgroup RCC_PLL_Config PLL Config
AnnaBridge	163:e59c8e839560	419	* @{
AnnaBridge	163:e59c8e839560	420	*/
AnnaBridge	163:e59c8e839560	421	#define RCC_PLL_NONE (0x00000000U) /!< PLL is not configured /
AnnaBridge	163:e59c8e839560	422	#define RCC_PLL_OFF (0x00000001U) /!< PLL deactivation /
AnnaBridge	163:e59c8e839560	423	#define RCC_PLL_ON (0x00000002U) /!< PLL activation /
AnnaBridge	163:e59c8e839560	424
AnnaBridge	163:e59c8e839560	425	/**
AnnaBridge	163:e59c8e839560	426	* @}
AnnaBridge	163:e59c8e839560	427	*/
AnnaBridge	163:e59c8e839560	428
AnnaBridge	163:e59c8e839560	429	/** @defgroup RCC_System_Clock_Type System Clock Type
AnnaBridge	163:e59c8e839560	430	* @{
AnnaBridge	163:e59c8e839560	431	*/
AnnaBridge	163:e59c8e839560	432	#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /!< SYSCLK to configure /
AnnaBridge	163:e59c8e839560	433	#define RCC_CLOCKTYPE_HCLK (0x00000002U) /!< HCLK to configure /
AnnaBridge	163:e59c8e839560	434	#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /!< PCLK1 to configure /
AnnaBridge	163:e59c8e839560	435	#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /!< PCLK2 to configure /
AnnaBridge	163:e59c8e839560	436
AnnaBridge	163:e59c8e839560	437	/**
AnnaBridge	163:e59c8e839560	438	* @}
AnnaBridge	163:e59c8e839560	439	*/
AnnaBridge	163:e59c8e839560	440
AnnaBridge	163:e59c8e839560	441	/** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge	163:e59c8e839560	442	* @{
AnnaBridge	163:e59c8e839560	443	*/
AnnaBridge	163:e59c8e839560	444	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
AnnaBridge	163:e59c8e839560	445	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
AnnaBridge	163:e59c8e839560	446	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
AnnaBridge	163:e59c8e839560	447
AnnaBridge	163:e59c8e839560	448	/**
AnnaBridge	163:e59c8e839560	449	* @}
AnnaBridge	163:e59c8e839560	450	*/
AnnaBridge	163:e59c8e839560	451
AnnaBridge	163:e59c8e839560	452	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge	163:e59c8e839560	453	* @{
AnnaBridge	163:e59c8e839560	454	*/
AnnaBridge	163:e59c8e839560	455	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	163:e59c8e839560	456	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	163:e59c8e839560	457	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	163:e59c8e839560	458
AnnaBridge	163:e59c8e839560	459	/**
AnnaBridge	163:e59c8e839560	460	* @}
AnnaBridge	163:e59c8e839560	461	*/
AnnaBridge	163:e59c8e839560	462
AnnaBridge	163:e59c8e839560	463	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
AnnaBridge	163:e59c8e839560	464	* @{
AnnaBridge	163:e59c8e839560	465	*/
AnnaBridge	163:e59c8e839560	466	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	163:e59c8e839560	467	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	163:e59c8e839560	468	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	163:e59c8e839560	469	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	163:e59c8e839560	470	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	163:e59c8e839560	471	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	163:e59c8e839560	472	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	163:e59c8e839560	473	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	163:e59c8e839560	474	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	163:e59c8e839560	475
AnnaBridge	163:e59c8e839560	476	/**
AnnaBridge	163:e59c8e839560	477	* @}
AnnaBridge	163:e59c8e839560	478	*/
AnnaBridge	163:e59c8e839560	479
AnnaBridge	163:e59c8e839560	480	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
AnnaBridge	163:e59c8e839560	481	* @{
AnnaBridge	163:e59c8e839560	482	*/
AnnaBridge	163:e59c8e839560	483	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	163:e59c8e839560	484	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	163:e59c8e839560	485	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	163:e59c8e839560	486	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	163:e59c8e839560	487	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	163:e59c8e839560	488
AnnaBridge	163:e59c8e839560	489	/**
AnnaBridge	163:e59c8e839560	490	* @}
AnnaBridge	163:e59c8e839560	491	*/
AnnaBridge	163:e59c8e839560	492
AnnaBridge	163:e59c8e839560	493	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
AnnaBridge	163:e59c8e839560	494	* @{
AnnaBridge	163:e59c8e839560	495	*/
AnnaBridge	163:e59c8e839560	496	#define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK /!< No clock /
AnnaBridge	163:e59c8e839560	497	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
AnnaBridge	163:e59c8e839560	498	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
AnnaBridge	163:e59c8e839560	499	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /!< HSE oscillator clock divided by 32 used as RTC clock /
AnnaBridge	163:e59c8e839560	500	/**
AnnaBridge	163:e59c8e839560	501	* @}
AnnaBridge	163:e59c8e839560	502	*/
AnnaBridge	163:e59c8e839560	503
AnnaBridge	163:e59c8e839560	504	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
AnnaBridge	163:e59c8e839560	505	* @{
AnnaBridge	163:e59c8e839560	506	*/
AnnaBridge	163:e59c8e839560	507	#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
AnnaBridge	163:e59c8e839560	508	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
AnnaBridge	163:e59c8e839560	509	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
AnnaBridge	163:e59c8e839560	510	#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
AnnaBridge	163:e59c8e839560	511	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
AnnaBridge	163:e59c8e839560	512	#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
AnnaBridge	163:e59c8e839560	513	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
AnnaBridge	163:e59c8e839560	514	#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
AnnaBridge	163:e59c8e839560	515	#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
AnnaBridge	163:e59c8e839560	516	#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
AnnaBridge	163:e59c8e839560	517	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
AnnaBridge	163:e59c8e839560	518	#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
AnnaBridge	163:e59c8e839560	519	#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
AnnaBridge	163:e59c8e839560	520	#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
AnnaBridge	163:e59c8e839560	521	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
AnnaBridge	163:e59c8e839560	522
AnnaBridge	163:e59c8e839560	523	/**
AnnaBridge	163:e59c8e839560	524	* @}
AnnaBridge	163:e59c8e839560	525	*/
AnnaBridge	163:e59c8e839560	526
AnnaBridge	163:e59c8e839560	527	#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
AnnaBridge	163:e59c8e839560	528	/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
AnnaBridge	163:e59c8e839560	529	* @{
AnnaBridge	163:e59c8e839560	530	*/
AnnaBridge	163:e59c8e839560	531
AnnaBridge	163:e59c8e839560	532	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
AnnaBridge	163:e59c8e839560	533	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
AnnaBridge	163:e59c8e839560	534	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
AnnaBridge	163:e59c8e839560	535	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
AnnaBridge	163:e59c8e839560	536	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
AnnaBridge	163:e59c8e839560	537	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
AnnaBridge	163:e59c8e839560	538	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
AnnaBridge	163:e59c8e839560	539	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
AnnaBridge	163:e59c8e839560	540	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
AnnaBridge	163:e59c8e839560	541	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
AnnaBridge	163:e59c8e839560	542	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
AnnaBridge	163:e59c8e839560	543	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
AnnaBridge	163:e59c8e839560	544	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
AnnaBridge	163:e59c8e839560	545	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
AnnaBridge	163:e59c8e839560	546	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
AnnaBridge	163:e59c8e839560	547	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
AnnaBridge	163:e59c8e839560	548
AnnaBridge	163:e59c8e839560	549	/**
AnnaBridge	163:e59c8e839560	550	* @}
AnnaBridge	163:e59c8e839560	551	*/
AnnaBridge	163:e59c8e839560	552
AnnaBridge	163:e59c8e839560	553	#endif
AnnaBridge	163:e59c8e839560	554	#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
AnnaBridge	163:e59c8e839560	555	/** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor
AnnaBridge	163:e59c8e839560	556	* @{
AnnaBridge	163:e59c8e839560	557	*/
AnnaBridge	163:e59c8e839560	558
AnnaBridge	163:e59c8e839560	559	#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
AnnaBridge	163:e59c8e839560	560	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
AnnaBridge	163:e59c8e839560	561	#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
AnnaBridge	163:e59c8e839560	562	#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
AnnaBridge	163:e59c8e839560	563	#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
AnnaBridge	163:e59c8e839560	564	#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
AnnaBridge	163:e59c8e839560	565	#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
AnnaBridge	163:e59c8e839560	566	#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
AnnaBridge	163:e59c8e839560	567	#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
AnnaBridge	163:e59c8e839560	568	#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
AnnaBridge	163:e59c8e839560	569	#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
AnnaBridge	163:e59c8e839560	570	#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
AnnaBridge	163:e59c8e839560	571	#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
AnnaBridge	163:e59c8e839560	572	#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
AnnaBridge	163:e59c8e839560	573	#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
AnnaBridge	163:e59c8e839560	574	#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
AnnaBridge	163:e59c8e839560	575
AnnaBridge	163:e59c8e839560	576	/**
AnnaBridge	163:e59c8e839560	577	* @}
AnnaBridge	163:e59c8e839560	578	*/
AnnaBridge	163:e59c8e839560	579	#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
AnnaBridge	163:e59c8e839560	580
AnnaBridge	163:e59c8e839560	581	#if defined(RCC_CFGR3_USART2SW)
AnnaBridge	163:e59c8e839560	582	/** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
AnnaBridge	163:e59c8e839560	583	* @{
AnnaBridge	163:e59c8e839560	584	*/
AnnaBridge	163:e59c8e839560	585	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
AnnaBridge	163:e59c8e839560	586	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
AnnaBridge	163:e59c8e839560	587	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
AnnaBridge	163:e59c8e839560	588	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
AnnaBridge	163:e59c8e839560	589
AnnaBridge	163:e59c8e839560	590	/**
AnnaBridge	163:e59c8e839560	591	* @}
AnnaBridge	163:e59c8e839560	592	*/
AnnaBridge	163:e59c8e839560	593	#endif /* RCC_CFGR3_USART2SW */
AnnaBridge	163:e59c8e839560	594
AnnaBridge	163:e59c8e839560	595	#if defined(RCC_CFGR3_USART3SW)
AnnaBridge	163:e59c8e839560	596	/** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
AnnaBridge	163:e59c8e839560	597	* @{
AnnaBridge	163:e59c8e839560	598	*/
AnnaBridge	163:e59c8e839560	599	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
AnnaBridge	163:e59c8e839560	600	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
AnnaBridge	163:e59c8e839560	601	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
AnnaBridge	163:e59c8e839560	602	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
AnnaBridge	163:e59c8e839560	603
AnnaBridge	163:e59c8e839560	604	/**
AnnaBridge	163:e59c8e839560	605	* @}
AnnaBridge	163:e59c8e839560	606	*/
AnnaBridge	163:e59c8e839560	607	#endif /* RCC_CFGR3_USART3SW */
AnnaBridge	163:e59c8e839560	608
AnnaBridge	163:e59c8e839560	609	/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
AnnaBridge	163:e59c8e839560	610	* @{
AnnaBridge	163:e59c8e839560	611	*/
AnnaBridge	163:e59c8e839560	612	#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
AnnaBridge	163:e59c8e839560	613	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
AnnaBridge	163:e59c8e839560	614
AnnaBridge	163:e59c8e839560	615	/**
AnnaBridge	163:e59c8e839560	616	* @}
AnnaBridge	163:e59c8e839560	617	*/
AnnaBridge	163:e59c8e839560	618	/** @defgroup RCC_MCO_Index MCO Index
AnnaBridge	163:e59c8e839560	619	* @{
AnnaBridge	163:e59c8e839560	620	*/
AnnaBridge	163:e59c8e839560	621	#define RCC_MCO1 (0x00000000U)
AnnaBridge	163:e59c8e839560	622	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
AnnaBridge	163:e59c8e839560	623
AnnaBridge	163:e59c8e839560	624	/**
AnnaBridge	163:e59c8e839560	625	* @}
AnnaBridge	163:e59c8e839560	626	*/
AnnaBridge	163:e59c8e839560	627
AnnaBridge	163:e59c8e839560	628	/** @defgroup RCC_Interrupt Interrupts
AnnaBridge	163:e59c8e839560	629	* @{
AnnaBridge	163:e59c8e839560	630	*/
AnnaBridge	163:e59c8e839560	631	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
AnnaBridge	163:e59c8e839560	632	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
AnnaBridge	163:e59c8e839560	633	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
AnnaBridge	163:e59c8e839560	634	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
AnnaBridge	163:e59c8e839560	635	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
AnnaBridge	163:e59c8e839560	636	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
AnnaBridge	163:e59c8e839560	637	/**
AnnaBridge	163:e59c8e839560	638	* @}
AnnaBridge	163:e59c8e839560	639	*/
AnnaBridge	163:e59c8e839560	640
AnnaBridge	163:e59c8e839560	641	/** @defgroup RCC_Flag Flags
AnnaBridge	163:e59c8e839560	642	* Elements values convention: XXXYYYYYb
AnnaBridge	163:e59c8e839560	643	* - YYYYY : Flag position in the register
AnnaBridge	163:e59c8e839560	644	* - XXX : Register index
AnnaBridge	163:e59c8e839560	645	* - 001: CR register
AnnaBridge	163:e59c8e839560	646	* - 010: BDCR register
AnnaBridge	163:e59c8e839560	647	* - 011: CSR register
AnnaBridge	163:e59c8e839560	648	* - 100: CFGR register
AnnaBridge	163:e59c8e839560	649	* @{
AnnaBridge	163:e59c8e839560	650	*/
AnnaBridge	163:e59c8e839560	651	/* Flags in the CR register */
AnnaBridge	163:e59c8e839560	652	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< Internal High Speed clock ready flag /
AnnaBridge	163:e59c8e839560	653	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_HSERDY))) /!< External High Speed clock ready flag /
AnnaBridge	163:e59c8e839560	654	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL clock ready flag /
AnnaBridge	163:e59c8e839560	655
AnnaBridge	163:e59c8e839560	656	/* Flags in the CSR register */
AnnaBridge	163:e59c8e839560	657	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< Internal Low Speed oscillator Ready /
AnnaBridge	163:e59c8e839560	658	#if defined(RCC_CSR_V18PWRRSTF)
AnnaBridge	163:e59c8e839560	659	#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_V18PWRRSTF)))
AnnaBridge	163:e59c8e839560	660	#endif
AnnaBridge	163:e59c8e839560	661	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_OBLRSTF))) /!< Options bytes loading reset flag /
AnnaBridge	163:e59c8e839560	662	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
AnnaBridge	163:e59c8e839560	663	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_PORRSTF))) /!< POR/PDR reset flag /
AnnaBridge	163:e59c8e839560	664	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
AnnaBridge	163:e59c8e839560	665	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
AnnaBridge	163:e59c8e839560	666	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
AnnaBridge	163:e59c8e839560	667	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
AnnaBridge	163:e59c8e839560	668
AnnaBridge	163:e59c8e839560	669	/* Flags in the BDCR register */
AnnaBridge	163:e59c8e839560	670	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< External Low Speed oscillator Ready /
AnnaBridge	163:e59c8e839560	671
AnnaBridge	163:e59c8e839560	672	/* Flags in the CFGR register */
AnnaBridge	163:e59c8e839560	673	#if defined(RCC_CFGR_MCOF)
AnnaBridge	163:e59c8e839560	674	#define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CFGR_MCOF))) /!< Microcontroller Clock Output Flag /
AnnaBridge	163:e59c8e839560	675	#endif /* RCC_CFGR_MCOF */
AnnaBridge	163:e59c8e839560	676
AnnaBridge	163:e59c8e839560	677	/**
AnnaBridge	163:e59c8e839560	678	* @}
AnnaBridge	163:e59c8e839560	679	*/
AnnaBridge	163:e59c8e839560	680
AnnaBridge	163:e59c8e839560	681	/**
AnnaBridge	163:e59c8e839560	682	* @}
AnnaBridge	163:e59c8e839560	683	*/
AnnaBridge	163:e59c8e839560	684
AnnaBridge	163:e59c8e839560	685	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	686
AnnaBridge	163:e59c8e839560	687	/** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge	163:e59c8e839560	688	* @{
AnnaBridge	163:e59c8e839560	689	*/
AnnaBridge	163:e59c8e839560	690
AnnaBridge	163:e59c8e839560	691	/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
AnnaBridge	163:e59c8e839560	692	* @brief Enable or disable the AHB peripheral clock.
AnnaBridge	163:e59c8e839560	693	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	694	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	695	* using it.
AnnaBridge	163:e59c8e839560	696	* @{
AnnaBridge	163:e59c8e839560	697	*/
AnnaBridge	163:e59c8e839560	698	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	699	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	700	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
AnnaBridge	163:e59c8e839560	701	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	702	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
AnnaBridge	163:e59c8e839560	703	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	704	} while(0U)
AnnaBridge	163:e59c8e839560	705	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	706	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	707	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
AnnaBridge	163:e59c8e839560	708	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	709	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
AnnaBridge	163:e59c8e839560	710	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	711	} while(0U)
AnnaBridge	163:e59c8e839560	712	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	713	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	714	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
AnnaBridge	163:e59c8e839560	715	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	716	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
AnnaBridge	163:e59c8e839560	717	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	718	} while(0U)
AnnaBridge	163:e59c8e839560	719	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	720	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	721	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	722	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	723	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
AnnaBridge	163:e59c8e839560	724	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	725	} while(0U)
AnnaBridge	163:e59c8e839560	726	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	727	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	728	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
AnnaBridge	163:e59c8e839560	729	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	730	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
AnnaBridge	163:e59c8e839560	731	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	732	} while(0U)
AnnaBridge	163:e59c8e839560	733	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	734	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	735	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge	163:e59c8e839560	736	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	737	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge	163:e59c8e839560	738	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	739	} while(0U)
AnnaBridge	163:e59c8e839560	740	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	741	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	742	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge	163:e59c8e839560	743	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	744	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge	163:e59c8e839560	745	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	746	} while(0U)
AnnaBridge	163:e59c8e839560	747	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	748	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	749	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
AnnaBridge	163:e59c8e839560	750	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	751	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
AnnaBridge	163:e59c8e839560	752	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	753	} while(0U)
AnnaBridge	163:e59c8e839560	754	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	755	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	756	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
AnnaBridge	163:e59c8e839560	757	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	758	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
AnnaBridge	163:e59c8e839560	759	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	760	} while(0U)
AnnaBridge	163:e59c8e839560	761	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	762	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	763	SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
AnnaBridge	163:e59c8e839560	764	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	765	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
AnnaBridge	163:e59c8e839560	766	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	767	} while(0U)
AnnaBridge	163:e59c8e839560	768
AnnaBridge	163:e59c8e839560	769	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
AnnaBridge	163:e59c8e839560	770	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
AnnaBridge	163:e59c8e839560	771	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
AnnaBridge	163:e59c8e839560	772	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
AnnaBridge	163:e59c8e839560	773	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
AnnaBridge	163:e59c8e839560	774	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
AnnaBridge	163:e59c8e839560	775	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
AnnaBridge	163:e59c8e839560	776	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
AnnaBridge	163:e59c8e839560	777	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
AnnaBridge	163:e59c8e839560	778	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
AnnaBridge	163:e59c8e839560	779	/**
AnnaBridge	163:e59c8e839560	780	* @}
AnnaBridge	163:e59c8e839560	781	*/
AnnaBridge	163:e59c8e839560	782
AnnaBridge	163:e59c8e839560	783	/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
AnnaBridge	163:e59c8e839560	784	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	163:e59c8e839560	785	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	786	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	787	* using it.
AnnaBridge	163:e59c8e839560	788	* @{
AnnaBridge	163:e59c8e839560	789	*/
AnnaBridge	163:e59c8e839560	790	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	791	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	792	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	793	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	794	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	163:e59c8e839560	795	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	796	} while(0U)
AnnaBridge	163:e59c8e839560	797	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	798	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	799	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	800	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	801	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	163:e59c8e839560	802	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	803	} while(0U)
AnnaBridge	163:e59c8e839560	804	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	805	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	806	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge	163:e59c8e839560	807	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	808	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge	163:e59c8e839560	809	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	810	} while(0U)
AnnaBridge	163:e59c8e839560	811	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	812	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	813	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge	163:e59c8e839560	814	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	815	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge	163:e59c8e839560	816	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	817	} while(0U)
AnnaBridge	163:e59c8e839560	818	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	819	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	820	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	163:e59c8e839560	821	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	822	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	163:e59c8e839560	823	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	824	} while(0U)
AnnaBridge	163:e59c8e839560	825	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	826	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	827	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge	163:e59c8e839560	828	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	829	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge	163:e59c8e839560	830	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	831	} while(0U)
AnnaBridge	163:e59c8e839560	832	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	833	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	834	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge	163:e59c8e839560	835	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	836	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge	163:e59c8e839560	837	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	838	} while(0U)
AnnaBridge	163:e59c8e839560	839	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	840	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	841	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
AnnaBridge	163:e59c8e839560	842	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	843	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
AnnaBridge	163:e59c8e839560	844	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	845	} while(0U)
AnnaBridge	163:e59c8e839560	846
AnnaBridge	163:e59c8e839560	847	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	163:e59c8e839560	848	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	163:e59c8e839560	849	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
AnnaBridge	163:e59c8e839560	850	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
AnnaBridge	163:e59c8e839560	851	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	163:e59c8e839560	852	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
AnnaBridge	163:e59c8e839560	853	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
AnnaBridge	163:e59c8e839560	854	#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
AnnaBridge	163:e59c8e839560	855	/**
AnnaBridge	163:e59c8e839560	856	* @}
AnnaBridge	163:e59c8e839560	857	*/
AnnaBridge	163:e59c8e839560	858
AnnaBridge	163:e59c8e839560	859	/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
AnnaBridge	163:e59c8e839560	860	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	163:e59c8e839560	861	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	862	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	863	* using it.
AnnaBridge	163:e59c8e839560	864	* @{
AnnaBridge	163:e59c8e839560	865	*/
AnnaBridge	163:e59c8e839560	866	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	867	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	868	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge	163:e59c8e839560	869	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	870	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge	163:e59c8e839560	871	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	872	} while(0U)
AnnaBridge	163:e59c8e839560	873	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	874	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	875	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
AnnaBridge	163:e59c8e839560	876	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	877	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
AnnaBridge	163:e59c8e839560	878	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	879	} while(0U)
AnnaBridge	163:e59c8e839560	880	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	881	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	882	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
AnnaBridge	163:e59c8e839560	883	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	884	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
AnnaBridge	163:e59c8e839560	885	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	886	} while(0U)
AnnaBridge	163:e59c8e839560	887	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	888	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	889	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
AnnaBridge	163:e59c8e839560	890	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	891	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
AnnaBridge	163:e59c8e839560	892	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	893	} while(0U)
AnnaBridge	163:e59c8e839560	894	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge	163:e59c8e839560	895	__IO uint32_t tmpreg; \
AnnaBridge	163:e59c8e839560	896	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge	163:e59c8e839560	897	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	163:e59c8e839560	898	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge	163:e59c8e839560	899	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	900	} while(0U)
AnnaBridge	163:e59c8e839560	901
AnnaBridge	163:e59c8e839560	902	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
AnnaBridge	163:e59c8e839560	903	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
AnnaBridge	163:e59c8e839560	904	#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
AnnaBridge	163:e59c8e839560	905	#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
AnnaBridge	163:e59c8e839560	906	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
AnnaBridge	163:e59c8e839560	907	/**
AnnaBridge	163:e59c8e839560	908	* @}
AnnaBridge	163:e59c8e839560	909	*/
AnnaBridge	163:e59c8e839560	910
AnnaBridge	163:e59c8e839560	911	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	912	* @brief Get the enable or disable status of the AHB peripheral clock.
AnnaBridge	163:e59c8e839560	913	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	914	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	915	* using it.
AnnaBridge	163:e59c8e839560	916	* @{
AnnaBridge	163:e59c8e839560	917	*/
AnnaBridge	163:e59c8e839560	918	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
AnnaBridge	163:e59c8e839560	919	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
AnnaBridge	163:e59c8e839560	920	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
AnnaBridge	163:e59c8e839560	921	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
AnnaBridge	163:e59c8e839560	922	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
AnnaBridge	163:e59c8e839560	923	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
AnnaBridge	163:e59c8e839560	924	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
AnnaBridge	163:e59c8e839560	925	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
AnnaBridge	163:e59c8e839560	926	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
AnnaBridge	163:e59c8e839560	927	#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
AnnaBridge	163:e59c8e839560	928
AnnaBridge	163:e59c8e839560	929	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
AnnaBridge	163:e59c8e839560	930	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
AnnaBridge	163:e59c8e839560	931	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
AnnaBridge	163:e59c8e839560	932	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
AnnaBridge	163:e59c8e839560	933	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
AnnaBridge	163:e59c8e839560	934	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
AnnaBridge	163:e59c8e839560	935	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
AnnaBridge	163:e59c8e839560	936	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
AnnaBridge	163:e59c8e839560	937	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
AnnaBridge	163:e59c8e839560	938	#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
AnnaBridge	163:e59c8e839560	939	/**
AnnaBridge	163:e59c8e839560	940	* @}
AnnaBridge	163:e59c8e839560	941	*/
AnnaBridge	163:e59c8e839560	942
AnnaBridge	163:e59c8e839560	943	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	944	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	163:e59c8e839560	945	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	946	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	947	* using it.
AnnaBridge	163:e59c8e839560	948	* @{
AnnaBridge	163:e59c8e839560	949	*/
AnnaBridge	163:e59c8e839560	950	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	163:e59c8e839560	951	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	163:e59c8e839560	952	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
AnnaBridge	163:e59c8e839560	953	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
AnnaBridge	163:e59c8e839560	954	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	163:e59c8e839560	955	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
AnnaBridge	163:e59c8e839560	956	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
AnnaBridge	163:e59c8e839560	957	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
AnnaBridge	163:e59c8e839560	958
AnnaBridge	163:e59c8e839560	959	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	163:e59c8e839560	960	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	163:e59c8e839560	961	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
AnnaBridge	163:e59c8e839560	962	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
AnnaBridge	163:e59c8e839560	963	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	163:e59c8e839560	964	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
AnnaBridge	163:e59c8e839560	965	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
AnnaBridge	163:e59c8e839560	966	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
AnnaBridge	163:e59c8e839560	967	/**
AnnaBridge	163:e59c8e839560	968	* @}
AnnaBridge	163:e59c8e839560	969	*/
AnnaBridge	163:e59c8e839560	970
AnnaBridge	163:e59c8e839560	971	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	163:e59c8e839560	972	* @brief EGet the enable or disable status of the APB2 peripheral clock.
AnnaBridge	163:e59c8e839560	973	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	163:e59c8e839560	974	* is disabled and the application software has to enable this clock before
AnnaBridge	163:e59c8e839560	975	* using it.
AnnaBridge	163:e59c8e839560	976	* @{
AnnaBridge	163:e59c8e839560	977	*/
AnnaBridge	163:e59c8e839560	978	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
AnnaBridge	163:e59c8e839560	979	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
AnnaBridge	163:e59c8e839560	980	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
AnnaBridge	163:e59c8e839560	981	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
AnnaBridge	163:e59c8e839560	982	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
AnnaBridge	163:e59c8e839560	983
AnnaBridge	163:e59c8e839560	984	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
AnnaBridge	163:e59c8e839560	985	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
AnnaBridge	163:e59c8e839560	986	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
AnnaBridge	163:e59c8e839560	987	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
AnnaBridge	163:e59c8e839560	988	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
AnnaBridge	163:e59c8e839560	989	/**
AnnaBridge	163:e59c8e839560	990	* @}
AnnaBridge	163:e59c8e839560	991	*/
AnnaBridge	163:e59c8e839560	992
AnnaBridge	163:e59c8e839560	993	/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
AnnaBridge	163:e59c8e839560	994	* @brief Force or release AHB peripheral reset.
AnnaBridge	163:e59c8e839560	995	* @{
AnnaBridge	163:e59c8e839560	996	*/
AnnaBridge	163:e59c8e839560	997	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	998	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
AnnaBridge	163:e59c8e839560	999	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
AnnaBridge	163:e59c8e839560	1000	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
AnnaBridge	163:e59c8e839560	1001	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	1002	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOFRST))
AnnaBridge	163:e59c8e839560	1003	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
AnnaBridge	163:e59c8e839560	1004
AnnaBridge	163:e59c8e839560	1005	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
AnnaBridge	163:e59c8e839560	1006	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
AnnaBridge	163:e59c8e839560	1007	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
AnnaBridge	163:e59c8e839560	1008	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
AnnaBridge	163:e59c8e839560	1009	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
AnnaBridge	163:e59c8e839560	1010	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
AnnaBridge	163:e59c8e839560	1011	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
AnnaBridge	163:e59c8e839560	1012	/**
AnnaBridge	163:e59c8e839560	1013	* @}
AnnaBridge	163:e59c8e839560	1014	*/
AnnaBridge	163:e59c8e839560	1015
AnnaBridge	163:e59c8e839560	1016	/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
AnnaBridge	163:e59c8e839560	1017	* @brief Force or release APB1 peripheral reset.
AnnaBridge	163:e59c8e839560	1018	* @{
AnnaBridge	163:e59c8e839560	1019	*/
AnnaBridge	163:e59c8e839560	1020	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	1021	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	1022	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	1023	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
AnnaBridge	163:e59c8e839560	1024	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
AnnaBridge	163:e59c8e839560	1025	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	163:e59c8e839560	1026	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
AnnaBridge	163:e59c8e839560	1027	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
AnnaBridge	163:e59c8e839560	1028	#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC1RST))
AnnaBridge	163:e59c8e839560	1029
AnnaBridge	163:e59c8e839560	1030	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
AnnaBridge	163:e59c8e839560	1031	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	163:e59c8e839560	1032	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	163:e59c8e839560	1033	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
AnnaBridge	163:e59c8e839560	1034	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
AnnaBridge	163:e59c8e839560	1035	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	163:e59c8e839560	1036	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
AnnaBridge	163:e59c8e839560	1037	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
AnnaBridge	163:e59c8e839560	1038	#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
AnnaBridge	163:e59c8e839560	1039	/**
AnnaBridge	163:e59c8e839560	1040	* @}
AnnaBridge	163:e59c8e839560	1041	*/
AnnaBridge	163:e59c8e839560	1042
AnnaBridge	163:e59c8e839560	1043	/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
AnnaBridge	163:e59c8e839560	1044	* @brief Force or release APB2 peripheral reset.
AnnaBridge	163:e59c8e839560	1045	* @{
AnnaBridge	163:e59c8e839560	1046	*/
AnnaBridge	163:e59c8e839560	1047	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge	163:e59c8e839560	1048	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	163:e59c8e839560	1049	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
AnnaBridge	163:e59c8e839560	1050	#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
AnnaBridge	163:e59c8e839560	1051	#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
AnnaBridge	163:e59c8e839560	1052	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
AnnaBridge	163:e59c8e839560	1053
AnnaBridge	163:e59c8e839560	1054	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
AnnaBridge	163:e59c8e839560	1055	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	163:e59c8e839560	1056	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
AnnaBridge	163:e59c8e839560	1057	#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
AnnaBridge	163:e59c8e839560	1058	#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
AnnaBridge	163:e59c8e839560	1059	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
AnnaBridge	163:e59c8e839560	1060	/**
AnnaBridge	163:e59c8e839560	1061	* @}
AnnaBridge	163:e59c8e839560	1062	*/
AnnaBridge	163:e59c8e839560	1063
AnnaBridge	163:e59c8e839560	1064	/** @defgroup RCC_HSI_Configuration HSI Configuration
AnnaBridge	163:e59c8e839560	1065	* @{
AnnaBridge	163:e59c8e839560	1066	*/
AnnaBridge	163:e59c8e839560	1067
AnnaBridge	163:e59c8e839560	1068	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge	163:e59c8e839560	1069	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	163:e59c8e839560	1070	* It is used (enabled by hardware) as system clock source after startup
AnnaBridge	163:e59c8e839560	1071	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
AnnaBridge	163:e59c8e839560	1072	* of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge	163:e59c8e839560	1073	* Security System CSS is enabled).
AnnaBridge	163:e59c8e839560	1074	* @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge	163:e59c8e839560	1075	* you have to select another source of the system clock then stop the HSI.
AnnaBridge	163:e59c8e839560	1076	* @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge	163:e59c8e839560	1077	* flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge	163:e59c8e839560	1078	* system clock source.
AnnaBridge	163:e59c8e839560	1079	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge	163:e59c8e839560	1080	* clock cycles.
AnnaBridge	163:e59c8e839560	1081	*/
AnnaBridge	163:e59c8e839560	1082	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
AnnaBridge	163:e59c8e839560	1083	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
AnnaBridge	163:e59c8e839560	1084
AnnaBridge	163:e59c8e839560	1085	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
AnnaBridge	163:e59c8e839560	1086	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	163:e59c8e839560	1087	* and temperature that influence the frequency of the internal HSI RC.
AnnaBridge	163:e59c8e839560	1088	* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
AnnaBridge	163:e59c8e839560	1089	* (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	163:e59c8e839560	1090	* This parameter must be a number between 0 and 0x1F.
AnnaBridge	163:e59c8e839560	1091	*/
AnnaBridge	163:e59c8e839560	1092	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
AnnaBridge	163:e59c8e839560	1093	(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
AnnaBridge	163:e59c8e839560	1094
AnnaBridge	163:e59c8e839560	1095	/**
AnnaBridge	163:e59c8e839560	1096	* @}
AnnaBridge	163:e59c8e839560	1097	*/
AnnaBridge	163:e59c8e839560	1098
AnnaBridge	163:e59c8e839560	1099	/** @defgroup RCC_LSI_Configuration LSI Configuration
AnnaBridge	163:e59c8e839560	1100	* @{
AnnaBridge	163:e59c8e839560	1101	*/
AnnaBridge	163:e59c8e839560	1102
AnnaBridge	163:e59c8e839560	1103	/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
AnnaBridge	163:e59c8e839560	1104	* @note After enabling the LSI, the application software should wait on
AnnaBridge	163:e59c8e839560	1105	* LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge	163:e59c8e839560	1106	* be used to clock the IWDG and/or the RTC.
AnnaBridge	163:e59c8e839560	1107	*/
AnnaBridge	163:e59c8e839560	1108	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
AnnaBridge	163:e59c8e839560	1109
AnnaBridge	163:e59c8e839560	1110	/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
AnnaBridge	163:e59c8e839560	1111	* @note LSI can not be disabled if the IWDG is running.
AnnaBridge	163:e59c8e839560	1112	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge	163:e59c8e839560	1113	* clock cycles.
AnnaBridge	163:e59c8e839560	1114	*/
AnnaBridge	163:e59c8e839560	1115	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
AnnaBridge	163:e59c8e839560	1116
AnnaBridge	163:e59c8e839560	1117	/**
AnnaBridge	163:e59c8e839560	1118	* @}
AnnaBridge	163:e59c8e839560	1119	*/
AnnaBridge	163:e59c8e839560	1120
AnnaBridge	163:e59c8e839560	1121	/** @defgroup RCC_HSE_Configuration HSE Configuration
AnnaBridge	163:e59c8e839560	1122	* @{
AnnaBridge	163:e59c8e839560	1123	*/
AnnaBridge	163:e59c8e839560	1124
AnnaBridge	163:e59c8e839560	1125	/**
AnnaBridge	163:e59c8e839560	1126	* @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge	163:e59c8e839560	1127	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
AnnaBridge	163:e59c8e839560	1128	* supported by this macro. User should request a transition to HSE Off
AnnaBridge	163:e59c8e839560	1129	* first and then HSE On or HSE Bypass.
AnnaBridge	163:e59c8e839560	1130	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge	163:e59c8e839560	1131	* software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge	163:e59c8e839560	1132	* is stable and can be used to clock the PLL and/or system clock.
AnnaBridge	163:e59c8e839560	1133	* @note HSE state can not be changed if it is used directly or through the
AnnaBridge	163:e59c8e839560	1134	* PLL as system clock. In this case, you have to select another source
AnnaBridge	163:e59c8e839560	1135	* of the system clock then change the HSE state (ex. disable it).
AnnaBridge	163:e59c8e839560	1136	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	163:e59c8e839560	1137	* @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge	163:e59c8e839560	1138	* was previously enabled you have to enable it again after calling this
AnnaBridge	163:e59c8e839560	1139	* function.
AnnaBridge	163:e59c8e839560	1140	* @param __STATE__ specifies the new state of the HSE.
AnnaBridge	163:e59c8e839560	1141	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1142	* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge	163:e59c8e839560	1143	* 6 HSE oscillator clock cycles.
AnnaBridge	163:e59c8e839560	1144	* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
AnnaBridge	163:e59c8e839560	1145	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
AnnaBridge	163:e59c8e839560	1146	*/
AnnaBridge	163:e59c8e839560	1147	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge	163:e59c8e839560	1148	do{ \
AnnaBridge	163:e59c8e839560	1149	if ((__STATE__) == RCC_HSE_ON) \
AnnaBridge	163:e59c8e839560	1150	{ \
AnnaBridge	163:e59c8e839560	1151	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	163:e59c8e839560	1152	} \
AnnaBridge	163:e59c8e839560	1153	else if ((__STATE__) == RCC_HSE_OFF) \
AnnaBridge	163:e59c8e839560	1154	{ \
AnnaBridge	163:e59c8e839560	1155	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	163:e59c8e839560	1156	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	163:e59c8e839560	1157	} \
AnnaBridge	163:e59c8e839560	1158	else if ((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge	163:e59c8e839560	1159	{ \
AnnaBridge	163:e59c8e839560	1160	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	163:e59c8e839560	1161	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	163:e59c8e839560	1162	} \
AnnaBridge	163:e59c8e839560	1163	else \
AnnaBridge	163:e59c8e839560	1164	{ \
AnnaBridge	163:e59c8e839560	1165	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	163:e59c8e839560	1166	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	163:e59c8e839560	1167	} \
AnnaBridge	163:e59c8e839560	1168	}while(0U)
AnnaBridge	163:e59c8e839560	1169
AnnaBridge	163:e59c8e839560	1170	/**
AnnaBridge	163:e59c8e839560	1171	* @}
AnnaBridge	163:e59c8e839560	1172	*/
AnnaBridge	163:e59c8e839560	1173
AnnaBridge	163:e59c8e839560	1174	/** @defgroup RCC_LSE_Configuration LSE Configuration
AnnaBridge	163:e59c8e839560	1175	* @{
AnnaBridge	163:e59c8e839560	1176	*/
AnnaBridge	163:e59c8e839560	1177
AnnaBridge	163:e59c8e839560	1178	/**
AnnaBridge	163:e59c8e839560	1179	* @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge	163:e59c8e839560	1180	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
AnnaBridge	163:e59c8e839560	1181	* @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge	163:e59c8e839560	1182	* this domain after reset, you have to enable write access using
AnnaBridge	163:e59c8e839560	1183	* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge	163:e59c8e839560	1184	* (to be done once after reset).
AnnaBridge	163:e59c8e839560	1185	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge	163:e59c8e839560	1186	* software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge	163:e59c8e839560	1187	* is stable and can be used to clock the RTC.
AnnaBridge	163:e59c8e839560	1188	* @param __STATE__ specifies the new state of the LSE.
AnnaBridge	163:e59c8e839560	1189	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1190	* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge	163:e59c8e839560	1191	* 6 LSE oscillator clock cycles.
AnnaBridge	163:e59c8e839560	1192	* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
AnnaBridge	163:e59c8e839560	1193	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
AnnaBridge	163:e59c8e839560	1194	*/
AnnaBridge	163:e59c8e839560	1195	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge	163:e59c8e839560	1196	do{ \
AnnaBridge	163:e59c8e839560	1197	if ((__STATE__) == RCC_LSE_ON) \
AnnaBridge	163:e59c8e839560	1198	{ \
AnnaBridge	163:e59c8e839560	1199	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	163:e59c8e839560	1200	} \
AnnaBridge	163:e59c8e839560	1201	else if ((__STATE__) == RCC_LSE_OFF) \
AnnaBridge	163:e59c8e839560	1202	{ \
AnnaBridge	163:e59c8e839560	1203	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	163:e59c8e839560	1204	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge	163:e59c8e839560	1205	} \
AnnaBridge	163:e59c8e839560	1206	else if ((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge	163:e59c8e839560	1207	{ \
AnnaBridge	163:e59c8e839560	1208	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge	163:e59c8e839560	1209	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	163:e59c8e839560	1210	} \
AnnaBridge	163:e59c8e839560	1211	else \
AnnaBridge	163:e59c8e839560	1212	{ \
AnnaBridge	163:e59c8e839560	1213	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	163:e59c8e839560	1214	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge	163:e59c8e839560	1215	} \
AnnaBridge	163:e59c8e839560	1216	}while(0U)
AnnaBridge	163:e59c8e839560	1217
AnnaBridge	163:e59c8e839560	1218	/**
AnnaBridge	163:e59c8e839560	1219	* @}
AnnaBridge	163:e59c8e839560	1220	*/
AnnaBridge	163:e59c8e839560	1221
AnnaBridge	163:e59c8e839560	1222	/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
AnnaBridge	163:e59c8e839560	1223	* @{
AnnaBridge	163:e59c8e839560	1224	*/
AnnaBridge	163:e59c8e839560	1225
AnnaBridge	163:e59c8e839560	1226	/** @brief Macro to configure the USART1 clock (USART1CLK).
AnnaBridge	163:e59c8e839560	1227	* @param __USART1CLKSOURCE__ specifies the USART1 clock source.
AnnaBridge	163:e59c8e839560	1228	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1229	@if STM32F302xC
AnnaBridge	163:e59c8e839560	1230	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1231	@endif
AnnaBridge	163:e59c8e839560	1232	@if STM32F303xC
AnnaBridge	163:e59c8e839560	1233	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1234	@endif
AnnaBridge	163:e59c8e839560	1235	@if STM32F358xx
AnnaBridge	163:e59c8e839560	1236	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1237	@endif
AnnaBridge	163:e59c8e839560	1238	@if STM32F302xE
AnnaBridge	163:e59c8e839560	1239	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1240	@endif
AnnaBridge	163:e59c8e839560	1241	@if STM32F303xE
AnnaBridge	163:e59c8e839560	1242	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1243	@endif
AnnaBridge	163:e59c8e839560	1244	@if STM32F398xx
AnnaBridge	163:e59c8e839560	1245	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1246	@endif
AnnaBridge	163:e59c8e839560	1247	@if STM32F373xC
AnnaBridge	163:e59c8e839560	1248	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1249	@endif
AnnaBridge	163:e59c8e839560	1250	@if STM32F378xx
AnnaBridge	163:e59c8e839560	1251	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1252	@endif
AnnaBridge	163:e59c8e839560	1253	@if STM32F301x8
AnnaBridge	163:e59c8e839560	1254	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1255	@endif
AnnaBridge	163:e59c8e839560	1256	@if STM32F302x8
AnnaBridge	163:e59c8e839560	1257	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1258	@endif
AnnaBridge	163:e59c8e839560	1259	@if STM32F318xx
AnnaBridge	163:e59c8e839560	1260	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1261	@endif
AnnaBridge	163:e59c8e839560	1262	@if STM32F303x8
AnnaBridge	163:e59c8e839560	1263	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1264	@endif
AnnaBridge	163:e59c8e839560	1265	@if STM32F334x8
AnnaBridge	163:e59c8e839560	1266	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1267	@endif
AnnaBridge	163:e59c8e839560	1268	@if STM32F328xx
AnnaBridge	163:e59c8e839560	1269	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1270	@endif
AnnaBridge	163:e59c8e839560	1271	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge	163:e59c8e839560	1272	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge	163:e59c8e839560	1273	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
AnnaBridge	163:e59c8e839560	1274	*/
AnnaBridge	163:e59c8e839560	1275	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
AnnaBridge	163:e59c8e839560	1276	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
AnnaBridge	163:e59c8e839560	1277
AnnaBridge	163:e59c8e839560	1278	/** @brief Macro to get the USART1 clock source.
AnnaBridge	163:e59c8e839560	1279	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	1280	@if STM32F302xC
AnnaBridge	163:e59c8e839560	1281	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1282	@endif
AnnaBridge	163:e59c8e839560	1283	@if STM32F303xC
AnnaBridge	163:e59c8e839560	1284	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1285	@endif
AnnaBridge	163:e59c8e839560	1286	@if STM32F358xx
AnnaBridge	163:e59c8e839560	1287	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1288	@endif
AnnaBridge	163:e59c8e839560	1289	@if STM32F302xE
AnnaBridge	163:e59c8e839560	1290	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1291	@endif
AnnaBridge	163:e59c8e839560	1292	@if STM32F303xE
AnnaBridge	163:e59c8e839560	1293	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1294	@endif
AnnaBridge	163:e59c8e839560	1295	@if STM32F398xx
AnnaBridge	163:e59c8e839560	1296	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1297	@endif
AnnaBridge	163:e59c8e839560	1298	@if STM32F373xC
AnnaBridge	163:e59c8e839560	1299	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1300	@endif
AnnaBridge	163:e59c8e839560	1301	@if STM32F378xx
AnnaBridge	163:e59c8e839560	1302	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1303	@endif
AnnaBridge	163:e59c8e839560	1304	@if STM32F301x8
AnnaBridge	163:e59c8e839560	1305	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1306	@endif
AnnaBridge	163:e59c8e839560	1307	@if STM32F302x8
AnnaBridge	163:e59c8e839560	1308	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1309	@endif
AnnaBridge	163:e59c8e839560	1310	@if STM32F318xx
AnnaBridge	163:e59c8e839560	1311	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1312	@endif
AnnaBridge	163:e59c8e839560	1313	@if STM32F303x8
AnnaBridge	163:e59c8e839560	1314	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1315	@endif
AnnaBridge	163:e59c8e839560	1316	@if STM32F334x8
AnnaBridge	163:e59c8e839560	1317	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1318	@endif
AnnaBridge	163:e59c8e839560	1319	@if STM32F328xx
AnnaBridge	163:e59c8e839560	1320	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	163:e59c8e839560	1321	@endif
AnnaBridge	163:e59c8e839560	1322	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge	163:e59c8e839560	1323	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge	163:e59c8e839560	1324	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
AnnaBridge	163:e59c8e839560	1325	*/
AnnaBridge	163:e59c8e839560	1326	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
AnnaBridge	163:e59c8e839560	1327
AnnaBridge	163:e59c8e839560	1328	#if defined(RCC_CFGR3_USART2SW)
AnnaBridge	163:e59c8e839560	1329	/** @brief Macro to configure the USART2 clock (USART2CLK).
AnnaBridge	163:e59c8e839560	1330	* @param __USART2CLKSOURCE__ specifies the USART2 clock source.
AnnaBridge	163:e59c8e839560	1331	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1332	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge	163:e59c8e839560	1333	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge	163:e59c8e839560	1334	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge	163:e59c8e839560	1335	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge	163:e59c8e839560	1336	*/
AnnaBridge	163:e59c8e839560	1337	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
AnnaBridge	163:e59c8e839560	1338	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
AnnaBridge	163:e59c8e839560	1339
AnnaBridge	163:e59c8e839560	1340	/** @brief Macro to get the USART2 clock source.
AnnaBridge	163:e59c8e839560	1341	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	1342	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge	163:e59c8e839560	1343	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge	163:e59c8e839560	1344	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge	163:e59c8e839560	1345	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge	163:e59c8e839560	1346	*/
AnnaBridge	163:e59c8e839560	1347	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
AnnaBridge	163:e59c8e839560	1348	#endif /* RCC_CFGR3_USART2SW */
AnnaBridge	163:e59c8e839560	1349
AnnaBridge	163:e59c8e839560	1350	#if defined(RCC_CFGR3_USART3SW)
AnnaBridge	163:e59c8e839560	1351	/** @brief Macro to configure the USART3 clock (USART3CLK).
AnnaBridge	163:e59c8e839560	1352	* @param __USART3CLKSOURCE__ specifies the USART3 clock source.
AnnaBridge	163:e59c8e839560	1353	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1354	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
AnnaBridge	163:e59c8e839560	1355	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
AnnaBridge	163:e59c8e839560	1356	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
AnnaBridge	163:e59c8e839560	1357	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
AnnaBridge	163:e59c8e839560	1358	*/
AnnaBridge	163:e59c8e839560	1359	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
AnnaBridge	163:e59c8e839560	1360	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
AnnaBridge	163:e59c8e839560	1361
AnnaBridge	163:e59c8e839560	1362	/** @brief Macro to get the USART3 clock source.
AnnaBridge	163:e59c8e839560	1363	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	1364	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
AnnaBridge	163:e59c8e839560	1365	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
AnnaBridge	163:e59c8e839560	1366	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
AnnaBridge	163:e59c8e839560	1367	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
AnnaBridge	163:e59c8e839560	1368	*/
AnnaBridge	163:e59c8e839560	1369	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
AnnaBridge	163:e59c8e839560	1370	#endif /* RCC_CFGR3_USART2SW */
AnnaBridge	163:e59c8e839560	1371	/**
AnnaBridge	163:e59c8e839560	1372	* @}
AnnaBridge	163:e59c8e839560	1373	*/
AnnaBridge	163:e59c8e839560	1374
AnnaBridge	163:e59c8e839560	1375	/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
AnnaBridge	163:e59c8e839560	1376	* @{
AnnaBridge	163:e59c8e839560	1377	*/
AnnaBridge	163:e59c8e839560	1378
AnnaBridge	163:e59c8e839560	1379	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
AnnaBridge	163:e59c8e839560	1380	* @param __I2C1CLKSOURCE__ specifies the I2C1 clock source.
AnnaBridge	163:e59c8e839560	1381	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1382	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge	163:e59c8e839560	1383	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge	163:e59c8e839560	1384	*/
AnnaBridge	163:e59c8e839560	1385	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
AnnaBridge	163:e59c8e839560	1386	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
AnnaBridge	163:e59c8e839560	1387
AnnaBridge	163:e59c8e839560	1388	/** @brief Macro to get the I2C1 clock source.
AnnaBridge	163:e59c8e839560	1389	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	1390	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge	163:e59c8e839560	1391	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge	163:e59c8e839560	1392	*/
AnnaBridge	163:e59c8e839560	1393	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
AnnaBridge	163:e59c8e839560	1394	/**
AnnaBridge	163:e59c8e839560	1395	* @}
AnnaBridge	163:e59c8e839560	1396	*/
AnnaBridge	163:e59c8e839560	1397
AnnaBridge	163:e59c8e839560	1398	/** @defgroup RCC_PLL_Configuration PLL Configuration
AnnaBridge	163:e59c8e839560	1399	* @{
AnnaBridge	163:e59c8e839560	1400	*/
AnnaBridge	163:e59c8e839560	1401
AnnaBridge	163:e59c8e839560	1402	/** @brief Macro to enable the main PLL.
AnnaBridge	163:e59c8e839560	1403	* @note After enabling the main PLL, the application software should wait on
AnnaBridge	163:e59c8e839560	1404	* PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge	163:e59c8e839560	1405	* be used as system clock source.
AnnaBridge	163:e59c8e839560	1406	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	163:e59c8e839560	1407	*/
AnnaBridge	163:e59c8e839560	1408	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
AnnaBridge	163:e59c8e839560	1409
AnnaBridge	163:e59c8e839560	1410	/** @brief Macro to disable the main PLL.
AnnaBridge	163:e59c8e839560	1411	* @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge	163:e59c8e839560	1412	*/
AnnaBridge	163:e59c8e839560	1413	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
AnnaBridge	163:e59c8e839560	1414
AnnaBridge	163:e59c8e839560	1415
AnnaBridge	163:e59c8e839560	1416	/** @brief Get oscillator clock selected as PLL input clock
AnnaBridge	163:e59c8e839560	1417	* @retval The clock source used for PLL entry. The returned value can be one
AnnaBridge	163:e59c8e839560	1418	* of the following:
AnnaBridge	163:e59c8e839560	1419	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
AnnaBridge	163:e59c8e839560	1420	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
AnnaBridge	163:e59c8e839560	1421	*/
AnnaBridge	163:e59c8e839560	1422	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
AnnaBridge	163:e59c8e839560	1423
AnnaBridge	163:e59c8e839560	1424	/**
AnnaBridge	163:e59c8e839560	1425	* @}
AnnaBridge	163:e59c8e839560	1426	*/
AnnaBridge	163:e59c8e839560	1427
AnnaBridge	163:e59c8e839560	1428	/** @defgroup RCC_Get_Clock_source Get Clock source
AnnaBridge	163:e59c8e839560	1429	* @{
AnnaBridge	163:e59c8e839560	1430	*/
AnnaBridge	163:e59c8e839560	1431
AnnaBridge	163:e59c8e839560	1432	/**
AnnaBridge	163:e59c8e839560	1433	* @brief Macro to configure the system clock source.
AnnaBridge	163:e59c8e839560	1434	* @param __SYSCLKSOURCE__ specifies the system clock source.
AnnaBridge	163:e59c8e839560	1435	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1436	* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
AnnaBridge	163:e59c8e839560	1437	* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
AnnaBridge	163:e59c8e839560	1438	* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
AnnaBridge	163:e59c8e839560	1439	*/
AnnaBridge	163:e59c8e839560	1440	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
AnnaBridge	163:e59c8e839560	1441	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
AnnaBridge	163:e59c8e839560	1442
AnnaBridge	163:e59c8e839560	1443	/** @brief Macro to get the clock source used as system clock.
AnnaBridge	163:e59c8e839560	1444	* @retval The clock source used as system clock. The returned value can be one
AnnaBridge	163:e59c8e839560	1445	* of the following:
AnnaBridge	163:e59c8e839560	1446	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
AnnaBridge	163:e59c8e839560	1447	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
AnnaBridge	163:e59c8e839560	1448	* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
AnnaBridge	163:e59c8e839560	1449	*/
AnnaBridge	163:e59c8e839560	1450	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
AnnaBridge	163:e59c8e839560	1451
AnnaBridge	163:e59c8e839560	1452	/**
AnnaBridge	163:e59c8e839560	1453	* @}
AnnaBridge	163:e59c8e839560	1454	*/
AnnaBridge	163:e59c8e839560	1455
AnnaBridge	163:e59c8e839560	1456	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
AnnaBridge	163:e59c8e839560	1457	* @{
AnnaBridge	163:e59c8e839560	1458	*/
AnnaBridge	163:e59c8e839560	1459
AnnaBridge	163:e59c8e839560	1460	#if defined(RCC_CFGR_MCOPRE)
AnnaBridge	163:e59c8e839560	1461	/** @brief Macro to configure the MCO clock.
AnnaBridge	163:e59c8e839560	1462	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge	163:e59c8e839560	1463	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1464	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
AnnaBridge	163:e59c8e839560	1465	* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
AnnaBridge	163:e59c8e839560	1466	* @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
AnnaBridge	163:e59c8e839560	1467	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
AnnaBridge	163:e59c8e839560	1468	* @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
AnnaBridge	163:e59c8e839560	1469	* @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
AnnaBridge	163:e59c8e839560	1470	* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
AnnaBridge	163:e59c8e839560	1471	* @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge	163:e59c8e839560	1472	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1473	* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
AnnaBridge	163:e59c8e839560	1474	* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
AnnaBridge	163:e59c8e839560	1475	* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
AnnaBridge	163:e59c8e839560	1476	* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
AnnaBridge	163:e59c8e839560	1477	* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
AnnaBridge	163:e59c8e839560	1478	* @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
AnnaBridge	163:e59c8e839560	1479	* @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
AnnaBridge	163:e59c8e839560	1480	* @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
AnnaBridge	163:e59c8e839560	1481	*/
AnnaBridge	163:e59c8e839560	1482	#else
AnnaBridge	163:e59c8e839560	1483	/** @brief Macro to configure the MCO clock.
AnnaBridge	163:e59c8e839560	1484	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge	163:e59c8e839560	1485	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1486	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
AnnaBridge	163:e59c8e839560	1487	* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
AnnaBridge	163:e59c8e839560	1488	* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
AnnaBridge	163:e59c8e839560	1489	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
AnnaBridge	163:e59c8e839560	1490	* @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
AnnaBridge	163:e59c8e839560	1491	* @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
AnnaBridge	163:e59c8e839560	1492	* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
AnnaBridge	163:e59c8e839560	1493	* @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge	163:e59c8e839560	1494	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1495	* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
AnnaBridge	163:e59c8e839560	1496	*/
AnnaBridge	163:e59c8e839560	1497	#endif
AnnaBridge	163:e59c8e839560	1498	#if defined(RCC_CFGR_MCOPRE)
AnnaBridge	163:e59c8e839560	1499	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge	163:e59c8e839560	1500	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
AnnaBridge	163:e59c8e839560	1501	#else
AnnaBridge	163:e59c8e839560	1502
AnnaBridge	163:e59c8e839560	1503	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge	163:e59c8e839560	1504	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
AnnaBridge	163:e59c8e839560	1505
AnnaBridge	163:e59c8e839560	1506	#endif
AnnaBridge	163:e59c8e839560	1507
AnnaBridge	163:e59c8e839560	1508	/**
AnnaBridge	163:e59c8e839560	1509	* @}
AnnaBridge	163:e59c8e839560	1510	*/
AnnaBridge	163:e59c8e839560	1511
AnnaBridge	163:e59c8e839560	1512	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
AnnaBridge	163:e59c8e839560	1513	* @{
AnnaBridge	163:e59c8e839560	1514	*/
AnnaBridge	163:e59c8e839560	1515
AnnaBridge	163:e59c8e839560	1516	/** @brief Macro to configure the RTC clock (RTCCLK).
AnnaBridge	163:e59c8e839560	1517	* @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge	163:e59c8e839560	1518	* access is denied to this domain after reset, you have to enable write
AnnaBridge	163:e59c8e839560	1519	* access using the Power Backup Access macro before to configure
AnnaBridge	163:e59c8e839560	1520	* the RTC clock source (to be done once after reset).
AnnaBridge	163:e59c8e839560	1521	* @note Once the RTC clock is configured it cannot be changed unless the
AnnaBridge	163:e59c8e839560	1522	* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
AnnaBridge	163:e59c8e839560	1523	* a Power On Reset (POR).
AnnaBridge	163:e59c8e839560	1524	*
AnnaBridge	163:e59c8e839560	1525	* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
AnnaBridge	163:e59c8e839560	1526	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1527	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge	163:e59c8e839560	1528	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge	163:e59c8e839560	1529	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge	163:e59c8e839560	1530	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
AnnaBridge	163:e59c8e839560	1531	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge	163:e59c8e839560	1532	* work in STOP and STANDBY modes, and can be used as wakeup source.
AnnaBridge	163:e59c8e839560	1533	* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
AnnaBridge	163:e59c8e839560	1534	* the RTC cannot be used in STOP and STANDBY modes.
AnnaBridge	163:e59c8e839560	1535	* @note The system must always be configured so as to get a PCLK frequency greater than or
AnnaBridge	163:e59c8e839560	1536	* equal to the RTCCLK frequency for a proper operation of the RTC.
AnnaBridge	163:e59c8e839560	1537	*/
AnnaBridge	163:e59c8e839560	1538	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
AnnaBridge	163:e59c8e839560	1539
AnnaBridge	163:e59c8e839560	1540	/** @brief Macro to get the RTC clock source.
AnnaBridge	163:e59c8e839560	1541	* @retval The clock source can be one of the following values:
AnnaBridge	163:e59c8e839560	1542	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge	163:e59c8e839560	1543	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge	163:e59c8e839560	1544	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge	163:e59c8e839560	1545	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
AnnaBridge	163:e59c8e839560	1546	*/
AnnaBridge	163:e59c8e839560	1547	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
AnnaBridge	163:e59c8e839560	1548
AnnaBridge	163:e59c8e839560	1549	/** @brief Macro to enable the the RTC clock.
AnnaBridge	163:e59c8e839560	1550	* @note These macros must be used only after the RTC clock source was selected.
AnnaBridge	163:e59c8e839560	1551	*/
AnnaBridge	163:e59c8e839560	1552	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
AnnaBridge	163:e59c8e839560	1553
AnnaBridge	163:e59c8e839560	1554	/** @brief Macro to disable the the RTC clock.
AnnaBridge	163:e59c8e839560	1555	* @note These macros must be used only after the RTC clock source was selected.
AnnaBridge	163:e59c8e839560	1556	*/
AnnaBridge	163:e59c8e839560	1557	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
AnnaBridge	163:e59c8e839560	1558
AnnaBridge	163:e59c8e839560	1559	/** @brief Macro to force the Backup domain reset.
AnnaBridge	163:e59c8e839560	1560	* @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge	163:e59c8e839560	1561	* and the RTC clock source selection in RCC_BDCR register.
AnnaBridge	163:e59c8e839560	1562	*/
AnnaBridge	163:e59c8e839560	1563	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
AnnaBridge	163:e59c8e839560	1564
AnnaBridge	163:e59c8e839560	1565	/** @brief Macros to release the Backup domain reset.
AnnaBridge	163:e59c8e839560	1566	*/
AnnaBridge	163:e59c8e839560	1567	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
AnnaBridge	163:e59c8e839560	1568
AnnaBridge	163:e59c8e839560	1569	/**
AnnaBridge	163:e59c8e839560	1570	* @}
AnnaBridge	163:e59c8e839560	1571	*/
AnnaBridge	163:e59c8e839560	1572
AnnaBridge	163:e59c8e839560	1573	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge	163:e59c8e839560	1574	* @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge	163:e59c8e839560	1575	* @{
AnnaBridge	163:e59c8e839560	1576	*/
AnnaBridge	163:e59c8e839560	1577
AnnaBridge	163:e59c8e839560	1578	/** @brief Enable RCC interrupt.
AnnaBridge	163:e59c8e839560	1579	* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
AnnaBridge	163:e59c8e839560	1580	* This parameter can be any combination of the following values:
AnnaBridge	163:e59c8e839560	1581	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	163:e59c8e839560	1582	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	163:e59c8e839560	1583	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	163:e59c8e839560	1584	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	163:e59c8e839560	1585	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge	163:e59c8e839560	1586	*/
AnnaBridge	163:e59c8e839560	1587	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
AnnaBridge	163:e59c8e839560	1588
AnnaBridge	163:e59c8e839560	1589	/** @brief Disable RCC interrupt.
AnnaBridge	163:e59c8e839560	1590	* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
AnnaBridge	163:e59c8e839560	1591	* This parameter can be any combination of the following values:
AnnaBridge	163:e59c8e839560	1592	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	163:e59c8e839560	1593	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	163:e59c8e839560	1594	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	163:e59c8e839560	1595	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	163:e59c8e839560	1596	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge	163:e59c8e839560	1597	*/
AnnaBridge	163:e59c8e839560	1598	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
AnnaBridge	163:e59c8e839560	1599
AnnaBridge	163:e59c8e839560	1600	/** @brief Clear the RCC's interrupt pending bits.
AnnaBridge	163:e59c8e839560	1601	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	163:e59c8e839560	1602	* This parameter can be any combination of the following values:
AnnaBridge	163:e59c8e839560	1603	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
AnnaBridge	163:e59c8e839560	1604	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
AnnaBridge	163:e59c8e839560	1605	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
AnnaBridge	163:e59c8e839560	1606	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
AnnaBridge	163:e59c8e839560	1607	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
AnnaBridge	163:e59c8e839560	1608	* @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge	163:e59c8e839560	1609	*/
AnnaBridge	163:e59c8e839560	1610	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
AnnaBridge	163:e59c8e839560	1611
AnnaBridge	163:e59c8e839560	1612	/** @brief Check the RCC's interrupt has occurred or not.
AnnaBridge	163:e59c8e839560	1613	* @param __INTERRUPT__ specifies the RCC interrupt source to check.
AnnaBridge	163:e59c8e839560	1614	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1615	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
AnnaBridge	163:e59c8e839560	1616	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
AnnaBridge	163:e59c8e839560	1617	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
AnnaBridge	163:e59c8e839560	1618	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
AnnaBridge	163:e59c8e839560	1619	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
AnnaBridge	163:e59c8e839560	1620	* @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge	163:e59c8e839560	1621	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	163:e59c8e839560	1622	*/
AnnaBridge	163:e59c8e839560	1623	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	163:e59c8e839560	1624
AnnaBridge	163:e59c8e839560	1625	/** @brief Set RMVF bit to clear the reset flags.
AnnaBridge	163:e59c8e839560	1626	* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
AnnaBridge	163:e59c8e839560	1627	* RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
AnnaBridge	163:e59c8e839560	1628	*/
AnnaBridge	163:e59c8e839560	1629	#define __HAL_RCC_CLEAR_RESET_FLAGS() ((__IO uint32_t )RCC_CSR_RMVF_BB = ENABLE)
AnnaBridge	163:e59c8e839560	1630
AnnaBridge	163:e59c8e839560	1631	/** @brief Check RCC flag is set or not.
AnnaBridge	163:e59c8e839560	1632	* @param __FLAG__ specifies the flag to check.
AnnaBridge	163:e59c8e839560	1633	* This parameter can be one of the following values:
AnnaBridge	163:e59c8e839560	1634	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
AnnaBridge	163:e59c8e839560	1635	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
AnnaBridge	163:e59c8e839560	1636	* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
AnnaBridge	163:e59c8e839560	1637	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
AnnaBridge	163:e59c8e839560	1638	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
AnnaBridge	163:e59c8e839560	1639	* @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
AnnaBridge	163:e59c8e839560	1640	* @arg @ref RCC_FLAG_PINRST Pin reset.
AnnaBridge	163:e59c8e839560	1641	* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
AnnaBridge	163:e59c8e839560	1642	* @arg @ref RCC_FLAG_SFTRST Software reset.
AnnaBridge	163:e59c8e839560	1643	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
AnnaBridge	163:e59c8e839560	1644	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
AnnaBridge	163:e59c8e839560	1645	* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
AnnaBridge	163:e59c8e839560	1646	@if defined(STM32F301x8)
AnnaBridge	163:e59c8e839560	1647	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	163:e59c8e839560	1648	@endif
AnnaBridge	163:e59c8e839560	1649	@if defined(STM32F302x8)
AnnaBridge	163:e59c8e839560	1650	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	163:e59c8e839560	1651	@endif
AnnaBridge	163:e59c8e839560	1652	@if defined(STM32F302xC)
AnnaBridge	163:e59c8e839560	1653	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	163:e59c8e839560	1654	* @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
AnnaBridge	163:e59c8e839560	1655	@endif
AnnaBridge	163:e59c8e839560	1656	@if defined(STM32F302xE)
AnnaBridge	163:e59c8e839560	1657	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	163:e59c8e839560	1658	@endif
AnnaBridge	163:e59c8e839560	1659	@if defined(STM32F303x8)
AnnaBridge	163:e59c8e839560	1660	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	163:e59c8e839560	1661	@endif
AnnaBridge	163:e59c8e839560	1662	@if defined(STM32F303xC)
AnnaBridge	163:e59c8e839560	1663	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	163:e59c8e839560	1664	* @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
AnnaBridge	163:e59c8e839560	1665	@endif
AnnaBridge	163:e59c8e839560	1666	@if defined(STM32F303xE)
AnnaBridge	163:e59c8e839560	1667	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	163:e59c8e839560	1668	@endif
AnnaBridge	163:e59c8e839560	1669	@if defined(STM32F334x8)
AnnaBridge	163:e59c8e839560	1670	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	163:e59c8e839560	1671	@endif
AnnaBridge	163:e59c8e839560	1672	@if defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	1673	* @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
AnnaBridge	163:e59c8e839560	1674	@endif
AnnaBridge	163:e59c8e839560	1675	@if defined(STM32F373xC)
AnnaBridge	163:e59c8e839560	1676	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	163:e59c8e839560	1677	@endif
AnnaBridge	163:e59c8e839560	1678	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	163:e59c8e839560	1679	*/
AnnaBridge	163:e59c8e839560	1680	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
AnnaBridge	163:e59c8e839560	1681	(((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
AnnaBridge	163:e59c8e839560	1682	(((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \
AnnaBridge	163:e59c8e839560	1683	RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
AnnaBridge	163:e59c8e839560	1684
AnnaBridge	163:e59c8e839560	1685	/**
AnnaBridge	163:e59c8e839560	1686	* @}
AnnaBridge	163:e59c8e839560	1687	*/
AnnaBridge	163:e59c8e839560	1688
AnnaBridge	163:e59c8e839560	1689	/**
AnnaBridge	163:e59c8e839560	1690	* @}
AnnaBridge	163:e59c8e839560	1691	*/
AnnaBridge	163:e59c8e839560	1692
AnnaBridge	163:e59c8e839560	1693	/* Include RCC HAL Extension module */
AnnaBridge	163:e59c8e839560	1694	#include "stm32f3xx_hal_rcc_ex.h"
AnnaBridge	163:e59c8e839560	1695
AnnaBridge	163:e59c8e839560	1696	/* Exported functions --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1697	/** @addtogroup RCC_Exported_Functions
AnnaBridge	163:e59c8e839560	1698	* @{
AnnaBridge	163:e59c8e839560	1699	*/
AnnaBridge	163:e59c8e839560	1700
AnnaBridge	163:e59c8e839560	1701	/** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge	163:e59c8e839560	1702	* @{
AnnaBridge	163:e59c8e839560	1703	*/
AnnaBridge	163:e59c8e839560	1704
AnnaBridge	163:e59c8e839560	1705	/* Initialization and de-initialization functions ******************************/
AnnaBridge	163:e59c8e839560	1706	void HAL_RCC_DeInit(void);
AnnaBridge	163:e59c8e839560	1707	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	163:e59c8e839560	1708	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge	163:e59c8e839560	1709
AnnaBridge	163:e59c8e839560	1710	/**
AnnaBridge	163:e59c8e839560	1711	* @}
AnnaBridge	163:e59c8e839560	1712	*/
AnnaBridge	163:e59c8e839560	1713
AnnaBridge	163:e59c8e839560	1714	/** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge	163:e59c8e839560	1715	* @{
AnnaBridge	163:e59c8e839560	1716	*/
AnnaBridge	163:e59c8e839560	1717
AnnaBridge	163:e59c8e839560	1718	/* Peripheral Control functions ************************************************/
AnnaBridge	163:e59c8e839560	1719	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge	163:e59c8e839560	1720	void HAL_RCC_EnableCSS(void);
AnnaBridge	163:e59c8e839560	1721	/* CSS NMI IRQ handler */
AnnaBridge	163:e59c8e839560	1722	void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge	163:e59c8e839560	1723	/* User Callbacks in non blocking mode (IT mode) */
AnnaBridge	163:e59c8e839560	1724	void HAL_RCC_CSSCallback(void);
AnnaBridge	163:e59c8e839560	1725	void HAL_RCC_DisableCSS(void);
AnnaBridge	163:e59c8e839560	1726	uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge	163:e59c8e839560	1727	uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge	163:e59c8e839560	1728	uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge	163:e59c8e839560	1729	uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge	163:e59c8e839560	1730	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	163:e59c8e839560	1731	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
AnnaBridge	163:e59c8e839560	1732
AnnaBridge	163:e59c8e839560	1733	/**
AnnaBridge	163:e59c8e839560	1734	* @}
AnnaBridge	163:e59c8e839560	1735	*/
AnnaBridge	163:e59c8e839560	1736
AnnaBridge	163:e59c8e839560	1737	/**
AnnaBridge	163:e59c8e839560	1738	* @}
AnnaBridge	163:e59c8e839560	1739	*/
AnnaBridge	163:e59c8e839560	1740
AnnaBridge	163:e59c8e839560	1741	/**
AnnaBridge	163:e59c8e839560	1742	* @}
AnnaBridge	163:e59c8e839560	1743	*/
AnnaBridge	163:e59c8e839560	1744
AnnaBridge	163:e59c8e839560	1745	/**
AnnaBridge	163:e59c8e839560	1746	* @}
AnnaBridge	163:e59c8e839560	1747	*/
AnnaBridge	163:e59c8e839560	1748
AnnaBridge	163:e59c8e839560	1749	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	1750	}
AnnaBridge	163:e59c8e839560	1751	#endif
AnnaBridge	163:e59c8e839560	1752
AnnaBridge	163:e59c8e839560	1753	#endif /* __STM32F3xx_HAL_RCC_H */
AnnaBridge	163:e59c8e839560	1754
AnnaBridge	163:e59c8e839560	1755	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	163:e59c8e839560	1756