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TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_hrtim.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.h@168:b9e159c1930a 
mbed library. Release version 164

Who changed what in which revision?

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AnnaBridge 163:e59c8e839560 1 /**
AnnaBridge 163:e59c8e839560 2 ******************************************************************************
AnnaBridge 163:e59c8e839560 3 * @file stm32f3xx_hal_hrtim.h
AnnaBridge 163:e59c8e839560 4 * @author MCD Application Team
AnnaBridge 163:e59c8e839560 5 * @brief Header file of HRTIM HAL module.
AnnaBridge 163:e59c8e839560 6 ******************************************************************************
AnnaBridge 163:e59c8e839560 7 * @attention
AnnaBridge 163:e59c8e839560 8 *
AnnaBridge 163:e59c8e839560 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 163:e59c8e839560 10 *
AnnaBridge 163:e59c8e839560 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 163:e59c8e839560 12 * are permitted provided that the following conditions are met:
AnnaBridge 163:e59c8e839560 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 163:e59c8e839560 14 * this list of conditions and the following disclaimer.
AnnaBridge 163:e59c8e839560 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 163:e59c8e839560 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 163:e59c8e839560 17 * and/or other materials provided with the distribution.
AnnaBridge 163:e59c8e839560 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 163:e59c8e839560 19 * may be used to endorse or promote products derived from this software
AnnaBridge 163:e59c8e839560 20 * without specific prior written permission.
AnnaBridge 163:e59c8e839560 21 *
AnnaBridge 163:e59c8e839560 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 163:e59c8e839560 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 163:e59c8e839560 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 163:e59c8e839560 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 163:e59c8e839560 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 163:e59c8e839560 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 163:e59c8e839560 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 163:e59c8e839560 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 163:e59c8e839560 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 163:e59c8e839560 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 163:e59c8e839560 32 *
AnnaBridge 163:e59c8e839560 33 ******************************************************************************
AnnaBridge 163:e59c8e839560 34 */
AnnaBridge 163:e59c8e839560 35
AnnaBridge 163:e59c8e839560 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 163:e59c8e839560 37 #ifndef __STM32F3xx_HAL_HRTIM_H
AnnaBridge 163:e59c8e839560 38 #define __STM32F3xx_HAL_HRTIM_H
AnnaBridge 163:e59c8e839560 39
AnnaBridge 163:e59c8e839560 40 #ifdef __cplusplus
AnnaBridge 163:e59c8e839560 41 extern "C" {
AnnaBridge 163:e59c8e839560 42 #endif
AnnaBridge 163:e59c8e839560 43
AnnaBridge 163:e59c8e839560 44 #if defined(STM32F334x8)
AnnaBridge 163:e59c8e839560 45
AnnaBridge 163:e59c8e839560 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 47 #include "stm32f3xx_hal_def.h"
AnnaBridge 163:e59c8e839560 48
AnnaBridge 163:e59c8e839560 49 /** @addtogroup STM32F3xx_HAL_Driver
AnnaBridge 163:e59c8e839560 50 * @{
AnnaBridge 163:e59c8e839560 51 */
AnnaBridge 163:e59c8e839560 52
AnnaBridge 163:e59c8e839560 53 /** @addtogroup HRTIM HRTIM
AnnaBridge 163:e59c8e839560 54 * @{
AnnaBridge 163:e59c8e839560 55 */
AnnaBridge 163:e59c8e839560 56
AnnaBridge 163:e59c8e839560 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 58 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
AnnaBridge 163:e59c8e839560 59 * @{
AnnaBridge 163:e59c8e839560 60 */
AnnaBridge 163:e59c8e839560 61 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer
AnnaBridge 163:e59c8e839560 62 * @{
AnnaBridge 163:e59c8e839560 63 */
AnnaBridge 163:e59c8e839560 64 #define MAX_HRTIM_TIMER 6U
AnnaBridge 163:e59c8e839560 65 /**
AnnaBridge 163:e59c8e839560 66 * @}
AnnaBridge 163:e59c8e839560 67 */
AnnaBridge 163:e59c8e839560 68 /**
AnnaBridge 163:e59c8e839560 69 * @}
AnnaBridge 163:e59c8e839560 70 */
AnnaBridge 163:e59c8e839560 71
AnnaBridge 163:e59c8e839560 72 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types
AnnaBridge 163:e59c8e839560 73 * @{
AnnaBridge 163:e59c8e839560 74 */
AnnaBridge 163:e59c8e839560 75
AnnaBridge 163:e59c8e839560 76 /**
AnnaBridge 163:e59c8e839560 77 * @brief HRTIM Configuration Structure definition - Time base related parameters
AnnaBridge 163:e59c8e839560 78 */
AnnaBridge 163:e59c8e839560 79 typedef struct
AnnaBridge 163:e59c8e839560 80 {
AnnaBridge 163:e59c8e839560 81 uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
AnnaBridge 163:e59c8e839560 82 This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
AnnaBridge 163:e59c8e839560 83 uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals.
AnnaBridge 163:e59c8e839560 84 The HRTIM instance can be configured to act as a slave (waiting for a trigger
AnnaBridge 163:e59c8e839560 85 to be synchronized) or a master (generating a synchronization signal) or both.
AnnaBridge 163:e59c8e839560 86 This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
AnnaBridge 163:e59c8e839560 87 uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when
AnnaBridge 163:e59c8e839560 88 the HRTIM instance is configured as a slave).
AnnaBridge 163:e59c8e839560 89 This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
AnnaBridge 163:e59c8e839560 90 uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
AnnaBridge 163:e59c8e839560 91 (significant only when the HRTIM instance is configured as a master).
AnnaBridge 163:e59c8e839560 92 This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
AnnaBridge 163:e59c8e839560 93 uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization
AnnaBridge 163:e59c8e839560 94 outputs (significant only when the HRTIM instance is configured as a master).
AnnaBridge 163:e59c8e839560 95 This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
AnnaBridge 163:e59c8e839560 96 } HRTIM_InitTypeDef;
AnnaBridge 163:e59c8e839560 97
AnnaBridge 163:e59c8e839560 98 /**
AnnaBridge 163:e59c8e839560 99 * @brief HAL State structures definition
AnnaBridge 163:e59c8e839560 100 */
AnnaBridge 163:e59c8e839560 101 typedef enum
AnnaBridge 163:e59c8e839560 102 {
AnnaBridge 163:e59c8e839560 103 HAL_HRTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
AnnaBridge 163:e59c8e839560 104 HAL_HRTIM_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
AnnaBridge 163:e59c8e839560 105 HAL_HRTIM_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
AnnaBridge 163:e59c8e839560 106 HAL_HRTIM_STATE_ERROR = 0x07U, /*!< Error state */
AnnaBridge 163:e59c8e839560 107 } HAL_HRTIM_StateTypeDef;
AnnaBridge 163:e59c8e839560 108
AnnaBridge 163:e59c8e839560 109 /**
AnnaBridge 163:e59c8e839560 110 * @brief HRTIM Timer Structure definition
AnnaBridge 163:e59c8e839560 111 */
AnnaBridge 163:e59c8e839560 112 typedef struct
AnnaBridge 163:e59c8e839560 113 {
AnnaBridge 163:e59c8e839560 114 uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1.
AnnaBridge 163:e59c8e839560 115 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
AnnaBridge 163:e59c8e839560 116 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
AnnaBridge 163:e59c8e839560 117 uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2.
AnnaBridge 163:e59c8e839560 118 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
AnnaBridge 163:e59c8e839560 119 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
AnnaBridge 163:e59c8e839560 120 uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer. */
AnnaBridge 163:e59c8e839560 121 uint32_t DMARequests; /*!< DMA requests enabled for the timer. */
AnnaBridge 163:e59c8e839560 122 uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer. */
AnnaBridge 163:e59c8e839560 123 uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer. */
AnnaBridge 163:e59c8e839560 124 uint32_t DMASize; /*!< Size of the DMA transfer */
AnnaBridge 163:e59c8e839560 125 } HRTIM_TimerParamTypeDef;
AnnaBridge 163:e59c8e839560 126
AnnaBridge 163:e59c8e839560 127 /**
AnnaBridge 163:e59c8e839560 128 * @brief HRTIM Handle Structure definition
AnnaBridge 163:e59c8e839560 129 */
AnnaBridge 163:e59c8e839560 130 typedef struct __HRTIM_HandleTypeDef
AnnaBridge 163:e59c8e839560 131 {
AnnaBridge 163:e59c8e839560 132 HRTIM_TypeDef * Instance; /*!< Register base address */
AnnaBridge 163:e59c8e839560 133
AnnaBridge 163:e59c8e839560 134 HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */
AnnaBridge 163:e59c8e839560 135
AnnaBridge 163:e59c8e839560 136 HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */
AnnaBridge 163:e59c8e839560 137
AnnaBridge 163:e59c8e839560 138 HAL_LockTypeDef Lock; /*!< Locking object */
AnnaBridge 163:e59c8e839560 139
AnnaBridge 163:e59c8e839560 140 __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */
AnnaBridge 163:e59c8e839560 141
AnnaBridge 163:e59c8e839560 142 DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */
AnnaBridge 163:e59c8e839560 143 DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */
AnnaBridge 163:e59c8e839560 144 DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */
AnnaBridge 163:e59c8e839560 145 DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */
AnnaBridge 163:e59c8e839560 146 DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */
AnnaBridge 163:e59c8e839560 147 DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */
AnnaBridge 163:e59c8e839560 148 } HRTIM_HandleTypeDef;
AnnaBridge 163:e59c8e839560 149
AnnaBridge 163:e59c8e839560 150 /**
AnnaBridge 163:e59c8e839560 151 * @brief Simple output compare mode configuration definition
AnnaBridge 163:e59c8e839560 152 */
AnnaBridge 163:e59c8e839560 153 typedef struct {
AnnaBridge 163:e59c8e839560 154 uint32_t Period; /*!< Specifies the timer period.
AnnaBridge 163:e59c8e839560 155 The period value must be above 3 periods of the fHRTIM clock.
AnnaBridge 163:e59c8e839560 156 Maximum value is = 0xFFDFU */
AnnaBridge 163:e59c8e839560 157 uint32_t RepetitionCounter; /*!< Specifies the timer repetition period.
AnnaBridge 163:e59c8e839560 158 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
AnnaBridge 163:e59c8e839560 159 uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
AnnaBridge 163:e59c8e839560 160 This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
AnnaBridge 163:e59c8e839560 161 uint32_t Mode; /*!< Specifies the counter operating mode.
AnnaBridge 163:e59c8e839560 162 This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */
AnnaBridge 163:e59c8e839560 163 } HRTIM_TimeBaseCfgTypeDef;
AnnaBridge 163:e59c8e839560 164
AnnaBridge 163:e59c8e839560 165 /**
AnnaBridge 163:e59c8e839560 166 * @brief Simple output compare mode configuration definition
AnnaBridge 163:e59c8e839560 167 */
AnnaBridge 163:e59c8e839560 168 typedef struct {
AnnaBridge 163:e59c8e839560 169 uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive).
AnnaBridge 163:e59c8e839560 170 This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
AnnaBridge 163:e59c8e839560 171 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
AnnaBridge 163:e59c8e839560 172 The compare value must be above or equal to 3 periods of the fHRTIM clock */
AnnaBridge 163:e59c8e839560 173 uint32_t Polarity; /*!< Specifies the output polarity.
AnnaBridge 163:e59c8e839560 174 This parameter can be any value of @ref HRTIM_Output_Polarity */
AnnaBridge 163:e59c8e839560 175 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
AnnaBridge 163:e59c8e839560 176 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
AnnaBridge 163:e59c8e839560 177 } HRTIM_SimpleOCChannelCfgTypeDef;
AnnaBridge 163:e59c8e839560 178
AnnaBridge 163:e59c8e839560 179 /**
AnnaBridge 163:e59c8e839560 180 * @brief Simple PWM output mode configuration definition
AnnaBridge 163:e59c8e839560 181 */
AnnaBridge 163:e59c8e839560 182 typedef struct {
AnnaBridge 163:e59c8e839560 183 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
AnnaBridge 163:e59c8e839560 184 The compare value must be above or equal to 3 periods of the fHRTIM clock */
AnnaBridge 163:e59c8e839560 185 uint32_t Polarity; /*!< Specifies the output polarity.
AnnaBridge 163:e59c8e839560 186 This parameter can be any value of @ref HRTIM_Output_Polarity */
AnnaBridge 163:e59c8e839560 187 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
AnnaBridge 163:e59c8e839560 188 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
AnnaBridge 163:e59c8e839560 189 } HRTIM_SimplePWMChannelCfgTypeDef;
AnnaBridge 163:e59c8e839560 190
AnnaBridge 163:e59c8e839560 191 /**
AnnaBridge 163:e59c8e839560 192 * @brief Simple capture mode configuration definition
AnnaBridge 163:e59c8e839560 193 */
AnnaBridge 163:e59c8e839560 194 typedef struct {
AnnaBridge 163:e59c8e839560 195 uint32_t Event; /*!< Specifies the external event triggering the capture.
AnnaBridge 163:e59c8e839560 196 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
AnnaBridge 163:e59c8e839560 197 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
AnnaBridge 163:e59c8e839560 198 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
AnnaBridge 163:e59c8e839560 199 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
AnnaBridge 163:e59c8e839560 200 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
AnnaBridge 163:e59c8e839560 201 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
AnnaBridge 163:e59c8e839560 202 This parameter can be a value of @ref HRTIM_External_Event_Filter */
AnnaBridge 163:e59c8e839560 203 } HRTIM_SimpleCaptureChannelCfgTypeDef;
AnnaBridge 163:e59c8e839560 204
AnnaBridge 163:e59c8e839560 205 /**
AnnaBridge 163:e59c8e839560 206 * @brief Simple One Pulse mode configuration definition
AnnaBridge 163:e59c8e839560 207 */
AnnaBridge 163:e59c8e839560 208 typedef struct {
AnnaBridge 163:e59c8e839560 209 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
AnnaBridge 163:e59c8e839560 210 The compare value must be above or equal to 3 periods of the fHRTIM clock */
AnnaBridge 163:e59c8e839560 211 uint32_t OutputPolarity; /*!< Specifies the output polarity.
AnnaBridge 163:e59c8e839560 212 This parameter can be any value of @ref HRTIM_Output_Polarity */
AnnaBridge 163:e59c8e839560 213 uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
AnnaBridge 163:e59c8e839560 214 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
AnnaBridge 163:e59c8e839560 215 uint32_t Event; /*!< Specifies the external event triggering the pulse generation.
AnnaBridge 163:e59c8e839560 216 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
AnnaBridge 163:e59c8e839560 217 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
AnnaBridge 163:e59c8e839560 218 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
AnnaBridge 163:e59c8e839560 219 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
AnnaBridge 163:e59c8e839560 220 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
AnnaBridge 163:e59c8e839560 221 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
AnnaBridge 163:e59c8e839560 222 This parameter can be a value of @ref HRTIM_External_Event_Filter */
AnnaBridge 163:e59c8e839560 223 } HRTIM_SimpleOnePulseChannelCfgTypeDef;
AnnaBridge 163:e59c8e839560 224
AnnaBridge 163:e59c8e839560 225 /**
AnnaBridge 163:e59c8e839560 226 * @brief Timer configuration definition
AnnaBridge 163:e59c8e839560 227 */
AnnaBridge 163:e59c8e839560 228 typedef struct {
AnnaBridge 163:e59c8e839560 229 uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 230 Specifies which interrupts requests must enabled for the timer.
AnnaBridge 163:e59c8e839560 231 This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
AnnaBridge 163:e59c8e839560 232 or @ref HRTIM_Timing_Unit_Interrupt_Enable */
AnnaBridge 163:e59c8e839560 233 uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 234 Specifies which DMA requests must be enabled for the timer.
AnnaBridge 163:e59c8e839560 235 This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
AnnaBridge 163:e59c8e839560 236 or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
AnnaBridge 163:e59c8e839560 237 uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 238 Specifies the address of the source address of the DMA transfer */
AnnaBridge 163:e59c8e839560 239 uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 240 Specifies the address of the destination address of the DMA transfer */
AnnaBridge 163:e59c8e839560 241 uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 242 Specifies the size of the DMA transfer */
AnnaBridge 163:e59c8e839560 243 uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 244 Specifies whether or not hald mode is enabled
AnnaBridge 163:e59c8e839560 245 This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
AnnaBridge 163:e59c8e839560 246 uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 247 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
AnnaBridge 163:e59c8e839560 248 This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
AnnaBridge 163:e59c8e839560 249 uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 250 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
AnnaBridge 163:e59c8e839560 251 This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
AnnaBridge 163:e59c8e839560 252 uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 253 Indicates whether or not the a DAC synchronization event is generated.
AnnaBridge 163:e59c8e839560 254 This parameter can be any value of @ref HRTIM_DAC_Synchronization */
AnnaBridge 163:e59c8e839560 255 uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 256 Specifies whether or not register preload is enabled.
AnnaBridge 163:e59c8e839560 257 This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
AnnaBridge 163:e59c8e839560 258 uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 259 Specifies how the update occurs with respect to a burst DMA transaction or
AnnaBridge 163:e59c8e839560 260 update enable inputs (Slave timers only).
AnnaBridge 163:e59c8e839560 261 This parameter can be any value of @ref HRTIM_Update_Gating */
AnnaBridge 163:e59c8e839560 262 uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 263 Specifies how the timer behaves during a burst mode operation.
AnnaBridge 163:e59c8e839560 264 This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
AnnaBridge 163:e59c8e839560 265 uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge 163:e59c8e839560 266 Specifies whether or not registers update is triggered by the repetition event.
AnnaBridge 163:e59c8e839560 267 This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
AnnaBridge 163:e59c8e839560 268 uint32_t PushPull; /*!< Relevant for Timer A to Timer E.
AnnaBridge 163:e59c8e839560 269 Specifies whether or not the push-pull mode is enabled.
AnnaBridge 163:e59c8e839560 270 This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
AnnaBridge 163:e59c8e839560 271 uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E.
AnnaBridge 163:e59c8e839560 272 Specifies which fault channels are enabled for the timer.
AnnaBridge 163:e59c8e839560 273 This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
AnnaBridge 163:e59c8e839560 274 uint32_t FaultLock; /*!< Relevant for Timer A to Timer E.
AnnaBridge 163:e59c8e839560 275 Specifies whether or not fault enabling status is write protected.
AnnaBridge 163:e59c8e839560 276 This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
AnnaBridge 163:e59c8e839560 277 uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E.
AnnaBridge 163:e59c8e839560 278 Specifies whether or not dead-time insertion is enabled for the timer.
AnnaBridge 163:e59c8e839560 279 This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
AnnaBridge 163:e59c8e839560 280 uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E.
AnnaBridge 163:e59c8e839560 281 Specifies the delayed protection mode.
AnnaBridge 163:e59c8e839560 282 This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
AnnaBridge 163:e59c8e839560 283 uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E.
AnnaBridge 163:e59c8e839560 284 Specifies source(s) triggering the timer registers update.
AnnaBridge 163:e59c8e839560 285 This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
AnnaBridge 163:e59c8e839560 286 uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E.
AnnaBridge 163:e59c8e839560 287 Specifies source(s) triggering the timer counter reset.
AnnaBridge 163:e59c8e839560 288 This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
AnnaBridge 163:e59c8e839560 289 uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E.
AnnaBridge 163:e59c8e839560 290 Specifies whether or not registers update is triggered when the timer counter is reset.
AnnaBridge 163:e59c8e839560 291 This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
AnnaBridge 163:e59c8e839560 292 } HRTIM_TimerCfgTypeDef;
AnnaBridge 163:e59c8e839560 293
AnnaBridge 163:e59c8e839560 294 /**
AnnaBridge 163:e59c8e839560 295 * @brief Compare unit configuration definition
AnnaBridge 163:e59c8e839560 296 */
AnnaBridge 163:e59c8e839560 297 typedef struct {
AnnaBridge 163:e59c8e839560 298 uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit.
AnnaBridge 163:e59c8e839560 299 The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
AnnaBridge 163:e59c8e839560 300 The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
AnnaBridge 163:e59c8e839560 301 uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4.
AnnaBridge 163:e59c8e839560 302 This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
AnnaBridge 163:e59c8e839560 303 uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
AnnaBridge 163:e59c8e839560 304 CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */
AnnaBridge 163:e59c8e839560 305 } HRTIM_CompareCfgTypeDef;
AnnaBridge 163:e59c8e839560 306
AnnaBridge 163:e59c8e839560 307 /**
AnnaBridge 163:e59c8e839560 308 * @brief Capture unit configuration definition
AnnaBridge 163:e59c8e839560 309 */
AnnaBridge 163:e59c8e839560 310 typedef struct {
AnnaBridge 163:e59c8e839560 311 uint32_t Trigger; /*!< Specifies source(s) triggering the capture.
AnnaBridge 163:e59c8e839560 312 This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
AnnaBridge 163:e59c8e839560 313 } HRTIM_CaptureCfgTypeDef;
AnnaBridge 163:e59c8e839560 314
AnnaBridge 163:e59c8e839560 315 /**
AnnaBridge 163:e59c8e839560 316 * @brief Output configuration definition
AnnaBridge 163:e59c8e839560 317 */
AnnaBridge 163:e59c8e839560 318 typedef struct {
AnnaBridge 163:e59c8e839560 319 uint32_t Polarity; /*!< Specifies the output polarity.
AnnaBridge 163:e59c8e839560 320 This parameter can be any value of @ref HRTIM_Output_Polarity */
AnnaBridge 163:e59c8e839560 321 uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
AnnaBridge 163:e59c8e839560 322 This parameter can be a combination of @ref HRTIM_Output_Set_Source */
AnnaBridge 163:e59c8e839560 323 uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
AnnaBridge 163:e59c8e839560 324 This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
AnnaBridge 163:e59c8e839560 325 uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation.
AnnaBridge 163:e59c8e839560 326 This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
AnnaBridge 163:e59c8e839560 327 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
AnnaBridge 163:e59c8e839560 328 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
AnnaBridge 163:e59c8e839560 329 uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state.
AnnaBridge 163:e59c8e839560 330 This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
AnnaBridge 163:e59c8e839560 331 uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
AnnaBridge 163:e59c8e839560 332 This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
AnnaBridge 163:e59c8e839560 333 uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
AnnaBridge 163:e59c8e839560 334 This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
AnnaBridge 163:e59c8e839560 335 } HRTIM_OutputCfgTypeDef;
AnnaBridge 163:e59c8e839560 336
AnnaBridge 163:e59c8e839560 337 /**
AnnaBridge 163:e59c8e839560 338 * @brief External event filtering in timing units configuration definition
AnnaBridge 163:e59c8e839560 339 */
AnnaBridge 163:e59c8e839560 340 typedef struct {
AnnaBridge 163:e59c8e839560 341 uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit.
AnnaBridge 163:e59c8e839560 342 This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
AnnaBridge 163:e59c8e839560 343 uint32_t Latch; /*!< Specifies whether or not the signal is latched.
AnnaBridge 163:e59c8e839560 344 This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
AnnaBridge 163:e59c8e839560 345 } HRTIM_TimerEventFilteringCfgTypeDef;
AnnaBridge 163:e59c8e839560 346
AnnaBridge 163:e59c8e839560 347 /**
AnnaBridge 163:e59c8e839560 348 * @brief Dead time feature configuration definition
AnnaBridge 163:e59c8e839560 349 */
AnnaBridge 163:e59c8e839560 350 typedef struct {
AnnaBridge 163:e59c8e839560 351 uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler.
AnnaBridge 163:e59c8e839560 352 This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
AnnaBridge 163:e59c8e839560 353 uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge.
AnnaBridge 163:e59c8e839560 354 This parameter can be a number between 0x0 and 0x1FFU */
AnnaBridge 163:e59c8e839560 355 uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge.
AnnaBridge 163:e59c8e839560 356 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
AnnaBridge 163:e59c8e839560 357 uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected.
AnnaBridge 163:e59c8e839560 358 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
AnnaBridge 163:e59c8e839560 359 uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected.
AnnaBridge 163:e59c8e839560 360 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
AnnaBridge 163:e59c8e839560 361 uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge.
AnnaBridge 163:e59c8e839560 362 This parameter can be a number between 0x0 and 0x1FFU */
AnnaBridge 163:e59c8e839560 363 uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge.
AnnaBridge 163:e59c8e839560 364 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
AnnaBridge 163:e59c8e839560 365 uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected.
AnnaBridge 163:e59c8e839560 366 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
AnnaBridge 163:e59c8e839560 367 uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected.
AnnaBridge 163:e59c8e839560 368 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
AnnaBridge 163:e59c8e839560 369 } HRTIM_DeadTimeCfgTypeDef ;
AnnaBridge 163:e59c8e839560 370
AnnaBridge 163:e59c8e839560 371 /**
AnnaBridge 163:e59c8e839560 372 * @brief Chopper mode configuration definition
AnnaBridge 163:e59c8e839560 373 */
AnnaBridge 163:e59c8e839560 374 typedef struct {
AnnaBridge 163:e59c8e839560 375 uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
AnnaBridge 163:e59c8e839560 376 This parameter can be a value of @ref HRTIM_Chopper_Frequency */
AnnaBridge 163:e59c8e839560 377 uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
AnnaBridge 163:e59c8e839560 378 This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
AnnaBridge 163:e59c8e839560 379 uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
AnnaBridge 163:e59c8e839560 380 This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
AnnaBridge 163:e59c8e839560 381 } HRTIM_ChopperModeCfgTypeDef;
AnnaBridge 163:e59c8e839560 382
AnnaBridge 163:e59c8e839560 383 /**
AnnaBridge 163:e59c8e839560 384 * @brief External event channel configuration definition
AnnaBridge 163:e59c8e839560 385 */
AnnaBridge 163:e59c8e839560 386 typedef struct {
AnnaBridge 163:e59c8e839560 387 uint32_t Source; /*!< Identifies the source of the external event.
AnnaBridge 163:e59c8e839560 388 This parameter can be a value of @ref HRTIM_External_Event_Sources */
AnnaBridge 163:e59c8e839560 389 uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
AnnaBridge 163:e59c8e839560 390 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
AnnaBridge 163:e59c8e839560 391 uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event.
AnnaBridge 163:e59c8e839560 392 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
AnnaBridge 163:e59c8e839560 393 uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
AnnaBridge 163:e59c8e839560 394 This parameter can be a value of @ref HRTIM_External_Event_Filter */
AnnaBridge 163:e59c8e839560 395 uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event.
AnnaBridge 163:e59c8e839560 396 This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
AnnaBridge 163:e59c8e839560 397 } HRTIM_EventCfgTypeDef;
AnnaBridge 163:e59c8e839560 398
AnnaBridge 163:e59c8e839560 399 /**
AnnaBridge 163:e59c8e839560 400 * @brief Fault channel configuration definition
AnnaBridge 163:e59c8e839560 401 */
AnnaBridge 163:e59c8e839560 402 typedef struct {
AnnaBridge 163:e59c8e839560 403 uint32_t Source; /*!< Identifies the source of the fault.
AnnaBridge 163:e59c8e839560 404 This parameter can be a value of @ref HRTIM_Fault_Sources */
AnnaBridge 163:e59c8e839560 405 uint32_t Polarity; /*!< Specifies the polarity of the fault event.
AnnaBridge 163:e59c8e839560 406 This parameter can be a value of @ref HRTIM_Fault_Polarity */
AnnaBridge 163:e59c8e839560 407 uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
AnnaBridge 163:e59c8e839560 408 This parameter can be a value of @ref HRTIM_Fault_Filter */
AnnaBridge 163:e59c8e839560 409 uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected.
AnnaBridge 163:e59c8e839560 410 This parameter can be a value of @ref HRTIM_Fault_Lock */
AnnaBridge 163:e59c8e839560 411 } HRTIM_FaultCfgTypeDef;
AnnaBridge 163:e59c8e839560 412
AnnaBridge 163:e59c8e839560 413 /**
AnnaBridge 163:e59c8e839560 414 * @brief Burst mode configuration definition
AnnaBridge 163:e59c8e839560 415 */
AnnaBridge 163:e59c8e839560 416 typedef struct {
AnnaBridge 163:e59c8e839560 417 uint32_t Mode; /*!< Specifies the burst mode operating mode.
AnnaBridge 163:e59c8e839560 418 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
AnnaBridge 163:e59c8e839560 419 uint32_t ClockSource; /*!< Specifies the burst mode clock source.
AnnaBridge 163:e59c8e839560 420 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
AnnaBridge 163:e59c8e839560 421 uint32_t Prescaler; /*!< Specifies the burst mode prescaler.
AnnaBridge 163:e59c8e839560 422 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
AnnaBridge 163:e59c8e839560 423 uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
AnnaBridge 163:e59c8e839560 424 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */
AnnaBridge 163:e59c8e839560 425 uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation.
AnnaBridge 163:e59c8e839560 426 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */
AnnaBridge 163:e59c8e839560 427 uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state.
AnnaBridge 163:e59c8e839560 428 This parameter can be a number between 0x0 and 0xFFFF */
AnnaBridge 163:e59c8e839560 429 uint32_t Period; /*!< Specifies burst mode repetition period.
AnnaBridge 163:e59c8e839560 430 This parameter can be a number between 0x1 and 0xFFFF */
AnnaBridge 163:e59c8e839560 431 } HRTIM_BurstModeCfgTypeDef;
AnnaBridge 163:e59c8e839560 432
AnnaBridge 163:e59c8e839560 433 /**
AnnaBridge 163:e59c8e839560 434 * @brief ADC trigger configuration definition
AnnaBridge 163:e59c8e839560 435 */
AnnaBridge 163:e59c8e839560 436 typedef struct {
AnnaBridge 163:e59c8e839560 437 uint32_t UpdateSource; /*!< Specifies the ADC trigger update source.
AnnaBridge 163:e59c8e839560 438 This parameter can be a combination of @ref HRTIM_ADC_Trigger_Update_Source */
AnnaBridge 163:e59c8e839560 439 uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion.
AnnaBridge 163:e59c8e839560 440 This parameter can be a value of @ref HRTIM_ADC_Trigger_Event */
AnnaBridge 163:e59c8e839560 441 } HRTIM_ADCTriggerCfgTypeDef;
AnnaBridge 163:e59c8e839560 442
AnnaBridge 163:e59c8e839560 443 /**
AnnaBridge 163:e59c8e839560 444 * @}
AnnaBridge 163:e59c8e839560 445 */
AnnaBridge 163:e59c8e839560 446
AnnaBridge 163:e59c8e839560 447 /* Exported constants --------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 448 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
AnnaBridge 163:e59c8e839560 449 * @{
AnnaBridge 163:e59c8e839560 450 */
AnnaBridge 163:e59c8e839560 451
AnnaBridge 163:e59c8e839560 452 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index
AnnaBridge 163:e59c8e839560 453 * @{
AnnaBridge 163:e59c8e839560 454 * @brief Constants defining the timer indexes
AnnaBridge 163:e59c8e839560 455 */
AnnaBridge 163:e59c8e839560 456 #define HRTIM_TIMERINDEX_TIMER_A 0x0U /*!< Index used to access timer A registers */
AnnaBridge 163:e59c8e839560 457 #define HRTIM_TIMERINDEX_TIMER_B 0x1U /*!< Index used to access timer B registers */
AnnaBridge 163:e59c8e839560 458 #define HRTIM_TIMERINDEX_TIMER_C 0x2U /*!< Index used to access timer C registers */
AnnaBridge 163:e59c8e839560 459 #define HRTIM_TIMERINDEX_TIMER_D 0x3U /*!< Index used to access timer D registers */
AnnaBridge 163:e59c8e839560 460 #define HRTIM_TIMERINDEX_TIMER_E 0x4U /*!< Index used to access timer E registers */
AnnaBridge 163:e59c8e839560 461 #define HRTIM_TIMERINDEX_MASTER 0x5U /*!< Index used to access master registers */
AnnaBridge 163:e59c8e839560 462 #define HRTIM_TIMERINDEX_COMMON 0xFFU /*!< Index used to access HRTIM common registers */
AnnaBridge 163:e59c8e839560 463 /**
AnnaBridge 163:e59c8e839560 464 * @}
AnnaBridge 163:e59c8e839560 465 */
AnnaBridge 163:e59c8e839560 466
AnnaBridge 163:e59c8e839560 467 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
AnnaBridge 163:e59c8e839560 468 * @{
AnnaBridge 163:e59c8e839560 469 * @brief Constants defining timer identifiers
AnnaBridge 163:e59c8e839560 470 */
AnnaBridge 163:e59c8e839560 471 #define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier*/
AnnaBridge 163:e59c8e839560 472 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */
AnnaBridge 163:e59c8e839560 473 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */
AnnaBridge 163:e59c8e839560 474 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */
AnnaBridge 163:e59c8e839560 475 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */
AnnaBridge 163:e59c8e839560 476 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */
AnnaBridge 163:e59c8e839560 477 /**
AnnaBridge 163:e59c8e839560 478 * @}
AnnaBridge 163:e59c8e839560 479 */
AnnaBridge 163:e59c8e839560 480
AnnaBridge 163:e59c8e839560 481 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
AnnaBridge 163:e59c8e839560 482 * @{
AnnaBridge 163:e59c8e839560 483 * @brief Constants defining compare unit identifiers
AnnaBridge 163:e59c8e839560 484 */
AnnaBridge 163:e59c8e839560 485 #define HRTIM_COMPAREUNIT_1 0x00000001U /*!< Compare unit 1 identifier */
AnnaBridge 163:e59c8e839560 486 #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */
AnnaBridge 163:e59c8e839560 487 #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */
AnnaBridge 163:e59c8e839560 488 #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */
AnnaBridge 163:e59c8e839560 489 /**
AnnaBridge 163:e59c8e839560 490 * @}
AnnaBridge 163:e59c8e839560 491 */
AnnaBridge 163:e59c8e839560 492
AnnaBridge 163:e59c8e839560 493 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
AnnaBridge 163:e59c8e839560 494 * @{
AnnaBridge 163:e59c8e839560 495 * @brief Constants defining capture unit identifiers
AnnaBridge 163:e59c8e839560 496 */
AnnaBridge 163:e59c8e839560 497 #define HRTIM_CAPTUREUNIT_1 0x00000001U /*!< Capture unit 1 identifier */
AnnaBridge 163:e59c8e839560 498 #define HRTIM_CAPTUREUNIT_2 0x00000002U /*!< Capture unit 2 identifier */
AnnaBridge 163:e59c8e839560 499 /**
AnnaBridge 163:e59c8e839560 500 * @}
AnnaBridge 163:e59c8e839560 501 */
AnnaBridge 163:e59c8e839560 502
AnnaBridge 163:e59c8e839560 503 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output
AnnaBridge 163:e59c8e839560 504 * @{
AnnaBridge 163:e59c8e839560 505 * @brief Constants defining timer output identifiers
AnnaBridge 163:e59c8e839560 506 */
AnnaBridge 163:e59c8e839560 507 #define HRTIM_OUTPUT_TA1 0x00000001U /*!< Timer A - Output 1 identifier */
AnnaBridge 163:e59c8e839560 508 #define HRTIM_OUTPUT_TA2 0x00000002U /*!< Timer A - Output 2 identifier */
AnnaBridge 163:e59c8e839560 509 #define HRTIM_OUTPUT_TB1 0x00000004U /*!< Timer B - Output 1 identifier */
AnnaBridge 163:e59c8e839560 510 #define HRTIM_OUTPUT_TB2 0x00000008U /*!< Timer B - Output 2 identifier */
AnnaBridge 163:e59c8e839560 511 #define HRTIM_OUTPUT_TC1 0x00000010U /*!< Timer C - Output 1 identifier */
AnnaBridge 163:e59c8e839560 512 #define HRTIM_OUTPUT_TC2 0x00000020U /*!< Timer C - Output 2 identifier */
AnnaBridge 163:e59c8e839560 513 #define HRTIM_OUTPUT_TD1 0x00000040U /*!< Timer D - Output 1 identifier */
AnnaBridge 163:e59c8e839560 514 #define HRTIM_OUTPUT_TD2 0x00000080U /*!< Timer D - Output 2 identifier */
AnnaBridge 163:e59c8e839560 515 #define HRTIM_OUTPUT_TE1 0x00000100U /*!< Timer E - Output 1 identifier */
AnnaBridge 163:e59c8e839560 516 #define HRTIM_OUTPUT_TE2 0x00000200U /*!< Timer E - Output 2 identifier */
AnnaBridge 163:e59c8e839560 517 /**
AnnaBridge 163:e59c8e839560 518 * @}
AnnaBridge 163:e59c8e839560 519 */
AnnaBridge 163:e59c8e839560 520
AnnaBridge 163:e59c8e839560 521 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
AnnaBridge 163:e59c8e839560 522 * @{
AnnaBridge 163:e59c8e839560 523 * @brief Constants defining ADC triggers identifiers
AnnaBridge 163:e59c8e839560 524 */
AnnaBridge 163:e59c8e839560 525 #define HRTIM_ADCTRIGGER_1 0x00000001U /*!< ADC trigger 1 identifier */
AnnaBridge 163:e59c8e839560 526 #define HRTIM_ADCTRIGGER_2 0x00000002U /*!< ADC trigger 2 identifier */
AnnaBridge 163:e59c8e839560 527 #define HRTIM_ADCTRIGGER_3 0x00000004U /*!< ADC trigger 3 identifier */
AnnaBridge 163:e59c8e839560 528 #define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */
AnnaBridge 163:e59c8e839560 529
AnnaBridge 163:e59c8e839560 530 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
AnnaBridge 163:e59c8e839560 531 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
AnnaBridge 163:e59c8e839560 532 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
AnnaBridge 163:e59c8e839560 533 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
AnnaBridge 163:e59c8e839560 534 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
AnnaBridge 163:e59c8e839560 535 /**
AnnaBridge 163:e59c8e839560 536 * @}
AnnaBridge 163:e59c8e839560 537 */
AnnaBridge 163:e59c8e839560 538
AnnaBridge 163:e59c8e839560 539 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
AnnaBridge 163:e59c8e839560 540 * @{
AnnaBridge 163:e59c8e839560 541 * @brief Constants defining external event channel identifiers
AnnaBridge 163:e59c8e839560 542 */
AnnaBridge 163:e59c8e839560 543 #define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */
AnnaBridge 163:e59c8e839560 544 #define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */
AnnaBridge 163:e59c8e839560 545 #define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */
AnnaBridge 163:e59c8e839560 546 #define HRTIM_EVENT_3 (0x00000004U) /*!< External event channel 3 identifier */
AnnaBridge 163:e59c8e839560 547 #define HRTIM_EVENT_4 (0x00000008U) /*!< External event channel 4 identifier */
AnnaBridge 163:e59c8e839560 548 #define HRTIM_EVENT_5 (0x00000010U) /*!< External event channel 5 identifier */
AnnaBridge 163:e59c8e839560 549 #define HRTIM_EVENT_6 (0x00000020U) /*!< External event channel 6 identifier */
AnnaBridge 163:e59c8e839560 550 #define HRTIM_EVENT_7 (0x00000040U) /*!< External event channel 7 identifier */
AnnaBridge 163:e59c8e839560 551 #define HRTIM_EVENT_8 (0x00000080U) /*!< External event channel 8 identifier */
AnnaBridge 163:e59c8e839560 552 #define HRTIM_EVENT_9 (0x00000100U) /*!< External event channel 9 identifier */
AnnaBridge 163:e59c8e839560 553 #define HRTIM_EVENT_10 (0x00000200U) /*!< External event channel 10 identifier */
AnnaBridge 163:e59c8e839560 554 /**
AnnaBridge 163:e59c8e839560 555 * @}
AnnaBridge 163:e59c8e839560 556 */
AnnaBridge 163:e59c8e839560 557
AnnaBridge 163:e59c8e839560 558 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
AnnaBridge 163:e59c8e839560 559 * @{
AnnaBridge 163:e59c8e839560 560 * @brief Constants defining fault channel identifiers
AnnaBridge 163:e59c8e839560 561 */
AnnaBridge 163:e59c8e839560 562 #define HRTIM_FAULT_1 (0x01U) /*!< Fault channel 1 identifier */
AnnaBridge 163:e59c8e839560 563 #define HRTIM_FAULT_2 (0x02U) /*!< Fault channel 2 identifier */
AnnaBridge 163:e59c8e839560 564 #define HRTIM_FAULT_3 (0x04U) /*!< Fault channel 3 identifier */
AnnaBridge 163:e59c8e839560 565 #define HRTIM_FAULT_4 (0x08U) /*!< Fault channel 4 identifier */
AnnaBridge 163:e59c8e839560 566 #define HRTIM_FAULT_5 (0x10U) /*!< Fault channel 5 identifier */
AnnaBridge 163:e59c8e839560 567 /**
AnnaBridge 163:e59c8e839560 568 * @}
AnnaBridge 163:e59c8e839560 569 */
AnnaBridge 163:e59c8e839560 570
AnnaBridge 163:e59c8e839560 571
AnnaBridge 163:e59c8e839560 572 /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
AnnaBridge 163:e59c8e839560 573 * @{
AnnaBridge 163:e59c8e839560 574 * @brief Constants defining timer high-resolution clock prescaler ratio.
AnnaBridge 163:e59c8e839560 575 */
AnnaBridge 163:e59c8e839560 576 #define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
AnnaBridge 163:e59c8e839560 577 #define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
AnnaBridge 163:e59c8e839560 578 #define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
AnnaBridge 163:e59c8e839560 579 #define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
AnnaBridge 163:e59c8e839560 580 #define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
AnnaBridge 163:e59c8e839560 581 #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
AnnaBridge 163:e59c8e839560 582 #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
AnnaBridge 163:e59c8e839560 583 #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
AnnaBridge 163:e59c8e839560 584 /**
AnnaBridge 163:e59c8e839560 585 * @}
AnnaBridge 163:e59c8e839560 586 */
AnnaBridge 163:e59c8e839560 587
AnnaBridge 163:e59c8e839560 588 /** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
AnnaBridge 163:e59c8e839560 589 * @{
AnnaBridge 163:e59c8e839560 590 * @brief Constants defining timer counter operating mode.
AnnaBridge 163:e59c8e839560 591 */
AnnaBridge 163:e59c8e839560 592 #define HRTIM_MODE_CONTINUOUS (0x00000008U) /*!< The timer operates in continuous (free-running) mode */
AnnaBridge 163:e59c8e839560 593 #define HRTIM_MODE_SINGLESHOT (0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */
AnnaBridge 163:e59c8e839560 594 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
AnnaBridge 163:e59c8e839560 595 /**
AnnaBridge 163:e59c8e839560 596 * @}
AnnaBridge 163:e59c8e839560 597 */
AnnaBridge 163:e59c8e839560 598
AnnaBridge 163:e59c8e839560 599 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
AnnaBridge 163:e59c8e839560 600 * @{
AnnaBridge 163:e59c8e839560 601 * @brief Constants defining half mode enabling status.
AnnaBridge 163:e59c8e839560 602 */
AnnaBridge 163:e59c8e839560 603 #define HRTIM_HALFMODE_DISABLED (0x00000000U) /*!< Half mode is disabled */
AnnaBridge 163:e59c8e839560 604 #define HRTIM_HALFMODE_ENABLED (0x00000020U) /*!< Half mode is enabled */
AnnaBridge 163:e59c8e839560 605 /**
AnnaBridge 163:e59c8e839560 606 * @}
AnnaBridge 163:e59c8e839560 607 */
AnnaBridge 163:e59c8e839560 608
AnnaBridge 163:e59c8e839560 609 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
AnnaBridge 163:e59c8e839560 610 * @{
AnnaBridge 163:e59c8e839560 611 * @brief Constants defining the timer behavior following the synchronization event
AnnaBridge 163:e59c8e839560 612 */
AnnaBridge 163:e59c8e839560 613 #define HRTIM_SYNCSTART_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
AnnaBridge 163:e59c8e839560 614 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
AnnaBridge 163:e59c8e839560 615 /**
AnnaBridge 163:e59c8e839560 616 * @}
AnnaBridge 163:e59c8e839560 617 */
AnnaBridge 163:e59c8e839560 618
AnnaBridge 163:e59c8e839560 619 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
AnnaBridge 163:e59c8e839560 620 * @{
AnnaBridge 163:e59c8e839560 621 * @brief Constants defining the timer behavior following the synchronization event
AnnaBridge 163:e59c8e839560 622 */
AnnaBridge 163:e59c8e839560 623 #define HRTIM_SYNCRESET_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
AnnaBridge 163:e59c8e839560 624 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
AnnaBridge 163:e59c8e839560 625 /**
AnnaBridge 163:e59c8e839560 626 * @}
AnnaBridge 163:e59c8e839560 627 */
AnnaBridge 163:e59c8e839560 628
AnnaBridge 163:e59c8e839560 629 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
AnnaBridge 163:e59c8e839560 630 * @{
AnnaBridge 163:e59c8e839560 631 * @brief Constants defining on which output the DAC synchronization event is sent
AnnaBridge 163:e59c8e839560 632 */
AnnaBridge 163:e59c8e839560 633 #define HRTIM_DACSYNC_NONE 0x00000000U /*!< No DAC synchronization event generated */
AnnaBridge 163:e59c8e839560 634 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
AnnaBridge 163:e59c8e839560 635 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
AnnaBridge 163:e59c8e839560 636 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
AnnaBridge 163:e59c8e839560 637 /**
AnnaBridge 163:e59c8e839560 638 * @}
AnnaBridge 163:e59c8e839560 639 */
AnnaBridge 163:e59c8e839560 640
AnnaBridge 163:e59c8e839560 641 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
AnnaBridge 163:e59c8e839560 642 * @{
AnnaBridge 163:e59c8e839560 643 * @brief Constants defining whether a write access into a preloadable
AnnaBridge 163:e59c8e839560 644 * register is done into the active or the preload register.
AnnaBridge 163:e59c8e839560 645 */
AnnaBridge 163:e59c8e839560 646 #define HRTIM_PRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into the active register */
AnnaBridge 163:e59c8e839560 647 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
AnnaBridge 163:e59c8e839560 648 /**
AnnaBridge 163:e59c8e839560 649 * @}
AnnaBridge 163:e59c8e839560 650 */
AnnaBridge 163:e59c8e839560 651
AnnaBridge 163:e59c8e839560 652 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating
AnnaBridge 163:e59c8e839560 653 * @{
AnnaBridge 163:e59c8e839560 654 * @brief Constants defining how the update occurs relatively to the burst DMA
AnnaBridge 163:e59c8e839560 655 * transaction and the external update request on update enable inputs 1 to 3.
AnnaBridge 163:e59c8e839560 656 */
AnnaBridge 163:e59c8e839560 657 #define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
AnnaBridge 163:e59c8e839560 658 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
AnnaBridge 163:e59c8e839560 659 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
AnnaBridge 163:e59c8e839560 660 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */
AnnaBridge 163:e59c8e839560 661 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */
AnnaBridge 163:e59c8e839560 662 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */
AnnaBridge 163:e59c8e839560 663 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U */
AnnaBridge 163:e59c8e839560 664 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U */
AnnaBridge 163:e59c8e839560 665 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U */
AnnaBridge 163:e59c8e839560 666 /**
AnnaBridge 163:e59c8e839560 667 * @}
AnnaBridge 163:e59c8e839560 668 */
AnnaBridge 163:e59c8e839560 669
AnnaBridge 163:e59c8e839560 670 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
AnnaBridge 163:e59c8e839560 671 * @{
AnnaBridge 163:e59c8e839560 672 * @brief Constants defining how the timer behaves during a burst
AnnaBridge 163:e59c8e839560 673 mode operation.
AnnaBridge 163:e59c8e839560 674 */
AnnaBridge 163:e59c8e839560 675 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x000000U /*!< Timer counter clock is maintained and the timer operates normally */
AnnaBridge 163:e59c8e839560 676 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
AnnaBridge 163:e59c8e839560 677 /**
AnnaBridge 163:e59c8e839560 678 * @}
AnnaBridge 163:e59c8e839560 679 */
AnnaBridge 163:e59c8e839560 680
AnnaBridge 163:e59c8e839560 681 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
AnnaBridge 163:e59c8e839560 682 * @{
AnnaBridge 163:e59c8e839560 683 * @brief Constants defining whether registers are updated when the timer
AnnaBridge 163:e59c8e839560 684 * repetition period is completed (either due to roll-over or
AnnaBridge 163:e59c8e839560 685 * reset events)
AnnaBridge 163:e59c8e839560 686 */
AnnaBridge 163:e59c8e839560 687 #define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U /*!< Update on repetition disabled */
AnnaBridge 163:e59c8e839560 688 #define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */
AnnaBridge 163:e59c8e839560 689 /**
AnnaBridge 163:e59c8e839560 690 * @}
AnnaBridge 163:e59c8e839560 691 */
AnnaBridge 163:e59c8e839560 692
AnnaBridge 163:e59c8e839560 693
AnnaBridge 163:e59c8e839560 694 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
AnnaBridge 163:e59c8e839560 695 * @{
AnnaBridge 163:e59c8e839560 696 * @brief Constants defining whether or not the puhs-pull mode is enabled for
AnnaBridge 163:e59c8e839560 697 * a timer.
AnnaBridge 163:e59c8e839560 698 */
AnnaBridge 163:e59c8e839560 699 #define HRTIM_TIMPUSHPULLMODE_DISABLED (0x00000000U) /*!< Push-Pull mode disabled */
AnnaBridge 163:e59c8e839560 700 #define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
AnnaBridge 163:e59c8e839560 701 /**
AnnaBridge 163:e59c8e839560 702 * @}
AnnaBridge 163:e59c8e839560 703 */
AnnaBridge 163:e59c8e839560 704
AnnaBridge 163:e59c8e839560 705 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
AnnaBridge 163:e59c8e839560 706 * @{
AnnaBridge 163:e59c8e839560 707 * @brief Constants defining whether a faut channel is enabled for a timer
AnnaBridge 163:e59c8e839560 708 */
AnnaBridge 163:e59c8e839560 709 #define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */
AnnaBridge 163:e59c8e839560 710 #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */
AnnaBridge 163:e59c8e839560 711 #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */
AnnaBridge 163:e59c8e839560 712 #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */
AnnaBridge 163:e59c8e839560 713 #define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */
AnnaBridge 163:e59c8e839560 714 #define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */
AnnaBridge 163:e59c8e839560 715 /**
AnnaBridge 163:e59c8e839560 716 * @}
AnnaBridge 163:e59c8e839560 717 */
AnnaBridge 163:e59c8e839560 718
AnnaBridge 163:e59c8e839560 719 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
AnnaBridge 163:e59c8e839560 720 * @{
AnnaBridge 163:e59c8e839560 721 * @brief Constants defining whether or not fault enabling bits are write
AnnaBridge 163:e59c8e839560 722 * protected for a timer
AnnaBridge 163:e59c8e839560 723 */
AnnaBridge 163:e59c8e839560 724 #define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /*!< Timer fault enabling bits are read/write */
AnnaBridge 163:e59c8e839560 725 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */
AnnaBridge 163:e59c8e839560 726 /**
AnnaBridge 163:e59c8e839560 727 * @}
AnnaBridge 163:e59c8e839560 728 */
AnnaBridge 163:e59c8e839560 729
AnnaBridge 163:e59c8e839560 730 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Deadtime Insertion
AnnaBridge 163:e59c8e839560 731 * @{
AnnaBridge 163:e59c8e839560 732 * @brief Constants defining whether or not fault the dead time insertion
AnnaBridge 163:e59c8e839560 733 * feature is enabled for a timer
AnnaBridge 163:e59c8e839560 734 */
AnnaBridge 163:e59c8e839560 735 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /*!< Output 1 and output 2 signals are independent */
AnnaBridge 163:e59c8e839560 736 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2U */
AnnaBridge 163:e59c8e839560 737 /**
AnnaBridge 163:e59c8e839560 738 * @}
AnnaBridge 163:e59c8e839560 739 */
AnnaBridge 163:e59c8e839560 740
AnnaBridge 163:e59c8e839560 741 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
AnnaBridge 163:e59c8e839560 742 * @{
AnnaBridge 163:e59c8e839560 743 * @brief Constants defining all possible delayed protection modes
AnnaBridge 163:e59c8e839560 744 * for a timer. Also definethe source and outputs on which the delayed
AnnaBridge 163:e59c8e839560 745 * protection schemes are applied
AnnaBridge 163:e59c8e839560 746 */
AnnaBridge 163:e59c8e839560 747 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */
AnnaBridge 163:e59c8e839560 748 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */
AnnaBridge 163:e59c8e839560 749 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */
AnnaBridge 163:e59c8e839560 750 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */
AnnaBridge 163:e59c8e839560 751 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6U */
AnnaBridge 163:e59c8e839560 752 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */
AnnaBridge 163:e59c8e839560 753 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */
AnnaBridge 163:e59c8e839560 754 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */
AnnaBridge 163:e59c8e839560 755 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */
AnnaBridge 163:e59c8e839560 756
AnnaBridge 163:e59c8e839560 757 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */
AnnaBridge 163:e59c8e839560 758 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */
AnnaBridge 163:e59c8e839560 759 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */
AnnaBridge 163:e59c8e839560 760 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */
AnnaBridge 163:e59c8e839560 761 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */
AnnaBridge 163:e59c8e839560 762 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */
AnnaBridge 163:e59c8e839560 763 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */
AnnaBridge 163:e59c8e839560 764 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */
AnnaBridge 163:e59c8e839560 765 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */
AnnaBridge 163:e59c8e839560 766 /**
AnnaBridge 163:e59c8e839560 767 * @}
AnnaBridge 163:e59c8e839560 768 */
AnnaBridge 163:e59c8e839560 769
AnnaBridge 163:e59c8e839560 770 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
AnnaBridge 163:e59c8e839560 771 * @{
AnnaBridge 163:e59c8e839560 772 * @brief Constants defining whether the registers update is done synchronously
AnnaBridge 163:e59c8e839560 773 * with any other timer or master update
AnnaBridge 163:e59c8e839560 774 */
AnnaBridge 163:e59c8e839560 775 #define HRTIM_TIMUPDATETRIGGER_NONE 0x00000000U /*!< Register update is disabled */
AnnaBridge 163:e59c8e839560 776 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
AnnaBridge 163:e59c8e839560 777 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
AnnaBridge 163:e59c8e839560 778 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
AnnaBridge 163:e59c8e839560 779 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/
AnnaBridge 163:e59c8e839560 780 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */
AnnaBridge 163:e59c8e839560 781 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */
AnnaBridge 163:e59c8e839560 782 /**
AnnaBridge 163:e59c8e839560 783 * @}
AnnaBridge 163:e59c8e839560 784 */
AnnaBridge 163:e59c8e839560 785
AnnaBridge 163:e59c8e839560 786 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
AnnaBridge 163:e59c8e839560 787 * @{
AnnaBridge 163:e59c8e839560 788 * @brief Constants defining the events that can be selected to trigger the reset
AnnaBridge 163:e59c8e839560 789 * of the timer counter
AnnaBridge 163:e59c8e839560 790 */
AnnaBridge 163:e59c8e839560 791 #define HRTIM_TIMRESETTRIGGER_NONE 0x00000000U /*!< No counter reset trigger */
AnnaBridge 163:e59c8e839560 792 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
AnnaBridge 163:e59c8e839560 793 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
AnnaBridge 163:e59c8e839560 794 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
AnnaBridge 163:e59c8e839560 795 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */
AnnaBridge 163:e59c8e839560 796 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */
AnnaBridge 163:e59c8e839560 797 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
AnnaBridge 163:e59c8e839560 798 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
AnnaBridge 163:e59c8e839560 799 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
AnnaBridge 163:e59c8e839560 800 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1U */
AnnaBridge 163:e59c8e839560 801 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2U */
AnnaBridge 163:e59c8e839560 802 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3U */
AnnaBridge 163:e59c8e839560 803 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4U */
AnnaBridge 163:e59c8e839560 804 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5U */
AnnaBridge 163:e59c8e839560 805 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6U */
AnnaBridge 163:e59c8e839560 806 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7U */
AnnaBridge 163:e59c8e839560 807 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8U */
AnnaBridge 163:e59c8e839560 808 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9U */
AnnaBridge 163:e59c8e839560 809 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */
AnnaBridge 163:e59c8e839560 810 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
AnnaBridge 163:e59c8e839560 811 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
AnnaBridge 163:e59c8e839560 812 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
AnnaBridge 163:e59c8e839560 813 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
AnnaBridge 163:e59c8e839560 814 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
AnnaBridge 163:e59c8e839560 815 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
AnnaBridge 163:e59c8e839560 816 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
AnnaBridge 163:e59c8e839560 817 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
AnnaBridge 163:e59c8e839560 818 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
AnnaBridge 163:e59c8e839560 819 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
AnnaBridge 163:e59c8e839560 820 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
AnnaBridge 163:e59c8e839560 821 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
AnnaBridge 163:e59c8e839560 822 /**
AnnaBridge 163:e59c8e839560 823 * @}
AnnaBridge 163:e59c8e839560 824 */
AnnaBridge 163:e59c8e839560 825
AnnaBridge 163:e59c8e839560 826 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
AnnaBridge 163:e59c8e839560 827 * @{
AnnaBridge 163:e59c8e839560 828 * @brief Constants defining whether the register are updated upon Timerx
AnnaBridge 163:e59c8e839560 829 * counter reset or roll-over to 0 after reaching the period value
AnnaBridge 163:e59c8e839560 830 * in continuous mode
AnnaBridge 163:e59c8e839560 831 */
AnnaBridge 163:e59c8e839560 832 #define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */
AnnaBridge 163:e59c8e839560 833 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */
AnnaBridge 163:e59c8e839560 834 /**
AnnaBridge 163:e59c8e839560 835 * @}
AnnaBridge 163:e59c8e839560 836 */
AnnaBridge 163:e59c8e839560 837
AnnaBridge 163:e59c8e839560 838 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
AnnaBridge 163:e59c8e839560 839 * @{
AnnaBridge 163:e59c8e839560 840 * @brief Constants defining whether the compare register is behaving in
AnnaBridge 163:e59c8e839560 841 * regular mode (compare match issued as soon as counter equal compare),
AnnaBridge 163:e59c8e839560 842 * or in auto-delayed mode
AnnaBridge 163:e59c8e839560 843 */
AnnaBridge 163:e59c8e839560 844 #define HRTIM_AUTODELAYEDMODE_REGULAR (0x00000000U) /*!< standard compare mode */
AnnaBridge 163:e59c8e839560 845 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
AnnaBridge 163:e59c8e839560 846 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
AnnaBridge 163:e59c8e839560 847 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
AnnaBridge 163:e59c8e839560 848 /**
AnnaBridge 163:e59c8e839560 849 * @}
AnnaBridge 163:e59c8e839560 850 */
AnnaBridge 163:e59c8e839560 851
AnnaBridge 163:e59c8e839560 852 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
AnnaBridge 163:e59c8e839560 853 * @{
AnnaBridge 163:e59c8e839560 854 * @brief Constants defining the behavior of the output signal when the timer
AnnaBridge 163:e59c8e839560 855 operates in basic output compare mode
AnnaBridge 163:e59c8e839560 856 */
AnnaBridge 163:e59c8e839560 857 #define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /*!< Output toggles when the timer counter reaches the compare value */
AnnaBridge 163:e59c8e839560 858 #define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /*!< Output forced to active level when the timer counter reaches the compare value */
AnnaBridge 163:e59c8e839560 859 #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */
AnnaBridge 163:e59c8e839560 860
AnnaBridge 163:e59c8e839560 861 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
AnnaBridge 163:e59c8e839560 862 (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
AnnaBridge 163:e59c8e839560 863 ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
AnnaBridge 163:e59c8e839560 864 ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
AnnaBridge 163:e59c8e839560 865 /**
AnnaBridge 163:e59c8e839560 866 * @}
AnnaBridge 163:e59c8e839560 867 */
AnnaBridge 163:e59c8e839560 868
AnnaBridge 163:e59c8e839560 869 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
AnnaBridge 163:e59c8e839560 870 * @{
AnnaBridge 163:e59c8e839560 871 * @brief Constants defining the polarity of a timer output
AnnaBridge 163:e59c8e839560 872 */
AnnaBridge 163:e59c8e839560 873 #define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is acitve HIGH */
AnnaBridge 163:e59c8e839560 874 #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
AnnaBridge 163:e59c8e839560 875 /**
AnnaBridge 163:e59c8e839560 876 * @}
AnnaBridge 163:e59c8e839560 877 */
AnnaBridge 163:e59c8e839560 878
AnnaBridge 163:e59c8e839560 879 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
AnnaBridge 163:e59c8e839560 880 * @{
AnnaBridge 163:e59c8e839560 881 * @brief Constants defining the events that can be selected to configure the
AnnaBridge 163:e59c8e839560 882 * set crossbar of a timer output
AnnaBridge 163:e59c8e839560 883 */
AnnaBridge 163:e59c8e839560 884 #define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
AnnaBridge 163:e59c8e839560 885 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
AnnaBridge 163:e59c8e839560 886 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
AnnaBridge 163:e59c8e839560 887 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
AnnaBridge 163:e59c8e839560 888 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
AnnaBridge 163:e59c8e839560 889 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
AnnaBridge 163:e59c8e839560 890 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
AnnaBridge 163:e59c8e839560 891 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
AnnaBridge 163:e59c8e839560 892 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
AnnaBridge 163:e59c8e839560 893 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
AnnaBridge 163:e59c8e839560 894 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
AnnaBridge 163:e59c8e839560 895 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
AnnaBridge 163:e59c8e839560 896 #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
AnnaBridge 163:e59c8e839560 897 #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
AnnaBridge 163:e59c8e839560 898 #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
AnnaBridge 163:e59c8e839560 899 #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
AnnaBridge 163:e59c8e839560 900 #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
AnnaBridge 163:e59c8e839560 901 #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
AnnaBridge 163:e59c8e839560 902 #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
AnnaBridge 163:e59c8e839560 903 #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
AnnaBridge 163:e59c8e839560 904 #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
AnnaBridge 163:e59c8e839560 905 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
AnnaBridge 163:e59c8e839560 906 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
AnnaBridge 163:e59c8e839560 907 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
AnnaBridge 163:e59c8e839560 908 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
AnnaBridge 163:e59c8e839560 909 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
AnnaBridge 163:e59c8e839560 910 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
AnnaBridge 163:e59c8e839560 911 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
AnnaBridge 163:e59c8e839560 912 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
AnnaBridge 163:e59c8e839560 913 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
AnnaBridge 163:e59c8e839560 914 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
AnnaBridge 163:e59c8e839560 915 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
AnnaBridge 163:e59c8e839560 916 /**
AnnaBridge 163:e59c8e839560 917 * @}
AnnaBridge 163:e59c8e839560 918 */
AnnaBridge 163:e59c8e839560 919
AnnaBridge 163:e59c8e839560 920 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
AnnaBridge 163:e59c8e839560 921 * @{
AnnaBridge 163:e59c8e839560 922 * @brief Constants defining the events that can be selected to configure the
AnnaBridge 163:e59c8e839560 923 * set crossbar of a timer output
AnnaBridge 163:e59c8e839560 924 */
AnnaBridge 163:e59c8e839560 925 #define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
AnnaBridge 163:e59c8e839560 926 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 927 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 928 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 929 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 930 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 931 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 932 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 933 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 934 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 935 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 936 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 937 #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 938 #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 939 #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 940 #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 941 #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 942 #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 943 #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 944 #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 945 #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 946 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 947 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 948 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 949 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 950 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 951 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 952 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 953 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 954 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 955 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 956 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 957 /**
AnnaBridge 163:e59c8e839560 958 * @}
AnnaBridge 163:e59c8e839560 959 */
AnnaBridge 163:e59c8e839560 960
AnnaBridge 163:e59c8e839560 961 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
AnnaBridge 163:e59c8e839560 962 * @{
AnnaBridge 163:e59c8e839560 963 * @brief Constants defining whether or not the timer output transition to its
AnnaBridge 163:e59c8e839560 964 IDLE state when burst mode is entered
AnnaBridge 163:e59c8e839560 965 */
AnnaBridge 163:e59c8e839560 966 #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */
AnnaBridge 163:e59c8e839560 967 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
AnnaBridge 163:e59c8e839560 968 /**
AnnaBridge 163:e59c8e839560 969 * @}
AnnaBridge 163:e59c8e839560 970 */
AnnaBridge 163:e59c8e839560 971
AnnaBridge 163:e59c8e839560 972 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
AnnaBridge 163:e59c8e839560 973 * @{
AnnaBridge 163:e59c8e839560 974 * @brief Constants defining the output level when output is in IDLE state
AnnaBridge 163:e59c8e839560 975 */
AnnaBridge 163:e59c8e839560 976 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
AnnaBridge 163:e59c8e839560 977 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
AnnaBridge 163:e59c8e839560 978 /**
AnnaBridge 163:e59c8e839560 979 * @}
AnnaBridge 163:e59c8e839560 980 */
AnnaBridge 163:e59c8e839560 981
AnnaBridge 163:e59c8e839560 982 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
AnnaBridge 163:e59c8e839560 983 * @{
AnnaBridge 163:e59c8e839560 984 * @brief Constants defining the output level when output is in FAULT state
AnnaBridge 163:e59c8e839560 985 */
AnnaBridge 163:e59c8e839560 986 #define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */
AnnaBridge 163:e59c8e839560 987 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
AnnaBridge 163:e59c8e839560 988 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
AnnaBridge 163:e59c8e839560 989 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
AnnaBridge 163:e59c8e839560 990 /**
AnnaBridge 163:e59c8e839560 991 * @}
AnnaBridge 163:e59c8e839560 992 */
AnnaBridge 163:e59c8e839560 993
AnnaBridge 163:e59c8e839560 994 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
AnnaBridge 163:e59c8e839560 995 * @{
AnnaBridge 163:e59c8e839560 996 * @brief Constants defining whether or not chopper mode is enabled for a timer
AnnaBridge 163:e59c8e839560 997 output
AnnaBridge 163:e59c8e839560 998 */
AnnaBridge 163:e59c8e839560 999 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
AnnaBridge 163:e59c8e839560 1000 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
AnnaBridge 163:e59c8e839560 1001 /**
AnnaBridge 163:e59c8e839560 1002 * @}
AnnaBridge 163:e59c8e839560 1003 */
AnnaBridge 163:e59c8e839560 1004
AnnaBridge 163:e59c8e839560 1005 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
AnnaBridge 163:e59c8e839560 1006 * @{
AnnaBridge 163:e59c8e839560 1007 * @brief Constants defining the idle mode entry is delayed by forcing a
AnnaBridge 163:e59c8e839560 1008 deadtime insertion before switching the outputs to their idle state
AnnaBridge 163:e59c8e839560 1009 */
AnnaBridge 163:e59c8e839560 1010 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
AnnaBridge 163:e59c8e839560 1011 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
AnnaBridge 163:e59c8e839560 1012 /**
AnnaBridge 163:e59c8e839560 1013 * @}
AnnaBridge 163:e59c8e839560 1014 */
AnnaBridge 163:e59c8e839560 1015
AnnaBridge 163:e59c8e839560 1016 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
AnnaBridge 163:e59c8e839560 1017 * @{
AnnaBridge 163:e59c8e839560 1018 * @brief Constants defining the events that can be selected to trigger the
AnnaBridge 163:e59c8e839560 1019 * capture of the timing unit counter
AnnaBridge 163:e59c8e839560 1020 */
AnnaBridge 163:e59c8e839560 1021 #define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */
AnnaBridge 163:e59c8e839560 1022 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
AnnaBridge 163:e59c8e839560 1023 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
AnnaBridge 163:e59c8e839560 1024 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
AnnaBridge 163:e59c8e839560 1025 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */
AnnaBridge 163:e59c8e839560 1026 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */
AnnaBridge 163:e59c8e839560 1027 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */
AnnaBridge 163:e59c8e839560 1028 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */
AnnaBridge 163:e59c8e839560 1029 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */
AnnaBridge 163:e59c8e839560 1030 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */
AnnaBridge 163:e59c8e839560 1031 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */
AnnaBridge 163:e59c8e839560 1032 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
AnnaBridge 163:e59c8e839560 1033 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */
AnnaBridge 163:e59c8e839560 1034 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */
AnnaBridge 163:e59c8e839560 1035 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */
AnnaBridge 163:e59c8e839560 1036 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */
AnnaBridge 163:e59c8e839560 1037 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */
AnnaBridge 163:e59c8e839560 1038 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */
AnnaBridge 163:e59c8e839560 1039 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */
AnnaBridge 163:e59c8e839560 1040 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */
AnnaBridge 163:e59c8e839560 1041 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */
AnnaBridge 163:e59c8e839560 1042 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */
AnnaBridge 163:e59c8e839560 1043 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */
AnnaBridge 163:e59c8e839560 1044 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */
AnnaBridge 163:e59c8e839560 1045 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */
AnnaBridge 163:e59c8e839560 1046 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */
AnnaBridge 163:e59c8e839560 1047 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */
AnnaBridge 163:e59c8e839560 1048 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */
AnnaBridge 163:e59c8e839560 1049 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */
AnnaBridge 163:e59c8e839560 1050 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */
AnnaBridge 163:e59c8e839560 1051 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */
AnnaBridge 163:e59c8e839560 1052 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */
AnnaBridge 163:e59c8e839560 1053 /**
AnnaBridge 163:e59c8e839560 1054 * @}
AnnaBridge 163:e59c8e839560 1055 */
AnnaBridge 163:e59c8e839560 1056
AnnaBridge 163:e59c8e839560 1057 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
AnnaBridge 163:e59c8e839560 1058 * @{
AnnaBridge 163:e59c8e839560 1059 * @brief Constants defining the event filtering apploed to external events
AnnaBridge 163:e59c8e839560 1060 * by a timer
AnnaBridge 163:e59c8e839560 1061 */
AnnaBridge 163:e59c8e839560 1062 #define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
AnnaBridge 163:e59c8e839560 1063 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
AnnaBridge 163:e59c8e839560 1064 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
AnnaBridge 163:e59c8e839560 1065 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
AnnaBridge 163:e59c8e839560 1066 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
AnnaBridge 163:e59c8e839560 1067 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
AnnaBridge 163:e59c8e839560 1068 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
AnnaBridge 163:e59c8e839560 1069 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
AnnaBridge 163:e59c8e839560 1070 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
AnnaBridge 163:e59c8e839560 1071 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
AnnaBridge 163:e59c8e839560 1072 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
AnnaBridge 163:e59c8e839560 1073 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
AnnaBridge 163:e59c8e839560 1074 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
AnnaBridge 163:e59c8e839560 1075 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
AnnaBridge 163:e59c8e839560 1076 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
AnnaBridge 163:e59c8e839560 1077 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
AnnaBridge 163:e59c8e839560 1078 /**
AnnaBridge 163:e59c8e839560 1079 * @}
AnnaBridge 163:e59c8e839560 1080 */
AnnaBridge 163:e59c8e839560 1081
AnnaBridge 163:e59c8e839560 1082 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
AnnaBridge 163:e59c8e839560 1083 * @{
AnnaBridge 163:e59c8e839560 1084 * @brief Constants defining whether or not the external event is
AnnaBridge 163:e59c8e839560 1085 * memorized (latched) and generated as soon as the blanking period
AnnaBridge 163:e59c8e839560 1086 * is completed or the window ends
AnnaBridge 163:e59c8e839560 1087 */
AnnaBridge 163:e59c8e839560 1088 #define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */
AnnaBridge 163:e59c8e839560 1089 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
AnnaBridge 163:e59c8e839560 1090 /**
AnnaBridge 163:e59c8e839560 1091 * @}
AnnaBridge 163:e59c8e839560 1092 */
AnnaBridge 163:e59c8e839560 1093
AnnaBridge 163:e59c8e839560 1094 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Deadtime Prescaler Ratio
AnnaBridge 163:e59c8e839560 1095 * @{
AnnaBridge 163:e59c8e839560 1096 * @brief Constants defining division ratio between the timer clock frequency
AnnaBridge 163:e59c8e839560 1097 * (fHRTIM) and the deadtime generator clock (fDTG)
AnnaBridge 163:e59c8e839560 1098 */
AnnaBridge 163:e59c8e839560 1099 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< fDTG = fHRTIM * 8U */
AnnaBridge 163:e59c8e839560 1100 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4U */
AnnaBridge 163:e59c8e839560 1101 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2U */
AnnaBridge 163:e59c8e839560 1102 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
AnnaBridge 163:e59c8e839560 1103 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */
AnnaBridge 163:e59c8e839560 1104 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */
AnnaBridge 163:e59c8e839560 1105 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */
AnnaBridge 163:e59c8e839560 1106 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */
AnnaBridge 163:e59c8e839560 1107 /**
AnnaBridge 163:e59c8e839560 1108 * @}
AnnaBridge 163:e59c8e839560 1109 */
AnnaBridge 163:e59c8e839560 1110
AnnaBridge 163:e59c8e839560 1111 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Deadtime Rising Sign
AnnaBridge 163:e59c8e839560 1112 * @{
AnnaBridge 163:e59c8e839560 1113 * @brief Constants defining whether the deadtime is positive or negative
AnnaBridge 163:e59c8e839560 1114 * (overlapping signal) on rising edge
AnnaBridge 163:e59c8e839560 1115 */
AnnaBridge 163:e59c8e839560 1116 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on rising edge */
AnnaBridge 163:e59c8e839560 1117 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
AnnaBridge 163:e59c8e839560 1118 /**
AnnaBridge 163:e59c8e839560 1119 * @}
AnnaBridge 163:e59c8e839560 1120 */
AnnaBridge 163:e59c8e839560 1121
AnnaBridge 163:e59c8e839560 1122 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Deadtime Rising Lock
AnnaBridge 163:e59c8e839560 1123 * @{
AnnaBridge 163:e59c8e839560 1124 * @brief Constants defining whether or not the deadtime (rising sign and
AnnaBridge 163:e59c8e839560 1125 * value) is write protected
AnnaBridge 163:e59c8e839560 1126 */
AnnaBridge 163:e59c8e839560 1127 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /*!< Deadtime rising value and sign is writeable */
AnnaBridge 163:e59c8e839560 1128 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */
AnnaBridge 163:e59c8e839560 1129 /**
AnnaBridge 163:e59c8e839560 1130 * @}
AnnaBridge 163:e59c8e839560 1131 */
AnnaBridge 163:e59c8e839560 1132
AnnaBridge 163:e59c8e839560 1133 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Deadtime Rising Sign Lock
AnnaBridge 163:e59c8e839560 1134 * @{
AnnaBridge 163:e59c8e839560 1135 * @brief Constants defining whether or not the deadtime rising sign is write
AnnaBridge 163:e59c8e839560 1136 * protected
AnnaBridge 163:e59c8e839560 1137 */
AnnaBridge 163:e59c8e839560 1138 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime rising sign is writeable */
AnnaBridge 163:e59c8e839560 1139 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */
AnnaBridge 163:e59c8e839560 1140 /**
AnnaBridge 163:e59c8e839560 1141 * @}
AnnaBridge 163:e59c8e839560 1142 */
AnnaBridge 163:e59c8e839560 1143
AnnaBridge 163:e59c8e839560 1144 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Deadtime Falling Sign
AnnaBridge 163:e59c8e839560 1145 * @{
AnnaBridge 163:e59c8e839560 1146 * @brief Constants defining whether the deadtime is positive or negative
AnnaBridge 163:e59c8e839560 1147 * (overlapping signal) on falling edge
AnnaBridge 163:e59c8e839560 1148 */
AnnaBridge 163:e59c8e839560 1149 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on falling edge */
AnnaBridge 163:e59c8e839560 1150 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
AnnaBridge 163:e59c8e839560 1151 /**
AnnaBridge 163:e59c8e839560 1152 * @}
AnnaBridge 163:e59c8e839560 1153 */
AnnaBridge 163:e59c8e839560 1154
AnnaBridge 163:e59c8e839560 1155 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Deadtime Falling Lock
AnnaBridge 163:e59c8e839560 1156 * @{
AnnaBridge 163:e59c8e839560 1157 * @brief Constants defining whether or not the deadtime (falling sign and
AnnaBridge 163:e59c8e839560 1158 * value) is write protected
AnnaBridge 163:e59c8e839560 1159 */
AnnaBridge 163:e59c8e839560 1160 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Deadtime falling value and sign is writeable */
AnnaBridge 163:e59c8e839560 1161 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */
AnnaBridge 163:e59c8e839560 1162 /**
AnnaBridge 163:e59c8e839560 1163 * @}
AnnaBridge 163:e59c8e839560 1164 */
AnnaBridge 163:e59c8e839560 1165
AnnaBridge 163:e59c8e839560 1166 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Deadtime Falling Sign Lock
AnnaBridge 163:e59c8e839560 1167 * @{
AnnaBridge 163:e59c8e839560 1168 * @brief Constants defining whether or not the deadtime falling sign is write
AnnaBridge 163:e59c8e839560 1169 * protected
AnnaBridge 163:e59c8e839560 1170 */
AnnaBridge 163:e59c8e839560 1171 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime falling sign is writeable */
AnnaBridge 163:e59c8e839560 1172 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */
AnnaBridge 163:e59c8e839560 1173 /**
AnnaBridge 163:e59c8e839560 1174 * @}
AnnaBridge 163:e59c8e839560 1175 */
AnnaBridge 163:e59c8e839560 1176
AnnaBridge 163:e59c8e839560 1177 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
AnnaBridge 163:e59c8e839560 1178 * @{
AnnaBridge 163:e59c8e839560 1179 * @brief Constants defining the frequency of the generated high frequency carrier
AnnaBridge 163:e59c8e839560 1180 */
AnnaBridge 163:e59c8e839560 1181 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 (0x000000U) /*!< fCHPFRQ = fHRTIM / 16 */
AnnaBridge 163:e59c8e839560 1182 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
AnnaBridge 163:e59c8e839560 1183 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
AnnaBridge 163:e59c8e839560 1184 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
AnnaBridge 163:e59c8e839560 1185 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
AnnaBridge 163:e59c8e839560 1186 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
AnnaBridge 163:e59c8e839560 1187 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
AnnaBridge 163:e59c8e839560 1188 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
AnnaBridge 163:e59c8e839560 1189 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
AnnaBridge 163:e59c8e839560 1190 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
AnnaBridge 163:e59c8e839560 1191 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
AnnaBridge 163:e59c8e839560 1192 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
AnnaBridge 163:e59c8e839560 1193 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
AnnaBridge 163:e59c8e839560 1194 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
AnnaBridge 163:e59c8e839560 1195 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
AnnaBridge 163:e59c8e839560 1196 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
AnnaBridge 163:e59c8e839560 1197 /**
AnnaBridge 163:e59c8e839560 1198 * @}
AnnaBridge 163:e59c8e839560 1199 */
AnnaBridge 163:e59c8e839560 1200
AnnaBridge 163:e59c8e839560 1201 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
AnnaBridge 163:e59c8e839560 1202 * @{
AnnaBridge 163:e59c8e839560 1203 * @brief Constants defining the duty cycle of the generated high frequency carrier
AnnaBridge 163:e59c8e839560 1204 * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
AnnaBridge 163:e59c8e839560 1205 */
AnnaBridge 163:e59c8e839560 1206 #define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */
AnnaBridge 163:e59c8e839560 1207 #define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */
AnnaBridge 163:e59c8e839560 1208 #define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */
AnnaBridge 163:e59c8e839560 1209 #define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */
AnnaBridge 163:e59c8e839560 1210 #define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50U % */
AnnaBridge 163:e59c8e839560 1211 #define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5U % */
AnnaBridge 163:e59c8e839560 1212 #define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75U % */
AnnaBridge 163:e59c8e839560 1213 #define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */
AnnaBridge 163:e59c8e839560 1214 /**
AnnaBridge 163:e59c8e839560 1215 * @}
AnnaBridge 163:e59c8e839560 1216 */
AnnaBridge 163:e59c8e839560 1217
AnnaBridge 163:e59c8e839560 1218 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
AnnaBridge 163:e59c8e839560 1219 * @{
AnnaBridge 163:e59c8e839560 1220 * @brief Constants defining the pulse width of the first pulse of the generated
AnnaBridge 163:e59c8e839560 1221 * high frequency carrier
AnnaBridge 163:e59c8e839560 1222 */
AnnaBridge 163:e59c8e839560 1223 #define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */
AnnaBridge 163:e59c8e839560 1224 #define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
AnnaBridge 163:e59c8e839560 1225 #define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
AnnaBridge 163:e59c8e839560 1226 #define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
AnnaBridge 163:e59c8e839560 1227 #define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
AnnaBridge 163:e59c8e839560 1228 #define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
AnnaBridge 163:e59c8e839560 1229 #define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
AnnaBridge 163:e59c8e839560 1230 #define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
AnnaBridge 163:e59c8e839560 1231 #define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
AnnaBridge 163:e59c8e839560 1232 #define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
AnnaBridge 163:e59c8e839560 1233 #define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
AnnaBridge 163:e59c8e839560 1234 #define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
AnnaBridge 163:e59c8e839560 1235 #define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
AnnaBridge 163:e59c8e839560 1236 #define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
AnnaBridge 163:e59c8e839560 1237 #define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
AnnaBridge 163:e59c8e839560 1238 #define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
AnnaBridge 163:e59c8e839560 1239 /**
AnnaBridge 163:e59c8e839560 1240 * @}
AnnaBridge 163:e59c8e839560 1241 */
AnnaBridge 163:e59c8e839560 1242
AnnaBridge 163:e59c8e839560 1243 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
AnnaBridge 163:e59c8e839560 1244 * @{
AnnaBridge 163:e59c8e839560 1245 * @brief Constants defining the options for synchronizing multiple HRTIM
AnnaBridge 163:e59c8e839560 1246 * instances, as a master unit (generating a synchronization signal)
AnnaBridge 163:e59c8e839560 1247 * or as a slave (waiting for a trigger to be synchronized)
AnnaBridge 163:e59c8e839560 1248 */
AnnaBridge 163:e59c8e839560 1249 #define HRTIM_SYNCOPTION_NONE 0x00000000U /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
AnnaBridge 163:e59c8e839560 1250 #define HRTIM_SYNCOPTION_MASTER 0x00000001U /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
AnnaBridge 163:e59c8e839560 1251 #define HRTIM_SYNCOPTION_SLAVE 0x00000002U /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
AnnaBridge 163:e59c8e839560 1252 /**
AnnaBridge 163:e59c8e839560 1253 * @}
AnnaBridge 163:e59c8e839560 1254 */
AnnaBridge 163:e59c8e839560 1255
AnnaBridge 163:e59c8e839560 1256 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
AnnaBridge 163:e59c8e839560 1257 * @{
AnnaBridge 163:e59c8e839560 1258 * @brief Constants defining defining the synchronization input source
AnnaBridge 163:e59c8e839560 1259 */
AnnaBridge 163:e59c8e839560 1260 #define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
AnnaBridge 163:e59c8e839560 1261 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
AnnaBridge 163:e59c8e839560 1262 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
AnnaBridge 163:e59c8e839560 1263 /**
AnnaBridge 163:e59c8e839560 1264 * @}
AnnaBridge 163:e59c8e839560 1265 */
AnnaBridge 163:e59c8e839560 1266
AnnaBridge 163:e59c8e839560 1267 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
AnnaBridge 163:e59c8e839560 1268 * @{
AnnaBridge 163:e59c8e839560 1269 * @brief Constants defining the source and event to be sent on the
AnnaBridge 163:e59c8e839560 1270 * synchronization outputs
AnnaBridge 163:e59c8e839560 1271 */
AnnaBridge 163:e59c8e839560 1272 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
AnnaBridge 163:e59c8e839560 1273 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
AnnaBridge 163:e59c8e839560 1274 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
AnnaBridge 163:e59c8e839560 1275 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
AnnaBridge 163:e59c8e839560 1276 /**
AnnaBridge 163:e59c8e839560 1277 * @}
AnnaBridge 163:e59c8e839560 1278 */
AnnaBridge 163:e59c8e839560 1279
AnnaBridge 163:e59c8e839560 1280 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
AnnaBridge 163:e59c8e839560 1281 * @{
AnnaBridge 163:e59c8e839560 1282 * @brief Constants defining the routing and conditioning of the synchronization output event
AnnaBridge 163:e59c8e839560 1283 */
AnnaBridge 163:e59c8e839560 1284 #define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */
AnnaBridge 163:e59c8e839560 1285 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
AnnaBridge 163:e59c8e839560 1286 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
AnnaBridge 163:e59c8e839560 1287 /**
AnnaBridge 163:e59c8e839560 1288 * @}
AnnaBridge 163:e59c8e839560 1289 */
AnnaBridge 163:e59c8e839560 1290
AnnaBridge 163:e59c8e839560 1291 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
AnnaBridge 163:e59c8e839560 1292 * @{
AnnaBridge 163:e59c8e839560 1293 * @brief Constants defining available sources associated to external events
AnnaBridge 163:e59c8e839560 1294 */
AnnaBridge 163:e59c8e839560 1295 #define HRTIM_EVENTSRC_1 (0x00000000U) /*!< External event source 1U */
AnnaBridge 163:e59c8e839560 1296 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U */
AnnaBridge 163:e59c8e839560 1297 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U */
AnnaBridge 163:e59c8e839560 1298 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U */
AnnaBridge 163:e59c8e839560 1299 /**
AnnaBridge 163:e59c8e839560 1300 * @}
AnnaBridge 163:e59c8e839560 1301 */
AnnaBridge 163:e59c8e839560 1302
AnnaBridge 163:e59c8e839560 1303 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
AnnaBridge 163:e59c8e839560 1304 * @{
AnnaBridge 163:e59c8e839560 1305 * @brief Constants defining the polarity of an external event
AnnaBridge 163:e59c8e839560 1306 */
AnnaBridge 163:e59c8e839560 1307 #define HRTIM_EVENTPOLARITY_HIGH (0x00000000U) /*!< External event is active high */
AnnaBridge 163:e59c8e839560 1308 #define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
AnnaBridge 163:e59c8e839560 1309 /**
AnnaBridge 163:e59c8e839560 1310 * @}
AnnaBridge 163:e59c8e839560 1311 */
AnnaBridge 163:e59c8e839560 1312
AnnaBridge 163:e59c8e839560 1313 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
AnnaBridge 163:e59c8e839560 1314 * @{
AnnaBridge 163:e59c8e839560 1315 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
AnnaBridge 163:e59c8e839560 1316 * of an external event
AnnaBridge 163:e59c8e839560 1317 */
AnnaBridge 163:e59c8e839560 1318 #define HRTIM_EVENTSENSITIVITY_LEVEL (0x00000000U) /*!< External event is active on level */
AnnaBridge 163:e59c8e839560 1319 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
AnnaBridge 163:e59c8e839560 1320 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
AnnaBridge 163:e59c8e839560 1321 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
AnnaBridge 163:e59c8e839560 1322 /**
AnnaBridge 163:e59c8e839560 1323 * @}
AnnaBridge 163:e59c8e839560 1324 */
AnnaBridge 163:e59c8e839560 1325
AnnaBridge 163:e59c8e839560 1326 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
AnnaBridge 163:e59c8e839560 1327 * @{
AnnaBridge 163:e59c8e839560 1328 * @brief Constants defining whether or not an external event is programmed in
AnnaBridge 163:e59c8e839560 1329 fast mode
AnnaBridge 163:e59c8e839560 1330 */
AnnaBridge 168:b9e159c1930a 1331
AnnaBridge 168:b9e159c1930a 1332 #define HRTIM_EVENTFASTMODE_ENABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
AnnaBridge 168:b9e159c1930a 1333 #define HRTIM_EVENTFASTMODE_DISABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
AnnaBridge 163:e59c8e839560 1334 /**
AnnaBridge 163:e59c8e839560 1335 * @}
AnnaBridge 163:e59c8e839560 1336 */
AnnaBridge 163:e59c8e839560 1337
AnnaBridge 163:e59c8e839560 1338 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
AnnaBridge 163:e59c8e839560 1339 * @{
AnnaBridge 163:e59c8e839560 1340 * @brief Constants defining the frequency used to sample an external event 6
AnnaBridge 163:e59c8e839560 1341 * input and the length (N) of the digital filter applied
AnnaBridge 163:e59c8e839560 1342 */
AnnaBridge 163:e59c8e839560 1343 #define HRTIM_EVENTFILTER_NONE (0x00000000U) /*!< Filter disabled */
AnnaBridge 163:e59c8e839560 1344 #define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2U */
AnnaBridge 163:e59c8e839560 1345 #define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4U */
AnnaBridge 163:e59c8e839560 1346 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8U */
AnnaBridge 163:e59c8e839560 1347 #define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2U, N=6U */
AnnaBridge 163:e59c8e839560 1348 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2U, N=8U */
AnnaBridge 163:e59c8e839560 1349 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4U, N=6U */
AnnaBridge 163:e59c8e839560 1350 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4U, N=8U */
AnnaBridge 163:e59c8e839560 1351 #define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8U, N=6U */
AnnaBridge 163:e59c8e839560 1352 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8U, N=8U */
AnnaBridge 163:e59c8e839560 1353 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16U, N=5U */
AnnaBridge 163:e59c8e839560 1354 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16U, N=6U */
AnnaBridge 163:e59c8e839560 1355 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16U, N=8U */
AnnaBridge 163:e59c8e839560 1356 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=5U */
AnnaBridge 163:e59c8e839560 1357 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32U, N=6U */
AnnaBridge 163:e59c8e839560 1358 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=8U */
AnnaBridge 163:e59c8e839560 1359 /**
AnnaBridge 163:e59c8e839560 1360 * @}
AnnaBridge 163:e59c8e839560 1361 */
AnnaBridge 163:e59c8e839560 1362
AnnaBridge 163:e59c8e839560 1363 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
AnnaBridge 163:e59c8e839560 1364 * @{
AnnaBridge 163:e59c8e839560 1365 * @brief Constants defining division ratio between the timer clock frequency
AnnaBridge 163:e59c8e839560 1366 * fHRTIM) and the external event signal sampling clock (fEEVS)
AnnaBridge 163:e59c8e839560 1367 * used by the digital filters
AnnaBridge 163:e59c8e839560 1368 */
AnnaBridge 163:e59c8e839560 1369 #define HRTIM_EVENTPRESCALER_DIV1 (0x00000000U) /*!< fEEVS=fHRTIM */
AnnaBridge 163:e59c8e839560 1370 #define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2U */
AnnaBridge 163:e59c8e839560 1371 #define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4U */
AnnaBridge 163:e59c8e839560 1372 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8U */
AnnaBridge 163:e59c8e839560 1373 /**
AnnaBridge 163:e59c8e839560 1374 * @}
AnnaBridge 163:e59c8e839560 1375 */
AnnaBridge 163:e59c8e839560 1376
AnnaBridge 163:e59c8e839560 1377 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
AnnaBridge 163:e59c8e839560 1378 * @{
AnnaBridge 163:e59c8e839560 1379 * @brief Constants defining whether a faults is be triggered by any external
AnnaBridge 163:e59c8e839560 1380 * or internal fault source
AnnaBridge 163:e59c8e839560 1381 */
AnnaBridge 163:e59c8e839560 1382 #define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */
AnnaBridge 163:e59c8e839560 1383 #define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
AnnaBridge 163:e59c8e839560 1384 /**
AnnaBridge 163:e59c8e839560 1385 * @}
AnnaBridge 163:e59c8e839560 1386 */
AnnaBridge 163:e59c8e839560 1387
AnnaBridge 163:e59c8e839560 1388 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
AnnaBridge 163:e59c8e839560 1389 * @{
AnnaBridge 163:e59c8e839560 1390 * @brief Constants defining the polarity of a fault event
AnnaBridge 163:e59c8e839560 1391 */
AnnaBridge 163:e59c8e839560 1392 #define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */
AnnaBridge 163:e59c8e839560 1393 #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
AnnaBridge 163:e59c8e839560 1394 /**
AnnaBridge 163:e59c8e839560 1395 * @}
AnnaBridge 163:e59c8e839560 1396 */
AnnaBridge 163:e59c8e839560 1397
AnnaBridge 163:e59c8e839560 1398 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
AnnaBridge 163:e59c8e839560 1399 * @{
AnnaBridge 163:e59c8e839560 1400 * @ brief Constants defining the frequency used to sample the fault input and
AnnaBridge 163:e59c8e839560 1401 * the length (N) of the digital filter applied
AnnaBridge 163:e59c8e839560 1402 */
AnnaBridge 163:e59c8e839560 1403 #define HRTIM_FAULTFILTER_NONE (0x00000000U) /*!< Filter disabled */
AnnaBridge 163:e59c8e839560 1404 #define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2U */
AnnaBridge 163:e59c8e839560 1405 #define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4U */
AnnaBridge 163:e59c8e839560 1406 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8U */
AnnaBridge 163:e59c8e839560 1407 #define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2U, N=6U */
AnnaBridge 163:e59c8e839560 1408 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2U, N=8U */
AnnaBridge 163:e59c8e839560 1409 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4U, N=6U */
AnnaBridge 163:e59c8e839560 1410 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4U, N=8U */
AnnaBridge 163:e59c8e839560 1411 #define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8U, N=6U */
AnnaBridge 163:e59c8e839560 1412 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8U, N=8U */
AnnaBridge 163:e59c8e839560 1413 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16U, N=5U */
AnnaBridge 163:e59c8e839560 1414 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16U, N=6U */
AnnaBridge 163:e59c8e839560 1415 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16U, N=8U */
AnnaBridge 163:e59c8e839560 1416 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=5U */
AnnaBridge 163:e59c8e839560 1417 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32U, N=6U */
AnnaBridge 163:e59c8e839560 1418 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=8U */
AnnaBridge 163:e59c8e839560 1419 /**
AnnaBridge 163:e59c8e839560 1420 * @}
AnnaBridge 163:e59c8e839560 1421 */
AnnaBridge 163:e59c8e839560 1422
AnnaBridge 163:e59c8e839560 1423 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
AnnaBridge 163:e59c8e839560 1424 * @{
AnnaBridge 163:e59c8e839560 1425 * @brief Constants defining whether or not the fault programming bits are
AnnaBridge 163:e59c8e839560 1426 write protected
AnnaBridge 163:e59c8e839560 1427 */
AnnaBridge 163:e59c8e839560 1428 #define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */
AnnaBridge 163:e59c8e839560 1429 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
AnnaBridge 163:e59c8e839560 1430 /**
AnnaBridge 163:e59c8e839560 1431 * @}
AnnaBridge 163:e59c8e839560 1432 */
AnnaBridge 163:e59c8e839560 1433
AnnaBridge 163:e59c8e839560 1434 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
AnnaBridge 163:e59c8e839560 1435 * @{
AnnaBridge 163:e59c8e839560 1436 * @brief Constants defining the division ratio between the timer clock
AnnaBridge 163:e59c8e839560 1437 * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
AnnaBridge 163:e59c8e839560 1438 * by the digital filters.
AnnaBridge 163:e59c8e839560 1439 */
AnnaBridge 163:e59c8e839560 1440 #define HRTIM_FAULTPRESCALER_DIV1 (0x00000000U) /*!< fFLTS=fHRTIM */
AnnaBridge 163:e59c8e839560 1441 #define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2U */
AnnaBridge 163:e59c8e839560 1442 #define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4U */
AnnaBridge 163:e59c8e839560 1443 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8U */
AnnaBridge 163:e59c8e839560 1444 /**
AnnaBridge 163:e59c8e839560 1445 * @}
AnnaBridge 163:e59c8e839560 1446 */
AnnaBridge 163:e59c8e839560 1447
AnnaBridge 163:e59c8e839560 1448 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
AnnaBridge 163:e59c8e839560 1449 * @{
AnnaBridge 163:e59c8e839560 1450 * @brief Constants defining if the burst mode is entered once or if it is
AnnaBridge 163:e59c8e839560 1451 * continuously operating
AnnaBridge 163:e59c8e839560 1452 */
AnnaBridge 163:e59c8e839560 1453 #define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */
AnnaBridge 163:e59c8e839560 1454 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
AnnaBridge 163:e59c8e839560 1455 /**
AnnaBridge 163:e59c8e839560 1456 * @}
AnnaBridge 163:e59c8e839560 1457 */
AnnaBridge 163:e59c8e839560 1458
AnnaBridge 163:e59c8e839560 1459 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
AnnaBridge 163:e59c8e839560 1460 * @{
AnnaBridge 163:e59c8e839560 1461 * @brief Constants defining the clock source for the burst mode counter
AnnaBridge 163:e59c8e839560 1462 */
AnnaBridge 163:e59c8e839560 1463 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
AnnaBridge 163:e59c8e839560 1464 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
AnnaBridge 163:e59c8e839560 1465 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
AnnaBridge 163:e59c8e839560 1466 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
AnnaBridge 163:e59c8e839560 1467 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
AnnaBridge 163:e59c8e839560 1468 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
AnnaBridge 163:e59c8e839560 1469 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
AnnaBridge 163:e59c8e839560 1470 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
AnnaBridge 163:e59c8e839560 1471 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
AnnaBridge 163:e59c8e839560 1472 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
AnnaBridge 163:e59c8e839560 1473 /**
AnnaBridge 163:e59c8e839560 1474 * @}
AnnaBridge 163:e59c8e839560 1475 */
AnnaBridge 163:e59c8e839560 1476
AnnaBridge 163:e59c8e839560 1477 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
AnnaBridge 163:e59c8e839560 1478 * @{
AnnaBridge 163:e59c8e839560 1479 * @brief Constants defining the prescaling ratio of the fHRTIM clock
AnnaBridge 163:e59c8e839560 1480 * for the burst mode controller
AnnaBridge 163:e59c8e839560 1481 */
AnnaBridge 163:e59c8e839560 1482 #define HRTIM_BURSTMODEPRESCALER_DIV1 (0x00000000U) /*!< fBRST = fHRTIM */
AnnaBridge 163:e59c8e839560 1483 #define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2U */
AnnaBridge 163:e59c8e839560 1484 #define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4U */
AnnaBridge 163:e59c8e839560 1485 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8U */
AnnaBridge 163:e59c8e839560 1486 #define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16U */
AnnaBridge 163:e59c8e839560 1487 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32U */
AnnaBridge 163:e59c8e839560 1488 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64U */
AnnaBridge 163:e59c8e839560 1489 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128U */
AnnaBridge 163:e59c8e839560 1490 #define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256U */
AnnaBridge 163:e59c8e839560 1491 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512U */
AnnaBridge 163:e59c8e839560 1492 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024U */
AnnaBridge 163:e59c8e839560 1493 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048U*/
AnnaBridge 163:e59c8e839560 1494 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096U */
AnnaBridge 163:e59c8e839560 1495 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192U */
AnnaBridge 163:e59c8e839560 1496 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384U */
AnnaBridge 163:e59c8e839560 1497 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */
AnnaBridge 163:e59c8e839560 1498 /**
AnnaBridge 163:e59c8e839560 1499 * @}
AnnaBridge 163:e59c8e839560 1500 */
AnnaBridge 163:e59c8e839560 1501
AnnaBridge 163:e59c8e839560 1502 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
AnnaBridge 163:e59c8e839560 1503 * @{
AnnaBridge 163:e59c8e839560 1504 * @brief Constants defining whether or not burst mode registers preload
AnnaBridge 163:e59c8e839560 1505 mechanism is enabled, i.e. a write access into a preloadable register
AnnaBridge 163:e59c8e839560 1506 (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
AnnaBridge 163:e59c8e839560 1507 */
AnnaBridge 163:e59c8e839560 1508 #define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into active registers */
AnnaBridge 163:e59c8e839560 1509 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
AnnaBridge 163:e59c8e839560 1510 /**
AnnaBridge 163:e59c8e839560 1511 * @}
AnnaBridge 163:e59c8e839560 1512 */
AnnaBridge 163:e59c8e839560 1513
AnnaBridge 163:e59c8e839560 1514 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
AnnaBridge 163:e59c8e839560 1515 * @{
AnnaBridge 163:e59c8e839560 1516 * @brief Constants defining the events that can be used tor trig the burst
AnnaBridge 163:e59c8e839560 1517 * mode operation
AnnaBridge 163:e59c8e839560 1518 */
AnnaBridge 163:e59c8e839560 1519 #define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */
AnnaBridge 163:e59c8e839560 1520 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */
AnnaBridge 163:e59c8e839560 1521 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
AnnaBridge 163:e59c8e839560 1522 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1U */
AnnaBridge 163:e59c8e839560 1523 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2U */
AnnaBridge 163:e59c8e839560 1524 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3U */
AnnaBridge 163:e59c8e839560 1525 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4U */
AnnaBridge 163:e59c8e839560 1526 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */
AnnaBridge 163:e59c8e839560 1527 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
AnnaBridge 163:e59c8e839560 1528 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */
AnnaBridge 163:e59c8e839560 1529 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */
AnnaBridge 163:e59c8e839560 1530 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */
AnnaBridge 163:e59c8e839560 1531 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */
AnnaBridge 163:e59c8e839560 1532 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */
AnnaBridge 163:e59c8e839560 1533 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */
AnnaBridge 163:e59c8e839560 1534 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */
AnnaBridge 163:e59c8e839560 1535 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */
AnnaBridge 163:e59c8e839560 1536 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */
AnnaBridge 163:e59c8e839560 1537 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */
AnnaBridge 163:e59c8e839560 1538 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */
AnnaBridge 163:e59c8e839560 1539 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */
AnnaBridge 163:e59c8e839560 1540 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */
AnnaBridge 163:e59c8e839560 1541 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */
AnnaBridge 163:e59c8e839560 1542 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */
AnnaBridge 163:e59c8e839560 1543 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */
AnnaBridge 163:e59c8e839560 1544 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */
AnnaBridge 163:e59c8e839560 1545 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */
AnnaBridge 163:e59c8e839560 1546 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */
AnnaBridge 163:e59c8e839560 1547 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */
AnnaBridge 163:e59c8e839560 1548 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */
AnnaBridge 163:e59c8e839560 1549 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/
AnnaBridge 163:e59c8e839560 1550 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */
AnnaBridge 163:e59c8e839560 1551 /**
AnnaBridge 163:e59c8e839560 1552 * @}
AnnaBridge 163:e59c8e839560 1553 */
AnnaBridge 163:e59c8e839560 1554
AnnaBridge 163:e59c8e839560 1555 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
AnnaBridge 163:e59c8e839560 1556 * @{
AnnaBridge 163:e59c8e839560 1557 * @brief constants defining the source triggering the update of the
AnnaBridge 163:e59c8e839560 1558 HRTIM_ADCxR register (transfer from preload to active register).
AnnaBridge 163:e59c8e839560 1559 */
AnnaBridge 163:e59c8e839560 1560 #define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */
AnnaBridge 163:e59c8e839560 1561 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */
AnnaBridge 163:e59c8e839560 1562 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */
AnnaBridge 163:e59c8e839560 1563 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
AnnaBridge 163:e59c8e839560 1564 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */
AnnaBridge 163:e59c8e839560 1565 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
AnnaBridge 163:e59c8e839560 1566 /**
AnnaBridge 163:e59c8e839560 1567 * @}
AnnaBridge 163:e59c8e839560 1568 */
AnnaBridge 163:e59c8e839560 1569
AnnaBridge 163:e59c8e839560 1570 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
AnnaBridge 163:e59c8e839560 1571 * @{
AnnaBridge 163:e59c8e839560 1572 * @brief constants defining the events triggering ADC conversion.
AnnaBridge 163:e59c8e839560 1573 * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
AnnaBridge 163:e59c8e839560 1574 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
AnnaBridge 163:e59c8e839560 1575 */
AnnaBridge 163:e59c8e839560 1576 #define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */
AnnaBridge 163:e59c8e839560 1577 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */
AnnaBridge 163:e59c8e839560 1578 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */
AnnaBridge 163:e59c8e839560 1579 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */
AnnaBridge 163:e59c8e839560 1580 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4U */
AnnaBridge 163:e59c8e839560 1581 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
AnnaBridge 163:e59c8e839560 1582 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1U */
AnnaBridge 163:e59c8e839560 1583 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2U */
AnnaBridge 163:e59c8e839560 1584 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3U */
AnnaBridge 163:e59c8e839560 1585 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4U */
AnnaBridge 163:e59c8e839560 1586 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5U */
AnnaBridge 163:e59c8e839560 1587 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2U */
AnnaBridge 163:e59c8e839560 1588 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3U */
AnnaBridge 163:e59c8e839560 1589 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4U */
AnnaBridge 163:e59c8e839560 1590 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
AnnaBridge 163:e59c8e839560 1591 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
AnnaBridge 163:e59c8e839560 1592 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2U */
AnnaBridge 163:e59c8e839560 1593 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3U */
AnnaBridge 163:e59c8e839560 1594 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4U */
AnnaBridge 163:e59c8e839560 1595 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
AnnaBridge 163:e59c8e839560 1596 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
AnnaBridge 163:e59c8e839560 1597 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2U */
AnnaBridge 163:e59c8e839560 1598 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3U */
AnnaBridge 163:e59c8e839560 1599 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4U */
AnnaBridge 163:e59c8e839560 1600 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
AnnaBridge 163:e59c8e839560 1601 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2U */
AnnaBridge 163:e59c8e839560 1602 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3U */
AnnaBridge 163:e59c8e839560 1603 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4U */
AnnaBridge 163:e59c8e839560 1604 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
AnnaBridge 163:e59c8e839560 1605 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2U */
AnnaBridge 163:e59c8e839560 1606 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3U */
AnnaBridge 163:e59c8e839560 1607 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4U */
AnnaBridge 163:e59c8e839560 1608 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
AnnaBridge 163:e59c8e839560 1609
AnnaBridge 163:e59c8e839560 1610 #define HRTIM_ADCTRIGGEREVENT24_NONE 0x00000000U /*!< No ADC trigger event */
AnnaBridge 163:e59c8e839560 1611 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1U */
AnnaBridge 163:e59c8e839560 1612 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2U */
AnnaBridge 163:e59c8e839560 1613 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3U */
AnnaBridge 163:e59c8e839560 1614 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4U */
AnnaBridge 163:e59c8e839560 1615 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
AnnaBridge 163:e59c8e839560 1616 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6U */
AnnaBridge 163:e59c8e839560 1617 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7U */
AnnaBridge 163:e59c8e839560 1618 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8U */
AnnaBridge 163:e59c8e839560 1619 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9U */
AnnaBridge 163:e59c8e839560 1620 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10U */
AnnaBridge 163:e59c8e839560 1621 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2U */
AnnaBridge 163:e59c8e839560 1622 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3U */
AnnaBridge 163:e59c8e839560 1623 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4U */
AnnaBridge 163:e59c8e839560 1624 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
AnnaBridge 163:e59c8e839560 1625 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2U */
AnnaBridge 163:e59c8e839560 1626 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3U */
AnnaBridge 163:e59c8e839560 1627 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4U */
AnnaBridge 163:e59c8e839560 1628 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
AnnaBridge 163:e59c8e839560 1629 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2U */
AnnaBridge 163:e59c8e839560 1630 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3U */
AnnaBridge 163:e59c8e839560 1631 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4U */
AnnaBridge 163:e59c8e839560 1632 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
AnnaBridge 163:e59c8e839560 1633 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
AnnaBridge 163:e59c8e839560 1634 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2U */
AnnaBridge 163:e59c8e839560 1635 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3U */
AnnaBridge 163:e59c8e839560 1636 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4U */
AnnaBridge 163:e59c8e839560 1637 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
AnnaBridge 163:e59c8e839560 1638 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
AnnaBridge 163:e59c8e839560 1639 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2U */
AnnaBridge 163:e59c8e839560 1640 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */
AnnaBridge 163:e59c8e839560 1641 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */
AnnaBridge 163:e59c8e839560 1642 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
AnnaBridge 163:e59c8e839560 1643
AnnaBridge 163:e59c8e839560 1644 /**
AnnaBridge 163:e59c8e839560 1645 * @}
AnnaBridge 163:e59c8e839560 1646 */
AnnaBridge 163:e59c8e839560 1647
AnnaBridge 163:e59c8e839560 1648 /** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
AnnaBridge 163:e59c8e839560 1649 * @{
AnnaBridge 163:e59c8e839560 1650 * @brief Constants defining the DLL calibration periods (in micro seconds)
AnnaBridge 163:e59c8e839560 1651 */
AnnaBridge 163:e59c8e839560 1652 #define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */
AnnaBridge 163:e59c8e839560 1653 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (7.3 ms) */
AnnaBridge 163:e59c8e839560 1654 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (910 ms) */
AnnaBridge 163:e59c8e839560 1655 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (114 ms) */
AnnaBridge 163:e59c8e839560 1656 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (14 ms) */
AnnaBridge 163:e59c8e839560 1657 /**
AnnaBridge 163:e59c8e839560 1658 * @}
AnnaBridge 163:e59c8e839560 1659 */
AnnaBridge 163:e59c8e839560 1660
AnnaBridge 163:e59c8e839560 1661 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
AnnaBridge 163:e59c8e839560 1662 * @{
AnnaBridge 163:e59c8e839560 1663 * @brief Constants defining the registers that can be written during a burst
AnnaBridge 163:e59c8e839560 1664 * DMA operation
AnnaBridge 163:e59c8e839560 1665 */
AnnaBridge 163:e59c8e839560 1666 #define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1667 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1668 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1669 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1670 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1671 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1672 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1673 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1674 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1675 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1676 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1677 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1678 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1679 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1680 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1681 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1682 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1683 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1684 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1685 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1686 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1687 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
AnnaBridge 163:e59c8e839560 1688 /**
AnnaBridge 163:e59c8e839560 1689 * @}
AnnaBridge 163:e59c8e839560 1690 */
AnnaBridge 163:e59c8e839560 1691
AnnaBridge 163:e59c8e839560 1692 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
AnnaBridge 163:e59c8e839560 1693 * @{
AnnaBridge 163:e59c8e839560 1694 * @brief Constants used to enable or disable the burst mode controller
AnnaBridge 163:e59c8e839560 1695 */
AnnaBridge 163:e59c8e839560 1696 #define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */
AnnaBridge 163:e59c8e839560 1697 #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */
AnnaBridge 163:e59c8e839560 1698 /**
AnnaBridge 163:e59c8e839560 1699 * @}
AnnaBridge 163:e59c8e839560 1700 */
AnnaBridge 163:e59c8e839560 1701
AnnaBridge 163:e59c8e839560 1702 /** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control
AnnaBridge 163:e59c8e839560 1703 * @{
AnnaBridge 163:e59c8e839560 1704 * @brief Constants used to enable or disable a fault channel
AnnaBridge 163:e59c8e839560 1705 */
AnnaBridge 163:e59c8e839560 1706 #define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */
AnnaBridge 163:e59c8e839560 1707 #define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /*!< Fault channel is enabled */
AnnaBridge 163:e59c8e839560 1708
AnnaBridge 163:e59c8e839560 1709 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
AnnaBridge 163:e59c8e839560 1710 (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \
AnnaBridge 163:e59c8e839560 1711 ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
AnnaBridge 163:e59c8e839560 1712 /**
AnnaBridge 163:e59c8e839560 1713 * @}
AnnaBridge 163:e59c8e839560 1714 */
AnnaBridge 163:e59c8e839560 1715
AnnaBridge 163:e59c8e839560 1716 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
AnnaBridge 163:e59c8e839560 1717 * @{
AnnaBridge 163:e59c8e839560 1718 * @brief Constants used to force timer registers update
AnnaBridge 163:e59c8e839560 1719 */
AnnaBridge 163:e59c8e839560 1720 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Forces an immediate transfer from the preload to the active register in the master timer */
AnnaBridge 163:e59c8e839560 1721 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Forces an immediate transfer from the preload to the active register in the timer A */
AnnaBridge 163:e59c8e839560 1722 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer B */
AnnaBridge 163:e59c8e839560 1723 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer C */
AnnaBridge 163:e59c8e839560 1724 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer D */
AnnaBridge 163:e59c8e839560 1725 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Forces an immediate transfer from the preload to the active register in the timer E */
AnnaBridge 163:e59c8e839560 1726 /**
AnnaBridge 163:e59c8e839560 1727 * @}
AnnaBridge 163:e59c8e839560 1728 */
AnnaBridge 163:e59c8e839560 1729
AnnaBridge 163:e59c8e839560 1730 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
AnnaBridge 163:e59c8e839560 1731 * @{
AnnaBridge 163:e59c8e839560 1732 * @brief Constants used to force timer counter reset
AnnaBridge 163:e59c8e839560 1733 */
AnnaBridge 163:e59c8e839560 1734 #define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Resets the master timer counter */
AnnaBridge 163:e59c8e839560 1735 #define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Resets the timer A counter */
AnnaBridge 163:e59c8e839560 1736 #define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Resets the timer B counter */
AnnaBridge 163:e59c8e839560 1737 #define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Resets the timer C counter */
AnnaBridge 163:e59c8e839560 1738 #define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Resets the timer D counter */
AnnaBridge 163:e59c8e839560 1739 #define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Resets the timer E counter */
AnnaBridge 163:e59c8e839560 1740 /**
AnnaBridge 163:e59c8e839560 1741 * @}
AnnaBridge 163:e59c8e839560 1742 */
AnnaBridge 163:e59c8e839560 1743
AnnaBridge 163:e59c8e839560 1744 /** @defgroup HRTIM_Output_Level HRTIM Output Level
AnnaBridge 163:e59c8e839560 1745 * @{
AnnaBridge 163:e59c8e839560 1746 * @brief Constants defining the level of a timer output
AnnaBridge 163:e59c8e839560 1747 */
AnnaBridge 163:e59c8e839560 1748 #define HRTIM_OUTPUTLEVEL_ACTIVE (0x00000001U) /*!< Forces the output to its active state */
AnnaBridge 163:e59c8e839560 1749 #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Forces the output to its inactive state */
AnnaBridge 163:e59c8e839560 1750
AnnaBridge 163:e59c8e839560 1751 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
AnnaBridge 163:e59c8e839560 1752 (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
AnnaBridge 163:e59c8e839560 1753 ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
AnnaBridge 163:e59c8e839560 1754 /**
AnnaBridge 163:e59c8e839560 1755 * @}
AnnaBridge 163:e59c8e839560 1756 */
AnnaBridge 163:e59c8e839560 1757
AnnaBridge 163:e59c8e839560 1758 /** @defgroup HRTIM_Output_State HRTIM Output State
AnnaBridge 163:e59c8e839560 1759 * @{
AnnaBridge 163:e59c8e839560 1760 * @brief Constants defining the state of a timer output
AnnaBridge 163:e59c8e839560 1761 */
AnnaBridge 163:e59c8e839560 1762 #define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or
AnnaBridge 163:e59c8e839560 1763 inactive level as programmed in the crossbar unit */
AnnaBridge 163:e59c8e839560 1764 #define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the
AnnaBridge 163:e59c8e839560 1765 outputs are disabled by software or during a burst mode operation */
AnnaBridge 163:e59c8e839560 1766 #define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on
AnnaBridge 163:e59c8e839560 1767 FAULTx inputs */
AnnaBridge 163:e59c8e839560 1768 /**
AnnaBridge 163:e59c8e839560 1769 * @}
AnnaBridge 163:e59c8e839560 1770 */
AnnaBridge 163:e59c8e839560 1771
AnnaBridge 163:e59c8e839560 1772 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
AnnaBridge 163:e59c8e839560 1773 * @{
AnnaBridge 163:e59c8e839560 1774 * @brief Constants defining the operating state of the burst mode controller
AnnaBridge 163:e59c8e839560 1775 */
AnnaBridge 163:e59c8e839560 1776 #define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */
AnnaBridge 163:e59c8e839560 1777 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
AnnaBridge 163:e59c8e839560 1778 /**
AnnaBridge 163:e59c8e839560 1779 * @}
AnnaBridge 163:e59c8e839560 1780 */
AnnaBridge 163:e59c8e839560 1781
AnnaBridge 163:e59c8e839560 1782 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
AnnaBridge 163:e59c8e839560 1783 * @{
AnnaBridge 163:e59c8e839560 1784 * @brief Constants defining on which output the signal is currently applied
AnnaBridge 163:e59c8e839560 1785 * in push-pull mode
AnnaBridge 163:e59c8e839560 1786 */
AnnaBridge 163:e59c8e839560 1787 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */
AnnaBridge 163:e59c8e839560 1788 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
AnnaBridge 163:e59c8e839560 1789 /**
AnnaBridge 163:e59c8e839560 1790 * @}
AnnaBridge 163:e59c8e839560 1791 */
AnnaBridge 163:e59c8e839560 1792
AnnaBridge 163:e59c8e839560 1793 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
AnnaBridge 163:e59c8e839560 1794 * @{
AnnaBridge 163:e59c8e839560 1795 * @brief Constants defining on which output the signal was applied, in
AnnaBridge 163:e59c8e839560 1796 * push-pull mode balanced fault mode or delayed idle mode, when the
AnnaBridge 163:e59c8e839560 1797 * protection was triggered
AnnaBridge 163:e59c8e839560 1798 */
AnnaBridge 163:e59c8e839560 1799 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
AnnaBridge 163:e59c8e839560 1800 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
AnnaBridge 163:e59c8e839560 1801 /**
AnnaBridge 163:e59c8e839560 1802 * @}
AnnaBridge 163:e59c8e839560 1803 */
AnnaBridge 163:e59c8e839560 1804
AnnaBridge 163:e59c8e839560 1805 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
AnnaBridge 163:e59c8e839560 1806 * @{
AnnaBridge 163:e59c8e839560 1807 */
AnnaBridge 163:e59c8e839560 1808 #define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */
AnnaBridge 163:e59c8e839560 1809 #define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */
AnnaBridge 163:e59c8e839560 1810 #define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */
AnnaBridge 163:e59c8e839560 1811 #define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */
AnnaBridge 163:e59c8e839560 1812 #define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */
AnnaBridge 163:e59c8e839560 1813 #define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */
AnnaBridge 163:e59c8e839560 1814 #define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */
AnnaBridge 163:e59c8e839560 1815 #define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /*!< DLL ready interrupt enable */
AnnaBridge 163:e59c8e839560 1816 #define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */
AnnaBridge 163:e59c8e839560 1817 /**
AnnaBridge 163:e59c8e839560 1818 * @}
AnnaBridge 163:e59c8e839560 1819 */
AnnaBridge 163:e59c8e839560 1820
AnnaBridge 163:e59c8e839560 1821 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
AnnaBridge 163:e59c8e839560 1822 * @{
AnnaBridge 163:e59c8e839560 1823 */
AnnaBridge 163:e59c8e839560 1824 #define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */
AnnaBridge 163:e59c8e839560 1825 #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */
AnnaBridge 163:e59c8e839560 1826 #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */
AnnaBridge 163:e59c8e839560 1827 #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */
AnnaBridge 163:e59c8e839560 1828 #define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */
AnnaBridge 163:e59c8e839560 1829 #define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */
AnnaBridge 163:e59c8e839560 1830 #define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */
AnnaBridge 163:e59c8e839560 1831 #define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */
AnnaBridge 163:e59c8e839560 1832 /**
AnnaBridge 163:e59c8e839560 1833 * @}
AnnaBridge 163:e59c8e839560 1834 */
AnnaBridge 163:e59c8e839560 1835
AnnaBridge 163:e59c8e839560 1836 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
AnnaBridge 163:e59c8e839560 1837 * @{
AnnaBridge 163:e59c8e839560 1838 */
AnnaBridge 163:e59c8e839560 1839 #define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */
AnnaBridge 163:e59c8e839560 1840 #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */
AnnaBridge 163:e59c8e839560 1841 #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */
AnnaBridge 163:e59c8e839560 1842 #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */
AnnaBridge 163:e59c8e839560 1843 #define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */
AnnaBridge 163:e59c8e839560 1844 #define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */
AnnaBridge 163:e59c8e839560 1845 #define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */
AnnaBridge 163:e59c8e839560 1846 #define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */
AnnaBridge 163:e59c8e839560 1847 #define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */
AnnaBridge 163:e59c8e839560 1848 #define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */
AnnaBridge 163:e59c8e839560 1849 #define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */
AnnaBridge 163:e59c8e839560 1850 #define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */
AnnaBridge 163:e59c8e839560 1851 #define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */
AnnaBridge 163:e59c8e839560 1852 #define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */
AnnaBridge 163:e59c8e839560 1853 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */
AnnaBridge 163:e59c8e839560 1854 /**
AnnaBridge 163:e59c8e839560 1855 * @}
AnnaBridge 163:e59c8e839560 1856 */
AnnaBridge 163:e59c8e839560 1857
AnnaBridge 163:e59c8e839560 1858 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
AnnaBridge 163:e59c8e839560 1859 * @{
AnnaBridge 163:e59c8e839560 1860 */
AnnaBridge 163:e59c8e839560 1861 #define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */
AnnaBridge 163:e59c8e839560 1862 #define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */
AnnaBridge 163:e59c8e839560 1863 #define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */
AnnaBridge 163:e59c8e839560 1864 #define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */
AnnaBridge 163:e59c8e839560 1865 #define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */
AnnaBridge 163:e59c8e839560 1866 #define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */
AnnaBridge 163:e59c8e839560 1867 #define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */
AnnaBridge 163:e59c8e839560 1868 #define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */
AnnaBridge 163:e59c8e839560 1869 /**
AnnaBridge 163:e59c8e839560 1870 * @}
AnnaBridge 163:e59c8e839560 1871 */
AnnaBridge 163:e59c8e839560 1872
AnnaBridge 163:e59c8e839560 1873 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
AnnaBridge 163:e59c8e839560 1874 * @{
AnnaBridge 163:e59c8e839560 1875 */
AnnaBridge 163:e59c8e839560 1876 #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */
AnnaBridge 163:e59c8e839560 1877 #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */
AnnaBridge 163:e59c8e839560 1878 #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */
AnnaBridge 163:e59c8e839560 1879 #define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */
AnnaBridge 163:e59c8e839560 1880 #define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */
AnnaBridge 163:e59c8e839560 1881 #define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */
AnnaBridge 163:e59c8e839560 1882 #define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */
AnnaBridge 163:e59c8e839560 1883 /**
AnnaBridge 163:e59c8e839560 1884 * @}
AnnaBridge 163:e59c8e839560 1885 */
AnnaBridge 163:e59c8e839560 1886
AnnaBridge 163:e59c8e839560 1887 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
AnnaBridge 163:e59c8e839560 1888 * @{
AnnaBridge 163:e59c8e839560 1889 */
AnnaBridge 163:e59c8e839560 1890 #define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */
AnnaBridge 163:e59c8e839560 1891 #define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */
AnnaBridge 163:e59c8e839560 1892 #define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */
AnnaBridge 163:e59c8e839560 1893 #define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */
AnnaBridge 163:e59c8e839560 1894 #define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */
AnnaBridge 163:e59c8e839560 1895 #define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */
AnnaBridge 163:e59c8e839560 1896 #define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */
AnnaBridge 163:e59c8e839560 1897 #define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */
AnnaBridge 163:e59c8e839560 1898 #define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */
AnnaBridge 163:e59c8e839560 1899 #define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */
AnnaBridge 163:e59c8e839560 1900 #define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */
AnnaBridge 163:e59c8e839560 1901 #define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */
AnnaBridge 163:e59c8e839560 1902 #define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */
AnnaBridge 163:e59c8e839560 1903 #define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */
AnnaBridge 163:e59c8e839560 1904 /**
AnnaBridge 163:e59c8e839560 1905 * @}
AnnaBridge 163:e59c8e839560 1906 */
AnnaBridge 163:e59c8e839560 1907
AnnaBridge 163:e59c8e839560 1908 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
AnnaBridge 163:e59c8e839560 1909 * @{
AnnaBridge 163:e59c8e839560 1910 */
AnnaBridge 163:e59c8e839560 1911 #define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */
AnnaBridge 163:e59c8e839560 1912 #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */
AnnaBridge 163:e59c8e839560 1913 #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */
AnnaBridge 163:e59c8e839560 1914 #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */
AnnaBridge 163:e59c8e839560 1915 #define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */
AnnaBridge 163:e59c8e839560 1916 #define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */
AnnaBridge 163:e59c8e839560 1917 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */
AnnaBridge 163:e59c8e839560 1918 #define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */
AnnaBridge 163:e59c8e839560 1919 /**
AnnaBridge 163:e59c8e839560 1920 * @}
AnnaBridge 163:e59c8e839560 1921 */
AnnaBridge 163:e59c8e839560 1922
AnnaBridge 163:e59c8e839560 1923 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
AnnaBridge 163:e59c8e839560 1924 * @{
AnnaBridge 163:e59c8e839560 1925 */
AnnaBridge 163:e59c8e839560 1926 #define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */
AnnaBridge 163:e59c8e839560 1927 #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */
AnnaBridge 163:e59c8e839560 1928 #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */
AnnaBridge 163:e59c8e839560 1929 #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */
AnnaBridge 163:e59c8e839560 1930 #define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */
AnnaBridge 163:e59c8e839560 1931 #define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */
AnnaBridge 163:e59c8e839560 1932 #define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */
AnnaBridge 163:e59c8e839560 1933 #define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */
AnnaBridge 163:e59c8e839560 1934 #define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */
AnnaBridge 163:e59c8e839560 1935 #define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */
AnnaBridge 163:e59c8e839560 1936 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */
AnnaBridge 163:e59c8e839560 1937 #define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */
AnnaBridge 163:e59c8e839560 1938 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */
AnnaBridge 163:e59c8e839560 1939 #define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */
AnnaBridge 163:e59c8e839560 1940 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */
AnnaBridge 163:e59c8e839560 1941 /**
AnnaBridge 163:e59c8e839560 1942 * @}
AnnaBridge 163:e59c8e839560 1943 */
AnnaBridge 163:e59c8e839560 1944
AnnaBridge 163:e59c8e839560 1945 /**
AnnaBridge 163:e59c8e839560 1946 * @}
AnnaBridge 163:e59c8e839560 1947 */
AnnaBridge 163:e59c8e839560 1948
AnnaBridge 163:e59c8e839560 1949 /* Private macros --------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 1950 /** @addtogroup HRTIM_Private_Macros HRTIM Private Macros
AnnaBridge 163:e59c8e839560 1951 * @{
AnnaBridge 163:e59c8e839560 1952 */
AnnaBridge 163:e59c8e839560 1953
AnnaBridge 163:e59c8e839560 1954 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
AnnaBridge 163:e59c8e839560 1955 (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
AnnaBridge 163:e59c8e839560 1956 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
AnnaBridge 163:e59c8e839560 1957 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
AnnaBridge 163:e59c8e839560 1958 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
AnnaBridge 163:e59c8e839560 1959 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
AnnaBridge 163:e59c8e839560 1960 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
AnnaBridge 163:e59c8e839560 1961
AnnaBridge 163:e59c8e839560 1962 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
AnnaBridge 163:e59c8e839560 1963 (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
AnnaBridge 163:e59c8e839560 1964 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
AnnaBridge 163:e59c8e839560 1965 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
AnnaBridge 163:e59c8e839560 1966 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
AnnaBridge 163:e59c8e839560 1967 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
AnnaBridge 163:e59c8e839560 1968
AnnaBridge 163:e59c8e839560 1969 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)
AnnaBridge 163:e59c8e839560 1970
AnnaBridge 163:e59c8e839560 1971 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
AnnaBridge 163:e59c8e839560 1972 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
AnnaBridge 163:e59c8e839560 1973 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
AnnaBridge 163:e59c8e839560 1974 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
AnnaBridge 163:e59c8e839560 1975 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
AnnaBridge 163:e59c8e839560 1976
AnnaBridge 163:e59c8e839560 1977 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
AnnaBridge 163:e59c8e839560 1978 (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
AnnaBridge 163:e59c8e839560 1979 ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
AnnaBridge 163:e59c8e839560 1980
AnnaBridge 163:e59c8e839560 1981 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
AnnaBridge 163:e59c8e839560 1982
AnnaBridge 163:e59c8e839560 1983 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
AnnaBridge 163:e59c8e839560 1984 ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
AnnaBridge 163:e59c8e839560 1985 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
AnnaBridge 163:e59c8e839560 1986 ((OUTPUT) == HRTIM_OUTPUT_TA2))) \
AnnaBridge 163:e59c8e839560 1987 || \
AnnaBridge 163:e59c8e839560 1988 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
AnnaBridge 163:e59c8e839560 1989 (((OUTPUT) == HRTIM_OUTPUT_TB1) || \
AnnaBridge 163:e59c8e839560 1990 ((OUTPUT) == HRTIM_OUTPUT_TB2))) \
AnnaBridge 163:e59c8e839560 1991 || \
AnnaBridge 163:e59c8e839560 1992 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
AnnaBridge 163:e59c8e839560 1993 (((OUTPUT) == HRTIM_OUTPUT_TC1) || \
AnnaBridge 163:e59c8e839560 1994 ((OUTPUT) == HRTIM_OUTPUT_TC2))) \
AnnaBridge 163:e59c8e839560 1995 || \
AnnaBridge 163:e59c8e839560 1996 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
AnnaBridge 163:e59c8e839560 1997 (((OUTPUT) == HRTIM_OUTPUT_TD1) || \
AnnaBridge 163:e59c8e839560 1998 ((OUTPUT) == HRTIM_OUTPUT_TD2))) \
AnnaBridge 163:e59c8e839560 1999 || \
AnnaBridge 163:e59c8e839560 2000 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
AnnaBridge 163:e59c8e839560 2001 (((OUTPUT) == HRTIM_OUTPUT_TE1) || \
AnnaBridge 163:e59c8e839560 2002 ((OUTPUT) == HRTIM_OUTPUT_TE2))))
AnnaBridge 163:e59c8e839560 2003
AnnaBridge 163:e59c8e839560 2004 #define IS_HRTIM_EVENT(EVENT)\
AnnaBridge 163:e59c8e839560 2005 (((EVENT) == HRTIM_EVENT_1) || \
AnnaBridge 163:e59c8e839560 2006 ((EVENT) == HRTIM_EVENT_2) || \
AnnaBridge 163:e59c8e839560 2007 ((EVENT) == HRTIM_EVENT_3) || \
AnnaBridge 163:e59c8e839560 2008 ((EVENT) == HRTIM_EVENT_4) || \
AnnaBridge 163:e59c8e839560 2009 ((EVENT) == HRTIM_EVENT_5) || \
AnnaBridge 163:e59c8e839560 2010 ((EVENT) == HRTIM_EVENT_6) || \
AnnaBridge 163:e59c8e839560 2011 ((EVENT) == HRTIM_EVENT_7) || \
AnnaBridge 163:e59c8e839560 2012 ((EVENT) == HRTIM_EVENT_8) || \
AnnaBridge 163:e59c8e839560 2013 ((EVENT) == HRTIM_EVENT_9) || \
AnnaBridge 163:e59c8e839560 2014 ((EVENT) == HRTIM_EVENT_10))
AnnaBridge 163:e59c8e839560 2015
AnnaBridge 163:e59c8e839560 2016 #define IS_HRTIM_FAULT(FAULT)\
AnnaBridge 163:e59c8e839560 2017 (((FAULT) == HRTIM_FAULT_1) || \
AnnaBridge 163:e59c8e839560 2018 ((FAULT) == HRTIM_FAULT_2) || \
AnnaBridge 163:e59c8e839560 2019 ((FAULT) == HRTIM_FAULT_3) || \
AnnaBridge 163:e59c8e839560 2020 ((FAULT) == HRTIM_FAULT_4) || \
AnnaBridge 163:e59c8e839560 2021 ((FAULT) == HRTIM_FAULT_5))
AnnaBridge 163:e59c8e839560 2022
AnnaBridge 163:e59c8e839560 2023 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
AnnaBridge 163:e59c8e839560 2024 (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
AnnaBridge 163:e59c8e839560 2025 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
AnnaBridge 163:e59c8e839560 2026 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
AnnaBridge 163:e59c8e839560 2027 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
AnnaBridge 163:e59c8e839560 2028 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
AnnaBridge 163:e59c8e839560 2029 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
AnnaBridge 163:e59c8e839560 2030 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
AnnaBridge 163:e59c8e839560 2031 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
AnnaBridge 163:e59c8e839560 2032
AnnaBridge 163:e59c8e839560 2033 #define IS_HRTIM_MODE(MODE)\
AnnaBridge 163:e59c8e839560 2034 (((MODE) == HRTIM_MODE_CONTINUOUS) || \
AnnaBridge 163:e59c8e839560 2035 ((MODE) == HRTIM_MODE_SINGLESHOT) || \
AnnaBridge 163:e59c8e839560 2036 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
AnnaBridge 163:e59c8e839560 2037
AnnaBridge 163:e59c8e839560 2038 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
AnnaBridge 163:e59c8e839560 2039 (((MODE) == HRTIM_MODE_SINGLESHOT) || \
AnnaBridge 163:e59c8e839560 2040 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
AnnaBridge 163:e59c8e839560 2041
AnnaBridge 163:e59c8e839560 2042
AnnaBridge 163:e59c8e839560 2043 #define IS_HRTIM_HALFMODE(HALFMODE)\
AnnaBridge 163:e59c8e839560 2044 (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
AnnaBridge 163:e59c8e839560 2045 ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
AnnaBridge 163:e59c8e839560 2046
AnnaBridge 163:e59c8e839560 2047 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
AnnaBridge 163:e59c8e839560 2048 (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
AnnaBridge 163:e59c8e839560 2049 ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
AnnaBridge 163:e59c8e839560 2050
AnnaBridge 163:e59c8e839560 2051 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
AnnaBridge 163:e59c8e839560 2052 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
AnnaBridge 163:e59c8e839560 2053 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
AnnaBridge 163:e59c8e839560 2054
AnnaBridge 163:e59c8e839560 2055 #define IS_HHRTIM_DACSYNC(DACSYNC)\
AnnaBridge 163:e59c8e839560 2056 (((DACSYNC) == HRTIM_DACSYNC_NONE) || \
AnnaBridge 163:e59c8e839560 2057 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
AnnaBridge 163:e59c8e839560 2058 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
AnnaBridge 163:e59c8e839560 2059 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
AnnaBridge 163:e59c8e839560 2060
AnnaBridge 163:e59c8e839560 2061 #define IS_HRTIM_PRELOAD(PRELOAD)\
AnnaBridge 163:e59c8e839560 2062 (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
AnnaBridge 163:e59c8e839560 2063 ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
AnnaBridge 163:e59c8e839560 2064
AnnaBridge 163:e59c8e839560 2065 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
AnnaBridge 163:e59c8e839560 2066 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
AnnaBridge 163:e59c8e839560 2067 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
AnnaBridge 163:e59c8e839560 2068 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
AnnaBridge 163:e59c8e839560 2069
AnnaBridge 163:e59c8e839560 2070 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
AnnaBridge 163:e59c8e839560 2071 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
AnnaBridge 163:e59c8e839560 2072 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
AnnaBridge 163:e59c8e839560 2073 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
AnnaBridge 163:e59c8e839560 2074 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
AnnaBridge 163:e59c8e839560 2075 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
AnnaBridge 163:e59c8e839560 2076 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
AnnaBridge 163:e59c8e839560 2077 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
AnnaBridge 163:e59c8e839560 2078 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
AnnaBridge 163:e59c8e839560 2079 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
AnnaBridge 163:e59c8e839560 2080
AnnaBridge 163:e59c8e839560 2081 #define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
AnnaBridge 163:e59c8e839560 2082 (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
AnnaBridge 163:e59c8e839560 2083 ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
AnnaBridge 163:e59c8e839560 2084
AnnaBridge 163:e59c8e839560 2085 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
AnnaBridge 163:e59c8e839560 2086 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
AnnaBridge 163:e59c8e839560 2087 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
AnnaBridge 163:e59c8e839560 2088
AnnaBridge 163:e59c8e839560 2089 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
AnnaBridge 163:e59c8e839560 2090 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
AnnaBridge 163:e59c8e839560 2091 ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
AnnaBridge 163:e59c8e839560 2092
AnnaBridge 163:e59c8e839560 2093 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
AnnaBridge 163:e59c8e839560 2094
AnnaBridge 163:e59c8e839560 2095
AnnaBridge 163:e59c8e839560 2096 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
AnnaBridge 163:e59c8e839560 2097 (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
AnnaBridge 163:e59c8e839560 2098 ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
AnnaBridge 163:e59c8e839560 2099
AnnaBridge 163:e59c8e839560 2100 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
AnnaBridge 163:e59c8e839560 2101 ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \
AnnaBridge 163:e59c8e839560 2102 ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
AnnaBridge 163:e59c8e839560 2103 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \
AnnaBridge 163:e59c8e839560 2104 || \
AnnaBridge 163:e59c8e839560 2105 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
AnnaBridge 163:e59c8e839560 2106 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
AnnaBridge 163:e59c8e839560 2107
AnnaBridge 163:e59c8e839560 2108 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
AnnaBridge 163:e59c8e839560 2109 ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \
AnnaBridge 163:e59c8e839560 2110 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \
AnnaBridge 163:e59c8e839560 2111 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \
AnnaBridge 163:e59c8e839560 2112 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \
AnnaBridge 163:e59c8e839560 2113 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
AnnaBridge 163:e59c8e839560 2114 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
AnnaBridge 163:e59c8e839560 2115 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \
AnnaBridge 163:e59c8e839560 2116 || \
AnnaBridge 163:e59c8e839560 2117 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
AnnaBridge 163:e59c8e839560 2118 (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \
AnnaBridge 163:e59c8e839560 2119 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
AnnaBridge 163:e59c8e839560 2120
AnnaBridge 163:e59c8e839560 2121 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
AnnaBridge 163:e59c8e839560 2122
AnnaBridge 163:e59c8e839560 2123 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000U)
AnnaBridge 163:e59c8e839560 2124
AnnaBridge 163:e59c8e839560 2125
AnnaBridge 163:e59c8e839560 2126 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
AnnaBridge 163:e59c8e839560 2127 (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
AnnaBridge 163:e59c8e839560 2128 ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
AnnaBridge 163:e59c8e839560 2129
AnnaBridge 163:e59c8e839560 2130 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
AnnaBridge 163:e59c8e839560 2131 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
AnnaBridge 163:e59c8e839560 2132 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
AnnaBridge 163:e59c8e839560 2133 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
AnnaBridge 163:e59c8e839560 2134 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
AnnaBridge 163:e59c8e839560 2135
AnnaBridge 163:e59c8e839560 2136 /* Auto delayed mode is only available for compare units 2 and 4U */
AnnaBridge 163:e59c8e839560 2137 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
AnnaBridge 163:e59c8e839560 2138 ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
AnnaBridge 163:e59c8e839560 2139 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
AnnaBridge 163:e59c8e839560 2140 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
AnnaBridge 163:e59c8e839560 2141 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
AnnaBridge 163:e59c8e839560 2142 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
AnnaBridge 163:e59c8e839560 2143 || \
AnnaBridge 163:e59c8e839560 2144 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
AnnaBridge 163:e59c8e839560 2145 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
AnnaBridge 163:e59c8e839560 2146 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
AnnaBridge 163:e59c8e839560 2147 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
AnnaBridge 163:e59c8e839560 2148 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
AnnaBridge 163:e59c8e839560 2149
AnnaBridge 163:e59c8e839560 2150 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
AnnaBridge 163:e59c8e839560 2151 (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
AnnaBridge 163:e59c8e839560 2152 ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
AnnaBridge 163:e59c8e839560 2153
AnnaBridge 163:e59c8e839560 2154 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
AnnaBridge 163:e59c8e839560 2155 (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
AnnaBridge 163:e59c8e839560 2156 ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
AnnaBridge 163:e59c8e839560 2157 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
AnnaBridge 163:e59c8e839560 2158 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
AnnaBridge 163:e59c8e839560 2159 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
AnnaBridge 163:e59c8e839560 2160 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
AnnaBridge 163:e59c8e839560 2161 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
AnnaBridge 163:e59c8e839560 2162 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
AnnaBridge 163:e59c8e839560 2163 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
AnnaBridge 163:e59c8e839560 2164 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
AnnaBridge 163:e59c8e839560 2165 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
AnnaBridge 163:e59c8e839560 2166 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
AnnaBridge 163:e59c8e839560 2167 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
AnnaBridge 163:e59c8e839560 2168 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
AnnaBridge 163:e59c8e839560 2169 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
AnnaBridge 163:e59c8e839560 2170 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
AnnaBridge 163:e59c8e839560 2171 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
AnnaBridge 163:e59c8e839560 2172 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
AnnaBridge 163:e59c8e839560 2173 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
AnnaBridge 163:e59c8e839560 2174 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
AnnaBridge 163:e59c8e839560 2175 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
AnnaBridge 163:e59c8e839560 2176 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
AnnaBridge 163:e59c8e839560 2177 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
AnnaBridge 163:e59c8e839560 2178 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
AnnaBridge 163:e59c8e839560 2179 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
AnnaBridge 163:e59c8e839560 2180 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
AnnaBridge 163:e59c8e839560 2181 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
AnnaBridge 163:e59c8e839560 2182 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
AnnaBridge 163:e59c8e839560 2183 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
AnnaBridge 163:e59c8e839560 2184 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
AnnaBridge 163:e59c8e839560 2185 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
AnnaBridge 163:e59c8e839560 2186 ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
AnnaBridge 163:e59c8e839560 2187
AnnaBridge 163:e59c8e839560 2188 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
AnnaBridge 163:e59c8e839560 2189 (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
AnnaBridge 163:e59c8e839560 2190 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
AnnaBridge 163:e59c8e839560 2191 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
AnnaBridge 163:e59c8e839560 2192 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
AnnaBridge 163:e59c8e839560 2193 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
AnnaBridge 163:e59c8e839560 2194 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
AnnaBridge 163:e59c8e839560 2195 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
AnnaBridge 163:e59c8e839560 2196 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
AnnaBridge 163:e59c8e839560 2197 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
AnnaBridge 163:e59c8e839560 2198 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
AnnaBridge 163:e59c8e839560 2199 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
AnnaBridge 163:e59c8e839560 2200 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
AnnaBridge 163:e59c8e839560 2201 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
AnnaBridge 163:e59c8e839560 2202 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
AnnaBridge 163:e59c8e839560 2203 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
AnnaBridge 163:e59c8e839560 2204 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
AnnaBridge 163:e59c8e839560 2205 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
AnnaBridge 163:e59c8e839560 2206 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
AnnaBridge 163:e59c8e839560 2207 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
AnnaBridge 163:e59c8e839560 2208 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
AnnaBridge 163:e59c8e839560 2209 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
AnnaBridge 163:e59c8e839560 2210 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
AnnaBridge 163:e59c8e839560 2211 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
AnnaBridge 163:e59c8e839560 2212 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
AnnaBridge 163:e59c8e839560 2213 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
AnnaBridge 163:e59c8e839560 2214 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
AnnaBridge 163:e59c8e839560 2215 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
AnnaBridge 163:e59c8e839560 2216 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
AnnaBridge 163:e59c8e839560 2217 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
AnnaBridge 163:e59c8e839560 2218 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
AnnaBridge 163:e59c8e839560 2219 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
AnnaBridge 163:e59c8e839560 2220 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
AnnaBridge 163:e59c8e839560 2221
AnnaBridge 163:e59c8e839560 2222 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
AnnaBridge 163:e59c8e839560 2223 (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
AnnaBridge 163:e59c8e839560 2224 ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
AnnaBridge 163:e59c8e839560 2225
AnnaBridge 163:e59c8e839560 2226 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
AnnaBridge 163:e59c8e839560 2227 (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
AnnaBridge 163:e59c8e839560 2228 ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
AnnaBridge 163:e59c8e839560 2229
AnnaBridge 163:e59c8e839560 2230 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
AnnaBridge 163:e59c8e839560 2231 (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \
AnnaBridge 163:e59c8e839560 2232 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \
AnnaBridge 163:e59c8e839560 2233 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
AnnaBridge 163:e59c8e839560 2234 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
AnnaBridge 163:e59c8e839560 2235
AnnaBridge 163:e59c8e839560 2236 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
AnnaBridge 163:e59c8e839560 2237 (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
AnnaBridge 163:e59c8e839560 2238 ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
AnnaBridge 163:e59c8e839560 2239
AnnaBridge 163:e59c8e839560 2240 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
AnnaBridge 163:e59c8e839560 2241 (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
AnnaBridge 163:e59c8e839560 2242 ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
AnnaBridge 163:e59c8e839560 2243
AnnaBridge 163:e59c8e839560 2244 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
AnnaBridge 163:e59c8e839560 2245 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
AnnaBridge 163:e59c8e839560 2246 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
AnnaBridge 163:e59c8e839560 2247 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
AnnaBridge 163:e59c8e839560 2248 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
AnnaBridge 163:e59c8e839560 2249 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
AnnaBridge 163:e59c8e839560 2250 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
AnnaBridge 163:e59c8e839560 2251 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
AnnaBridge 163:e59c8e839560 2252 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
AnnaBridge 163:e59c8e839560 2253 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
AnnaBridge 163:e59c8e839560 2254 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
AnnaBridge 163:e59c8e839560 2255 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
AnnaBridge 163:e59c8e839560 2256 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
AnnaBridge 163:e59c8e839560 2257 || \
AnnaBridge 163:e59c8e839560 2258 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
AnnaBridge 163:e59c8e839560 2259 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
AnnaBridge 163:e59c8e839560 2260 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
AnnaBridge 163:e59c8e839560 2261 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
AnnaBridge 163:e59c8e839560 2262 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
AnnaBridge 163:e59c8e839560 2263 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
AnnaBridge 163:e59c8e839560 2264 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
AnnaBridge 163:e59c8e839560 2265 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
AnnaBridge 163:e59c8e839560 2266 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
AnnaBridge 163:e59c8e839560 2267 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
AnnaBridge 163:e59c8e839560 2268 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
AnnaBridge 163:e59c8e839560 2269 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
AnnaBridge 163:e59c8e839560 2270 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
AnnaBridge 163:e59c8e839560 2271 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
AnnaBridge 163:e59c8e839560 2272 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
AnnaBridge 163:e59c8e839560 2273 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
AnnaBridge 163:e59c8e839560 2274 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
AnnaBridge 163:e59c8e839560 2275 || \
AnnaBridge 163:e59c8e839560 2276 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
AnnaBridge 163:e59c8e839560 2277 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
AnnaBridge 163:e59c8e839560 2278 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
AnnaBridge 163:e59c8e839560 2279 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
AnnaBridge 163:e59c8e839560 2280 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
AnnaBridge 163:e59c8e839560 2281 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
AnnaBridge 163:e59c8e839560 2282 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
AnnaBridge 163:e59c8e839560 2283 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
AnnaBridge 163:e59c8e839560 2284 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
AnnaBridge 163:e59c8e839560 2285 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
AnnaBridge 163:e59c8e839560 2286 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
AnnaBridge 163:e59c8e839560 2287 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
AnnaBridge 163:e59c8e839560 2288 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
AnnaBridge 163:e59c8e839560 2289 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
AnnaBridge 163:e59c8e839560 2290 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
AnnaBridge 163:e59c8e839560 2291 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
AnnaBridge 163:e59c8e839560 2292 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
AnnaBridge 163:e59c8e839560 2293 || \
AnnaBridge 163:e59c8e839560 2294 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
AnnaBridge 163:e59c8e839560 2295 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
AnnaBridge 163:e59c8e839560 2296 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
AnnaBridge 163:e59c8e839560 2297 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
AnnaBridge 163:e59c8e839560 2298 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
AnnaBridge 163:e59c8e839560 2299 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
AnnaBridge 163:e59c8e839560 2300 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
AnnaBridge 163:e59c8e839560 2301 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
AnnaBridge 163:e59c8e839560 2302 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
AnnaBridge 163:e59c8e839560 2303 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
AnnaBridge 163:e59c8e839560 2304 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
AnnaBridge 163:e59c8e839560 2305 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
AnnaBridge 163:e59c8e839560 2306 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
AnnaBridge 163:e59c8e839560 2307 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
AnnaBridge 163:e59c8e839560 2308 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
AnnaBridge 163:e59c8e839560 2309 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
AnnaBridge 163:e59c8e839560 2310 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
AnnaBridge 163:e59c8e839560 2311 || \
AnnaBridge 163:e59c8e839560 2312 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
AnnaBridge 163:e59c8e839560 2313 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
AnnaBridge 163:e59c8e839560 2314 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
AnnaBridge 163:e59c8e839560 2315 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
AnnaBridge 163:e59c8e839560 2316 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
AnnaBridge 163:e59c8e839560 2317 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
AnnaBridge 163:e59c8e839560 2318 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
AnnaBridge 163:e59c8e839560 2319 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
AnnaBridge 163:e59c8e839560 2320 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
AnnaBridge 163:e59c8e839560 2321 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
AnnaBridge 163:e59c8e839560 2322 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
AnnaBridge 163:e59c8e839560 2323 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
AnnaBridge 163:e59c8e839560 2324 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
AnnaBridge 163:e59c8e839560 2325 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
AnnaBridge 163:e59c8e839560 2326 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
AnnaBridge 163:e59c8e839560 2327 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
AnnaBridge 163:e59c8e839560 2328 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
AnnaBridge 163:e59c8e839560 2329 || \
AnnaBridge 163:e59c8e839560 2330 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
AnnaBridge 163:e59c8e839560 2331 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
AnnaBridge 163:e59c8e839560 2332 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
AnnaBridge 163:e59c8e839560 2333 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
AnnaBridge 163:e59c8e839560 2334 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
AnnaBridge 163:e59c8e839560 2335 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
AnnaBridge 163:e59c8e839560 2336 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
AnnaBridge 163:e59c8e839560 2337 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
AnnaBridge 163:e59c8e839560 2338 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
AnnaBridge 163:e59c8e839560 2339 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
AnnaBridge 163:e59c8e839560 2340 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
AnnaBridge 163:e59c8e839560 2341 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
AnnaBridge 163:e59c8e839560 2342 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
AnnaBridge 163:e59c8e839560 2343 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
AnnaBridge 163:e59c8e839560 2344 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
AnnaBridge 163:e59c8e839560 2345 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
AnnaBridge 163:e59c8e839560 2346 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
AnnaBridge 163:e59c8e839560 2347
AnnaBridge 163:e59c8e839560 2348 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
AnnaBridge 163:e59c8e839560 2349 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \
AnnaBridge 163:e59c8e839560 2350 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \
AnnaBridge 163:e59c8e839560 2351 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \
AnnaBridge 163:e59c8e839560 2352 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \
AnnaBridge 163:e59c8e839560 2353 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \
AnnaBridge 163:e59c8e839560 2354 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \
AnnaBridge 163:e59c8e839560 2355 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \
AnnaBridge 163:e59c8e839560 2356 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \
AnnaBridge 163:e59c8e839560 2357 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \
AnnaBridge 163:e59c8e839560 2358 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \
AnnaBridge 163:e59c8e839560 2359 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \
AnnaBridge 163:e59c8e839560 2360 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \
AnnaBridge 163:e59c8e839560 2361 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \
AnnaBridge 163:e59c8e839560 2362 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \
AnnaBridge 163:e59c8e839560 2363 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \
AnnaBridge 163:e59c8e839560 2364 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
AnnaBridge 163:e59c8e839560 2365
AnnaBridge 163:e59c8e839560 2366 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
AnnaBridge 163:e59c8e839560 2367 (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
AnnaBridge 163:e59c8e839560 2368 ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
AnnaBridge 163:e59c8e839560 2369
AnnaBridge 163:e59c8e839560 2370 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
AnnaBridge 163:e59c8e839560 2371 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
AnnaBridge 163:e59c8e839560 2372 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
AnnaBridge 163:e59c8e839560 2373 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
AnnaBridge 163:e59c8e839560 2374 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
AnnaBridge 163:e59c8e839560 2375 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
AnnaBridge 163:e59c8e839560 2376 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
AnnaBridge 163:e59c8e839560 2377 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
AnnaBridge 163:e59c8e839560 2378 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
AnnaBridge 163:e59c8e839560 2379
AnnaBridge 163:e59c8e839560 2380 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
AnnaBridge 163:e59c8e839560 2381 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
AnnaBridge 163:e59c8e839560 2382 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
AnnaBridge 163:e59c8e839560 2383
AnnaBridge 163:e59c8e839560 2384 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
AnnaBridge 163:e59c8e839560 2385 (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
AnnaBridge 163:e59c8e839560 2386 ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
AnnaBridge 163:e59c8e839560 2387
AnnaBridge 163:e59c8e839560 2388 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
AnnaBridge 163:e59c8e839560 2389 (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
AnnaBridge 163:e59c8e839560 2390 ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
AnnaBridge 163:e59c8e839560 2391
AnnaBridge 163:e59c8e839560 2392 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
AnnaBridge 163:e59c8e839560 2393 (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
AnnaBridge 163:e59c8e839560 2394 ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
AnnaBridge 163:e59c8e839560 2395
AnnaBridge 163:e59c8e839560 2396 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
AnnaBridge 163:e59c8e839560 2397 (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
AnnaBridge 163:e59c8e839560 2398 ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
AnnaBridge 163:e59c8e839560 2399
AnnaBridge 163:e59c8e839560 2400 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
AnnaBridge 163:e59c8e839560 2401 (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
AnnaBridge 163:e59c8e839560 2402 ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
AnnaBridge 163:e59c8e839560 2403
AnnaBridge 163:e59c8e839560 2404 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
AnnaBridge 163:e59c8e839560 2405 (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \
AnnaBridge 163:e59c8e839560 2406 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \
AnnaBridge 163:e59c8e839560 2407 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \
AnnaBridge 163:e59c8e839560 2408 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \
AnnaBridge 163:e59c8e839560 2409 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \
AnnaBridge 163:e59c8e839560 2410 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \
AnnaBridge 163:e59c8e839560 2411 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \
AnnaBridge 163:e59c8e839560 2412 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \
AnnaBridge 163:e59c8e839560 2413 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \
AnnaBridge 163:e59c8e839560 2414 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \
AnnaBridge 163:e59c8e839560 2415 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \
AnnaBridge 163:e59c8e839560 2416 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \
AnnaBridge 163:e59c8e839560 2417 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \
AnnaBridge 163:e59c8e839560 2418 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \
AnnaBridge 163:e59c8e839560 2419 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \
AnnaBridge 163:e59c8e839560 2420 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
AnnaBridge 163:e59c8e839560 2421
AnnaBridge 163:e59c8e839560 2422 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
AnnaBridge 163:e59c8e839560 2423 (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \
AnnaBridge 163:e59c8e839560 2424 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \
AnnaBridge 163:e59c8e839560 2425 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \
AnnaBridge 163:e59c8e839560 2426 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \
AnnaBridge 163:e59c8e839560 2427 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \
AnnaBridge 163:e59c8e839560 2428 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \
AnnaBridge 163:e59c8e839560 2429 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \
AnnaBridge 163:e59c8e839560 2430 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
AnnaBridge 163:e59c8e839560 2431
AnnaBridge 163:e59c8e839560 2432 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
AnnaBridge 163:e59c8e839560 2433 (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \
AnnaBridge 163:e59c8e839560 2434 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \
AnnaBridge 163:e59c8e839560 2435 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \
AnnaBridge 163:e59c8e839560 2436 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \
AnnaBridge 163:e59c8e839560 2437 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \
AnnaBridge 163:e59c8e839560 2438 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \
AnnaBridge 163:e59c8e839560 2439 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \
AnnaBridge 163:e59c8e839560 2440 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \
AnnaBridge 163:e59c8e839560 2441 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \
AnnaBridge 163:e59c8e839560 2442 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \
AnnaBridge 163:e59c8e839560 2443 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \
AnnaBridge 163:e59c8e839560 2444 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \
AnnaBridge 163:e59c8e839560 2445 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \
AnnaBridge 163:e59c8e839560 2446 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \
AnnaBridge 163:e59c8e839560 2447 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \
AnnaBridge 163:e59c8e839560 2448 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
AnnaBridge 163:e59c8e839560 2449
AnnaBridge 163:e59c8e839560 2450 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
AnnaBridge 163:e59c8e839560 2451 (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
AnnaBridge 163:e59c8e839560 2452 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
AnnaBridge 163:e59c8e839560 2453 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
AnnaBridge 163:e59c8e839560 2454
AnnaBridge 163:e59c8e839560 2455 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
AnnaBridge 163:e59c8e839560 2456 (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
AnnaBridge 163:e59c8e839560 2457 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
AnnaBridge 163:e59c8e839560 2458 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
AnnaBridge 163:e59c8e839560 2459 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
AnnaBridge 163:e59c8e839560 2460
AnnaBridge 163:e59c8e839560 2461 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
AnnaBridge 163:e59c8e839560 2462 (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
AnnaBridge 163:e59c8e839560 2463 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
AnnaBridge 163:e59c8e839560 2464 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
AnnaBridge 163:e59c8e839560 2465
AnnaBridge 163:e59c8e839560 2466 #define IS_HRTIM_EVENTSRC(EVENTSRC)\
AnnaBridge 163:e59c8e839560 2467 (((EVENTSRC) == HRTIM_EVENTSRC_1) || \
AnnaBridge 163:e59c8e839560 2468 ((EVENTSRC) == HRTIM_EVENTSRC_2) || \
AnnaBridge 163:e59c8e839560 2469 ((EVENTSRC) == HRTIM_EVENTSRC_3) || \
AnnaBridge 163:e59c8e839560 2470 ((EVENTSRC) == HRTIM_EVENTSRC_4))
AnnaBridge 163:e59c8e839560 2471
AnnaBridge 163:e59c8e839560 2472 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
AnnaBridge 163:e59c8e839560 2473 ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
AnnaBridge 163:e59c8e839560 2474 (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
AnnaBridge 163:e59c8e839560 2475 ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \
AnnaBridge 163:e59c8e839560 2476 || \
AnnaBridge 163:e59c8e839560 2477 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
AnnaBridge 163:e59c8e839560 2478 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
AnnaBridge 163:e59c8e839560 2479 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
AnnaBridge 163:e59c8e839560 2480
AnnaBridge 163:e59c8e839560 2481 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
AnnaBridge 163:e59c8e839560 2482 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
AnnaBridge 163:e59c8e839560 2483 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
AnnaBridge 163:e59c8e839560 2484 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
AnnaBridge 163:e59c8e839560 2485 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
AnnaBridge 163:e59c8e839560 2486
AnnaBridge 163:e59c8e839560 2487 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
AnnaBridge 163:e59c8e839560 2488 (((((EVENT) == HRTIM_EVENT_1) || \
AnnaBridge 163:e59c8e839560 2489 ((EVENT) == HRTIM_EVENT_2) || \
AnnaBridge 163:e59c8e839560 2490 ((EVENT) == HRTIM_EVENT_3) || \
AnnaBridge 163:e59c8e839560 2491 ((EVENT) == HRTIM_EVENT_4) || \
AnnaBridge 163:e59c8e839560 2492 ((EVENT) == HRTIM_EVENT_5)) && \
AnnaBridge 163:e59c8e839560 2493 (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
AnnaBridge 163:e59c8e839560 2494 ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
AnnaBridge 163:e59c8e839560 2495 || \
AnnaBridge 163:e59c8e839560 2496 (((EVENT) == HRTIM_EVENT_6) || \
AnnaBridge 163:e59c8e839560 2497 ((EVENT) == HRTIM_EVENT_7) || \
AnnaBridge 163:e59c8e839560 2498 ((EVENT) == HRTIM_EVENT_8) || \
AnnaBridge 163:e59c8e839560 2499 ((EVENT) == HRTIM_EVENT_9) || \
AnnaBridge 163:e59c8e839560 2500 ((EVENT) == HRTIM_EVENT_10)))
AnnaBridge 163:e59c8e839560 2501
AnnaBridge 163:e59c8e839560 2502
AnnaBridge 163:e59c8e839560 2503 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
AnnaBridge 163:e59c8e839560 2504 ((((EVENT) == HRTIM_EVENT_1) || \
AnnaBridge 163:e59c8e839560 2505 ((EVENT) == HRTIM_EVENT_2) || \
AnnaBridge 163:e59c8e839560 2506 ((EVENT) == HRTIM_EVENT_3) || \
AnnaBridge 163:e59c8e839560 2507 ((EVENT) == HRTIM_EVENT_4) || \
AnnaBridge 163:e59c8e839560 2508 ((EVENT) == HRTIM_EVENT_5)) \
AnnaBridge 163:e59c8e839560 2509 || \
AnnaBridge 163:e59c8e839560 2510 ((((EVENT) == HRTIM_EVENT_6) || \
AnnaBridge 163:e59c8e839560 2511 ((EVENT) == HRTIM_EVENT_7) || \
AnnaBridge 163:e59c8e839560 2512 ((EVENT) == HRTIM_EVENT_8) || \
AnnaBridge 163:e59c8e839560 2513 ((EVENT) == HRTIM_EVENT_9) || \
AnnaBridge 163:e59c8e839560 2514 ((EVENT) == HRTIM_EVENT_10)) && \
AnnaBridge 163:e59c8e839560 2515 (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
AnnaBridge 163:e59c8e839560 2516 ((FILTER) == HRTIM_EVENTFILTER_1) || \
AnnaBridge 163:e59c8e839560 2517 ((FILTER) == HRTIM_EVENTFILTER_2) || \
AnnaBridge 163:e59c8e839560 2518 ((FILTER) == HRTIM_EVENTFILTER_3) || \
AnnaBridge 163:e59c8e839560 2519 ((FILTER) == HRTIM_EVENTFILTER_4) || \
AnnaBridge 163:e59c8e839560 2520 ((FILTER) == HRTIM_EVENTFILTER_5) || \
AnnaBridge 163:e59c8e839560 2521 ((FILTER) == HRTIM_EVENTFILTER_6) || \
AnnaBridge 163:e59c8e839560 2522 ((FILTER) == HRTIM_EVENTFILTER_7) || \
AnnaBridge 163:e59c8e839560 2523 ((FILTER) == HRTIM_EVENTFILTER_8) || \
AnnaBridge 163:e59c8e839560 2524 ((FILTER) == HRTIM_EVENTFILTER_9) || \
AnnaBridge 163:e59c8e839560 2525 ((FILTER) == HRTIM_EVENTFILTER_10) || \
AnnaBridge 163:e59c8e839560 2526 ((FILTER) == HRTIM_EVENTFILTER_11) || \
AnnaBridge 163:e59c8e839560 2527 ((FILTER) == HRTIM_EVENTFILTER_12) || \
AnnaBridge 163:e59c8e839560 2528 ((FILTER) == HRTIM_EVENTFILTER_13) || \
AnnaBridge 163:e59c8e839560 2529 ((FILTER) == HRTIM_EVENTFILTER_14) || \
AnnaBridge 163:e59c8e839560 2530 ((FILTER) == HRTIM_EVENTFILTER_15))))
AnnaBridge 163:e59c8e839560 2531
AnnaBridge 163:e59c8e839560 2532 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
AnnaBridge 163:e59c8e839560 2533 (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
AnnaBridge 163:e59c8e839560 2534 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
AnnaBridge 163:e59c8e839560 2535 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
AnnaBridge 163:e59c8e839560 2536 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
AnnaBridge 163:e59c8e839560 2537 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
AnnaBridge 163:e59c8e839560 2538 (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
AnnaBridge 163:e59c8e839560 2539 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
AnnaBridge 163:e59c8e839560 2540
AnnaBridge 163:e59c8e839560 2541 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
AnnaBridge 163:e59c8e839560 2542 (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
AnnaBridge 163:e59c8e839560 2543 ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
AnnaBridge 163:e59c8e839560 2544
AnnaBridge 163:e59c8e839560 2545 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
AnnaBridge 163:e59c8e839560 2546 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
AnnaBridge 163:e59c8e839560 2547 ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
AnnaBridge 163:e59c8e839560 2548 ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
AnnaBridge 163:e59c8e839560 2549 ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
AnnaBridge 163:e59c8e839560 2550 ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
AnnaBridge 163:e59c8e839560 2551 ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
AnnaBridge 163:e59c8e839560 2552 ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
AnnaBridge 163:e59c8e839560 2553 ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
AnnaBridge 163:e59c8e839560 2554 ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
AnnaBridge 163:e59c8e839560 2555 ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
AnnaBridge 163:e59c8e839560 2556 ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
AnnaBridge 163:e59c8e839560 2557 ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
AnnaBridge 163:e59c8e839560 2558 ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
AnnaBridge 163:e59c8e839560 2559 ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
AnnaBridge 163:e59c8e839560 2560 ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
AnnaBridge 163:e59c8e839560 2561 ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
AnnaBridge 163:e59c8e839560 2562
AnnaBridge 163:e59c8e839560 2563 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
AnnaBridge 163:e59c8e839560 2564 (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
AnnaBridge 163:e59c8e839560 2565 ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
AnnaBridge 163:e59c8e839560 2566
AnnaBridge 163:e59c8e839560 2567 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
AnnaBridge 163:e59c8e839560 2568 (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
AnnaBridge 163:e59c8e839560 2569 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
AnnaBridge 163:e59c8e839560 2570 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
AnnaBridge 163:e59c8e839560 2571 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
AnnaBridge 163:e59c8e839560 2572
AnnaBridge 163:e59c8e839560 2573 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
AnnaBridge 163:e59c8e839560 2574 (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
AnnaBridge 163:e59c8e839560 2575 ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
AnnaBridge 163:e59c8e839560 2576
AnnaBridge 163:e59c8e839560 2577 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
AnnaBridge 163:e59c8e839560 2578 (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
AnnaBridge 163:e59c8e839560 2579 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
AnnaBridge 163:e59c8e839560 2580 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
AnnaBridge 163:e59c8e839560 2581 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
AnnaBridge 163:e59c8e839560 2582 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
AnnaBridge 163:e59c8e839560 2583 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
AnnaBridge 163:e59c8e839560 2584 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \
AnnaBridge 163:e59c8e839560 2585 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \
AnnaBridge 163:e59c8e839560 2586 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \
AnnaBridge 163:e59c8e839560 2587 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
AnnaBridge 163:e59c8e839560 2588
AnnaBridge 163:e59c8e839560 2589 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
AnnaBridge 163:e59c8e839560 2590 (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
AnnaBridge 163:e59c8e839560 2591 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
AnnaBridge 163:e59c8e839560 2592 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
AnnaBridge 163:e59c8e839560 2593 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
AnnaBridge 163:e59c8e839560 2594 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
AnnaBridge 163:e59c8e839560 2595 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
AnnaBridge 163:e59c8e839560 2596 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
AnnaBridge 163:e59c8e839560 2597 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
AnnaBridge 163:e59c8e839560 2598 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
AnnaBridge 163:e59c8e839560 2599 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
AnnaBridge 163:e59c8e839560 2600 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
AnnaBridge 163:e59c8e839560 2601 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
AnnaBridge 163:e59c8e839560 2602 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
AnnaBridge 163:e59c8e839560 2603 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
AnnaBridge 163:e59c8e839560 2604 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
AnnaBridge 163:e59c8e839560 2605 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
AnnaBridge 163:e59c8e839560 2606
AnnaBridge 163:e59c8e839560 2607 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
AnnaBridge 163:e59c8e839560 2608 (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
AnnaBridge 163:e59c8e839560 2609 ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
AnnaBridge 163:e59c8e839560 2610
AnnaBridge 163:e59c8e839560 2611 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
AnnaBridge 163:e59c8e839560 2612 (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
AnnaBridge 163:e59c8e839560 2613 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
AnnaBridge 163:e59c8e839560 2614 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
AnnaBridge 163:e59c8e839560 2615 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
AnnaBridge 163:e59c8e839560 2616 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
AnnaBridge 163:e59c8e839560 2617 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
AnnaBridge 163:e59c8e839560 2618 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
AnnaBridge 163:e59c8e839560 2619 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
AnnaBridge 163:e59c8e839560 2620 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
AnnaBridge 163:e59c8e839560 2621 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
AnnaBridge 163:e59c8e839560 2622 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
AnnaBridge 163:e59c8e839560 2623 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
AnnaBridge 163:e59c8e839560 2624 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
AnnaBridge 163:e59c8e839560 2625 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
AnnaBridge 163:e59c8e839560 2626 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
AnnaBridge 163:e59c8e839560 2627 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
AnnaBridge 163:e59c8e839560 2628 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
AnnaBridge 163:e59c8e839560 2629 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
AnnaBridge 163:e59c8e839560 2630 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \
AnnaBridge 163:e59c8e839560 2631 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
AnnaBridge 163:e59c8e839560 2632 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
AnnaBridge 163:e59c8e839560 2633 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \
AnnaBridge 163:e59c8e839560 2634 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
AnnaBridge 163:e59c8e839560 2635 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \
AnnaBridge 163:e59c8e839560 2636 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
AnnaBridge 163:e59c8e839560 2637 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
AnnaBridge 163:e59c8e839560 2638 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
AnnaBridge 163:e59c8e839560 2639 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
AnnaBridge 163:e59c8e839560 2640 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
AnnaBridge 163:e59c8e839560 2641 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
AnnaBridge 163:e59c8e839560 2642 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
AnnaBridge 163:e59c8e839560 2643 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
AnnaBridge 163:e59c8e839560 2644
AnnaBridge 163:e59c8e839560 2645 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
AnnaBridge 163:e59c8e839560 2646 (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
AnnaBridge 163:e59c8e839560 2647 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
AnnaBridge 163:e59c8e839560 2648 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
AnnaBridge 163:e59c8e839560 2649 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
AnnaBridge 163:e59c8e839560 2650 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
AnnaBridge 163:e59c8e839560 2651 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
AnnaBridge 163:e59c8e839560 2652
AnnaBridge 163:e59c8e839560 2653 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
AnnaBridge 163:e59c8e839560 2654 (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
AnnaBridge 163:e59c8e839560 2655 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
AnnaBridge 163:e59c8e839560 2656 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \
AnnaBridge 163:e59c8e839560 2657 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
AnnaBridge 163:e59c8e839560 2658 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
AnnaBridge 163:e59c8e839560 2659
AnnaBridge 163:e59c8e839560 2660 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
AnnaBridge 163:e59c8e839560 2661 ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
AnnaBridge 163:e59c8e839560 2662 || \
AnnaBridge 163:e59c8e839560 2663 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
AnnaBridge 163:e59c8e839560 2664 || \
AnnaBridge 163:e59c8e839560 2665 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
AnnaBridge 163:e59c8e839560 2666 || \
AnnaBridge 163:e59c8e839560 2667 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
AnnaBridge 163:e59c8e839560 2668 || \
AnnaBridge 163:e59c8e839560 2669 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
AnnaBridge 163:e59c8e839560 2670 || \
AnnaBridge 163:e59c8e839560 2671 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
AnnaBridge 163:e59c8e839560 2672
AnnaBridge 163:e59c8e839560 2673 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
AnnaBridge 163:e59c8e839560 2674 (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
AnnaBridge 163:e59c8e839560 2675 ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
AnnaBridge 163:e59c8e839560 2676
AnnaBridge 163:e59c8e839560 2677 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
AnnaBridge 163:e59c8e839560 2678
AnnaBridge 163:e59c8e839560 2679 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
AnnaBridge 163:e59c8e839560 2680
AnnaBridge 163:e59c8e839560 2681 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
AnnaBridge 163:e59c8e839560 2682
AnnaBridge 163:e59c8e839560 2683
AnnaBridge 163:e59c8e839560 2684 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
AnnaBridge 163:e59c8e839560 2685
AnnaBridge 163:e59c8e839560 2686
AnnaBridge 163:e59c8e839560 2687 #define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000U)
AnnaBridge 163:e59c8e839560 2688
AnnaBridge 163:e59c8e839560 2689
AnnaBridge 163:e59c8e839560 2690 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
AnnaBridge 163:e59c8e839560 2691
AnnaBridge 163:e59c8e839560 2692 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
AnnaBridge 163:e59c8e839560 2693 /**
AnnaBridge 163:e59c8e839560 2694 * @}
AnnaBridge 163:e59c8e839560 2695 */
AnnaBridge 163:e59c8e839560 2696
AnnaBridge 163:e59c8e839560 2697 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 2698 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
AnnaBridge 163:e59c8e839560 2699 * @{
AnnaBridge 163:e59c8e839560 2700 */
AnnaBridge 163:e59c8e839560 2701
AnnaBridge 163:e59c8e839560 2702 /** @brief Reset HRTIM handle state
AnnaBridge 168:b9e159c1930a 2703 * @param __HANDLE__ HRTIM handle.
AnnaBridge 163:e59c8e839560 2704 * @retval None
AnnaBridge 163:e59c8e839560 2705 */
AnnaBridge 163:e59c8e839560 2706 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
AnnaBridge 163:e59c8e839560 2707
AnnaBridge 163:e59c8e839560 2708 /** @brief Enables or disables the timer counter(s)
AnnaBridge 168:b9e159c1930a 2709 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2710 * @param __TIMERS__ timers to enable/disable
AnnaBridge 163:e59c8e839560 2711 * This parameter can be any combinations of the following values:
AnnaBridge 163:e59c8e839560 2712 * @arg HRTIM_TIMERID_MASTER: Master timer identifier
AnnaBridge 163:e59c8e839560 2713 * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
AnnaBridge 163:e59c8e839560 2714 * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
AnnaBridge 163:e59c8e839560 2715 * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
AnnaBridge 163:e59c8e839560 2716 * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
AnnaBridge 163:e59c8e839560 2717 * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
AnnaBridge 163:e59c8e839560 2718 * @retval None
AnnaBridge 163:e59c8e839560 2719 */
AnnaBridge 163:e59c8e839560 2720 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
AnnaBridge 163:e59c8e839560 2721
AnnaBridge 163:e59c8e839560 2722 /* The counter of a timing unit is disabled only if all the timer outputs */
AnnaBridge 163:e59c8e839560 2723 /* are disabled and no capture is configured */
AnnaBridge 163:e59c8e839560 2724 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
AnnaBridge 163:e59c8e839560 2725 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
AnnaBridge 163:e59c8e839560 2726 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
AnnaBridge 163:e59c8e839560 2727 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
AnnaBridge 163:e59c8e839560 2728 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
AnnaBridge 163:e59c8e839560 2729 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
AnnaBridge 163:e59c8e839560 2730 do {\
AnnaBridge 163:e59c8e839560 2731 if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
AnnaBridge 163:e59c8e839560 2732 {\
AnnaBridge 163:e59c8e839560 2733 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
AnnaBridge 163:e59c8e839560 2734 }\
AnnaBridge 163:e59c8e839560 2735 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
AnnaBridge 163:e59c8e839560 2736 {\
AnnaBridge 163:e59c8e839560 2737 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
AnnaBridge 163:e59c8e839560 2738 {\
AnnaBridge 163:e59c8e839560 2739 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
AnnaBridge 163:e59c8e839560 2740 }\
AnnaBridge 163:e59c8e839560 2741 }\
AnnaBridge 163:e59c8e839560 2742 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
AnnaBridge 163:e59c8e839560 2743 {\
AnnaBridge 163:e59c8e839560 2744 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
AnnaBridge 163:e59c8e839560 2745 {\
AnnaBridge 163:e59c8e839560 2746 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
AnnaBridge 163:e59c8e839560 2747 }\
AnnaBridge 163:e59c8e839560 2748 }\
AnnaBridge 163:e59c8e839560 2749 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
AnnaBridge 163:e59c8e839560 2750 {\
AnnaBridge 163:e59c8e839560 2751 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
AnnaBridge 163:e59c8e839560 2752 {\
AnnaBridge 163:e59c8e839560 2753 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
AnnaBridge 163:e59c8e839560 2754 }\
AnnaBridge 163:e59c8e839560 2755 }\
AnnaBridge 163:e59c8e839560 2756 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
AnnaBridge 163:e59c8e839560 2757 {\
AnnaBridge 163:e59c8e839560 2758 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
AnnaBridge 163:e59c8e839560 2759 {\
AnnaBridge 163:e59c8e839560 2760 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
AnnaBridge 163:e59c8e839560 2761 }\
AnnaBridge 163:e59c8e839560 2762 }\
AnnaBridge 163:e59c8e839560 2763 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
AnnaBridge 163:e59c8e839560 2764 {\
AnnaBridge 163:e59c8e839560 2765 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
AnnaBridge 163:e59c8e839560 2766 {\
AnnaBridge 163:e59c8e839560 2767 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
AnnaBridge 163:e59c8e839560 2768 }\
AnnaBridge 163:e59c8e839560 2769 }\
AnnaBridge 163:e59c8e839560 2770 } while(0U)
AnnaBridge 163:e59c8e839560 2771
AnnaBridge 163:e59c8e839560 2772 /** @brief Enables or disables the specified HRTIM common interrupts.
AnnaBridge 168:b9e159c1930a 2773 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2774 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
AnnaBridge 163:e59c8e839560 2775 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2776 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
AnnaBridge 163:e59c8e839560 2777 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
AnnaBridge 163:e59c8e839560 2778 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
AnnaBridge 163:e59c8e839560 2779 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
AnnaBridge 163:e59c8e839560 2780 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
AnnaBridge 163:e59c8e839560 2781 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
AnnaBridge 163:e59c8e839560 2782 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
AnnaBridge 163:e59c8e839560 2783 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
AnnaBridge 163:e59c8e839560 2784 * @retval None
AnnaBridge 163:e59c8e839560 2785 */
AnnaBridge 163:e59c8e839560 2786 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
AnnaBridge 163:e59c8e839560 2787 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
AnnaBridge 163:e59c8e839560 2788
AnnaBridge 163:e59c8e839560 2789 /** @brief Enables or disables the specified HRTIM Master timer interrupts.
AnnaBridge 168:b9e159c1930a 2790 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2791 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
AnnaBridge 163:e59c8e839560 2792 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2793 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
AnnaBridge 163:e59c8e839560 2794 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
AnnaBridge 163:e59c8e839560 2795 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
AnnaBridge 163:e59c8e839560 2796 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
AnnaBridge 163:e59c8e839560 2797 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
AnnaBridge 163:e59c8e839560 2798 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
AnnaBridge 163:e59c8e839560 2799 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
AnnaBridge 163:e59c8e839560 2800 * @retval None
AnnaBridge 163:e59c8e839560 2801 */
AnnaBridge 163:e59c8e839560 2802 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
AnnaBridge 163:e59c8e839560 2803 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
AnnaBridge 163:e59c8e839560 2804
AnnaBridge 163:e59c8e839560 2805 /** @brief Enables or disables the specified HRTIM Timerx interrupts.
AnnaBridge 168:b9e159c1930a 2806 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2807 * @param __TIMER__ specified the timing unit (Timer A to E)
AnnaBridge 168:b9e159c1930a 2808 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
AnnaBridge 163:e59c8e839560 2809 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2810 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
AnnaBridge 163:e59c8e839560 2811 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
AnnaBridge 163:e59c8e839560 2812 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
AnnaBridge 163:e59c8e839560 2813 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
AnnaBridge 163:e59c8e839560 2814 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
AnnaBridge 163:e59c8e839560 2815 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
AnnaBridge 163:e59c8e839560 2816 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
AnnaBridge 163:e59c8e839560 2817 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
AnnaBridge 163:e59c8e839560 2818 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
AnnaBridge 163:e59c8e839560 2819 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
AnnaBridge 163:e59c8e839560 2820 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
AnnaBridge 163:e59c8e839560 2821 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
AnnaBridge 163:e59c8e839560 2822 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
AnnaBridge 163:e59c8e839560 2823 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
AnnaBridge 163:e59c8e839560 2824 * @retval None
AnnaBridge 163:e59c8e839560 2825 */
AnnaBridge 163:e59c8e839560 2826 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
AnnaBridge 163:e59c8e839560 2827 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
AnnaBridge 163:e59c8e839560 2828
AnnaBridge 163:e59c8e839560 2829 /** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
AnnaBridge 168:b9e159c1930a 2830 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2831 * @param __INTERRUPT__ specifies the interrupt source to check.
AnnaBridge 163:e59c8e839560 2832 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2833 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
AnnaBridge 163:e59c8e839560 2834 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
AnnaBridge 163:e59c8e839560 2835 * @arg HRTIM_IT_FLT3: Fault 3 enable
AnnaBridge 163:e59c8e839560 2836 * @arg HRTIM_IT_FLT4: Fault 4 enable
AnnaBridge 163:e59c8e839560 2837 * @arg HRTIM_IT_FLT5: Fault 5 enable
AnnaBridge 163:e59c8e839560 2838 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
AnnaBridge 163:e59c8e839560 2839 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
AnnaBridge 163:e59c8e839560 2840 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
AnnaBridge 163:e59c8e839560 2841 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 163:e59c8e839560 2842 */
AnnaBridge 163:e59c8e839560 2843 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge 163:e59c8e839560 2844
AnnaBridge 163:e59c8e839560 2845 /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
AnnaBridge 168:b9e159c1930a 2846 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2847 * @param __INTERRUPT__ specifies the interrupt source to check.
AnnaBridge 163:e59c8e839560 2848 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2849 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
AnnaBridge 163:e59c8e839560 2850 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
AnnaBridge 163:e59c8e839560 2851 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
AnnaBridge 163:e59c8e839560 2852 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
AnnaBridge 163:e59c8e839560 2853 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
AnnaBridge 163:e59c8e839560 2854 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
AnnaBridge 163:e59c8e839560 2855 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
AnnaBridge 163:e59c8e839560 2856 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 163:e59c8e839560 2857 */
AnnaBridge 163:e59c8e839560 2858 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge 163:e59c8e839560 2859
AnnaBridge 163:e59c8e839560 2860 /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
AnnaBridge 168:b9e159c1930a 2861 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2862 * @param __TIMER__ specified the timing unit (Timer A to E)
AnnaBridge 168:b9e159c1930a 2863 * @param __INTERRUPT__ specifies the interrupt source to check.
AnnaBridge 163:e59c8e839560 2864 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2865 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
AnnaBridge 163:e59c8e839560 2866 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
AnnaBridge 163:e59c8e839560 2867 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
AnnaBridge 163:e59c8e839560 2868 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
AnnaBridge 163:e59c8e839560 2869 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
AnnaBridge 163:e59c8e839560 2870 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
AnnaBridge 163:e59c8e839560 2871 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
AnnaBridge 163:e59c8e839560 2872 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
AnnaBridge 163:e59c8e839560 2873 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
AnnaBridge 163:e59c8e839560 2874 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
AnnaBridge 163:e59c8e839560 2875 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
AnnaBridge 163:e59c8e839560 2876 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
AnnaBridge 163:e59c8e839560 2877 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
AnnaBridge 163:e59c8e839560 2878 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
AnnaBridge 163:e59c8e839560 2879 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
AnnaBridge 163:e59c8e839560 2880 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
AnnaBridge 163:e59c8e839560 2881 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
AnnaBridge 163:e59c8e839560 2882 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
AnnaBridge 163:e59c8e839560 2883 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
AnnaBridge 163:e59c8e839560 2884 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
AnnaBridge 163:e59c8e839560 2885 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
AnnaBridge 163:e59c8e839560 2886 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 163:e59c8e839560 2887 */
AnnaBridge 163:e59c8e839560 2888 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge 163:e59c8e839560 2889
AnnaBridge 163:e59c8e839560 2890 /** @brief Clears the specified HRTIM common pending flag.
AnnaBridge 168:b9e159c1930a 2891 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2892 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge 163:e59c8e839560 2893 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2894 * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
AnnaBridge 163:e59c8e839560 2895 * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
AnnaBridge 163:e59c8e839560 2896 * @arg HRTIM_IT_FLT3: Fault 3 clear flag
AnnaBridge 163:e59c8e839560 2897 * @arg HRTIM_IT_FLT4: Fault 4 clear flag
AnnaBridge 163:e59c8e839560 2898 * @arg HRTIM_IT_FLT5: Fault 5 clear flag
AnnaBridge 163:e59c8e839560 2899 * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
AnnaBridge 163:e59c8e839560 2900 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
AnnaBridge 163:e59c8e839560 2901 * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
AnnaBridge 163:e59c8e839560 2902 * @retval None
AnnaBridge 163:e59c8e839560 2903 */
AnnaBridge 163:e59c8e839560 2904 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
AnnaBridge 163:e59c8e839560 2905
AnnaBridge 163:e59c8e839560 2906 /** @brief Clears the specified HRTIM Master pending flag.
AnnaBridge 168:b9e159c1930a 2907 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2908 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge 163:e59c8e839560 2909 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2910 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
AnnaBridge 163:e59c8e839560 2911 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
AnnaBridge 163:e59c8e839560 2912 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
AnnaBridge 163:e59c8e839560 2913 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
AnnaBridge 163:e59c8e839560 2914 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
AnnaBridge 163:e59c8e839560 2915 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
AnnaBridge 163:e59c8e839560 2916 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
AnnaBridge 163:e59c8e839560 2917 * @retval None
AnnaBridge 163:e59c8e839560 2918 */
AnnaBridge 163:e59c8e839560 2919 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
AnnaBridge 163:e59c8e839560 2920
AnnaBridge 163:e59c8e839560 2921 /** @brief Clears the specified HRTIM Timerx pending flag.
AnnaBridge 168:b9e159c1930a 2922 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2923 * @param __TIMER__ specified the timing unit (Timer A to E)
AnnaBridge 168:b9e159c1930a 2924 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge 163:e59c8e839560 2925 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2926 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
AnnaBridge 163:e59c8e839560 2927 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
AnnaBridge 163:e59c8e839560 2928 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
AnnaBridge 163:e59c8e839560 2929 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
AnnaBridge 163:e59c8e839560 2930 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
AnnaBridge 163:e59c8e839560 2931 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
AnnaBridge 163:e59c8e839560 2932 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
AnnaBridge 163:e59c8e839560 2933 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
AnnaBridge 163:e59c8e839560 2934 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
AnnaBridge 163:e59c8e839560 2935 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
AnnaBridge 163:e59c8e839560 2936 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
AnnaBridge 163:e59c8e839560 2937 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
AnnaBridge 163:e59c8e839560 2938 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
AnnaBridge 163:e59c8e839560 2939 * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
AnnaBridge 163:e59c8e839560 2940 * @retval None
AnnaBridge 163:e59c8e839560 2941 */
AnnaBridge 163:e59c8e839560 2942 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
AnnaBridge 163:e59c8e839560 2943
AnnaBridge 163:e59c8e839560 2944 /* DMA HANDLING */
AnnaBridge 163:e59c8e839560 2945 /** @brief Enables or disables the specified HRTIM common interrupts.
AnnaBridge 168:b9e159c1930a 2946 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2947 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
AnnaBridge 163:e59c8e839560 2948 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2949 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
AnnaBridge 163:e59c8e839560 2950 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
AnnaBridge 163:e59c8e839560 2951 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
AnnaBridge 163:e59c8e839560 2952 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
AnnaBridge 163:e59c8e839560 2953 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
AnnaBridge 163:e59c8e839560 2954 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
AnnaBridge 163:e59c8e839560 2955 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
AnnaBridge 163:e59c8e839560 2956 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
AnnaBridge 163:e59c8e839560 2957 * @retval None
AnnaBridge 163:e59c8e839560 2958 */
AnnaBridge 163:e59c8e839560 2959 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
AnnaBridge 163:e59c8e839560 2960 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
AnnaBridge 163:e59c8e839560 2961
AnnaBridge 163:e59c8e839560 2962 /** @brief Enables or disables the specified HRTIM Master timer DMA requets.
AnnaBridge 168:b9e159c1930a 2963 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2964 * @param __DMA__ specifies the DMA request to enable or disable.
AnnaBridge 163:e59c8e839560 2965 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2966 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
AnnaBridge 163:e59c8e839560 2967 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
AnnaBridge 163:e59c8e839560 2968 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
AnnaBridge 163:e59c8e839560 2969 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
AnnaBridge 163:e59c8e839560 2970 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
AnnaBridge 163:e59c8e839560 2971 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
AnnaBridge 163:e59c8e839560 2972 * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
AnnaBridge 163:e59c8e839560 2973 * @retval None
AnnaBridge 163:e59c8e839560 2974 */
AnnaBridge 163:e59c8e839560 2975 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
AnnaBridge 163:e59c8e839560 2976 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
AnnaBridge 163:e59c8e839560 2977
AnnaBridge 163:e59c8e839560 2978 /** @brief Enables or disables the specified HRTIM Timerx DMA requests.
AnnaBridge 168:b9e159c1930a 2979 * @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge 168:b9e159c1930a 2980 * @param __TIMER__ specified the timing unit (Timer A to E)
AnnaBridge 168:b9e159c1930a 2981 * @param __DMA__ specifies the DMA request to enable or disable.
AnnaBridge 163:e59c8e839560 2982 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 2983 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
AnnaBridge 163:e59c8e839560 2984 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
AnnaBridge 163:e59c8e839560 2985 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
AnnaBridge 163:e59c8e839560 2986 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
AnnaBridge 163:e59c8e839560 2987 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
AnnaBridge 163:e59c8e839560 2988 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
AnnaBridge 163:e59c8e839560 2989 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
AnnaBridge 163:e59c8e839560 2990 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
AnnaBridge 163:e59c8e839560 2991 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
AnnaBridge 163:e59c8e839560 2992 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
AnnaBridge 163:e59c8e839560 2993 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
AnnaBridge 163:e59c8e839560 2994 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
AnnaBridge 163:e59c8e839560 2995 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
AnnaBridge 163:e59c8e839560 2996 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
AnnaBridge 163:e59c8e839560 2997 * @retval None
AnnaBridge 163:e59c8e839560 2998 */
AnnaBridge 163:e59c8e839560 2999 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
AnnaBridge 163:e59c8e839560 3000 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
AnnaBridge 163:e59c8e839560 3001
AnnaBridge 163:e59c8e839560 3002 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
AnnaBridge 163:e59c8e839560 3003 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
AnnaBridge 163:e59c8e839560 3004
AnnaBridge 163:e59c8e839560 3005 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
AnnaBridge 163:e59c8e839560 3006 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
AnnaBridge 163:e59c8e839560 3007
AnnaBridge 163:e59c8e839560 3008 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
AnnaBridge 163:e59c8e839560 3009 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
AnnaBridge 163:e59c8e839560 3010
AnnaBridge 163:e59c8e839560 3011 /** @brief Sets the HRTIM timer Counter Register value on runtime
AnnaBridge 168:b9e159c1930a 3012 * @param __HANDLE__ HRTIM Handle.
AnnaBridge 168:b9e159c1930a 3013 * @param __TIMER__ HRTIM timer
AnnaBridge 163:e59c8e839560 3014 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 3015 * @arg 0x5 for master timer
AnnaBridge 163:e59c8e839560 3016 * @arg 0x0 to 0x4 for timers A to E
AnnaBridge 168:b9e159c1930a 3017 * @param __COUNTER__ specifies the Counter Register new value.
AnnaBridge 163:e59c8e839560 3018 * @retval None
AnnaBridge 163:e59c8e839560 3019 */
AnnaBridge 163:e59c8e839560 3020 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
AnnaBridge 163:e59c8e839560 3021 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
AnnaBridge 163:e59c8e839560 3022 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
AnnaBridge 163:e59c8e839560 3023
AnnaBridge 163:e59c8e839560 3024 /** @brief Gets the HRTIM timer Counter Register value on runtime
AnnaBridge 168:b9e159c1930a 3025 * @param __HANDLE__ HRTIM Handle.
AnnaBridge 168:b9e159c1930a 3026 * @param __TIMER__ HRTIM timer
AnnaBridge 163:e59c8e839560 3027 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 3028 * @arg 0x5 for master timer
AnnaBridge 163:e59c8e839560 3029 * @arg 0x0 to 0x4 for timers A to E
AnnaBridge 163:e59c8e839560 3030 * @retval HRTIM timer Counter Register value
AnnaBridge 163:e59c8e839560 3031 */
AnnaBridge 163:e59c8e839560 3032 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
AnnaBridge 163:e59c8e839560 3033 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
AnnaBridge 163:e59c8e839560 3034 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
AnnaBridge 163:e59c8e839560 3035
AnnaBridge 163:e59c8e839560 3036 /** @brief Sets the HRTIM timer Period value on runtime
AnnaBridge 168:b9e159c1930a 3037 * @param __HANDLE__ HRTIM Handle.
AnnaBridge 168:b9e159c1930a 3038 * @param __TIMER__ HRTIM timer
AnnaBridge 163:e59c8e839560 3039 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 3040 * @arg 0x5 for master timer
AnnaBridge 163:e59c8e839560 3041 * @arg 0x0 to 0x4 for timers A to E
AnnaBridge 168:b9e159c1930a 3042 * @param __PERIOD__ specifies the Period Register new value.
AnnaBridge 163:e59c8e839560 3043 * @retval None
AnnaBridge 163:e59c8e839560 3044 */
AnnaBridge 163:e59c8e839560 3045 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
AnnaBridge 163:e59c8e839560 3046 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
AnnaBridge 163:e59c8e839560 3047 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
AnnaBridge 163:e59c8e839560 3048
AnnaBridge 163:e59c8e839560 3049 /** @brief Gets the HRTIM timer Period Register value on runtime
AnnaBridge 168:b9e159c1930a 3050 * @param __HANDLE__ HRTIM Handle.
AnnaBridge 168:b9e159c1930a 3051 * @param __TIMER__ HRTIM timer
AnnaBridge 163:e59c8e839560 3052 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 3053 * @arg 0x5 for master timer
AnnaBridge 163:e59c8e839560 3054 * @arg 0x0 to 0x4 for timers A to E
AnnaBridge 163:e59c8e839560 3055 * @retval timer Period Register
AnnaBridge 163:e59c8e839560 3056 */
AnnaBridge 163:e59c8e839560 3057 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
AnnaBridge 163:e59c8e839560 3058 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
AnnaBridge 163:e59c8e839560 3059 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
AnnaBridge 163:e59c8e839560 3060
AnnaBridge 163:e59c8e839560 3061 /** @brief Sets the HRTIM timer clock prescaler value on runtime
AnnaBridge 168:b9e159c1930a 3062 * @param __HANDLE__ HRTIM Handle.
AnnaBridge 168:b9e159c1930a 3063 * @param __TIMER__ HRTIM timer
AnnaBridge 163:e59c8e839560 3064 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 3065 * @arg 0x5 for master timer
AnnaBridge 163:e59c8e839560 3066 * @arg 0x0 to 0x4 for timers A to E
AnnaBridge 168:b9e159c1930a 3067 * @param __PRESCALER__ specifies the clock prescaler new value.
AnnaBridge 163:e59c8e839560 3068 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 3069 * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
AnnaBridge 163:e59c8e839560 3070 * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
AnnaBridge 163:e59c8e839560 3071 * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
AnnaBridge 163:e59c8e839560 3072 * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
AnnaBridge 163:e59c8e839560 3073 * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
AnnaBridge 163:e59c8e839560 3074 * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
AnnaBridge 163:e59c8e839560 3075 * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
AnnaBridge 163:e59c8e839560 3076 * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
AnnaBridge 163:e59c8e839560 3077 * @retval None
AnnaBridge 163:e59c8e839560 3078 */
AnnaBridge 163:e59c8e839560 3079 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
AnnaBridge 168:b9e159c1930a 3080 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
AnnaBridge 168:b9e159c1930a 3081 (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
AnnaBridge 163:e59c8e839560 3082
AnnaBridge 163:e59c8e839560 3083 /** @brief Gets the HRTIM timer clock prescaler value on runtime
AnnaBridge 168:b9e159c1930a 3084 * @param __HANDLE__ HRTIM Handle.
AnnaBridge 168:b9e159c1930a 3085 * @param __TIMER__ HRTIM timer
AnnaBridge 163:e59c8e839560 3086 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 3087 * @arg 0x5 for master timer
AnnaBridge 163:e59c8e839560 3088 * @arg 0x0 to 0x4 for timers A to E
AnnaBridge 163:e59c8e839560 3089 * @retval timer clock prescaler value
AnnaBridge 163:e59c8e839560 3090 */
AnnaBridge 163:e59c8e839560 3091 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
AnnaBridge 163:e59c8e839560 3092 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
AnnaBridge 163:e59c8e839560 3093 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
AnnaBridge 163:e59c8e839560 3094
AnnaBridge 163:e59c8e839560 3095 /** @brief Sets the HRTIM timer Compare Register value on runtime
AnnaBridge 168:b9e159c1930a 3096 * @param __HANDLE__ HRTIM Handle.
AnnaBridge 168:b9e159c1930a 3097 * @param __TIMER__ HRTIM timer
AnnaBridge 163:e59c8e839560 3098 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 3099 * @arg 0x0 to 0x4 for timers A to E
AnnaBridge 168:b9e159c1930a 3100 * @param __COMPAREUNIT__ timer compare unit
AnnaBridge 163:e59c8e839560 3101 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 3102 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
AnnaBridge 163:e59c8e839560 3103 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
AnnaBridge 163:e59c8e839560 3104 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
AnnaBridge 163:e59c8e839560 3105 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
AnnaBridge 168:b9e159c1930a 3106 * @param __COMPARE__ specifies the Compare new value.
AnnaBridge 163:e59c8e839560 3107 * @retval None
AnnaBridge 163:e59c8e839560 3108 */
AnnaBridge 163:e59c8e839560 3109 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
AnnaBridge 163:e59c8e839560 3110 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
AnnaBridge 163:e59c8e839560 3111 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
AnnaBridge 163:e59c8e839560 3112 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
AnnaBridge 163:e59c8e839560 3113 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
AnnaBridge 163:e59c8e839560 3114 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
AnnaBridge 163:e59c8e839560 3115 : \
AnnaBridge 163:e59c8e839560 3116 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
AnnaBridge 163:e59c8e839560 3117 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
AnnaBridge 163:e59c8e839560 3118 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
AnnaBridge 163:e59c8e839560 3119 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
AnnaBridge 163:e59c8e839560 3120
AnnaBridge 163:e59c8e839560 3121 /** @brief Gets the HRTIM timer Compare Register value on runtime
AnnaBridge 168:b9e159c1930a 3122 * @param __HANDLE__ HRTIM Handle.
AnnaBridge 168:b9e159c1930a 3123 * @param __TIMER__ HRTIM timer
AnnaBridge 163:e59c8e839560 3124 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 3125 * @arg 0x0 to 0x4 for timers A to E
AnnaBridge 168:b9e159c1930a 3126 * @param __COMPAREUNIT__ timer compare unit
AnnaBridge 163:e59c8e839560 3127 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 3128 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
AnnaBridge 163:e59c8e839560 3129 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
AnnaBridge 163:e59c8e839560 3130 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
AnnaBridge 163:e59c8e839560 3131 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
AnnaBridge 163:e59c8e839560 3132 * @retval Compare value
AnnaBridge 163:e59c8e839560 3133 */
AnnaBridge 163:e59c8e839560 3134 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
AnnaBridge 163:e59c8e839560 3135 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
AnnaBridge 163:e59c8e839560 3136 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
AnnaBridge 163:e59c8e839560 3137 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
AnnaBridge 163:e59c8e839560 3138 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
AnnaBridge 163:e59c8e839560 3139 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
AnnaBridge 163:e59c8e839560 3140 : \
AnnaBridge 163:e59c8e839560 3141 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
AnnaBridge 163:e59c8e839560 3142 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
AnnaBridge 163:e59c8e839560 3143 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
AnnaBridge 163:e59c8e839560 3144 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
AnnaBridge 163:e59c8e839560 3145
AnnaBridge 163:e59c8e839560 3146 /**
AnnaBridge 163:e59c8e839560 3147 * @}
AnnaBridge 163:e59c8e839560 3148 */
AnnaBridge 163:e59c8e839560 3149
AnnaBridge 163:e59c8e839560 3150 /* Exported functions --------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 3151 /** @addtogroup HRTIM_Exported_Functions
AnnaBridge 163:e59c8e839560 3152 * @{
AnnaBridge 163:e59c8e839560 3153 */
AnnaBridge 163:e59c8e839560 3154
AnnaBridge 163:e59c8e839560 3155 /** @addtogroup HRTIM_Exported_Functions_Group1
AnnaBridge 163:e59c8e839560 3156 * @{
AnnaBridge 163:e59c8e839560 3157 */
AnnaBridge 163:e59c8e839560 3158
AnnaBridge 163:e59c8e839560 3159 /* Initialization and Configuration functions ********************************/
AnnaBridge 163:e59c8e839560 3160 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3161
AnnaBridge 163:e59c8e839560 3162 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3163
AnnaBridge 163:e59c8e839560 3164 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3165
AnnaBridge 163:e59c8e839560 3166 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3167
AnnaBridge 163:e59c8e839560 3168 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3169 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3170 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
AnnaBridge 163:e59c8e839560 3171
AnnaBridge 163:e59c8e839560 3172 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3173 uint32_t CalibrationRate);
AnnaBridge 163:e59c8e839560 3174
AnnaBridge 163:e59c8e839560 3175 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3176 uint32_t CalibrationRate);
AnnaBridge 163:e59c8e839560 3177
AnnaBridge 163:e59c8e839560 3178 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3179 uint32_t Timeout);
AnnaBridge 163:e59c8e839560 3180
AnnaBridge 163:e59c8e839560 3181 /**
AnnaBridge 163:e59c8e839560 3182 * @}
AnnaBridge 163:e59c8e839560 3183 */
AnnaBridge 163:e59c8e839560 3184
AnnaBridge 163:e59c8e839560 3185 /** @addtogroup HRTIM_Exported_Functions_Group2
AnnaBridge 163:e59c8e839560 3186 * @{
AnnaBridge 163:e59c8e839560 3187 */
AnnaBridge 163:e59c8e839560 3188
AnnaBridge 163:e59c8e839560 3189 /* Simple time base related functions *****************************************/
AnnaBridge 163:e59c8e839560 3190 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3191 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3192
AnnaBridge 163:e59c8e839560 3193 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3194 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3195
AnnaBridge 163:e59c8e839560 3196 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3197 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3198
AnnaBridge 163:e59c8e839560 3199 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3200 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3201
AnnaBridge 163:e59c8e839560 3202 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3203 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3204 uint32_t SrcAddr,
AnnaBridge 163:e59c8e839560 3205 uint32_t DestAddr,
AnnaBridge 163:e59c8e839560 3206 uint32_t Length);
AnnaBridge 163:e59c8e839560 3207
AnnaBridge 163:e59c8e839560 3208 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3209 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3210
AnnaBridge 163:e59c8e839560 3211 /**
AnnaBridge 163:e59c8e839560 3212 * @}
AnnaBridge 163:e59c8e839560 3213 */
AnnaBridge 163:e59c8e839560 3214
AnnaBridge 163:e59c8e839560 3215 /** @addtogroup HRTIM_Exported_Functions_Group3
AnnaBridge 163:e59c8e839560 3216 * @{
AnnaBridge 163:e59c8e839560 3217 */
AnnaBridge 163:e59c8e839560 3218 /* Simple output compare related functions ************************************/
AnnaBridge 163:e59c8e839560 3219 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3220 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3221 uint32_t OCChannel,
AnnaBridge 163:e59c8e839560 3222 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
AnnaBridge 163:e59c8e839560 3223
AnnaBridge 163:e59c8e839560 3224 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3225 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3226 uint32_t OCChannel);
AnnaBridge 163:e59c8e839560 3227
AnnaBridge 163:e59c8e839560 3228 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3229 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3230 uint32_t OCChannel);
AnnaBridge 163:e59c8e839560 3231
AnnaBridge 163:e59c8e839560 3232 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3233 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3234 uint32_t OCChannel);
AnnaBridge 163:e59c8e839560 3235
AnnaBridge 163:e59c8e839560 3236 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3237 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3238 uint32_t OCChannel);
AnnaBridge 163:e59c8e839560 3239
AnnaBridge 163:e59c8e839560 3240 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3241 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3242 uint32_t OCChannel,
AnnaBridge 163:e59c8e839560 3243 uint32_t SrcAddr,
AnnaBridge 163:e59c8e839560 3244 uint32_t DestAddr,
AnnaBridge 163:e59c8e839560 3245 uint32_t Length);
AnnaBridge 163:e59c8e839560 3246
AnnaBridge 163:e59c8e839560 3247 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3248 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3249 uint32_t OCChannel);
AnnaBridge 163:e59c8e839560 3250
AnnaBridge 163:e59c8e839560 3251 /**
AnnaBridge 163:e59c8e839560 3252 * @}
AnnaBridge 163:e59c8e839560 3253 */
AnnaBridge 163:e59c8e839560 3254
AnnaBridge 163:e59c8e839560 3255 /** @addtogroup HRTIM_Exported_Functions_Group4
AnnaBridge 163:e59c8e839560 3256 * @{
AnnaBridge 163:e59c8e839560 3257 */
AnnaBridge 163:e59c8e839560 3258 /* Simple PWM output related functions ****************************************/
AnnaBridge 163:e59c8e839560 3259 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3260 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3261 uint32_t PWMChannel,
AnnaBridge 163:e59c8e839560 3262 HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
AnnaBridge 163:e59c8e839560 3263
AnnaBridge 163:e59c8e839560 3264 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3265 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3266 uint32_t PWMChannel);
AnnaBridge 163:e59c8e839560 3267
AnnaBridge 163:e59c8e839560 3268 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3269 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3270 uint32_t PWMChannel);
AnnaBridge 163:e59c8e839560 3271
AnnaBridge 163:e59c8e839560 3272 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3273 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3274 uint32_t PWMChannel);
AnnaBridge 163:e59c8e839560 3275
AnnaBridge 163:e59c8e839560 3276 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3277 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3278 uint32_t PWMChannel);
AnnaBridge 163:e59c8e839560 3279
AnnaBridge 163:e59c8e839560 3280 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3281 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3282 uint32_t PWMChannel,
AnnaBridge 163:e59c8e839560 3283 uint32_t SrcAddr,
AnnaBridge 163:e59c8e839560 3284 uint32_t DestAddr,
AnnaBridge 163:e59c8e839560 3285 uint32_t Length);
AnnaBridge 163:e59c8e839560 3286
AnnaBridge 163:e59c8e839560 3287 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3288 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3289 uint32_t PWMChannel);
AnnaBridge 163:e59c8e839560 3290
AnnaBridge 163:e59c8e839560 3291 /**
AnnaBridge 163:e59c8e839560 3292 * @}
AnnaBridge 163:e59c8e839560 3293 */
AnnaBridge 163:e59c8e839560 3294
AnnaBridge 163:e59c8e839560 3295 /** @addtogroup HRTIM_Exported_Functions_Group5
AnnaBridge 163:e59c8e839560 3296 * @{
AnnaBridge 163:e59c8e839560 3297 */
AnnaBridge 163:e59c8e839560 3298 /* Simple capture related functions *******************************************/
AnnaBridge 163:e59c8e839560 3299 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3300 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3301 uint32_t CaptureChannel,
AnnaBridge 163:e59c8e839560 3302 HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
AnnaBridge 163:e59c8e839560 3303
AnnaBridge 163:e59c8e839560 3304 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3305 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3306 uint32_t CaptureChannel);
AnnaBridge 163:e59c8e839560 3307
AnnaBridge 163:e59c8e839560 3308 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3309 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3310 uint32_t CaptureChannel);
AnnaBridge 163:e59c8e839560 3311
AnnaBridge 163:e59c8e839560 3312 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3313 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3314 uint32_t CaptureChannel);
AnnaBridge 163:e59c8e839560 3315
AnnaBridge 163:e59c8e839560 3316 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3317 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3318 uint32_t CaptureChannel);
AnnaBridge 163:e59c8e839560 3319
AnnaBridge 163:e59c8e839560 3320 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3321 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3322 uint32_t CaptureChannel,
AnnaBridge 163:e59c8e839560 3323 uint32_t SrcAddr,
AnnaBridge 163:e59c8e839560 3324 uint32_t DestAddr,
AnnaBridge 163:e59c8e839560 3325 uint32_t Length);
AnnaBridge 163:e59c8e839560 3326
AnnaBridge 163:e59c8e839560 3327 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3328 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3329 uint32_t CaptureChannel);
AnnaBridge 163:e59c8e839560 3330
AnnaBridge 163:e59c8e839560 3331 /**
AnnaBridge 163:e59c8e839560 3332 * @}
AnnaBridge 163:e59c8e839560 3333 */
AnnaBridge 163:e59c8e839560 3334
AnnaBridge 163:e59c8e839560 3335 /** @addtogroup HRTIM_Exported_Functions_Group6
AnnaBridge 163:e59c8e839560 3336 * @{
AnnaBridge 163:e59c8e839560 3337 */
AnnaBridge 163:e59c8e839560 3338 /* Simple one pulse related functions *****************************************/
AnnaBridge 163:e59c8e839560 3339 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3340 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3341 uint32_t OnePulseChannel,
AnnaBridge 163:e59c8e839560 3342 HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
AnnaBridge 163:e59c8e839560 3343
AnnaBridge 163:e59c8e839560 3344 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3345 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3346 uint32_t OnePulseChannel);
AnnaBridge 163:e59c8e839560 3347
AnnaBridge 163:e59c8e839560 3348 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3349 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3350 uint32_t OnePulseChannel);
AnnaBridge 163:e59c8e839560 3351
AnnaBridge 163:e59c8e839560 3352 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3353 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3354 uint32_t OnePulseChannel);
AnnaBridge 163:e59c8e839560 3355
AnnaBridge 163:e59c8e839560 3356 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3357 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3358 uint32_t OnePulseChannel);
AnnaBridge 163:e59c8e839560 3359
AnnaBridge 163:e59c8e839560 3360 /**
AnnaBridge 163:e59c8e839560 3361 * @}
AnnaBridge 163:e59c8e839560 3362 */
AnnaBridge 163:e59c8e839560 3363
AnnaBridge 163:e59c8e839560 3364 /** @addtogroup HRTIM_Exported_Functions_Group7
AnnaBridge 163:e59c8e839560 3365 * @{
AnnaBridge 163:e59c8e839560 3366 */
AnnaBridge 163:e59c8e839560 3367 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3368 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
AnnaBridge 163:e59c8e839560 3369
AnnaBridge 163:e59c8e839560 3370 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3371 uint32_t Event,
AnnaBridge 163:e59c8e839560 3372 HRTIM_EventCfgTypeDef* pEventCfg);
AnnaBridge 163:e59c8e839560 3373
AnnaBridge 163:e59c8e839560 3374 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3375 uint32_t Prescaler);
AnnaBridge 163:e59c8e839560 3376
AnnaBridge 163:e59c8e839560 3377 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3378 uint32_t Fault,
AnnaBridge 163:e59c8e839560 3379 HRTIM_FaultCfgTypeDef* pFaultCfg);
AnnaBridge 163:e59c8e839560 3380
AnnaBridge 163:e59c8e839560 3381 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3382 uint32_t Prescaler);
AnnaBridge 163:e59c8e839560 3383
AnnaBridge 163:e59c8e839560 3384 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
AnnaBridge 163:e59c8e839560 3385 uint32_t Faults,
AnnaBridge 163:e59c8e839560 3386 uint32_t Enable);
AnnaBridge 163:e59c8e839560 3387
AnnaBridge 163:e59c8e839560 3388 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3389 uint32_t ADCTrigger,
AnnaBridge 163:e59c8e839560 3390 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
AnnaBridge 163:e59c8e839560 3391
AnnaBridge 163:e59c8e839560 3392 /**
AnnaBridge 163:e59c8e839560 3393 * @}
AnnaBridge 163:e59c8e839560 3394 */
AnnaBridge 163:e59c8e839560 3395
AnnaBridge 163:e59c8e839560 3396 /** @addtogroup HRTIM_Exported_Functions_Group8
AnnaBridge 163:e59c8e839560 3397 * @{
AnnaBridge 163:e59c8e839560 3398 */
AnnaBridge 163:e59c8e839560 3399 /* Waveform related functions *************************************************/
AnnaBridge 163:e59c8e839560 3400 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3401 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3402 HRTIM_TimerCfgTypeDef * pTimerCfg);
AnnaBridge 163:e59c8e839560 3403
AnnaBridge 163:e59c8e839560 3404 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3405 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3406 uint32_t CompareUnit,
AnnaBridge 163:e59c8e839560 3407 HRTIM_CompareCfgTypeDef* pCompareCfg);
AnnaBridge 163:e59c8e839560 3408
AnnaBridge 163:e59c8e839560 3409 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3410 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3411 uint32_t CaptureUnit,
AnnaBridge 163:e59c8e839560 3412 HRTIM_CaptureCfgTypeDef* pCaptureCfg);
AnnaBridge 163:e59c8e839560 3413
AnnaBridge 163:e59c8e839560 3414 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3415 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3416 uint32_t Output,
AnnaBridge 163:e59c8e839560 3417 HRTIM_OutputCfgTypeDef * pOutputCfg);
AnnaBridge 163:e59c8e839560 3418
AnnaBridge 163:e59c8e839560 3419 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3420 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3421 uint32_t Output,
AnnaBridge 163:e59c8e839560 3422 uint32_t OutputLevel);
AnnaBridge 163:e59c8e839560 3423
AnnaBridge 163:e59c8e839560 3424 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3425 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3426 uint32_t Event,
AnnaBridge 163:e59c8e839560 3427 HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
AnnaBridge 163:e59c8e839560 3428
AnnaBridge 163:e59c8e839560 3429 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3430 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3431 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
AnnaBridge 163:e59c8e839560 3432
AnnaBridge 163:e59c8e839560 3433 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3434 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3435 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
AnnaBridge 163:e59c8e839560 3436
AnnaBridge 163:e59c8e839560 3437 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3438 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3439 uint32_t RegistersToUpdate);
AnnaBridge 163:e59c8e839560 3440
AnnaBridge 163:e59c8e839560 3441
AnnaBridge 163:e59c8e839560 3442 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3443 uint32_t Timers);
AnnaBridge 163:e59c8e839560 3444
AnnaBridge 163:e59c8e839560 3445 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3446 uint32_t Timers);
AnnaBridge 163:e59c8e839560 3447
AnnaBridge 163:e59c8e839560 3448
AnnaBridge 163:e59c8e839560 3449 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3450 uint32_t Timers);
AnnaBridge 163:e59c8e839560 3451
AnnaBridge 163:e59c8e839560 3452 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3453 uint32_t Timers);
AnnaBridge 163:e59c8e839560 3454
AnnaBridge 163:e59c8e839560 3455
AnnaBridge 163:e59c8e839560 3456 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3457 uint32_t Timers);
AnnaBridge 163:e59c8e839560 3458
AnnaBridge 163:e59c8e839560 3459 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3460 uint32_t Timers);
AnnaBridge 163:e59c8e839560 3461
AnnaBridge 163:e59c8e839560 3462 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3463 uint32_t OutputsToStart);
AnnaBridge 163:e59c8e839560 3464
AnnaBridge 163:e59c8e839560 3465 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3466 uint32_t OutputsToStop);
AnnaBridge 163:e59c8e839560 3467
AnnaBridge 163:e59c8e839560 3468 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3469 uint32_t Enable);
AnnaBridge 163:e59c8e839560 3470
AnnaBridge 163:e59c8e839560 3471 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3472
AnnaBridge 163:e59c8e839560 3473 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3474 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3475 uint32_t CaptureUnit);
AnnaBridge 163:e59c8e839560 3476
AnnaBridge 163:e59c8e839560 3477 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3478 uint32_t Timers);
AnnaBridge 163:e59c8e839560 3479
AnnaBridge 163:e59c8e839560 3480 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3481 uint32_t Timers);
AnnaBridge 163:e59c8e839560 3482
AnnaBridge 163:e59c8e839560 3483 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3484 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3485 uint32_t BurstBufferAddress,
AnnaBridge 163:e59c8e839560 3486 uint32_t BurstBufferLength);
AnnaBridge 163:e59c8e839560 3487
AnnaBridge 163:e59c8e839560 3488 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3489 uint32_t Timers);
AnnaBridge 163:e59c8e839560 3490
AnnaBridge 163:e59c8e839560 3491 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3492 uint32_t Timers);
AnnaBridge 163:e59c8e839560 3493
AnnaBridge 163:e59c8e839560 3494 /**
AnnaBridge 163:e59c8e839560 3495 * @}
AnnaBridge 163:e59c8e839560 3496 */
AnnaBridge 163:e59c8e839560 3497
AnnaBridge 163:e59c8e839560 3498 /** @addtogroup HRTIM_Exported_Functions_Group9
AnnaBridge 163:e59c8e839560 3499 * @{
AnnaBridge 163:e59c8e839560 3500 */
AnnaBridge 163:e59c8e839560 3501 /* HRTIM peripheral state functions */
AnnaBridge 163:e59c8e839560 3502 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
AnnaBridge 163:e59c8e839560 3503
AnnaBridge 163:e59c8e839560 3504 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3505 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3506 uint32_t CaptureUnit);
AnnaBridge 163:e59c8e839560 3507
AnnaBridge 163:e59c8e839560 3508 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3509 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3510 uint32_t Output);
AnnaBridge 163:e59c8e839560 3511
AnnaBridge 163:e59c8e839560 3512 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
AnnaBridge 163:e59c8e839560 3513 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3514 uint32_t Output);
AnnaBridge 163:e59c8e839560 3515
AnnaBridge 163:e59c8e839560 3516 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3517 uint32_t TimerIdx,
AnnaBridge 163:e59c8e839560 3518 uint32_t Output);
AnnaBridge 163:e59c8e839560 3519
AnnaBridge 163:e59c8e839560 3520 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3521
AnnaBridge 163:e59c8e839560 3522 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3523 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3524
AnnaBridge 163:e59c8e839560 3525 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3526 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3527
AnnaBridge 163:e59c8e839560 3528 /**
AnnaBridge 163:e59c8e839560 3529 * @}
AnnaBridge 163:e59c8e839560 3530 */
AnnaBridge 163:e59c8e839560 3531
AnnaBridge 163:e59c8e839560 3532 /** @addtogroup HRTIM_Exported_Functions_Group10
AnnaBridge 163:e59c8e839560 3533 * @{
AnnaBridge 163:e59c8e839560 3534 */
AnnaBridge 163:e59c8e839560 3535 /* IRQ handler */
AnnaBridge 163:e59c8e839560 3536 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3537 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3538
AnnaBridge 163:e59c8e839560 3539 /* HRTIM events related callback functions */
AnnaBridge 163:e59c8e839560 3540 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3541 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3542 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3543 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3544 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3545 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3546 void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3547 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3548 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3549
AnnaBridge 163:e59c8e839560 3550 /* Timer events related callback functions */
AnnaBridge 163:e59c8e839560 3551 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3552 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3553 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3554 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3555 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3556 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3557 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3558 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3559 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3560 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3561 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3562 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3563 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3564 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3565 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3566 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3567 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3568 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3569 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3570 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3571 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3572 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3573 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3574 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3575 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3576 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3577 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3578 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3579 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge 163:e59c8e839560 3580 uint32_t TimerIdx);
AnnaBridge 163:e59c8e839560 3581 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge 163:e59c8e839560 3582
AnnaBridge 163:e59c8e839560 3583 /**
AnnaBridge 163:e59c8e839560 3584 * @}
AnnaBridge 163:e59c8e839560 3585 */
AnnaBridge 163:e59c8e839560 3586
AnnaBridge 163:e59c8e839560 3587 /**
AnnaBridge 163:e59c8e839560 3588 * @}
AnnaBridge 163:e59c8e839560 3589 */
AnnaBridge 163:e59c8e839560 3590
AnnaBridge 163:e59c8e839560 3591 /**
AnnaBridge 163:e59c8e839560 3592 * @}
AnnaBridge 163:e59c8e839560 3593 */
AnnaBridge 163:e59c8e839560 3594
AnnaBridge 163:e59c8e839560 3595 /**
AnnaBridge 163:e59c8e839560 3596 * @}
AnnaBridge 163:e59c8e839560 3597 */
AnnaBridge 163:e59c8e839560 3598
AnnaBridge 163:e59c8e839560 3599 #endif /* defined(STM32F334x8) */
AnnaBridge 163:e59c8e839560 3600
AnnaBridge 163:e59c8e839560 3601 #ifdef __cplusplus
AnnaBridge 163:e59c8e839560 3602 }
AnnaBridge 163:e59c8e839560 3603 #endif
AnnaBridge 163:e59c8e839560 3604
AnnaBridge 163:e59c8e839560 3605 #endif /* __STM32F3xx_HAL_HRTIM_H */
AnnaBridge 163:e59c8e839560 3606
AnnaBridge 163:e59c8e839560 3607 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/