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TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/stm32_hal_legacy.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32_hal_legacy.h@168:b9e159c1930a

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	163:e59c8e839560	1	/**
AnnaBridge	163:e59c8e839560	2	******************************************************************************
AnnaBridge	163:e59c8e839560	3	* @file stm32_hal_legacy.h
AnnaBridge	163:e59c8e839560	4	* @author MCD Application Team
AnnaBridge	163:e59c8e839560	5	* @brief This file contains aliases definition for the STM32Cube HAL constants
AnnaBridge	163:e59c8e839560	6	* macros and functions maintained for legacy purpose.
AnnaBridge	163:e59c8e839560	7	******************************************************************************
AnnaBridge	163:e59c8e839560	8	* @attention
AnnaBridge	163:e59c8e839560	9	*
AnnaBridge	168:b9e159c1930a	10	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	163:e59c8e839560	11	*
AnnaBridge	163:e59c8e839560	12	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	163:e59c8e839560	13	* are permitted provided that the following conditions are met:
AnnaBridge	163:e59c8e839560	14	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	163:e59c8e839560	15	* this list of conditions and the following disclaimer.
AnnaBridge	163:e59c8e839560	16	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	163:e59c8e839560	17	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	163:e59c8e839560	18	* and/or other materials provided with the distribution.
AnnaBridge	163:e59c8e839560	19	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	163:e59c8e839560	20	* may be used to endorse or promote products derived from this software
AnnaBridge	163:e59c8e839560	21	* without specific prior written permission.
AnnaBridge	163:e59c8e839560	22	*
AnnaBridge	163:e59c8e839560	23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	163:e59c8e839560	24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	163:e59c8e839560	25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	163:e59c8e839560	26	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	163:e59c8e839560	27	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	163:e59c8e839560	28	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	163:e59c8e839560	29	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	163:e59c8e839560	30	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	163:e59c8e839560	31	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	163:e59c8e839560	32	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	163:e59c8e839560	33	*
AnnaBridge	163:e59c8e839560	34	******************************************************************************
AnnaBridge	163:e59c8e839560	35	*/
AnnaBridge	163:e59c8e839560	36
AnnaBridge	163:e59c8e839560	37	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	163:e59c8e839560	38	#ifndef __STM32_HAL_LEGACY
AnnaBridge	163:e59c8e839560	39	#define __STM32_HAL_LEGACY
AnnaBridge	163:e59c8e839560	40
AnnaBridge	163:e59c8e839560	41	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	42	extern "C" {
AnnaBridge	163:e59c8e839560	43	#endif
AnnaBridge	163:e59c8e839560	44
AnnaBridge	163:e59c8e839560	45	/* Includes ------------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	46	/* Exported types ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	47	/* Exported constants --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	48
AnnaBridge	163:e59c8e839560	49	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	50	* @{
AnnaBridge	163:e59c8e839560	51	*/
AnnaBridge	163:e59c8e839560	52	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
AnnaBridge	163:e59c8e839560	53	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
AnnaBridge	163:e59c8e839560	54	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
AnnaBridge	163:e59c8e839560	55	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
AnnaBridge	163:e59c8e839560	56	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
AnnaBridge	163:e59c8e839560	57
AnnaBridge	163:e59c8e839560	58	/**
AnnaBridge	163:e59c8e839560	59	* @}
AnnaBridge	163:e59c8e839560	60	*/
AnnaBridge	163:e59c8e839560	61
AnnaBridge	163:e59c8e839560	62	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	63	* @{
AnnaBridge	163:e59c8e839560	64	*/
AnnaBridge	163:e59c8e839560	65	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
AnnaBridge	163:e59c8e839560	66	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
AnnaBridge	163:e59c8e839560	67	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
AnnaBridge	163:e59c8e839560	68	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
AnnaBridge	163:e59c8e839560	69	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
AnnaBridge	163:e59c8e839560	70	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
AnnaBridge	163:e59c8e839560	71	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
AnnaBridge	163:e59c8e839560	72	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
AnnaBridge	163:e59c8e839560	73	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
AnnaBridge	163:e59c8e839560	74	#define REGULAR_GROUP ADC_REGULAR_GROUP
AnnaBridge	163:e59c8e839560	75	#define INJECTED_GROUP ADC_INJECTED_GROUP
AnnaBridge	163:e59c8e839560	76	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
AnnaBridge	163:e59c8e839560	77	#define AWD_EVENT ADC_AWD_EVENT
AnnaBridge	163:e59c8e839560	78	#define AWD1_EVENT ADC_AWD1_EVENT
AnnaBridge	163:e59c8e839560	79	#define AWD2_EVENT ADC_AWD2_EVENT
AnnaBridge	163:e59c8e839560	80	#define AWD3_EVENT ADC_AWD3_EVENT
AnnaBridge	163:e59c8e839560	81	#define OVR_EVENT ADC_OVR_EVENT
AnnaBridge	163:e59c8e839560	82	#define JQOVF_EVENT ADC_JQOVF_EVENT
AnnaBridge	163:e59c8e839560	83	#define ALL_CHANNELS ADC_ALL_CHANNELS
AnnaBridge	163:e59c8e839560	84	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
AnnaBridge	163:e59c8e839560	85	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
AnnaBridge	163:e59c8e839560	86	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
AnnaBridge	163:e59c8e839560	87	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
AnnaBridge	163:e59c8e839560	88	#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
AnnaBridge	163:e59c8e839560	89	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
AnnaBridge	163:e59c8e839560	90	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
AnnaBridge	163:e59c8e839560	91	#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
AnnaBridge	163:e59c8e839560	92	#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
AnnaBridge	163:e59c8e839560	93	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
AnnaBridge	163:e59c8e839560	94	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
AnnaBridge	163:e59c8e839560	95	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
AnnaBridge	163:e59c8e839560	96	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
AnnaBridge	163:e59c8e839560	97	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
AnnaBridge	163:e59c8e839560	98	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
AnnaBridge	163:e59c8e839560	99	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
AnnaBridge	163:e59c8e839560	100	#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
AnnaBridge	163:e59c8e839560	101	#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
AnnaBridge	163:e59c8e839560	102	#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
AnnaBridge	163:e59c8e839560	103	#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
AnnaBridge	163:e59c8e839560	104	#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
AnnaBridge	163:e59c8e839560	105
AnnaBridge	163:e59c8e839560	106	#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
AnnaBridge	163:e59c8e839560	107	#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
AnnaBridge	163:e59c8e839560	108	#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
AnnaBridge	163:e59c8e839560	109	#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
AnnaBridge	163:e59c8e839560	110	#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
AnnaBridge	163:e59c8e839560	111	#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
AnnaBridge	163:e59c8e839560	112	#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
AnnaBridge	163:e59c8e839560	113	/**
AnnaBridge	163:e59c8e839560	114	* @}
AnnaBridge	163:e59c8e839560	115	*/
AnnaBridge	163:e59c8e839560	116
AnnaBridge	163:e59c8e839560	117	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	118	* @{
AnnaBridge	163:e59c8e839560	119	*/
AnnaBridge	163:e59c8e839560	120
AnnaBridge	163:e59c8e839560	121	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
AnnaBridge	163:e59c8e839560	122
AnnaBridge	163:e59c8e839560	123	/**
AnnaBridge	163:e59c8e839560	124	* @}
AnnaBridge	163:e59c8e839560	125	*/
AnnaBridge	163:e59c8e839560	126
AnnaBridge	163:e59c8e839560	127	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	128	* @{
AnnaBridge	163:e59c8e839560	129	*/
AnnaBridge	163:e59c8e839560	130	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
AnnaBridge	163:e59c8e839560	131	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
AnnaBridge	163:e59c8e839560	132	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
AnnaBridge	163:e59c8e839560	133	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
AnnaBridge	163:e59c8e839560	134	#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
AnnaBridge	163:e59c8e839560	135	#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
AnnaBridge	163:e59c8e839560	136	#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
AnnaBridge	163:e59c8e839560	137	#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
AnnaBridge	163:e59c8e839560	138	#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
AnnaBridge	163:e59c8e839560	139	#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /!< COMPX output is connected to LPTIM input 1 /
AnnaBridge	163:e59c8e839560	140	#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
AnnaBridge	163:e59c8e839560	141	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	142	#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
AnnaBridge	163:e59c8e839560	143	#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
AnnaBridge	163:e59c8e839560	144	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	163:e59c8e839560	145
AnnaBridge	163:e59c8e839560	146	#if defined(STM32L0) \|\| defined(STM32L4)
AnnaBridge	163:e59c8e839560	147	#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
AnnaBridge	163:e59c8e839560	148
AnnaBridge	163:e59c8e839560	149	#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
AnnaBridge	163:e59c8e839560	150	#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
AnnaBridge	163:e59c8e839560	151	#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
AnnaBridge	163:e59c8e839560	152	#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
AnnaBridge	163:e59c8e839560	153	#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
AnnaBridge	163:e59c8e839560	154	#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
AnnaBridge	163:e59c8e839560	155
AnnaBridge	163:e59c8e839560	156	#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
AnnaBridge	163:e59c8e839560	157	#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
AnnaBridge	163:e59c8e839560	158	#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
AnnaBridge	163:e59c8e839560	159	#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
AnnaBridge	163:e59c8e839560	160	#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
AnnaBridge	163:e59c8e839560	161	#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge	163:e59c8e839560	162	#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
AnnaBridge	163:e59c8e839560	163	#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge	163:e59c8e839560	164	#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
AnnaBridge	163:e59c8e839560	165	#if defined(STM32L0)
AnnaBridge	163:e59c8e839560	166	/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
AnnaBridge	163:e59c8e839560	167	/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
AnnaBridge	163:e59c8e839560	168	/* to the second dedicated IO (only for COMP2). */
AnnaBridge	163:e59c8e839560	169	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge	163:e59c8e839560	170	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
AnnaBridge	163:e59c8e839560	171	#else
AnnaBridge	163:e59c8e839560	172	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
AnnaBridge	163:e59c8e839560	173	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
AnnaBridge	163:e59c8e839560	174	#endif
AnnaBridge	163:e59c8e839560	175	#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
AnnaBridge	163:e59c8e839560	176	#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
AnnaBridge	163:e59c8e839560	177
AnnaBridge	163:e59c8e839560	178	#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
AnnaBridge	163:e59c8e839560	179	#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
AnnaBridge	163:e59c8e839560	180
AnnaBridge	163:e59c8e839560	181	/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
AnnaBridge	163:e59c8e839560	182	/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
AnnaBridge	163:e59c8e839560	183	#if defined(COMP_CSR_LOCK)
AnnaBridge	163:e59c8e839560	184	#define COMP_FLAG_LOCK COMP_CSR_LOCK
AnnaBridge	163:e59c8e839560	185	#elif defined(COMP_CSR_COMP1LOCK)
AnnaBridge	163:e59c8e839560	186	#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
AnnaBridge	163:e59c8e839560	187	#elif defined(COMP_CSR_COMPxLOCK)
AnnaBridge	163:e59c8e839560	188	#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
AnnaBridge	163:e59c8e839560	189	#endif
AnnaBridge	163:e59c8e839560	190
AnnaBridge	163:e59c8e839560	191	#if defined(STM32L4)
AnnaBridge	163:e59c8e839560	192	#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
AnnaBridge	163:e59c8e839560	193	#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
AnnaBridge	163:e59c8e839560	194	#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
AnnaBridge	163:e59c8e839560	195	#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
AnnaBridge	163:e59c8e839560	196	#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
AnnaBridge	163:e59c8e839560	197	#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
AnnaBridge	163:e59c8e839560	198	#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
AnnaBridge	163:e59c8e839560	199	#endif
AnnaBridge	163:e59c8e839560	200
AnnaBridge	163:e59c8e839560	201	#if defined(STM32L0)
AnnaBridge	163:e59c8e839560	202	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
AnnaBridge	163:e59c8e839560	203	#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
AnnaBridge	163:e59c8e839560	204	#else
AnnaBridge	163:e59c8e839560	205	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
AnnaBridge	163:e59c8e839560	206	#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
AnnaBridge	163:e59c8e839560	207	#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
AnnaBridge	163:e59c8e839560	208	#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
AnnaBridge	163:e59c8e839560	209	#endif
AnnaBridge	163:e59c8e839560	210
AnnaBridge	163:e59c8e839560	211	#endif
AnnaBridge	163:e59c8e839560	212	/**
AnnaBridge	163:e59c8e839560	213	* @}
AnnaBridge	163:e59c8e839560	214	*/
AnnaBridge	163:e59c8e839560	215
AnnaBridge	163:e59c8e839560	216	/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	217	* @{
AnnaBridge	163:e59c8e839560	218	*/
AnnaBridge	163:e59c8e839560	219	#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
AnnaBridge	163:e59c8e839560	220	/**
AnnaBridge	163:e59c8e839560	221	* @}
AnnaBridge	163:e59c8e839560	222	*/
AnnaBridge	163:e59c8e839560	223
AnnaBridge	163:e59c8e839560	224	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	225	* @{
AnnaBridge	163:e59c8e839560	226	*/
AnnaBridge	163:e59c8e839560	227
AnnaBridge	163:e59c8e839560	228	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
AnnaBridge	163:e59c8e839560	229	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
AnnaBridge	163:e59c8e839560	230
AnnaBridge	163:e59c8e839560	231	/**
AnnaBridge	163:e59c8e839560	232	* @}
AnnaBridge	163:e59c8e839560	233	*/
AnnaBridge	163:e59c8e839560	234
AnnaBridge	163:e59c8e839560	235	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	236	* @{
AnnaBridge	163:e59c8e839560	237	*/
AnnaBridge	163:e59c8e839560	238
AnnaBridge	163:e59c8e839560	239	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
AnnaBridge	163:e59c8e839560	240	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
AnnaBridge	163:e59c8e839560	241	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
AnnaBridge	163:e59c8e839560	242	#define DAC_WAVE_NONE 0x00000000U
AnnaBridge	163:e59c8e839560	243	#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
AnnaBridge	163:e59c8e839560	244	#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
AnnaBridge	163:e59c8e839560	245	#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
AnnaBridge	163:e59c8e839560	246	#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
AnnaBridge	163:e59c8e839560	247	#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
AnnaBridge	163:e59c8e839560	248
AnnaBridge	163:e59c8e839560	249	/**
AnnaBridge	163:e59c8e839560	250	* @}
AnnaBridge	163:e59c8e839560	251	*/
AnnaBridge	163:e59c8e839560	252
AnnaBridge	163:e59c8e839560	253	/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	254	* @{
AnnaBridge	163:e59c8e839560	255	*/
AnnaBridge	163:e59c8e839560	256	#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
AnnaBridge	163:e59c8e839560	257	#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
AnnaBridge	163:e59c8e839560	258	#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
AnnaBridge	163:e59c8e839560	259	#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
AnnaBridge	163:e59c8e839560	260	#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
AnnaBridge	163:e59c8e839560	261	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
AnnaBridge	163:e59c8e839560	262	#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
AnnaBridge	163:e59c8e839560	263	#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
AnnaBridge	163:e59c8e839560	264	#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
AnnaBridge	163:e59c8e839560	265	#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
AnnaBridge	163:e59c8e839560	266	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
AnnaBridge	163:e59c8e839560	267	#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
AnnaBridge	163:e59c8e839560	268	#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
AnnaBridge	163:e59c8e839560	269	#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
AnnaBridge	163:e59c8e839560	270	#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
AnnaBridge	163:e59c8e839560	271
AnnaBridge	163:e59c8e839560	272	#define IS_HAL_REMAPDMA IS_DMA_REMAP
AnnaBridge	163:e59c8e839560	273	#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
AnnaBridge	163:e59c8e839560	274	#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
AnnaBridge	163:e59c8e839560	275
AnnaBridge	163:e59c8e839560	276
AnnaBridge	163:e59c8e839560	277
AnnaBridge	163:e59c8e839560	278	/**
AnnaBridge	163:e59c8e839560	279	* @}
AnnaBridge	163:e59c8e839560	280	*/
AnnaBridge	163:e59c8e839560	281
AnnaBridge	163:e59c8e839560	282	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	283	* @{
AnnaBridge	163:e59c8e839560	284	*/
AnnaBridge	163:e59c8e839560	285
AnnaBridge	163:e59c8e839560	286	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
AnnaBridge	163:e59c8e839560	287	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
AnnaBridge	163:e59c8e839560	288	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
AnnaBridge	163:e59c8e839560	289	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
AnnaBridge	163:e59c8e839560	290	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
AnnaBridge	163:e59c8e839560	291	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
AnnaBridge	163:e59c8e839560	292	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
AnnaBridge	163:e59c8e839560	293	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
AnnaBridge	163:e59c8e839560	294	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
AnnaBridge	163:e59c8e839560	295	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
AnnaBridge	163:e59c8e839560	296	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
AnnaBridge	163:e59c8e839560	297	#define OBEX_PCROP OPTIONBYTE_PCROP
AnnaBridge	163:e59c8e839560	298	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
AnnaBridge	163:e59c8e839560	299	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
AnnaBridge	163:e59c8e839560	300	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
AnnaBridge	163:e59c8e839560	301	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
AnnaBridge	163:e59c8e839560	302	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
AnnaBridge	163:e59c8e839560	303	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
AnnaBridge	163:e59c8e839560	304	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
AnnaBridge	163:e59c8e839560	305	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
AnnaBridge	163:e59c8e839560	306	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
AnnaBridge	163:e59c8e839560	307	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
AnnaBridge	163:e59c8e839560	308	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
AnnaBridge	163:e59c8e839560	309	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
AnnaBridge	163:e59c8e839560	310	#define PAGESIZE FLASH_PAGE_SIZE
AnnaBridge	163:e59c8e839560	311	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
AnnaBridge	163:e59c8e839560	312	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
AnnaBridge	163:e59c8e839560	313	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
AnnaBridge	163:e59c8e839560	314	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
AnnaBridge	163:e59c8e839560	315	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
AnnaBridge	163:e59c8e839560	316	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
AnnaBridge	163:e59c8e839560	317	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
AnnaBridge	163:e59c8e839560	318	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
AnnaBridge	163:e59c8e839560	319	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
AnnaBridge	163:e59c8e839560	320	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
AnnaBridge	163:e59c8e839560	321	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
AnnaBridge	163:e59c8e839560	322	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
AnnaBridge	163:e59c8e839560	323	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
AnnaBridge	163:e59c8e839560	324	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
AnnaBridge	163:e59c8e839560	325	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
AnnaBridge	163:e59c8e839560	326	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
AnnaBridge	163:e59c8e839560	327	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
AnnaBridge	163:e59c8e839560	328	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
AnnaBridge	163:e59c8e839560	329	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
AnnaBridge	163:e59c8e839560	330	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
AnnaBridge	163:e59c8e839560	331	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
AnnaBridge	163:e59c8e839560	332	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
AnnaBridge	163:e59c8e839560	333	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
AnnaBridge	163:e59c8e839560	334	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
AnnaBridge	163:e59c8e839560	335	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
AnnaBridge	163:e59c8e839560	336	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
AnnaBridge	163:e59c8e839560	337	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
AnnaBridge	163:e59c8e839560	338	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
AnnaBridge	163:e59c8e839560	339	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
AnnaBridge	163:e59c8e839560	340	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
AnnaBridge	163:e59c8e839560	341	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
AnnaBridge	163:e59c8e839560	342	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
AnnaBridge	163:e59c8e839560	343	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
AnnaBridge	163:e59c8e839560	344	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
AnnaBridge	163:e59c8e839560	345	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
AnnaBridge	163:e59c8e839560	346	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
AnnaBridge	163:e59c8e839560	347	#define OB_WDG_SW OB_IWDG_SW
AnnaBridge	163:e59c8e839560	348	#define OB_WDG_HW OB_IWDG_HW
AnnaBridge	163:e59c8e839560	349	#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
AnnaBridge	163:e59c8e839560	350	#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
AnnaBridge	163:e59c8e839560	351	#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
AnnaBridge	163:e59c8e839560	352	#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
AnnaBridge	163:e59c8e839560	353	#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
AnnaBridge	163:e59c8e839560	354	#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
AnnaBridge	163:e59c8e839560	355	#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
AnnaBridge	163:e59c8e839560	356	#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
AnnaBridge	163:e59c8e839560	357
AnnaBridge	163:e59c8e839560	358	/**
AnnaBridge	163:e59c8e839560	359	* @}
AnnaBridge	163:e59c8e839560	360	*/
AnnaBridge	163:e59c8e839560	361
AnnaBridge	163:e59c8e839560	362	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	363	* @{
AnnaBridge	163:e59c8e839560	364	*/
AnnaBridge	163:e59c8e839560	365
AnnaBridge	163:e59c8e839560	366	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
AnnaBridge	163:e59c8e839560	367	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
AnnaBridge	163:e59c8e839560	368	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
AnnaBridge	163:e59c8e839560	369	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
AnnaBridge	163:e59c8e839560	370	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
AnnaBridge	163:e59c8e839560	371	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
AnnaBridge	163:e59c8e839560	372	#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
AnnaBridge	163:e59c8e839560	373	#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
AnnaBridge	163:e59c8e839560	374	#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
AnnaBridge	163:e59c8e839560	375	/**
AnnaBridge	163:e59c8e839560	376	* @}
AnnaBridge	163:e59c8e839560	377	*/
AnnaBridge	163:e59c8e839560	378
AnnaBridge	163:e59c8e839560	379
AnnaBridge	163:e59c8e839560	380	/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
AnnaBridge	163:e59c8e839560	381	* @{
AnnaBridge	163:e59c8e839560	382	*/
AnnaBridge	168:b9e159c1930a	383	#if defined(STM32L4) \|\| defined(STM32F7) \|\| defined(STM32H7)
AnnaBridge	163:e59c8e839560	384	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
AnnaBridge	163:e59c8e839560	385	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
AnnaBridge	163:e59c8e839560	386	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
AnnaBridge	163:e59c8e839560	387	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
AnnaBridge	163:e59c8e839560	388	#else
AnnaBridge	163:e59c8e839560	389	#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
AnnaBridge	163:e59c8e839560	390	#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
AnnaBridge	163:e59c8e839560	391	#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
AnnaBridge	163:e59c8e839560	392	#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
AnnaBridge	163:e59c8e839560	393	#endif
AnnaBridge	163:e59c8e839560	394	/**
AnnaBridge	163:e59c8e839560	395	* @}
AnnaBridge	163:e59c8e839560	396	*/
AnnaBridge	163:e59c8e839560	397
AnnaBridge	163:e59c8e839560	398	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	399	* @{
AnnaBridge	163:e59c8e839560	400	*/
AnnaBridge	163:e59c8e839560	401
AnnaBridge	163:e59c8e839560	402	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
AnnaBridge	163:e59c8e839560	403	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
AnnaBridge	163:e59c8e839560	404	/**
AnnaBridge	163:e59c8e839560	405	* @}
AnnaBridge	163:e59c8e839560	406	*/
AnnaBridge	163:e59c8e839560	407
AnnaBridge	163:e59c8e839560	408	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	409	* @{
AnnaBridge	163:e59c8e839560	410	*/
AnnaBridge	163:e59c8e839560	411	#define GET_GPIO_SOURCE GPIO_GET_INDEX
AnnaBridge	163:e59c8e839560	412	#define GET_GPIO_INDEX GPIO_GET_INDEX
AnnaBridge	163:e59c8e839560	413
AnnaBridge	163:e59c8e839560	414	#if defined(STM32F4)
AnnaBridge	163:e59c8e839560	415	#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
AnnaBridge	163:e59c8e839560	416	#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
AnnaBridge	163:e59c8e839560	417	#endif
AnnaBridge	163:e59c8e839560	418
AnnaBridge	163:e59c8e839560	419	#if defined(STM32F7)
AnnaBridge	163:e59c8e839560	420	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
AnnaBridge	163:e59c8e839560	421	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
AnnaBridge	163:e59c8e839560	422	#endif
AnnaBridge	163:e59c8e839560	423
AnnaBridge	163:e59c8e839560	424	#if defined(STM32L4)
AnnaBridge	163:e59c8e839560	425	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
AnnaBridge	163:e59c8e839560	426	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
AnnaBridge	163:e59c8e839560	427	#endif
AnnaBridge	163:e59c8e839560	428
AnnaBridge	163:e59c8e839560	429	#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
AnnaBridge	163:e59c8e839560	430	#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
AnnaBridge	163:e59c8e839560	431	#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
AnnaBridge	163:e59c8e839560	432
AnnaBridge	163:e59c8e839560	433	#if defined(STM32L0) \|\| defined(STM32L4) \|\| defined(STM32F4) \|\| defined(STM32F2) \|\| defined(STM32F7)
AnnaBridge	163:e59c8e839560	434	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge	163:e59c8e839560	435	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
AnnaBridge	163:e59c8e839560	436	#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
AnnaBridge	163:e59c8e839560	437	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
AnnaBridge	163:e59c8e839560	438	#endif /* STM32L0 \|\| STM32L4 \|\| STM32F4 \|\| STM32F2 \|\| STM32F7 */
AnnaBridge	163:e59c8e839560	439
AnnaBridge	163:e59c8e839560	440	#if defined(STM32L1)
AnnaBridge	163:e59c8e839560	441	#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge	163:e59c8e839560	442	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
AnnaBridge	163:e59c8e839560	443	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
AnnaBridge	163:e59c8e839560	444	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
AnnaBridge	163:e59c8e839560	445	#endif /* STM32L1 */
AnnaBridge	163:e59c8e839560	446
AnnaBridge	163:e59c8e839560	447	#if defined(STM32F0) \|\| defined(STM32F3) \|\| defined(STM32F1)
AnnaBridge	163:e59c8e839560	448	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge	163:e59c8e839560	449	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
AnnaBridge	163:e59c8e839560	450	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
AnnaBridge	163:e59c8e839560	451	#endif /* STM32F0 \|\| STM32F3 \|\| STM32F1 */
AnnaBridge	163:e59c8e839560	452
AnnaBridge	163:e59c8e839560	453	#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
AnnaBridge	163:e59c8e839560	454	/**
AnnaBridge	163:e59c8e839560	455	* @}
AnnaBridge	163:e59c8e839560	456	*/
AnnaBridge	163:e59c8e839560	457
AnnaBridge	163:e59c8e839560	458	/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	459	* @{
AnnaBridge	163:e59c8e839560	460	*/
AnnaBridge	163:e59c8e839560	461	#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
AnnaBridge	163:e59c8e839560	462	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
AnnaBridge	163:e59c8e839560	463	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
AnnaBridge	163:e59c8e839560	464	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
AnnaBridge	163:e59c8e839560	465	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
AnnaBridge	163:e59c8e839560	466	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
AnnaBridge	163:e59c8e839560	467	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
AnnaBridge	163:e59c8e839560	468	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
AnnaBridge	163:e59c8e839560	469	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
AnnaBridge	163:e59c8e839560	470
AnnaBridge	163:e59c8e839560	471	#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
AnnaBridge	163:e59c8e839560	472	#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
AnnaBridge	163:e59c8e839560	473	#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
AnnaBridge	163:e59c8e839560	474	#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
AnnaBridge	163:e59c8e839560	475	#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
AnnaBridge	163:e59c8e839560	476	#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
AnnaBridge	163:e59c8e839560	477	#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
AnnaBridge	163:e59c8e839560	478	#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
AnnaBridge	163:e59c8e839560	479	/**
AnnaBridge	163:e59c8e839560	480	* @}
AnnaBridge	163:e59c8e839560	481	*/
AnnaBridge	163:e59c8e839560	482
AnnaBridge	163:e59c8e839560	483	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	484	* @{
AnnaBridge	163:e59c8e839560	485	*/
AnnaBridge	163:e59c8e839560	486	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
AnnaBridge	163:e59c8e839560	487	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
AnnaBridge	163:e59c8e839560	488	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
AnnaBridge	163:e59c8e839560	489	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
AnnaBridge	163:e59c8e839560	490	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
AnnaBridge	163:e59c8e839560	491	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
AnnaBridge	163:e59c8e839560	492	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
AnnaBridge	163:e59c8e839560	493	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
AnnaBridge	163:e59c8e839560	494	#if defined(STM32F0) \|\| defined(STM32F1) \|\| defined(STM32F3) \|\| defined(STM32G0) \|\| defined(STM32L4) \|\| defined(STM32L1) \|\| defined(STM32F7)
AnnaBridge	163:e59c8e839560	495	#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge	163:e59c8e839560	496	#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge	163:e59c8e839560	497	#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge	163:e59c8e839560	498	#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge	163:e59c8e839560	499	#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge	163:e59c8e839560	500	#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge	163:e59c8e839560	501	#endif
AnnaBridge	163:e59c8e839560	502	/**
AnnaBridge	163:e59c8e839560	503	* @}
AnnaBridge	163:e59c8e839560	504	*/
AnnaBridge	163:e59c8e839560	505
AnnaBridge	163:e59c8e839560	506	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	507	* @{
AnnaBridge	163:e59c8e839560	508	*/
AnnaBridge	163:e59c8e839560	509	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	163:e59c8e839560	510	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	163:e59c8e839560	511
AnnaBridge	163:e59c8e839560	512	/**
AnnaBridge	163:e59c8e839560	513	* @}
AnnaBridge	163:e59c8e839560	514	*/
AnnaBridge	163:e59c8e839560	515
AnnaBridge	163:e59c8e839560	516	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	517	* @{
AnnaBridge	163:e59c8e839560	518	*/
AnnaBridge	163:e59c8e839560	519	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
AnnaBridge	163:e59c8e839560	520	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
AnnaBridge	163:e59c8e839560	521	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
AnnaBridge	163:e59c8e839560	522	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
AnnaBridge	163:e59c8e839560	523	/**
AnnaBridge	163:e59c8e839560	524	* @}
AnnaBridge	163:e59c8e839560	525	*/
AnnaBridge	163:e59c8e839560	526
AnnaBridge	163:e59c8e839560	527	/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	528	* @{
AnnaBridge	163:e59c8e839560	529	*/
AnnaBridge	163:e59c8e839560	530
AnnaBridge	163:e59c8e839560	531	#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
AnnaBridge	163:e59c8e839560	532	#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
AnnaBridge	163:e59c8e839560	533	#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
AnnaBridge	163:e59c8e839560	534	#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
AnnaBridge	163:e59c8e839560	535
AnnaBridge	163:e59c8e839560	536	#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
AnnaBridge	163:e59c8e839560	537	#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
AnnaBridge	163:e59c8e839560	538	#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
AnnaBridge	163:e59c8e839560	539
AnnaBridge	163:e59c8e839560	540	#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
AnnaBridge	163:e59c8e839560	541	#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
AnnaBridge	163:e59c8e839560	542	#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
AnnaBridge	163:e59c8e839560	543	#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
AnnaBridge	163:e59c8e839560	544
AnnaBridge	163:e59c8e839560	545	/* The following 3 definition have also been present in a temporary version of lptim.h */
AnnaBridge	163:e59c8e839560	546	/* They need to be renamed also to the right name, just in case */
AnnaBridge	163:e59c8e839560	547	#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
AnnaBridge	163:e59c8e839560	548	#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
AnnaBridge	163:e59c8e839560	549	#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
AnnaBridge	163:e59c8e839560	550
AnnaBridge	163:e59c8e839560	551	/**
AnnaBridge	163:e59c8e839560	552	* @}
AnnaBridge	163:e59c8e839560	553	*/
AnnaBridge	163:e59c8e839560	554
AnnaBridge	163:e59c8e839560	555	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	556	* @{
AnnaBridge	163:e59c8e839560	557	*/
AnnaBridge	163:e59c8e839560	558	#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
AnnaBridge	163:e59c8e839560	559	#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
AnnaBridge	163:e59c8e839560	560	#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
AnnaBridge	163:e59c8e839560	561	#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
AnnaBridge	163:e59c8e839560	562
AnnaBridge	163:e59c8e839560	563	#define NAND_AddressTypedef NAND_AddressTypeDef
AnnaBridge	163:e59c8e839560	564
AnnaBridge	163:e59c8e839560	565	#define __ARRAY_ADDRESS ARRAY_ADDRESS
AnnaBridge	163:e59c8e839560	566	#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
AnnaBridge	163:e59c8e839560	567	#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
AnnaBridge	163:e59c8e839560	568	#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
AnnaBridge	163:e59c8e839560	569	#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
AnnaBridge	163:e59c8e839560	570	/**
AnnaBridge	163:e59c8e839560	571	* @}
AnnaBridge	163:e59c8e839560	572	*/
AnnaBridge	163:e59c8e839560	573
AnnaBridge	163:e59c8e839560	574	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	575	* @{
AnnaBridge	163:e59c8e839560	576	*/
AnnaBridge	163:e59c8e839560	577	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
AnnaBridge	163:e59c8e839560	578	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
AnnaBridge	163:e59c8e839560	579	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
AnnaBridge	163:e59c8e839560	580	#define NOR_ERROR HAL_NOR_STATUS_ERROR
AnnaBridge	163:e59c8e839560	581	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
AnnaBridge	163:e59c8e839560	582
AnnaBridge	163:e59c8e839560	583	#define __NOR_WRITE NOR_WRITE
AnnaBridge	163:e59c8e839560	584	#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
AnnaBridge	163:e59c8e839560	585	/**
AnnaBridge	163:e59c8e839560	586	* @}
AnnaBridge	163:e59c8e839560	587	*/
AnnaBridge	163:e59c8e839560	588
AnnaBridge	163:e59c8e839560	589	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	590	* @{
AnnaBridge	163:e59c8e839560	591	*/
AnnaBridge	163:e59c8e839560	592
AnnaBridge	163:e59c8e839560	593	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
AnnaBridge	163:e59c8e839560	594	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
AnnaBridge	163:e59c8e839560	595	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
AnnaBridge	163:e59c8e839560	596	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
AnnaBridge	163:e59c8e839560	597
AnnaBridge	163:e59c8e839560	598	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
AnnaBridge	163:e59c8e839560	599	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
AnnaBridge	163:e59c8e839560	600	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
AnnaBridge	163:e59c8e839560	601	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
AnnaBridge	163:e59c8e839560	602
AnnaBridge	163:e59c8e839560	603	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
AnnaBridge	163:e59c8e839560	604	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
AnnaBridge	163:e59c8e839560	605
AnnaBridge	163:e59c8e839560	606	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
AnnaBridge	163:e59c8e839560	607	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
AnnaBridge	163:e59c8e839560	608
AnnaBridge	163:e59c8e839560	609	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
AnnaBridge	163:e59c8e839560	610	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
AnnaBridge	163:e59c8e839560	611
AnnaBridge	163:e59c8e839560	612	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
AnnaBridge	163:e59c8e839560	613
AnnaBridge	163:e59c8e839560	614	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
AnnaBridge	163:e59c8e839560	615	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
AnnaBridge	163:e59c8e839560	616	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
AnnaBridge	163:e59c8e839560	617
AnnaBridge	163:e59c8e839560	618	/**
AnnaBridge	163:e59c8e839560	619	* @}
AnnaBridge	163:e59c8e839560	620	*/
AnnaBridge	163:e59c8e839560	621
AnnaBridge	163:e59c8e839560	622	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	623	* @{
AnnaBridge	163:e59c8e839560	624	*/
AnnaBridge	163:e59c8e839560	625	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
AnnaBridge	163:e59c8e839560	626	#if defined(STM32F7)
AnnaBridge	163:e59c8e839560	627	#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
AnnaBridge	163:e59c8e839560	628	#endif
AnnaBridge	163:e59c8e839560	629	/**
AnnaBridge	163:e59c8e839560	630	* @}
AnnaBridge	163:e59c8e839560	631	*/
AnnaBridge	163:e59c8e839560	632
AnnaBridge	163:e59c8e839560	633	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	634	* @{
AnnaBridge	163:e59c8e839560	635	*/
AnnaBridge	163:e59c8e839560	636
AnnaBridge	163:e59c8e839560	637	/* Compact Flash-ATA registers description */
AnnaBridge	163:e59c8e839560	638	#define CF_DATA ATA_DATA
AnnaBridge	163:e59c8e839560	639	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
AnnaBridge	163:e59c8e839560	640	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
AnnaBridge	163:e59c8e839560	641	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
AnnaBridge	163:e59c8e839560	642	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
AnnaBridge	163:e59c8e839560	643	#define CF_CARD_HEAD ATA_CARD_HEAD
AnnaBridge	163:e59c8e839560	644	#define CF_STATUS_CMD ATA_STATUS_CMD
AnnaBridge	163:e59c8e839560	645	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
AnnaBridge	163:e59c8e839560	646	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
AnnaBridge	163:e59c8e839560	647
AnnaBridge	163:e59c8e839560	648	/* Compact Flash-ATA commands */
AnnaBridge	163:e59c8e839560	649	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
AnnaBridge	163:e59c8e839560	650	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
AnnaBridge	163:e59c8e839560	651	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
AnnaBridge	163:e59c8e839560	652	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
AnnaBridge	163:e59c8e839560	653
AnnaBridge	163:e59c8e839560	654	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
AnnaBridge	163:e59c8e839560	655	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
AnnaBridge	163:e59c8e839560	656	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
AnnaBridge	163:e59c8e839560	657	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
AnnaBridge	163:e59c8e839560	658	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
AnnaBridge	163:e59c8e839560	659	/**
AnnaBridge	163:e59c8e839560	660	* @}
AnnaBridge	163:e59c8e839560	661	*/
AnnaBridge	163:e59c8e839560	662
AnnaBridge	163:e59c8e839560	663	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	664	* @{
AnnaBridge	163:e59c8e839560	665	*/
AnnaBridge	163:e59c8e839560	666
AnnaBridge	163:e59c8e839560	667	#define FORMAT_BIN RTC_FORMAT_BIN
AnnaBridge	163:e59c8e839560	668	#define FORMAT_BCD RTC_FORMAT_BCD
AnnaBridge	163:e59c8e839560	669
AnnaBridge	163:e59c8e839560	670	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
AnnaBridge	163:e59c8e839560	671	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
AnnaBridge	163:e59c8e839560	672	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
AnnaBridge	163:e59c8e839560	673	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
AnnaBridge	163:e59c8e839560	674	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
AnnaBridge	163:e59c8e839560	675
AnnaBridge	163:e59c8e839560	676	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
AnnaBridge	163:e59c8e839560	677	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
AnnaBridge	163:e59c8e839560	678	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
AnnaBridge	163:e59c8e839560	679	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
AnnaBridge	163:e59c8e839560	680	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
AnnaBridge	163:e59c8e839560	681	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
AnnaBridge	163:e59c8e839560	682	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
AnnaBridge	163:e59c8e839560	683	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
AnnaBridge	163:e59c8e839560	684
AnnaBridge	163:e59c8e839560	685	#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
AnnaBridge	163:e59c8e839560	686	#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
AnnaBridge	163:e59c8e839560	687	#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
AnnaBridge	163:e59c8e839560	688	#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
AnnaBridge	163:e59c8e839560	689
AnnaBridge	163:e59c8e839560	690	#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
AnnaBridge	163:e59c8e839560	691	#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
AnnaBridge	163:e59c8e839560	692	#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
AnnaBridge	163:e59c8e839560	693
AnnaBridge	163:e59c8e839560	694	#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
AnnaBridge	163:e59c8e839560	695	#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
AnnaBridge	163:e59c8e839560	696	#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
AnnaBridge	163:e59c8e839560	697
AnnaBridge	163:e59c8e839560	698	/**
AnnaBridge	163:e59c8e839560	699	* @}
AnnaBridge	163:e59c8e839560	700	*/
AnnaBridge	163:e59c8e839560	701
AnnaBridge	163:e59c8e839560	702
AnnaBridge	163:e59c8e839560	703	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	704	* @{
AnnaBridge	163:e59c8e839560	705	*/
AnnaBridge	163:e59c8e839560	706	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
AnnaBridge	163:e59c8e839560	707	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
AnnaBridge	163:e59c8e839560	708
AnnaBridge	163:e59c8e839560	709	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	163:e59c8e839560	710	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	163:e59c8e839560	711	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	163:e59c8e839560	712	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	163:e59c8e839560	713
AnnaBridge	163:e59c8e839560	714	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
AnnaBridge	163:e59c8e839560	715	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
AnnaBridge	163:e59c8e839560	716
AnnaBridge	163:e59c8e839560	717	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
AnnaBridge	163:e59c8e839560	718	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
AnnaBridge	163:e59c8e839560	719	/**
AnnaBridge	163:e59c8e839560	720	* @}
AnnaBridge	163:e59c8e839560	721	*/
AnnaBridge	163:e59c8e839560	722
AnnaBridge	163:e59c8e839560	723
AnnaBridge	163:e59c8e839560	724	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	725	* @{
AnnaBridge	163:e59c8e839560	726	*/
AnnaBridge	163:e59c8e839560	727	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
AnnaBridge	163:e59c8e839560	728	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
AnnaBridge	163:e59c8e839560	729	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
AnnaBridge	163:e59c8e839560	730	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
AnnaBridge	163:e59c8e839560	731	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
AnnaBridge	163:e59c8e839560	732	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
AnnaBridge	163:e59c8e839560	733	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
AnnaBridge	163:e59c8e839560	734	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
AnnaBridge	163:e59c8e839560	735	#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
AnnaBridge	163:e59c8e839560	736	#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
AnnaBridge	163:e59c8e839560	737	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
AnnaBridge	163:e59c8e839560	738	/**
AnnaBridge	163:e59c8e839560	739	* @}
AnnaBridge	163:e59c8e839560	740	*/
AnnaBridge	163:e59c8e839560	741
AnnaBridge	163:e59c8e839560	742	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	743	* @{
AnnaBridge	163:e59c8e839560	744	*/
AnnaBridge	163:e59c8e839560	745	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
AnnaBridge	163:e59c8e839560	746	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
AnnaBridge	163:e59c8e839560	747
AnnaBridge	163:e59c8e839560	748	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
AnnaBridge	163:e59c8e839560	749	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
AnnaBridge	163:e59c8e839560	750
AnnaBridge	163:e59c8e839560	751	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
AnnaBridge	163:e59c8e839560	752	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
AnnaBridge	163:e59c8e839560	753
AnnaBridge	163:e59c8e839560	754	/**
AnnaBridge	163:e59c8e839560	755	* @}
AnnaBridge	163:e59c8e839560	756	*/
AnnaBridge	163:e59c8e839560	757
AnnaBridge	163:e59c8e839560	758	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	759	* @{
AnnaBridge	163:e59c8e839560	760	*/
AnnaBridge	163:e59c8e839560	761	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
AnnaBridge	163:e59c8e839560	762	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
AnnaBridge	163:e59c8e839560	763
AnnaBridge	163:e59c8e839560	764	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
AnnaBridge	163:e59c8e839560	765	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
AnnaBridge	163:e59c8e839560	766	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
AnnaBridge	163:e59c8e839560	767	#define TIM_DMABase_DIER TIM_DMABASE_DIER
AnnaBridge	163:e59c8e839560	768	#define TIM_DMABase_SR TIM_DMABASE_SR
AnnaBridge	163:e59c8e839560	769	#define TIM_DMABase_EGR TIM_DMABASE_EGR
AnnaBridge	163:e59c8e839560	770	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
AnnaBridge	163:e59c8e839560	771	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
AnnaBridge	163:e59c8e839560	772	#define TIM_DMABase_CCER TIM_DMABASE_CCER
AnnaBridge	163:e59c8e839560	773	#define TIM_DMABase_CNT TIM_DMABASE_CNT
AnnaBridge	163:e59c8e839560	774	#define TIM_DMABase_PSC TIM_DMABASE_PSC
AnnaBridge	163:e59c8e839560	775	#define TIM_DMABase_ARR TIM_DMABASE_ARR
AnnaBridge	163:e59c8e839560	776	#define TIM_DMABase_RCR TIM_DMABASE_RCR
AnnaBridge	163:e59c8e839560	777	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
AnnaBridge	163:e59c8e839560	778	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
AnnaBridge	163:e59c8e839560	779	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
AnnaBridge	163:e59c8e839560	780	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
AnnaBridge	163:e59c8e839560	781	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
AnnaBridge	163:e59c8e839560	782	#define TIM_DMABase_DCR TIM_DMABASE_DCR
AnnaBridge	163:e59c8e839560	783	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
AnnaBridge	163:e59c8e839560	784	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
AnnaBridge	163:e59c8e839560	785	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
AnnaBridge	163:e59c8e839560	786	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
AnnaBridge	163:e59c8e839560	787	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
AnnaBridge	163:e59c8e839560	788	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
AnnaBridge	163:e59c8e839560	789	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
AnnaBridge	163:e59c8e839560	790	#define TIM_DMABase_OR TIM_DMABASE_OR
AnnaBridge	163:e59c8e839560	791
AnnaBridge	163:e59c8e839560	792	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
AnnaBridge	163:e59c8e839560	793	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
AnnaBridge	163:e59c8e839560	794	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
AnnaBridge	163:e59c8e839560	795	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
AnnaBridge	163:e59c8e839560	796	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
AnnaBridge	163:e59c8e839560	797	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
AnnaBridge	163:e59c8e839560	798	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
AnnaBridge	163:e59c8e839560	799	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
AnnaBridge	163:e59c8e839560	800	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
AnnaBridge	163:e59c8e839560	801
AnnaBridge	163:e59c8e839560	802	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
AnnaBridge	163:e59c8e839560	803	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
AnnaBridge	163:e59c8e839560	804	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
AnnaBridge	163:e59c8e839560	805	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
AnnaBridge	163:e59c8e839560	806	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
AnnaBridge	163:e59c8e839560	807	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
AnnaBridge	163:e59c8e839560	808	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
AnnaBridge	163:e59c8e839560	809	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
AnnaBridge	163:e59c8e839560	810	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
AnnaBridge	163:e59c8e839560	811	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
AnnaBridge	163:e59c8e839560	812	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
AnnaBridge	163:e59c8e839560	813	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
AnnaBridge	163:e59c8e839560	814	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
AnnaBridge	163:e59c8e839560	815	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
AnnaBridge	163:e59c8e839560	816	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
AnnaBridge	163:e59c8e839560	817	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
AnnaBridge	163:e59c8e839560	818	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
AnnaBridge	163:e59c8e839560	819	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
AnnaBridge	163:e59c8e839560	820
AnnaBridge	163:e59c8e839560	821	/**
AnnaBridge	163:e59c8e839560	822	* @}
AnnaBridge	163:e59c8e839560	823	*/
AnnaBridge	163:e59c8e839560	824
AnnaBridge	163:e59c8e839560	825	/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	826	* @{
AnnaBridge	163:e59c8e839560	827	*/
AnnaBridge	163:e59c8e839560	828	#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
AnnaBridge	163:e59c8e839560	829	#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
AnnaBridge	163:e59c8e839560	830	/**
AnnaBridge	163:e59c8e839560	831	* @}
AnnaBridge	163:e59c8e839560	832	*/
AnnaBridge	163:e59c8e839560	833
AnnaBridge	163:e59c8e839560	834	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	835	* @{
AnnaBridge	163:e59c8e839560	836	*/
AnnaBridge	163:e59c8e839560	837	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	163:e59c8e839560	838	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	163:e59c8e839560	839	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	163:e59c8e839560	840	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	163:e59c8e839560	841
AnnaBridge	163:e59c8e839560	842	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	163:e59c8e839560	843	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	163:e59c8e839560	844
AnnaBridge	163:e59c8e839560	845	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
AnnaBridge	163:e59c8e839560	846	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
AnnaBridge	163:e59c8e839560	847	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
AnnaBridge	163:e59c8e839560	848	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
AnnaBridge	163:e59c8e839560	849
AnnaBridge	163:e59c8e839560	850	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
AnnaBridge	163:e59c8e839560	851	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
AnnaBridge	163:e59c8e839560	852	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
AnnaBridge	163:e59c8e839560	853	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
AnnaBridge	163:e59c8e839560	854
AnnaBridge	163:e59c8e839560	855	#define __DIV_LPUART UART_DIV_LPUART
AnnaBridge	163:e59c8e839560	856
AnnaBridge	163:e59c8e839560	857	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
AnnaBridge	163:e59c8e839560	858	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
AnnaBridge	163:e59c8e839560	859
AnnaBridge	163:e59c8e839560	860	/**
AnnaBridge	163:e59c8e839560	861	* @}
AnnaBridge	163:e59c8e839560	862	*/
AnnaBridge	163:e59c8e839560	863
AnnaBridge	163:e59c8e839560	864
AnnaBridge	163:e59c8e839560	865	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	866	* @{
AnnaBridge	163:e59c8e839560	867	*/
AnnaBridge	163:e59c8e839560	868
AnnaBridge	163:e59c8e839560	869	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
AnnaBridge	163:e59c8e839560	870	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
AnnaBridge	163:e59c8e839560	871
AnnaBridge	163:e59c8e839560	872	#define USARTNACK_ENABLED USART_NACK_ENABLE
AnnaBridge	163:e59c8e839560	873	#define USARTNACK_DISABLED USART_NACK_DISABLE
AnnaBridge	163:e59c8e839560	874	/**
AnnaBridge	163:e59c8e839560	875	* @}
AnnaBridge	163:e59c8e839560	876	*/
AnnaBridge	163:e59c8e839560	877
AnnaBridge	163:e59c8e839560	878	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	879	* @{
AnnaBridge	163:e59c8e839560	880	*/
AnnaBridge	163:e59c8e839560	881	#define CFR_BASE WWDG_CFR_BASE
AnnaBridge	163:e59c8e839560	882
AnnaBridge	163:e59c8e839560	883	/**
AnnaBridge	163:e59c8e839560	884	* @}
AnnaBridge	163:e59c8e839560	885	*/
AnnaBridge	163:e59c8e839560	886
AnnaBridge	163:e59c8e839560	887	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	888	* @{
AnnaBridge	163:e59c8e839560	889	*/
AnnaBridge	163:e59c8e839560	890	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
AnnaBridge	163:e59c8e839560	891	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
AnnaBridge	163:e59c8e839560	892	#define CAN_IT_RQCP0 CAN_IT_TME
AnnaBridge	163:e59c8e839560	893	#define CAN_IT_RQCP1 CAN_IT_TME
AnnaBridge	163:e59c8e839560	894	#define CAN_IT_RQCP2 CAN_IT_TME
AnnaBridge	163:e59c8e839560	895	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
AnnaBridge	163:e59c8e839560	896	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
AnnaBridge	163:e59c8e839560	897	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
AnnaBridge	163:e59c8e839560	898	#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
AnnaBridge	163:e59c8e839560	899	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
AnnaBridge	163:e59c8e839560	900
AnnaBridge	163:e59c8e839560	901	/**
AnnaBridge	163:e59c8e839560	902	* @}
AnnaBridge	163:e59c8e839560	903	*/
AnnaBridge	163:e59c8e839560	904
AnnaBridge	163:e59c8e839560	905	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	906	* @{
AnnaBridge	163:e59c8e839560	907	*/
AnnaBridge	163:e59c8e839560	908
AnnaBridge	163:e59c8e839560	909	#define VLAN_TAG ETH_VLAN_TAG
AnnaBridge	163:e59c8e839560	910	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
AnnaBridge	163:e59c8e839560	911	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
AnnaBridge	163:e59c8e839560	912	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
AnnaBridge	163:e59c8e839560	913	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
AnnaBridge	163:e59c8e839560	914	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
AnnaBridge	163:e59c8e839560	915	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
AnnaBridge	163:e59c8e839560	916	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
AnnaBridge	163:e59c8e839560	917
AnnaBridge	163:e59c8e839560	918	#define ETH_MMCCR 0x00000100U
AnnaBridge	163:e59c8e839560	919	#define ETH_MMCRIR 0x00000104U
AnnaBridge	163:e59c8e839560	920	#define ETH_MMCTIR 0x00000108U
AnnaBridge	163:e59c8e839560	921	#define ETH_MMCRIMR 0x0000010CU
AnnaBridge	163:e59c8e839560	922	#define ETH_MMCTIMR 0x00000110U
AnnaBridge	163:e59c8e839560	923	#define ETH_MMCTGFSCCR 0x0000014CU
AnnaBridge	163:e59c8e839560	924	#define ETH_MMCTGFMSCCR 0x00000150U
AnnaBridge	163:e59c8e839560	925	#define ETH_MMCTGFCR 0x00000168U
AnnaBridge	163:e59c8e839560	926	#define ETH_MMCRFCECR 0x00000194U
AnnaBridge	163:e59c8e839560	927	#define ETH_MMCRFAECR 0x00000198U
AnnaBridge	163:e59c8e839560	928	#define ETH_MMCRGUFCR 0x000001C4U
AnnaBridge	163:e59c8e839560	929
AnnaBridge	163:e59c8e839560	930	#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
AnnaBridge	163:e59c8e839560	931	#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
AnnaBridge	163:e59c8e839560	932	#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
AnnaBridge	163:e59c8e839560	933	#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
AnnaBridge	163:e59c8e839560	934	#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
AnnaBridge	163:e59c8e839560	935	#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
AnnaBridge	163:e59c8e839560	936	#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
AnnaBridge	163:e59c8e839560	937	#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
AnnaBridge	163:e59c8e839560	938	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
AnnaBridge	163:e59c8e839560	939	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
AnnaBridge	163:e59c8e839560	940	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
AnnaBridge	163:e59c8e839560	941	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
AnnaBridge	163:e59c8e839560	942	#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
AnnaBridge	163:e59c8e839560	943	#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
AnnaBridge	163:e59c8e839560	944	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
AnnaBridge	163:e59c8e839560	945	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
AnnaBridge	163:e59c8e839560	946	#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
AnnaBridge	163:e59c8e839560	947	#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
AnnaBridge	163:e59c8e839560	948	#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
AnnaBridge	163:e59c8e839560	949	#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
AnnaBridge	163:e59c8e839560	950	#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
AnnaBridge	163:e59c8e839560	951	#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
AnnaBridge	163:e59c8e839560	952	#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
AnnaBridge	163:e59c8e839560	953	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
AnnaBridge	163:e59c8e839560	954	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
AnnaBridge	163:e59c8e839560	955	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
AnnaBridge	163:e59c8e839560	956	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
AnnaBridge	163:e59c8e839560	957
AnnaBridge	163:e59c8e839560	958	/**
AnnaBridge	163:e59c8e839560	959	* @}
AnnaBridge	163:e59c8e839560	960	*/
AnnaBridge	163:e59c8e839560	961
AnnaBridge	163:e59c8e839560	962	/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	963	* @{
AnnaBridge	163:e59c8e839560	964	*/
AnnaBridge	163:e59c8e839560	965	#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
AnnaBridge	163:e59c8e839560	966	#define DCMI_IT_OVF DCMI_IT_OVR
AnnaBridge	163:e59c8e839560	967	#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
AnnaBridge	163:e59c8e839560	968	#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
AnnaBridge	163:e59c8e839560	969
AnnaBridge	163:e59c8e839560	970	#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
AnnaBridge	163:e59c8e839560	971	#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
AnnaBridge	163:e59c8e839560	972	#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
AnnaBridge	163:e59c8e839560	973
AnnaBridge	163:e59c8e839560	974	/**
AnnaBridge	163:e59c8e839560	975	* @}
AnnaBridge	163:e59c8e839560	976	*/
AnnaBridge	163:e59c8e839560	977
AnnaBridge	168:b9e159c1930a	978	#if defined(STM32L4) \|\| defined(STM32F7) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\|\
AnnaBridge	163:e59c8e839560	979	defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	980	/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	981	* @{
AnnaBridge	163:e59c8e839560	982	*/
AnnaBridge	163:e59c8e839560	983	#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
AnnaBridge	163:e59c8e839560	984	#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
AnnaBridge	163:e59c8e839560	985	#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
AnnaBridge	163:e59c8e839560	986	#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
AnnaBridge	163:e59c8e839560	987	#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
AnnaBridge	163:e59c8e839560	988
AnnaBridge	163:e59c8e839560	989	#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
AnnaBridge	163:e59c8e839560	990	#define CM_RGB888 DMA2D_INPUT_RGB888
AnnaBridge	163:e59c8e839560	991	#define CM_RGB565 DMA2D_INPUT_RGB565
AnnaBridge	163:e59c8e839560	992	#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
AnnaBridge	163:e59c8e839560	993	#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
AnnaBridge	163:e59c8e839560	994	#define CM_L8 DMA2D_INPUT_L8
AnnaBridge	163:e59c8e839560	995	#define CM_AL44 DMA2D_INPUT_AL44
AnnaBridge	163:e59c8e839560	996	#define CM_AL88 DMA2D_INPUT_AL88
AnnaBridge	163:e59c8e839560	997	#define CM_L4 DMA2D_INPUT_L4
AnnaBridge	163:e59c8e839560	998	#define CM_A8 DMA2D_INPUT_A8
AnnaBridge	163:e59c8e839560	999	#define CM_A4 DMA2D_INPUT_A4
AnnaBridge	163:e59c8e839560	1000	/**
AnnaBridge	163:e59c8e839560	1001	* @}
AnnaBridge	163:e59c8e839560	1002	*/
AnnaBridge	168:b9e159c1930a	1003	#endif /* STM32L4 \|\| STM32F7*/
AnnaBridge	163:e59c8e839560	1004
AnnaBridge	163:e59c8e839560	1005	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1006	* @{
AnnaBridge	163:e59c8e839560	1007	*/
AnnaBridge	163:e59c8e839560	1008
AnnaBridge	163:e59c8e839560	1009	/**
AnnaBridge	163:e59c8e839560	1010	* @}
AnnaBridge	163:e59c8e839560	1011	*/
AnnaBridge	163:e59c8e839560	1012
AnnaBridge	163:e59c8e839560	1013	/* Exported functions --------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1014
AnnaBridge	163:e59c8e839560	1015	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1016	* @{
AnnaBridge	163:e59c8e839560	1017	*/
AnnaBridge	163:e59c8e839560	1018	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
AnnaBridge	163:e59c8e839560	1019	/**
AnnaBridge	163:e59c8e839560	1020	* @}
AnnaBridge	163:e59c8e839560	1021	*/
AnnaBridge	163:e59c8e839560	1022
AnnaBridge	163:e59c8e839560	1023	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1024	* @{
AnnaBridge	163:e59c8e839560	1025	*/
AnnaBridge	163:e59c8e839560	1026	#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
AnnaBridge	163:e59c8e839560	1027	#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
AnnaBridge	163:e59c8e839560	1028	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
AnnaBridge	163:e59c8e839560	1029	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
AnnaBridge	163:e59c8e839560	1030	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
AnnaBridge	163:e59c8e839560	1031	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
AnnaBridge	163:e59c8e839560	1032
AnnaBridge	163:e59c8e839560	1033	/HASH Algorithm Selection/
AnnaBridge	163:e59c8e839560	1034
AnnaBridge	163:e59c8e839560	1035	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
AnnaBridge	163:e59c8e839560	1036	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
AnnaBridge	163:e59c8e839560	1037	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
AnnaBridge	163:e59c8e839560	1038	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
AnnaBridge	163:e59c8e839560	1039
AnnaBridge	163:e59c8e839560	1040	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
AnnaBridge	163:e59c8e839560	1041	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
AnnaBridge	163:e59c8e839560	1042
AnnaBridge	163:e59c8e839560	1043	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
AnnaBridge	163:e59c8e839560	1044	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
AnnaBridge	163:e59c8e839560	1045	/**
AnnaBridge	163:e59c8e839560	1046	* @}
AnnaBridge	163:e59c8e839560	1047	*/
AnnaBridge	163:e59c8e839560	1048
AnnaBridge	163:e59c8e839560	1049	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1050	* @{
AnnaBridge	163:e59c8e839560	1051	*/
AnnaBridge	163:e59c8e839560	1052	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
AnnaBridge	163:e59c8e839560	1053	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
AnnaBridge	163:e59c8e839560	1054	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
AnnaBridge	163:e59c8e839560	1055	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
AnnaBridge	163:e59c8e839560	1056	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
AnnaBridge	163:e59c8e839560	1057	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
AnnaBridge	163:e59c8e839560	1058	#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
AnnaBridge	163:e59c8e839560	1059	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
AnnaBridge	163:e59c8e839560	1060	#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
AnnaBridge	163:e59c8e839560	1061	#if defined(STM32L0)
AnnaBridge	163:e59c8e839560	1062	#else
AnnaBridge	163:e59c8e839560	1063	#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
AnnaBridge	163:e59c8e839560	1064	#endif
AnnaBridge	163:e59c8e839560	1065	#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
AnnaBridge	163:e59c8e839560	1066	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
AnnaBridge	163:e59c8e839560	1067	/**
AnnaBridge	163:e59c8e839560	1068	* @}
AnnaBridge	163:e59c8e839560	1069	*/
AnnaBridge	163:e59c8e839560	1070
AnnaBridge	163:e59c8e839560	1071	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1072	* @{
AnnaBridge	163:e59c8e839560	1073	*/
AnnaBridge	163:e59c8e839560	1074	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
AnnaBridge	163:e59c8e839560	1075	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
AnnaBridge	163:e59c8e839560	1076	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
AnnaBridge	163:e59c8e839560	1077	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
AnnaBridge	163:e59c8e839560	1078	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
AnnaBridge	163:e59c8e839560	1079	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
AnnaBridge	163:e59c8e839560	1080	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
AnnaBridge	163:e59c8e839560	1081
AnnaBridge	163:e59c8e839560	1082	/**
AnnaBridge	163:e59c8e839560	1083	* @}
AnnaBridge	163:e59c8e839560	1084	*/
AnnaBridge	163:e59c8e839560	1085
AnnaBridge	163:e59c8e839560	1086	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1087	* @{
AnnaBridge	163:e59c8e839560	1088	*/
AnnaBridge	163:e59c8e839560	1089	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
AnnaBridge	163:e59c8e839560	1090	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
AnnaBridge	163:e59c8e839560	1091	#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
AnnaBridge	163:e59c8e839560	1092	#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
AnnaBridge	163:e59c8e839560	1093
AnnaBridge	163:e59c8e839560	1094	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
AnnaBridge	163:e59c8e839560	1095	/**
AnnaBridge	163:e59c8e839560	1096	* @}
AnnaBridge	163:e59c8e839560	1097	*/
AnnaBridge	163:e59c8e839560	1098
AnnaBridge	163:e59c8e839560	1099	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1100	* @{
AnnaBridge	163:e59c8e839560	1101	*/
AnnaBridge	163:e59c8e839560	1102	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
AnnaBridge	163:e59c8e839560	1103	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
AnnaBridge	163:e59c8e839560	1104	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
AnnaBridge	163:e59c8e839560	1105	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
AnnaBridge	163:e59c8e839560	1106	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
AnnaBridge	163:e59c8e839560	1107	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
AnnaBridge	163:e59c8e839560	1108	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
AnnaBridge	163:e59c8e839560	1109	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
AnnaBridge	163:e59c8e839560	1110	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
AnnaBridge	163:e59c8e839560	1111	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
AnnaBridge	163:e59c8e839560	1112	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
AnnaBridge	163:e59c8e839560	1113	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
AnnaBridge	163:e59c8e839560	1114	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
AnnaBridge	163:e59c8e839560	1115	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
AnnaBridge	163:e59c8e839560	1116	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
AnnaBridge	163:e59c8e839560	1117	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
AnnaBridge	163:e59c8e839560	1118
AnnaBridge	163:e59c8e839560	1119	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
AnnaBridge	163:e59c8e839560	1120	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
AnnaBridge	163:e59c8e839560	1121	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
AnnaBridge	163:e59c8e839560	1122	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
AnnaBridge	163:e59c8e839560	1123	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
AnnaBridge	163:e59c8e839560	1124	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
AnnaBridge	163:e59c8e839560	1125	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
AnnaBridge	163:e59c8e839560	1126
AnnaBridge	163:e59c8e839560	1127	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
AnnaBridge	163:e59c8e839560	1128	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
AnnaBridge	163:e59c8e839560	1129
AnnaBridge	163:e59c8e839560	1130	#define DBP_BitNumber DBP_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1131	#define PVDE_BitNumber PVDE_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1132	#define PMODE_BitNumber PMODE_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1133	#define EWUP_BitNumber EWUP_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1134	#define FPDS_BitNumber FPDS_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1135	#define ODEN_BitNumber ODEN_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1136	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1137	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1138	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1139	#define BRE_BitNumber BRE_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1140
AnnaBridge	163:e59c8e839560	1141	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
AnnaBridge	163:e59c8e839560	1142
AnnaBridge	163:e59c8e839560	1143	/**
AnnaBridge	163:e59c8e839560	1144	* @}
AnnaBridge	163:e59c8e839560	1145	*/
AnnaBridge	163:e59c8e839560	1146
AnnaBridge	163:e59c8e839560	1147	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1148	* @{
AnnaBridge	163:e59c8e839560	1149	*/
AnnaBridge	163:e59c8e839560	1150	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
AnnaBridge	163:e59c8e839560	1151	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
AnnaBridge	163:e59c8e839560	1152	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
AnnaBridge	163:e59c8e839560	1153	/**
AnnaBridge	163:e59c8e839560	1154	* @}
AnnaBridge	163:e59c8e839560	1155	*/
AnnaBridge	163:e59c8e839560	1156
AnnaBridge	163:e59c8e839560	1157	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1158	* @{
AnnaBridge	163:e59c8e839560	1159	*/
AnnaBridge	163:e59c8e839560	1160	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
AnnaBridge	163:e59c8e839560	1161	/**
AnnaBridge	163:e59c8e839560	1162	* @}
AnnaBridge	163:e59c8e839560	1163	*/
AnnaBridge	163:e59c8e839560	1164
AnnaBridge	163:e59c8e839560	1165	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1166	* @{
AnnaBridge	163:e59c8e839560	1167	*/
AnnaBridge	163:e59c8e839560	1168	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
AnnaBridge	163:e59c8e839560	1169	#define HAL_TIM_DMAError TIM_DMAError
AnnaBridge	163:e59c8e839560	1170	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
AnnaBridge	163:e59c8e839560	1171	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
AnnaBridge	163:e59c8e839560	1172	/**
AnnaBridge	163:e59c8e839560	1173	* @}
AnnaBridge	163:e59c8e839560	1174	*/
AnnaBridge	163:e59c8e839560	1175
AnnaBridge	163:e59c8e839560	1176	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1177	* @{
AnnaBridge	163:e59c8e839560	1178	*/
AnnaBridge	163:e59c8e839560	1179	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
AnnaBridge	163:e59c8e839560	1180	/**
AnnaBridge	163:e59c8e839560	1181	* @}
AnnaBridge	163:e59c8e839560	1182	*/
AnnaBridge	163:e59c8e839560	1183
AnnaBridge	163:e59c8e839560	1184	/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1185	* @{
AnnaBridge	163:e59c8e839560	1186	*/
AnnaBridge	163:e59c8e839560	1187	#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
AnnaBridge	168:b9e159c1930a	1188	#define HAL_LTDC_Relaod HAL_LTDC_Reload
AnnaBridge	168:b9e159c1930a	1189	#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
AnnaBridge	168:b9e159c1930a	1190	#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
AnnaBridge	163:e59c8e839560	1191	/**
AnnaBridge	163:e59c8e839560	1192	* @}
AnnaBridge	163:e59c8e839560	1193	*/
AnnaBridge	163:e59c8e839560	1194
AnnaBridge	163:e59c8e839560	1195
AnnaBridge	163:e59c8e839560	1196	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1197	* @{
AnnaBridge	163:e59c8e839560	1198	*/
AnnaBridge	163:e59c8e839560	1199
AnnaBridge	163:e59c8e839560	1200	/**
AnnaBridge	163:e59c8e839560	1201	* @}
AnnaBridge	163:e59c8e839560	1202	*/
AnnaBridge	163:e59c8e839560	1203
AnnaBridge	163:e59c8e839560	1204	/* Exported macros ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	1205
AnnaBridge	163:e59c8e839560	1206	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1207	* @{
AnnaBridge	163:e59c8e839560	1208	*/
AnnaBridge	163:e59c8e839560	1209	#define AES_IT_CC CRYP_IT_CC
AnnaBridge	163:e59c8e839560	1210	#define AES_IT_ERR CRYP_IT_ERR
AnnaBridge	163:e59c8e839560	1211	#define AES_FLAG_CCF CRYP_FLAG_CCF
AnnaBridge	163:e59c8e839560	1212	/**
AnnaBridge	163:e59c8e839560	1213	* @}
AnnaBridge	163:e59c8e839560	1214	*/
AnnaBridge	163:e59c8e839560	1215
AnnaBridge	163:e59c8e839560	1216	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1217	* @{
AnnaBridge	163:e59c8e839560	1218	*/
AnnaBridge	163:e59c8e839560	1219	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
AnnaBridge	163:e59c8e839560	1220	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
AnnaBridge	163:e59c8e839560	1221	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
AnnaBridge	163:e59c8e839560	1222	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
AnnaBridge	163:e59c8e839560	1223	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
AnnaBridge	163:e59c8e839560	1224	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
AnnaBridge	163:e59c8e839560	1225	#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
AnnaBridge	163:e59c8e839560	1226	#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
AnnaBridge	163:e59c8e839560	1227	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
AnnaBridge	163:e59c8e839560	1228	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
AnnaBridge	163:e59c8e839560	1229	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
AnnaBridge	163:e59c8e839560	1230	#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
AnnaBridge	163:e59c8e839560	1231	#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
AnnaBridge	163:e59c8e839560	1232
AnnaBridge	163:e59c8e839560	1233	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
AnnaBridge	163:e59c8e839560	1234	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
AnnaBridge	163:e59c8e839560	1235	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
AnnaBridge	163:e59c8e839560	1236	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1237	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
AnnaBridge	163:e59c8e839560	1238
AnnaBridge	163:e59c8e839560	1239	/**
AnnaBridge	163:e59c8e839560	1240	* @}
AnnaBridge	163:e59c8e839560	1241	*/
AnnaBridge	163:e59c8e839560	1242
AnnaBridge	163:e59c8e839560	1243
AnnaBridge	163:e59c8e839560	1244	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1245	* @{
AnnaBridge	163:e59c8e839560	1246	*/
AnnaBridge	163:e59c8e839560	1247	#define __ADC_ENABLE __HAL_ADC_ENABLE
AnnaBridge	163:e59c8e839560	1248	#define __ADC_DISABLE __HAL_ADC_DISABLE
AnnaBridge	163:e59c8e839560	1249	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
AnnaBridge	163:e59c8e839560	1250	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
AnnaBridge	163:e59c8e839560	1251	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
AnnaBridge	163:e59c8e839560	1252	#define __ADC_IS_ENABLED ADC_IS_ENABLE
AnnaBridge	163:e59c8e839560	1253	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
AnnaBridge	163:e59c8e839560	1254	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
AnnaBridge	163:e59c8e839560	1255	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
AnnaBridge	163:e59c8e839560	1256	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
AnnaBridge	163:e59c8e839560	1257	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
AnnaBridge	163:e59c8e839560	1258	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
AnnaBridge	163:e59c8e839560	1259	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
AnnaBridge	163:e59c8e839560	1260
AnnaBridge	163:e59c8e839560	1261	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
AnnaBridge	163:e59c8e839560	1262	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
AnnaBridge	163:e59c8e839560	1263	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
AnnaBridge	163:e59c8e839560	1264	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
AnnaBridge	163:e59c8e839560	1265	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
AnnaBridge	163:e59c8e839560	1266	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
AnnaBridge	163:e59c8e839560	1267	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
AnnaBridge	163:e59c8e839560	1268	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
AnnaBridge	163:e59c8e839560	1269	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
AnnaBridge	163:e59c8e839560	1270	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
AnnaBridge	163:e59c8e839560	1271	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
AnnaBridge	163:e59c8e839560	1272	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
AnnaBridge	163:e59c8e839560	1273	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
AnnaBridge	163:e59c8e839560	1274	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
AnnaBridge	163:e59c8e839560	1275	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
AnnaBridge	163:e59c8e839560	1276	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
AnnaBridge	163:e59c8e839560	1277	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
AnnaBridge	163:e59c8e839560	1278	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
AnnaBridge	163:e59c8e839560	1279	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
AnnaBridge	163:e59c8e839560	1280	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
AnnaBridge	163:e59c8e839560	1281
AnnaBridge	163:e59c8e839560	1282	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
AnnaBridge	163:e59c8e839560	1283	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
AnnaBridge	163:e59c8e839560	1284	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
AnnaBridge	163:e59c8e839560	1285	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
AnnaBridge	163:e59c8e839560	1286	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
AnnaBridge	163:e59c8e839560	1287	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
AnnaBridge	163:e59c8e839560	1288	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
AnnaBridge	163:e59c8e839560	1289	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
AnnaBridge	163:e59c8e839560	1290	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
AnnaBridge	163:e59c8e839560	1291	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
AnnaBridge	163:e59c8e839560	1292
AnnaBridge	163:e59c8e839560	1293	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
AnnaBridge	163:e59c8e839560	1294	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
AnnaBridge	163:e59c8e839560	1295	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
AnnaBridge	163:e59c8e839560	1296	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
AnnaBridge	163:e59c8e839560	1297	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
AnnaBridge	163:e59c8e839560	1298	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
AnnaBridge	163:e59c8e839560	1299	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
AnnaBridge	163:e59c8e839560	1300	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
AnnaBridge	163:e59c8e839560	1301
AnnaBridge	163:e59c8e839560	1302	#define __HAL_ADC_SQR1 ADC_SQR1
AnnaBridge	163:e59c8e839560	1303	#define __HAL_ADC_SMPR1 ADC_SMPR1
AnnaBridge	163:e59c8e839560	1304	#define __HAL_ADC_SMPR2 ADC_SMPR2
AnnaBridge	163:e59c8e839560	1305	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
AnnaBridge	163:e59c8e839560	1306	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
AnnaBridge	163:e59c8e839560	1307	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
AnnaBridge	163:e59c8e839560	1308	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
AnnaBridge	163:e59c8e839560	1309	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
AnnaBridge	163:e59c8e839560	1310	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
AnnaBridge	163:e59c8e839560	1311	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
AnnaBridge	163:e59c8e839560	1312	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
AnnaBridge	163:e59c8e839560	1313	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
AnnaBridge	163:e59c8e839560	1314	#define __HAL_ADC_JSQR ADC_JSQR
AnnaBridge	163:e59c8e839560	1315
AnnaBridge	163:e59c8e839560	1316	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
AnnaBridge	163:e59c8e839560	1317	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
AnnaBridge	163:e59c8e839560	1318	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
AnnaBridge	163:e59c8e839560	1319	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
AnnaBridge	163:e59c8e839560	1320	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
AnnaBridge	163:e59c8e839560	1321	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
AnnaBridge	163:e59c8e839560	1322	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
AnnaBridge	163:e59c8e839560	1323	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
AnnaBridge	163:e59c8e839560	1324
AnnaBridge	163:e59c8e839560	1325	/**
AnnaBridge	163:e59c8e839560	1326	* @}
AnnaBridge	163:e59c8e839560	1327	*/
AnnaBridge	163:e59c8e839560	1328
AnnaBridge	163:e59c8e839560	1329	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1330	* @{
AnnaBridge	163:e59c8e839560	1331	*/
AnnaBridge	163:e59c8e839560	1332	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
AnnaBridge	163:e59c8e839560	1333	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
AnnaBridge	163:e59c8e839560	1334	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
AnnaBridge	163:e59c8e839560	1335	#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
AnnaBridge	163:e59c8e839560	1336
AnnaBridge	163:e59c8e839560	1337	/**
AnnaBridge	163:e59c8e839560	1338	* @}
AnnaBridge	163:e59c8e839560	1339	*/
AnnaBridge	163:e59c8e839560	1340
AnnaBridge	163:e59c8e839560	1341	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1342	* @{
AnnaBridge	163:e59c8e839560	1343	*/
AnnaBridge	163:e59c8e839560	1344	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
AnnaBridge	163:e59c8e839560	1345	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
AnnaBridge	163:e59c8e839560	1346	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
AnnaBridge	163:e59c8e839560	1347	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
AnnaBridge	163:e59c8e839560	1348	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
AnnaBridge	163:e59c8e839560	1349	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
AnnaBridge	163:e59c8e839560	1350	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
AnnaBridge	163:e59c8e839560	1351	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
AnnaBridge	163:e59c8e839560	1352	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
AnnaBridge	163:e59c8e839560	1353	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
AnnaBridge	163:e59c8e839560	1354	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
AnnaBridge	163:e59c8e839560	1355	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
AnnaBridge	163:e59c8e839560	1356	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
AnnaBridge	163:e59c8e839560	1357	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
AnnaBridge	163:e59c8e839560	1358	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
AnnaBridge	163:e59c8e839560	1359	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
AnnaBridge	163:e59c8e839560	1360
AnnaBridge	163:e59c8e839560	1361	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
AnnaBridge	163:e59c8e839560	1362	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
AnnaBridge	163:e59c8e839560	1363	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
AnnaBridge	163:e59c8e839560	1364	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
AnnaBridge	163:e59c8e839560	1365	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
AnnaBridge	163:e59c8e839560	1366	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
AnnaBridge	163:e59c8e839560	1367	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
AnnaBridge	163:e59c8e839560	1368	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
AnnaBridge	163:e59c8e839560	1369	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
AnnaBridge	163:e59c8e839560	1370	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
AnnaBridge	163:e59c8e839560	1371	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
AnnaBridge	163:e59c8e839560	1372	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
AnnaBridge	163:e59c8e839560	1373	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
AnnaBridge	163:e59c8e839560	1374	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
AnnaBridge	163:e59c8e839560	1375
AnnaBridge	163:e59c8e839560	1376
AnnaBridge	163:e59c8e839560	1377	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
AnnaBridge	163:e59c8e839560	1378	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
AnnaBridge	163:e59c8e839560	1379	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
AnnaBridge	163:e59c8e839560	1380	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
AnnaBridge	163:e59c8e839560	1381	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
AnnaBridge	163:e59c8e839560	1382	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
AnnaBridge	163:e59c8e839560	1383	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
AnnaBridge	163:e59c8e839560	1384	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
AnnaBridge	163:e59c8e839560	1385	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
AnnaBridge	163:e59c8e839560	1386	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
AnnaBridge	163:e59c8e839560	1387	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
AnnaBridge	163:e59c8e839560	1388	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
AnnaBridge	163:e59c8e839560	1389	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
AnnaBridge	163:e59c8e839560	1390	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
AnnaBridge	163:e59c8e839560	1391	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
AnnaBridge	163:e59c8e839560	1392	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
AnnaBridge	163:e59c8e839560	1393	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
AnnaBridge	163:e59c8e839560	1394	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
AnnaBridge	163:e59c8e839560	1395	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
AnnaBridge	163:e59c8e839560	1396	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
AnnaBridge	163:e59c8e839560	1397	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
AnnaBridge	163:e59c8e839560	1398	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
AnnaBridge	163:e59c8e839560	1399	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
AnnaBridge	163:e59c8e839560	1400	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
AnnaBridge	163:e59c8e839560	1401
AnnaBridge	163:e59c8e839560	1402	/**
AnnaBridge	163:e59c8e839560	1403	* @}
AnnaBridge	163:e59c8e839560	1404	*/
AnnaBridge	163:e59c8e839560	1405
AnnaBridge	163:e59c8e839560	1406	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1407	* @{
AnnaBridge	163:e59c8e839560	1408	*/
AnnaBridge	163:e59c8e839560	1409	#if defined(STM32F3)
AnnaBridge	163:e59c8e839560	1410	#define COMP_START __HAL_COMP_ENABLE
AnnaBridge	163:e59c8e839560	1411	#define COMP_STOP __HAL_COMP_DISABLE
AnnaBridge	163:e59c8e839560	1412	#define COMP_LOCK __HAL_COMP_LOCK
AnnaBridge	163:e59c8e839560	1413
AnnaBridge	163:e59c8e839560	1414	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	163:e59c8e839560	1415	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1416	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1417	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
AnnaBridge	163:e59c8e839560	1418	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1419	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1420	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
AnnaBridge	163:e59c8e839560	1421	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1422	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1423	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge	163:e59c8e839560	1424	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1425	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1426	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge	163:e59c8e839560	1427	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1428	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1429	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
AnnaBridge	163:e59c8e839560	1430	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1431	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1432	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
AnnaBridge	163:e59c8e839560	1433	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1434	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1435	__HAL_COMP_COMP6_EXTI_GET_FLAG())
AnnaBridge	163:e59c8e839560	1436	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1437	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1438	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
AnnaBridge	163:e59c8e839560	1439	# endif
AnnaBridge	163:e59c8e839560	1440	# if defined(STM32F302xE) \|\| defined(STM32F302xC)
AnnaBridge	163:e59c8e839560	1441	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1442	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1443	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1444	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
AnnaBridge	163:e59c8e839560	1445	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1446	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1447	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1448	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
AnnaBridge	163:e59c8e839560	1449	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1450	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1451	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1452	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge	163:e59c8e839560	1453	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1454	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1455	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1456	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge	163:e59c8e839560	1457	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1458	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1459	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1460	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
AnnaBridge	163:e59c8e839560	1461	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1462	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1463	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1464	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
AnnaBridge	163:e59c8e839560	1465	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1466	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1467	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1468	__HAL_COMP_COMP6_EXTI_GET_FLAG())
AnnaBridge	163:e59c8e839560	1469	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1470	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1471	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1472	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
AnnaBridge	163:e59c8e839560	1473	# endif
AnnaBridge	163:e59c8e839560	1474	# if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	163:e59c8e839560	1475	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1476	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1477	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1478	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1479	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1480	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1481	__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
AnnaBridge	163:e59c8e839560	1482	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1483	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1484	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1485	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1486	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1487	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1488	__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
AnnaBridge	163:e59c8e839560	1489	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1490	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1491	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1492	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1493	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1494	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1495	__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge	163:e59c8e839560	1496	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1497	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1498	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1499	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1500	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1501	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1502	__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge	163:e59c8e839560	1503	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1504	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1505	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1506	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1507	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1508	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1509	__HAL_COMP_COMP7_EXTI_ENABLE_IT())
AnnaBridge	163:e59c8e839560	1510	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1511	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1512	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1513	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1514	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1515	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1516	__HAL_COMP_COMP7_EXTI_DISABLE_IT())
AnnaBridge	163:e59c8e839560	1517	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1518	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1519	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1520	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1521	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1522	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1523	__HAL_COMP_COMP7_EXTI_GET_FLAG())
AnnaBridge	163:e59c8e839560	1524	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1525	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1526	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1527	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1528	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1529	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1530	__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
AnnaBridge	163:e59c8e839560	1531	# endif
AnnaBridge	163:e59c8e839560	1532	# if defined(STM32F373xC) \|\|defined(STM32F378xx)
AnnaBridge	163:e59c8e839560	1533	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1534	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
AnnaBridge	163:e59c8e839560	1535	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1536	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
AnnaBridge	163:e59c8e839560	1537	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1538	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge	163:e59c8e839560	1539	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1540	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge	163:e59c8e839560	1541	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1542	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
AnnaBridge	163:e59c8e839560	1543	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1544	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
AnnaBridge	163:e59c8e839560	1545	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1546	__HAL_COMP_COMP2_EXTI_GET_FLAG())
AnnaBridge	163:e59c8e839560	1547	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1548	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
AnnaBridge	163:e59c8e839560	1549	# endif
AnnaBridge	163:e59c8e839560	1550	#else
AnnaBridge	163:e59c8e839560	1551	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1552	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
AnnaBridge	163:e59c8e839560	1553	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	163:e59c8e839560	1554	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
AnnaBridge	163:e59c8e839560	1555	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1556	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge	163:e59c8e839560	1557	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	163:e59c8e839560	1558	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge	163:e59c8e839560	1559	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	1560	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
AnnaBridge	163:e59c8e839560	1561	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	1562	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
AnnaBridge	163:e59c8e839560	1563	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	1564	__HAL_COMP_COMP2_EXTI_GET_FLAG())
AnnaBridge	163:e59c8e839560	1565	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	1566	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
AnnaBridge	163:e59c8e839560	1567	#endif
AnnaBridge	163:e59c8e839560	1568
AnnaBridge	163:e59c8e839560	1569	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
AnnaBridge	163:e59c8e839560	1570
AnnaBridge	163:e59c8e839560	1571	#if defined(STM32L0) \|\| defined(STM32L4)
AnnaBridge	163:e59c8e839560	1572	/* Note: On these STM32 families, the only argument of this macro */
AnnaBridge	163:e59c8e839560	1573	/* is COMP_FLAG_LOCK. */
AnnaBridge	163:e59c8e839560	1574	/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
AnnaBridge	163:e59c8e839560	1575	/* argument. */
AnnaBridge	163:e59c8e839560	1576	#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
AnnaBridge	163:e59c8e839560	1577	#endif
AnnaBridge	163:e59c8e839560	1578	/**
AnnaBridge	163:e59c8e839560	1579	* @}
AnnaBridge	163:e59c8e839560	1580	*/
AnnaBridge	163:e59c8e839560	1581
AnnaBridge	163:e59c8e839560	1582	#if defined(STM32L0) \|\| defined(STM32L4)
AnnaBridge	163:e59c8e839560	1583	/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1584	* @{
AnnaBridge	163:e59c8e839560	1585	*/
AnnaBridge	163:e59c8e839560	1586	#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
AnnaBridge	163:e59c8e839560	1587	#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
AnnaBridge	163:e59c8e839560	1588	/**
AnnaBridge	163:e59c8e839560	1589	* @}
AnnaBridge	163:e59c8e839560	1590	*/
AnnaBridge	163:e59c8e839560	1591	#endif
AnnaBridge	163:e59c8e839560	1592
AnnaBridge	163:e59c8e839560	1593	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1594	* @{
AnnaBridge	163:e59c8e839560	1595	*/
AnnaBridge	163:e59c8e839560	1596
AnnaBridge	163:e59c8e839560	1597	#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) \|\| \
AnnaBridge	163:e59c8e839560	1598	((WAVE) == DAC_WAVE_NOISE)\|\| \
AnnaBridge	163:e59c8e839560	1599	((WAVE) == DAC_WAVE_TRIANGLE))
AnnaBridge	163:e59c8e839560	1600
AnnaBridge	163:e59c8e839560	1601	/**
AnnaBridge	163:e59c8e839560	1602	* @}
AnnaBridge	163:e59c8e839560	1603	*/
AnnaBridge	163:e59c8e839560	1604
AnnaBridge	163:e59c8e839560	1605	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1606	* @{
AnnaBridge	163:e59c8e839560	1607	*/
AnnaBridge	163:e59c8e839560	1608
AnnaBridge	163:e59c8e839560	1609	#define IS_WRPAREA IS_OB_WRPAREA
AnnaBridge	163:e59c8e839560	1610	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
AnnaBridge	163:e59c8e839560	1611	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
AnnaBridge	163:e59c8e839560	1612	#define IS_TYPEERASE IS_FLASH_TYPEERASE
AnnaBridge	163:e59c8e839560	1613	#define IS_NBSECTORS IS_FLASH_NBSECTORS
AnnaBridge	163:e59c8e839560	1614	#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
AnnaBridge	163:e59c8e839560	1615
AnnaBridge	163:e59c8e839560	1616	/**
AnnaBridge	163:e59c8e839560	1617	* @}
AnnaBridge	163:e59c8e839560	1618	*/
AnnaBridge	163:e59c8e839560	1619
AnnaBridge	163:e59c8e839560	1620	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1621	* @{
AnnaBridge	163:e59c8e839560	1622	*/
AnnaBridge	163:e59c8e839560	1623
AnnaBridge	163:e59c8e839560	1624	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
AnnaBridge	163:e59c8e839560	1625	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
AnnaBridge	168:b9e159c1930a	1626	#if defined(STM32F1)
AnnaBridge	168:b9e159c1930a	1627	#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
AnnaBridge	168:b9e159c1930a	1628	#else
AnnaBridge	163:e59c8e839560	1629	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
AnnaBridge	168:b9e159c1930a	1630	#endif /* STM32F1 */
AnnaBridge	163:e59c8e839560	1631	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
AnnaBridge	163:e59c8e839560	1632	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
AnnaBridge	163:e59c8e839560	1633	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
AnnaBridge	163:e59c8e839560	1634	#define __HAL_I2C_SPEED I2C_SPEED
AnnaBridge	163:e59c8e839560	1635	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
AnnaBridge	163:e59c8e839560	1636	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
AnnaBridge	163:e59c8e839560	1637	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
AnnaBridge	163:e59c8e839560	1638	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
AnnaBridge	163:e59c8e839560	1639	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
AnnaBridge	163:e59c8e839560	1640	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
AnnaBridge	163:e59c8e839560	1641	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
AnnaBridge	163:e59c8e839560	1642	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
AnnaBridge	163:e59c8e839560	1643	/**
AnnaBridge	163:e59c8e839560	1644	* @}
AnnaBridge	163:e59c8e839560	1645	*/
AnnaBridge	163:e59c8e839560	1646
AnnaBridge	163:e59c8e839560	1647	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1648	* @{
AnnaBridge	163:e59c8e839560	1649	*/
AnnaBridge	163:e59c8e839560	1650
AnnaBridge	163:e59c8e839560	1651	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
AnnaBridge	163:e59c8e839560	1652	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
AnnaBridge	163:e59c8e839560	1653
AnnaBridge	163:e59c8e839560	1654	/**
AnnaBridge	163:e59c8e839560	1655	* @}
AnnaBridge	163:e59c8e839560	1656	*/
AnnaBridge	163:e59c8e839560	1657
AnnaBridge	163:e59c8e839560	1658	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1659	* @{
AnnaBridge	163:e59c8e839560	1660	*/
AnnaBridge	163:e59c8e839560	1661
AnnaBridge	163:e59c8e839560	1662	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
AnnaBridge	163:e59c8e839560	1663	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
AnnaBridge	163:e59c8e839560	1664
AnnaBridge	163:e59c8e839560	1665	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
AnnaBridge	163:e59c8e839560	1666	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
AnnaBridge	163:e59c8e839560	1667	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
AnnaBridge	163:e59c8e839560	1668	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
AnnaBridge	163:e59c8e839560	1669
AnnaBridge	163:e59c8e839560	1670	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
AnnaBridge	163:e59c8e839560	1671
AnnaBridge	163:e59c8e839560	1672
AnnaBridge	163:e59c8e839560	1673	/**
AnnaBridge	163:e59c8e839560	1674	* @}
AnnaBridge	163:e59c8e839560	1675	*/
AnnaBridge	163:e59c8e839560	1676
AnnaBridge	163:e59c8e839560	1677
AnnaBridge	163:e59c8e839560	1678	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1679	* @{
AnnaBridge	163:e59c8e839560	1680	*/
AnnaBridge	163:e59c8e839560	1681	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
AnnaBridge	163:e59c8e839560	1682	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
AnnaBridge	163:e59c8e839560	1683	/**
AnnaBridge	163:e59c8e839560	1684	* @}
AnnaBridge	163:e59c8e839560	1685	*/
AnnaBridge	163:e59c8e839560	1686
AnnaBridge	163:e59c8e839560	1687
AnnaBridge	163:e59c8e839560	1688	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1689	* @{
AnnaBridge	163:e59c8e839560	1690	*/
AnnaBridge	163:e59c8e839560	1691
AnnaBridge	163:e59c8e839560	1692	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
AnnaBridge	163:e59c8e839560	1693	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
AnnaBridge	163:e59c8e839560	1694	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
AnnaBridge	163:e59c8e839560	1695
AnnaBridge	163:e59c8e839560	1696	/**
AnnaBridge	163:e59c8e839560	1697	* @}
AnnaBridge	163:e59c8e839560	1698	*/
AnnaBridge	163:e59c8e839560	1699
AnnaBridge	163:e59c8e839560	1700
AnnaBridge	163:e59c8e839560	1701	/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1702	* @{
AnnaBridge	163:e59c8e839560	1703	*/
AnnaBridge	163:e59c8e839560	1704	#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
AnnaBridge	163:e59c8e839560	1705	#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
AnnaBridge	163:e59c8e839560	1706	#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
AnnaBridge	163:e59c8e839560	1707	#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
AnnaBridge	163:e59c8e839560	1708	#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
AnnaBridge	163:e59c8e839560	1709	#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
AnnaBridge	163:e59c8e839560	1710	#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
AnnaBridge	163:e59c8e839560	1711	#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
AnnaBridge	163:e59c8e839560	1712	#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
AnnaBridge	163:e59c8e839560	1713	#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
AnnaBridge	163:e59c8e839560	1714	#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
AnnaBridge	163:e59c8e839560	1715	#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
AnnaBridge	163:e59c8e839560	1716	#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
AnnaBridge	163:e59c8e839560	1717
AnnaBridge	163:e59c8e839560	1718	/**
AnnaBridge	163:e59c8e839560	1719	* @}
AnnaBridge	163:e59c8e839560	1720	*/
AnnaBridge	163:e59c8e839560	1721
AnnaBridge	163:e59c8e839560	1722
AnnaBridge	163:e59c8e839560	1723	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1724	* @{
AnnaBridge	163:e59c8e839560	1725	*/
AnnaBridge	163:e59c8e839560	1726	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
AnnaBridge	163:e59c8e839560	1727	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
AnnaBridge	163:e59c8e839560	1728	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
AnnaBridge	163:e59c8e839560	1729	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	163:e59c8e839560	1730	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
AnnaBridge	163:e59c8e839560	1731	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge	163:e59c8e839560	1732	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
AnnaBridge	163:e59c8e839560	1733	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
AnnaBridge	163:e59c8e839560	1734	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
AnnaBridge	163:e59c8e839560	1735	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
AnnaBridge	163:e59c8e839560	1736	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
AnnaBridge	163:e59c8e839560	1737	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
AnnaBridge	163:e59c8e839560	1738	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
AnnaBridge	163:e59c8e839560	1739	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
AnnaBridge	163:e59c8e839560	1740	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
AnnaBridge	163:e59c8e839560	1741	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
AnnaBridge	163:e59c8e839560	1742	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
AnnaBridge	163:e59c8e839560	1743	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
AnnaBridge	163:e59c8e839560	1744	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
AnnaBridge	163:e59c8e839560	1745	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
AnnaBridge	163:e59c8e839560	1746	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	163:e59c8e839560	1747	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
AnnaBridge	163:e59c8e839560	1748	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge	163:e59c8e839560	1749	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	163:e59c8e839560	1750	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge	163:e59c8e839560	1751	#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
AnnaBridge	163:e59c8e839560	1752	#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
AnnaBridge	163:e59c8e839560	1753	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
AnnaBridge	163:e59c8e839560	1754	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
AnnaBridge	163:e59c8e839560	1755	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
AnnaBridge	163:e59c8e839560	1756	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
AnnaBridge	163:e59c8e839560	1757	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
AnnaBridge	163:e59c8e839560	1758	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	163:e59c8e839560	1759	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
AnnaBridge	163:e59c8e839560	1760	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
AnnaBridge	163:e59c8e839560	1761
AnnaBridge	163:e59c8e839560	1762	#if defined (STM32F4)
AnnaBridge	163:e59c8e839560	1763	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
AnnaBridge	163:e59c8e839560	1764	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
AnnaBridge	163:e59c8e839560	1765	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
AnnaBridge	163:e59c8e839560	1766	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
AnnaBridge	163:e59c8e839560	1767	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
AnnaBridge	163:e59c8e839560	1768	#else
AnnaBridge	163:e59c8e839560	1769	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
AnnaBridge	163:e59c8e839560	1770	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
AnnaBridge	163:e59c8e839560	1771	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
AnnaBridge	163:e59c8e839560	1772	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
AnnaBridge	163:e59c8e839560	1773	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
AnnaBridge	163:e59c8e839560	1774	#endif /* STM32F4 */
AnnaBridge	163:e59c8e839560	1775	/**
AnnaBridge	163:e59c8e839560	1776	* @}
AnnaBridge	163:e59c8e839560	1777	*/
AnnaBridge	163:e59c8e839560	1778
AnnaBridge	163:e59c8e839560	1779
AnnaBridge	163:e59c8e839560	1780	/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
AnnaBridge	163:e59c8e839560	1781	* @{
AnnaBridge	163:e59c8e839560	1782	*/
AnnaBridge	163:e59c8e839560	1783
AnnaBridge	163:e59c8e839560	1784	#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
AnnaBridge	163:e59c8e839560	1785	#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
AnnaBridge	163:e59c8e839560	1786
AnnaBridge	163:e59c8e839560	1787	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
AnnaBridge	163:e59c8e839560	1788	#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
AnnaBridge	163:e59c8e839560	1789
AnnaBridge	163:e59c8e839560	1790	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1791	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1792	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1793	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1794	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
AnnaBridge	163:e59c8e839560	1795	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1796	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1797	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1798	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
AnnaBridge	163:e59c8e839560	1799	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1800	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1801	#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1802	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1803	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1804	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
AnnaBridge	163:e59c8e839560	1805	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1806	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1807	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1808	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
AnnaBridge	163:e59c8e839560	1809	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1810	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1811	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1812	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1813	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1814	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
AnnaBridge	163:e59c8e839560	1815	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1816	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1817	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1818	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1819	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1820	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
AnnaBridge	163:e59c8e839560	1821	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1822	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1823	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1824	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
AnnaBridge	163:e59c8e839560	1825	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1826	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
AnnaBridge	163:e59c8e839560	1827	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1828	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
AnnaBridge	163:e59c8e839560	1829	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1830	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
AnnaBridge	163:e59c8e839560	1831	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1832	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
AnnaBridge	163:e59c8e839560	1833	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1834	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
AnnaBridge	163:e59c8e839560	1835	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1836	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
AnnaBridge	163:e59c8e839560	1837	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1838	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1839	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1840	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
AnnaBridge	163:e59c8e839560	1841	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1842	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1843	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1844	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1845	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1846	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
AnnaBridge	163:e59c8e839560	1847	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1848	#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1849	#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1850	#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
AnnaBridge	163:e59c8e839560	1851	#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1852	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1853	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1854	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
AnnaBridge	163:e59c8e839560	1855	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1856	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1857	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1858	#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1859	#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1860	#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
AnnaBridge	163:e59c8e839560	1861	#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1862	#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1863	#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1864	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
AnnaBridge	163:e59c8e839560	1865	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1866	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1867	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1868	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1869	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1870	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
AnnaBridge	163:e59c8e839560	1871	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1872	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1873	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1874	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
AnnaBridge	163:e59c8e839560	1875	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1876	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1877	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1878	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1879	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1880	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
AnnaBridge	163:e59c8e839560	1881	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1882	#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1883	#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1884	#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
AnnaBridge	163:e59c8e839560	1885	#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1886	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1887	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1888	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1889	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1890	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
AnnaBridge	163:e59c8e839560	1891	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1892	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1893	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1894	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1895	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1896	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
AnnaBridge	163:e59c8e839560	1897	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1898	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1899	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1900	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1901	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1902	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
AnnaBridge	163:e59c8e839560	1903	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1904	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1905	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1906	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
AnnaBridge	163:e59c8e839560	1907	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1908	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1909	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1910	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1911	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1912	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1913	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1914	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1915	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1916	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1917	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1918	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
AnnaBridge	163:e59c8e839560	1919	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1920	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1921	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1922	#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
AnnaBridge	163:e59c8e839560	1923	#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1924	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1925	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1926	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1927	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1928	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1929	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1930	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
AnnaBridge	163:e59c8e839560	1931	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1932	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1933	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1934	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1935	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1936	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1937	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1938	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
AnnaBridge	163:e59c8e839560	1939	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1940	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1941	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1942	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1943	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1944	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
AnnaBridge	163:e59c8e839560	1945	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1946	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1947	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1948	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1949	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1950	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
AnnaBridge	163:e59c8e839560	1951	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1952	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1953	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1954	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1955	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1956	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
AnnaBridge	163:e59c8e839560	1957	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1958	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1959	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1960	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1961	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1962	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
AnnaBridge	163:e59c8e839560	1963	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1964	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1965	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1966	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1967	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1968	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
AnnaBridge	163:e59c8e839560	1969	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1970	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1971	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1972	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1973	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1974	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
AnnaBridge	163:e59c8e839560	1975	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1976	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1977	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1978	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1979	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1980	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
AnnaBridge	163:e59c8e839560	1981	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1982	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1983	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1984	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1985	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1986	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
AnnaBridge	163:e59c8e839560	1987	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1988	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1989	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1990	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1991	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1992	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
AnnaBridge	163:e59c8e839560	1993	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	1994	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
AnnaBridge	163:e59c8e839560	1995	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
AnnaBridge	163:e59c8e839560	1996	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	1997	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	1998	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
AnnaBridge	163:e59c8e839560	1999	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2000	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2001	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2002	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2003	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2004	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
AnnaBridge	163:e59c8e839560	2005	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2006	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2007	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2008	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2009	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2010	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
AnnaBridge	163:e59c8e839560	2011	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2012	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2013	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2014	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2015	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2016	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
AnnaBridge	163:e59c8e839560	2017	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2018	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2019	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2020	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2021	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2022	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
AnnaBridge	163:e59c8e839560	2023	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2024	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2025	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2026	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2027	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2028	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
AnnaBridge	163:e59c8e839560	2029	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2030	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2031	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2032	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2033	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2034	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
AnnaBridge	163:e59c8e839560	2035	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2036	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2037	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2038	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2039	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2040	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
AnnaBridge	163:e59c8e839560	2041	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2042	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2043	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2044	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2045	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2046	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
AnnaBridge	163:e59c8e839560	2047	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2048	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2049	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2050	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2051	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2052	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
AnnaBridge	163:e59c8e839560	2053	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2054	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2055	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2056	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2057	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2058	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
AnnaBridge	163:e59c8e839560	2059	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2060	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2061	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2062	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2063	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2064	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
AnnaBridge	163:e59c8e839560	2065	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2066	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2067	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2068	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2069	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2070	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2071	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2072	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
AnnaBridge	163:e59c8e839560	2073	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2074	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2075	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2076	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2077	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2078	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
AnnaBridge	163:e59c8e839560	2079	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2080	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2081	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2082	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2083	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2084	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
AnnaBridge	163:e59c8e839560	2085	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2086	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2087	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2088	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2089	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2090	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
AnnaBridge	163:e59c8e839560	2091	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2092	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2093	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2094	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2095	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2096	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2097	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2098	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2099	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2100	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2101	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2102	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
AnnaBridge	163:e59c8e839560	2103	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2104	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2105	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2106	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2107	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2108	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
AnnaBridge	163:e59c8e839560	2109	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2110	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2111	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2112	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2113	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2114	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
AnnaBridge	163:e59c8e839560	2115	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2116	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2117	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2118	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
AnnaBridge	163:e59c8e839560	2119	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2120	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2121	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2122	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
AnnaBridge	163:e59c8e839560	2123	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2124	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2125	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2126	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
AnnaBridge	163:e59c8e839560	2127	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2128	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2129	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2130	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
AnnaBridge	163:e59c8e839560	2131	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2132	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2133	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2134	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
AnnaBridge	163:e59c8e839560	2135	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2136	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2137	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2138	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2139	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2140	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
AnnaBridge	163:e59c8e839560	2141	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2142	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2143	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2144	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2145	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2146	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
AnnaBridge	163:e59c8e839560	2147	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2148	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2149	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2150	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2151	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2152	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
AnnaBridge	163:e59c8e839560	2153	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2154	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2155	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2156	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2157	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2158	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
AnnaBridge	163:e59c8e839560	2159	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2160	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2161	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2162	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2163	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2164	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
AnnaBridge	163:e59c8e839560	2165	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2166	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2167	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2168	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2169	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2170	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
AnnaBridge	163:e59c8e839560	2171	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2172	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2173	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2174	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2175	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2176	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
AnnaBridge	163:e59c8e839560	2177	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2178	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2179	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2180	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2181	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2182	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
AnnaBridge	163:e59c8e839560	2183	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2184	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2185	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2186	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2187	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2188	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
AnnaBridge	163:e59c8e839560	2189	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2190	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2191	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2192	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2193	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2194	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
AnnaBridge	163:e59c8e839560	2195	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2196	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2197	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2198	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
AnnaBridge	163:e59c8e839560	2199	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2200	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2201	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2202	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2203	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2204	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
AnnaBridge	163:e59c8e839560	2205	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2206	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2207	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2208	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2209	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2210	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
AnnaBridge	163:e59c8e839560	2211	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2212	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2213	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2214	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2215	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2216	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
AnnaBridge	163:e59c8e839560	2217	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2218	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2219	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2220	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2221	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2222	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
AnnaBridge	163:e59c8e839560	2223	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2224	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2225	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2226	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2227	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2228	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
AnnaBridge	163:e59c8e839560	2229	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2230	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2231	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2232	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2233	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2234	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
AnnaBridge	163:e59c8e839560	2235	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2236	#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2237	#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2238	#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2239	#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2240	#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
AnnaBridge	163:e59c8e839560	2241	#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2242	#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2243	#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2244	#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2245	#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2246	#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
AnnaBridge	163:e59c8e839560	2247	#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2248	#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2249	#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2250	#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
AnnaBridge	163:e59c8e839560	2251	#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2252	#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2253	#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2254	#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
AnnaBridge	163:e59c8e839560	2255	#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2256	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2257	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2258	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
AnnaBridge	163:e59c8e839560	2259	#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2260	#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2261	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2262	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2263	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2264	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2265	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2266	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2267	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2268	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
AnnaBridge	163:e59c8e839560	2269	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2270	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2271	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2272	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
AnnaBridge	163:e59c8e839560	2273	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2274	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2275	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2276	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2277	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2278	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
AnnaBridge	163:e59c8e839560	2279	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2280	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2281	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2282	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2283	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2284	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2285	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2286	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
AnnaBridge	163:e59c8e839560	2287	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2288	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
AnnaBridge	163:e59c8e839560	2289	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
AnnaBridge	163:e59c8e839560	2290
AnnaBridge	163:e59c8e839560	2291	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
AnnaBridge	163:e59c8e839560	2292	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2293	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2294	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2295	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2296	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2297	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2298	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2299	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2300	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2301	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2302	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2303	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2304	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2305	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2306	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2307	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2308	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2309	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2310	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
AnnaBridge	163:e59c8e839560	2311	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2312	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2313	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2314	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2315	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2316	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2317	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
AnnaBridge	163:e59c8e839560	2318	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2319	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2320	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2321	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2322	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2323	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
AnnaBridge	163:e59c8e839560	2324	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2325	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2326	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2327	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2328	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2329	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
AnnaBridge	163:e59c8e839560	2330	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2331	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2332	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2333	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2334	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2335	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2336	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2337	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2338	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2339	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2340	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2341	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2342	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2343	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2344	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2345	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2346	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2347	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2348	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2349	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2350	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2351	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2352	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
AnnaBridge	163:e59c8e839560	2353	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2354	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2355	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2356	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2357	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2358	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
AnnaBridge	163:e59c8e839560	2359	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2360	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2361	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2362	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2363	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2364	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
AnnaBridge	163:e59c8e839560	2365	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2366	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2367	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2368	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2369	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2370	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
AnnaBridge	163:e59c8e839560	2371	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2372	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2373	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2374	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2375	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2376	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2377	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2378	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2379	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2380	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2381	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2382	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2383	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
AnnaBridge	163:e59c8e839560	2384	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2385	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2386	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2387	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2388	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2389	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2390	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
AnnaBridge	163:e59c8e839560	2391	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2392	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2393	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2394	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2395	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
AnnaBridge	163:e59c8e839560	2396	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2397	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2398	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2399	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2400	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2401	#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
AnnaBridge	163:e59c8e839560	2402	#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2403	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2404	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2405	#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2406	#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2407	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
AnnaBridge	163:e59c8e839560	2408	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
AnnaBridge	163:e59c8e839560	2409	#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
AnnaBridge	163:e59c8e839560	2410	#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2411	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2412	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2413	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
AnnaBridge	163:e59c8e839560	2414	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
AnnaBridge	163:e59c8e839560	2415	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
AnnaBridge	163:e59c8e839560	2416	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2417	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2418	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2419	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2420	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2421	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2422	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2423	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2424	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2425	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
AnnaBridge	163:e59c8e839560	2426	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2427	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2428	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2429	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
AnnaBridge	163:e59c8e839560	2430	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2431	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2432	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2433	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2434	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2435	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
AnnaBridge	163:e59c8e839560	2436	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2437	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2438	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2439
AnnaBridge	163:e59c8e839560	2440	/* alias define maintained for legacy */
AnnaBridge	163:e59c8e839560	2441	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
AnnaBridge	163:e59c8e839560	2442	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2443
AnnaBridge	163:e59c8e839560	2444	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2445	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2446	#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2447	#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2448	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2449	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2450	#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2451	#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2452	#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2453	#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2454	#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2455	#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2456	#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2457	#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2458	#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2459	#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2460	#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2461	#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2462	#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2463	#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2464	#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2465	#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2466
AnnaBridge	163:e59c8e839560	2467	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
AnnaBridge	163:e59c8e839560	2468	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2469	#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
AnnaBridge	163:e59c8e839560	2470	#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2471	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
AnnaBridge	163:e59c8e839560	2472	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2473	#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
AnnaBridge	163:e59c8e839560	2474	#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2475	#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
AnnaBridge	163:e59c8e839560	2476	#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2477	#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
AnnaBridge	163:e59c8e839560	2478	#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2479	#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
AnnaBridge	163:e59c8e839560	2480	#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2481	#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
AnnaBridge	163:e59c8e839560	2482	#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2483	#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
AnnaBridge	163:e59c8e839560	2484	#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
AnnaBridge	163:e59c8e839560	2485	#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
AnnaBridge	163:e59c8e839560	2486	#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2487	#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2488	#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2489
AnnaBridge	163:e59c8e839560	2490	#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2491	#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2492	#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2493	#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2494	#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2495	#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2496	#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2497	#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2498	#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2499	#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2500	#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2501	#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2502	#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2503	#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2504	#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2505	#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2506	#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2507	#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2508	#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2509	#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2510	#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2511	#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2512	#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2513	#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2514	#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2515	#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2516	#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2517	#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2518	#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2519	#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2520	#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2521	#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2522	#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2523	#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2524	#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2525	#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2526	#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2527	#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2528	#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2529	#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2530	#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2531	#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2532	#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2533	#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2534	#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2535	#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2536	#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2537	#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2538	#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2539	#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2540	#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2541	#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2542	#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2543	#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2544	#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2545	#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2546	#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2547	#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2548	#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2549	#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2550	#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2551	#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2552	#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2553	#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2554	#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2555	#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2556	#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2557	#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2558	#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2559	#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2560	#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2561	#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2562	#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2563	#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2564	#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2565	#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2566	#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2567	#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2568	#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2569	#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2570	#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2571	#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2572	#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2573	#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2574	#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2575	#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2576	#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2577	#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2578	#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2579	#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2580	#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2581	#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2582	#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2583	#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2584	#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2585	#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2586	#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2587	#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2588	#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2589	#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2590	#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2591	#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2592	#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2593	#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2594	#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2595	#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2596	#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2597	#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2598	#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2599	#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2600	#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2601	#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2602	#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2603	#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2604	#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2605	#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2606
AnnaBridge	163:e59c8e839560	2607	#if defined(STM32F4)
AnnaBridge	163:e59c8e839560	2608	#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
AnnaBridge	163:e59c8e839560	2609	#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2610	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2611	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2612	#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2613	#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2614	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2615	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2616	#define Sdmmc1ClockSelection SdioClockSelection
AnnaBridge	163:e59c8e839560	2617	#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
AnnaBridge	163:e59c8e839560	2618	#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
AnnaBridge	163:e59c8e839560	2619	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
AnnaBridge	163:e59c8e839560	2620	#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
AnnaBridge	163:e59c8e839560	2621	#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
AnnaBridge	163:e59c8e839560	2622	#endif
AnnaBridge	163:e59c8e839560	2623
AnnaBridge	163:e59c8e839560	2624	#if defined(STM32F7) \|\| defined(STM32L4)
AnnaBridge	163:e59c8e839560	2625	#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
AnnaBridge	163:e59c8e839560	2626	#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2627	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2628	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2629	#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2630	#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2631	#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2632	#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2633	#define SdioClockSelection Sdmmc1ClockSelection
AnnaBridge	163:e59c8e839560	2634	#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
AnnaBridge	163:e59c8e839560	2635	#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
AnnaBridge	163:e59c8e839560	2636	#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
AnnaBridge	163:e59c8e839560	2637	#endif
AnnaBridge	163:e59c8e839560	2638
AnnaBridge	163:e59c8e839560	2639	#if defined(STM32F7)
AnnaBridge	163:e59c8e839560	2640	#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
AnnaBridge	163:e59c8e839560	2641	#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
AnnaBridge	163:e59c8e839560	2642	#endif
AnnaBridge	163:e59c8e839560	2643
AnnaBridge	163:e59c8e839560	2644	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
AnnaBridge	163:e59c8e839560	2645	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
AnnaBridge	163:e59c8e839560	2646
AnnaBridge	163:e59c8e839560	2647	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
AnnaBridge	163:e59c8e839560	2648
AnnaBridge	163:e59c8e839560	2649	#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
AnnaBridge	163:e59c8e839560	2650	#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
AnnaBridge	163:e59c8e839560	2651	#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
AnnaBridge	163:e59c8e839560	2652	#define IS_RCC_HCLK_DIV IS_RCC_PCLK
AnnaBridge	163:e59c8e839560	2653	#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
AnnaBridge	163:e59c8e839560	2654
AnnaBridge	163:e59c8e839560	2655	#define RCC_IT_HSI14 RCC_IT_HSI14RDY
AnnaBridge	163:e59c8e839560	2656
AnnaBridge	163:e59c8e839560	2657	#define RCC_IT_CSSLSE RCC_IT_LSECSS
AnnaBridge	163:e59c8e839560	2658	#define RCC_IT_CSSHSE RCC_IT_CSS
AnnaBridge	163:e59c8e839560	2659
AnnaBridge	163:e59c8e839560	2660	#define RCC_PLLMUL_3 RCC_PLL_MUL3
AnnaBridge	163:e59c8e839560	2661	#define RCC_PLLMUL_4 RCC_PLL_MUL4
AnnaBridge	163:e59c8e839560	2662	#define RCC_PLLMUL_6 RCC_PLL_MUL6
AnnaBridge	163:e59c8e839560	2663	#define RCC_PLLMUL_8 RCC_PLL_MUL8
AnnaBridge	163:e59c8e839560	2664	#define RCC_PLLMUL_12 RCC_PLL_MUL12
AnnaBridge	163:e59c8e839560	2665	#define RCC_PLLMUL_16 RCC_PLL_MUL16
AnnaBridge	163:e59c8e839560	2666	#define RCC_PLLMUL_24 RCC_PLL_MUL24
AnnaBridge	163:e59c8e839560	2667	#define RCC_PLLMUL_32 RCC_PLL_MUL32
AnnaBridge	163:e59c8e839560	2668	#define RCC_PLLMUL_48 RCC_PLL_MUL48
AnnaBridge	163:e59c8e839560	2669
AnnaBridge	163:e59c8e839560	2670	#define RCC_PLLDIV_2 RCC_PLL_DIV2
AnnaBridge	163:e59c8e839560	2671	#define RCC_PLLDIV_3 RCC_PLL_DIV3
AnnaBridge	163:e59c8e839560	2672	#define RCC_PLLDIV_4 RCC_PLL_DIV4
AnnaBridge	163:e59c8e839560	2673
AnnaBridge	163:e59c8e839560	2674	#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
AnnaBridge	163:e59c8e839560	2675	#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
AnnaBridge	163:e59c8e839560	2676	#define RCC_MCO_NODIV RCC_MCODIV_1
AnnaBridge	163:e59c8e839560	2677	#define RCC_MCO_DIV1 RCC_MCODIV_1
AnnaBridge	163:e59c8e839560	2678	#define RCC_MCO_DIV2 RCC_MCODIV_2
AnnaBridge	163:e59c8e839560	2679	#define RCC_MCO_DIV4 RCC_MCODIV_4
AnnaBridge	163:e59c8e839560	2680	#define RCC_MCO_DIV8 RCC_MCODIV_8
AnnaBridge	163:e59c8e839560	2681	#define RCC_MCO_DIV16 RCC_MCODIV_16
AnnaBridge	163:e59c8e839560	2682	#define RCC_MCO_DIV32 RCC_MCODIV_32
AnnaBridge	163:e59c8e839560	2683	#define RCC_MCO_DIV64 RCC_MCODIV_64
AnnaBridge	163:e59c8e839560	2684	#define RCC_MCO_DIV128 RCC_MCODIV_128
AnnaBridge	163:e59c8e839560	2685	#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
AnnaBridge	163:e59c8e839560	2686	#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
AnnaBridge	163:e59c8e839560	2687	#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
AnnaBridge	163:e59c8e839560	2688	#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
AnnaBridge	163:e59c8e839560	2689	#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
AnnaBridge	163:e59c8e839560	2690	#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
AnnaBridge	163:e59c8e839560	2691	#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
AnnaBridge	163:e59c8e839560	2692	#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
AnnaBridge	163:e59c8e839560	2693	#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
AnnaBridge	163:e59c8e839560	2694	#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
AnnaBridge	163:e59c8e839560	2695	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
AnnaBridge	163:e59c8e839560	2696
AnnaBridge	163:e59c8e839560	2697	#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
AnnaBridge	163:e59c8e839560	2698
AnnaBridge	163:e59c8e839560	2699	#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
AnnaBridge	163:e59c8e839560	2700	#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
AnnaBridge	163:e59c8e839560	2701	#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
AnnaBridge	163:e59c8e839560	2702	#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
AnnaBridge	163:e59c8e839560	2703	#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
AnnaBridge	163:e59c8e839560	2704	#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
AnnaBridge	163:e59c8e839560	2705	#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
AnnaBridge	163:e59c8e839560	2706	#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
AnnaBridge	163:e59c8e839560	2707
AnnaBridge	163:e59c8e839560	2708	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2709	#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2710	#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2711	#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2712	#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2713	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2714	#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2715	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2716	#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2717	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2718	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2719	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2720	#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2721	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2722	#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2723	#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2724	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2725	#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2726	#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2727	#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2728	#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2729	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2730	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2731	#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2732	#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2733	#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
AnnaBridge	163:e59c8e839560	2734	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
AnnaBridge	163:e59c8e839560	2735	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
AnnaBridge	163:e59c8e839560	2736	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
AnnaBridge	163:e59c8e839560	2737	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
AnnaBridge	163:e59c8e839560	2738	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
AnnaBridge	163:e59c8e839560	2739	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
AnnaBridge	163:e59c8e839560	2740
AnnaBridge	163:e59c8e839560	2741	#define CR_HSION_BB RCC_CR_HSION_BB
AnnaBridge	163:e59c8e839560	2742	#define CR_CSSON_BB RCC_CR_CSSON_BB
AnnaBridge	163:e59c8e839560	2743	#define CR_PLLON_BB RCC_CR_PLLON_BB
AnnaBridge	163:e59c8e839560	2744	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
AnnaBridge	163:e59c8e839560	2745	#define CR_MSION_BB RCC_CR_MSION_BB
AnnaBridge	163:e59c8e839560	2746	#define CSR_LSION_BB RCC_CSR_LSION_BB
AnnaBridge	163:e59c8e839560	2747	#define CSR_LSEON_BB RCC_CSR_LSEON_BB
AnnaBridge	163:e59c8e839560	2748	#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
AnnaBridge	163:e59c8e839560	2749	#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
AnnaBridge	163:e59c8e839560	2750	#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
AnnaBridge	163:e59c8e839560	2751	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
AnnaBridge	163:e59c8e839560	2752	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
AnnaBridge	163:e59c8e839560	2753	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
AnnaBridge	163:e59c8e839560	2754	#define CR_HSEON_BB RCC_CR_HSEON_BB
AnnaBridge	163:e59c8e839560	2755	#define CSR_RMVF_BB RCC_CSR_RMVF_BB
AnnaBridge	163:e59c8e839560	2756	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
AnnaBridge	163:e59c8e839560	2757	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
AnnaBridge	163:e59c8e839560	2758
AnnaBridge	163:e59c8e839560	2759	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
AnnaBridge	163:e59c8e839560	2760	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
AnnaBridge	163:e59c8e839560	2761	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
AnnaBridge	163:e59c8e839560	2762	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
AnnaBridge	163:e59c8e839560	2763	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
AnnaBridge	163:e59c8e839560	2764
AnnaBridge	163:e59c8e839560	2765	#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
AnnaBridge	163:e59c8e839560	2766
AnnaBridge	163:e59c8e839560	2767	#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
AnnaBridge	163:e59c8e839560	2768	#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
AnnaBridge	163:e59c8e839560	2769
AnnaBridge	163:e59c8e839560	2770	#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
AnnaBridge	163:e59c8e839560	2771	#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
AnnaBridge	163:e59c8e839560	2772	#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
AnnaBridge	163:e59c8e839560	2773	#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
AnnaBridge	163:e59c8e839560	2774	#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
AnnaBridge	163:e59c8e839560	2775	#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
AnnaBridge	163:e59c8e839560	2776
AnnaBridge	163:e59c8e839560	2777	#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
AnnaBridge	163:e59c8e839560	2778	#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
AnnaBridge	163:e59c8e839560	2779	#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
AnnaBridge	163:e59c8e839560	2780	#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
AnnaBridge	163:e59c8e839560	2781	#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
AnnaBridge	163:e59c8e839560	2782	#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
AnnaBridge	163:e59c8e839560	2783	#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
AnnaBridge	163:e59c8e839560	2784	#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
AnnaBridge	163:e59c8e839560	2785	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
AnnaBridge	163:e59c8e839560	2786	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
AnnaBridge	163:e59c8e839560	2787	#define DfsdmClockSelection Dfsdm1ClockSelection
AnnaBridge	163:e59c8e839560	2788	#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
AnnaBridge	163:e59c8e839560	2789	#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
AnnaBridge	163:e59c8e839560	2790	#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
AnnaBridge	163:e59c8e839560	2791	#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
AnnaBridge	163:e59c8e839560	2792	#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
AnnaBridge	163:e59c8e839560	2793	#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
AnnaBridge	163:e59c8e839560	2794	#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
AnnaBridge	163:e59c8e839560	2795	#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
AnnaBridge	163:e59c8e839560	2796	#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
AnnaBridge	168:b9e159c1930a	2797
AnnaBridge	168:b9e159c1930a	2798	#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
AnnaBridge	168:b9e159c1930a	2799	#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
AnnaBridge	168:b9e159c1930a	2800	#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
AnnaBridge	168:b9e159c1930a	2801	#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
AnnaBridge	168:b9e159c1930a	2802	#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
AnnaBridge	168:b9e159c1930a	2803	#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
AnnaBridge	168:b9e159c1930a	2804	#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
AnnaBridge	168:b9e159c1930a	2805
AnnaBridge	163:e59c8e839560	2806	/**
AnnaBridge	163:e59c8e839560	2807	* @}
AnnaBridge	163:e59c8e839560	2808	*/
AnnaBridge	163:e59c8e839560	2809
AnnaBridge	163:e59c8e839560	2810	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	2811	* @{
AnnaBridge	163:e59c8e839560	2812	*/
AnnaBridge	163:e59c8e839560	2813	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
AnnaBridge	163:e59c8e839560	2814
AnnaBridge	163:e59c8e839560	2815	/**
AnnaBridge	163:e59c8e839560	2816	* @}
AnnaBridge	163:e59c8e839560	2817	*/
AnnaBridge	163:e59c8e839560	2818
AnnaBridge	163:e59c8e839560	2819	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	2820	* @{
AnnaBridge	163:e59c8e839560	2821	*/
AnnaBridge	163:e59c8e839560	2822
AnnaBridge	163:e59c8e839560	2823	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
AnnaBridge	163:e59c8e839560	2824	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
AnnaBridge	163:e59c8e839560	2825	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
AnnaBridge	163:e59c8e839560	2826
AnnaBridge	163:e59c8e839560	2827	#if defined (STM32F1)
AnnaBridge	163:e59c8e839560	2828	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
AnnaBridge	163:e59c8e839560	2829
AnnaBridge	163:e59c8e839560	2830	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
AnnaBridge	163:e59c8e839560	2831
AnnaBridge	163:e59c8e839560	2832	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
AnnaBridge	163:e59c8e839560	2833
AnnaBridge	163:e59c8e839560	2834	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
AnnaBridge	163:e59c8e839560	2835
AnnaBridge	163:e59c8e839560	2836	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
AnnaBridge	163:e59c8e839560	2837	#else
AnnaBridge	163:e59c8e839560	2838	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	2839	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
AnnaBridge	163:e59c8e839560	2840	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
AnnaBridge	163:e59c8e839560	2841	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	2842	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
AnnaBridge	163:e59c8e839560	2843	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
AnnaBridge	163:e59c8e839560	2844	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	2845	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
AnnaBridge	163:e59c8e839560	2846	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
AnnaBridge	163:e59c8e839560	2847	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	2848	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
AnnaBridge	163:e59c8e839560	2849	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
AnnaBridge	163:e59c8e839560	2850	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
AnnaBridge	163:e59c8e839560	2851	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
AnnaBridge	163:e59c8e839560	2852	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
AnnaBridge	163:e59c8e839560	2853	#endif /* STM32F1 */
AnnaBridge	163:e59c8e839560	2854
AnnaBridge	163:e59c8e839560	2855	#define IS_ALARM IS_RTC_ALARM
AnnaBridge	163:e59c8e839560	2856	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
AnnaBridge	163:e59c8e839560	2857	#define IS_TAMPER IS_RTC_TAMPER
AnnaBridge	163:e59c8e839560	2858	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
AnnaBridge	163:e59c8e839560	2859	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
AnnaBridge	163:e59c8e839560	2860	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
AnnaBridge	163:e59c8e839560	2861	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
AnnaBridge	163:e59c8e839560	2862	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
AnnaBridge	163:e59c8e839560	2863	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
AnnaBridge	163:e59c8e839560	2864	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
AnnaBridge	163:e59c8e839560	2865	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
AnnaBridge	163:e59c8e839560	2866	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
AnnaBridge	163:e59c8e839560	2867	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
AnnaBridge	163:e59c8e839560	2868	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
AnnaBridge	163:e59c8e839560	2869
AnnaBridge	163:e59c8e839560	2870	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
AnnaBridge	163:e59c8e839560	2871	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
AnnaBridge	163:e59c8e839560	2872
AnnaBridge	163:e59c8e839560	2873	/**
AnnaBridge	163:e59c8e839560	2874	* @}
AnnaBridge	163:e59c8e839560	2875	*/
AnnaBridge	163:e59c8e839560	2876
AnnaBridge	163:e59c8e839560	2877	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	2878	* @{
AnnaBridge	163:e59c8e839560	2879	*/
AnnaBridge	163:e59c8e839560	2880
AnnaBridge	163:e59c8e839560	2881	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
AnnaBridge	163:e59c8e839560	2882	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
AnnaBridge	163:e59c8e839560	2883
AnnaBridge	163:e59c8e839560	2884	#if defined(STM32F4)
AnnaBridge	163:e59c8e839560	2885	#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
AnnaBridge	163:e59c8e839560	2886	#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
AnnaBridge	163:e59c8e839560	2887	#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
AnnaBridge	163:e59c8e839560	2888	#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
AnnaBridge	163:e59c8e839560	2889	#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
AnnaBridge	163:e59c8e839560	2890	#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
AnnaBridge	163:e59c8e839560	2891	#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
AnnaBridge	163:e59c8e839560	2892	#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
AnnaBridge	163:e59c8e839560	2893	#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
AnnaBridge	163:e59c8e839560	2894	#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
AnnaBridge	163:e59c8e839560	2895	#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
AnnaBridge	163:e59c8e839560	2896	#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
AnnaBridge	163:e59c8e839560	2897	#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
AnnaBridge	163:e59c8e839560	2898	#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
AnnaBridge	163:e59c8e839560	2899	#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
AnnaBridge	163:e59c8e839560	2900	#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
AnnaBridge	163:e59c8e839560	2901	#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
AnnaBridge	163:e59c8e839560	2902	#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
AnnaBridge	163:e59c8e839560	2903	#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
AnnaBridge	163:e59c8e839560	2904	#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
AnnaBridge	163:e59c8e839560	2905	/* alias CMSIS */
AnnaBridge	163:e59c8e839560	2906	#define SDMMC1_IRQn SDIO_IRQn
AnnaBridge	163:e59c8e839560	2907	#define SDMMC1_IRQHandler SDIO_IRQHandler
AnnaBridge	163:e59c8e839560	2908	#endif
AnnaBridge	163:e59c8e839560	2909
AnnaBridge	163:e59c8e839560	2910	#if defined(STM32F7) \|\| defined(STM32L4)
AnnaBridge	163:e59c8e839560	2911	#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
AnnaBridge	163:e59c8e839560	2912	#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
AnnaBridge	163:e59c8e839560	2913	#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
AnnaBridge	163:e59c8e839560	2914	#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
AnnaBridge	163:e59c8e839560	2915	#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
AnnaBridge	163:e59c8e839560	2916	#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
AnnaBridge	163:e59c8e839560	2917	#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
AnnaBridge	163:e59c8e839560	2918	#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
AnnaBridge	163:e59c8e839560	2919	#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
AnnaBridge	163:e59c8e839560	2920	#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
AnnaBridge	163:e59c8e839560	2921	#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
AnnaBridge	163:e59c8e839560	2922	#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
AnnaBridge	163:e59c8e839560	2923	#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
AnnaBridge	163:e59c8e839560	2924	#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
AnnaBridge	163:e59c8e839560	2925	#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
AnnaBridge	163:e59c8e839560	2926	#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
AnnaBridge	163:e59c8e839560	2927	#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
AnnaBridge	163:e59c8e839560	2928	#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
AnnaBridge	163:e59c8e839560	2929	#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
AnnaBridge	163:e59c8e839560	2930	#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
AnnaBridge	163:e59c8e839560	2931	/* alias CMSIS for compatibilities */
AnnaBridge	163:e59c8e839560	2932	#define SDIO_IRQn SDMMC1_IRQn
AnnaBridge	163:e59c8e839560	2933	#define SDIO_IRQHandler SDMMC1_IRQHandler
AnnaBridge	163:e59c8e839560	2934	#endif
AnnaBridge	168:b9e159c1930a	2935
AnnaBridge	168:b9e159c1930a	2936	#if defined(STM32F7) \|\| defined(STM32F4) \|\| defined(STM32F2)
AnnaBridge	168:b9e159c1930a	2937	#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
AnnaBridge	168:b9e159c1930a	2938	#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
AnnaBridge	168:b9e159c1930a	2939	#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
AnnaBridge	168:b9e159c1930a	2940	#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
AnnaBridge	168:b9e159c1930a	2941	#endif
AnnaBridge	168:b9e159c1930a	2942
AnnaBridge	163:e59c8e839560	2943	/**
AnnaBridge	163:e59c8e839560	2944	* @}
AnnaBridge	163:e59c8e839560	2945	*/
AnnaBridge	163:e59c8e839560	2946
AnnaBridge	163:e59c8e839560	2947	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	2948	* @{
AnnaBridge	163:e59c8e839560	2949	*/
AnnaBridge	163:e59c8e839560	2950
AnnaBridge	163:e59c8e839560	2951	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
AnnaBridge	163:e59c8e839560	2952	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
AnnaBridge	163:e59c8e839560	2953	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
AnnaBridge	163:e59c8e839560	2954	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
AnnaBridge	163:e59c8e839560	2955	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
AnnaBridge	163:e59c8e839560	2956	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
AnnaBridge	163:e59c8e839560	2957
AnnaBridge	163:e59c8e839560	2958	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
AnnaBridge	163:e59c8e839560	2959	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
AnnaBridge	163:e59c8e839560	2960
AnnaBridge	163:e59c8e839560	2961	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
AnnaBridge	163:e59c8e839560	2962
AnnaBridge	163:e59c8e839560	2963	/**
AnnaBridge	163:e59c8e839560	2964	* @}
AnnaBridge	163:e59c8e839560	2965	*/
AnnaBridge	163:e59c8e839560	2966
AnnaBridge	163:e59c8e839560	2967	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	2968	* @{
AnnaBridge	163:e59c8e839560	2969	*/
AnnaBridge	163:e59c8e839560	2970	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
AnnaBridge	163:e59c8e839560	2971	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
AnnaBridge	163:e59c8e839560	2972	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
AnnaBridge	163:e59c8e839560	2973	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
AnnaBridge	163:e59c8e839560	2974	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
AnnaBridge	163:e59c8e839560	2975	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
AnnaBridge	163:e59c8e839560	2976	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
AnnaBridge	163:e59c8e839560	2977	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
AnnaBridge	163:e59c8e839560	2978	/**
AnnaBridge	163:e59c8e839560	2979	* @}
AnnaBridge	163:e59c8e839560	2980	*/
AnnaBridge	163:e59c8e839560	2981
AnnaBridge	163:e59c8e839560	2982	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	2983	* @{
AnnaBridge	163:e59c8e839560	2984	*/
AnnaBridge	163:e59c8e839560	2985
AnnaBridge	163:e59c8e839560	2986	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
AnnaBridge	163:e59c8e839560	2987	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
AnnaBridge	163:e59c8e839560	2988	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
AnnaBridge	163:e59c8e839560	2989
AnnaBridge	163:e59c8e839560	2990	/**
AnnaBridge	163:e59c8e839560	2991	* @}
AnnaBridge	163:e59c8e839560	2992	*/
AnnaBridge	163:e59c8e839560	2993
AnnaBridge	163:e59c8e839560	2994	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	2995	* @{
AnnaBridge	163:e59c8e839560	2996	*/
AnnaBridge	163:e59c8e839560	2997
AnnaBridge	163:e59c8e839560	2998	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
AnnaBridge	163:e59c8e839560	2999	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
AnnaBridge	163:e59c8e839560	3000	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
AnnaBridge	163:e59c8e839560	3001	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
AnnaBridge	163:e59c8e839560	3002
AnnaBridge	163:e59c8e839560	3003	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
AnnaBridge	163:e59c8e839560	3004
AnnaBridge	163:e59c8e839560	3005	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
AnnaBridge	163:e59c8e839560	3006	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
AnnaBridge	163:e59c8e839560	3007
AnnaBridge	163:e59c8e839560	3008	/**
AnnaBridge	163:e59c8e839560	3009	* @}
AnnaBridge	163:e59c8e839560	3010	*/
AnnaBridge	163:e59c8e839560	3011
AnnaBridge	163:e59c8e839560	3012
AnnaBridge	163:e59c8e839560	3013	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	3014	* @{
AnnaBridge	163:e59c8e839560	3015	*/
AnnaBridge	163:e59c8e839560	3016
AnnaBridge	163:e59c8e839560	3017	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
AnnaBridge	163:e59c8e839560	3018	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
AnnaBridge	163:e59c8e839560	3019	#define __USART_ENABLE __HAL_USART_ENABLE
AnnaBridge	163:e59c8e839560	3020	#define __USART_DISABLE __HAL_USART_DISABLE
AnnaBridge	163:e59c8e839560	3021
AnnaBridge	163:e59c8e839560	3022	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
AnnaBridge	163:e59c8e839560	3023	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
AnnaBridge	163:e59c8e839560	3024
AnnaBridge	163:e59c8e839560	3025	/**
AnnaBridge	163:e59c8e839560	3026	* @}
AnnaBridge	163:e59c8e839560	3027	*/
AnnaBridge	163:e59c8e839560	3028
AnnaBridge	163:e59c8e839560	3029	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	3030	* @{
AnnaBridge	163:e59c8e839560	3031	*/
AnnaBridge	163:e59c8e839560	3032	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
AnnaBridge	163:e59c8e839560	3033
AnnaBridge	163:e59c8e839560	3034	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
AnnaBridge	163:e59c8e839560	3035	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
AnnaBridge	163:e59c8e839560	3036	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
AnnaBridge	163:e59c8e839560	3037	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
AnnaBridge	163:e59c8e839560	3038
AnnaBridge	163:e59c8e839560	3039	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
AnnaBridge	163:e59c8e839560	3040	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
AnnaBridge	163:e59c8e839560	3041	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
AnnaBridge	163:e59c8e839560	3042	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
AnnaBridge	163:e59c8e839560	3043
AnnaBridge	163:e59c8e839560	3044	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
AnnaBridge	163:e59c8e839560	3045	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
AnnaBridge	163:e59c8e839560	3046	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
AnnaBridge	163:e59c8e839560	3047	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge	163:e59c8e839560	3048	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge	163:e59c8e839560	3049	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	163:e59c8e839560	3050	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge	163:e59c8e839560	3051
AnnaBridge	163:e59c8e839560	3052	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
AnnaBridge	163:e59c8e839560	3053	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
AnnaBridge	163:e59c8e839560	3054	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
AnnaBridge	163:e59c8e839560	3055	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge	163:e59c8e839560	3056	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge	163:e59c8e839560	3057	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	163:e59c8e839560	3058	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge	163:e59c8e839560	3059	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
AnnaBridge	163:e59c8e839560	3060
AnnaBridge	163:e59c8e839560	3061	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
AnnaBridge	163:e59c8e839560	3062	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
AnnaBridge	163:e59c8e839560	3063	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
AnnaBridge	163:e59c8e839560	3064	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge	163:e59c8e839560	3065	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge	163:e59c8e839560	3066	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	163:e59c8e839560	3067	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge	163:e59c8e839560	3068	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
AnnaBridge	163:e59c8e839560	3069
AnnaBridge	163:e59c8e839560	3070	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
AnnaBridge	163:e59c8e839560	3071	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
AnnaBridge	163:e59c8e839560	3072
AnnaBridge	163:e59c8e839560	3073	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
AnnaBridge	163:e59c8e839560	3074	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
AnnaBridge	163:e59c8e839560	3075	/**
AnnaBridge	163:e59c8e839560	3076	* @}
AnnaBridge	163:e59c8e839560	3077	*/
AnnaBridge	163:e59c8e839560	3078
AnnaBridge	163:e59c8e839560	3079	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	3080	* @{
AnnaBridge	163:e59c8e839560	3081	*/
AnnaBridge	163:e59c8e839560	3082	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
AnnaBridge	163:e59c8e839560	3083	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
AnnaBridge	163:e59c8e839560	3084
AnnaBridge	163:e59c8e839560	3085	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
AnnaBridge	163:e59c8e839560	3086	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
AnnaBridge	163:e59c8e839560	3087
AnnaBridge	163:e59c8e839560	3088	#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
AnnaBridge	163:e59c8e839560	3089
AnnaBridge	163:e59c8e839560	3090	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
AnnaBridge	163:e59c8e839560	3091	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
AnnaBridge	163:e59c8e839560	3092	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
AnnaBridge	163:e59c8e839560	3093	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
AnnaBridge	163:e59c8e839560	3094	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
AnnaBridge	163:e59c8e839560	3095	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
AnnaBridge	163:e59c8e839560	3096	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
AnnaBridge	163:e59c8e839560	3097	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
AnnaBridge	163:e59c8e839560	3098	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
AnnaBridge	163:e59c8e839560	3099	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
AnnaBridge	163:e59c8e839560	3100	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
AnnaBridge	163:e59c8e839560	3101	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
AnnaBridge	163:e59c8e839560	3102
AnnaBridge	163:e59c8e839560	3103	#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
AnnaBridge	163:e59c8e839560	3104	/**
AnnaBridge	163:e59c8e839560	3105	* @}
AnnaBridge	163:e59c8e839560	3106	*/
AnnaBridge	163:e59c8e839560	3107
AnnaBridge	163:e59c8e839560	3108	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	3109	* @{
AnnaBridge	163:e59c8e839560	3110	*/
AnnaBridge	163:e59c8e839560	3111
AnnaBridge	163:e59c8e839560	3112	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
AnnaBridge	163:e59c8e839560	3113	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
AnnaBridge	163:e59c8e839560	3114	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
AnnaBridge	163:e59c8e839560	3115	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge	163:e59c8e839560	3116	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
AnnaBridge	163:e59c8e839560	3117	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
AnnaBridge	163:e59c8e839560	3118	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
AnnaBridge	163:e59c8e839560	3119
AnnaBridge	163:e59c8e839560	3120	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
AnnaBridge	163:e59c8e839560	3121	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
AnnaBridge	163:e59c8e839560	3122	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
AnnaBridge	163:e59c8e839560	3123	/**
AnnaBridge	163:e59c8e839560	3124	* @}
AnnaBridge	163:e59c8e839560	3125	*/
AnnaBridge	163:e59c8e839560	3126
AnnaBridge	163:e59c8e839560	3127	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	3128	* @{
AnnaBridge	163:e59c8e839560	3129	*/
AnnaBridge	163:e59c8e839560	3130	#define __HAL_LTDC_LAYER LTDC_LAYER
AnnaBridge	168:b9e159c1930a	3131	#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
AnnaBridge	163:e59c8e839560	3132	/**
AnnaBridge	163:e59c8e839560	3133	* @}
AnnaBridge	163:e59c8e839560	3134	*/
AnnaBridge	163:e59c8e839560	3135
AnnaBridge	163:e59c8e839560	3136	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	3137	* @{
AnnaBridge	163:e59c8e839560	3138	*/
AnnaBridge	163:e59c8e839560	3139	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
AnnaBridge	163:e59c8e839560	3140	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
AnnaBridge	163:e59c8e839560	3141	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
AnnaBridge	163:e59c8e839560	3142	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
AnnaBridge	163:e59c8e839560	3143	#define SAI_STREOMODE SAI_STEREOMODE
AnnaBridge	163:e59c8e839560	3144	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
AnnaBridge	163:e59c8e839560	3145	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
AnnaBridge	163:e59c8e839560	3146	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
AnnaBridge	163:e59c8e839560	3147	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
AnnaBridge	163:e59c8e839560	3148	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
AnnaBridge	163:e59c8e839560	3149	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
AnnaBridge	163:e59c8e839560	3150	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
AnnaBridge	163:e59c8e839560	3151	#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
AnnaBridge	163:e59c8e839560	3152	#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
AnnaBridge	163:e59c8e839560	3153	/**
AnnaBridge	163:e59c8e839560	3154	* @}
AnnaBridge	163:e59c8e839560	3155	*/
AnnaBridge	163:e59c8e839560	3156
AnnaBridge	163:e59c8e839560	3157
AnnaBridge	163:e59c8e839560	3158	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
AnnaBridge	163:e59c8e839560	3159	* @{
AnnaBridge	163:e59c8e839560	3160	*/
AnnaBridge	163:e59c8e839560	3161
AnnaBridge	163:e59c8e839560	3162	/**
AnnaBridge	163:e59c8e839560	3163	* @}
AnnaBridge	163:e59c8e839560	3164	*/
AnnaBridge	163:e59c8e839560	3165
AnnaBridge	163:e59c8e839560	3166	#ifdef __cplusplus
AnnaBridge	163:e59c8e839560	3167	}
AnnaBridge	163:e59c8e839560	3168	#endif
AnnaBridge	163:e59c8e839560	3169
AnnaBridge	163:e59c8e839560	3170	#endif /* ___STM32_HAL_LEGACY */
AnnaBridge	163:e59c8e839560	3171
AnnaBridge	163:e59c8e839560	3172	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	163:e59c8e839560	3173