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TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/mbed_rtx.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Child:
172:65be27845400
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /* mbed Microcontroller Library
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2017 ARM Limited
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 171:3a7713b1edbc 5 * you may not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 6 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 171:3a7713b1edbc 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 13 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 14 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 15 */
AnnaBridge 171:3a7713b1edbc 16
AnnaBridge 171:3a7713b1edbc 17 #ifndef MBED_MBED_RTX_H
AnnaBridge 171:3a7713b1edbc 18 #define MBED_MBED_RTX_H
AnnaBridge 171:3a7713b1edbc 19
AnnaBridge 171:3a7713b1edbc 20 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 21
AnnaBridge 171:3a7713b1edbc 22 #ifndef INITIAL_SP
AnnaBridge 171:3a7713b1edbc 23
AnnaBridge 171:3a7713b1edbc 24 #if (defined(TARGET_STM32L475VG) ||\
AnnaBridge 171:3a7713b1edbc 25 defined(TARGET_STM32L476RG) ||\
AnnaBridge 171:3a7713b1edbc 26 defined(TARGET_STM32L476JG) ||\
AnnaBridge 171:3a7713b1edbc 27 defined(TARGET_STM32L476VG) ||\
AnnaBridge 171:3a7713b1edbc 28 defined(TARGET_STM32L486RG) ||\
AnnaBridge 171:3a7713b1edbc 29 defined(TARGET_STM32L471QG))
AnnaBridge 171:3a7713b1edbc 30 /* only GCC_ARM and IAR toolchains have the stack on SRAM2 */
AnnaBridge 171:3a7713b1edbc 31 #if (((defined(__GNUC__) && !defined(__CC_ARM)) ||\
AnnaBridge 171:3a7713b1edbc 32 defined(__IAR_SYSTEMS_ICC__ )) &&\
AnnaBridge 171:3a7713b1edbc 33 defined(TWO_RAM_REGIONS))
AnnaBridge 171:3a7713b1edbc 34 #define INITIAL_SP (0x10008000UL)
AnnaBridge 171:3a7713b1edbc 35 #else
AnnaBridge 171:3a7713b1edbc 36 #define INITIAL_SP (0x20018000UL)
AnnaBridge 171:3a7713b1edbc 37 #endif /* toolchains */
AnnaBridge 171:3a7713b1edbc 38
AnnaBridge 171:3a7713b1edbc 39 #elif (defined(TARGET_STM32F051R8) ||\
AnnaBridge 171:3a7713b1edbc 40 defined(TARGET_STM32F100RB) ||\
AnnaBridge 171:3a7713b1edbc 41 defined(TARGET_STM32L031K6) ||\
AnnaBridge 171:3a7713b1edbc 42 defined(TARGET_STM32L053C8) ||\
AnnaBridge 171:3a7713b1edbc 43 defined(TARGET_STM32L053R8))
AnnaBridge 171:3a7713b1edbc 44 #define INITIAL_SP (0x20002000UL)
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 #elif (defined(TARGET_STM32F303K8) ||\
AnnaBridge 171:3a7713b1edbc 47 defined(TARGET_STM32F334C8) ||\
AnnaBridge 171:3a7713b1edbc 48 defined(TARGET_STM32F334R8))
AnnaBridge 171:3a7713b1edbc 49 #define INITIAL_SP (0x20003000UL)
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 #elif (defined(TARGET_STM32F070RB) ||\
AnnaBridge 171:3a7713b1edbc 52 defined(TARGET_STM32F072RB) ||\
AnnaBridge 171:3a7713b1edbc 53 defined(TARGET_STM32F302R8))
AnnaBridge 171:3a7713b1edbc 54 #define INITIAL_SP (0x20004000UL)
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 #elif (defined(TARGET_STM32F103RB) ||\
AnnaBridge 171:3a7713b1edbc 57 defined(TARGET_STM32F103C8) ||\
AnnaBridge 171:3a7713b1edbc 58 defined(TARGET_STM32L072CZ) ||\
AnnaBridge 171:3a7713b1edbc 59 defined(TARGET_STM32L073RZ) ||\
AnnaBridge 171:3a7713b1edbc 60 defined(TARGET_STM32L0x2xZ))
AnnaBridge 171:3a7713b1edbc 61 #define INITIAL_SP (0x20005000UL)
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 #elif (defined(TARGET_STM32F091RC) ||\
AnnaBridge 171:3a7713b1edbc 64 defined(TARGET_STM32F410RB) ||\
AnnaBridge 171:3a7713b1edbc 65 defined(TARGET_STM32L151CBA)||\
AnnaBridge 171:3a7713b1edbc 66 defined(TARGET_STM32L151CC) ||\
AnnaBridge 171:3a7713b1edbc 67 defined(TARGET_STM32L151RC) ||\
AnnaBridge 171:3a7713b1edbc 68 defined(TARGET_STM32L152RC))
AnnaBridge 171:3a7713b1edbc 69 #define INITIAL_SP (0x20008000UL)
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 #elif defined(TARGET_STM32F303VC)
AnnaBridge 171:3a7713b1edbc 72 #define INITIAL_SP (0x2000A000UL)
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 #elif defined(TARGET_STM32L443RC)
AnnaBridge 171:3a7713b1edbc 75 #define INITIAL_SP (0x2000C000UL)
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 #elif (defined(TARGET_STM32F303RE) ||\
AnnaBridge 171:3a7713b1edbc 78 defined(TARGET_STM32F303ZE) ||\
AnnaBridge 171:3a7713b1edbc 79 defined(TARGET_STM32F401VC) ||\
AnnaBridge 171:3a7713b1edbc 80 defined(TARGET_STM32L432KC) ||\
AnnaBridge 171:3a7713b1edbc 81 defined(TARGET_STM32L433RC))
AnnaBridge 171:3a7713b1edbc 82 #define INITIAL_SP (0x20010000UL)
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 #elif defined(TARGET_STM32L152RE)
AnnaBridge 171:3a7713b1edbc 85 #define INITIAL_SP (0x20014000UL)
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 #elif (defined(TARGET_STM32F401RE) ||\
AnnaBridge 171:3a7713b1edbc 88 defined(TARGET_STM32F401VE))
AnnaBridge 171:3a7713b1edbc 89 #define INITIAL_SP (0x20018000UL)
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 #elif (defined(TARGET_STM32F207ZG) ||\
AnnaBridge 171:3a7713b1edbc 92 defined(TARGET_STM32F405RG) ||\
AnnaBridge 171:3a7713b1edbc 93 defined(TARGET_STM32F407VG) ||\
AnnaBridge 171:3a7713b1edbc 94 defined(TARGET_STM32F411RE) ||\
AnnaBridge 171:3a7713b1edbc 95 defined(TARGET_STM32F446RE) ||\
AnnaBridge 171:3a7713b1edbc 96 defined(TARGET_STM32F446VE) ||\
AnnaBridge 171:3a7713b1edbc 97 defined(TARGET_STM32F446ZE))
AnnaBridge 171:3a7713b1edbc 98 #define INITIAL_SP (0x20020000UL)
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 #elif (defined(TARGET_STM32F429ZI) ||\
AnnaBridge 171:3a7713b1edbc 101 defined(TARGET_STM32F437VG) ||\
AnnaBridge 171:3a7713b1edbc 102 defined(TARGET_STM32F439VI) ||\
AnnaBridge 171:3a7713b1edbc 103 defined(TARGET_STM32F439ZI))
AnnaBridge 171:3a7713b1edbc 104 #define INITIAL_SP (0x20030000UL)
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 #elif defined(TARGET_STM32F412ZG)
AnnaBridge 171:3a7713b1edbc 107 #define INITIAL_SP (0x20040000UL)
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109 #elif (defined(TARGET_STM32F413ZH) ||\
AnnaBridge 171:3a7713b1edbc 110 defined(TARGET_STM32F469NI) ||\
AnnaBridge 171:3a7713b1edbc 111 defined(TARGET_STM32F746NG) ||\
AnnaBridge 171:3a7713b1edbc 112 defined(TARGET_STM32F746ZG) ||\
AnnaBridge 171:3a7713b1edbc 113 defined(TARGET_STM32F756ZG) ||\
AnnaBridge 171:3a7713b1edbc 114 defined(TARGET_STM32L496AG) ||\
AnnaBridge 171:3a7713b1edbc 115 defined(TARGET_STM32L496ZG))
AnnaBridge 171:3a7713b1edbc 116 #define INITIAL_SP (0x20050000UL)
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 #elif (defined(TARGET_STM32F767ZI) ||\
AnnaBridge 171:3a7713b1edbc 119 defined(TARGET_STM32F769NI))
AnnaBridge 171:3a7713b1edbc 120 #define INITIAL_SP (0x20080000UL)
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 #elif defined(TARGET_STM32L4R5ZI)
AnnaBridge 171:3a7713b1edbc 123 #define INITIAL_SP (0x200A0000UL)
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 #else
AnnaBridge 171:3a7713b1edbc 126 #error "INITIAL_SP is not defined for this target in the mbed_rtx.h file"
AnnaBridge 171:3a7713b1edbc 127 #endif
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 #endif // INITIAL_SP
AnnaBridge 171:3a7713b1edbc 130 #if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION) && defined(TWO_RAM_REGIONS))
AnnaBridge 171:3a7713b1edbc 131 extern uint32_t __StackLimit[];
AnnaBridge 171:3a7713b1edbc 132 extern uint32_t __StackTop[];
AnnaBridge 171:3a7713b1edbc 133 extern uint32_t __end__[];
AnnaBridge 171:3a7713b1edbc 134 extern uint32_t __HeapLimit[];
AnnaBridge 171:3a7713b1edbc 135 #define HEAP_START ((unsigned char*)__end__)
AnnaBridge 171:3a7713b1edbc 136 #define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START))
AnnaBridge 171:3a7713b1edbc 137 #define ISR_STACK_START ((unsigned char*)__StackLimit)
AnnaBridge 171:3a7713b1edbc 138 #define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit))
AnnaBridge 171:3a7713b1edbc 139 #endif
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141 #if (defined(TARGET_STM32F070RB) || defined(TARGET_STM32F072RB))
AnnaBridge 171:3a7713b1edbc 142 #if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION))
AnnaBridge 171:3a7713b1edbc 143 extern uint32_t __StackLimit;
AnnaBridge 171:3a7713b1edbc 144 extern uint32_t __StackTop;
AnnaBridge 171:3a7713b1edbc 145 extern uint32_t __end__;
AnnaBridge 171:3a7713b1edbc 146 extern uint32_t __HeapLimit;
AnnaBridge 171:3a7713b1edbc 147 #define HEAP_START ((unsigned char*) &__end__)
AnnaBridge 171:3a7713b1edbc 148 #define HEAP_SIZE ((uint32_t)((uint32_t) &__HeapLimit - (uint32_t) HEAP_START))
AnnaBridge 171:3a7713b1edbc 149 #define ISR_STACK_START ((unsigned char*) &__StackLimit)
AnnaBridge 171:3a7713b1edbc 150 #define ISR_STACK_SIZE ((uint32_t)((uint32_t) &__StackTop - (uint32_t) &__StackLimit))
AnnaBridge 171:3a7713b1edbc 151 #endif
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 #ifdef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE
AnnaBridge 171:3a7713b1edbc 154 #undef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE
AnnaBridge 171:3a7713b1edbc 155 #endif
AnnaBridge 171:3a7713b1edbc 156 #define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 3072
AnnaBridge 171:3a7713b1edbc 157
AnnaBridge 171:3a7713b1edbc 158 #endif
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 #endif // MBED_MBED_RTX_H