mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F207ZG/TOOLCHAIN_GCC_ARM/stm32f2xx_hal_tim.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f2xx_hal_tim.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @version V1.2.1
AnnaBridge 171:3a7713b1edbc 6 * @date 14-April-2017
AnnaBridge 171:3a7713b1edbc 7 * @brief Header file of TIM HAL module.
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 * @attention
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 12 *
AnnaBridge 171:3a7713b1edbc 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 14 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 19 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 21 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 22 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 23 *
AnnaBridge 171:3a7713b1edbc 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 34 *
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 36 */
AnnaBridge 171:3a7713b1edbc 37
AnnaBridge 171:3a7713b1edbc 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 39 #ifndef __STM32F2xx_HAL_TIM_H
AnnaBridge 171:3a7713b1edbc 40 #define __STM32F2xx_HAL_TIM_H
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 43 extern "C" {
AnnaBridge 171:3a7713b1edbc 44 #endif
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 47 #include "stm32f2xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /** @addtogroup STM32F2xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 50 * @{
AnnaBridge 171:3a7713b1edbc 51 */
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /** @addtogroup TIM
AnnaBridge 171:3a7713b1edbc 54 * @{
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 58 /** @defgroup TIM_Exported_Types TIM Exported Types
AnnaBridge 171:3a7713b1edbc 59 * @{
AnnaBridge 171:3a7713b1edbc 60 */
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 /**
AnnaBridge 171:3a7713b1edbc 63 * @brief TIM Time base Configuration Structure definition
AnnaBridge 171:3a7713b1edbc 64 */
AnnaBridge 171:3a7713b1edbc 65 typedef struct
AnnaBridge 171:3a7713b1edbc 66 {
AnnaBridge 171:3a7713b1edbc 67 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge 171:3a7713b1edbc 68 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge 171:3a7713b1edbc 71 This parameter can be a value of @ref TIM_Counter_Mode */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 uint32_t Period; /*!< Specifies the period value to be loaded into the active
AnnaBridge 171:3a7713b1edbc 74 Auto-Reload Register at the next update event.
AnnaBridge 171:3a7713b1edbc 75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge 171:3a7713b1edbc 78 This parameter can be a value of @ref TIM_ClockDivision */
AnnaBridge 171:3a7713b1edbc 79
AnnaBridge 171:3a7713b1edbc 80 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge 171:3a7713b1edbc 81 reaches zero, an update event is generated and counting restarts
AnnaBridge 171:3a7713b1edbc 82 from the RCR value (N).
AnnaBridge 171:3a7713b1edbc 83 This means in PWM mode that (N+1) corresponds to:
AnnaBridge 171:3a7713b1edbc 84 - the number of PWM periods in edge-aligned mode
AnnaBridge 171:3a7713b1edbc 85 - the number of half PWM period in center-aligned mode
AnnaBridge 171:3a7713b1edbc 86 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge 171:3a7713b1edbc 87 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 171:3a7713b1edbc 88
AnnaBridge 171:3a7713b1edbc 89 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
AnnaBridge 171:3a7713b1edbc 90 This parameter can be a value of @ref TIM_AutoReloadPreload */
AnnaBridge 171:3a7713b1edbc 91 } TIM_Base_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 /**
AnnaBridge 171:3a7713b1edbc 94 * @brief TIM Output Compare Configuration Structure definition
AnnaBridge 171:3a7713b1edbc 95 */
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 typedef struct
AnnaBridge 171:3a7713b1edbc 98 {
AnnaBridge 171:3a7713b1edbc 99 uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge 171:3a7713b1edbc 100 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 171:3a7713b1edbc 103 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 171:3a7713b1edbc 104
AnnaBridge 171:3a7713b1edbc 105 uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge 171:3a7713b1edbc 106 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge 171:3a7713b1edbc 109 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
AnnaBridge 171:3a7713b1edbc 110 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
AnnaBridge 171:3a7713b1edbc 113 This parameter can be a value of @ref TIM_Output_Fast_State
AnnaBridge 171:3a7713b1edbc 114 @note This parameter is valid only in PWM1 and PWM2 mode. */
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 171:3a7713b1edbc 118 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
AnnaBridge 171:3a7713b1edbc 119 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 171:3a7713b1edbc 122 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
AnnaBridge 171:3a7713b1edbc 123 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 171:3a7713b1edbc 124 } TIM_OC_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 /**
AnnaBridge 171:3a7713b1edbc 127 * @brief TIM One Pulse Mode Configuration Structure definition
AnnaBridge 171:3a7713b1edbc 128 */
AnnaBridge 171:3a7713b1edbc 129 typedef struct
AnnaBridge 171:3a7713b1edbc 130 {
AnnaBridge 171:3a7713b1edbc 131 uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge 171:3a7713b1edbc 132 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 171:3a7713b1edbc 135 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge 171:3a7713b1edbc 138 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge 171:3a7713b1edbc 141 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
AnnaBridge 171:3a7713b1edbc 142 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 171:3a7713b1edbc 143
AnnaBridge 171:3a7713b1edbc 144 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 171:3a7713b1edbc 145 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
AnnaBridge 171:3a7713b1edbc 146 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 171:3a7713b1edbc 149 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
AnnaBridge 171:3a7713b1edbc 150 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 171:3a7713b1edbc 153 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge 171:3a7713b1edbc 156 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 171:3a7713b1edbc 157
AnnaBridge 171:3a7713b1edbc 158 uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge 171:3a7713b1edbc 159 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 171:3a7713b1edbc 160 } TIM_OnePulse_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 /**
AnnaBridge 171:3a7713b1edbc 164 * @brief TIM Input Capture Configuration Structure definition
AnnaBridge 171:3a7713b1edbc 165 */
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 typedef struct
AnnaBridge 171:3a7713b1edbc 168 {
AnnaBridge 171:3a7713b1edbc 169 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 171:3a7713b1edbc 170 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge 171:3a7713b1edbc 173 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 171:3a7713b1edbc 176 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge 171:3a7713b1edbc 179 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 171:3a7713b1edbc 180 } TIM_IC_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 181
AnnaBridge 171:3a7713b1edbc 182 /**
AnnaBridge 171:3a7713b1edbc 183 * @brief TIM Encoder Configuration Structure definition
AnnaBridge 171:3a7713b1edbc 184 */
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 typedef struct
AnnaBridge 171:3a7713b1edbc 187 {
AnnaBridge 171:3a7713b1edbc 188 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
AnnaBridge 171:3a7713b1edbc 189 This parameter can be a value of @ref TIM_Encoder_Mode */
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 171:3a7713b1edbc 192 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 uint32_t IC1Selection; /*!< Specifies the input.
AnnaBridge 171:3a7713b1edbc 195 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 171:3a7713b1edbc 198 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 uint32_t IC1Filter; /*!< Specifies the input capture filter.
AnnaBridge 171:3a7713b1edbc 201 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 171:3a7713b1edbc 204 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 171:3a7713b1edbc 205
AnnaBridge 171:3a7713b1edbc 206 uint32_t IC2Selection; /*!< Specifies the input.
AnnaBridge 171:3a7713b1edbc 207 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 171:3a7713b1edbc 210 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 uint32_t IC2Filter; /*!< Specifies the input capture filter.
AnnaBridge 171:3a7713b1edbc 213 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 171:3a7713b1edbc 214 } TIM_Encoder_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /**
AnnaBridge 171:3a7713b1edbc 217 * @brief Clock Configuration Handle Structure definition
AnnaBridge 171:3a7713b1edbc 218 */
AnnaBridge 171:3a7713b1edbc 219 typedef struct
AnnaBridge 171:3a7713b1edbc 220 {
AnnaBridge 171:3a7713b1edbc 221 uint32_t ClockSource; /*!< TIM clock sources.
AnnaBridge 171:3a7713b1edbc 222 This parameter can be a value of @ref TIM_Clock_Source */
AnnaBridge 171:3a7713b1edbc 223 uint32_t ClockPolarity; /*!< TIM clock polarity.
AnnaBridge 171:3a7713b1edbc 224 This parameter can be a value of @ref TIM_Clock_Polarity */
AnnaBridge 171:3a7713b1edbc 225 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
AnnaBridge 171:3a7713b1edbc 226 This parameter can be a value of @ref TIM_Clock_Prescaler */
AnnaBridge 171:3a7713b1edbc 227 uint32_t ClockFilter; /*!< TIM clock filter.
AnnaBridge 171:3a7713b1edbc 228 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 171:3a7713b1edbc 229 }TIM_ClockConfigTypeDef;
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /**
AnnaBridge 171:3a7713b1edbc 232 * @brief Clear Input Configuration Handle Structure definition
AnnaBridge 171:3a7713b1edbc 233 */
AnnaBridge 171:3a7713b1edbc 234 typedef struct
AnnaBridge 171:3a7713b1edbc 235 {
AnnaBridge 171:3a7713b1edbc 236 uint32_t ClearInputState; /*!< TIM clear Input state.
AnnaBridge 171:3a7713b1edbc 237 This parameter can be ENABLE or DISABLE */
AnnaBridge 171:3a7713b1edbc 238 uint32_t ClearInputSource; /*!< TIM clear Input sources.
AnnaBridge 171:3a7713b1edbc 239 This parameter can be a value of @ref TIM_ClearInput_Source */
AnnaBridge 171:3a7713b1edbc 240 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
AnnaBridge 171:3a7713b1edbc 241 This parameter can be a value of @ref TIM_ClearInput_Polarity */
AnnaBridge 171:3a7713b1edbc 242 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
AnnaBridge 171:3a7713b1edbc 243 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
AnnaBridge 171:3a7713b1edbc 244 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
AnnaBridge 171:3a7713b1edbc 245 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 171:3a7713b1edbc 246 }TIM_ClearInputConfigTypeDef;
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 /**
AnnaBridge 171:3a7713b1edbc 249 * @brief TIM Slave configuration Structure definition
AnnaBridge 171:3a7713b1edbc 250 */
AnnaBridge 171:3a7713b1edbc 251 typedef struct {
AnnaBridge 171:3a7713b1edbc 252 uint32_t SlaveMode; /*!< Slave mode selection
AnnaBridge 171:3a7713b1edbc 253 This parameter can be a value of @ref TIM_Slave_Mode */
AnnaBridge 171:3a7713b1edbc 254 uint32_t InputTrigger; /*!< Input Trigger source
AnnaBridge 171:3a7713b1edbc 255 This parameter can be a value of @ref TIM_Trigger_Selection */
AnnaBridge 171:3a7713b1edbc 256 uint32_t TriggerPolarity; /*!< Input Trigger polarity
AnnaBridge 171:3a7713b1edbc 257 This parameter can be a value of @ref TIM_Trigger_Polarity */
AnnaBridge 171:3a7713b1edbc 258 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
AnnaBridge 171:3a7713b1edbc 259 This parameter can be a value of @ref TIM_Trigger_Prescaler */
AnnaBridge 171:3a7713b1edbc 260 uint32_t TriggerFilter; /*!< Input trigger filter
AnnaBridge 171:3a7713b1edbc 261 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 }TIM_SlaveConfigTypeDef;
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /**
AnnaBridge 171:3a7713b1edbc 266 * @brief HAL State structures definition
AnnaBridge 171:3a7713b1edbc 267 */
AnnaBridge 171:3a7713b1edbc 268 typedef enum
AnnaBridge 171:3a7713b1edbc 269 {
AnnaBridge 171:3a7713b1edbc 270 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
AnnaBridge 171:3a7713b1edbc 271 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
AnnaBridge 171:3a7713b1edbc 272 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
AnnaBridge 171:3a7713b1edbc 273 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
AnnaBridge 171:3a7713b1edbc 274 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
AnnaBridge 171:3a7713b1edbc 275 }HAL_TIM_StateTypeDef;
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 /**
AnnaBridge 171:3a7713b1edbc 278 * @brief HAL Active channel structures definition
AnnaBridge 171:3a7713b1edbc 279 */
AnnaBridge 171:3a7713b1edbc 280 typedef enum
AnnaBridge 171:3a7713b1edbc 281 {
AnnaBridge 171:3a7713b1edbc 282 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
AnnaBridge 171:3a7713b1edbc 283 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
AnnaBridge 171:3a7713b1edbc 284 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
AnnaBridge 171:3a7713b1edbc 285 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
AnnaBridge 171:3a7713b1edbc 286 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
AnnaBridge 171:3a7713b1edbc 287 }HAL_TIM_ActiveChannel;
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 /**
AnnaBridge 171:3a7713b1edbc 290 * @brief TIM Time Base Handle Structure definition
AnnaBridge 171:3a7713b1edbc 291 */
AnnaBridge 171:3a7713b1edbc 292 typedef struct
AnnaBridge 171:3a7713b1edbc 293 {
AnnaBridge 171:3a7713b1edbc 294 TIM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 171:3a7713b1edbc 295 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
AnnaBridge 171:3a7713b1edbc 296 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
AnnaBridge 171:3a7713b1edbc 297 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
AnnaBridge 171:3a7713b1edbc 298 This array is accessed by a @ref DMA_Handle_index */
AnnaBridge 171:3a7713b1edbc 299 HAL_LockTypeDef Lock; /*!< Locking object */
AnnaBridge 171:3a7713b1edbc 300 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
AnnaBridge 171:3a7713b1edbc 301 }TIM_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 302 /**
AnnaBridge 171:3a7713b1edbc 303 * @}
AnnaBridge 171:3a7713b1edbc 304 */
AnnaBridge 171:3a7713b1edbc 305
AnnaBridge 171:3a7713b1edbc 306 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 307 /** @defgroup TIM_Exported_Constants TIM Exported Constants
AnnaBridge 171:3a7713b1edbc 308 * @{
AnnaBridge 171:3a7713b1edbc 309 */
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
AnnaBridge 171:3a7713b1edbc 312 * @{
AnnaBridge 171:3a7713b1edbc 313 */
AnnaBridge 171:3a7713b1edbc 314 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
AnnaBridge 171:3a7713b1edbc 315 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
AnnaBridge 171:3a7713b1edbc 316 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
AnnaBridge 171:3a7713b1edbc 317 /**
AnnaBridge 171:3a7713b1edbc 318 * @}
AnnaBridge 171:3a7713b1edbc 319 */
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
AnnaBridge 171:3a7713b1edbc 322 * @{
AnnaBridge 171:3a7713b1edbc 323 */
AnnaBridge 171:3a7713b1edbc 324 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
AnnaBridge 171:3a7713b1edbc 325 #define TIM_ETRPOLARITY_NONINVERTED 0x0000U /*!< Polarity for ETR source */
AnnaBridge 171:3a7713b1edbc 326 /**
AnnaBridge 171:3a7713b1edbc 327 * @}
AnnaBridge 171:3a7713b1edbc 328 */
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
AnnaBridge 171:3a7713b1edbc 331 * @{
AnnaBridge 171:3a7713b1edbc 332 */
AnnaBridge 171:3a7713b1edbc 333 #define TIM_ETRPRESCALER_DIV1 0x0000U /*!< No prescaler is used */
AnnaBridge 171:3a7713b1edbc 334 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
AnnaBridge 171:3a7713b1edbc 335 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
AnnaBridge 171:3a7713b1edbc 336 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
AnnaBridge 171:3a7713b1edbc 337 /**
AnnaBridge 171:3a7713b1edbc 338 * @}
AnnaBridge 171:3a7713b1edbc 339 */
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341 /** @defgroup TIM_Counter_Mode TIM Counter Mode
AnnaBridge 171:3a7713b1edbc 342 * @{
AnnaBridge 171:3a7713b1edbc 343 */
AnnaBridge 171:3a7713b1edbc 344 #define TIM_COUNTERMODE_UP 0x0000U
AnnaBridge 171:3a7713b1edbc 345 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
AnnaBridge 171:3a7713b1edbc 346 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
AnnaBridge 171:3a7713b1edbc 347 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
AnnaBridge 171:3a7713b1edbc 348 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
AnnaBridge 171:3a7713b1edbc 349 /**
AnnaBridge 171:3a7713b1edbc 350 * @}
AnnaBridge 171:3a7713b1edbc 351 */
AnnaBridge 171:3a7713b1edbc 352
AnnaBridge 171:3a7713b1edbc 353 /** @defgroup TIM_ClockDivision TIM Clock Division
AnnaBridge 171:3a7713b1edbc 354 * @{
AnnaBridge 171:3a7713b1edbc 355 */
AnnaBridge 171:3a7713b1edbc 356 #define TIM_CLOCKDIVISION_DIV1 0x0000U
AnnaBridge 171:3a7713b1edbc 357 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
AnnaBridge 171:3a7713b1edbc 358 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
AnnaBridge 171:3a7713b1edbc 359 /**
AnnaBridge 171:3a7713b1edbc 360 * @}
AnnaBridge 171:3a7713b1edbc 361 */
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
AnnaBridge 171:3a7713b1edbc 364 * @{
AnnaBridge 171:3a7713b1edbc 365 */
AnnaBridge 171:3a7713b1edbc 366 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U /*!< TIMx_ARR register is not buffered */
AnnaBridge 171:3a7713b1edbc 367 #define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
AnnaBridge 171:3a7713b1edbc 368
AnnaBridge 171:3a7713b1edbc 369 /**
AnnaBridge 171:3a7713b1edbc 370 * @}
AnnaBridge 171:3a7713b1edbc 371 */
AnnaBridge 171:3a7713b1edbc 372
AnnaBridge 171:3a7713b1edbc 373 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
AnnaBridge 171:3a7713b1edbc 374 * @{
AnnaBridge 171:3a7713b1edbc 375 */
AnnaBridge 171:3a7713b1edbc 376 #define TIM_OCMODE_TIMING 0x0000U
AnnaBridge 171:3a7713b1edbc 377 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
AnnaBridge 171:3a7713b1edbc 378 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
AnnaBridge 171:3a7713b1edbc 379 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
AnnaBridge 171:3a7713b1edbc 380 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
AnnaBridge 171:3a7713b1edbc 381 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
AnnaBridge 171:3a7713b1edbc 382 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
AnnaBridge 171:3a7713b1edbc 383 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 /**
AnnaBridge 171:3a7713b1edbc 386 * @}
AnnaBridge 171:3a7713b1edbc 387 */
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
AnnaBridge 171:3a7713b1edbc 390 * @{
AnnaBridge 171:3a7713b1edbc 391 */
AnnaBridge 171:3a7713b1edbc 392 #define TIM_OCFAST_DISABLE 0x0000U
AnnaBridge 171:3a7713b1edbc 393 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
AnnaBridge 171:3a7713b1edbc 394 /**
AnnaBridge 171:3a7713b1edbc 395 * @}
AnnaBridge 171:3a7713b1edbc 396 */
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
AnnaBridge 171:3a7713b1edbc 399 * @{
AnnaBridge 171:3a7713b1edbc 400 */
AnnaBridge 171:3a7713b1edbc 401 #define TIM_OCPOLARITY_HIGH 0x0000U
AnnaBridge 171:3a7713b1edbc 402 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
AnnaBridge 171:3a7713b1edbc 403 /**
AnnaBridge 171:3a7713b1edbc 404 * @}
AnnaBridge 171:3a7713b1edbc 405 */
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
AnnaBridge 171:3a7713b1edbc 408 * @{
AnnaBridge 171:3a7713b1edbc 409 */
AnnaBridge 171:3a7713b1edbc 410 #define TIM_OCNPOLARITY_HIGH 0x0000U
AnnaBridge 171:3a7713b1edbc 411 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
AnnaBridge 171:3a7713b1edbc 412 /**
AnnaBridge 171:3a7713b1edbc 413 * @}
AnnaBridge 171:3a7713b1edbc 414 */
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
AnnaBridge 171:3a7713b1edbc 417 * @{
AnnaBridge 171:3a7713b1edbc 418 */
AnnaBridge 171:3a7713b1edbc 419 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
AnnaBridge 171:3a7713b1edbc 420 #define TIM_OCIDLESTATE_RESET 0x0000U
AnnaBridge 171:3a7713b1edbc 421 /**
AnnaBridge 171:3a7713b1edbc 422 * @}
AnnaBridge 171:3a7713b1edbc 423 */
AnnaBridge 171:3a7713b1edbc 424
AnnaBridge 171:3a7713b1edbc 425 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
AnnaBridge 171:3a7713b1edbc 426 * @{
AnnaBridge 171:3a7713b1edbc 427 */
AnnaBridge 171:3a7713b1edbc 428 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
AnnaBridge 171:3a7713b1edbc 429 #define TIM_OCNIDLESTATE_RESET 0x0000U
AnnaBridge 171:3a7713b1edbc 430 /**
AnnaBridge 171:3a7713b1edbc 431 * @}
AnnaBridge 171:3a7713b1edbc 432 */
AnnaBridge 171:3a7713b1edbc 433
AnnaBridge 171:3a7713b1edbc 434 /** @defgroup TIM_Channel TIM Channel
AnnaBridge 171:3a7713b1edbc 435 * @{
AnnaBridge 171:3a7713b1edbc 436 */
AnnaBridge 171:3a7713b1edbc 437 #define TIM_CHANNEL_1 0x0000U
AnnaBridge 171:3a7713b1edbc 438 #define TIM_CHANNEL_2 0x0004U
AnnaBridge 171:3a7713b1edbc 439 #define TIM_CHANNEL_3 0x0008U
AnnaBridge 171:3a7713b1edbc 440 #define TIM_CHANNEL_4 0x000CU
AnnaBridge 171:3a7713b1edbc 441 #define TIM_CHANNEL_ALL ((uint32_t)0x0018U)
AnnaBridge 171:3a7713b1edbc 442
AnnaBridge 171:3a7713b1edbc 443 /**
AnnaBridge 171:3a7713b1edbc 444 * @}
AnnaBridge 171:3a7713b1edbc 445 */
AnnaBridge 171:3a7713b1edbc 446
AnnaBridge 171:3a7713b1edbc 447 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
AnnaBridge 171:3a7713b1edbc 448 * @{
AnnaBridge 171:3a7713b1edbc 449 */
AnnaBridge 171:3a7713b1edbc 450 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
AnnaBridge 171:3a7713b1edbc 451 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
AnnaBridge 171:3a7713b1edbc 452 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
AnnaBridge 171:3a7713b1edbc 453 /**
AnnaBridge 171:3a7713b1edbc 454 * @}
AnnaBridge 171:3a7713b1edbc 455 */
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
AnnaBridge 171:3a7713b1edbc 458 * @{
AnnaBridge 171:3a7713b1edbc 459 */
AnnaBridge 171:3a7713b1edbc 460 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge 171:3a7713b1edbc 461 connected to IC1, IC2, IC3 or IC4, respectively */
AnnaBridge 171:3a7713b1edbc 462 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge 171:3a7713b1edbc 463 connected to IC2, IC1, IC4 or IC3, respectively */
AnnaBridge 171:3a7713b1edbc 464 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
AnnaBridge 171:3a7713b1edbc 465
AnnaBridge 171:3a7713b1edbc 466 /**
AnnaBridge 171:3a7713b1edbc 467 * @}
AnnaBridge 171:3a7713b1edbc 468 */
AnnaBridge 171:3a7713b1edbc 469
AnnaBridge 171:3a7713b1edbc 470 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
AnnaBridge 171:3a7713b1edbc 471 * @{
AnnaBridge 171:3a7713b1edbc 472 */
AnnaBridge 171:3a7713b1edbc 473 #define TIM_ICPSC_DIV1 0x0000U /*!< Capture performed each time an edge is detected on the capture input */
AnnaBridge 171:3a7713b1edbc 474 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
AnnaBridge 171:3a7713b1edbc 475 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
AnnaBridge 171:3a7713b1edbc 476 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
AnnaBridge 171:3a7713b1edbc 477 /**
AnnaBridge 171:3a7713b1edbc 478 * @}
AnnaBridge 171:3a7713b1edbc 479 */
AnnaBridge 171:3a7713b1edbc 480
AnnaBridge 171:3a7713b1edbc 481 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
AnnaBridge 171:3a7713b1edbc 482 * @{
AnnaBridge 171:3a7713b1edbc 483 */
AnnaBridge 171:3a7713b1edbc 484 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
AnnaBridge 171:3a7713b1edbc 485 #define TIM_OPMODE_REPETITIVE 0x0000U
AnnaBridge 171:3a7713b1edbc 486 /**
AnnaBridge 171:3a7713b1edbc 487 * @}
AnnaBridge 171:3a7713b1edbc 488 */
AnnaBridge 171:3a7713b1edbc 489
AnnaBridge 171:3a7713b1edbc 490 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
AnnaBridge 171:3a7713b1edbc 491 * @{
AnnaBridge 171:3a7713b1edbc 492 */
AnnaBridge 171:3a7713b1edbc 493 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
AnnaBridge 171:3a7713b1edbc 494 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
AnnaBridge 171:3a7713b1edbc 495 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 /**
AnnaBridge 171:3a7713b1edbc 498 * @}
AnnaBridge 171:3a7713b1edbc 499 */
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 /** @defgroup TIM_Interrupt_definition TIM Interrupt definition
AnnaBridge 171:3a7713b1edbc 502 * @{
AnnaBridge 171:3a7713b1edbc 503 */
AnnaBridge 171:3a7713b1edbc 504 #define TIM_IT_UPDATE (TIM_DIER_UIE)
AnnaBridge 171:3a7713b1edbc 505 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
AnnaBridge 171:3a7713b1edbc 506 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
AnnaBridge 171:3a7713b1edbc 507 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
AnnaBridge 171:3a7713b1edbc 508 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
AnnaBridge 171:3a7713b1edbc 509 #define TIM_IT_COM (TIM_DIER_COMIE)
AnnaBridge 171:3a7713b1edbc 510 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
AnnaBridge 171:3a7713b1edbc 511 #define TIM_IT_BREAK (TIM_DIER_BIE)
AnnaBridge 171:3a7713b1edbc 512 /**
AnnaBridge 171:3a7713b1edbc 513 * @}
AnnaBridge 171:3a7713b1edbc 514 */
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 /** @defgroup TIM_Commutation_Source TIM Commutation Source
AnnaBridge 171:3a7713b1edbc 517 * @{
AnnaBridge 171:3a7713b1edbc 518 */
AnnaBridge 171:3a7713b1edbc 519 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
AnnaBridge 171:3a7713b1edbc 520 #define TIM_COMMUTATION_SOFTWARE 0x0000U
AnnaBridge 171:3a7713b1edbc 521 /**
AnnaBridge 171:3a7713b1edbc 522 * @}
AnnaBridge 171:3a7713b1edbc 523 */
AnnaBridge 171:3a7713b1edbc 524
AnnaBridge 171:3a7713b1edbc 525 /** @defgroup TIM_DMA_sources TIM DMA sources
AnnaBridge 171:3a7713b1edbc 526 * @{
AnnaBridge 171:3a7713b1edbc 527 */
AnnaBridge 171:3a7713b1edbc 528 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
AnnaBridge 171:3a7713b1edbc 529 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
AnnaBridge 171:3a7713b1edbc 530 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
AnnaBridge 171:3a7713b1edbc 531 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
AnnaBridge 171:3a7713b1edbc 532 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
AnnaBridge 171:3a7713b1edbc 533 #define TIM_DMA_COM (TIM_DIER_COMDE)
AnnaBridge 171:3a7713b1edbc 534 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
AnnaBridge 171:3a7713b1edbc 535 /**
AnnaBridge 171:3a7713b1edbc 536 * @}
AnnaBridge 171:3a7713b1edbc 537 */
AnnaBridge 171:3a7713b1edbc 538
AnnaBridge 171:3a7713b1edbc 539 /** @defgroup TIM_Event_Source TIM Event Source
AnnaBridge 171:3a7713b1edbc 540 * @{
AnnaBridge 171:3a7713b1edbc 541 */
AnnaBridge 171:3a7713b1edbc 542 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
AnnaBridge 171:3a7713b1edbc 543 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
AnnaBridge 171:3a7713b1edbc 544 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
AnnaBridge 171:3a7713b1edbc 545 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
AnnaBridge 171:3a7713b1edbc 546 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
AnnaBridge 171:3a7713b1edbc 547 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
AnnaBridge 171:3a7713b1edbc 548 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
AnnaBridge 171:3a7713b1edbc 549 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
AnnaBridge 171:3a7713b1edbc 550
AnnaBridge 171:3a7713b1edbc 551 /**
AnnaBridge 171:3a7713b1edbc 552 * @}
AnnaBridge 171:3a7713b1edbc 553 */
AnnaBridge 171:3a7713b1edbc 554
AnnaBridge 171:3a7713b1edbc 555 /** @defgroup TIM_Flag_definition TIM Flag definition
AnnaBridge 171:3a7713b1edbc 556 * @{
AnnaBridge 171:3a7713b1edbc 557 */
AnnaBridge 171:3a7713b1edbc 558 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
AnnaBridge 171:3a7713b1edbc 559 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
AnnaBridge 171:3a7713b1edbc 560 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
AnnaBridge 171:3a7713b1edbc 561 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
AnnaBridge 171:3a7713b1edbc 562 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
AnnaBridge 171:3a7713b1edbc 563 #define TIM_FLAG_COM (TIM_SR_COMIF)
AnnaBridge 171:3a7713b1edbc 564 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
AnnaBridge 171:3a7713b1edbc 565 #define TIM_FLAG_BREAK (TIM_SR_BIF)
AnnaBridge 171:3a7713b1edbc 566 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
AnnaBridge 171:3a7713b1edbc 567 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
AnnaBridge 171:3a7713b1edbc 568 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
AnnaBridge 171:3a7713b1edbc 569 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
AnnaBridge 171:3a7713b1edbc 570 /**
AnnaBridge 171:3a7713b1edbc 571 * @}
AnnaBridge 171:3a7713b1edbc 572 */
AnnaBridge 171:3a7713b1edbc 573
AnnaBridge 171:3a7713b1edbc 574 /** @defgroup TIM_Clock_Source TIM Clock Source
AnnaBridge 171:3a7713b1edbc 575 * @{
AnnaBridge 171:3a7713b1edbc 576 */
AnnaBridge 171:3a7713b1edbc 577 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
AnnaBridge 171:3a7713b1edbc 578 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
AnnaBridge 171:3a7713b1edbc 579 #define TIM_CLOCKSOURCE_ITR0 0x0000U
AnnaBridge 171:3a7713b1edbc 580 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
AnnaBridge 171:3a7713b1edbc 581 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
AnnaBridge 171:3a7713b1edbc 582 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
AnnaBridge 171:3a7713b1edbc 583 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
AnnaBridge 171:3a7713b1edbc 584 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
AnnaBridge 171:3a7713b1edbc 585 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
AnnaBridge 171:3a7713b1edbc 586 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
AnnaBridge 171:3a7713b1edbc 587 /**
AnnaBridge 171:3a7713b1edbc 588 * @}
AnnaBridge 171:3a7713b1edbc 589 */
AnnaBridge 171:3a7713b1edbc 590
AnnaBridge 171:3a7713b1edbc 591 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
AnnaBridge 171:3a7713b1edbc 592 * @{
AnnaBridge 171:3a7713b1edbc 593 */
AnnaBridge 171:3a7713b1edbc 594 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
AnnaBridge 171:3a7713b1edbc 595 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
AnnaBridge 171:3a7713b1edbc 596 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
AnnaBridge 171:3a7713b1edbc 597 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
AnnaBridge 171:3a7713b1edbc 598 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
AnnaBridge 171:3a7713b1edbc 599 /**
AnnaBridge 171:3a7713b1edbc 600 * @}
AnnaBridge 171:3a7713b1edbc 601 */
AnnaBridge 171:3a7713b1edbc 602
AnnaBridge 171:3a7713b1edbc 603 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
AnnaBridge 171:3a7713b1edbc 604 * @{
AnnaBridge 171:3a7713b1edbc 605 */
AnnaBridge 171:3a7713b1edbc 606 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 171:3a7713b1edbc 607 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
AnnaBridge 171:3a7713b1edbc 608 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
AnnaBridge 171:3a7713b1edbc 609 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
AnnaBridge 171:3a7713b1edbc 610 /**
AnnaBridge 171:3a7713b1edbc 611 * @}
AnnaBridge 171:3a7713b1edbc 612 */
AnnaBridge 171:3a7713b1edbc 613
AnnaBridge 171:3a7713b1edbc 614 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
AnnaBridge 171:3a7713b1edbc 615 * @{
AnnaBridge 171:3a7713b1edbc 616 */
AnnaBridge 171:3a7713b1edbc 617 #define TIM_CLEARINPUTSOURCE_ETR 0x0001U
AnnaBridge 171:3a7713b1edbc 618 #define TIM_CLEARINPUTSOURCE_NONE 0x0000U
AnnaBridge 171:3a7713b1edbc 619 /**
AnnaBridge 171:3a7713b1edbc 620 * @}
AnnaBridge 171:3a7713b1edbc 621 */
AnnaBridge 171:3a7713b1edbc 622
AnnaBridge 171:3a7713b1edbc 623 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
AnnaBridge 171:3a7713b1edbc 624 * @{
AnnaBridge 171:3a7713b1edbc 625 */
AnnaBridge 171:3a7713b1edbc 626 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
AnnaBridge 171:3a7713b1edbc 627 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
AnnaBridge 171:3a7713b1edbc 628 /**
AnnaBridge 171:3a7713b1edbc 629 * @}
AnnaBridge 171:3a7713b1edbc 630 */
AnnaBridge 171:3a7713b1edbc 631
AnnaBridge 171:3a7713b1edbc 632 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
AnnaBridge 171:3a7713b1edbc 633 * @{
AnnaBridge 171:3a7713b1edbc 634 */
AnnaBridge 171:3a7713b1edbc 635 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 171:3a7713b1edbc 636 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
AnnaBridge 171:3a7713b1edbc 637 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
AnnaBridge 171:3a7713b1edbc 638 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
AnnaBridge 171:3a7713b1edbc 639 /**
AnnaBridge 171:3a7713b1edbc 640 * @}
AnnaBridge 171:3a7713b1edbc 641 */
AnnaBridge 171:3a7713b1edbc 642
AnnaBridge 171:3a7713b1edbc 643 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
AnnaBridge 171:3a7713b1edbc 644 * @{
AnnaBridge 171:3a7713b1edbc 645 */
AnnaBridge 171:3a7713b1edbc 646 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
AnnaBridge 171:3a7713b1edbc 647 #define TIM_OSSR_DISABLE 0x0000U
AnnaBridge 171:3a7713b1edbc 648 /**
AnnaBridge 171:3a7713b1edbc 649 * @}
AnnaBridge 171:3a7713b1edbc 650 */
AnnaBridge 171:3a7713b1edbc 651
AnnaBridge 171:3a7713b1edbc 652 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
AnnaBridge 171:3a7713b1edbc 653 * @{
AnnaBridge 171:3a7713b1edbc 654 */
AnnaBridge 171:3a7713b1edbc 655 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
AnnaBridge 171:3a7713b1edbc 656 #define TIM_OSSI_DISABLE 0x0000U
AnnaBridge 171:3a7713b1edbc 657 /**
AnnaBridge 171:3a7713b1edbc 658 * @}
AnnaBridge 171:3a7713b1edbc 659 */
AnnaBridge 171:3a7713b1edbc 660
AnnaBridge 171:3a7713b1edbc 661 /** @defgroup TIM_Lock_level TIM Lock level
AnnaBridge 171:3a7713b1edbc 662 * @{
AnnaBridge 171:3a7713b1edbc 663 */
AnnaBridge 171:3a7713b1edbc 664 #define TIM_LOCKLEVEL_OFF 0x0000U
AnnaBridge 171:3a7713b1edbc 665 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
AnnaBridge 171:3a7713b1edbc 666 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
AnnaBridge 171:3a7713b1edbc 667 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
AnnaBridge 171:3a7713b1edbc 668 /**
AnnaBridge 171:3a7713b1edbc 669 * @}
AnnaBridge 171:3a7713b1edbc 670 */
AnnaBridge 171:3a7713b1edbc 671 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
AnnaBridge 171:3a7713b1edbc 672 * @{
AnnaBridge 171:3a7713b1edbc 673 */
AnnaBridge 171:3a7713b1edbc 674 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
AnnaBridge 171:3a7713b1edbc 675 #define TIM_BREAK_DISABLE 0x0000U
AnnaBridge 171:3a7713b1edbc 676 /**
AnnaBridge 171:3a7713b1edbc 677 * @}
AnnaBridge 171:3a7713b1edbc 678 */
AnnaBridge 171:3a7713b1edbc 679
AnnaBridge 171:3a7713b1edbc 680 /** @defgroup TIM_Break_Polarity TIM Break Polarity
AnnaBridge 171:3a7713b1edbc 681 * @{
AnnaBridge 171:3a7713b1edbc 682 */
AnnaBridge 171:3a7713b1edbc 683 #define TIM_BREAKPOLARITY_LOW 0x0000U
AnnaBridge 171:3a7713b1edbc 684 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
AnnaBridge 171:3a7713b1edbc 685 /**
AnnaBridge 171:3a7713b1edbc 686 * @}
AnnaBridge 171:3a7713b1edbc 687 */
AnnaBridge 171:3a7713b1edbc 688
AnnaBridge 171:3a7713b1edbc 689 /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
AnnaBridge 171:3a7713b1edbc 690 * @{
AnnaBridge 171:3a7713b1edbc 691 */
AnnaBridge 171:3a7713b1edbc 692 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
AnnaBridge 171:3a7713b1edbc 693 #define TIM_AUTOMATICOUTPUT_DISABLE 0x0000U
AnnaBridge 171:3a7713b1edbc 694 /**
AnnaBridge 171:3a7713b1edbc 695 * @}
AnnaBridge 171:3a7713b1edbc 696 */
AnnaBridge 171:3a7713b1edbc 697
AnnaBridge 171:3a7713b1edbc 698 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
AnnaBridge 171:3a7713b1edbc 699 * @{
AnnaBridge 171:3a7713b1edbc 700 */
AnnaBridge 171:3a7713b1edbc 701 #define TIM_TRGO_RESET 0x0000U
AnnaBridge 171:3a7713b1edbc 702 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
AnnaBridge 171:3a7713b1edbc 703 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
AnnaBridge 171:3a7713b1edbc 704 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
AnnaBridge 171:3a7713b1edbc 705 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
AnnaBridge 171:3a7713b1edbc 706 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
AnnaBridge 171:3a7713b1edbc 707 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
AnnaBridge 171:3a7713b1edbc 708 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
AnnaBridge 171:3a7713b1edbc 709 /**
AnnaBridge 171:3a7713b1edbc 710 * @}
AnnaBridge 171:3a7713b1edbc 711 */
AnnaBridge 171:3a7713b1edbc 712
AnnaBridge 171:3a7713b1edbc 713 /** @defgroup TIM_Slave_Mode TIM Slave Mode
AnnaBridge 171:3a7713b1edbc 714 * @{
AnnaBridge 171:3a7713b1edbc 715 */
AnnaBridge 171:3a7713b1edbc 716 #define TIM_SLAVEMODE_DISABLE 0x0000U
AnnaBridge 171:3a7713b1edbc 717 #define TIM_SLAVEMODE_RESET 0x0004U
AnnaBridge 171:3a7713b1edbc 718 #define TIM_SLAVEMODE_GATED 0x0005U
AnnaBridge 171:3a7713b1edbc 719 #define TIM_SLAVEMODE_TRIGGER 0x0006U
AnnaBridge 171:3a7713b1edbc 720 #define TIM_SLAVEMODE_EXTERNAL1 0x0007U
AnnaBridge 171:3a7713b1edbc 721 /**
AnnaBridge 171:3a7713b1edbc 722 * @}
AnnaBridge 171:3a7713b1edbc 723 */
AnnaBridge 171:3a7713b1edbc 724
AnnaBridge 171:3a7713b1edbc 725 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
AnnaBridge 171:3a7713b1edbc 726 * @{
AnnaBridge 171:3a7713b1edbc 727 */
AnnaBridge 171:3a7713b1edbc 728 #define TIM_MASTERSLAVEMODE_ENABLE 0x0080U
AnnaBridge 171:3a7713b1edbc 729 #define TIM_MASTERSLAVEMODE_DISABLE 0x0000U
AnnaBridge 171:3a7713b1edbc 730 /**
AnnaBridge 171:3a7713b1edbc 731 * @}
AnnaBridge 171:3a7713b1edbc 732 */
AnnaBridge 171:3a7713b1edbc 733
AnnaBridge 171:3a7713b1edbc 734 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
AnnaBridge 171:3a7713b1edbc 735 * @{
AnnaBridge 171:3a7713b1edbc 736 */
AnnaBridge 171:3a7713b1edbc 737 #define TIM_TS_ITR0 0x0000U
AnnaBridge 171:3a7713b1edbc 738 #define TIM_TS_ITR1 0x0010U
AnnaBridge 171:3a7713b1edbc 739 #define TIM_TS_ITR2 0x0020U
AnnaBridge 171:3a7713b1edbc 740 #define TIM_TS_ITR3 0x0030U
AnnaBridge 171:3a7713b1edbc 741 #define TIM_TS_TI1F_ED 0x0040U
AnnaBridge 171:3a7713b1edbc 742 #define TIM_TS_TI1FP1 0x0050U
AnnaBridge 171:3a7713b1edbc 743 #define TIM_TS_TI2FP2 0x0060U
AnnaBridge 171:3a7713b1edbc 744 #define TIM_TS_ETRF 0x0070U
AnnaBridge 171:3a7713b1edbc 745 #define TIM_TS_NONE 0xFFFFU
AnnaBridge 171:3a7713b1edbc 746 /**
AnnaBridge 171:3a7713b1edbc 747 * @}
AnnaBridge 171:3a7713b1edbc 748 */
AnnaBridge 171:3a7713b1edbc 749
AnnaBridge 171:3a7713b1edbc 750 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
AnnaBridge 171:3a7713b1edbc 751 * @{
AnnaBridge 171:3a7713b1edbc 752 */
AnnaBridge 171:3a7713b1edbc 753 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
AnnaBridge 171:3a7713b1edbc 754 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
AnnaBridge 171:3a7713b1edbc 755 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 171:3a7713b1edbc 756 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 171:3a7713b1edbc 757 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 171:3a7713b1edbc 758 /**
AnnaBridge 171:3a7713b1edbc 759 * @}
AnnaBridge 171:3a7713b1edbc 760 */
AnnaBridge 171:3a7713b1edbc 761
AnnaBridge 171:3a7713b1edbc 762 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
AnnaBridge 171:3a7713b1edbc 763 * @{
AnnaBridge 171:3a7713b1edbc 764 */
AnnaBridge 171:3a7713b1edbc 765 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 171:3a7713b1edbc 766 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
AnnaBridge 171:3a7713b1edbc 767 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
AnnaBridge 171:3a7713b1edbc 768 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
AnnaBridge 171:3a7713b1edbc 769 /**
AnnaBridge 171:3a7713b1edbc 770 * @}
AnnaBridge 171:3a7713b1edbc 771 */
AnnaBridge 171:3a7713b1edbc 772
AnnaBridge 171:3a7713b1edbc 773
AnnaBridge 171:3a7713b1edbc 774 /** @defgroup TIM_TI1_Selection TIM TI1 Selection
AnnaBridge 171:3a7713b1edbc 775 * @{
AnnaBridge 171:3a7713b1edbc 776 */
AnnaBridge 171:3a7713b1edbc 777 #define TIM_TI1SELECTION_CH1 0x0000U
AnnaBridge 171:3a7713b1edbc 778 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
AnnaBridge 171:3a7713b1edbc 779 /**
AnnaBridge 171:3a7713b1edbc 780 * @}
AnnaBridge 171:3a7713b1edbc 781 */
AnnaBridge 171:3a7713b1edbc 782
AnnaBridge 171:3a7713b1edbc 783 /** @defgroup TIM_DMA_Base_address TIM DMA Base address
AnnaBridge 171:3a7713b1edbc 784 * @{
AnnaBridge 171:3a7713b1edbc 785 */
AnnaBridge 171:3a7713b1edbc 786 #define TIM_DMABASE_CR1 0x00000000U
AnnaBridge 171:3a7713b1edbc 787 #define TIM_DMABASE_CR2 0x00000001U
AnnaBridge 171:3a7713b1edbc 788 #define TIM_DMABASE_SMCR 0x00000002U
AnnaBridge 171:3a7713b1edbc 789 #define TIM_DMABASE_DIER 0x00000003U
AnnaBridge 171:3a7713b1edbc 790 #define TIM_DMABASE_SR 0x00000004U
AnnaBridge 171:3a7713b1edbc 791 #define TIM_DMABASE_EGR 0x00000005U
AnnaBridge 171:3a7713b1edbc 792 #define TIM_DMABASE_CCMR1 0x00000006U
AnnaBridge 171:3a7713b1edbc 793 #define TIM_DMABASE_CCMR2 0x00000007U
AnnaBridge 171:3a7713b1edbc 794 #define TIM_DMABASE_CCER 0x00000008U
AnnaBridge 171:3a7713b1edbc 795 #define TIM_DMABASE_CNT 0x00000009U
AnnaBridge 171:3a7713b1edbc 796 #define TIM_DMABASE_PSC 0x0000000AU
AnnaBridge 171:3a7713b1edbc 797 #define TIM_DMABASE_ARR 0x0000000BU
AnnaBridge 171:3a7713b1edbc 798 #define TIM_DMABASE_RCR 0x0000000CU
AnnaBridge 171:3a7713b1edbc 799 #define TIM_DMABASE_CCR1 0x0000000DU
AnnaBridge 171:3a7713b1edbc 800 #define TIM_DMABASE_CCR2 0x0000000EU
AnnaBridge 171:3a7713b1edbc 801 #define TIM_DMABASE_CCR3 0x0000000FU
AnnaBridge 171:3a7713b1edbc 802 #define TIM_DMABASE_CCR4 0x00000010U
AnnaBridge 171:3a7713b1edbc 803 #define TIM_DMABASE_BDTR 0x00000011U
AnnaBridge 171:3a7713b1edbc 804 #define TIM_DMABASE_DCR 0x00000012U
AnnaBridge 171:3a7713b1edbc 805 #define TIM_DMABASE_OR 0x00000013U
AnnaBridge 171:3a7713b1edbc 806 /**
AnnaBridge 171:3a7713b1edbc 807 * @}
AnnaBridge 171:3a7713b1edbc 808 */
AnnaBridge 171:3a7713b1edbc 809
AnnaBridge 171:3a7713b1edbc 810 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
AnnaBridge 171:3a7713b1edbc 811 * @{
AnnaBridge 171:3a7713b1edbc 812 */
AnnaBridge 171:3a7713b1edbc 813 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
AnnaBridge 171:3a7713b1edbc 814 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
AnnaBridge 171:3a7713b1edbc 815 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
AnnaBridge 171:3a7713b1edbc 816 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
AnnaBridge 171:3a7713b1edbc 817 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
AnnaBridge 171:3a7713b1edbc 818 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
AnnaBridge 171:3a7713b1edbc 819 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
AnnaBridge 171:3a7713b1edbc 820 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
AnnaBridge 171:3a7713b1edbc 821 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
AnnaBridge 171:3a7713b1edbc 822 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
AnnaBridge 171:3a7713b1edbc 823 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
AnnaBridge 171:3a7713b1edbc 824 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
AnnaBridge 171:3a7713b1edbc 825 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
AnnaBridge 171:3a7713b1edbc 826 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
AnnaBridge 171:3a7713b1edbc 827 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
AnnaBridge 171:3a7713b1edbc 828 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
AnnaBridge 171:3a7713b1edbc 829 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
AnnaBridge 171:3a7713b1edbc 830 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
AnnaBridge 171:3a7713b1edbc 831 /**
AnnaBridge 171:3a7713b1edbc 832 * @}
AnnaBridge 171:3a7713b1edbc 833 */
AnnaBridge 171:3a7713b1edbc 834
AnnaBridge 171:3a7713b1edbc 835 /** @defgroup DMA_Handle_index DMA Handle index
AnnaBridge 171:3a7713b1edbc 836 * @{
AnnaBridge 171:3a7713b1edbc 837 */
AnnaBridge 171:3a7713b1edbc 838 #define TIM_DMA_ID_UPDATE (uint16_t)0x00 /*!< Index of the DMA handle used for Update DMA requests */
AnnaBridge 171:3a7713b1edbc 839 #define TIM_DMA_ID_CC1 (uint16_t)0x01 /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
AnnaBridge 171:3a7713b1edbc 840 #define TIM_DMA_ID_CC2 (uint16_t)0x02 /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
AnnaBridge 171:3a7713b1edbc 841 #define TIM_DMA_ID_CC3 (uint16_t)0x03 /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
AnnaBridge 171:3a7713b1edbc 842 #define TIM_DMA_ID_CC4 (uint16_t)0x04 /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
AnnaBridge 171:3a7713b1edbc 843 #define TIM_DMA_ID_COMMUTATION (uint16_t)0x05 /*!< Index of the DMA handle used for Commutation DMA requests */
AnnaBridge 171:3a7713b1edbc 844 #define TIM_DMA_ID_TRIGGER (uint16_t)0x06 /*!< Index of the DMA handle used for Trigger DMA requests */
AnnaBridge 171:3a7713b1edbc 845 /**
AnnaBridge 171:3a7713b1edbc 846 * @}
AnnaBridge 171:3a7713b1edbc 847 */
AnnaBridge 171:3a7713b1edbc 848
AnnaBridge 171:3a7713b1edbc 849 /** @defgroup Channel_CC_State Channel CC State
AnnaBridge 171:3a7713b1edbc 850 * @{
AnnaBridge 171:3a7713b1edbc 851 */
AnnaBridge 171:3a7713b1edbc 852 #define TIM_CCx_ENABLE 0x0001U
AnnaBridge 171:3a7713b1edbc 853 #define TIM_CCx_DISABLE 0x0000U
AnnaBridge 171:3a7713b1edbc 854 #define TIM_CCxN_ENABLE 0x0004U
AnnaBridge 171:3a7713b1edbc 855 #define TIM_CCxN_DISABLE 0x0000U
AnnaBridge 171:3a7713b1edbc 856 /**
AnnaBridge 171:3a7713b1edbc 857 * @}
AnnaBridge 171:3a7713b1edbc 858 */
AnnaBridge 171:3a7713b1edbc 859
AnnaBridge 171:3a7713b1edbc 860 /**
AnnaBridge 171:3a7713b1edbc 861 * @}
AnnaBridge 171:3a7713b1edbc 862 */
AnnaBridge 171:3a7713b1edbc 863
AnnaBridge 171:3a7713b1edbc 864 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 865 /** @defgroup TIM_Exported_Macros TIM Exported Macros
AnnaBridge 171:3a7713b1edbc 866 * @{
AnnaBridge 171:3a7713b1edbc 867 */
AnnaBridge 171:3a7713b1edbc 868 /** @brief Reset TIM handle state
AnnaBridge 171:3a7713b1edbc 869 * @param __HANDLE__: TIM handle
AnnaBridge 171:3a7713b1edbc 870 * @retval None
AnnaBridge 171:3a7713b1edbc 871 */
AnnaBridge 171:3a7713b1edbc 872 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 873
AnnaBridge 171:3a7713b1edbc 874 /**
AnnaBridge 171:3a7713b1edbc 875 * @brief Enable the TIM peripheral.
AnnaBridge 171:3a7713b1edbc 876 * @param __HANDLE__: TIM handle
AnnaBridge 171:3a7713b1edbc 877 * @retval None
AnnaBridge 171:3a7713b1edbc 878 */
AnnaBridge 171:3a7713b1edbc 879 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
AnnaBridge 171:3a7713b1edbc 880
AnnaBridge 171:3a7713b1edbc 881 /**
AnnaBridge 171:3a7713b1edbc 882 * @brief Enable the TIM main Output.
AnnaBridge 171:3a7713b1edbc 883 * @param __HANDLE__: TIM handle
AnnaBridge 171:3a7713b1edbc 884 * @retval None
AnnaBridge 171:3a7713b1edbc 885 */
AnnaBridge 171:3a7713b1edbc 886 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
AnnaBridge 171:3a7713b1edbc 887
AnnaBridge 171:3a7713b1edbc 888
AnnaBridge 171:3a7713b1edbc 889 /**
AnnaBridge 171:3a7713b1edbc 890 * @brief Disable the TIM peripheral.
AnnaBridge 171:3a7713b1edbc 891 * @param __HANDLE__: TIM handle
AnnaBridge 171:3a7713b1edbc 892 * @retval None
AnnaBridge 171:3a7713b1edbc 893 */
AnnaBridge 171:3a7713b1edbc 894 #define __HAL_TIM_DISABLE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 895 do { \
AnnaBridge 171:3a7713b1edbc 896 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
AnnaBridge 171:3a7713b1edbc 897 { \
AnnaBridge 171:3a7713b1edbc 898 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
AnnaBridge 171:3a7713b1edbc 899 { \
AnnaBridge 171:3a7713b1edbc 900 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
AnnaBridge 171:3a7713b1edbc 901 } \
AnnaBridge 171:3a7713b1edbc 902 } \
AnnaBridge 171:3a7713b1edbc 903 } while(0)
AnnaBridge 171:3a7713b1edbc 904
AnnaBridge 171:3a7713b1edbc 905 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
AnnaBridge 171:3a7713b1edbc 906 channels have been disabled */
AnnaBridge 171:3a7713b1edbc 907 /**
AnnaBridge 171:3a7713b1edbc 908 * @brief Disable the TIM main Output.
AnnaBridge 171:3a7713b1edbc 909 * @param __HANDLE__: TIM handle
AnnaBridge 171:3a7713b1edbc 910 * @retval None
AnnaBridge 171:3a7713b1edbc 911 */
AnnaBridge 171:3a7713b1edbc 912 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 913 do { \
AnnaBridge 171:3a7713b1edbc 914 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
AnnaBridge 171:3a7713b1edbc 915 { \
AnnaBridge 171:3a7713b1edbc 916 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
AnnaBridge 171:3a7713b1edbc 917 { \
AnnaBridge 171:3a7713b1edbc 918 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
AnnaBridge 171:3a7713b1edbc 919 } \
AnnaBridge 171:3a7713b1edbc 920 } \
AnnaBridge 171:3a7713b1edbc 921 } while(0)
AnnaBridge 171:3a7713b1edbc 922
AnnaBridge 171:3a7713b1edbc 923 /**
AnnaBridge 171:3a7713b1edbc 924 * @brief Disable the TIM main Output.
AnnaBridge 171:3a7713b1edbc 925 * @param __HANDLE__: TIM handle
AnnaBridge 171:3a7713b1edbc 926 * @retval None
AnnaBridge 171:3a7713b1edbc 927 * @note The Main Output Enable of a timer instance is disabled unconditionally
AnnaBridge 171:3a7713b1edbc 928 */
AnnaBridge 171:3a7713b1edbc 929 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
AnnaBridge 171:3a7713b1edbc 930
AnnaBridge 171:3a7713b1edbc 931 /** @brief Enable the specified TIM interrupt.
AnnaBridge 171:3a7713b1edbc 932 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 171:3a7713b1edbc 933 * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
AnnaBridge 171:3a7713b1edbc 934 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 935 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 171:3a7713b1edbc 936 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 171:3a7713b1edbc 937 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 171:3a7713b1edbc 938 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 171:3a7713b1edbc 939 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 171:3a7713b1edbc 940 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 171:3a7713b1edbc 941 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 171:3a7713b1edbc 942 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 171:3a7713b1edbc 943 * @retval None
AnnaBridge 171:3a7713b1edbc 944 */
AnnaBridge 171:3a7713b1edbc 945 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 946
AnnaBridge 171:3a7713b1edbc 947 /** @brief Disable the specified TIM interrupt.
AnnaBridge 171:3a7713b1edbc 948 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 171:3a7713b1edbc 949 * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
AnnaBridge 171:3a7713b1edbc 950 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 951 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 171:3a7713b1edbc 952 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 171:3a7713b1edbc 953 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 171:3a7713b1edbc 954 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 171:3a7713b1edbc 955 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 171:3a7713b1edbc 956 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 171:3a7713b1edbc 957 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 171:3a7713b1edbc 958 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 171:3a7713b1edbc 959 * @retval None
AnnaBridge 171:3a7713b1edbc 960 */
AnnaBridge 171:3a7713b1edbc 961 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 962
AnnaBridge 171:3a7713b1edbc 963 /** @brief Enable the specified DMA request.
AnnaBridge 171:3a7713b1edbc 964 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 171:3a7713b1edbc 965 * @param __DMA__: specifies the TIM DMA request to enable.
AnnaBridge 171:3a7713b1edbc 966 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 967 * @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge 171:3a7713b1edbc 968 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge 171:3a7713b1edbc 969 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge 171:3a7713b1edbc 970 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge 171:3a7713b1edbc 971 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge 171:3a7713b1edbc 972 * @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge 171:3a7713b1edbc 973 * @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge 171:3a7713b1edbc 974 * @retval None
AnnaBridge 171:3a7713b1edbc 975 */
AnnaBridge 171:3a7713b1edbc 976 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
AnnaBridge 171:3a7713b1edbc 977
AnnaBridge 171:3a7713b1edbc 978 /** @brief Disable the specified DMA request.
AnnaBridge 171:3a7713b1edbc 979 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 171:3a7713b1edbc 980 * @param __DMA__: specifies the TIM DMA request to disable.
AnnaBridge 171:3a7713b1edbc 981 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 982 * @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge 171:3a7713b1edbc 983 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge 171:3a7713b1edbc 984 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge 171:3a7713b1edbc 985 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge 171:3a7713b1edbc 986 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge 171:3a7713b1edbc 987 * @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge 171:3a7713b1edbc 988 * @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge 171:3a7713b1edbc 989 * @retval None
AnnaBridge 171:3a7713b1edbc 990 */
AnnaBridge 171:3a7713b1edbc 991 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
AnnaBridge 171:3a7713b1edbc 992
AnnaBridge 171:3a7713b1edbc 993 /** @brief Check whether the specified TIM interrupt flag is set or not.
AnnaBridge 171:3a7713b1edbc 994 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 171:3a7713b1edbc 995 * @param __FLAG__: specifies the TIM interrupt flag to check.
AnnaBridge 171:3a7713b1edbc 996 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 997 * @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge 171:3a7713b1edbc 998 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge 171:3a7713b1edbc 999 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge 171:3a7713b1edbc 1000 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge 171:3a7713b1edbc 1001 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge 171:3a7713b1edbc 1002 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
AnnaBridge 171:3a7713b1edbc 1003 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
AnnaBridge 171:3a7713b1edbc 1004 * @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge 171:3a7713b1edbc 1005 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge 171:3a7713b1edbc 1006 * @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge 171:3a7713b1edbc 1007 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
AnnaBridge 171:3a7713b1edbc 1008 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
AnnaBridge 171:3a7713b1edbc 1009 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge 171:3a7713b1edbc 1010 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge 171:3a7713b1edbc 1011 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge 171:3a7713b1edbc 1012 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge 171:3a7713b1edbc 1013 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 1014 */
AnnaBridge 171:3a7713b1edbc 1015 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge 171:3a7713b1edbc 1016
AnnaBridge 171:3a7713b1edbc 1017 /** @brief Clear the specified TIM interrupt flag.
AnnaBridge 171:3a7713b1edbc 1018 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 171:3a7713b1edbc 1019 * @param __FLAG__: specifies the TIM interrupt flag to clear.
AnnaBridge 171:3a7713b1edbc 1020 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1021 * @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge 171:3a7713b1edbc 1022 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge 171:3a7713b1edbc 1023 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge 171:3a7713b1edbc 1024 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge 171:3a7713b1edbc 1025 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge 171:3a7713b1edbc 1026 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
AnnaBridge 171:3a7713b1edbc 1027 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
AnnaBridge 171:3a7713b1edbc 1028 * @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge 171:3a7713b1edbc 1029 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge 171:3a7713b1edbc 1030 * @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge 171:3a7713b1edbc 1031 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
AnnaBridge 171:3a7713b1edbc 1032 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
AnnaBridge 171:3a7713b1edbc 1033 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge 171:3a7713b1edbc 1034 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge 171:3a7713b1edbc 1035 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge 171:3a7713b1edbc 1036 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge 171:3a7713b1edbc 1037 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 1038 */
AnnaBridge 171:3a7713b1edbc 1039 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
AnnaBridge 171:3a7713b1edbc 1040
AnnaBridge 171:3a7713b1edbc 1041 /**
AnnaBridge 171:3a7713b1edbc 1042 * @brief Check whether the specified TIM interrupt source is enabled or not.
AnnaBridge 171:3a7713b1edbc 1043 * @param __HANDLE__: TIM handle
AnnaBridge 171:3a7713b1edbc 1044 * @param __INTERRUPT__: specifies the TIM interrupt source to check.
AnnaBridge 171:3a7713b1edbc 1045 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1046 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 171:3a7713b1edbc 1047 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 171:3a7713b1edbc 1048 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 171:3a7713b1edbc 1049 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 171:3a7713b1edbc 1050 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 171:3a7713b1edbc 1051 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 171:3a7713b1edbc 1052 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 171:3a7713b1edbc 1053 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 171:3a7713b1edbc 1054 * @retval The state of TIM_IT (SET or RESET).
AnnaBridge 171:3a7713b1edbc 1055 */
AnnaBridge 171:3a7713b1edbc 1056 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge 171:3a7713b1edbc 1057
AnnaBridge 171:3a7713b1edbc 1058 /** @brief Clear the TIM interrupt pending bits.
AnnaBridge 171:3a7713b1edbc 1059 * @param __HANDLE__: TIM handle
AnnaBridge 171:3a7713b1edbc 1060 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge 171:3a7713b1edbc 1061 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1062 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 171:3a7713b1edbc 1063 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 171:3a7713b1edbc 1064 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 171:3a7713b1edbc 1065 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 171:3a7713b1edbc 1066 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 171:3a7713b1edbc 1067 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 171:3a7713b1edbc 1068 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 171:3a7713b1edbc 1069 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 171:3a7713b1edbc 1070 * @retval None
AnnaBridge 171:3a7713b1edbc 1071 */
AnnaBridge 171:3a7713b1edbc 1072 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 1073
AnnaBridge 171:3a7713b1edbc 1074 /**
AnnaBridge 171:3a7713b1edbc 1075 * @brief Indicates whether or not the TIM Counter is used as downcounter.
AnnaBridge 171:3a7713b1edbc 1076 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1077 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
AnnaBridge 171:3a7713b1edbc 1078 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
AnnaBridge 171:3a7713b1edbc 1079 mode.
AnnaBridge 171:3a7713b1edbc 1080 */
AnnaBridge 171:3a7713b1edbc 1081 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
AnnaBridge 171:3a7713b1edbc 1082
AnnaBridge 171:3a7713b1edbc 1083 /**
AnnaBridge 171:3a7713b1edbc 1084 * @brief Set the TIM Prescaler on runtime.
AnnaBridge 171:3a7713b1edbc 1085 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1086 * @param __PRESC__: specifies the Prescaler new value.
AnnaBridge 171:3a7713b1edbc 1087 * @retval None
AnnaBridge 171:3a7713b1edbc 1088 */
AnnaBridge 171:3a7713b1edbc 1089 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
AnnaBridge 171:3a7713b1edbc 1090
AnnaBridge 171:3a7713b1edbc 1091 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge 171:3a7713b1edbc 1092 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
AnnaBridge 171:3a7713b1edbc 1093 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
AnnaBridge 171:3a7713b1edbc 1094 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
AnnaBridge 171:3a7713b1edbc 1095 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
AnnaBridge 171:3a7713b1edbc 1096
AnnaBridge 171:3a7713b1edbc 1097 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
AnnaBridge 171:3a7713b1edbc 1098 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
AnnaBridge 171:3a7713b1edbc 1099 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
AnnaBridge 171:3a7713b1edbc 1100 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
AnnaBridge 171:3a7713b1edbc 1101 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
AnnaBridge 171:3a7713b1edbc 1102
AnnaBridge 171:3a7713b1edbc 1103 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge 171:3a7713b1edbc 1104 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
AnnaBridge 171:3a7713b1edbc 1105 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
AnnaBridge 171:3a7713b1edbc 1106 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
AnnaBridge 171:3a7713b1edbc 1107 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
AnnaBridge 171:3a7713b1edbc 1108
AnnaBridge 171:3a7713b1edbc 1109 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
AnnaBridge 171:3a7713b1edbc 1110 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
AnnaBridge 171:3a7713b1edbc 1111 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
AnnaBridge 171:3a7713b1edbc 1112 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
AnnaBridge 171:3a7713b1edbc 1113 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
AnnaBridge 171:3a7713b1edbc 1114
AnnaBridge 171:3a7713b1edbc 1115 /**
AnnaBridge 171:3a7713b1edbc 1116 * @brief Sets the TIM Capture Compare Register value on runtime without
AnnaBridge 171:3a7713b1edbc 1117 * calling another time ConfigChannel function.
AnnaBridge 171:3a7713b1edbc 1118 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1119 * @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge 171:3a7713b1edbc 1120 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1121 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 171:3a7713b1edbc 1122 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 171:3a7713b1edbc 1123 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 171:3a7713b1edbc 1124 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 171:3a7713b1edbc 1125 * @param __COMPARE__: specifies the Capture Compare register new value.
AnnaBridge 171:3a7713b1edbc 1126 * @retval None
AnnaBridge 171:3a7713b1edbc 1127 */
AnnaBridge 171:3a7713b1edbc 1128 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
AnnaBridge 171:3a7713b1edbc 1129 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
AnnaBridge 171:3a7713b1edbc 1130
AnnaBridge 171:3a7713b1edbc 1131 /**
AnnaBridge 171:3a7713b1edbc 1132 * @brief Gets the TIM Capture Compare Register value on runtime
AnnaBridge 171:3a7713b1edbc 1133 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1134 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
AnnaBridge 171:3a7713b1edbc 1135 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1136 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
AnnaBridge 171:3a7713b1edbc 1137 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
AnnaBridge 171:3a7713b1edbc 1138 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
AnnaBridge 171:3a7713b1edbc 1139 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge 171:3a7713b1edbc 1140 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
AnnaBridge 171:3a7713b1edbc 1141 */
AnnaBridge 171:3a7713b1edbc 1142 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
AnnaBridge 171:3a7713b1edbc 1143 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
AnnaBridge 171:3a7713b1edbc 1144
AnnaBridge 171:3a7713b1edbc 1145 /**
AnnaBridge 171:3a7713b1edbc 1146 * @brief Sets the TIM Counter Register value on runtime.
AnnaBridge 171:3a7713b1edbc 1147 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1148 * @param __COUNTER__: specifies the Counter register new value.
AnnaBridge 171:3a7713b1edbc 1149 * @retval None
AnnaBridge 171:3a7713b1edbc 1150 */
AnnaBridge 171:3a7713b1edbc 1151 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
AnnaBridge 171:3a7713b1edbc 1152
AnnaBridge 171:3a7713b1edbc 1153 /**
AnnaBridge 171:3a7713b1edbc 1154 * @brief Gets the TIM Counter Register value on runtime.
AnnaBridge 171:3a7713b1edbc 1155 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1156 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
AnnaBridge 171:3a7713b1edbc 1157 */
AnnaBridge 171:3a7713b1edbc 1158 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
AnnaBridge 171:3a7713b1edbc 1159
AnnaBridge 171:3a7713b1edbc 1160 /**
AnnaBridge 171:3a7713b1edbc 1161 * @brief Sets the TIM Autoreload Register value on runtime without calling
AnnaBridge 171:3a7713b1edbc 1162 * another time any Init function.
AnnaBridge 171:3a7713b1edbc 1163 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1164 * @param __AUTORELOAD__: specifies the Counter register new value.
AnnaBridge 171:3a7713b1edbc 1165 * @retval None
AnnaBridge 171:3a7713b1edbc 1166 */
AnnaBridge 171:3a7713b1edbc 1167 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
AnnaBridge 171:3a7713b1edbc 1168 do{ \
AnnaBridge 171:3a7713b1edbc 1169 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
AnnaBridge 171:3a7713b1edbc 1170 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
AnnaBridge 171:3a7713b1edbc 1171 } while(0)
AnnaBridge 171:3a7713b1edbc 1172 /**
AnnaBridge 171:3a7713b1edbc 1173 * @brief Gets the TIM Autoreload Register value on runtime
AnnaBridge 171:3a7713b1edbc 1174 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1175 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
AnnaBridge 171:3a7713b1edbc 1176 */
AnnaBridge 171:3a7713b1edbc 1177 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
AnnaBridge 171:3a7713b1edbc 1178
AnnaBridge 171:3a7713b1edbc 1179 /**
AnnaBridge 171:3a7713b1edbc 1180 * @brief Sets the TIM Clock Division value on runtime without calling
AnnaBridge 171:3a7713b1edbc 1181 * another time any Init function.
AnnaBridge 171:3a7713b1edbc 1182 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1183 * @param __CKD__: specifies the clock division value.
AnnaBridge 171:3a7713b1edbc 1184 * This parameter can be one of the following value:
AnnaBridge 171:3a7713b1edbc 1185 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge 171:3a7713b1edbc 1186 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge 171:3a7713b1edbc 1187 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
AnnaBridge 171:3a7713b1edbc 1188 * @retval None
AnnaBridge 171:3a7713b1edbc 1189 */
AnnaBridge 171:3a7713b1edbc 1190 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
AnnaBridge 171:3a7713b1edbc 1191 do{ \
AnnaBridge 171:3a7713b1edbc 1192 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
AnnaBridge 171:3a7713b1edbc 1193 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
AnnaBridge 171:3a7713b1edbc 1194 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
AnnaBridge 171:3a7713b1edbc 1195 } while(0)
AnnaBridge 171:3a7713b1edbc 1196 /**
AnnaBridge 171:3a7713b1edbc 1197 * @brief Gets the TIM Clock Division value on runtime.
AnnaBridge 171:3a7713b1edbc 1198 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1199 * @retval The clock division can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1200 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge 171:3a7713b1edbc 1201 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge 171:3a7713b1edbc 1202 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
AnnaBridge 171:3a7713b1edbc 1203 */
AnnaBridge 171:3a7713b1edbc 1204 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
AnnaBridge 171:3a7713b1edbc 1205
AnnaBridge 171:3a7713b1edbc 1206 /**
AnnaBridge 171:3a7713b1edbc 1207 * @brief Sets the TIM Input Capture prescaler on runtime without calling
AnnaBridge 171:3a7713b1edbc 1208 * another time HAL_TIM_IC_ConfigChannel() function.
AnnaBridge 171:3a7713b1edbc 1209 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1210 * @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge 171:3a7713b1edbc 1211 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1212 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 171:3a7713b1edbc 1213 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 171:3a7713b1edbc 1214 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 171:3a7713b1edbc 1215 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 171:3a7713b1edbc 1216 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
AnnaBridge 171:3a7713b1edbc 1217 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1218 * @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge 171:3a7713b1edbc 1219 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge 171:3a7713b1edbc 1220 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge 171:3a7713b1edbc 1221 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge 171:3a7713b1edbc 1222 * @retval None
AnnaBridge 171:3a7713b1edbc 1223 */
AnnaBridge 171:3a7713b1edbc 1224 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge 171:3a7713b1edbc 1225 do{ \
AnnaBridge 171:3a7713b1edbc 1226 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
AnnaBridge 171:3a7713b1edbc 1227 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
AnnaBridge 171:3a7713b1edbc 1228 } while(0)
AnnaBridge 171:3a7713b1edbc 1229
AnnaBridge 171:3a7713b1edbc 1230 /**
AnnaBridge 171:3a7713b1edbc 1231 * @brief Gets the TIM Input Capture prescaler on runtime.
AnnaBridge 171:3a7713b1edbc 1232 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1233 * @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge 171:3a7713b1edbc 1234 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1235 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
AnnaBridge 171:3a7713b1edbc 1236 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
AnnaBridge 171:3a7713b1edbc 1237 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
AnnaBridge 171:3a7713b1edbc 1238 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
AnnaBridge 171:3a7713b1edbc 1239 * @retval The input capture prescaler can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1240 * @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge 171:3a7713b1edbc 1241 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge 171:3a7713b1edbc 1242 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge 171:3a7713b1edbc 1243 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge 171:3a7713b1edbc 1244 */
AnnaBridge 171:3a7713b1edbc 1245 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
AnnaBridge 171:3a7713b1edbc 1246 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
AnnaBridge 171:3a7713b1edbc 1247 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
AnnaBridge 171:3a7713b1edbc 1248 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
AnnaBridge 171:3a7713b1edbc 1249 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
AnnaBridge 171:3a7713b1edbc 1250
AnnaBridge 171:3a7713b1edbc 1251 /**
AnnaBridge 171:3a7713b1edbc 1252 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge 171:3a7713b1edbc 1253 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1254 * @note When the USR bit of the TIMx_CR1 register is set, only counter
AnnaBridge 171:3a7713b1edbc 1255 * overflow/underflow generates an update interrupt or DMA request (if
AnnaBridge 171:3a7713b1edbc 1256 * enabled)
AnnaBridge 171:3a7713b1edbc 1257 * @retval None
AnnaBridge 171:3a7713b1edbc 1258 */
AnnaBridge 171:3a7713b1edbc 1259 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 1260 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
AnnaBridge 171:3a7713b1edbc 1261
AnnaBridge 171:3a7713b1edbc 1262 /**
AnnaBridge 171:3a7713b1edbc 1263 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge 171:3a7713b1edbc 1264 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1265 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
AnnaBridge 171:3a7713b1edbc 1266 * following events generate an update interrupt or DMA request (if
AnnaBridge 171:3a7713b1edbc 1267 * enabled):
AnnaBridge 171:3a7713b1edbc 1268 * _ Counter overflow/underflow
AnnaBridge 171:3a7713b1edbc 1269 * _ Setting the UG bit
AnnaBridge 171:3a7713b1edbc 1270 * _ Update generation through the slave mode controller
AnnaBridge 171:3a7713b1edbc 1271 * @retval None
AnnaBridge 171:3a7713b1edbc 1272 */
AnnaBridge 171:3a7713b1edbc 1273 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 1274 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
AnnaBridge 171:3a7713b1edbc 1275
AnnaBridge 171:3a7713b1edbc 1276 /**
AnnaBridge 171:3a7713b1edbc 1277 * @brief Sets the TIM Capture x input polarity on runtime.
AnnaBridge 171:3a7713b1edbc 1278 * @param __HANDLE__: TIM handle.
AnnaBridge 171:3a7713b1edbc 1279 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 171:3a7713b1edbc 1280 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1281 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 171:3a7713b1edbc 1282 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 171:3a7713b1edbc 1283 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 171:3a7713b1edbc 1284 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 171:3a7713b1edbc 1285 * @param __POLARITY__: Polarity for TIx source
AnnaBridge 171:3a7713b1edbc 1286 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
AnnaBridge 171:3a7713b1edbc 1287 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
AnnaBridge 171:3a7713b1edbc 1288 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
AnnaBridge 171:3a7713b1edbc 1289 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
AnnaBridge 171:3a7713b1edbc 1290 * @retval None
AnnaBridge 171:3a7713b1edbc 1291 */
AnnaBridge 171:3a7713b1edbc 1292 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge 171:3a7713b1edbc 1293 do{ \
AnnaBridge 171:3a7713b1edbc 1294 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
AnnaBridge 171:3a7713b1edbc 1295 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
AnnaBridge 171:3a7713b1edbc 1296 }while(0)
AnnaBridge 171:3a7713b1edbc 1297 /**
AnnaBridge 171:3a7713b1edbc 1298 * @}
AnnaBridge 171:3a7713b1edbc 1299 */
AnnaBridge 171:3a7713b1edbc 1300
AnnaBridge 171:3a7713b1edbc 1301 /* Include TIM HAL Extension module */
AnnaBridge 171:3a7713b1edbc 1302 #include "stm32f2xx_hal_tim_ex.h"
AnnaBridge 171:3a7713b1edbc 1303
AnnaBridge 171:3a7713b1edbc 1304 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1305 /** @addtogroup TIM_Exported_Functions
AnnaBridge 171:3a7713b1edbc 1306 * @{
AnnaBridge 171:3a7713b1edbc 1307 */
AnnaBridge 171:3a7713b1edbc 1308
AnnaBridge 171:3a7713b1edbc 1309 /** @addtogroup TIM_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 1310 * @{
AnnaBridge 171:3a7713b1edbc 1311 */
AnnaBridge 171:3a7713b1edbc 1312
AnnaBridge 171:3a7713b1edbc 1313 /* Time Base functions ********************************************************/
AnnaBridge 171:3a7713b1edbc 1314 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1315 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1316 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1317 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1318 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 1319 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1320 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1321 /* Non-Blocking mode: Interrupt */
AnnaBridge 171:3a7713b1edbc 1322 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1323 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1324 /* Non-Blocking mode: DMA */
AnnaBridge 171:3a7713b1edbc 1325 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
AnnaBridge 171:3a7713b1edbc 1326 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1327 /**
AnnaBridge 171:3a7713b1edbc 1328 * @}
AnnaBridge 171:3a7713b1edbc 1329 */
AnnaBridge 171:3a7713b1edbc 1330
AnnaBridge 171:3a7713b1edbc 1331 /** @addtogroup TIM_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 1332 * @{
AnnaBridge 171:3a7713b1edbc 1333 */
AnnaBridge 171:3a7713b1edbc 1334 /* Timer Output Compare functions **********************************************/
AnnaBridge 171:3a7713b1edbc 1335 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1336 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1337 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1338 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1339 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 1340 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1341 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1342 /* Non-Blocking mode: Interrupt */
AnnaBridge 171:3a7713b1edbc 1343 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1344 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1345 /* Non-Blocking mode: DMA */
AnnaBridge 171:3a7713b1edbc 1346 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 171:3a7713b1edbc 1347 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1348
AnnaBridge 171:3a7713b1edbc 1349 /**
AnnaBridge 171:3a7713b1edbc 1350 * @}
AnnaBridge 171:3a7713b1edbc 1351 */
AnnaBridge 171:3a7713b1edbc 1352
AnnaBridge 171:3a7713b1edbc 1353 /** @addtogroup TIM_Exported_Functions_Group3
AnnaBridge 171:3a7713b1edbc 1354 * @{
AnnaBridge 171:3a7713b1edbc 1355 */
AnnaBridge 171:3a7713b1edbc 1356 /* Timer PWM functions *********************************************************/
AnnaBridge 171:3a7713b1edbc 1357 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1358 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1359 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1360 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1361 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 1362 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1363 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1364 /* Non-Blocking mode: Interrupt */
AnnaBridge 171:3a7713b1edbc 1365 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1366 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1367 /* Non-Blocking mode: DMA */
AnnaBridge 171:3a7713b1edbc 1368 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 171:3a7713b1edbc 1369 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1370
AnnaBridge 171:3a7713b1edbc 1371 /**
AnnaBridge 171:3a7713b1edbc 1372 * @}
AnnaBridge 171:3a7713b1edbc 1373 */
AnnaBridge 171:3a7713b1edbc 1374
AnnaBridge 171:3a7713b1edbc 1375 /** @addtogroup TIM_Exported_Functions_Group4
AnnaBridge 171:3a7713b1edbc 1376 * @{
AnnaBridge 171:3a7713b1edbc 1377 */
AnnaBridge 171:3a7713b1edbc 1378 /* Timer Input Capture functions ***********************************************/
AnnaBridge 171:3a7713b1edbc 1379 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1380 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1381 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1382 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1383 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 1384 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1385 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1386 /* Non-Blocking mode: Interrupt */
AnnaBridge 171:3a7713b1edbc 1387 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1388 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1389 /* Non-Blocking mode: DMA */
AnnaBridge 171:3a7713b1edbc 1390 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 171:3a7713b1edbc 1391 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1392
AnnaBridge 171:3a7713b1edbc 1393 /**
AnnaBridge 171:3a7713b1edbc 1394 * @}
AnnaBridge 171:3a7713b1edbc 1395 */
AnnaBridge 171:3a7713b1edbc 1396
AnnaBridge 171:3a7713b1edbc 1397 /** @addtogroup TIM_Exported_Functions_Group5
AnnaBridge 171:3a7713b1edbc 1398 * @{
AnnaBridge 171:3a7713b1edbc 1399 */
AnnaBridge 171:3a7713b1edbc 1400 /* Timer One Pulse functions ***************************************************/
AnnaBridge 171:3a7713b1edbc 1401 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
AnnaBridge 171:3a7713b1edbc 1402 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1403 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1404 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1405 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 1406 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 171:3a7713b1edbc 1407 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 171:3a7713b1edbc 1408
AnnaBridge 171:3a7713b1edbc 1409 /* Non-Blocking mode: Interrupt */
AnnaBridge 171:3a7713b1edbc 1410 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 171:3a7713b1edbc 1411 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 171:3a7713b1edbc 1412
AnnaBridge 171:3a7713b1edbc 1413 /**
AnnaBridge 171:3a7713b1edbc 1414 * @}
AnnaBridge 171:3a7713b1edbc 1415 */
AnnaBridge 171:3a7713b1edbc 1416
AnnaBridge 171:3a7713b1edbc 1417 /** @addtogroup TIM_Exported_Functions_Group6
AnnaBridge 171:3a7713b1edbc 1418 * @{
AnnaBridge 171:3a7713b1edbc 1419 */
AnnaBridge 171:3a7713b1edbc 1420 /* Timer Encoder functions *****************************************************/
AnnaBridge 171:3a7713b1edbc 1421 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
AnnaBridge 171:3a7713b1edbc 1422 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1423 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1424 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1425 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 1426 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1427 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1428 /* Non-Blocking mode: Interrupt */
AnnaBridge 171:3a7713b1edbc 1429 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1430 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1431 /* Non-Blocking mode: DMA */
AnnaBridge 171:3a7713b1edbc 1432 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
AnnaBridge 171:3a7713b1edbc 1433 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1434
AnnaBridge 171:3a7713b1edbc 1435 /**
AnnaBridge 171:3a7713b1edbc 1436 * @}
AnnaBridge 171:3a7713b1edbc 1437 */
AnnaBridge 171:3a7713b1edbc 1438
AnnaBridge 171:3a7713b1edbc 1439 /** @addtogroup TIM_Exported_Functions_Group7
AnnaBridge 171:3a7713b1edbc 1440 * @{
AnnaBridge 171:3a7713b1edbc 1441 */
AnnaBridge 171:3a7713b1edbc 1442 /* Interrupt Handler functions **********************************************/
AnnaBridge 171:3a7713b1edbc 1443 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1444
AnnaBridge 171:3a7713b1edbc 1445 /**
AnnaBridge 171:3a7713b1edbc 1446 * @}
AnnaBridge 171:3a7713b1edbc 1447 */
AnnaBridge 171:3a7713b1edbc 1448
AnnaBridge 171:3a7713b1edbc 1449 /** @addtogroup TIM_Exported_Functions_Group8
AnnaBridge 171:3a7713b1edbc 1450 * @{
AnnaBridge 171:3a7713b1edbc 1451 */
AnnaBridge 171:3a7713b1edbc 1452 /* Control functions *********************************************************/
AnnaBridge 171:3a7713b1edbc 1453 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1454 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1455 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1456 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
AnnaBridge 171:3a7713b1edbc 1457 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1458 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
AnnaBridge 171:3a7713b1edbc 1459 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
AnnaBridge 171:3a7713b1edbc 1460 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
AnnaBridge 171:3a7713b1edbc 1461 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
AnnaBridge 171:3a7713b1edbc 1462 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 171:3a7713b1edbc 1463 uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge 171:3a7713b1edbc 1464 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge 171:3a7713b1edbc 1465 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 171:3a7713b1edbc 1466 uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge 171:3a7713b1edbc 1467 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge 171:3a7713b1edbc 1468 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
AnnaBridge 171:3a7713b1edbc 1469 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 1470
AnnaBridge 171:3a7713b1edbc 1471 /**
AnnaBridge 171:3a7713b1edbc 1472 * @}
AnnaBridge 171:3a7713b1edbc 1473 */
AnnaBridge 171:3a7713b1edbc 1474
AnnaBridge 171:3a7713b1edbc 1475 /** @addtogroup TIM_Exported_Functions_Group9
AnnaBridge 171:3a7713b1edbc 1476 * @{
AnnaBridge 171:3a7713b1edbc 1477 */
AnnaBridge 171:3a7713b1edbc 1478 /* Callback in non blocking modes (Interrupt and DMA) *************************/
AnnaBridge 171:3a7713b1edbc 1479 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1480 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1481 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1482 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1483 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1484 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1485
AnnaBridge 171:3a7713b1edbc 1486 /**
AnnaBridge 171:3a7713b1edbc 1487 * @}
AnnaBridge 171:3a7713b1edbc 1488 */
AnnaBridge 171:3a7713b1edbc 1489
AnnaBridge 171:3a7713b1edbc 1490 /** @addtogroup TIM_Exported_Functions_Group10
AnnaBridge 171:3a7713b1edbc 1491 * @{
AnnaBridge 171:3a7713b1edbc 1492 */
AnnaBridge 171:3a7713b1edbc 1493 /* Peripheral State functions **************************************************/
AnnaBridge 171:3a7713b1edbc 1494 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1495 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1496 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1497 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1498 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1499 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 1500
AnnaBridge 171:3a7713b1edbc 1501 /**
AnnaBridge 171:3a7713b1edbc 1502 * @}
AnnaBridge 171:3a7713b1edbc 1503 */
AnnaBridge 171:3a7713b1edbc 1504
AnnaBridge 171:3a7713b1edbc 1505 /**
AnnaBridge 171:3a7713b1edbc 1506 * @}
AnnaBridge 171:3a7713b1edbc 1507 */
AnnaBridge 171:3a7713b1edbc 1508
AnnaBridge 171:3a7713b1edbc 1509 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1510 /** @defgroup TIM_Private_Macros TIM Private Macros
AnnaBridge 171:3a7713b1edbc 1511 * @{
AnnaBridge 171:3a7713b1edbc 1512 */
AnnaBridge 171:3a7713b1edbc 1513
AnnaBridge 171:3a7713b1edbc 1514 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
AnnaBridge 171:3a7713b1edbc 1515 * @{
AnnaBridge 171:3a7713b1edbc 1516 */
AnnaBridge 171:3a7713b1edbc 1517 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
AnnaBridge 171:3a7713b1edbc 1518 ((MODE) == TIM_COUNTERMODE_DOWN) || \
AnnaBridge 171:3a7713b1edbc 1519 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
AnnaBridge 171:3a7713b1edbc 1520 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
AnnaBridge 171:3a7713b1edbc 1521 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
AnnaBridge 171:3a7713b1edbc 1522
AnnaBridge 171:3a7713b1edbc 1523 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
AnnaBridge 171:3a7713b1edbc 1524 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
AnnaBridge 171:3a7713b1edbc 1525 ((DIV) == TIM_CLOCKDIVISION_DIV4))
AnnaBridge 171:3a7713b1edbc 1526
AnnaBridge 171:3a7713b1edbc 1527 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
AnnaBridge 171:3a7713b1edbc 1528 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
AnnaBridge 171:3a7713b1edbc 1529
AnnaBridge 171:3a7713b1edbc 1530 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
AnnaBridge 171:3a7713b1edbc 1531 ((MODE) == TIM_OCMODE_PWM2))
AnnaBridge 171:3a7713b1edbc 1532
AnnaBridge 171:3a7713b1edbc 1533 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
AnnaBridge 171:3a7713b1edbc 1534 ((MODE) == TIM_OCMODE_ACTIVE) || \
AnnaBridge 171:3a7713b1edbc 1535 ((MODE) == TIM_OCMODE_INACTIVE) || \
AnnaBridge 171:3a7713b1edbc 1536 ((MODE) == TIM_OCMODE_TOGGLE) || \
AnnaBridge 171:3a7713b1edbc 1537 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
AnnaBridge 171:3a7713b1edbc 1538 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
AnnaBridge 171:3a7713b1edbc 1539
AnnaBridge 171:3a7713b1edbc 1540 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
AnnaBridge 171:3a7713b1edbc 1541 ((STATE) == TIM_OCFAST_ENABLE))
AnnaBridge 171:3a7713b1edbc 1542
AnnaBridge 171:3a7713b1edbc 1543 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
AnnaBridge 171:3a7713b1edbc 1544 ((POLARITY) == TIM_OCPOLARITY_LOW))
AnnaBridge 171:3a7713b1edbc 1545
AnnaBridge 171:3a7713b1edbc 1546 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
AnnaBridge 171:3a7713b1edbc 1547 ((POLARITY) == TIM_OCNPOLARITY_LOW))
AnnaBridge 171:3a7713b1edbc 1548
AnnaBridge 171:3a7713b1edbc 1549 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
AnnaBridge 171:3a7713b1edbc 1550 ((STATE) == TIM_OCIDLESTATE_RESET))
AnnaBridge 171:3a7713b1edbc 1551
AnnaBridge 171:3a7713b1edbc 1552 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
AnnaBridge 171:3a7713b1edbc 1553 ((STATE) == TIM_OCNIDLESTATE_RESET))
AnnaBridge 171:3a7713b1edbc 1554
AnnaBridge 171:3a7713b1edbc 1555 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 1556 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 1557 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 1558 ((CHANNEL) == TIM_CHANNEL_4) || \
AnnaBridge 171:3a7713b1edbc 1559 ((CHANNEL) == TIM_CHANNEL_ALL))
AnnaBridge 171:3a7713b1edbc 1560
AnnaBridge 171:3a7713b1edbc 1561 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 1562 ((CHANNEL) == TIM_CHANNEL_2))
AnnaBridge 171:3a7713b1edbc 1563
AnnaBridge 171:3a7713b1edbc 1564 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 1565 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 1566 ((CHANNEL) == TIM_CHANNEL_3))
AnnaBridge 171:3a7713b1edbc 1567
AnnaBridge 171:3a7713b1edbc 1568 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
AnnaBridge 171:3a7713b1edbc 1569 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
AnnaBridge 171:3a7713b1edbc 1570 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
AnnaBridge 171:3a7713b1edbc 1571
AnnaBridge 171:3a7713b1edbc 1572 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
AnnaBridge 171:3a7713b1edbc 1573 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
AnnaBridge 171:3a7713b1edbc 1574 ((SELECTION) == TIM_ICSELECTION_TRC))
AnnaBridge 171:3a7713b1edbc 1575
AnnaBridge 171:3a7713b1edbc 1576 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
AnnaBridge 171:3a7713b1edbc 1577 ((PRESCALER) == TIM_ICPSC_DIV2) || \
AnnaBridge 171:3a7713b1edbc 1578 ((PRESCALER) == TIM_ICPSC_DIV4) || \
AnnaBridge 171:3a7713b1edbc 1579 ((PRESCALER) == TIM_ICPSC_DIV8))
AnnaBridge 171:3a7713b1edbc 1580
AnnaBridge 171:3a7713b1edbc 1581 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
AnnaBridge 171:3a7713b1edbc 1582 ((MODE) == TIM_OPMODE_REPETITIVE))
AnnaBridge 171:3a7713b1edbc 1583
AnnaBridge 171:3a7713b1edbc 1584 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
AnnaBridge 171:3a7713b1edbc 1585
AnnaBridge 171:3a7713b1edbc 1586 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
AnnaBridge 171:3a7713b1edbc 1587 ((MODE) == TIM_ENCODERMODE_TI2) || \
AnnaBridge 171:3a7713b1edbc 1588 ((MODE) == TIM_ENCODERMODE_TI12))
AnnaBridge 171:3a7713b1edbc 1589
AnnaBridge 171:3a7713b1edbc 1590 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
AnnaBridge 171:3a7713b1edbc 1591
AnnaBridge 171:3a7713b1edbc 1592 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
AnnaBridge 171:3a7713b1edbc 1593 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
AnnaBridge 171:3a7713b1edbc 1594 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
AnnaBridge 171:3a7713b1edbc 1595 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
AnnaBridge 171:3a7713b1edbc 1596 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
AnnaBridge 171:3a7713b1edbc 1597 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
AnnaBridge 171:3a7713b1edbc 1598 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
AnnaBridge 171:3a7713b1edbc 1599 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
AnnaBridge 171:3a7713b1edbc 1600 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
AnnaBridge 171:3a7713b1edbc 1601 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
AnnaBridge 171:3a7713b1edbc 1602
AnnaBridge 171:3a7713b1edbc 1603 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
AnnaBridge 171:3a7713b1edbc 1604 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
AnnaBridge 171:3a7713b1edbc 1605 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
AnnaBridge 171:3a7713b1edbc 1606 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
AnnaBridge 171:3a7713b1edbc 1607 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
AnnaBridge 171:3a7713b1edbc 1608
AnnaBridge 171:3a7713b1edbc 1609 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
AnnaBridge 171:3a7713b1edbc 1610 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
AnnaBridge 171:3a7713b1edbc 1611 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
AnnaBridge 171:3a7713b1edbc 1612 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
AnnaBridge 171:3a7713b1edbc 1613
AnnaBridge 171:3a7713b1edbc 1614 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
AnnaBridge 171:3a7713b1edbc 1615
AnnaBridge 171:3a7713b1edbc 1616 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
AnnaBridge 171:3a7713b1edbc 1617 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
AnnaBridge 171:3a7713b1edbc 1618
AnnaBridge 171:3a7713b1edbc 1619 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
AnnaBridge 171:3a7713b1edbc 1620 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
AnnaBridge 171:3a7713b1edbc 1621
AnnaBridge 171:3a7713b1edbc 1622 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
AnnaBridge 171:3a7713b1edbc 1623 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
AnnaBridge 171:3a7713b1edbc 1624 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
AnnaBridge 171:3a7713b1edbc 1625 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
AnnaBridge 171:3a7713b1edbc 1626
AnnaBridge 171:3a7713b1edbc 1627 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
AnnaBridge 171:3a7713b1edbc 1628
AnnaBridge 171:3a7713b1edbc 1629 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 1630 ((STATE) == TIM_OSSR_DISABLE))
AnnaBridge 171:3a7713b1edbc 1631
AnnaBridge 171:3a7713b1edbc 1632 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 1633 ((STATE) == TIM_OSSI_DISABLE))
AnnaBridge 171:3a7713b1edbc 1634
AnnaBridge 171:3a7713b1edbc 1635 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
AnnaBridge 171:3a7713b1edbc 1636 ((LEVEL) == TIM_LOCKLEVEL_1) || \
AnnaBridge 171:3a7713b1edbc 1637 ((LEVEL) == TIM_LOCKLEVEL_2) || \
AnnaBridge 171:3a7713b1edbc 1638 ((LEVEL) == TIM_LOCKLEVEL_3))
AnnaBridge 171:3a7713b1edbc 1639
AnnaBridge 171:3a7713b1edbc 1640 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 1641 ((STATE) == TIM_BREAK_DISABLE))
AnnaBridge 171:3a7713b1edbc 1642
AnnaBridge 171:3a7713b1edbc 1643 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
AnnaBridge 171:3a7713b1edbc 1644 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
AnnaBridge 171:3a7713b1edbc 1645
AnnaBridge 171:3a7713b1edbc 1646 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 1647 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
AnnaBridge 171:3a7713b1edbc 1648
AnnaBridge 171:3a7713b1edbc 1649 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
AnnaBridge 171:3a7713b1edbc 1650 ((SOURCE) == TIM_TRGO_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 1651 ((SOURCE) == TIM_TRGO_UPDATE) || \
AnnaBridge 171:3a7713b1edbc 1652 ((SOURCE) == TIM_TRGO_OC1) || \
AnnaBridge 171:3a7713b1edbc 1653 ((SOURCE) == TIM_TRGO_OC1REF) || \
AnnaBridge 171:3a7713b1edbc 1654 ((SOURCE) == TIM_TRGO_OC2REF) || \
AnnaBridge 171:3a7713b1edbc 1655 ((SOURCE) == TIM_TRGO_OC3REF) || \
AnnaBridge 171:3a7713b1edbc 1656 ((SOURCE) == TIM_TRGO_OC4REF))
AnnaBridge 171:3a7713b1edbc 1657
AnnaBridge 171:3a7713b1edbc 1658 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
AnnaBridge 171:3a7713b1edbc 1659 ((MODE) == TIM_SLAVEMODE_GATED) || \
AnnaBridge 171:3a7713b1edbc 1660 ((MODE) == TIM_SLAVEMODE_RESET) || \
AnnaBridge 171:3a7713b1edbc 1661 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
AnnaBridge 171:3a7713b1edbc 1662 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
AnnaBridge 171:3a7713b1edbc 1663
AnnaBridge 171:3a7713b1edbc 1664 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 1665 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
AnnaBridge 171:3a7713b1edbc 1666
AnnaBridge 171:3a7713b1edbc 1667 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
AnnaBridge 171:3a7713b1edbc 1668 ((SELECTION) == TIM_TS_ITR1) || \
AnnaBridge 171:3a7713b1edbc 1669 ((SELECTION) == TIM_TS_ITR2) || \
AnnaBridge 171:3a7713b1edbc 1670 ((SELECTION) == TIM_TS_ITR3) || \
AnnaBridge 171:3a7713b1edbc 1671 ((SELECTION) == TIM_TS_TI1F_ED) || \
AnnaBridge 171:3a7713b1edbc 1672 ((SELECTION) == TIM_TS_TI1FP1) || \
AnnaBridge 171:3a7713b1edbc 1673 ((SELECTION) == TIM_TS_TI2FP2) || \
AnnaBridge 171:3a7713b1edbc 1674 ((SELECTION) == TIM_TS_ETRF))
AnnaBridge 171:3a7713b1edbc 1675
AnnaBridge 171:3a7713b1edbc 1676 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
AnnaBridge 171:3a7713b1edbc 1677 ((SELECTION) == TIM_TS_ITR1) || \
AnnaBridge 171:3a7713b1edbc 1678 ((SELECTION) == TIM_TS_ITR2) || \
AnnaBridge 171:3a7713b1edbc 1679 ((SELECTION) == TIM_TS_ITR3) || \
AnnaBridge 171:3a7713b1edbc 1680 ((SELECTION) == TIM_TS_NONE))
AnnaBridge 171:3a7713b1edbc 1681
AnnaBridge 171:3a7713b1edbc 1682 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
AnnaBridge 171:3a7713b1edbc 1683 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
AnnaBridge 171:3a7713b1edbc 1684 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
AnnaBridge 171:3a7713b1edbc 1685 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
AnnaBridge 171:3a7713b1edbc 1686 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
AnnaBridge 171:3a7713b1edbc 1687
AnnaBridge 171:3a7713b1edbc 1688 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
AnnaBridge 171:3a7713b1edbc 1689 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
AnnaBridge 171:3a7713b1edbc 1690 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
AnnaBridge 171:3a7713b1edbc 1691 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
AnnaBridge 171:3a7713b1edbc 1692
AnnaBridge 171:3a7713b1edbc 1693 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
AnnaBridge 171:3a7713b1edbc 1694
AnnaBridge 171:3a7713b1edbc 1695 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
AnnaBridge 171:3a7713b1edbc 1696 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
AnnaBridge 171:3a7713b1edbc 1697
AnnaBridge 171:3a7713b1edbc 1698 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
AnnaBridge 171:3a7713b1edbc 1699 ((BASE) == TIM_DMABASE_CR2) || \
AnnaBridge 171:3a7713b1edbc 1700 ((BASE) == TIM_DMABASE_SMCR) || \
AnnaBridge 171:3a7713b1edbc 1701 ((BASE) == TIM_DMABASE_DIER) || \
AnnaBridge 171:3a7713b1edbc 1702 ((BASE) == TIM_DMABASE_SR) || \
AnnaBridge 171:3a7713b1edbc 1703 ((BASE) == TIM_DMABASE_EGR) || \
AnnaBridge 171:3a7713b1edbc 1704 ((BASE) == TIM_DMABASE_CCMR1) || \
AnnaBridge 171:3a7713b1edbc 1705 ((BASE) == TIM_DMABASE_CCMR2) || \
AnnaBridge 171:3a7713b1edbc 1706 ((BASE) == TIM_DMABASE_CCER) || \
AnnaBridge 171:3a7713b1edbc 1707 ((BASE) == TIM_DMABASE_CNT) || \
AnnaBridge 171:3a7713b1edbc 1708 ((BASE) == TIM_DMABASE_PSC) || \
AnnaBridge 171:3a7713b1edbc 1709 ((BASE) == TIM_DMABASE_ARR) || \
AnnaBridge 171:3a7713b1edbc 1710 ((BASE) == TIM_DMABASE_RCR) || \
AnnaBridge 171:3a7713b1edbc 1711 ((BASE) == TIM_DMABASE_CCR1) || \
AnnaBridge 171:3a7713b1edbc 1712 ((BASE) == TIM_DMABASE_CCR2) || \
AnnaBridge 171:3a7713b1edbc 1713 ((BASE) == TIM_DMABASE_CCR3) || \
AnnaBridge 171:3a7713b1edbc 1714 ((BASE) == TIM_DMABASE_CCR4) || \
AnnaBridge 171:3a7713b1edbc 1715 ((BASE) == TIM_DMABASE_BDTR) || \
AnnaBridge 171:3a7713b1edbc 1716 ((BASE) == TIM_DMABASE_DCR) || \
AnnaBridge 171:3a7713b1edbc 1717 ((BASE) == TIM_DMABASE_OR))
AnnaBridge 171:3a7713b1edbc 1718
AnnaBridge 171:3a7713b1edbc 1719 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
AnnaBridge 171:3a7713b1edbc 1720 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1721 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1722 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1723 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1724 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1725 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1726 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1727 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1728 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1729 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1730 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1731 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1732 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1733 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1734 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1735 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
AnnaBridge 171:3a7713b1edbc 1736 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
AnnaBridge 171:3a7713b1edbc 1737
AnnaBridge 171:3a7713b1edbc 1738 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
AnnaBridge 171:3a7713b1edbc 1739 /**
AnnaBridge 171:3a7713b1edbc 1740 * @}
AnnaBridge 171:3a7713b1edbc 1741 */
AnnaBridge 171:3a7713b1edbc 1742
AnnaBridge 171:3a7713b1edbc 1743 /** @defgroup TIM_Mask_Definitions TIM Mask Definition
AnnaBridge 171:3a7713b1edbc 1744 * @{
AnnaBridge 171:3a7713b1edbc 1745 */
AnnaBridge 171:3a7713b1edbc 1746 /* The counter of a timer instance is disabled only if all the CCx and CCxN
AnnaBridge 171:3a7713b1edbc 1747 channels have been disabled */
AnnaBridge 171:3a7713b1edbc 1748 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
AnnaBridge 171:3a7713b1edbc 1749 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
AnnaBridge 171:3a7713b1edbc 1750 /**
AnnaBridge 171:3a7713b1edbc 1751 * @}
AnnaBridge 171:3a7713b1edbc 1752 */
AnnaBridge 171:3a7713b1edbc 1753
AnnaBridge 171:3a7713b1edbc 1754 /**
AnnaBridge 171:3a7713b1edbc 1755 * @}
AnnaBridge 171:3a7713b1edbc 1756 */
AnnaBridge 171:3a7713b1edbc 1757
AnnaBridge 171:3a7713b1edbc 1758 /* Private functions ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1759 /** @defgroup TIM_Private_Functions TIM Private Functions
AnnaBridge 171:3a7713b1edbc 1760 * @{
AnnaBridge 171:3a7713b1edbc 1761 */
AnnaBridge 171:3a7713b1edbc 1762 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
AnnaBridge 171:3a7713b1edbc 1763 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
AnnaBridge 171:3a7713b1edbc 1764 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
AnnaBridge 171:3a7713b1edbc 1765 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 1766 void TIM_DMAError(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 1767 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 1768 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
AnnaBridge 171:3a7713b1edbc 1769 /**
AnnaBridge 171:3a7713b1edbc 1770 * @}
AnnaBridge 171:3a7713b1edbc 1771 */
AnnaBridge 171:3a7713b1edbc 1772
AnnaBridge 171:3a7713b1edbc 1773 /**
AnnaBridge 171:3a7713b1edbc 1774 * @}
AnnaBridge 171:3a7713b1edbc 1775 */
AnnaBridge 171:3a7713b1edbc 1776
AnnaBridge 171:3a7713b1edbc 1777 /**
AnnaBridge 171:3a7713b1edbc 1778 * @}
AnnaBridge 171:3a7713b1edbc 1779 */
AnnaBridge 171:3a7713b1edbc 1780
AnnaBridge 171:3a7713b1edbc 1781 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 1782 }
AnnaBridge 171:3a7713b1edbc 1783 #endif
AnnaBridge 171:3a7713b1edbc 1784
AnnaBridge 171:3a7713b1edbc 1785 #endif /* __STM32F2xx_HAL_TIM_H */
AnnaBridge 171:3a7713b1edbc 1786
AnnaBridge 171:3a7713b1edbc 1787 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/