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TARGET_NUCLEO_F207ZG/TOOLCHAIN_ARM_STD/stm32f2xx_ll_sdmmc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f2xx_ll_sdmmc.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @version V1.2.1
AnnaBridge	171:3a7713b1edbc	6	* @date 14-April-2017
AnnaBridge	171:3a7713b1edbc	7	* @brief Header file of SDMMC HAL module.
AnnaBridge	171:3a7713b1edbc	8	******************************************************************************
AnnaBridge	171:3a7713b1edbc	9	* @attention
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	12	*
AnnaBridge	171:3a7713b1edbc	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	14	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	19	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	21	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	22	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	23	*
AnnaBridge	171:3a7713b1edbc	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	34	*
AnnaBridge	171:3a7713b1edbc	35	******************************************************************************
AnnaBridge	171:3a7713b1edbc	36	*/
AnnaBridge	171:3a7713b1edbc	37
AnnaBridge	171:3a7713b1edbc	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	39	#ifndef __STM32F2xx_LL_SDMMC_H
AnnaBridge	171:3a7713b1edbc	40	#define __STM32F2xx_LL_SDMMC_H
AnnaBridge	171:3a7713b1edbc	41
AnnaBridge	171:3a7713b1edbc	42	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	43	extern "C" {
AnnaBridge	171:3a7713b1edbc	44	#endif
AnnaBridge	171:3a7713b1edbc	45
AnnaBridge	171:3a7713b1edbc	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	47	#include "stm32f2xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	48
AnnaBridge	171:3a7713b1edbc	49	/** @addtogroup STM32F2xx_Driver
AnnaBridge	171:3a7713b1edbc	50	* @{
AnnaBridge	171:3a7713b1edbc	51	*/
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	/** @addtogroup SDMMC_LL
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
AnnaBridge	171:3a7713b1edbc	59	* @{
AnnaBridge	171:3a7713b1edbc	60	*/
AnnaBridge	171:3a7713b1edbc	61
AnnaBridge	171:3a7713b1edbc	62	/**
AnnaBridge	171:3a7713b1edbc	63	* @brief SDMMC Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	64	*/
AnnaBridge	171:3a7713b1edbc	65	typedef struct
AnnaBridge	171:3a7713b1edbc	66	{
AnnaBridge	171:3a7713b1edbc	67	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
AnnaBridge	171:3a7713b1edbc	68	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
AnnaBridge	171:3a7713b1edbc	69
AnnaBridge	171:3a7713b1edbc	70	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
AnnaBridge	171:3a7713b1edbc	71	enabled or disabled.
AnnaBridge	171:3a7713b1edbc	72	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
AnnaBridge	171:3a7713b1edbc	73
AnnaBridge	171:3a7713b1edbc	74	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
AnnaBridge	171:3a7713b1edbc	75	disabled when the bus is idle.
AnnaBridge	171:3a7713b1edbc	76	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
AnnaBridge	171:3a7713b1edbc	77
AnnaBridge	171:3a7713b1edbc	78	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
AnnaBridge	171:3a7713b1edbc	79	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
AnnaBridge	171:3a7713b1edbc	80
AnnaBridge	171:3a7713b1edbc	81	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	82	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
AnnaBridge	171:3a7713b1edbc	83
AnnaBridge	171:3a7713b1edbc	84	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
AnnaBridge	171:3a7713b1edbc	85	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	86
AnnaBridge	171:3a7713b1edbc	87	}SDIO_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	88
AnnaBridge	171:3a7713b1edbc	89
AnnaBridge	171:3a7713b1edbc	90	/**
AnnaBridge	171:3a7713b1edbc	91	* @brief SDMMC Command Control structure
AnnaBridge	171:3a7713b1edbc	92	*/
AnnaBridge	171:3a7713b1edbc	93	typedef struct
AnnaBridge	171:3a7713b1edbc	94	{
AnnaBridge	171:3a7713b1edbc	95	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
AnnaBridge	171:3a7713b1edbc	96	to a card as part of a command message. If a command
AnnaBridge	171:3a7713b1edbc	97	contains an argument, it must be loaded into this register
AnnaBridge	171:3a7713b1edbc	98	before writing the command to the command register. */
AnnaBridge	171:3a7713b1edbc	99
AnnaBridge	171:3a7713b1edbc	100	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
AnnaBridge	171:3a7713b1edbc	101	Max_Data = 64 */
AnnaBridge	171:3a7713b1edbc	102
AnnaBridge	171:3a7713b1edbc	103	uint32_t Response; /*!< Specifies the SDMMC response type.
AnnaBridge	171:3a7713b1edbc	104	This parameter can be a value of @ref SDMMC_LL_Response_Type */
AnnaBridge	171:3a7713b1edbc	105
AnnaBridge	171:3a7713b1edbc	106	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
AnnaBridge	171:3a7713b1edbc	107	enabled or disabled.
AnnaBridge	171:3a7713b1edbc	108	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
AnnaBridge	171:3a7713b1edbc	109
AnnaBridge	171:3a7713b1edbc	110	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
AnnaBridge	171:3a7713b1edbc	111	is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	112	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
AnnaBridge	171:3a7713b1edbc	113	}SDIO_CmdInitTypeDef;
AnnaBridge	171:3a7713b1edbc	114
AnnaBridge	171:3a7713b1edbc	115
AnnaBridge	171:3a7713b1edbc	116	/**
AnnaBridge	171:3a7713b1edbc	117	* @brief SDMMC Data Control structure
AnnaBridge	171:3a7713b1edbc	118	*/
AnnaBridge	171:3a7713b1edbc	119	typedef struct
AnnaBridge	171:3a7713b1edbc	120	{
AnnaBridge	171:3a7713b1edbc	121	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
AnnaBridge	171:3a7713b1edbc	122
AnnaBridge	171:3a7713b1edbc	123	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
AnnaBridge	171:3a7713b1edbc	124
AnnaBridge	171:3a7713b1edbc	125	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
AnnaBridge	171:3a7713b1edbc	126	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
AnnaBridge	171:3a7713b1edbc	127
AnnaBridge	171:3a7713b1edbc	128	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
AnnaBridge	171:3a7713b1edbc	129	is a read or write.
AnnaBridge	171:3a7713b1edbc	130	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
AnnaBridge	171:3a7713b1edbc	131
AnnaBridge	171:3a7713b1edbc	132	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
AnnaBridge	171:3a7713b1edbc	133	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
AnnaBridge	171:3a7713b1edbc	134
AnnaBridge	171:3a7713b1edbc	135	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
AnnaBridge	171:3a7713b1edbc	136	is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	137	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
AnnaBridge	171:3a7713b1edbc	138	}SDIO_DataInitTypeDef;
AnnaBridge	171:3a7713b1edbc	139
AnnaBridge	171:3a7713b1edbc	140	/**
AnnaBridge	171:3a7713b1edbc	141	* @}
AnnaBridge	171:3a7713b1edbc	142	*/
AnnaBridge	171:3a7713b1edbc	143
AnnaBridge	171:3a7713b1edbc	144	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	145	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
AnnaBridge	171:3a7713b1edbc	146	* @{
AnnaBridge	171:3a7713b1edbc	147	*/
AnnaBridge	171:3a7713b1edbc	148	#define SDMMC_ERROR_NONE 0x00000000U /!< No error /
AnnaBridge	171:3a7713b1edbc	149	#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /!< Command response received (but CRC check failed) /
AnnaBridge	171:3a7713b1edbc	150	#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /!< Data block sent/received (CRC check failed) /
AnnaBridge	171:3a7713b1edbc	151	#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /!< Command response timeout /
AnnaBridge	171:3a7713b1edbc	152	#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /!< Data timeout /
AnnaBridge	171:3a7713b1edbc	153	#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /!< Transmit FIFO underrun /
AnnaBridge	171:3a7713b1edbc	154	#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /!< Receive FIFO overrun /
AnnaBridge	171:3a7713b1edbc	155	#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /!< Misaligned address /
AnnaBridge	171:3a7713b1edbc	156	#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
AnnaBridge	171:3a7713b1edbc	157	number of transferred bytes does not match the block length */
AnnaBridge	171:3a7713b1edbc	158	#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /!< An error in the sequence of erase command occurs /
AnnaBridge	171:3a7713b1edbc	159	#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /!< An invalid selection for erase groups /
AnnaBridge	171:3a7713b1edbc	160	#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /!< Attempt to program a write protect block /
AnnaBridge	171:3a7713b1edbc	161	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
AnnaBridge	171:3a7713b1edbc	162	command or if there was an attempt to access a locked card */
AnnaBridge	171:3a7713b1edbc	163	#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /!< CRC check of the previous command failed /
AnnaBridge	171:3a7713b1edbc	164	#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /!< Command is not legal for the card state /
AnnaBridge	171:3a7713b1edbc	165	#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /!< Card internal ECC was applied but failed to correct the data /
AnnaBridge	171:3a7713b1edbc	166	#define SDMMC_ERROR_CC_ERR 0x00008000U /!< Internal card controller error /
AnnaBridge	171:3a7713b1edbc	167	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /!< General or unknown error /
AnnaBridge	171:3a7713b1edbc	168	#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /!< The card could not sustain data reading in stream rmode /
AnnaBridge	171:3a7713b1edbc	169	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /!< The card could not sustain data programming in stream mode /
AnnaBridge	171:3a7713b1edbc	170	#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /!< CID/CSD overwrite error /
AnnaBridge	171:3a7713b1edbc	171	#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /!< Only partial address space was erased /
AnnaBridge	171:3a7713b1edbc	172	#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /!< Command has been executed without using internal ECC /
AnnaBridge	171:3a7713b1edbc	173	#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
AnnaBridge	171:3a7713b1edbc	174	of erase sequence command was received */
AnnaBridge	171:3a7713b1edbc	175	#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /!< Error in sequence of authentication /
AnnaBridge	171:3a7713b1edbc	176	#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /!< Error in case of invalid voltage range /
AnnaBridge	171:3a7713b1edbc	177	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /!< Error when addressed block is out of range /
AnnaBridge	171:3a7713b1edbc	178	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /!< Error when command request is not applicable /
AnnaBridge	171:3a7713b1edbc	179	#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /!< the used parameter is not valid /
AnnaBridge	171:3a7713b1edbc	180	#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /!< Error when feature is not insupported /
AnnaBridge	171:3a7713b1edbc	181	#define SDMMC_ERROR_BUSY 0x20000000U /!< Error when transfer process is busy /
AnnaBridge	171:3a7713b1edbc	182	#define SDMMC_ERROR_DMA 0x40000000U /!< Error while DMA transfer /
AnnaBridge	171:3a7713b1edbc	183	#define SDMMC_ERROR_TIMEOUT 0x80000000U /!< Timeout error /
AnnaBridge	171:3a7713b1edbc	184
AnnaBridge	171:3a7713b1edbc	185	/**
AnnaBridge	171:3a7713b1edbc	186	* @brief SDMMC Commands Index
AnnaBridge	171:3a7713b1edbc	187	*/
AnnaBridge	171:3a7713b1edbc	188	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /!< Resets the SD memory card. /
AnnaBridge	171:3a7713b1edbc	189	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /!< Sends host capacity support information and activates the card's initialization process. /
AnnaBridge	171:3a7713b1edbc	190	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
AnnaBridge	171:3a7713b1edbc	191	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /!< Asks the card to publish a new relative address (RCA). /
AnnaBridge	171:3a7713b1edbc	192	#define SDMMC_CMD_SET_DSR ((uint8_t)4) /!< Programs the DSR of all cards. /
AnnaBridge	171:3a7713b1edbc	193	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
AnnaBridge	171:3a7713b1edbc	194	operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	171:3a7713b1edbc	195	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
AnnaBridge	171:3a7713b1edbc	196	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /!< Selects the card by its own relative address and gets deselected by any other address /
AnnaBridge	171:3a7713b1edbc	197	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
AnnaBridge	171:3a7713b1edbc	198	and asks the card whether card supports voltage. */
AnnaBridge	171:3a7713b1edbc	199	#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
AnnaBridge	171:3a7713b1edbc	200	#define SDMMC_CMD_SEND_CID ((uint8_t)10) /!< Addressed card sends its card identification (CID) on the CMD line. /
AnnaBridge	171:3a7713b1edbc	201	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /!< SD card doesn't support it. /
AnnaBridge	171:3a7713b1edbc	202	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /!< Forces the card to stop transmission. /
AnnaBridge	171:3a7713b1edbc	203	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /!< Addressed card sends its status register. /
AnnaBridge	171:3a7713b1edbc	204	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /!< Reserved /
AnnaBridge	171:3a7713b1edbc	205	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /!< Sends an addressed card into the inactive state. /
AnnaBridge	171:3a7713b1edbc	206	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
AnnaBridge	171:3a7713b1edbc	207	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
AnnaBridge	171:3a7713b1edbc	208	for SDHS and SDXC. */
AnnaBridge	171:3a7713b1edbc	209	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	171:3a7713b1edbc	210	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	171:3a7713b1edbc	211	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
AnnaBridge	171:3a7713b1edbc	212	STOP_TRANSMISSION command. */
AnnaBridge	171:3a7713b1edbc	213	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
AnnaBridge	171:3a7713b1edbc	214	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /!< Speed class control command. /
AnnaBridge	171:3a7713b1edbc	215	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /!< Specify block count for CMD18 and CMD25. /
AnnaBridge	171:3a7713b1edbc	216	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	171:3a7713b1edbc	217	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	171:3a7713b1edbc	218	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
AnnaBridge	171:3a7713b1edbc	219	#define SDMMC_CMD_PROG_CID ((uint8_t)26) /!< Reserved for manufacturers. /
AnnaBridge	171:3a7713b1edbc	220	#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /!< Programming of the programmable bits of the CSD. /
AnnaBridge	171:3a7713b1edbc	221	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /!< Sets the write protection bit of the addressed group. /
AnnaBridge	171:3a7713b1edbc	222	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /!< Clears the write protection bit of the addressed group. /
AnnaBridge	171:3a7713b1edbc	223	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /!< Asks the card to send the status of the write protection bits. /
AnnaBridge	171:3a7713b1edbc	224	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /!< Sets the address of the first write block to be erased. (For SD card only). /
AnnaBridge	171:3a7713b1edbc	225	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /!< Sets the address of the last write block of the continuous range to be erased. /
AnnaBridge	171:3a7713b1edbc	226	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
AnnaBridge	171:3a7713b1edbc	227	system set by switch function command (CMD6). */
AnnaBridge	171:3a7713b1edbc	228	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
AnnaBridge	171:3a7713b1edbc	229	Reserved for each command system set by switch function command (CMD6). */
AnnaBridge	171:3a7713b1edbc	230	#define SDMMC_CMD_ERASE ((uint8_t)38) /!< Reserved for SD security applications. /
AnnaBridge	171:3a7713b1edbc	231	#define SDMMC_CMD_FAST_IO ((uint8_t)39) /!< SD card doesn't support it (Reserved). /
AnnaBridge	171:3a7713b1edbc	232	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /!< SD card doesn't support it (Reserved). /
AnnaBridge	171:3a7713b1edbc	233	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
AnnaBridge	171:3a7713b1edbc	234	the SET_BLOCK_LEN command. */
AnnaBridge	171:3a7713b1edbc	235	#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
AnnaBridge	171:3a7713b1edbc	236	than a standard command. */
AnnaBridge	171:3a7713b1edbc	237	#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
AnnaBridge	171:3a7713b1edbc	238	for general purpose/application specific commands. */
AnnaBridge	171:3a7713b1edbc	239	#define SDMMC_CMD_NO_CMD ((uint8_t)64) /!< No command /
AnnaBridge	171:3a7713b1edbc	240
AnnaBridge	171:3a7713b1edbc	241	/**
AnnaBridge	171:3a7713b1edbc	242	* @brief Following commands are SD Card Specific commands.
AnnaBridge	171:3a7713b1edbc	243	* SDMMC_APP_CMD should be sent before sending these commands.
AnnaBridge	171:3a7713b1edbc	244	*/
AnnaBridge	171:3a7713b1edbc	245	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
AnnaBridge	171:3a7713b1edbc	246	widths are given in SCR register. */
AnnaBridge	171:3a7713b1edbc	247	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /!< (ACMD13) Sends the SD status. /
AnnaBridge	171:3a7713b1edbc	248	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
AnnaBridge	171:3a7713b1edbc	249	32bit+CRC data block. */
AnnaBridge	171:3a7713b1edbc	250	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
AnnaBridge	171:3a7713b1edbc	251	send its operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	171:3a7713b1edbc	252	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
AnnaBridge	171:3a7713b1edbc	253	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /!< Reads the SD Configuration Register (SCR). /
AnnaBridge	171:3a7713b1edbc	254	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	171:3a7713b1edbc	255	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	171:3a7713b1edbc	256
AnnaBridge	171:3a7713b1edbc	257	/**
AnnaBridge	171:3a7713b1edbc	258	* @brief Following commands are SD Card Specific security commands.
AnnaBridge	171:3a7713b1edbc	259	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
AnnaBridge	171:3a7713b1edbc	260	*/
AnnaBridge	171:3a7713b1edbc	261	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
AnnaBridge	171:3a7713b1edbc	262	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
AnnaBridge	171:3a7713b1edbc	263	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
AnnaBridge	171:3a7713b1edbc	264	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
AnnaBridge	171:3a7713b1edbc	265	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
AnnaBridge	171:3a7713b1edbc	266	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
AnnaBridge	171:3a7713b1edbc	267	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
AnnaBridge	171:3a7713b1edbc	268	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
AnnaBridge	171:3a7713b1edbc	269	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
AnnaBridge	171:3a7713b1edbc	270	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
AnnaBridge	171:3a7713b1edbc	271	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
AnnaBridge	171:3a7713b1edbc	272
AnnaBridge	171:3a7713b1edbc	273	/**
AnnaBridge	171:3a7713b1edbc	274	* @brief Masks for errors Card Status R1 (OCR Register)
AnnaBridge	171:3a7713b1edbc	275	*/
AnnaBridge	171:3a7713b1edbc	276	#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
AnnaBridge	171:3a7713b1edbc	277	#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
AnnaBridge	171:3a7713b1edbc	278	#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
AnnaBridge	171:3a7713b1edbc	279	#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
AnnaBridge	171:3a7713b1edbc	280	#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
AnnaBridge	171:3a7713b1edbc	281	#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
AnnaBridge	171:3a7713b1edbc	282	#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
AnnaBridge	171:3a7713b1edbc	283	#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
AnnaBridge	171:3a7713b1edbc	284	#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
AnnaBridge	171:3a7713b1edbc	285	#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
AnnaBridge	171:3a7713b1edbc	286	#define SDMMC_OCR_CC_ERROR 0x00100000U
AnnaBridge	171:3a7713b1edbc	287	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
AnnaBridge	171:3a7713b1edbc	288	#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
AnnaBridge	171:3a7713b1edbc	289	#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
AnnaBridge	171:3a7713b1edbc	290	#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
AnnaBridge	171:3a7713b1edbc	291	#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
AnnaBridge	171:3a7713b1edbc	292	#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
AnnaBridge	171:3a7713b1edbc	293	#define SDMMC_OCR_ERASE_RESET 0x00002000U
AnnaBridge	171:3a7713b1edbc	294	#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
AnnaBridge	171:3a7713b1edbc	295	#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
AnnaBridge	171:3a7713b1edbc	296
AnnaBridge	171:3a7713b1edbc	297	/**
AnnaBridge	171:3a7713b1edbc	298	* @brief Masks for R6 Response
AnnaBridge	171:3a7713b1edbc	299	*/
AnnaBridge	171:3a7713b1edbc	300	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
AnnaBridge	171:3a7713b1edbc	301	#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
AnnaBridge	171:3a7713b1edbc	302	#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
AnnaBridge	171:3a7713b1edbc	303
AnnaBridge	171:3a7713b1edbc	304	#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
AnnaBridge	171:3a7713b1edbc	305	#define SDMMC_HIGH_CAPACITY 0x40000000U
AnnaBridge	171:3a7713b1edbc	306	#define SDMMC_STD_CAPACITY 0x00000000U
AnnaBridge	171:3a7713b1edbc	307	#define SDMMC_CHECK_PATTERN 0x000001AAU
AnnaBridge	171:3a7713b1edbc	308
AnnaBridge	171:3a7713b1edbc	309	#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
AnnaBridge	171:3a7713b1edbc	310
AnnaBridge	171:3a7713b1edbc	311	#define SDMMC_MAX_TRIAL 0x0000FFFFU
AnnaBridge	171:3a7713b1edbc	312
AnnaBridge	171:3a7713b1edbc	313	#define SDMMC_ALLZERO 0x00000000U
AnnaBridge	171:3a7713b1edbc	314
AnnaBridge	171:3a7713b1edbc	315	#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
AnnaBridge	171:3a7713b1edbc	316	#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
AnnaBridge	171:3a7713b1edbc	317	#define SDMMC_CARD_LOCKED 0x02000000U
AnnaBridge	171:3a7713b1edbc	318
AnnaBridge	171:3a7713b1edbc	319	#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
AnnaBridge	171:3a7713b1edbc	320
AnnaBridge	171:3a7713b1edbc	321	#define SDMMC_0TO7BITS 0x000000FFU
AnnaBridge	171:3a7713b1edbc	322	#define SDMMC_8TO15BITS 0x0000FF00U
AnnaBridge	171:3a7713b1edbc	323	#define SDMMC_16TO23BITS 0x00FF0000U
AnnaBridge	171:3a7713b1edbc	324	#define SDMMC_24TO31BITS 0xFF000000U
AnnaBridge	171:3a7713b1edbc	325	#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
AnnaBridge	171:3a7713b1edbc	326
AnnaBridge	171:3a7713b1edbc	327	#define SDMMC_HALFFIFO 0x00000008U
AnnaBridge	171:3a7713b1edbc	328	#define SDMMC_HALFFIFOBYTES 0x00000020U
AnnaBridge	171:3a7713b1edbc	329
AnnaBridge	171:3a7713b1edbc	330	/**
AnnaBridge	171:3a7713b1edbc	331	* @brief Command Class supported
AnnaBridge	171:3a7713b1edbc	332	*/
AnnaBridge	171:3a7713b1edbc	333	#define SDIO_CCCC_ERASE 0x00000020U
AnnaBridge	171:3a7713b1edbc	334
AnnaBridge	171:3a7713b1edbc	335	#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
AnnaBridge	171:3a7713b1edbc	336	#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
AnnaBridge	171:3a7713b1edbc	337
AnnaBridge	171:3a7713b1edbc	338
AnnaBridge	171:3a7713b1edbc	339	/** @defgroup SDIO_LL_Clock_Edge Clock Edge
AnnaBridge	171:3a7713b1edbc	340	* @{
AnnaBridge	171:3a7713b1edbc	341	*/
AnnaBridge	171:3a7713b1edbc	342	#define SDIO_CLOCK_EDGE_RISING 0x00000000U
AnnaBridge	171:3a7713b1edbc	343	#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
AnnaBridge	171:3a7713b1edbc	344
AnnaBridge	171:3a7713b1edbc	345	#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) \|\| \
AnnaBridge	171:3a7713b1edbc	346	((EDGE) == SDIO_CLOCK_EDGE_FALLING))
AnnaBridge	171:3a7713b1edbc	347	/**
AnnaBridge	171:3a7713b1edbc	348	* @}
AnnaBridge	171:3a7713b1edbc	349	*/
AnnaBridge	171:3a7713b1edbc	350
AnnaBridge	171:3a7713b1edbc	351	/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
AnnaBridge	171:3a7713b1edbc	352	* @{
AnnaBridge	171:3a7713b1edbc	353	*/
AnnaBridge	171:3a7713b1edbc	354	#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	355	#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
AnnaBridge	171:3a7713b1edbc	356
AnnaBridge	171:3a7713b1edbc	357	#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	358	((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
AnnaBridge	171:3a7713b1edbc	359	/**
AnnaBridge	171:3a7713b1edbc	360	* @}
AnnaBridge	171:3a7713b1edbc	361	*/
AnnaBridge	171:3a7713b1edbc	362
AnnaBridge	171:3a7713b1edbc	363	/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
AnnaBridge	171:3a7713b1edbc	364	* @{
AnnaBridge	171:3a7713b1edbc	365	*/
AnnaBridge	171:3a7713b1edbc	366	#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	367	#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
AnnaBridge	171:3a7713b1edbc	368
AnnaBridge	171:3a7713b1edbc	369	#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	370	((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
AnnaBridge	171:3a7713b1edbc	371	/**
AnnaBridge	171:3a7713b1edbc	372	* @}
AnnaBridge	171:3a7713b1edbc	373	*/
AnnaBridge	171:3a7713b1edbc	374
AnnaBridge	171:3a7713b1edbc	375	/** @defgroup SDIO_LL_Bus_Wide Bus Width
AnnaBridge	171:3a7713b1edbc	376	* @{
AnnaBridge	171:3a7713b1edbc	377	*/
AnnaBridge	171:3a7713b1edbc	378	#define SDIO_BUS_WIDE_1B 0x00000000U
AnnaBridge	171:3a7713b1edbc	379	#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
AnnaBridge	171:3a7713b1edbc	380	#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
AnnaBridge	171:3a7713b1edbc	381
AnnaBridge	171:3a7713b1edbc	382	#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) \|\| \
AnnaBridge	171:3a7713b1edbc	383	((WIDE) == SDIO_BUS_WIDE_4B) \|\| \
AnnaBridge	171:3a7713b1edbc	384	((WIDE) == SDIO_BUS_WIDE_8B))
AnnaBridge	171:3a7713b1edbc	385	/**
AnnaBridge	171:3a7713b1edbc	386	* @}
AnnaBridge	171:3a7713b1edbc	387	*/
AnnaBridge	171:3a7713b1edbc	388
AnnaBridge	171:3a7713b1edbc	389	/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
AnnaBridge	171:3a7713b1edbc	390	* @{
AnnaBridge	171:3a7713b1edbc	391	*/
AnnaBridge	171:3a7713b1edbc	392	#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	393	#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
AnnaBridge	171:3a7713b1edbc	394
AnnaBridge	171:3a7713b1edbc	395	#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	396	((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
AnnaBridge	171:3a7713b1edbc	397	/**
AnnaBridge	171:3a7713b1edbc	398	* @}
AnnaBridge	171:3a7713b1edbc	399	*/
AnnaBridge	171:3a7713b1edbc	400
AnnaBridge	171:3a7713b1edbc	401	/** @defgroup SDIO_LL_Clock_Division Clock Division
AnnaBridge	171:3a7713b1edbc	402	* @{
AnnaBridge	171:3a7713b1edbc	403	*/
AnnaBridge	171:3a7713b1edbc	404	#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
AnnaBridge	171:3a7713b1edbc	405	/**
AnnaBridge	171:3a7713b1edbc	406	* @}
AnnaBridge	171:3a7713b1edbc	407	*/
AnnaBridge	171:3a7713b1edbc	408
AnnaBridge	171:3a7713b1edbc	409	/** @defgroup SDIO_LL_Command_Index Command Index
AnnaBridge	171:3a7713b1edbc	410	* @{
AnnaBridge	171:3a7713b1edbc	411	*/
AnnaBridge	171:3a7713b1edbc	412	#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
AnnaBridge	171:3a7713b1edbc	413	/**
AnnaBridge	171:3a7713b1edbc	414	* @}
AnnaBridge	171:3a7713b1edbc	415	*/
AnnaBridge	171:3a7713b1edbc	416
AnnaBridge	171:3a7713b1edbc	417	/** @defgroup SDIO_LL_Response_Type Response Type
AnnaBridge	171:3a7713b1edbc	418	* @{
AnnaBridge	171:3a7713b1edbc	419	*/
AnnaBridge	171:3a7713b1edbc	420	#define SDIO_RESPONSE_NO 0x00000000U
AnnaBridge	171:3a7713b1edbc	421	#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
AnnaBridge	171:3a7713b1edbc	422	#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
AnnaBridge	171:3a7713b1edbc	423
AnnaBridge	171:3a7713b1edbc	424	#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) \|\| \
AnnaBridge	171:3a7713b1edbc	425	((RESPONSE) == SDIO_RESPONSE_SHORT) \|\| \
AnnaBridge	171:3a7713b1edbc	426	((RESPONSE) == SDIO_RESPONSE_LONG))
AnnaBridge	171:3a7713b1edbc	427	/**
AnnaBridge	171:3a7713b1edbc	428	* @}
AnnaBridge	171:3a7713b1edbc	429	*/
AnnaBridge	171:3a7713b1edbc	430
AnnaBridge	171:3a7713b1edbc	431	/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
AnnaBridge	171:3a7713b1edbc	432	* @{
AnnaBridge	171:3a7713b1edbc	433	*/
AnnaBridge	171:3a7713b1edbc	434	#define SDIO_WAIT_NO 0x00000000U
AnnaBridge	171:3a7713b1edbc	435	#define SDIO_WAIT_IT SDIO_CMD_WAITINT
AnnaBridge	171:3a7713b1edbc	436	#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
AnnaBridge	171:3a7713b1edbc	437
AnnaBridge	171:3a7713b1edbc	438	#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) \|\| \
AnnaBridge	171:3a7713b1edbc	439	((WAIT) == SDIO_WAIT_IT) \|\| \
AnnaBridge	171:3a7713b1edbc	440	((WAIT) == SDIO_WAIT_PEND))
AnnaBridge	171:3a7713b1edbc	441	/**
AnnaBridge	171:3a7713b1edbc	442	* @}
AnnaBridge	171:3a7713b1edbc	443	*/
AnnaBridge	171:3a7713b1edbc	444
AnnaBridge	171:3a7713b1edbc	445	/** @defgroup SDIO_LL_CPSM_State CPSM State
AnnaBridge	171:3a7713b1edbc	446	* @{
AnnaBridge	171:3a7713b1edbc	447	*/
AnnaBridge	171:3a7713b1edbc	448	#define SDIO_CPSM_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	449	#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
AnnaBridge	171:3a7713b1edbc	450
AnnaBridge	171:3a7713b1edbc	451	#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	452	((CPSM) == SDIO_CPSM_ENABLE))
AnnaBridge	171:3a7713b1edbc	453	/**
AnnaBridge	171:3a7713b1edbc	454	* @}
AnnaBridge	171:3a7713b1edbc	455	*/
AnnaBridge	171:3a7713b1edbc	456
AnnaBridge	171:3a7713b1edbc	457	/** @defgroup SDIO_LL_Response_Registers Response Register
AnnaBridge	171:3a7713b1edbc	458	* @{
AnnaBridge	171:3a7713b1edbc	459	*/
AnnaBridge	171:3a7713b1edbc	460	#define SDIO_RESP1 0x00000000U
AnnaBridge	171:3a7713b1edbc	461	#define SDIO_RESP2 0x00000004U
AnnaBridge	171:3a7713b1edbc	462	#define SDIO_RESP3 0x00000008U
AnnaBridge	171:3a7713b1edbc	463	#define SDIO_RESP4 0x0000000CU
AnnaBridge	171:3a7713b1edbc	464
AnnaBridge	171:3a7713b1edbc	465	#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) \|\| \
AnnaBridge	171:3a7713b1edbc	466	((RESP) == SDIO_RESP2) \|\| \
AnnaBridge	171:3a7713b1edbc	467	((RESP) == SDIO_RESP3) \|\| \
AnnaBridge	171:3a7713b1edbc	468	((RESP) == SDIO_RESP4))
AnnaBridge	171:3a7713b1edbc	469	/**
AnnaBridge	171:3a7713b1edbc	470	* @}
AnnaBridge	171:3a7713b1edbc	471	*/
AnnaBridge	171:3a7713b1edbc	472
AnnaBridge	171:3a7713b1edbc	473	/** @defgroup SDIO_LL_Data_Length Data Lenght
AnnaBridge	171:3a7713b1edbc	474	* @{
AnnaBridge	171:3a7713b1edbc	475	*/
AnnaBridge	171:3a7713b1edbc	476	#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
AnnaBridge	171:3a7713b1edbc	477	/**
AnnaBridge	171:3a7713b1edbc	478	* @}
AnnaBridge	171:3a7713b1edbc	479	*/
AnnaBridge	171:3a7713b1edbc	480
AnnaBridge	171:3a7713b1edbc	481	/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
AnnaBridge	171:3a7713b1edbc	482	* @{
AnnaBridge	171:3a7713b1edbc	483	*/
AnnaBridge	171:3a7713b1edbc	484	#define SDIO_DATABLOCK_SIZE_1B 0x00000000U
AnnaBridge	171:3a7713b1edbc	485	#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
AnnaBridge	171:3a7713b1edbc	486	#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
AnnaBridge	171:3a7713b1edbc	487	#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1)
AnnaBridge	171:3a7713b1edbc	488	#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
AnnaBridge	171:3a7713b1edbc	489	#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2)
AnnaBridge	171:3a7713b1edbc	490	#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
AnnaBridge	171:3a7713b1edbc	491	#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
AnnaBridge	171:3a7713b1edbc	492	#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
AnnaBridge	171:3a7713b1edbc	493	#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	494	#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	495	#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	496	#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	497	#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	498	#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	171:3a7713b1edbc	499
AnnaBridge	171:3a7713b1edbc	500	#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) \|\| \
AnnaBridge	171:3a7713b1edbc	501	((SIZE) == SDIO_DATABLOCK_SIZE_2B) \|\| \
AnnaBridge	171:3a7713b1edbc	502	((SIZE) == SDIO_DATABLOCK_SIZE_4B) \|\| \
AnnaBridge	171:3a7713b1edbc	503	((SIZE) == SDIO_DATABLOCK_SIZE_8B) \|\| \
AnnaBridge	171:3a7713b1edbc	504	((SIZE) == SDIO_DATABLOCK_SIZE_16B) \|\| \
AnnaBridge	171:3a7713b1edbc	505	((SIZE) == SDIO_DATABLOCK_SIZE_32B) \|\| \
AnnaBridge	171:3a7713b1edbc	506	((SIZE) == SDIO_DATABLOCK_SIZE_64B) \|\| \
AnnaBridge	171:3a7713b1edbc	507	((SIZE) == SDIO_DATABLOCK_SIZE_128B) \|\| \
AnnaBridge	171:3a7713b1edbc	508	((SIZE) == SDIO_DATABLOCK_SIZE_256B) \|\| \
AnnaBridge	171:3a7713b1edbc	509	((SIZE) == SDIO_DATABLOCK_SIZE_512B) \|\| \
AnnaBridge	171:3a7713b1edbc	510	((SIZE) == SDIO_DATABLOCK_SIZE_1024B) \|\| \
AnnaBridge	171:3a7713b1edbc	511	((SIZE) == SDIO_DATABLOCK_SIZE_2048B) \|\| \
AnnaBridge	171:3a7713b1edbc	512	((SIZE) == SDIO_DATABLOCK_SIZE_4096B) \|\| \
AnnaBridge	171:3a7713b1edbc	513	((SIZE) == SDIO_DATABLOCK_SIZE_8192B) \|\| \
AnnaBridge	171:3a7713b1edbc	514	((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
AnnaBridge	171:3a7713b1edbc	515	/**
AnnaBridge	171:3a7713b1edbc	516	* @}
AnnaBridge	171:3a7713b1edbc	517	*/
AnnaBridge	171:3a7713b1edbc	518
AnnaBridge	171:3a7713b1edbc	519	/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
AnnaBridge	171:3a7713b1edbc	520	* @{
AnnaBridge	171:3a7713b1edbc	521	*/
AnnaBridge	171:3a7713b1edbc	522	#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
AnnaBridge	171:3a7713b1edbc	523	#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
AnnaBridge	171:3a7713b1edbc	524
AnnaBridge	171:3a7713b1edbc	525	#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) \|\| \
AnnaBridge	171:3a7713b1edbc	526	((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
AnnaBridge	171:3a7713b1edbc	527	/**
AnnaBridge	171:3a7713b1edbc	528	* @}
AnnaBridge	171:3a7713b1edbc	529	*/
AnnaBridge	171:3a7713b1edbc	530
AnnaBridge	171:3a7713b1edbc	531	/** @defgroup SDIO_LL_Transfer_Type Transfer Type
AnnaBridge	171:3a7713b1edbc	532	* @{
AnnaBridge	171:3a7713b1edbc	533	*/
AnnaBridge	171:3a7713b1edbc	534	#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
AnnaBridge	171:3a7713b1edbc	535	#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
AnnaBridge	171:3a7713b1edbc	536
AnnaBridge	171:3a7713b1edbc	537	#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) \|\| \
AnnaBridge	171:3a7713b1edbc	538	((MODE) == SDIO_TRANSFER_MODE_STREAM))
AnnaBridge	171:3a7713b1edbc	539	/**
AnnaBridge	171:3a7713b1edbc	540	* @}
AnnaBridge	171:3a7713b1edbc	541	*/
AnnaBridge	171:3a7713b1edbc	542
AnnaBridge	171:3a7713b1edbc	543	/** @defgroup SDIO_LL_DPSM_State DPSM State
AnnaBridge	171:3a7713b1edbc	544	* @{
AnnaBridge	171:3a7713b1edbc	545	*/
AnnaBridge	171:3a7713b1edbc	546	#define SDIO_DPSM_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	547	#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
AnnaBridge	171:3a7713b1edbc	548
AnnaBridge	171:3a7713b1edbc	549	#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) \|\|\
AnnaBridge	171:3a7713b1edbc	550	((DPSM) == SDIO_DPSM_ENABLE))
AnnaBridge	171:3a7713b1edbc	551	/**
AnnaBridge	171:3a7713b1edbc	552	* @}
AnnaBridge	171:3a7713b1edbc	553	*/
AnnaBridge	171:3a7713b1edbc	554
AnnaBridge	171:3a7713b1edbc	555	/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
AnnaBridge	171:3a7713b1edbc	556	* @{
AnnaBridge	171:3a7713b1edbc	557	*/
AnnaBridge	171:3a7713b1edbc	558	#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
AnnaBridge	171:3a7713b1edbc	559	#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
AnnaBridge	171:3a7713b1edbc	560
AnnaBridge	171:3a7713b1edbc	561	#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) \|\| \
AnnaBridge	171:3a7713b1edbc	562	((MODE) == SDIO_READ_WAIT_MODE_DATA2))
AnnaBridge	171:3a7713b1edbc	563	/**
AnnaBridge	171:3a7713b1edbc	564	* @}
AnnaBridge	171:3a7713b1edbc	565	*/
AnnaBridge	171:3a7713b1edbc	566
AnnaBridge	171:3a7713b1edbc	567	/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
AnnaBridge	171:3a7713b1edbc	568	* @{
AnnaBridge	171:3a7713b1edbc	569	*/
AnnaBridge	171:3a7713b1edbc	570	#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
AnnaBridge	171:3a7713b1edbc	571	#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
AnnaBridge	171:3a7713b1edbc	572	#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
AnnaBridge	171:3a7713b1edbc	573	#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
AnnaBridge	171:3a7713b1edbc	574	#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
AnnaBridge	171:3a7713b1edbc	575	#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
AnnaBridge	171:3a7713b1edbc	576	#define SDIO_IT_CMDREND SDIO_STA_CMDREND
AnnaBridge	171:3a7713b1edbc	577	#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
AnnaBridge	171:3a7713b1edbc	578	#define SDIO_IT_DATAEND SDIO_STA_DATAEND
AnnaBridge	171:3a7713b1edbc	579	#define SDIO_IT_STBITERR SDIO_STA_STBITERR
AnnaBridge	171:3a7713b1edbc	580	#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
AnnaBridge	171:3a7713b1edbc	581	#define SDIO_IT_CMDACT SDIO_STA_CMDACT
AnnaBridge	171:3a7713b1edbc	582	#define SDIO_IT_TXACT SDIO_STA_TXACT
AnnaBridge	171:3a7713b1edbc	583	#define SDIO_IT_RXACT SDIO_STA_RXACT
AnnaBridge	171:3a7713b1edbc	584	#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
AnnaBridge	171:3a7713b1edbc	585	#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
AnnaBridge	171:3a7713b1edbc	586	#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
AnnaBridge	171:3a7713b1edbc	587	#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
AnnaBridge	171:3a7713b1edbc	588	#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
AnnaBridge	171:3a7713b1edbc	589	#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
AnnaBridge	171:3a7713b1edbc	590	#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
AnnaBridge	171:3a7713b1edbc	591	#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
AnnaBridge	171:3a7713b1edbc	592	#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
AnnaBridge	171:3a7713b1edbc	593	#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
AnnaBridge	171:3a7713b1edbc	594	/**
AnnaBridge	171:3a7713b1edbc	595	* @}
AnnaBridge	171:3a7713b1edbc	596	*/
AnnaBridge	171:3a7713b1edbc	597
AnnaBridge	171:3a7713b1edbc	598	/** @defgroup SDIO_LL_Flags Flags
AnnaBridge	171:3a7713b1edbc	599	* @{
AnnaBridge	171:3a7713b1edbc	600	*/
AnnaBridge	171:3a7713b1edbc	601	#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
AnnaBridge	171:3a7713b1edbc	602	#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
AnnaBridge	171:3a7713b1edbc	603	#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
AnnaBridge	171:3a7713b1edbc	604	#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
AnnaBridge	171:3a7713b1edbc	605	#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
AnnaBridge	171:3a7713b1edbc	606	#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
AnnaBridge	171:3a7713b1edbc	607	#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
AnnaBridge	171:3a7713b1edbc	608	#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
AnnaBridge	171:3a7713b1edbc	609	#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
AnnaBridge	171:3a7713b1edbc	610	#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
AnnaBridge	171:3a7713b1edbc	611	#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
AnnaBridge	171:3a7713b1edbc	612	#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
AnnaBridge	171:3a7713b1edbc	613	#define SDIO_FLAG_TXACT SDIO_STA_TXACT
AnnaBridge	171:3a7713b1edbc	614	#define SDIO_FLAG_RXACT SDIO_STA_RXACT
AnnaBridge	171:3a7713b1edbc	615	#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
AnnaBridge	171:3a7713b1edbc	616	#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
AnnaBridge	171:3a7713b1edbc	617	#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
AnnaBridge	171:3a7713b1edbc	618	#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
AnnaBridge	171:3a7713b1edbc	619	#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
AnnaBridge	171:3a7713b1edbc	620	#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
AnnaBridge	171:3a7713b1edbc	621	#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
AnnaBridge	171:3a7713b1edbc	622	#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
AnnaBridge	171:3a7713b1edbc	623	#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
AnnaBridge	171:3a7713b1edbc	624	#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
AnnaBridge	171:3a7713b1edbc	625	#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL \| SDIO_FLAG_DCRCFAIL \| SDIO_FLAG_CTIMEOUT \|\
AnnaBridge	171:3a7713b1edbc	626	SDIO_FLAG_DTIMEOUT \| SDIO_FLAG_TXUNDERR \| SDIO_FLAG_RXOVERR \|\
AnnaBridge	171:3a7713b1edbc	627	SDIO_FLAG_CMDREND \| SDIO_FLAG_CMDSENT \| SDIO_FLAG_DATAEND \|\
AnnaBridge	171:3a7713b1edbc	628	SDIO_FLAG_DBCKEND))
AnnaBridge	171:3a7713b1edbc	629	/**
AnnaBridge	171:3a7713b1edbc	630	* @}
AnnaBridge	171:3a7713b1edbc	631	*/
AnnaBridge	171:3a7713b1edbc	632
AnnaBridge	171:3a7713b1edbc	633	/**
AnnaBridge	171:3a7713b1edbc	634	* @}
AnnaBridge	171:3a7713b1edbc	635	*/
AnnaBridge	171:3a7713b1edbc	636
AnnaBridge	171:3a7713b1edbc	637	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	638	/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
AnnaBridge	171:3a7713b1edbc	639	* @{
AnnaBridge	171:3a7713b1edbc	640	*/
AnnaBridge	171:3a7713b1edbc	641
AnnaBridge	171:3a7713b1edbc	642	/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
AnnaBridge	171:3a7713b1edbc	643	* @{
AnnaBridge	171:3a7713b1edbc	644	*/
AnnaBridge	171:3a7713b1edbc	645	/* ------------ SDIO registers bit address in the alias region -------------- */
AnnaBridge	171:3a7713b1edbc	646	#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
AnnaBridge	171:3a7713b1edbc	647
AnnaBridge	171:3a7713b1edbc	648	/* --- CLKCR Register ---*/
AnnaBridge	171:3a7713b1edbc	649	/* Alias word address of CLKEN bit */
AnnaBridge	171:3a7713b1edbc	650	#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
AnnaBridge	171:3a7713b1edbc	651	#define CLKEN_BITNUMBER 0x08U
AnnaBridge	171:3a7713b1edbc	652	#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	653
AnnaBridge	171:3a7713b1edbc	654	/* --- CMD Register ---*/
AnnaBridge	171:3a7713b1edbc	655	/* Alias word address of SDIOSUSPEND bit */
AnnaBridge	171:3a7713b1edbc	656	#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
AnnaBridge	171:3a7713b1edbc	657	#define SDIOSUSPEND_BITNUMBER 0x0BU
AnnaBridge	171:3a7713b1edbc	658	#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	659
AnnaBridge	171:3a7713b1edbc	660	/* Alias word address of ENCMDCOMPL bit */
AnnaBridge	171:3a7713b1edbc	661	#define ENCMDCOMPL_BITNUMBER 0x0CU
AnnaBridge	171:3a7713b1edbc	662	#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	663
AnnaBridge	171:3a7713b1edbc	664	/* Alias word address of NIEN bit */
AnnaBridge	171:3a7713b1edbc	665	#define NIEN_BITNUMBER 0x0DU
AnnaBridge	171:3a7713b1edbc	666	#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	667
AnnaBridge	171:3a7713b1edbc	668	/* Alias word address of ATACMD bit */
AnnaBridge	171:3a7713b1edbc	669	#define ATACMD_BITNUMBER 0x0EU
AnnaBridge	171:3a7713b1edbc	670	#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	671
AnnaBridge	171:3a7713b1edbc	672	/* --- DCTRL Register ---*/
AnnaBridge	171:3a7713b1edbc	673	/* Alias word address of DMAEN bit */
AnnaBridge	171:3a7713b1edbc	674	#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
AnnaBridge	171:3a7713b1edbc	675	#define DMAEN_BITNUMBER 0x03U
AnnaBridge	171:3a7713b1edbc	676	#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	677
AnnaBridge	171:3a7713b1edbc	678	/* Alias word address of RWSTART bit */
AnnaBridge	171:3a7713b1edbc	679	#define RWSTART_BITNUMBER 0x08U
AnnaBridge	171:3a7713b1edbc	680	#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	681
AnnaBridge	171:3a7713b1edbc	682	/* Alias word address of RWSTOP bit */
AnnaBridge	171:3a7713b1edbc	683	#define RWSTOP_BITNUMBER 0x09U
AnnaBridge	171:3a7713b1edbc	684	#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	685
AnnaBridge	171:3a7713b1edbc	686	/* Alias word address of RWMOD bit */
AnnaBridge	171:3a7713b1edbc	687	#define RWMOD_BITNUMBER 0x0AU
AnnaBridge	171:3a7713b1edbc	688	#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	689
AnnaBridge	171:3a7713b1edbc	690	/* Alias word address of SDIOEN bit */
AnnaBridge	171:3a7713b1edbc	691	#define SDIOEN_BITNUMBER 0x0BU
AnnaBridge	171:3a7713b1edbc	692	#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	693	/**
AnnaBridge	171:3a7713b1edbc	694	* @}
AnnaBridge	171:3a7713b1edbc	695	*/
AnnaBridge	171:3a7713b1edbc	696
AnnaBridge	171:3a7713b1edbc	697	/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
AnnaBridge	171:3a7713b1edbc	698	* @brief SDIO_LL registers bit address in the alias region
AnnaBridge	171:3a7713b1edbc	699	* @{
AnnaBridge	171:3a7713b1edbc	700	*/
AnnaBridge	171:3a7713b1edbc	701	/* ---------------------- SDIO registers bit mask --------------------------- */
AnnaBridge	171:3a7713b1edbc	702	/* --- CLKCR Register ---*/
AnnaBridge	171:3a7713b1edbc	703	/* CLKCR register clear mask */
AnnaBridge	171:3a7713b1edbc	704	#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV \| SDIO_CLKCR_PWRSAV \|\
AnnaBridge	171:3a7713b1edbc	705	SDIO_CLKCR_BYPASS \| SDIO_CLKCR_WIDBUS \|\
AnnaBridge	171:3a7713b1edbc	706	SDIO_CLKCR_NEGEDGE \| SDIO_CLKCR_HWFC_EN))
AnnaBridge	171:3a7713b1edbc	707
AnnaBridge	171:3a7713b1edbc	708	/* --- DCTRL Register ---*/
AnnaBridge	171:3a7713b1edbc	709	/* SDIO DCTRL Clear Mask */
AnnaBridge	171:3a7713b1edbc	710	#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN \| SDIO_DCTRL_DTDIR \|\
AnnaBridge	171:3a7713b1edbc	711	SDIO_DCTRL_DTMODE \| SDIO_DCTRL_DBLOCKSIZE))
AnnaBridge	171:3a7713b1edbc	712
AnnaBridge	171:3a7713b1edbc	713	/* --- CMD Register ---*/
AnnaBridge	171:3a7713b1edbc	714	/* CMD Register clear mask */
AnnaBridge	171:3a7713b1edbc	715	#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX \| SDIO_CMD_WAITRESP \|\
AnnaBridge	171:3a7713b1edbc	716	SDIO_CMD_WAITINT \| SDIO_CMD_WAITPEND \|\
AnnaBridge	171:3a7713b1edbc	717	SDIO_CMD_CPSMEN \| SDIO_CMD_SDIOSUSPEND))
AnnaBridge	171:3a7713b1edbc	718
AnnaBridge	171:3a7713b1edbc	719	/* SDIO Initialization Frequency (400KHz max) */
AnnaBridge	171:3a7713b1edbc	720	#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
AnnaBridge	171:3a7713b1edbc	721
AnnaBridge	171:3a7713b1edbc	722	/* SDIO Data Transfer Frequency (25MHz max) */
AnnaBridge	171:3a7713b1edbc	723	#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
AnnaBridge	171:3a7713b1edbc	724
AnnaBridge	171:3a7713b1edbc	725	/**
AnnaBridge	171:3a7713b1edbc	726	* @}
AnnaBridge	171:3a7713b1edbc	727	*/
AnnaBridge	171:3a7713b1edbc	728
AnnaBridge	171:3a7713b1edbc	729	/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
AnnaBridge	171:3a7713b1edbc	730	* @brief macros to handle interrupts and specific clock configurations
AnnaBridge	171:3a7713b1edbc	731	* @{
AnnaBridge	171:3a7713b1edbc	732	*/
AnnaBridge	171:3a7713b1edbc	733
AnnaBridge	171:3a7713b1edbc	734	/**
AnnaBridge	171:3a7713b1edbc	735	* @brief Enable the SDIO device.
AnnaBridge	171:3a7713b1edbc	736	* @param __INSTANCE__: SDIO Instance
AnnaBridge	171:3a7713b1edbc	737	* @retval None
AnnaBridge	171:3a7713b1edbc	738	*/
AnnaBridge	171:3a7713b1edbc	739	#define __SDIO_ENABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	740
AnnaBridge	171:3a7713b1edbc	741	/**
AnnaBridge	171:3a7713b1edbc	742	* @brief Disable the SDIO device.
AnnaBridge	171:3a7713b1edbc	743	* @param __INSTANCE__: SDIO Instance
AnnaBridge	171:3a7713b1edbc	744	* @retval None
AnnaBridge	171:3a7713b1edbc	745	*/
AnnaBridge	171:3a7713b1edbc	746	#define __SDIO_DISABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	747
AnnaBridge	171:3a7713b1edbc	748	/**
AnnaBridge	171:3a7713b1edbc	749	* @brief Enable the SDIO DMA transfer.
AnnaBridge	171:3a7713b1edbc	750	* @param __INSTANCE__: SDIO Instance
AnnaBridge	171:3a7713b1edbc	751	* @retval None
AnnaBridge	171:3a7713b1edbc	752	*/
AnnaBridge	171:3a7713b1edbc	753	#define __SDIO_DMA_ENABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	754	/**
AnnaBridge	171:3a7713b1edbc	755	* @brief Disable the SDIO DMA transfer.
AnnaBridge	171:3a7713b1edbc	756	* @param __INSTANCE__: SDIO Instance
AnnaBridge	171:3a7713b1edbc	757	* @retval None
AnnaBridge	171:3a7713b1edbc	758	*/
AnnaBridge	171:3a7713b1edbc	759	#define __SDIO_DMA_DISABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	760
AnnaBridge	171:3a7713b1edbc	761	/**
AnnaBridge	171:3a7713b1edbc	762	* @brief Enable the SDIO device interrupt.
AnnaBridge	171:3a7713b1edbc	763	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	764	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
AnnaBridge	171:3a7713b1edbc	765	* This parameter can be one or a combination of the following values:
AnnaBridge	171:3a7713b1edbc	766	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	767	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	768	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	171:3a7713b1edbc	769	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	171:3a7713b1edbc	770	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	171:3a7713b1edbc	771	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	171:3a7713b1edbc	772	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	773	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	171:3a7713b1edbc	774	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	171:3a7713b1edbc	775	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	776	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	171:3a7713b1edbc	777	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	171:3a7713b1edbc	778	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
AnnaBridge	171:3a7713b1edbc	779	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	171:3a7713b1edbc	780	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	171:3a7713b1edbc	781	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	782	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	783	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	784	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	785	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	171:3a7713b1edbc	786	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	171:3a7713b1edbc	787	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	171:3a7713b1edbc	788	* @retval None
AnnaBridge	171:3a7713b1edbc	789	*/
AnnaBridge	171:3a7713b1edbc	790	#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	791
AnnaBridge	171:3a7713b1edbc	792	/**
AnnaBridge	171:3a7713b1edbc	793	* @brief Disable the SDIO device interrupt.
AnnaBridge	171:3a7713b1edbc	794	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	795	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
AnnaBridge	171:3a7713b1edbc	796	* This parameter can be one or a combination of the following values:
AnnaBridge	171:3a7713b1edbc	797	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	798	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	799	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	171:3a7713b1edbc	800	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	171:3a7713b1edbc	801	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	171:3a7713b1edbc	802	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	171:3a7713b1edbc	803	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	804	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	171:3a7713b1edbc	805	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	171:3a7713b1edbc	806	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	807	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	171:3a7713b1edbc	808	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	171:3a7713b1edbc	809	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
AnnaBridge	171:3a7713b1edbc	810	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	171:3a7713b1edbc	811	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	171:3a7713b1edbc	812	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	813	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	814	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	815	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	816	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	171:3a7713b1edbc	817	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	171:3a7713b1edbc	818	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	171:3a7713b1edbc	819	* @retval None
AnnaBridge	171:3a7713b1edbc	820	*/
AnnaBridge	171:3a7713b1edbc	821	#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	822
AnnaBridge	171:3a7713b1edbc	823	/**
AnnaBridge	171:3a7713b1edbc	824	* @brief Checks whether the specified SDIO flag is set or not.
AnnaBridge	171:3a7713b1edbc	825	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	826	* @param __FLAG__: specifies the flag to check.
AnnaBridge	171:3a7713b1edbc	827	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	828	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	171:3a7713b1edbc	829	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	171:3a7713b1edbc	830	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	171:3a7713b1edbc	831	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
AnnaBridge	171:3a7713b1edbc	832	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	171:3a7713b1edbc	833	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	171:3a7713b1edbc	834	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	171:3a7713b1edbc	835	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	171:3a7713b1edbc	836	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	171:3a7713b1edbc	837	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	171:3a7713b1edbc	838	* @arg SDIO_FLAG_CMDACT: Command transfer in progress
AnnaBridge	171:3a7713b1edbc	839	* @arg SDIO_FLAG_TXACT: Data transmit in progress
AnnaBridge	171:3a7713b1edbc	840	* @arg SDIO_FLAG_RXACT: Data receive in progress
AnnaBridge	171:3a7713b1edbc	841	* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
AnnaBridge	171:3a7713b1edbc	842	* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
AnnaBridge	171:3a7713b1edbc	843	* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
AnnaBridge	171:3a7713b1edbc	844	* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
AnnaBridge	171:3a7713b1edbc	845	* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
AnnaBridge	171:3a7713b1edbc	846	* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
AnnaBridge	171:3a7713b1edbc	847	* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
AnnaBridge	171:3a7713b1edbc	848	* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
AnnaBridge	171:3a7713b1edbc	849	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	171:3a7713b1edbc	850	* @retval The new state of SDIO_FLAG (SET or RESET).
AnnaBridge	171:3a7713b1edbc	851	*/
AnnaBridge	171:3a7713b1edbc	852	#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
AnnaBridge	171:3a7713b1edbc	853
AnnaBridge	171:3a7713b1edbc	854
AnnaBridge	171:3a7713b1edbc	855	/**
AnnaBridge	171:3a7713b1edbc	856	* @brief Clears the SDIO pending flags.
AnnaBridge	171:3a7713b1edbc	857	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	858	* @param __FLAG__: specifies the flag to clear.
AnnaBridge	171:3a7713b1edbc	859	* This parameter can be one or a combination of the following values:
AnnaBridge	171:3a7713b1edbc	860	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	171:3a7713b1edbc	861	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	171:3a7713b1edbc	862	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	171:3a7713b1edbc	863	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
AnnaBridge	171:3a7713b1edbc	864	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	171:3a7713b1edbc	865	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	171:3a7713b1edbc	866	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	171:3a7713b1edbc	867	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	171:3a7713b1edbc	868	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	171:3a7713b1edbc	869	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	171:3a7713b1edbc	870	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	171:3a7713b1edbc	871	* @retval None
AnnaBridge	171:3a7713b1edbc	872	*/
AnnaBridge	171:3a7713b1edbc	873	#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
AnnaBridge	171:3a7713b1edbc	874
AnnaBridge	171:3a7713b1edbc	875	/**
AnnaBridge	171:3a7713b1edbc	876	* @brief Checks whether the specified SDIO interrupt has occurred or not.
AnnaBridge	171:3a7713b1edbc	877	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	878	* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
AnnaBridge	171:3a7713b1edbc	879	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	880	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	881	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	882	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	171:3a7713b1edbc	883	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	171:3a7713b1edbc	884	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	171:3a7713b1edbc	885	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	171:3a7713b1edbc	886	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	887	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	171:3a7713b1edbc	888	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	171:3a7713b1edbc	889	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	890	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	171:3a7713b1edbc	891	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	171:3a7713b1edbc	892	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
AnnaBridge	171:3a7713b1edbc	893	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	171:3a7713b1edbc	894	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	171:3a7713b1edbc	895	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	896	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	171:3a7713b1edbc	897	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	898	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	171:3a7713b1edbc	899	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	171:3a7713b1edbc	900	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	171:3a7713b1edbc	901	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	171:3a7713b1edbc	902	* @retval The new state of SDIO_IT (SET or RESET).
AnnaBridge	171:3a7713b1edbc	903	*/
AnnaBridge	171:3a7713b1edbc	904	#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	905
AnnaBridge	171:3a7713b1edbc	906	/**
AnnaBridge	171:3a7713b1edbc	907	* @brief Clears the SDIO's interrupt pending bits.
AnnaBridge	171:3a7713b1edbc	908	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	909	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge	171:3a7713b1edbc	910	* This parameter can be one or a combination of the following values:
AnnaBridge	171:3a7713b1edbc	911	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	912	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	171:3a7713b1edbc	913	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	171:3a7713b1edbc	914	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	171:3a7713b1edbc	915	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	171:3a7713b1edbc	916	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	171:3a7713b1edbc	917	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	171:3a7713b1edbc	918	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	171:3a7713b1edbc	919	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
AnnaBridge	171:3a7713b1edbc	920	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	171:3a7713b1edbc	921	* @retval None
AnnaBridge	171:3a7713b1edbc	922	*/
AnnaBridge	171:3a7713b1edbc	923	#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	924
AnnaBridge	171:3a7713b1edbc	925	/**
AnnaBridge	171:3a7713b1edbc	926	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	171:3a7713b1edbc	927	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	928	* @retval None
AnnaBridge	171:3a7713b1edbc	929	*/
AnnaBridge	171:3a7713b1edbc	930	#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	931
AnnaBridge	171:3a7713b1edbc	932	/**
AnnaBridge	171:3a7713b1edbc	933	* @brief Disable Start the SD I/O Read Wait operations.
AnnaBridge	171:3a7713b1edbc	934	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	935	* @retval None
AnnaBridge	171:3a7713b1edbc	936	*/
AnnaBridge	171:3a7713b1edbc	937	#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	938
AnnaBridge	171:3a7713b1edbc	939	/**
AnnaBridge	171:3a7713b1edbc	940	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	171:3a7713b1edbc	941	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	942	* @retval None
AnnaBridge	171:3a7713b1edbc	943	*/
AnnaBridge	171:3a7713b1edbc	944	#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	945
AnnaBridge	171:3a7713b1edbc	946	/**
AnnaBridge	171:3a7713b1edbc	947	* @brief Disable Stop the SD I/O Read Wait operations.
AnnaBridge	171:3a7713b1edbc	948	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	949	* @retval None
AnnaBridge	171:3a7713b1edbc	950	*/
AnnaBridge	171:3a7713b1edbc	951	#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	952
AnnaBridge	171:3a7713b1edbc	953	/**
AnnaBridge	171:3a7713b1edbc	954	* @brief Enable the SD I/O Mode Operation.
AnnaBridge	171:3a7713b1edbc	955	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	956	* @retval None
AnnaBridge	171:3a7713b1edbc	957	*/
AnnaBridge	171:3a7713b1edbc	958	#define __SDIO_OPERATION_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	959
AnnaBridge	171:3a7713b1edbc	960	/**
AnnaBridge	171:3a7713b1edbc	961	* @brief Disable the SD I/O Mode Operation.
AnnaBridge	171:3a7713b1edbc	962	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	963	* @retval None
AnnaBridge	171:3a7713b1edbc	964	*/
AnnaBridge	171:3a7713b1edbc	965	#define __SDIO_OPERATION_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	966
AnnaBridge	171:3a7713b1edbc	967	/**
AnnaBridge	171:3a7713b1edbc	968	* @brief Enable the SD I/O Suspend command sending.
AnnaBridge	171:3a7713b1edbc	969	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	970	* @retval None
AnnaBridge	171:3a7713b1edbc	971	*/
AnnaBridge	171:3a7713b1edbc	972	#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	973
AnnaBridge	171:3a7713b1edbc	974	/**
AnnaBridge	171:3a7713b1edbc	975	* @brief Disable the SD I/O Suspend command sending.
AnnaBridge	171:3a7713b1edbc	976	* @param __INSTANCE__ : Pointer to SDIO register base
AnnaBridge	171:3a7713b1edbc	977	* @retval None
AnnaBridge	171:3a7713b1edbc	978	*/
AnnaBridge	171:3a7713b1edbc	979	#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	980
AnnaBridge	171:3a7713b1edbc	981	/**
AnnaBridge	171:3a7713b1edbc	982	* @brief Enable the command completion signal.
AnnaBridge	171:3a7713b1edbc	983	* @retval None
AnnaBridge	171:3a7713b1edbc	984	*/
AnnaBridge	171:3a7713b1edbc	985	#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	986
AnnaBridge	171:3a7713b1edbc	987	/**
AnnaBridge	171:3a7713b1edbc	988	* @brief Disable the command completion signal.
AnnaBridge	171:3a7713b1edbc	989	* @retval None
AnnaBridge	171:3a7713b1edbc	990	*/
AnnaBridge	171:3a7713b1edbc	991	#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	992
AnnaBridge	171:3a7713b1edbc	993	/**
AnnaBridge	171:3a7713b1edbc	994	* @brief Enable the CE-ATA interrupt.
AnnaBridge	171:3a7713b1edbc	995	* @retval None
AnnaBridge	171:3a7713b1edbc	996	*/
AnnaBridge	171:3a7713b1edbc	997	#define __SDIO_CEATA_ENABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)0U)
AnnaBridge	171:3a7713b1edbc	998
AnnaBridge	171:3a7713b1edbc	999	/**
AnnaBridge	171:3a7713b1edbc	1000	* @brief Disable the CE-ATA interrupt.
AnnaBridge	171:3a7713b1edbc	1001	* @retval None
AnnaBridge	171:3a7713b1edbc	1002	*/
AnnaBridge	171:3a7713b1edbc	1003	#define __SDIO_CEATA_DISABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)1U)
AnnaBridge	171:3a7713b1edbc	1004
AnnaBridge	171:3a7713b1edbc	1005	/**
AnnaBridge	171:3a7713b1edbc	1006	* @brief Enable send CE-ATA command (CMD61).
AnnaBridge	171:3a7713b1edbc	1007	* @retval None
AnnaBridge	171:3a7713b1edbc	1008	*/
AnnaBridge	171:3a7713b1edbc	1009	#define __SDIO_CEATA_SENDCMD_ENABLE() ((__IO uint32_t ) CMD_ATACMD_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1010
AnnaBridge	171:3a7713b1edbc	1011	/**
AnnaBridge	171:3a7713b1edbc	1012	* @brief Disable send CE-ATA command (CMD61).
AnnaBridge	171:3a7713b1edbc	1013	* @retval None
AnnaBridge	171:3a7713b1edbc	1014	*/
AnnaBridge	171:3a7713b1edbc	1015	#define __SDIO_CEATA_SENDCMD_DISABLE() ((__IO uint32_t ) CMD_ATACMD_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1016
AnnaBridge	171:3a7713b1edbc	1017	/**
AnnaBridge	171:3a7713b1edbc	1018	* @}
AnnaBridge	171:3a7713b1edbc	1019	*/
AnnaBridge	171:3a7713b1edbc	1020
AnnaBridge	171:3a7713b1edbc	1021	/**
AnnaBridge	171:3a7713b1edbc	1022	* @}
AnnaBridge	171:3a7713b1edbc	1023	*/
AnnaBridge	171:3a7713b1edbc	1024
AnnaBridge	171:3a7713b1edbc	1025	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1026	/** @addtogroup SDMMC_LL_Exported_Functions
AnnaBridge	171:3a7713b1edbc	1027	* @{
AnnaBridge	171:3a7713b1edbc	1028	*/
AnnaBridge	171:3a7713b1edbc	1029
AnnaBridge	171:3a7713b1edbc	1030	/* Initialization/de-initialization functions **********************************/
AnnaBridge	171:3a7713b1edbc	1031	/** @addtogroup HAL_SDMMC_LL_Group1
AnnaBridge	171:3a7713b1edbc	1032	* @{
AnnaBridge	171:3a7713b1edbc	1033	*/
AnnaBridge	171:3a7713b1edbc	1034	HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
AnnaBridge	171:3a7713b1edbc	1035	/**
AnnaBridge	171:3a7713b1edbc	1036	* @}
AnnaBridge	171:3a7713b1edbc	1037	*/
AnnaBridge	171:3a7713b1edbc	1038
AnnaBridge	171:3a7713b1edbc	1039	/* I/O operation functions *****************************************************/
AnnaBridge	171:3a7713b1edbc	1040	/** @addtogroup HAL_SDMMC_LL_Group2
AnnaBridge	171:3a7713b1edbc	1041	* @{
AnnaBridge	171:3a7713b1edbc	1042	*/
AnnaBridge	171:3a7713b1edbc	1043	uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1044	HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef SDIOx, uint32_t pWriteData);
AnnaBridge	171:3a7713b1edbc	1045	/**
AnnaBridge	171:3a7713b1edbc	1046	* @}
AnnaBridge	171:3a7713b1edbc	1047	*/
AnnaBridge	171:3a7713b1edbc	1048
AnnaBridge	171:3a7713b1edbc	1049	/* Peripheral Control functions ************************************************/
AnnaBridge	171:3a7713b1edbc	1050	/** @addtogroup HAL_SDMMC_LL_Group3
AnnaBridge	171:3a7713b1edbc	1051	* @{
AnnaBridge	171:3a7713b1edbc	1052	*/
AnnaBridge	171:3a7713b1edbc	1053	HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1054	HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1055	uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1056
AnnaBridge	171:3a7713b1edbc	1057	/* Command path state machine (CPSM) management functions */
AnnaBridge	171:3a7713b1edbc	1058	HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef SDIOx, SDIO_CmdInitTypeDef Command);
AnnaBridge	171:3a7713b1edbc	1059	uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1060	uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
AnnaBridge	171:3a7713b1edbc	1061
AnnaBridge	171:3a7713b1edbc	1062	/* Data path state machine (DPSM) management functions */
AnnaBridge	171:3a7713b1edbc	1063	HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef SDIOx, SDIO_DataInitTypeDef Data);
AnnaBridge	171:3a7713b1edbc	1064	uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1065	uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1066
AnnaBridge	171:3a7713b1edbc	1067	/* SDMMC Cards mode management functions */
AnnaBridge	171:3a7713b1edbc	1068	HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
AnnaBridge	171:3a7713b1edbc	1069
AnnaBridge	171:3a7713b1edbc	1070	/* SDMMC Commands management functions */
AnnaBridge	171:3a7713b1edbc	1071	uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
AnnaBridge	171:3a7713b1edbc	1072	uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
AnnaBridge	171:3a7713b1edbc	1073	uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
AnnaBridge	171:3a7713b1edbc	1074	uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
AnnaBridge	171:3a7713b1edbc	1075	uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
AnnaBridge	171:3a7713b1edbc	1076	uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
AnnaBridge	171:3a7713b1edbc	1077	uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
AnnaBridge	171:3a7713b1edbc	1078	uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1079	uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1080	uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
AnnaBridge	171:3a7713b1edbc	1081	uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1082	uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1083	uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	171:3a7713b1edbc	1084	uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
AnnaBridge	171:3a7713b1edbc	1085	uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
AnnaBridge	171:3a7713b1edbc	1086	uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1087	uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1088	uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	171:3a7713b1edbc	1089	uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef SDIOx, uint16_t pRCA);
AnnaBridge	171:3a7713b1edbc	1090	uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	171:3a7713b1edbc	1091	uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
AnnaBridge	171:3a7713b1edbc	1092
AnnaBridge	171:3a7713b1edbc	1093	uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	171:3a7713b1edbc	1094	uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	171:3a7713b1edbc	1095	uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
AnnaBridge	171:3a7713b1edbc	1096	uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
AnnaBridge	171:3a7713b1edbc	1097
AnnaBridge	171:3a7713b1edbc	1098	/**
AnnaBridge	171:3a7713b1edbc	1099	* @}
AnnaBridge	171:3a7713b1edbc	1100	*/
AnnaBridge	171:3a7713b1edbc	1101
AnnaBridge	171:3a7713b1edbc	1102	/**
AnnaBridge	171:3a7713b1edbc	1103	* @}
AnnaBridge	171:3a7713b1edbc	1104	*/
AnnaBridge	171:3a7713b1edbc	1105
AnnaBridge	171:3a7713b1edbc	1106	/**
AnnaBridge	171:3a7713b1edbc	1107	* @}
AnnaBridge	171:3a7713b1edbc	1108	*/
AnnaBridge	171:3a7713b1edbc	1109
AnnaBridge	171:3a7713b1edbc	1110	/**
AnnaBridge	171:3a7713b1edbc	1111	* @}
AnnaBridge	171:3a7713b1edbc	1112	*/
AnnaBridge	171:3a7713b1edbc	1113
AnnaBridge	171:3a7713b1edbc	1114	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1115	}
AnnaBridge	171:3a7713b1edbc	1116	#endif
AnnaBridge	171:3a7713b1edbc	1117
AnnaBridge	171:3a7713b1edbc	1118	#endif /* __STM32F2xx_LL_SDMMC_H */
AnnaBridge	171:3a7713b1edbc	1119
AnnaBridge	171:3a7713b1edbc	1120	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/