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TARGET_NUCLEO_F207ZG/TOOLCHAIN_ARM_MICRO/stm32f2xx_hal_dma.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f2xx_hal_dma.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @version V1.2.1
AnnaBridge 171:3a7713b1edbc 6 * @date 14-April-2017
AnnaBridge 171:3a7713b1edbc 7 * @brief Header file of DMA HAL module.
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 * @attention
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 12 *
AnnaBridge 171:3a7713b1edbc 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 14 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 19 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 21 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 22 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 23 *
AnnaBridge 171:3a7713b1edbc 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 34 *
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 36 */
AnnaBridge 171:3a7713b1edbc 37
AnnaBridge 171:3a7713b1edbc 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 39 #ifndef __STM32F2xx_HAL_DMA_H
AnnaBridge 171:3a7713b1edbc 40 #define __STM32F2xx_HAL_DMA_H
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 43 extern "C" {
AnnaBridge 171:3a7713b1edbc 44 #endif
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 47 #include "stm32f2xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /** @addtogroup STM32F2xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 50 * @{
AnnaBridge 171:3a7713b1edbc 51 */
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /** @addtogroup DMA
AnnaBridge 171:3a7713b1edbc 54 * @{
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /** @defgroup DMA_Exported_Types DMA Exported Types
AnnaBridge 171:3a7713b1edbc 60 * @brief DMA Exported Types
AnnaBridge 171:3a7713b1edbc 61 * @{
AnnaBridge 171:3a7713b1edbc 62 */
AnnaBridge 171:3a7713b1edbc 63
AnnaBridge 171:3a7713b1edbc 64 /**
AnnaBridge 171:3a7713b1edbc 65 * @brief DMA Configuration Structure definition
AnnaBridge 171:3a7713b1edbc 66 */
AnnaBridge 171:3a7713b1edbc 67 typedef struct
AnnaBridge 171:3a7713b1edbc 68 {
AnnaBridge 171:3a7713b1edbc 69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
AnnaBridge 171:3a7713b1edbc 70 This parameter can be a value of @ref DMA_Channel_selection */
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge 171:3a7713b1edbc 73 from memory to memory or from peripheral to memory.
AnnaBridge 171:3a7713b1edbc 74 This parameter can be a value of @ref DMA_Data_transfer_direction */
AnnaBridge 171:3a7713b1edbc 75
AnnaBridge 171:3a7713b1edbc 76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
AnnaBridge 171:3a7713b1edbc 77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
AnnaBridge 171:3a7713b1edbc 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
AnnaBridge 171:3a7713b1edbc 83 This parameter can be a value of @ref DMA_Peripheral_data_size */
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
AnnaBridge 171:3a7713b1edbc 86 This parameter can be a value of @ref DMA_Memory_data_size */
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
AnnaBridge 171:3a7713b1edbc 89 This parameter can be a value of @ref DMA_mode
AnnaBridge 171:3a7713b1edbc 90 @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 171:3a7713b1edbc 91 data transfer is configured on the selected Stream */
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
AnnaBridge 171:3a7713b1edbc 94 This parameter can be a value of @ref DMA_Priority_level */
AnnaBridge 171:3a7713b1edbc 95
AnnaBridge 171:3a7713b1edbc 96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
AnnaBridge 171:3a7713b1edbc 97 This parameter can be a value of @ref DMA_FIFO_direct_mode
AnnaBridge 171:3a7713b1edbc 98 @note The Direct mode (FIFO mode disabled) cannot be used if the
AnnaBridge 171:3a7713b1edbc 99 memory-to-memory data transfer is configured on the selected stream */
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
AnnaBridge 171:3a7713b1edbc 102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
AnnaBridge 171:3a7713b1edbc 103
AnnaBridge 171:3a7713b1edbc 104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
AnnaBridge 171:3a7713b1edbc 105 It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge 171:3a7713b1edbc 106 transaction.
AnnaBridge 171:3a7713b1edbc 107 This parameter can be a value of @ref DMA_Memory_burst
AnnaBridge 171:3a7713b1edbc 108 @note The burst mode is possible only if the address Increment mode is enabled. */
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
AnnaBridge 171:3a7713b1edbc 111 It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge 171:3a7713b1edbc 112 transaction.
AnnaBridge 171:3a7713b1edbc 113 This parameter can be a value of @ref DMA_Peripheral_burst
AnnaBridge 171:3a7713b1edbc 114 @note The burst mode is possible only if the address Increment mode is enabled. */
AnnaBridge 171:3a7713b1edbc 115 }DMA_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 /**
AnnaBridge 171:3a7713b1edbc 119 * @brief HAL DMA State structures definition
AnnaBridge 171:3a7713b1edbc 120 */
AnnaBridge 171:3a7713b1edbc 121 typedef enum
AnnaBridge 171:3a7713b1edbc 122 {
AnnaBridge 171:3a7713b1edbc 123 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
AnnaBridge 171:3a7713b1edbc 124 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
AnnaBridge 171:3a7713b1edbc 125 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
AnnaBridge 171:3a7713b1edbc 126 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
AnnaBridge 171:3a7713b1edbc 127 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
AnnaBridge 171:3a7713b1edbc 128 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
AnnaBridge 171:3a7713b1edbc 129 }HAL_DMA_StateTypeDef;
AnnaBridge 171:3a7713b1edbc 130
AnnaBridge 171:3a7713b1edbc 131 /**
AnnaBridge 171:3a7713b1edbc 132 * @brief HAL DMA Error Code structure definition
AnnaBridge 171:3a7713b1edbc 133 */
AnnaBridge 171:3a7713b1edbc 134 typedef enum
AnnaBridge 171:3a7713b1edbc 135 {
AnnaBridge 171:3a7713b1edbc 136 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
AnnaBridge 171:3a7713b1edbc 137 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
AnnaBridge 171:3a7713b1edbc 138 }HAL_DMA_LevelCompleteTypeDef;
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 /**
AnnaBridge 171:3a7713b1edbc 141 * @brief HAL DMA Error Code structure definition
AnnaBridge 171:3a7713b1edbc 142 */
AnnaBridge 171:3a7713b1edbc 143 typedef enum
AnnaBridge 171:3a7713b1edbc 144 {
AnnaBridge 171:3a7713b1edbc 145 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
AnnaBridge 171:3a7713b1edbc 146 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
AnnaBridge 171:3a7713b1edbc 147 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
AnnaBridge 171:3a7713b1edbc 148 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
AnnaBridge 171:3a7713b1edbc 149 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
AnnaBridge 171:3a7713b1edbc 150 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
AnnaBridge 171:3a7713b1edbc 151 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
AnnaBridge 171:3a7713b1edbc 152 }HAL_DMA_CallbackIDTypeDef;
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154 /**
AnnaBridge 171:3a7713b1edbc 155 * @brief DMA handle Structure definition
AnnaBridge 171:3a7713b1edbc 156 */
AnnaBridge 171:3a7713b1edbc 157 typedef struct __DMA_HandleTypeDef
AnnaBridge 171:3a7713b1edbc 158 {
AnnaBridge 171:3a7713b1edbc 159 DMA_Stream_TypeDef *Instance; /*!< Register base address */
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 DMA_InitTypeDef Init; /*!< DMA communication parameters */
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 HAL_LockTypeDef Lock; /*!< DMA locking object */
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 void *Parent; /*!< Parent object state */
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
AnnaBridge 171:3a7713b1edbc 180
AnnaBridge 171:3a7713b1edbc 181 __IO uint32_t ErrorCode; /*!< DMA Error code */
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 uint32_t StreamIndex; /*!< DMA Stream Index */
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 }DMA_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /**
AnnaBridge 171:3a7713b1edbc 190 * @}
AnnaBridge 171:3a7713b1edbc 191 */
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 /** @defgroup DMA_Exported_Constants DMA Exported Constants
AnnaBridge 171:3a7713b1edbc 196 * @brief DMA Exported constants
AnnaBridge 171:3a7713b1edbc 197 * @{
AnnaBridge 171:3a7713b1edbc 198 */
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /** @defgroup DMA_Error_Code DMA Error Code
AnnaBridge 171:3a7713b1edbc 201 * @brief DMA Error Code
AnnaBridge 171:3a7713b1edbc 202 * @{
AnnaBridge 171:3a7713b1edbc 203 */
AnnaBridge 171:3a7713b1edbc 204 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 171:3a7713b1edbc 205 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
AnnaBridge 171:3a7713b1edbc 206 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
AnnaBridge 171:3a7713b1edbc 207 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
AnnaBridge 171:3a7713b1edbc 208 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
AnnaBridge 171:3a7713b1edbc 209 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
AnnaBridge 171:3a7713b1edbc 210 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
AnnaBridge 171:3a7713b1edbc 211 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
AnnaBridge 171:3a7713b1edbc 212 /**
AnnaBridge 171:3a7713b1edbc 213 * @}
AnnaBridge 171:3a7713b1edbc 214 */
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /** @defgroup DMA_Channel_selection DMA Channel selection
AnnaBridge 171:3a7713b1edbc 217 * @brief DMA channel selection
AnnaBridge 171:3a7713b1edbc 218 * @{
AnnaBridge 171:3a7713b1edbc 219 */
AnnaBridge 171:3a7713b1edbc 220 #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
AnnaBridge 171:3a7713b1edbc 221 #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
AnnaBridge 171:3a7713b1edbc 222 #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
AnnaBridge 171:3a7713b1edbc 223 #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
AnnaBridge 171:3a7713b1edbc 224 #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
AnnaBridge 171:3a7713b1edbc 225 #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
AnnaBridge 171:3a7713b1edbc 226 #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
AnnaBridge 171:3a7713b1edbc 227 #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
AnnaBridge 171:3a7713b1edbc 228 /**
AnnaBridge 171:3a7713b1edbc 229 * @}
AnnaBridge 171:3a7713b1edbc 230 */
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
AnnaBridge 171:3a7713b1edbc 233 * @brief DMA data transfer direction
AnnaBridge 171:3a7713b1edbc 234 * @{
AnnaBridge 171:3a7713b1edbc 235 */
AnnaBridge 171:3a7713b1edbc 236 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
AnnaBridge 171:3a7713b1edbc 237 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
AnnaBridge 171:3a7713b1edbc 238 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
AnnaBridge 171:3a7713b1edbc 239 /**
AnnaBridge 171:3a7713b1edbc 240 * @}
AnnaBridge 171:3a7713b1edbc 241 */
AnnaBridge 171:3a7713b1edbc 242
AnnaBridge 171:3a7713b1edbc 243 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
AnnaBridge 171:3a7713b1edbc 244 * @brief DMA peripheral incremented mode
AnnaBridge 171:3a7713b1edbc 245 * @{
AnnaBridge 171:3a7713b1edbc 246 */
AnnaBridge 171:3a7713b1edbc 247 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
AnnaBridge 171:3a7713b1edbc 248 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
AnnaBridge 171:3a7713b1edbc 249 /**
AnnaBridge 171:3a7713b1edbc 250 * @}
AnnaBridge 171:3a7713b1edbc 251 */
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
AnnaBridge 171:3a7713b1edbc 254 * @brief DMA memory incremented mode
AnnaBridge 171:3a7713b1edbc 255 * @{
AnnaBridge 171:3a7713b1edbc 256 */
AnnaBridge 171:3a7713b1edbc 257 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
AnnaBridge 171:3a7713b1edbc 258 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
AnnaBridge 171:3a7713b1edbc 259 /**
AnnaBridge 171:3a7713b1edbc 260 * @}
AnnaBridge 171:3a7713b1edbc 261 */
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
AnnaBridge 171:3a7713b1edbc 264 * @brief DMA peripheral data size
AnnaBridge 171:3a7713b1edbc 265 * @{
AnnaBridge 171:3a7713b1edbc 266 */
AnnaBridge 171:3a7713b1edbc 267 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
AnnaBridge 171:3a7713b1edbc 268 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
AnnaBridge 171:3a7713b1edbc 269 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
AnnaBridge 171:3a7713b1edbc 270 /**
AnnaBridge 171:3a7713b1edbc 271 * @}
AnnaBridge 171:3a7713b1edbc 272 */
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274 /** @defgroup DMA_Memory_data_size DMA Memory data size
AnnaBridge 171:3a7713b1edbc 275 * @brief DMA memory data size
AnnaBridge 171:3a7713b1edbc 276 * @{
AnnaBridge 171:3a7713b1edbc 277 */
AnnaBridge 171:3a7713b1edbc 278 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
AnnaBridge 171:3a7713b1edbc 279 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
AnnaBridge 171:3a7713b1edbc 280 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
AnnaBridge 171:3a7713b1edbc 281 /**
AnnaBridge 171:3a7713b1edbc 282 * @}
AnnaBridge 171:3a7713b1edbc 283 */
AnnaBridge 171:3a7713b1edbc 284
AnnaBridge 171:3a7713b1edbc 285 /** @defgroup DMA_mode DMA mode
AnnaBridge 171:3a7713b1edbc 286 * @brief DMA mode
AnnaBridge 171:3a7713b1edbc 287 * @{
AnnaBridge 171:3a7713b1edbc 288 */
AnnaBridge 171:3a7713b1edbc 289 #define DMA_NORMAL 0x00000000U /*!< Normal mode */
AnnaBridge 171:3a7713b1edbc 290 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
AnnaBridge 171:3a7713b1edbc 291 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
AnnaBridge 171:3a7713b1edbc 292 /**
AnnaBridge 171:3a7713b1edbc 293 * @}
AnnaBridge 171:3a7713b1edbc 294 */
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 /** @defgroup DMA_Priority_level DMA Priority level
AnnaBridge 171:3a7713b1edbc 297 * @brief DMA priority levels
AnnaBridge 171:3a7713b1edbc 298 * @{
AnnaBridge 171:3a7713b1edbc 299 */
AnnaBridge 171:3a7713b1edbc 300 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
AnnaBridge 171:3a7713b1edbc 301 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
AnnaBridge 171:3a7713b1edbc 302 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
AnnaBridge 171:3a7713b1edbc 303 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
AnnaBridge 171:3a7713b1edbc 304 /**
AnnaBridge 171:3a7713b1edbc 305 * @}
AnnaBridge 171:3a7713b1edbc 306 */
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
AnnaBridge 171:3a7713b1edbc 309 * @brief DMA FIFO direct mode
AnnaBridge 171:3a7713b1edbc 310 * @{
AnnaBridge 171:3a7713b1edbc 311 */
AnnaBridge 171:3a7713b1edbc 312 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
AnnaBridge 171:3a7713b1edbc 313 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
AnnaBridge 171:3a7713b1edbc 314 /**
AnnaBridge 171:3a7713b1edbc 315 * @}
AnnaBridge 171:3a7713b1edbc 316 */
AnnaBridge 171:3a7713b1edbc 317
AnnaBridge 171:3a7713b1edbc 318 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
AnnaBridge 171:3a7713b1edbc 319 * @brief DMA FIFO level
AnnaBridge 171:3a7713b1edbc 320 * @{
AnnaBridge 171:3a7713b1edbc 321 */
AnnaBridge 171:3a7713b1edbc 322 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
AnnaBridge 171:3a7713b1edbc 323 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
AnnaBridge 171:3a7713b1edbc 324 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
AnnaBridge 171:3a7713b1edbc 325 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
AnnaBridge 171:3a7713b1edbc 326 /**
AnnaBridge 171:3a7713b1edbc 327 * @}
AnnaBridge 171:3a7713b1edbc 328 */
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 /** @defgroup DMA_Memory_burst DMA Memory burst
AnnaBridge 171:3a7713b1edbc 331 * @brief DMA memory burst
AnnaBridge 171:3a7713b1edbc 332 * @{
AnnaBridge 171:3a7713b1edbc 333 */
AnnaBridge 171:3a7713b1edbc 334 #define DMA_MBURST_SINGLE 0x00000000U
AnnaBridge 171:3a7713b1edbc 335 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
AnnaBridge 171:3a7713b1edbc 336 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
AnnaBridge 171:3a7713b1edbc 337 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
AnnaBridge 171:3a7713b1edbc 338 /**
AnnaBridge 171:3a7713b1edbc 339 * @}
AnnaBridge 171:3a7713b1edbc 340 */
AnnaBridge 171:3a7713b1edbc 341
AnnaBridge 171:3a7713b1edbc 342 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
AnnaBridge 171:3a7713b1edbc 343 * @brief DMA peripheral burst
AnnaBridge 171:3a7713b1edbc 344 * @{
AnnaBridge 171:3a7713b1edbc 345 */
AnnaBridge 171:3a7713b1edbc 346 #define DMA_PBURST_SINGLE 0x00000000U
AnnaBridge 171:3a7713b1edbc 347 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
AnnaBridge 171:3a7713b1edbc 348 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
AnnaBridge 171:3a7713b1edbc 349 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
AnnaBridge 171:3a7713b1edbc 350 /**
AnnaBridge 171:3a7713b1edbc 351 * @}
AnnaBridge 171:3a7713b1edbc 352 */
AnnaBridge 171:3a7713b1edbc 353
AnnaBridge 171:3a7713b1edbc 354 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
AnnaBridge 171:3a7713b1edbc 355 * @brief DMA interrupts definition
AnnaBridge 171:3a7713b1edbc 356 * @{
AnnaBridge 171:3a7713b1edbc 357 */
AnnaBridge 171:3a7713b1edbc 358 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
AnnaBridge 171:3a7713b1edbc 359 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
AnnaBridge 171:3a7713b1edbc 360 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
AnnaBridge 171:3a7713b1edbc 361 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
AnnaBridge 171:3a7713b1edbc 362 #define DMA_IT_FE 0x00000080U
AnnaBridge 171:3a7713b1edbc 363 /**
AnnaBridge 171:3a7713b1edbc 364 * @}
AnnaBridge 171:3a7713b1edbc 365 */
AnnaBridge 171:3a7713b1edbc 366
AnnaBridge 171:3a7713b1edbc 367 /** @defgroup DMA_flag_definitions DMA flag definitions
AnnaBridge 171:3a7713b1edbc 368 * @brief DMA flag definitions
AnnaBridge 171:3a7713b1edbc 369 * @{
AnnaBridge 171:3a7713b1edbc 370 */
AnnaBridge 171:3a7713b1edbc 371 #define DMA_FLAG_FEIF0_4 0x00800001U
AnnaBridge 171:3a7713b1edbc 372 #define DMA_FLAG_DMEIF0_4 0x00800004U
AnnaBridge 171:3a7713b1edbc 373 #define DMA_FLAG_TEIF0_4 0x00000008U
AnnaBridge 171:3a7713b1edbc 374 #define DMA_FLAG_HTIF0_4 0x00000010U
AnnaBridge 171:3a7713b1edbc 375 #define DMA_FLAG_TCIF0_4 0x00000020U
AnnaBridge 171:3a7713b1edbc 376 #define DMA_FLAG_FEIF1_5 0x00000040U
AnnaBridge 171:3a7713b1edbc 377 #define DMA_FLAG_DMEIF1_5 0x00000100U
AnnaBridge 171:3a7713b1edbc 378 #define DMA_FLAG_TEIF1_5 0x00000200U
AnnaBridge 171:3a7713b1edbc 379 #define DMA_FLAG_HTIF1_5 0x00000400U
AnnaBridge 171:3a7713b1edbc 380 #define DMA_FLAG_TCIF1_5 0x00000800U
AnnaBridge 171:3a7713b1edbc 381 #define DMA_FLAG_FEIF2_6 0x00010000U
AnnaBridge 171:3a7713b1edbc 382 #define DMA_FLAG_DMEIF2_6 0x00040000U
AnnaBridge 171:3a7713b1edbc 383 #define DMA_FLAG_TEIF2_6 0x00080000U
AnnaBridge 171:3a7713b1edbc 384 #define DMA_FLAG_HTIF2_6 0x00100000U
AnnaBridge 171:3a7713b1edbc 385 #define DMA_FLAG_TCIF2_6 0x00200000U
AnnaBridge 171:3a7713b1edbc 386 #define DMA_FLAG_FEIF3_7 0x00400000U
AnnaBridge 171:3a7713b1edbc 387 #define DMA_FLAG_DMEIF3_7 0x01000000U
AnnaBridge 171:3a7713b1edbc 388 #define DMA_FLAG_TEIF3_7 0x02000000U
AnnaBridge 171:3a7713b1edbc 389 #define DMA_FLAG_HTIF3_7 0x04000000U
AnnaBridge 171:3a7713b1edbc 390 #define DMA_FLAG_TCIF3_7 0x08000000U
AnnaBridge 171:3a7713b1edbc 391 /**
AnnaBridge 171:3a7713b1edbc 392 * @}
AnnaBridge 171:3a7713b1edbc 393 */
AnnaBridge 171:3a7713b1edbc 394
AnnaBridge 171:3a7713b1edbc 395 /**
AnnaBridge 171:3a7713b1edbc 396 * @}
AnnaBridge 171:3a7713b1edbc 397 */
AnnaBridge 171:3a7713b1edbc 398
AnnaBridge 171:3a7713b1edbc 399 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 400
AnnaBridge 171:3a7713b1edbc 401 /** @brief Reset DMA handle state
AnnaBridge 171:3a7713b1edbc 402 * @param __HANDLE__: specifies the DMA handle.
AnnaBridge 171:3a7713b1edbc 403 * @retval None
AnnaBridge 171:3a7713b1edbc 404 */
AnnaBridge 171:3a7713b1edbc 405 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /**
AnnaBridge 171:3a7713b1edbc 408 * @brief Return the current DMA Stream FIFO filled level.
AnnaBridge 171:3a7713b1edbc 409 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 410 * @retval The FIFO filling state.
AnnaBridge 171:3a7713b1edbc 411 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
AnnaBridge 171:3a7713b1edbc 412 * and not empty.
AnnaBridge 171:3a7713b1edbc 413 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
AnnaBridge 171:3a7713b1edbc 414 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
AnnaBridge 171:3a7713b1edbc 415 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
AnnaBridge 171:3a7713b1edbc 416 * - DMA_FIFOStatus_Empty: when FIFO is empty
AnnaBridge 171:3a7713b1edbc 417 * - DMA_FIFOStatus_Full: when FIFO is full
AnnaBridge 171:3a7713b1edbc 418 */
AnnaBridge 171:3a7713b1edbc 419 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
AnnaBridge 171:3a7713b1edbc 420
AnnaBridge 171:3a7713b1edbc 421 /**
AnnaBridge 171:3a7713b1edbc 422 * @brief Enable the specified DMA Stream.
AnnaBridge 171:3a7713b1edbc 423 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 424 * @retval None
AnnaBridge 171:3a7713b1edbc 425 */
AnnaBridge 171:3a7713b1edbc 426 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
AnnaBridge 171:3a7713b1edbc 427
AnnaBridge 171:3a7713b1edbc 428 /**
AnnaBridge 171:3a7713b1edbc 429 * @brief Disable the specified DMA Stream.
AnnaBridge 171:3a7713b1edbc 430 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 431 * @retval None
AnnaBridge 171:3a7713b1edbc 432 */
AnnaBridge 171:3a7713b1edbc 433 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 /* Interrupt & Flag management */
AnnaBridge 171:3a7713b1edbc 436
AnnaBridge 171:3a7713b1edbc 437 /**
AnnaBridge 171:3a7713b1edbc 438 * @brief Return the current DMA Stream transfer complete flag.
AnnaBridge 171:3a7713b1edbc 439 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 440 * @retval The specified transfer complete flag index.
AnnaBridge 171:3a7713b1edbc 441 */
AnnaBridge 171:3a7713b1edbc 442 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 443 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 171:3a7713b1edbc 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 171:3a7713b1edbc 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 171:3a7713b1edbc 446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 171:3a7713b1edbc 447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 171:3a7713b1edbc 448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 171:3a7713b1edbc 449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 171:3a7713b1edbc 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 171:3a7713b1edbc 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 171:3a7713b1edbc 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 171:3a7713b1edbc 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 171:3a7713b1edbc 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 171:3a7713b1edbc 455 DMA_FLAG_TCIF3_7)
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 /**
AnnaBridge 171:3a7713b1edbc 458 * @brief Return the current DMA Stream half transfer complete flag.
AnnaBridge 171:3a7713b1edbc 459 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 460 * @retval The specified half transfer complete flag index.
AnnaBridge 171:3a7713b1edbc 461 */
AnnaBridge 171:3a7713b1edbc 462 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
AnnaBridge 171:3a7713b1edbc 463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 171:3a7713b1edbc 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 171:3a7713b1edbc 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 171:3a7713b1edbc 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 171:3a7713b1edbc 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 171:3a7713b1edbc 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 171:3a7713b1edbc 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 171:3a7713b1edbc 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 171:3a7713b1edbc 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 171:3a7713b1edbc 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 171:3a7713b1edbc 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 171:3a7713b1edbc 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 171:3a7713b1edbc 475 DMA_FLAG_HTIF3_7)
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 /**
AnnaBridge 171:3a7713b1edbc 478 * @brief Return the current DMA Stream transfer error flag.
AnnaBridge 171:3a7713b1edbc 479 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 480 * @retval The specified transfer error flag index.
AnnaBridge 171:3a7713b1edbc 481 */
AnnaBridge 171:3a7713b1edbc 482 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
AnnaBridge 171:3a7713b1edbc 483 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 495 DMA_FLAG_TEIF3_7)
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 /**
AnnaBridge 171:3a7713b1edbc 498 * @brief Return the current DMA Stream FIFO error flag.
AnnaBridge 171:3a7713b1edbc 499 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 500 * @retval The specified FIFO error flag index.
AnnaBridge 171:3a7713b1edbc 501 */
AnnaBridge 171:3a7713b1edbc 502 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
AnnaBridge 171:3a7713b1edbc 503 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 515 DMA_FLAG_FEIF3_7)
AnnaBridge 171:3a7713b1edbc 516
AnnaBridge 171:3a7713b1edbc 517 /**
AnnaBridge 171:3a7713b1edbc 518 * @brief Return the current DMA Stream direct mode error flag.
AnnaBridge 171:3a7713b1edbc 519 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 520 * @retval The specified direct mode error flag index.
AnnaBridge 171:3a7713b1edbc 521 */
AnnaBridge 171:3a7713b1edbc 522 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
AnnaBridge 171:3a7713b1edbc 523 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 171:3a7713b1edbc 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 171:3a7713b1edbc 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 171:3a7713b1edbc 535 DMA_FLAG_DMEIF3_7)
AnnaBridge 171:3a7713b1edbc 536
AnnaBridge 171:3a7713b1edbc 537 /**
AnnaBridge 171:3a7713b1edbc 538 * @brief Get the DMA Stream pending flags.
AnnaBridge 171:3a7713b1edbc 539 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 540 * @param __FLAG__: Get the specified flag.
AnnaBridge 171:3a7713b1edbc 541 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 542 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
AnnaBridge 171:3a7713b1edbc 543 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
AnnaBridge 171:3a7713b1edbc 544 * @arg DMA_FLAG_TEIFx: Transfer error flag.
AnnaBridge 171:3a7713b1edbc 545 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
AnnaBridge 171:3a7713b1edbc 546 * @arg DMA_FLAG_FEIFx: FIFO error flag.
AnnaBridge 171:3a7713b1edbc 547 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
AnnaBridge 171:3a7713b1edbc 548 * @retval The state of FLAG (SET or RESET).
AnnaBridge 171:3a7713b1edbc 549 */
AnnaBridge 171:3a7713b1edbc 550 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
AnnaBridge 171:3a7713b1edbc 551 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
AnnaBridge 171:3a7713b1edbc 552 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
AnnaBridge 171:3a7713b1edbc 553 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
AnnaBridge 171:3a7713b1edbc 554
AnnaBridge 171:3a7713b1edbc 555 /**
AnnaBridge 171:3a7713b1edbc 556 * @brief Clear the DMA Stream pending flags.
AnnaBridge 171:3a7713b1edbc 557 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 558 * @param __FLAG__: specifies the flag to clear.
AnnaBridge 171:3a7713b1edbc 559 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 560 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
AnnaBridge 171:3a7713b1edbc 561 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
AnnaBridge 171:3a7713b1edbc 562 * @arg DMA_FLAG_TEIFx: Transfer error flag.
AnnaBridge 171:3a7713b1edbc 563 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
AnnaBridge 171:3a7713b1edbc 564 * @arg DMA_FLAG_FEIFx: FIFO error flag.
AnnaBridge 171:3a7713b1edbc 565 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
AnnaBridge 171:3a7713b1edbc 566 * @retval None
AnnaBridge 171:3a7713b1edbc 567 */
AnnaBridge 171:3a7713b1edbc 568 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
AnnaBridge 171:3a7713b1edbc 569 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
AnnaBridge 171:3a7713b1edbc 570 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
AnnaBridge 171:3a7713b1edbc 571 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
AnnaBridge 171:3a7713b1edbc 572
AnnaBridge 171:3a7713b1edbc 573 /**
AnnaBridge 171:3a7713b1edbc 574 * @brief Enable the specified DMA Stream interrupts.
AnnaBridge 171:3a7713b1edbc 575 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 576 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 171:3a7713b1edbc 577 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 578 * @arg DMA_IT_TC: Transfer complete interrupt mask.
AnnaBridge 171:3a7713b1edbc 579 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
AnnaBridge 171:3a7713b1edbc 580 * @arg DMA_IT_TE: Transfer error interrupt mask.
AnnaBridge 171:3a7713b1edbc 581 * @arg DMA_IT_FE: FIFO error interrupt mask.
AnnaBridge 171:3a7713b1edbc 582 * @arg DMA_IT_DME: Direct mode error interrupt.
AnnaBridge 171:3a7713b1edbc 583 * @retval None
AnnaBridge 171:3a7713b1edbc 584 */
AnnaBridge 171:3a7713b1edbc 585 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
AnnaBridge 171:3a7713b1edbc 586 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
AnnaBridge 171:3a7713b1edbc 587
AnnaBridge 171:3a7713b1edbc 588 /**
AnnaBridge 171:3a7713b1edbc 589 * @brief Disable the specified DMA Stream interrupts.
AnnaBridge 171:3a7713b1edbc 590 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 591 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 171:3a7713b1edbc 592 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 593 * @arg DMA_IT_TC: Transfer complete interrupt mask.
AnnaBridge 171:3a7713b1edbc 594 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
AnnaBridge 171:3a7713b1edbc 595 * @arg DMA_IT_TE: Transfer error interrupt mask.
AnnaBridge 171:3a7713b1edbc 596 * @arg DMA_IT_FE: FIFO error interrupt mask.
AnnaBridge 171:3a7713b1edbc 597 * @arg DMA_IT_DME: Direct mode error interrupt.
AnnaBridge 171:3a7713b1edbc 598 * @retval None
AnnaBridge 171:3a7713b1edbc 599 */
AnnaBridge 171:3a7713b1edbc 600 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
AnnaBridge 171:3a7713b1edbc 601 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
AnnaBridge 171:3a7713b1edbc 602
AnnaBridge 171:3a7713b1edbc 603 /**
AnnaBridge 171:3a7713b1edbc 604 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 605 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 606 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
AnnaBridge 171:3a7713b1edbc 607 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 608 * @arg DMA_IT_TC: Transfer complete interrupt mask.
AnnaBridge 171:3a7713b1edbc 609 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
AnnaBridge 171:3a7713b1edbc 610 * @arg DMA_IT_TE: Transfer error interrupt mask.
AnnaBridge 171:3a7713b1edbc 611 * @arg DMA_IT_FE: FIFO error interrupt mask.
AnnaBridge 171:3a7713b1edbc 612 * @arg DMA_IT_DME: Direct mode error interrupt.
AnnaBridge 171:3a7713b1edbc 613 * @retval The state of DMA_IT.
AnnaBridge 171:3a7713b1edbc 614 */
AnnaBridge 171:3a7713b1edbc 615 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
AnnaBridge 171:3a7713b1edbc 616 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
AnnaBridge 171:3a7713b1edbc 617 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
AnnaBridge 171:3a7713b1edbc 618
AnnaBridge 171:3a7713b1edbc 619 /**
AnnaBridge 171:3a7713b1edbc 620 * @brief Writes the number of data units to be transferred on the DMA Stream.
AnnaBridge 171:3a7713b1edbc 621 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 622 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
AnnaBridge 171:3a7713b1edbc 623 * Number of data items depends only on the Peripheral data format.
AnnaBridge 171:3a7713b1edbc 624 *
AnnaBridge 171:3a7713b1edbc 625 * @note If Peripheral data format is Bytes: number of data units is equal
AnnaBridge 171:3a7713b1edbc 626 * to total number of bytes to be transferred.
AnnaBridge 171:3a7713b1edbc 627 *
AnnaBridge 171:3a7713b1edbc 628 * @note If Peripheral data format is Half-Word: number of data units is
AnnaBridge 171:3a7713b1edbc 629 * equal to total number of bytes to be transferred / 2.
AnnaBridge 171:3a7713b1edbc 630 *
AnnaBridge 171:3a7713b1edbc 631 * @note If Peripheral data format is Word: number of data units is equal
AnnaBridge 171:3a7713b1edbc 632 * to total number of bytes to be transferred / 4.
AnnaBridge 171:3a7713b1edbc 633 *
AnnaBridge 171:3a7713b1edbc 634 * @retval The number of remaining data units in the current DMAy Streamx transfer.
AnnaBridge 171:3a7713b1edbc 635 */
AnnaBridge 171:3a7713b1edbc 636 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
AnnaBridge 171:3a7713b1edbc 637
AnnaBridge 171:3a7713b1edbc 638 /**
AnnaBridge 171:3a7713b1edbc 639 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
AnnaBridge 171:3a7713b1edbc 640 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 641 *
AnnaBridge 171:3a7713b1edbc 642 * @retval The number of remaining data units in the current DMA Stream transfer.
AnnaBridge 171:3a7713b1edbc 643 */
AnnaBridge 171:3a7713b1edbc 644 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
AnnaBridge 171:3a7713b1edbc 645
AnnaBridge 171:3a7713b1edbc 646
AnnaBridge 171:3a7713b1edbc 647 /* Include DMA HAL Extension module */
AnnaBridge 171:3a7713b1edbc 648 #include "stm32f2xx_hal_dma_ex.h"
AnnaBridge 171:3a7713b1edbc 649
AnnaBridge 171:3a7713b1edbc 650 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 651
AnnaBridge 171:3a7713b1edbc 652 /** @defgroup DMA_Exported_Functions DMA Exported Functions
AnnaBridge 171:3a7713b1edbc 653 * @brief DMA Exported functions
AnnaBridge 171:3a7713b1edbc 654 * @{
AnnaBridge 171:3a7713b1edbc 655 */
AnnaBridge 171:3a7713b1edbc 656
AnnaBridge 171:3a7713b1edbc 657 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 171:3a7713b1edbc 658 * @brief Initialization and de-initialization functions
AnnaBridge 171:3a7713b1edbc 659 * @{
AnnaBridge 171:3a7713b1edbc 660 */
AnnaBridge 171:3a7713b1edbc 661 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 662 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 663 /**
AnnaBridge 171:3a7713b1edbc 664 * @}
AnnaBridge 171:3a7713b1edbc 665 */
AnnaBridge 171:3a7713b1edbc 666
AnnaBridge 171:3a7713b1edbc 667 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
AnnaBridge 171:3a7713b1edbc 668 * @brief I/O operation functions
AnnaBridge 171:3a7713b1edbc 669 * @{
AnnaBridge 171:3a7713b1edbc 670 */
AnnaBridge 171:3a7713b1edbc 671 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 171:3a7713b1edbc 672 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 171:3a7713b1edbc 673 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 674 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 675 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 676 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 677 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 678 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
AnnaBridge 171:3a7713b1edbc 679 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
AnnaBridge 171:3a7713b1edbc 680
AnnaBridge 171:3a7713b1edbc 681 /**
AnnaBridge 171:3a7713b1edbc 682 * @}
AnnaBridge 171:3a7713b1edbc 683 */
AnnaBridge 171:3a7713b1edbc 684
AnnaBridge 171:3a7713b1edbc 685 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
AnnaBridge 171:3a7713b1edbc 686 * @brief Peripheral State functions
AnnaBridge 171:3a7713b1edbc 687 * @{
AnnaBridge 171:3a7713b1edbc 688 */
AnnaBridge 171:3a7713b1edbc 689 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 690 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 691 /**
AnnaBridge 171:3a7713b1edbc 692 * @}
AnnaBridge 171:3a7713b1edbc 693 */
AnnaBridge 171:3a7713b1edbc 694 /**
AnnaBridge 171:3a7713b1edbc 695 * @}
AnnaBridge 171:3a7713b1edbc 696 */
AnnaBridge 171:3a7713b1edbc 697 /* Private Constants -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 698 /** @defgroup DMA_Private_Constants DMA Private Constants
AnnaBridge 171:3a7713b1edbc 699 * @brief DMA private defines and constants
AnnaBridge 171:3a7713b1edbc 700 * @{
AnnaBridge 171:3a7713b1edbc 701 */
AnnaBridge 171:3a7713b1edbc 702 /**
AnnaBridge 171:3a7713b1edbc 703 * @}
AnnaBridge 171:3a7713b1edbc 704 */
AnnaBridge 171:3a7713b1edbc 705
AnnaBridge 171:3a7713b1edbc 706 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 707 /** @defgroup DMA_Private_Macros DMA Private Macros
AnnaBridge 171:3a7713b1edbc 708 * @brief DMA private macros
AnnaBridge 171:3a7713b1edbc 709 * @{
AnnaBridge 171:3a7713b1edbc 710 */
AnnaBridge 171:3a7713b1edbc 711 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
AnnaBridge 171:3a7713b1edbc 712 ((CHANNEL) == DMA_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 713 ((CHANNEL) == DMA_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 714 ((CHANNEL) == DMA_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 715 ((CHANNEL) == DMA_CHANNEL_4) || \
AnnaBridge 171:3a7713b1edbc 716 ((CHANNEL) == DMA_CHANNEL_5) || \
AnnaBridge 171:3a7713b1edbc 717 ((CHANNEL) == DMA_CHANNEL_6) || \
AnnaBridge 171:3a7713b1edbc 718 ((CHANNEL) == DMA_CHANNEL_7))
AnnaBridge 171:3a7713b1edbc 719
AnnaBridge 171:3a7713b1edbc 720 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
AnnaBridge 171:3a7713b1edbc 721 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
AnnaBridge 171:3a7713b1edbc 722 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
AnnaBridge 171:3a7713b1edbc 723
AnnaBridge 171:3a7713b1edbc 724 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
AnnaBridge 171:3a7713b1edbc 725
AnnaBridge 171:3a7713b1edbc 726 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 727 ((STATE) == DMA_PINC_DISABLE))
AnnaBridge 171:3a7713b1edbc 728
AnnaBridge 171:3a7713b1edbc 729 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 730 ((STATE) == DMA_MINC_DISABLE))
AnnaBridge 171:3a7713b1edbc 731
AnnaBridge 171:3a7713b1edbc 732 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
AnnaBridge 171:3a7713b1edbc 733 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
AnnaBridge 171:3a7713b1edbc 734 ((SIZE) == DMA_PDATAALIGN_WORD))
AnnaBridge 171:3a7713b1edbc 735
AnnaBridge 171:3a7713b1edbc 736 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
AnnaBridge 171:3a7713b1edbc 737 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
AnnaBridge 171:3a7713b1edbc 738 ((SIZE) == DMA_MDATAALIGN_WORD ))
AnnaBridge 171:3a7713b1edbc 739
AnnaBridge 171:3a7713b1edbc 740 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
AnnaBridge 171:3a7713b1edbc 741 ((MODE) == DMA_CIRCULAR) || \
AnnaBridge 171:3a7713b1edbc 742 ((MODE) == DMA_PFCTRL))
AnnaBridge 171:3a7713b1edbc 743
AnnaBridge 171:3a7713b1edbc 744 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
AnnaBridge 171:3a7713b1edbc 745 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
AnnaBridge 171:3a7713b1edbc 746 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
AnnaBridge 171:3a7713b1edbc 747 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
AnnaBridge 171:3a7713b1edbc 748
AnnaBridge 171:3a7713b1edbc 749 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
AnnaBridge 171:3a7713b1edbc 750 ((STATE) == DMA_FIFOMODE_ENABLE))
AnnaBridge 171:3a7713b1edbc 751
AnnaBridge 171:3a7713b1edbc 752 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
AnnaBridge 171:3a7713b1edbc 753 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
AnnaBridge 171:3a7713b1edbc 754 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
AnnaBridge 171:3a7713b1edbc 755 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
AnnaBridge 171:3a7713b1edbc 756
AnnaBridge 171:3a7713b1edbc 757 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
AnnaBridge 171:3a7713b1edbc 758 ((BURST) == DMA_MBURST_INC4) || \
AnnaBridge 171:3a7713b1edbc 759 ((BURST) == DMA_MBURST_INC8) || \
AnnaBridge 171:3a7713b1edbc 760 ((BURST) == DMA_MBURST_INC16))
AnnaBridge 171:3a7713b1edbc 761
AnnaBridge 171:3a7713b1edbc 762 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
AnnaBridge 171:3a7713b1edbc 763 ((BURST) == DMA_PBURST_INC4) || \
AnnaBridge 171:3a7713b1edbc 764 ((BURST) == DMA_PBURST_INC8) || \
AnnaBridge 171:3a7713b1edbc 765 ((BURST) == DMA_PBURST_INC16))
AnnaBridge 171:3a7713b1edbc 766 /**
AnnaBridge 171:3a7713b1edbc 767 * @}
AnnaBridge 171:3a7713b1edbc 768 */
AnnaBridge 171:3a7713b1edbc 769
AnnaBridge 171:3a7713b1edbc 770 /* Private functions ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 771 /** @defgroup DMA_Private_Functions DMA Private Functions
AnnaBridge 171:3a7713b1edbc 772 * @brief DMA private functions
AnnaBridge 171:3a7713b1edbc 773 * @{
AnnaBridge 171:3a7713b1edbc 774 */
AnnaBridge 171:3a7713b1edbc 775 /**
AnnaBridge 171:3a7713b1edbc 776 * @}
AnnaBridge 171:3a7713b1edbc 777 */
AnnaBridge 171:3a7713b1edbc 778
AnnaBridge 171:3a7713b1edbc 779 /**
AnnaBridge 171:3a7713b1edbc 780 * @}
AnnaBridge 171:3a7713b1edbc 781 */
AnnaBridge 171:3a7713b1edbc 782
AnnaBridge 171:3a7713b1edbc 783 /**
AnnaBridge 171:3a7713b1edbc 784 * @}
AnnaBridge 171:3a7713b1edbc 785 */
AnnaBridge 171:3a7713b1edbc 786
AnnaBridge 171:3a7713b1edbc 787 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 788 }
AnnaBridge 171:3a7713b1edbc 789 #endif
AnnaBridge 171:3a7713b1edbc 790
AnnaBridge 171:3a7713b1edbc 791 #endif /* __STM32F2xx_HAL_DMA_H */
AnnaBridge 171:3a7713b1edbc 792
AnnaBridge 171:3a7713b1edbc 793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/