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TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f1xx_ll_i2c.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_NUCLEO_F103RB/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h@170:e95d10626187

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	143:86740a56073b	1	/**
AnnaBridge	143:86740a56073b	2	******************************************************************************
AnnaBridge	143:86740a56073b	3	* @file stm32f1xx_ll_i2c.h
AnnaBridge	143:86740a56073b	4	* @author MCD Application Team
AnnaBridge	143:86740a56073b	5	* @brief Header file of I2C LL module.
AnnaBridge	143:86740a56073b	6	******************************************************************************
AnnaBridge	143:86740a56073b	7	* @attention
AnnaBridge	143:86740a56073b	8	*
AnnaBridge	143:86740a56073b	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	143:86740a56073b	10	*
AnnaBridge	143:86740a56073b	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	143:86740a56073b	12	* are permitted provided that the following conditions are met:
AnnaBridge	143:86740a56073b	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	143:86740a56073b	14	* this list of conditions and the following disclaimer.
AnnaBridge	143:86740a56073b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	143:86740a56073b	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	143:86740a56073b	17	* and/or other materials provided with the distribution.
AnnaBridge	143:86740a56073b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	143:86740a56073b	19	* may be used to endorse or promote products derived from this software
AnnaBridge	143:86740a56073b	20	* without specific prior written permission.
AnnaBridge	143:86740a56073b	21	*
AnnaBridge	143:86740a56073b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	143:86740a56073b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	143:86740a56073b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	143:86740a56073b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	143:86740a56073b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	143:86740a56073b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	143:86740a56073b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	143:86740a56073b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	143:86740a56073b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	143:86740a56073b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	143:86740a56073b	32	*
AnnaBridge	143:86740a56073b	33	******************************************************************************
AnnaBridge	143:86740a56073b	34	*/
AnnaBridge	143:86740a56073b	35
AnnaBridge	143:86740a56073b	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	143:86740a56073b	37	#ifndef __STM32F1xx_LL_I2C_H
AnnaBridge	143:86740a56073b	38	#define __STM32F1xx_LL_I2C_H
AnnaBridge	143:86740a56073b	39
AnnaBridge	143:86740a56073b	40	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	41	extern "C" {
AnnaBridge	143:86740a56073b	42	#endif
AnnaBridge	143:86740a56073b	43
AnnaBridge	143:86740a56073b	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	45	#include "stm32f1xx.h"
AnnaBridge	143:86740a56073b	46
AnnaBridge	143:86740a56073b	47	/** @addtogroup STM32F1xx_LL_Driver
AnnaBridge	143:86740a56073b	48	* @{
AnnaBridge	143:86740a56073b	49	*/
AnnaBridge	143:86740a56073b	50
AnnaBridge	143:86740a56073b	51	#if defined (I2C1) \|\| defined (I2C2)
AnnaBridge	143:86740a56073b	52
AnnaBridge	143:86740a56073b	53	/** @defgroup I2C_LL I2C
AnnaBridge	143:86740a56073b	54	* @{
AnnaBridge	143:86740a56073b	55	*/
AnnaBridge	143:86740a56073b	56
AnnaBridge	143:86740a56073b	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	143:86740a56073b	59
AnnaBridge	143:86740a56073b	60	/* Private constants ---------------------------------------------------------*/
AnnaBridge	143:86740a56073b	61	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
AnnaBridge	143:86740a56073b	62	* @{
AnnaBridge	143:86740a56073b	63	*/
AnnaBridge	143:86740a56073b	64
AnnaBridge	143:86740a56073b	65	/* Defines used to perform compute and check in the macros */
AnnaBridge	143:86740a56073b	66	#define LL_I2C_MAX_SPEED_STANDARD 100000U
AnnaBridge	143:86740a56073b	67	#define LL_I2C_MAX_SPEED_FAST 400000U
AnnaBridge	143:86740a56073b	68	/**
AnnaBridge	143:86740a56073b	69	* @}
AnnaBridge	143:86740a56073b	70	*/
AnnaBridge	143:86740a56073b	71
AnnaBridge	143:86740a56073b	72	/* Private macros ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	73	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	74	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
AnnaBridge	143:86740a56073b	75	* @{
AnnaBridge	143:86740a56073b	76	*/
AnnaBridge	143:86740a56073b	77	/**
AnnaBridge	143:86740a56073b	78	* @}
AnnaBridge	143:86740a56073b	79	*/
AnnaBridge	143:86740a56073b	80	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	143:86740a56073b	81
AnnaBridge	143:86740a56073b	82	/* Exported types ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	83	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	84	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
AnnaBridge	143:86740a56073b	85	* @{
AnnaBridge	143:86740a56073b	86	*/
AnnaBridge	143:86740a56073b	87	typedef struct
AnnaBridge	143:86740a56073b	88	{
AnnaBridge	143:86740a56073b	89	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
AnnaBridge	143:86740a56073b	90	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
AnnaBridge	143:86740a56073b	91
AnnaBridge	143:86740a56073b	92	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
AnnaBridge	143:86740a56073b	93
AnnaBridge	143:86740a56073b	94	uint32_t ClockSpeed; /*!< Specifies the clock frequency.
AnnaBridge	143:86740a56073b	95	This parameter must be set to a value lower than 400kHz (in Hz)
AnnaBridge	143:86740a56073b	96
AnnaBridge	143:86740a56073b	97	This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
AnnaBridge	143:86740a56073b	98	or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
AnnaBridge	143:86740a56073b	99
AnnaBridge	143:86740a56073b	100	uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
AnnaBridge	143:86740a56073b	101	This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
AnnaBridge	143:86740a56073b	102
AnnaBridge	143:86740a56073b	103	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
AnnaBridge	143:86740a56073b	104
AnnaBridge	143:86740a56073b	105	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
AnnaBridge	143:86740a56073b	106	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
AnnaBridge	143:86740a56073b	107
AnnaBridge	143:86740a56073b	108	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge	143:86740a56073b	109
AnnaBridge	143:86740a56073b	110	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge	143:86740a56073b	111	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
AnnaBridge	143:86740a56073b	112
AnnaBridge	143:86740a56073b	113	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
AnnaBridge	143:86740a56073b	114
AnnaBridge	143:86740a56073b	115	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
AnnaBridge	143:86740a56073b	116	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
AnnaBridge	143:86740a56073b	117
AnnaBridge	143:86740a56073b	118	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge	143:86740a56073b	119	} LL_I2C_InitTypeDef;
AnnaBridge	143:86740a56073b	120	/**
AnnaBridge	143:86740a56073b	121	* @}
AnnaBridge	143:86740a56073b	122	*/
AnnaBridge	143:86740a56073b	123	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	143:86740a56073b	124
AnnaBridge	143:86740a56073b	125	/* Exported constants --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	126	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
AnnaBridge	143:86740a56073b	127	* @{
AnnaBridge	143:86740a56073b	128	*/
AnnaBridge	143:86740a56073b	129
AnnaBridge	143:86740a56073b	130	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	143:86740a56073b	131	* @brief Flags defines which can be used with LL_I2C_ReadReg function
AnnaBridge	143:86740a56073b	132	* @{
AnnaBridge	143:86740a56073b	133	*/
AnnaBridge	143:86740a56073b	134	#define LL_I2C_SR1_SB I2C_SR1_SB /!< Start Bit (master mode) /
AnnaBridge	143:86740a56073b	135	#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
AnnaBridge	143:86740a56073b	136	Address matched flag (slave mode) */
AnnaBridge	143:86740a56073b	137	#define LL_I2C_SR1_BTF I2C_SR1_BTF /!< Byte Transfer Finished flag /
AnnaBridge	143:86740a56073b	138	#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /!< 10-bit header sent (master mode) /
AnnaBridge	143:86740a56073b	139	#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /!< Stop detection flag (slave mode) /
AnnaBridge	143:86740a56073b	140	#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /!< Data register not empty (receivers) /
AnnaBridge	143:86740a56073b	141	#define LL_I2C_SR1_TXE I2C_SR1_TXE /!< Data register empty (transmitters) /
AnnaBridge	143:86740a56073b	142	#define LL_I2C_SR1_BERR I2C_SR1_BERR /!< Bus error /
AnnaBridge	143:86740a56073b	143	#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /!< Arbitration lost /
AnnaBridge	143:86740a56073b	144	#define LL_I2C_SR1_AF I2C_SR1_AF /!< Acknowledge failure flag /
AnnaBridge	143:86740a56073b	145	#define LL_I2C_SR1_OVR I2C_SR1_OVR /!< Overrun/Underrun /
AnnaBridge	143:86740a56073b	146	#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
AnnaBridge	143:86740a56073b	147	#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
AnnaBridge	143:86740a56073b	148	#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /!< SMBus alert (SMBus mode) /
AnnaBridge	143:86740a56073b	149	#define LL_I2C_SR2_MSL I2C_SR2_MSL /!< Master/Slave flag /
AnnaBridge	143:86740a56073b	150	#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /!< Bus busy flag /
AnnaBridge	143:86740a56073b	151	#define LL_I2C_SR2_TRA I2C_SR2_TRA /!< Transmitter/receiver direction /
AnnaBridge	143:86740a56073b	152	#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /!< General call address (Slave mode) /
AnnaBridge	143:86740a56073b	153	#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /!< SMBus Device default address (Slave mode) /
AnnaBridge	143:86740a56073b	154	#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /!< SMBus Host address (Slave mode) /
AnnaBridge	143:86740a56073b	155	#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /!< Dual flag (Slave mode) /
AnnaBridge	143:86740a56073b	156	/**
AnnaBridge	143:86740a56073b	157	* @}
AnnaBridge	143:86740a56073b	158	*/
AnnaBridge	143:86740a56073b	159
AnnaBridge	143:86740a56073b	160	/** @defgroup I2C_LL_EC_IT IT Defines
AnnaBridge	143:86740a56073b	161	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
AnnaBridge	143:86740a56073b	162	* @{
AnnaBridge	143:86740a56073b	163	*/
AnnaBridge	143:86740a56073b	164	#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /!< Events interrupts enable /
AnnaBridge	143:86740a56073b	165	#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /!< Buffer interrupts enable /
AnnaBridge	143:86740a56073b	166	#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /!< Error interrupts enable /
AnnaBridge	143:86740a56073b	167	/**
AnnaBridge	143:86740a56073b	168	* @}
AnnaBridge	143:86740a56073b	169	*/
AnnaBridge	143:86740a56073b	170
AnnaBridge	143:86740a56073b	171	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
AnnaBridge	143:86740a56073b	172	* @{
AnnaBridge	143:86740a56073b	173	*/
AnnaBridge	143:86740a56073b	174	#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /!< Own address 1 is a 7-bit address. /
AnnaBridge	143:86740a56073b	175	#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE \| 0x00004000U) /!< Own address 1 is a 10-bit address. /
AnnaBridge	143:86740a56073b	176	/**
AnnaBridge	143:86740a56073b	177	* @}
AnnaBridge	143:86740a56073b	178	*/
AnnaBridge	143:86740a56073b	179
AnnaBridge	143:86740a56073b	180	/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
AnnaBridge	143:86740a56073b	181	* @{
AnnaBridge	143:86740a56073b	182	*/
AnnaBridge	143:86740a56073b	183	#define LL_I2C_DUTYCYCLE_2 0x00000000U /!< I2C fast mode Tlow/Thigh = 2 /
AnnaBridge	143:86740a56073b	184	#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /!< I2C fast mode Tlow/Thigh = 16/9 /
AnnaBridge	143:86740a56073b	185	/**
AnnaBridge	143:86740a56073b	186	* @}
AnnaBridge	143:86740a56073b	187	*/
AnnaBridge	143:86740a56073b	188
AnnaBridge	143:86740a56073b	189	/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
AnnaBridge	143:86740a56073b	190	* @{
AnnaBridge	143:86740a56073b	191	*/
AnnaBridge	143:86740a56073b	192	#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /!< Master clock speed range is standard mode /
AnnaBridge	143:86740a56073b	193	#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /!< Master clock speed range is fast mode /
AnnaBridge	143:86740a56073b	194	/**
AnnaBridge	143:86740a56073b	195	* @}
AnnaBridge	143:86740a56073b	196	*/
AnnaBridge	143:86740a56073b	197
AnnaBridge	143:86740a56073b	198	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
AnnaBridge	143:86740a56073b	199	* @{
AnnaBridge	143:86740a56073b	200	*/
AnnaBridge	143:86740a56073b	201	#define LL_I2C_MODE_I2C 0x00000000U /!< I2C Master or Slave mode /
AnnaBridge	143:86740a56073b	202	#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP) /!< SMBus Host address acknowledge /
AnnaBridge	143:86740a56073b	203	#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /!< SMBus Device default mode (Default address not acknowledge) /
AnnaBridge	143:86740a56073b	204	#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_ENARP) /!< SMBus Device Default address acknowledge /
AnnaBridge	143:86740a56073b	205	/**
AnnaBridge	143:86740a56073b	206	* @}
AnnaBridge	143:86740a56073b	207	*/
AnnaBridge	143:86740a56073b	208
AnnaBridge	143:86740a56073b	209	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
AnnaBridge	143:86740a56073b	210	* @{
AnnaBridge	143:86740a56073b	211	*/
AnnaBridge	143:86740a56073b	212	#define LL_I2C_ACK I2C_CR1_ACK /!< ACK is sent after current received byte. /
AnnaBridge	143:86740a56073b	213	#define LL_I2C_NACK 0x00000000U /!< NACK is sent after current received byte./
AnnaBridge	143:86740a56073b	214	/**
AnnaBridge	143:86740a56073b	215	* @}
AnnaBridge	143:86740a56073b	216	*/
AnnaBridge	143:86740a56073b	217
AnnaBridge	143:86740a56073b	218	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
AnnaBridge	143:86740a56073b	219	* @{
AnnaBridge	143:86740a56073b	220	*/
AnnaBridge	143:86740a56073b	221	#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /!< Bus is in write transfer /
AnnaBridge	143:86740a56073b	222	#define LL_I2C_DIRECTION_READ 0x00000000U /!< Bus is in read transfer /
AnnaBridge	143:86740a56073b	223	/**
AnnaBridge	143:86740a56073b	224	* @}
AnnaBridge	143:86740a56073b	225	*/
AnnaBridge	143:86740a56073b	226
AnnaBridge	143:86740a56073b	227	/**
AnnaBridge	143:86740a56073b	228	* @}
AnnaBridge	143:86740a56073b	229	*/
AnnaBridge	143:86740a56073b	230
AnnaBridge	143:86740a56073b	231	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	232	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
AnnaBridge	143:86740a56073b	233	* @{
AnnaBridge	143:86740a56073b	234	*/
AnnaBridge	143:86740a56073b	235
AnnaBridge	143:86740a56073b	236	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	143:86740a56073b	237	* @{
AnnaBridge	143:86740a56073b	238	*/
AnnaBridge	143:86740a56073b	239
AnnaBridge	143:86740a56073b	240	/**
AnnaBridge	143:86740a56073b	241	* @brief Write a value in I2C register
AnnaBridge	143:86740a56073b	242	* @param __INSTANCE__ I2C Instance
AnnaBridge	143:86740a56073b	243	* @param __REG__ Register to be written
AnnaBridge	143:86740a56073b	244	* @param __VALUE__ Value to be written in the register
AnnaBridge	143:86740a56073b	245	* @retval None
AnnaBridge	143:86740a56073b	246	*/
AnnaBridge	143:86740a56073b	247	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	143:86740a56073b	248
AnnaBridge	143:86740a56073b	249	/**
AnnaBridge	143:86740a56073b	250	* @brief Read a value in I2C register
AnnaBridge	143:86740a56073b	251	* @param __INSTANCE__ I2C Instance
AnnaBridge	143:86740a56073b	252	* @param __REG__ Register to be read
AnnaBridge	143:86740a56073b	253	* @retval Register value
AnnaBridge	143:86740a56073b	254	*/
AnnaBridge	143:86740a56073b	255	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	143:86740a56073b	256	/**
AnnaBridge	143:86740a56073b	257	* @}
AnnaBridge	143:86740a56073b	258	*/
AnnaBridge	143:86740a56073b	259
AnnaBridge	143:86740a56073b	260	/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
AnnaBridge	143:86740a56073b	261	* @{
AnnaBridge	143:86740a56073b	262	*/
AnnaBridge	143:86740a56073b	263
AnnaBridge	143:86740a56073b	264	/**
AnnaBridge	143:86740a56073b	265	* @brief Convert Peripheral Clock Frequency in Mhz.
AnnaBridge	143:86740a56073b	266	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	143:86740a56073b	267	* @retval Value of peripheral clock (in Mhz)
AnnaBridge	143:86740a56073b	268	*/
AnnaBridge	143:86740a56073b	269	#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
AnnaBridge	143:86740a56073b	270
AnnaBridge	143:86740a56073b	271	/**
AnnaBridge	143:86740a56073b	272	* @brief Convert Peripheral Clock Frequency in Hz.
AnnaBridge	143:86740a56073b	273	* @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge	143:86740a56073b	274	* @retval Value of peripheral clock (in Hz)
AnnaBridge	143:86740a56073b	275	*/
AnnaBridge	143:86740a56073b	276	#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
AnnaBridge	143:86740a56073b	277
AnnaBridge	143:86740a56073b	278	/**
AnnaBridge	143:86740a56073b	279	* @brief Compute I2C Clock rising time.
AnnaBridge	143:86740a56073b	280	* @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge	143:86740a56073b	281	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge	143:86740a56073b	282	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge	143:86740a56073b	283	*/
AnnaBridge	143:86740a56073b	284	#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
AnnaBridge	143:86740a56073b	285
AnnaBridge	143:86740a56073b	286	/**
AnnaBridge	143:86740a56073b	287	* @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge	143:86740a56073b	288	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	143:86740a56073b	289	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge	143:86740a56073b	290	* @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	291	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	143:86740a56073b	292	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	143:86740a56073b	293	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge	143:86740a56073b	294	*/
AnnaBridge	143:86740a56073b	295	#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
AnnaBridge	143:86740a56073b	296	(__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
AnnaBridge	143:86740a56073b	297	(__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
AnnaBridge	143:86740a56073b	298
AnnaBridge	143:86740a56073b	299	/**
AnnaBridge	143:86740a56073b	300	* @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge	143:86740a56073b	301	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	143:86740a56073b	302	* @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
AnnaBridge	143:86740a56073b	303	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
AnnaBridge	143:86740a56073b	304	*/
AnnaBridge	143:86740a56073b	305	#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
AnnaBridge	143:86740a56073b	306
AnnaBridge	143:86740a56073b	307	/**
AnnaBridge	143:86740a56073b	308	* @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge	143:86740a56073b	309	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	143:86740a56073b	310	* @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
AnnaBridge	143:86740a56073b	311	* @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	312	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	143:86740a56073b	313	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	143:86740a56073b	314	* @retval Value between Min_Data=0x001 and Max_Data=0xFFF
AnnaBridge	143:86740a56073b	315	*/
AnnaBridge	143:86740a56073b	316	#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
AnnaBridge	143:86740a56073b	317	(((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
AnnaBridge	143:86740a56073b	318	(((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
AnnaBridge	143:86740a56073b	319
AnnaBridge	143:86740a56073b	320	/**
AnnaBridge	143:86740a56073b	321	* @brief Get the Least significant bits of a 10-Bits address.
AnnaBridge	143:86740a56073b	322	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge	143:86740a56073b	323	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	143:86740a56073b	324	*/
AnnaBridge	143:86740a56073b	325	#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
AnnaBridge	143:86740a56073b	326
AnnaBridge	143:86740a56073b	327	/**
AnnaBridge	143:86740a56073b	328	* @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
AnnaBridge	143:86740a56073b	329	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge	143:86740a56073b	330	* @retval Value between Min_Data=0xF0 and Max_Data=0xF6
AnnaBridge	143:86740a56073b	331	*/
AnnaBridge	143:86740a56073b	332	#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF0))))
AnnaBridge	143:86740a56073b	333
AnnaBridge	143:86740a56073b	334	/**
AnnaBridge	143:86740a56073b	335	* @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
AnnaBridge	143:86740a56073b	336	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge	143:86740a56073b	337	* @retval Value between Min_Data=0xF1 and Max_Data=0xF7
AnnaBridge	143:86740a56073b	338	*/
AnnaBridge	143:86740a56073b	339	#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF1))))
AnnaBridge	143:86740a56073b	340
AnnaBridge	143:86740a56073b	341	/**
AnnaBridge	143:86740a56073b	342	* @}
AnnaBridge	143:86740a56073b	343	*/
AnnaBridge	143:86740a56073b	344
AnnaBridge	143:86740a56073b	345	/**
AnnaBridge	143:86740a56073b	346	* @}
AnnaBridge	143:86740a56073b	347	*/
AnnaBridge	143:86740a56073b	348
AnnaBridge	143:86740a56073b	349	/* Exported functions --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	350
AnnaBridge	143:86740a56073b	351	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
AnnaBridge	143:86740a56073b	352	* @{
AnnaBridge	143:86740a56073b	353	*/
AnnaBridge	143:86740a56073b	354
AnnaBridge	143:86740a56073b	355	/** @defgroup I2C_LL_EF_Configuration Configuration
AnnaBridge	143:86740a56073b	356	* @{
AnnaBridge	143:86740a56073b	357	*/
AnnaBridge	143:86740a56073b	358
AnnaBridge	143:86740a56073b	359	/**
AnnaBridge	143:86740a56073b	360	* @brief Enable I2C peripheral (PE = 1).
AnnaBridge	143:86740a56073b	361	* @rmtoll CR1 PE LL_I2C_Enable
AnnaBridge	143:86740a56073b	362	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	363	* @retval None
AnnaBridge	143:86740a56073b	364	*/
AnnaBridge	143:86740a56073b	365	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	366	{
AnnaBridge	143:86740a56073b	367	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge	143:86740a56073b	368	}
AnnaBridge	143:86740a56073b	369
AnnaBridge	143:86740a56073b	370	/**
AnnaBridge	143:86740a56073b	371	* @brief Disable I2C peripheral (PE = 0).
AnnaBridge	143:86740a56073b	372	* @rmtoll CR1 PE LL_I2C_Disable
AnnaBridge	143:86740a56073b	373	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	374	* @retval None
AnnaBridge	143:86740a56073b	375	*/
AnnaBridge	143:86740a56073b	376	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	377	{
AnnaBridge	143:86740a56073b	378	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge	143:86740a56073b	379	}
AnnaBridge	143:86740a56073b	380
AnnaBridge	143:86740a56073b	381	/**
AnnaBridge	143:86740a56073b	382	* @brief Check if the I2C peripheral is enabled or disabled.
AnnaBridge	143:86740a56073b	383	* @rmtoll CR1 PE LL_I2C_IsEnabled
AnnaBridge	143:86740a56073b	384	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	385	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	386	*/
AnnaBridge	143:86740a56073b	387	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	388	{
AnnaBridge	143:86740a56073b	389	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
AnnaBridge	143:86740a56073b	390	}
AnnaBridge	143:86740a56073b	391
AnnaBridge	143:86740a56073b	392
AnnaBridge	143:86740a56073b	393	/**
AnnaBridge	143:86740a56073b	394	* @brief Enable DMA transmission requests.
AnnaBridge	143:86740a56073b	395	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
AnnaBridge	143:86740a56073b	396	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	397	* @retval None
AnnaBridge	143:86740a56073b	398	*/
AnnaBridge	143:86740a56073b	399	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	400	{
AnnaBridge	143:86740a56073b	401	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	143:86740a56073b	402	}
AnnaBridge	143:86740a56073b	403
AnnaBridge	143:86740a56073b	404	/**
AnnaBridge	143:86740a56073b	405	* @brief Disable DMA transmission requests.
AnnaBridge	143:86740a56073b	406	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
AnnaBridge	143:86740a56073b	407	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	408	* @retval None
AnnaBridge	143:86740a56073b	409	*/
AnnaBridge	143:86740a56073b	410	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	411	{
AnnaBridge	143:86740a56073b	412	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	143:86740a56073b	413	}
AnnaBridge	143:86740a56073b	414
AnnaBridge	143:86740a56073b	415	/**
AnnaBridge	143:86740a56073b	416	* @brief Check if DMA transmission requests are enabled or disabled.
AnnaBridge	143:86740a56073b	417	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
AnnaBridge	143:86740a56073b	418	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	419	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	420	*/
AnnaBridge	143:86740a56073b	421	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	422	{
AnnaBridge	143:86740a56073b	423	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge	143:86740a56073b	424	}
AnnaBridge	143:86740a56073b	425
AnnaBridge	143:86740a56073b	426	/**
AnnaBridge	143:86740a56073b	427	* @brief Enable DMA reception requests.
AnnaBridge	143:86740a56073b	428	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
AnnaBridge	143:86740a56073b	429	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	430	* @retval None
AnnaBridge	143:86740a56073b	431	*/
AnnaBridge	143:86740a56073b	432	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	433	{
AnnaBridge	143:86740a56073b	434	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	143:86740a56073b	435	}
AnnaBridge	143:86740a56073b	436
AnnaBridge	143:86740a56073b	437	/**
AnnaBridge	143:86740a56073b	438	* @brief Disable DMA reception requests.
AnnaBridge	143:86740a56073b	439	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
AnnaBridge	143:86740a56073b	440	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	441	* @retval None
AnnaBridge	143:86740a56073b	442	*/
AnnaBridge	143:86740a56073b	443	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	444	{
AnnaBridge	143:86740a56073b	445	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	143:86740a56073b	446	}
AnnaBridge	143:86740a56073b	447
AnnaBridge	143:86740a56073b	448	/**
AnnaBridge	143:86740a56073b	449	* @brief Check if DMA reception requests are enabled or disabled.
AnnaBridge	143:86740a56073b	450	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
AnnaBridge	143:86740a56073b	451	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	452	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	453	*/
AnnaBridge	143:86740a56073b	454	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	455	{
AnnaBridge	143:86740a56073b	456	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge	143:86740a56073b	457	}
AnnaBridge	143:86740a56073b	458
AnnaBridge	143:86740a56073b	459	/**
AnnaBridge	143:86740a56073b	460	* @brief Get the data register address used for DMA transfer.
AnnaBridge	143:86740a56073b	461	* @rmtoll DR DR LL_I2C_DMA_GetRegAddr
AnnaBridge	143:86740a56073b	462	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	463	* @retval Address of data register
AnnaBridge	143:86740a56073b	464	*/
AnnaBridge	143:86740a56073b	465	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	466	{
AnnaBridge	143:86740a56073b	467	return (uint32_t) & (I2Cx->DR);
AnnaBridge	143:86740a56073b	468	}
AnnaBridge	143:86740a56073b	469
AnnaBridge	143:86740a56073b	470	/**
AnnaBridge	143:86740a56073b	471	* @brief Enable Clock stretching.
AnnaBridge	143:86740a56073b	472	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	143:86740a56073b	473	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
AnnaBridge	143:86740a56073b	474	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	475	* @retval None
AnnaBridge	143:86740a56073b	476	*/
AnnaBridge	143:86740a56073b	477	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	478	{
AnnaBridge	143:86740a56073b	479	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge	143:86740a56073b	480	}
AnnaBridge	143:86740a56073b	481
AnnaBridge	143:86740a56073b	482	/**
AnnaBridge	143:86740a56073b	483	* @brief Disable Clock stretching.
AnnaBridge	143:86740a56073b	484	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	143:86740a56073b	485	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
AnnaBridge	143:86740a56073b	486	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	487	* @retval None
AnnaBridge	143:86740a56073b	488	*/
AnnaBridge	143:86740a56073b	489	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	490	{
AnnaBridge	143:86740a56073b	491	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge	143:86740a56073b	492	}
AnnaBridge	143:86740a56073b	493
AnnaBridge	143:86740a56073b	494	/**
AnnaBridge	143:86740a56073b	495	* @brief Check if Clock stretching is enabled or disabled.
AnnaBridge	143:86740a56073b	496	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
AnnaBridge	143:86740a56073b	497	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	498	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	499	*/
AnnaBridge	143:86740a56073b	500	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	501	{
AnnaBridge	143:86740a56073b	502	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
AnnaBridge	143:86740a56073b	503	}
AnnaBridge	143:86740a56073b	504
AnnaBridge	143:86740a56073b	505	/**
AnnaBridge	143:86740a56073b	506	* @brief Enable General Call.
AnnaBridge	143:86740a56073b	507	* @note When enabled the Address 0x00 is ACKed.
AnnaBridge	143:86740a56073b	508	* @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
AnnaBridge	143:86740a56073b	509	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	510	* @retval None
AnnaBridge	143:86740a56073b	511	*/
AnnaBridge	143:86740a56073b	512	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	513	{
AnnaBridge	143:86740a56073b	514	SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge	143:86740a56073b	515	}
AnnaBridge	143:86740a56073b	516
AnnaBridge	143:86740a56073b	517	/**
AnnaBridge	143:86740a56073b	518	* @brief Disable General Call.
AnnaBridge	143:86740a56073b	519	* @note When disabled the Address 0x00 is NACKed.
AnnaBridge	143:86740a56073b	520	* @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
AnnaBridge	143:86740a56073b	521	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	522	* @retval None
AnnaBridge	143:86740a56073b	523	*/
AnnaBridge	143:86740a56073b	524	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	525	{
AnnaBridge	143:86740a56073b	526	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge	143:86740a56073b	527	}
AnnaBridge	143:86740a56073b	528
AnnaBridge	143:86740a56073b	529	/**
AnnaBridge	143:86740a56073b	530	* @brief Check if General Call is enabled or disabled.
AnnaBridge	143:86740a56073b	531	* @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
AnnaBridge	143:86740a56073b	532	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	533	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	534	*/
AnnaBridge	143:86740a56073b	535	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	536	{
AnnaBridge	143:86740a56073b	537	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
AnnaBridge	143:86740a56073b	538	}
AnnaBridge	143:86740a56073b	539
AnnaBridge	143:86740a56073b	540	/**
AnnaBridge	143:86740a56073b	541	* @brief Set the Own Address1.
AnnaBridge	143:86740a56073b	542	* @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
AnnaBridge	143:86740a56073b	543	* OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
AnnaBridge	143:86740a56073b	544	* OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
AnnaBridge	143:86740a56073b	545	* OAR1 ADDMODE LL_I2C_SetOwnAddress1
AnnaBridge	143:86740a56073b	546	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	547	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
AnnaBridge	143:86740a56073b	548	* @param OwnAddrSize This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	549	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
AnnaBridge	143:86740a56073b	550	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
AnnaBridge	143:86740a56073b	551	* @retval None
AnnaBridge	143:86740a56073b	552	*/
AnnaBridge	143:86740a56073b	553	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
AnnaBridge	143:86740a56073b	554	{
AnnaBridge	143:86740a56073b	555	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 \| I2C_OAR1_ADD1_7 \| I2C_OAR1_ADD8_9 \| I2C_OAR1_ADDMODE, OwnAddress1 \| OwnAddrSize);
AnnaBridge	143:86740a56073b	556	}
AnnaBridge	143:86740a56073b	557
AnnaBridge	143:86740a56073b	558	/**
AnnaBridge	143:86740a56073b	559	* @brief Set the 7bits Own Address2.
AnnaBridge	143:86740a56073b	560	* @note This action has no effect if own address2 is enabled.
AnnaBridge	143:86740a56073b	561	* @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
AnnaBridge	143:86740a56073b	562	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	563	* @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
AnnaBridge	143:86740a56073b	564	* @retval None
AnnaBridge	143:86740a56073b	565	*/
AnnaBridge	143:86740a56073b	566	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
AnnaBridge	143:86740a56073b	567	{
AnnaBridge	143:86740a56073b	568	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
AnnaBridge	143:86740a56073b	569	}
AnnaBridge	143:86740a56073b	570
AnnaBridge	143:86740a56073b	571	/**
AnnaBridge	143:86740a56073b	572	* @brief Enable acknowledge on Own Address2 match address.
AnnaBridge	143:86740a56073b	573	* @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
AnnaBridge	143:86740a56073b	574	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	575	* @retval None
AnnaBridge	143:86740a56073b	576	*/
AnnaBridge	143:86740a56073b	577	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	578	{
AnnaBridge	143:86740a56073b	579	SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge	143:86740a56073b	580	}
AnnaBridge	143:86740a56073b	581
AnnaBridge	143:86740a56073b	582	/**
AnnaBridge	143:86740a56073b	583	* @brief Disable acknowledge on Own Address2 match address.
AnnaBridge	143:86740a56073b	584	* @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
AnnaBridge	143:86740a56073b	585	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	586	* @retval None
AnnaBridge	143:86740a56073b	587	*/
AnnaBridge	143:86740a56073b	588	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	589	{
AnnaBridge	143:86740a56073b	590	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge	143:86740a56073b	591	}
AnnaBridge	143:86740a56073b	592
AnnaBridge	143:86740a56073b	593	/**
AnnaBridge	143:86740a56073b	594	* @brief Check if Own Address1 acknowledge is enabled or disabled.
AnnaBridge	143:86740a56073b	595	* @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
AnnaBridge	143:86740a56073b	596	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	597	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	598	*/
AnnaBridge	143:86740a56073b	599	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	600	{
AnnaBridge	143:86740a56073b	601	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
AnnaBridge	143:86740a56073b	602	}
AnnaBridge	143:86740a56073b	603
AnnaBridge	143:86740a56073b	604	/**
AnnaBridge	143:86740a56073b	605	* @brief Configure the Peripheral clock frequency.
AnnaBridge	143:86740a56073b	606	* @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
AnnaBridge	143:86740a56073b	607	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	608	* @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge	143:86740a56073b	609	* @retval None
AnnaBridge	143:86740a56073b	610	*/
AnnaBridge	143:86740a56073b	611	__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
AnnaBridge	143:86740a56073b	612	{
AnnaBridge	143:86740a56073b	613	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
AnnaBridge	143:86740a56073b	614	}
AnnaBridge	143:86740a56073b	615
AnnaBridge	143:86740a56073b	616	/**
AnnaBridge	143:86740a56073b	617	* @brief Get the Peripheral clock frequency.
AnnaBridge	143:86740a56073b	618	* @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
AnnaBridge	143:86740a56073b	619	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	620	* @retval Value of Peripheral Clock (in Hz)
AnnaBridge	143:86740a56073b	621	*/
AnnaBridge	143:86740a56073b	622	__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	623	{
AnnaBridge	143:86740a56073b	624	return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
AnnaBridge	143:86740a56073b	625	}
AnnaBridge	143:86740a56073b	626
AnnaBridge	143:86740a56073b	627	/**
AnnaBridge	143:86740a56073b	628	* @brief Configure the Duty cycle (Fast mode only).
AnnaBridge	143:86740a56073b	629	* @rmtoll CCR DUTY LL_I2C_SetDutyCycle
AnnaBridge	143:86740a56073b	630	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	631	* @param DutyCycle This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	632	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	143:86740a56073b	633	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	143:86740a56073b	634	* @retval None
AnnaBridge	143:86740a56073b	635	*/
AnnaBridge	143:86740a56073b	636	__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
AnnaBridge	143:86740a56073b	637	{
AnnaBridge	143:86740a56073b	638	MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
AnnaBridge	143:86740a56073b	639	}
AnnaBridge	143:86740a56073b	640
AnnaBridge	143:86740a56073b	641	/**
AnnaBridge	143:86740a56073b	642	* @brief Get the Duty cycle (Fast mode only).
AnnaBridge	143:86740a56073b	643	* @rmtoll CCR DUTY LL_I2C_GetDutyCycle
AnnaBridge	143:86740a56073b	644	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	645	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	646	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	143:86740a56073b	647	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	143:86740a56073b	648	*/
AnnaBridge	143:86740a56073b	649	__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	650	{
AnnaBridge	143:86740a56073b	651	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
AnnaBridge	143:86740a56073b	652	}
AnnaBridge	143:86740a56073b	653
AnnaBridge	143:86740a56073b	654	/**
AnnaBridge	143:86740a56073b	655	* @brief Configure the I2C master clock speed mode.
AnnaBridge	143:86740a56073b	656	* @rmtoll CCR FS LL_I2C_SetClockSpeedMode
AnnaBridge	143:86740a56073b	657	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	658	* @param ClockSpeedMode This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	659	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge	143:86740a56073b	660	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge	143:86740a56073b	661	* @retval None
AnnaBridge	143:86740a56073b	662	*/
AnnaBridge	143:86740a56073b	663	__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
AnnaBridge	143:86740a56073b	664	{
AnnaBridge	143:86740a56073b	665	MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
AnnaBridge	143:86740a56073b	666	}
AnnaBridge	143:86740a56073b	667
AnnaBridge	143:86740a56073b	668	/**
AnnaBridge	143:86740a56073b	669	* @brief Get the the I2C master speed mode.
AnnaBridge	143:86740a56073b	670	* @rmtoll CCR FS LL_I2C_GetClockSpeedMode
AnnaBridge	143:86740a56073b	671	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	672	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	673	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge	143:86740a56073b	674	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge	143:86740a56073b	675	*/
AnnaBridge	143:86740a56073b	676	__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	677	{
AnnaBridge	143:86740a56073b	678	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
AnnaBridge	143:86740a56073b	679	}
AnnaBridge	143:86740a56073b	680
AnnaBridge	143:86740a56073b	681	/**
AnnaBridge	143:86740a56073b	682	* @brief Configure the SCL, SDA rising time.
AnnaBridge	143:86740a56073b	683	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	143:86740a56073b	684	* @rmtoll TRISE TRISE LL_I2C_SetRiseTime
AnnaBridge	143:86740a56073b	685	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	686	* @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
AnnaBridge	143:86740a56073b	687	* @retval None
AnnaBridge	143:86740a56073b	688	*/
AnnaBridge	143:86740a56073b	689	__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
AnnaBridge	143:86740a56073b	690	{
AnnaBridge	143:86740a56073b	691	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
AnnaBridge	143:86740a56073b	692	}
AnnaBridge	143:86740a56073b	693
AnnaBridge	143:86740a56073b	694	/**
AnnaBridge	143:86740a56073b	695	* @brief Get the SCL, SDA rising time.
AnnaBridge	143:86740a56073b	696	* @rmtoll TRISE TRISE LL_I2C_GetRiseTime
AnnaBridge	143:86740a56073b	697	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	698	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge	143:86740a56073b	699	*/
AnnaBridge	143:86740a56073b	700	__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	701	{
AnnaBridge	143:86740a56073b	702	return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
AnnaBridge	143:86740a56073b	703	}
AnnaBridge	143:86740a56073b	704
AnnaBridge	143:86740a56073b	705	/**
AnnaBridge	143:86740a56073b	706	* @brief Configure the SCL high and low period.
AnnaBridge	143:86740a56073b	707	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	143:86740a56073b	708	* @rmtoll CCR CCR LL_I2C_SetClockPeriod
AnnaBridge	143:86740a56073b	709	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	710	* @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge	143:86740a56073b	711	* @retval None
AnnaBridge	143:86740a56073b	712	*/
AnnaBridge	143:86740a56073b	713	__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
AnnaBridge	143:86740a56073b	714	{
AnnaBridge	143:86740a56073b	715	MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
AnnaBridge	143:86740a56073b	716	}
AnnaBridge	143:86740a56073b	717
AnnaBridge	143:86740a56073b	718	/**
AnnaBridge	143:86740a56073b	719	* @brief Get the SCL high and low period.
AnnaBridge	143:86740a56073b	720	* @rmtoll CCR CCR LL_I2C_GetClockPeriod
AnnaBridge	143:86740a56073b	721	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	722	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge	143:86740a56073b	723	*/
AnnaBridge	143:86740a56073b	724	__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	725	{
AnnaBridge	143:86740a56073b	726	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
AnnaBridge	143:86740a56073b	727	}
AnnaBridge	143:86740a56073b	728
AnnaBridge	143:86740a56073b	729	/**
AnnaBridge	143:86740a56073b	730	* @brief Configure the SCL speed.
AnnaBridge	143:86740a56073b	731	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	143:86740a56073b	732	* @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
AnnaBridge	143:86740a56073b	733	* TRISE TRISE LL_I2C_ConfigSpeed\n
AnnaBridge	143:86740a56073b	734	* CCR FS LL_I2C_ConfigSpeed\n
AnnaBridge	143:86740a56073b	735	* CCR DUTY LL_I2C_ConfigSpeed\n
AnnaBridge	143:86740a56073b	736	* CCR CCR LL_I2C_ConfigSpeed
AnnaBridge	143:86740a56073b	737	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	738	* @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge	143:86740a56073b	739	* @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge	143:86740a56073b	740	* @param DutyCycle This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	741	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	143:86740a56073b	742	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	143:86740a56073b	743	* @retval None
AnnaBridge	143:86740a56073b	744	*/
AnnaBridge	143:86740a56073b	745	__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
AnnaBridge	143:86740a56073b	746	uint32_t DutyCycle)
AnnaBridge	143:86740a56073b	747	{
AnnaBridge	143:86740a56073b	748	register uint32_t freqrange = 0x0U;
AnnaBridge	143:86740a56073b	749	register uint32_t clockconfig = 0x0U;
AnnaBridge	143:86740a56073b	750
AnnaBridge	143:86740a56073b	751	/* Compute frequency range */
AnnaBridge	143:86740a56073b	752	freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
AnnaBridge	143:86740a56073b	753
AnnaBridge	143:86740a56073b	754	/* Configure I2Cx: Frequency range register */
AnnaBridge	143:86740a56073b	755	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
AnnaBridge	143:86740a56073b	756
AnnaBridge	143:86740a56073b	757	/* Configure I2Cx: Rise Time register */
AnnaBridge	143:86740a56073b	758	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
AnnaBridge	143:86740a56073b	759
AnnaBridge	143:86740a56073b	760	/* Configure Speed mode, Duty Cycle and Clock control register value */
AnnaBridge	143:86740a56073b	761	if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
AnnaBridge	143:86740a56073b	762	{
AnnaBridge	143:86740a56073b	763	/* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
AnnaBridge	143:86740a56073b	764	clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE \| \
AnnaBridge	143:86740a56073b	765	__LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) \| \
AnnaBridge	143:86740a56073b	766	DutyCycle;
AnnaBridge	143:86740a56073b	767	}
AnnaBridge	143:86740a56073b	768	else
AnnaBridge	143:86740a56073b	769	{
AnnaBridge	143:86740a56073b	770	/* Set Speed mode at standard for Clock Speed request in standard clock range */
AnnaBridge	143:86740a56073b	771	clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE \| \
AnnaBridge	143:86740a56073b	772	__LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
AnnaBridge	143:86740a56073b	773	}
AnnaBridge	143:86740a56073b	774
AnnaBridge	143:86740a56073b	775	/* Configure I2Cx: Clock control register */
AnnaBridge	143:86740a56073b	776	MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS \| I2C_CCR_DUTY \| I2C_CCR_CCR), clockconfig);
AnnaBridge	143:86740a56073b	777	}
AnnaBridge	143:86740a56073b	778
AnnaBridge	143:86740a56073b	779	/**
AnnaBridge	143:86740a56073b	780	* @brief Configure peripheral mode.
AnnaBridge	143:86740a56073b	781	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	782	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	783	* @rmtoll CR1 SMBUS LL_I2C_SetMode\n
AnnaBridge	143:86740a56073b	784	* CR1 SMBTYPE LL_I2C_SetMode\n
AnnaBridge	143:86740a56073b	785	* CR1 ENARP LL_I2C_SetMode
AnnaBridge	143:86740a56073b	786	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	787	* @param PeripheralMode This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	788	* @arg @ref LL_I2C_MODE_I2C
AnnaBridge	143:86740a56073b	789	* @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge	143:86740a56073b	790	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge	143:86740a56073b	791	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge	143:86740a56073b	792	* @retval None
AnnaBridge	143:86740a56073b	793	*/
AnnaBridge	143:86740a56073b	794	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
AnnaBridge	143:86740a56073b	795	{
AnnaBridge	143:86740a56073b	796	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP, PeripheralMode);
AnnaBridge	143:86740a56073b	797	}
AnnaBridge	143:86740a56073b	798
AnnaBridge	143:86740a56073b	799	/**
AnnaBridge	143:86740a56073b	800	* @brief Get peripheral mode.
AnnaBridge	143:86740a56073b	801	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	802	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	803	* @rmtoll CR1 SMBUS LL_I2C_GetMode\n
AnnaBridge	143:86740a56073b	804	* CR1 SMBTYPE LL_I2C_GetMode\n
AnnaBridge	143:86740a56073b	805	* CR1 ENARP LL_I2C_GetMode
AnnaBridge	143:86740a56073b	806	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	807	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	808	* @arg @ref LL_I2C_MODE_I2C
AnnaBridge	143:86740a56073b	809	* @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge	143:86740a56073b	810	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge	143:86740a56073b	811	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge	143:86740a56073b	812	*/
AnnaBridge	143:86740a56073b	813	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	814	{
AnnaBridge	143:86740a56073b	815	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP));
AnnaBridge	143:86740a56073b	816	}
AnnaBridge	143:86740a56073b	817
AnnaBridge	143:86740a56073b	818	/**
AnnaBridge	143:86740a56073b	819	* @brief Enable SMBus alert (Host or Device mode)
AnnaBridge	143:86740a56073b	820	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	821	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	822	* @note SMBus Device mode:
AnnaBridge	143:86740a56073b	823	* - SMBus Alert pin is drived low and
AnnaBridge	143:86740a56073b	824	* Alert Response Address Header acknowledge is enabled.
AnnaBridge	143:86740a56073b	825	* SMBus Host mode:
AnnaBridge	143:86740a56073b	826	* - SMBus Alert pin management is supported.
AnnaBridge	143:86740a56073b	827	* @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
AnnaBridge	143:86740a56073b	828	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	829	* @retval None
AnnaBridge	143:86740a56073b	830	*/
AnnaBridge	143:86740a56073b	831	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	832	{
AnnaBridge	143:86740a56073b	833	SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge	143:86740a56073b	834	}
AnnaBridge	143:86740a56073b	835
AnnaBridge	143:86740a56073b	836	/**
AnnaBridge	143:86740a56073b	837	* @brief Disable SMBus alert (Host or Device mode)
AnnaBridge	143:86740a56073b	838	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	839	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	840	* @note SMBus Device mode:
AnnaBridge	143:86740a56073b	841	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
AnnaBridge	143:86740a56073b	842	* Alert Response Address Header acknowledge is disabled.
AnnaBridge	143:86740a56073b	843	* SMBus Host mode:
AnnaBridge	143:86740a56073b	844	* - SMBus Alert pin management is not supported.
AnnaBridge	143:86740a56073b	845	* @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
AnnaBridge	143:86740a56073b	846	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	847	* @retval None
AnnaBridge	143:86740a56073b	848	*/
AnnaBridge	143:86740a56073b	849	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	850	{
AnnaBridge	143:86740a56073b	851	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge	143:86740a56073b	852	}
AnnaBridge	143:86740a56073b	853
AnnaBridge	143:86740a56073b	854	/**
AnnaBridge	143:86740a56073b	855	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
AnnaBridge	143:86740a56073b	856	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	857	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	858	* @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
AnnaBridge	143:86740a56073b	859	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	860	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	861	*/
AnnaBridge	143:86740a56073b	862	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	863	{
AnnaBridge	143:86740a56073b	864	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
AnnaBridge	143:86740a56073b	865	}
AnnaBridge	143:86740a56073b	866
AnnaBridge	143:86740a56073b	867	/**
AnnaBridge	143:86740a56073b	868	* @brief Enable SMBus Packet Error Calculation (PEC).
AnnaBridge	143:86740a56073b	869	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	870	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	871	* @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
AnnaBridge	143:86740a56073b	872	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	873	* @retval None
AnnaBridge	143:86740a56073b	874	*/
AnnaBridge	143:86740a56073b	875	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	876	{
AnnaBridge	143:86740a56073b	877	SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge	143:86740a56073b	878	}
AnnaBridge	143:86740a56073b	879
AnnaBridge	143:86740a56073b	880	/**
AnnaBridge	143:86740a56073b	881	* @brief Disable SMBus Packet Error Calculation (PEC).
AnnaBridge	143:86740a56073b	882	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	883	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	884	* @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
AnnaBridge	143:86740a56073b	885	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	886	* @retval None
AnnaBridge	143:86740a56073b	887	*/
AnnaBridge	143:86740a56073b	888	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	889	{
AnnaBridge	143:86740a56073b	890	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge	143:86740a56073b	891	}
AnnaBridge	143:86740a56073b	892
AnnaBridge	143:86740a56073b	893	/**
AnnaBridge	143:86740a56073b	894	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
AnnaBridge	143:86740a56073b	895	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	896	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	897	* @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
AnnaBridge	143:86740a56073b	898	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	899	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	900	*/
AnnaBridge	143:86740a56073b	901	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	902	{
AnnaBridge	143:86740a56073b	903	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
AnnaBridge	143:86740a56073b	904	}
AnnaBridge	143:86740a56073b	905
AnnaBridge	143:86740a56073b	906	/**
AnnaBridge	143:86740a56073b	907	* @}
AnnaBridge	143:86740a56073b	908	*/
AnnaBridge	143:86740a56073b	909
AnnaBridge	143:86740a56073b	910	/** @defgroup I2C_LL_EF_IT_Management IT_Management
AnnaBridge	143:86740a56073b	911	* @{
AnnaBridge	143:86740a56073b	912	*/
AnnaBridge	143:86740a56073b	913
AnnaBridge	143:86740a56073b	914	/**
AnnaBridge	143:86740a56073b	915	* @brief Enable TXE interrupt.
AnnaBridge	143:86740a56073b	916	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
AnnaBridge	143:86740a56073b	917	* CR2 ITBUFEN LL_I2C_EnableIT_TX
AnnaBridge	143:86740a56073b	918	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	919	* @retval None
AnnaBridge	143:86740a56073b	920	*/
AnnaBridge	143:86740a56073b	921	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	922	{
AnnaBridge	143:86740a56073b	923	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	143:86740a56073b	924	}
AnnaBridge	143:86740a56073b	925
AnnaBridge	143:86740a56073b	926	/**
AnnaBridge	143:86740a56073b	927	* @brief Disable TXE interrupt.
AnnaBridge	143:86740a56073b	928	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
AnnaBridge	143:86740a56073b	929	* CR2 ITBUFEN LL_I2C_DisableIT_TX
AnnaBridge	143:86740a56073b	930	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	931	* @retval None
AnnaBridge	143:86740a56073b	932	*/
AnnaBridge	143:86740a56073b	933	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	934	{
AnnaBridge	143:86740a56073b	935	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	143:86740a56073b	936	}
AnnaBridge	143:86740a56073b	937
AnnaBridge	143:86740a56073b	938	/**
AnnaBridge	143:86740a56073b	939	* @brief Check if the TXE Interrupt is enabled or disabled.
AnnaBridge	143:86740a56073b	940	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
AnnaBridge	143:86740a56073b	941	* CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
AnnaBridge	143:86740a56073b	942	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	943	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	944	*/
AnnaBridge	143:86740a56073b	945	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	946	{
AnnaBridge	143:86740a56073b	947	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
AnnaBridge	143:86740a56073b	948	}
AnnaBridge	143:86740a56073b	949
AnnaBridge	143:86740a56073b	950	/**
AnnaBridge	143:86740a56073b	951	* @brief Enable RXNE interrupt.
AnnaBridge	143:86740a56073b	952	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
AnnaBridge	143:86740a56073b	953	* CR2 ITBUFEN LL_I2C_EnableIT_RX
AnnaBridge	143:86740a56073b	954	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	955	* @retval None
AnnaBridge	143:86740a56073b	956	*/
AnnaBridge	143:86740a56073b	957	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	958	{
AnnaBridge	143:86740a56073b	959	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	143:86740a56073b	960	}
AnnaBridge	143:86740a56073b	961
AnnaBridge	143:86740a56073b	962	/**
AnnaBridge	143:86740a56073b	963	* @brief Disable RXNE interrupt.
AnnaBridge	143:86740a56073b	964	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
AnnaBridge	143:86740a56073b	965	* CR2 ITBUFEN LL_I2C_DisableIT_RX
AnnaBridge	143:86740a56073b	966	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	967	* @retval None
AnnaBridge	143:86740a56073b	968	*/
AnnaBridge	143:86740a56073b	969	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	970	{
AnnaBridge	143:86740a56073b	971	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	143:86740a56073b	972	}
AnnaBridge	143:86740a56073b	973
AnnaBridge	143:86740a56073b	974	/**
AnnaBridge	143:86740a56073b	975	* @brief Check if the RXNE Interrupt is enabled or disabled.
AnnaBridge	143:86740a56073b	976	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
AnnaBridge	143:86740a56073b	977	* CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
AnnaBridge	143:86740a56073b	978	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	979	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	980	*/
AnnaBridge	143:86740a56073b	981	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	982	{
AnnaBridge	143:86740a56073b	983	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
AnnaBridge	143:86740a56073b	984	}
AnnaBridge	143:86740a56073b	985
AnnaBridge	143:86740a56073b	986	/**
AnnaBridge	143:86740a56073b	987	* @brief Enable Events interrupts.
AnnaBridge	143:86740a56073b	988	* @note Any of these events will generate interrupt :
AnnaBridge	143:86740a56073b	989	* Start Bit (SB)
AnnaBridge	143:86740a56073b	990	* Address sent, Address matched (ADDR)
AnnaBridge	143:86740a56073b	991	* 10-bit header sent (ADD10)
AnnaBridge	143:86740a56073b	992	* Stop detection (STOPF)
AnnaBridge	143:86740a56073b	993	* Byte transfer finished (BTF)
AnnaBridge	143:86740a56073b	994	*
AnnaBridge	143:86740a56073b	995	* @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
AnnaBridge	143:86740a56073b	996	* Receive buffer not empty (RXNE)
AnnaBridge	143:86740a56073b	997	* Transmit buffer empty (TXE)
AnnaBridge	143:86740a56073b	998	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
AnnaBridge	143:86740a56073b	999	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1000	* @retval None
AnnaBridge	143:86740a56073b	1001	*/
AnnaBridge	143:86740a56073b	1002	__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1003	{
AnnaBridge	143:86740a56073b	1004	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge	143:86740a56073b	1005	}
AnnaBridge	143:86740a56073b	1006
AnnaBridge	143:86740a56073b	1007	/**
AnnaBridge	143:86740a56073b	1008	* @brief Disable Events interrupts.
AnnaBridge	143:86740a56073b	1009	* @note Any of these events will generate interrupt :
AnnaBridge	143:86740a56073b	1010	* Start Bit (SB)
AnnaBridge	143:86740a56073b	1011	* Address sent, Address matched (ADDR)
AnnaBridge	143:86740a56073b	1012	* 10-bit header sent (ADD10)
AnnaBridge	143:86740a56073b	1013	* Stop detection (STOPF)
AnnaBridge	143:86740a56073b	1014	* Byte transfer finished (BTF)
AnnaBridge	143:86740a56073b	1015	* Receive buffer not empty (RXNE)
AnnaBridge	143:86740a56073b	1016	* Transmit buffer empty (TXE)
AnnaBridge	143:86740a56073b	1017	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
AnnaBridge	143:86740a56073b	1018	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1019	* @retval None
AnnaBridge	143:86740a56073b	1020	*/
AnnaBridge	143:86740a56073b	1021	__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1022	{
AnnaBridge	143:86740a56073b	1023	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge	143:86740a56073b	1024	}
AnnaBridge	143:86740a56073b	1025
AnnaBridge	143:86740a56073b	1026	/**
AnnaBridge	143:86740a56073b	1027	* @brief Check if Events interrupts are enabled or disabled.
AnnaBridge	143:86740a56073b	1028	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
AnnaBridge	143:86740a56073b	1029	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1030	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1031	*/
AnnaBridge	143:86740a56073b	1032	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1033	{
AnnaBridge	143:86740a56073b	1034	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
AnnaBridge	143:86740a56073b	1035	}
AnnaBridge	143:86740a56073b	1036
AnnaBridge	143:86740a56073b	1037	/**
AnnaBridge	143:86740a56073b	1038	* @brief Enable Buffer interrupts.
AnnaBridge	143:86740a56073b	1039	* @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
AnnaBridge	143:86740a56073b	1040	* Receive buffer not empty (RXNE)
AnnaBridge	143:86740a56073b	1041	* Transmit buffer empty (TXE)
AnnaBridge	143:86740a56073b	1042	* @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
AnnaBridge	143:86740a56073b	1043	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1044	* @retval None
AnnaBridge	143:86740a56073b	1045	*/
AnnaBridge	143:86740a56073b	1046	__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1047	{
AnnaBridge	143:86740a56073b	1048	SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge	143:86740a56073b	1049	}
AnnaBridge	143:86740a56073b	1050
AnnaBridge	143:86740a56073b	1051	/**
AnnaBridge	143:86740a56073b	1052	* @brief Disable Buffer interrupts.
AnnaBridge	143:86740a56073b	1053	* @note Any of these Buffer events will generate interrupt :
AnnaBridge	143:86740a56073b	1054	* Receive buffer not empty (RXNE)
AnnaBridge	143:86740a56073b	1055	* Transmit buffer empty (TXE)
AnnaBridge	143:86740a56073b	1056	* @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
AnnaBridge	143:86740a56073b	1057	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1058	* @retval None
AnnaBridge	143:86740a56073b	1059	*/
AnnaBridge	143:86740a56073b	1060	__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1061	{
AnnaBridge	143:86740a56073b	1062	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge	143:86740a56073b	1063	}
AnnaBridge	143:86740a56073b	1064
AnnaBridge	143:86740a56073b	1065	/**
AnnaBridge	143:86740a56073b	1066	* @brief Check if Buffer interrupts are enabled or disabled.
AnnaBridge	143:86740a56073b	1067	* @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
AnnaBridge	143:86740a56073b	1068	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1069	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1070	*/
AnnaBridge	143:86740a56073b	1071	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1072	{
AnnaBridge	143:86740a56073b	1073	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
AnnaBridge	143:86740a56073b	1074	}
AnnaBridge	143:86740a56073b	1075
AnnaBridge	143:86740a56073b	1076	/**
AnnaBridge	143:86740a56073b	1077	* @brief Enable Error interrupts.
AnnaBridge	143:86740a56073b	1078	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1079	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1080	* @note Any of these errors will generate interrupt :
AnnaBridge	143:86740a56073b	1081	* Bus Error detection (BERR)
AnnaBridge	143:86740a56073b	1082	* Arbitration Loss (ARLO)
AnnaBridge	143:86740a56073b	1083	* Acknowledge Failure(AF)
AnnaBridge	143:86740a56073b	1084	* Overrun/Underrun (OVR)
AnnaBridge	143:86740a56073b	1085	* SMBus Timeout detection (TIMEOUT)
AnnaBridge	143:86740a56073b	1086	* SMBus PEC error detection (PECERR)
AnnaBridge	143:86740a56073b	1087	* SMBus Alert pin event detection (SMBALERT)
AnnaBridge	143:86740a56073b	1088	* @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
AnnaBridge	143:86740a56073b	1089	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1090	* @retval None
AnnaBridge	143:86740a56073b	1091	*/
AnnaBridge	143:86740a56073b	1092	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1093	{
AnnaBridge	143:86740a56073b	1094	SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge	143:86740a56073b	1095	}
AnnaBridge	143:86740a56073b	1096
AnnaBridge	143:86740a56073b	1097	/**
AnnaBridge	143:86740a56073b	1098	* @brief Disable Error interrupts.
AnnaBridge	143:86740a56073b	1099	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1100	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1101	* @note Any of these errors will generate interrupt :
AnnaBridge	143:86740a56073b	1102	* Bus Error detection (BERR)
AnnaBridge	143:86740a56073b	1103	* Arbitration Loss (ARLO)
AnnaBridge	143:86740a56073b	1104	* Acknowledge Failure(AF)
AnnaBridge	143:86740a56073b	1105	* Overrun/Underrun (OVR)
AnnaBridge	143:86740a56073b	1106	* SMBus Timeout detection (TIMEOUT)
AnnaBridge	143:86740a56073b	1107	* SMBus PEC error detection (PECERR)
AnnaBridge	143:86740a56073b	1108	* SMBus Alert pin event detection (SMBALERT)
AnnaBridge	143:86740a56073b	1109	* @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
AnnaBridge	143:86740a56073b	1110	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1111	* @retval None
AnnaBridge	143:86740a56073b	1112	*/
AnnaBridge	143:86740a56073b	1113	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1114	{
AnnaBridge	143:86740a56073b	1115	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge	143:86740a56073b	1116	}
AnnaBridge	143:86740a56073b	1117
AnnaBridge	143:86740a56073b	1118	/**
AnnaBridge	143:86740a56073b	1119	* @brief Check if Error interrupts are enabled or disabled.
AnnaBridge	143:86740a56073b	1120	* @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
AnnaBridge	143:86740a56073b	1121	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1122	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1123	*/
AnnaBridge	143:86740a56073b	1124	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1125	{
AnnaBridge	143:86740a56073b	1126	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
AnnaBridge	143:86740a56073b	1127	}
AnnaBridge	143:86740a56073b	1128
AnnaBridge	143:86740a56073b	1129	/**
AnnaBridge	143:86740a56073b	1130	* @}
AnnaBridge	143:86740a56073b	1131	*/
AnnaBridge	143:86740a56073b	1132
AnnaBridge	143:86740a56073b	1133	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
AnnaBridge	143:86740a56073b	1134	* @{
AnnaBridge	143:86740a56073b	1135	*/
AnnaBridge	143:86740a56073b	1136
AnnaBridge	143:86740a56073b	1137	/**
AnnaBridge	143:86740a56073b	1138	* @brief Indicate the status of Transmit data register empty flag.
AnnaBridge	143:86740a56073b	1139	* @note RESET: When next data is written in Transmit data register.
AnnaBridge	143:86740a56073b	1140	* SET: When Transmit data register is empty.
AnnaBridge	143:86740a56073b	1141	* @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
AnnaBridge	143:86740a56073b	1142	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1143	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1144	*/
AnnaBridge	143:86740a56073b	1145	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1146	{
AnnaBridge	143:86740a56073b	1147	return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
AnnaBridge	143:86740a56073b	1148	}
AnnaBridge	143:86740a56073b	1149
AnnaBridge	143:86740a56073b	1150	/**
AnnaBridge	143:86740a56073b	1151	* @brief Indicate the status of Byte Transfer Finished flag.
AnnaBridge	143:86740a56073b	1152	* RESET: When Data byte transfer not done.
AnnaBridge	143:86740a56073b	1153	* SET: When Data byte transfer succeeded.
AnnaBridge	143:86740a56073b	1154	* @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
AnnaBridge	143:86740a56073b	1155	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1156	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1157	*/
AnnaBridge	143:86740a56073b	1158	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1159	{
AnnaBridge	143:86740a56073b	1160	return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
AnnaBridge	143:86740a56073b	1161	}
AnnaBridge	143:86740a56073b	1162
AnnaBridge	143:86740a56073b	1163	/**
AnnaBridge	143:86740a56073b	1164	* @brief Indicate the status of Receive data register not empty flag.
AnnaBridge	143:86740a56073b	1165	* @note RESET: When Receive data register is read.
AnnaBridge	143:86740a56073b	1166	* SET: When the received data is copied in Receive data register.
AnnaBridge	143:86740a56073b	1167	* @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
AnnaBridge	143:86740a56073b	1168	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1169	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1170	*/
AnnaBridge	143:86740a56073b	1171	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1172	{
AnnaBridge	143:86740a56073b	1173	return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
AnnaBridge	143:86740a56073b	1174	}
AnnaBridge	143:86740a56073b	1175
AnnaBridge	143:86740a56073b	1176	/**
AnnaBridge	143:86740a56073b	1177	* @brief Indicate the status of Start Bit (master mode).
AnnaBridge	143:86740a56073b	1178	* @note RESET: When No Start condition.
AnnaBridge	143:86740a56073b	1179	* SET: When Start condition is generated.
AnnaBridge	143:86740a56073b	1180	* @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
AnnaBridge	143:86740a56073b	1181	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1182	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1183	*/
AnnaBridge	143:86740a56073b	1184	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1185	{
AnnaBridge	143:86740a56073b	1186	return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
AnnaBridge	143:86740a56073b	1187	}
AnnaBridge	143:86740a56073b	1188
AnnaBridge	143:86740a56073b	1189	/**
AnnaBridge	143:86740a56073b	1190	* @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
AnnaBridge	143:86740a56073b	1191	* @note RESET: Clear default value.
AnnaBridge	143:86740a56073b	1192	* SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
AnnaBridge	143:86740a56073b	1193	* @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
AnnaBridge	143:86740a56073b	1194	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1195	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1196	*/
AnnaBridge	143:86740a56073b	1197	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1198	{
AnnaBridge	143:86740a56073b	1199	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
AnnaBridge	143:86740a56073b	1200	}
AnnaBridge	143:86740a56073b	1201
AnnaBridge	143:86740a56073b	1202	/**
AnnaBridge	143:86740a56073b	1203	* @brief Indicate the status of 10-bit header sent (master mode).
AnnaBridge	143:86740a56073b	1204	* @note RESET: When no ADD10 event occured.
AnnaBridge	143:86740a56073b	1205	* SET: When the master has sent the first address byte (header).
AnnaBridge	143:86740a56073b	1206	* @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
AnnaBridge	143:86740a56073b	1207	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1208	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1209	*/
AnnaBridge	143:86740a56073b	1210	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1211	{
AnnaBridge	143:86740a56073b	1212	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
AnnaBridge	143:86740a56073b	1213	}
AnnaBridge	143:86740a56073b	1214
AnnaBridge	143:86740a56073b	1215	/**
AnnaBridge	143:86740a56073b	1216	* @brief Indicate the status of Acknowledge failure flag.
AnnaBridge	143:86740a56073b	1217	* @note RESET: No acknowledge failure.
AnnaBridge	143:86740a56073b	1218	* SET: When an acknowledge failure is received after a byte transmission.
AnnaBridge	143:86740a56073b	1219	* @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
AnnaBridge	143:86740a56073b	1220	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1221	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1222	*/
AnnaBridge	143:86740a56073b	1223	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1224	{
AnnaBridge	143:86740a56073b	1225	return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
AnnaBridge	143:86740a56073b	1226	}
AnnaBridge	143:86740a56073b	1227
AnnaBridge	143:86740a56073b	1228	/**
AnnaBridge	143:86740a56073b	1229	* @brief Indicate the status of Stop detection flag (slave mode).
AnnaBridge	143:86740a56073b	1230	* @note RESET: Clear default value.
AnnaBridge	143:86740a56073b	1231	* SET: When a Stop condition is detected.
AnnaBridge	143:86740a56073b	1232	* @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
AnnaBridge	143:86740a56073b	1233	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1234	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1235	*/
AnnaBridge	143:86740a56073b	1236	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1237	{
AnnaBridge	143:86740a56073b	1238	return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
AnnaBridge	143:86740a56073b	1239	}
AnnaBridge	143:86740a56073b	1240
AnnaBridge	143:86740a56073b	1241	/**
AnnaBridge	143:86740a56073b	1242	* @brief Indicate the status of Bus error flag.
AnnaBridge	143:86740a56073b	1243	* @note RESET: Clear default value.
AnnaBridge	143:86740a56073b	1244	* SET: When a misplaced Start or Stop condition is detected.
AnnaBridge	143:86740a56073b	1245	* @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
AnnaBridge	143:86740a56073b	1246	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1247	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1248	*/
AnnaBridge	143:86740a56073b	1249	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1250	{
AnnaBridge	143:86740a56073b	1251	return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
AnnaBridge	143:86740a56073b	1252	}
AnnaBridge	143:86740a56073b	1253
AnnaBridge	143:86740a56073b	1254	/**
AnnaBridge	143:86740a56073b	1255	* @brief Indicate the status of Arbitration lost flag.
AnnaBridge	143:86740a56073b	1256	* @note RESET: Clear default value.
AnnaBridge	143:86740a56073b	1257	* SET: When arbitration lost.
AnnaBridge	143:86740a56073b	1258	* @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
AnnaBridge	143:86740a56073b	1259	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1260	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1261	*/
AnnaBridge	143:86740a56073b	1262	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1263	{
AnnaBridge	143:86740a56073b	1264	return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
AnnaBridge	143:86740a56073b	1265	}
AnnaBridge	143:86740a56073b	1266
AnnaBridge	143:86740a56073b	1267	/**
AnnaBridge	143:86740a56073b	1268	* @brief Indicate the status of Overrun/Underrun flag.
AnnaBridge	143:86740a56073b	1269	* @note RESET: Clear default value.
AnnaBridge	143:86740a56073b	1270	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
AnnaBridge	143:86740a56073b	1271	* @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
AnnaBridge	143:86740a56073b	1272	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1273	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1274	*/
AnnaBridge	143:86740a56073b	1275	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1276	{
AnnaBridge	143:86740a56073b	1277	return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
AnnaBridge	143:86740a56073b	1278	}
AnnaBridge	143:86740a56073b	1279
AnnaBridge	143:86740a56073b	1280	/**
AnnaBridge	143:86740a56073b	1281	* @brief Indicate the status of SMBus PEC error flag in reception.
AnnaBridge	143:86740a56073b	1282	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1283	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1284	* @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
AnnaBridge	143:86740a56073b	1285	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1286	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1287	*/
AnnaBridge	143:86740a56073b	1288	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1289	{
AnnaBridge	143:86740a56073b	1290	return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
AnnaBridge	143:86740a56073b	1291	}
AnnaBridge	143:86740a56073b	1292
AnnaBridge	143:86740a56073b	1293	/**
AnnaBridge	143:86740a56073b	1294	* @brief Indicate the status of SMBus Timeout detection flag.
AnnaBridge	143:86740a56073b	1295	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1296	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1297	* @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
AnnaBridge	143:86740a56073b	1298	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1299	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1300	*/
AnnaBridge	143:86740a56073b	1301	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1302	{
AnnaBridge	143:86740a56073b	1303	return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
AnnaBridge	143:86740a56073b	1304	}
AnnaBridge	143:86740a56073b	1305
AnnaBridge	143:86740a56073b	1306	/**
AnnaBridge	143:86740a56073b	1307	* @brief Indicate the status of SMBus alert flag.
AnnaBridge	143:86740a56073b	1308	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1309	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1310	* @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
AnnaBridge	143:86740a56073b	1311	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1312	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1313	*/
AnnaBridge	143:86740a56073b	1314	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1315	{
AnnaBridge	143:86740a56073b	1316	return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
AnnaBridge	143:86740a56073b	1317	}
AnnaBridge	143:86740a56073b	1318
AnnaBridge	143:86740a56073b	1319	/**
AnnaBridge	143:86740a56073b	1320	* @brief Indicate the status of Bus Busy flag.
AnnaBridge	143:86740a56073b	1321	* @note RESET: Clear default value.
AnnaBridge	143:86740a56073b	1322	* SET: When a Start condition is detected.
AnnaBridge	143:86740a56073b	1323	* @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
AnnaBridge	143:86740a56073b	1324	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1325	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1326	*/
AnnaBridge	143:86740a56073b	1327	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1328	{
AnnaBridge	143:86740a56073b	1329	return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
AnnaBridge	143:86740a56073b	1330	}
AnnaBridge	143:86740a56073b	1331
AnnaBridge	143:86740a56073b	1332	/**
AnnaBridge	143:86740a56073b	1333	* @brief Indicate the status of Dual flag.
AnnaBridge	143:86740a56073b	1334	* @note RESET: Received address matched with OAR1.
AnnaBridge	143:86740a56073b	1335	* SET: Received address matched with OAR2.
AnnaBridge	143:86740a56073b	1336	* @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
AnnaBridge	143:86740a56073b	1337	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1338	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1339	*/
AnnaBridge	143:86740a56073b	1340	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1341	{
AnnaBridge	143:86740a56073b	1342	return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
AnnaBridge	143:86740a56073b	1343	}
AnnaBridge	143:86740a56073b	1344
AnnaBridge	143:86740a56073b	1345	/**
AnnaBridge	143:86740a56073b	1346	* @brief Indicate the status of SMBus Host address reception (Slave mode).
AnnaBridge	143:86740a56073b	1347	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1348	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1349	* @note RESET: No SMBus Host address
AnnaBridge	143:86740a56073b	1350	* SET: SMBus Host address received.
AnnaBridge	143:86740a56073b	1351	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge	143:86740a56073b	1352	* @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
AnnaBridge	143:86740a56073b	1353	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1354	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1355	*/
AnnaBridge	143:86740a56073b	1356	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1357	{
AnnaBridge	143:86740a56073b	1358	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
AnnaBridge	143:86740a56073b	1359	}
AnnaBridge	143:86740a56073b	1360
AnnaBridge	143:86740a56073b	1361	/**
AnnaBridge	143:86740a56073b	1362	* @brief Indicate the status of SMBus Device default address reception (Slave mode).
AnnaBridge	143:86740a56073b	1363	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1364	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1365	* @note RESET: No SMBus Device default address
AnnaBridge	143:86740a56073b	1366	* SET: SMBus Device default address received.
AnnaBridge	143:86740a56073b	1367	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge	143:86740a56073b	1368	* @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
AnnaBridge	143:86740a56073b	1369	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1370	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1371	*/
AnnaBridge	143:86740a56073b	1372	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1373	{
AnnaBridge	143:86740a56073b	1374	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
AnnaBridge	143:86740a56073b	1375	}
AnnaBridge	143:86740a56073b	1376
AnnaBridge	143:86740a56073b	1377	/**
AnnaBridge	143:86740a56073b	1378	* @brief Indicate the status of General call address reception (Slave mode).
AnnaBridge	143:86740a56073b	1379	* @note RESET: No Generall call address
AnnaBridge	143:86740a56073b	1380	* SET: General call address received.
AnnaBridge	143:86740a56073b	1381	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge	143:86740a56073b	1382	* @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
AnnaBridge	143:86740a56073b	1383	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1384	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1385	*/
AnnaBridge	143:86740a56073b	1386	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1387	{
AnnaBridge	143:86740a56073b	1388	return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
AnnaBridge	143:86740a56073b	1389	}
AnnaBridge	143:86740a56073b	1390
AnnaBridge	143:86740a56073b	1391	/**
AnnaBridge	143:86740a56073b	1392	* @brief Indicate the status of Master/Slave flag.
AnnaBridge	143:86740a56073b	1393	* @note RESET: Slave Mode.
AnnaBridge	143:86740a56073b	1394	* SET: Master Mode.
AnnaBridge	143:86740a56073b	1395	* @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
AnnaBridge	143:86740a56073b	1396	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1397	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1398	*/
AnnaBridge	143:86740a56073b	1399	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1400	{
AnnaBridge	143:86740a56073b	1401	return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
AnnaBridge	143:86740a56073b	1402	}
AnnaBridge	143:86740a56073b	1403
AnnaBridge	143:86740a56073b	1404	/**
AnnaBridge	143:86740a56073b	1405	* @brief Clear Address Matched flag.
AnnaBridge	143:86740a56073b	1406	* @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge	143:86740a56073b	1407	* register followed by a read access to the I2Cx_SR2 register.
AnnaBridge	143:86740a56073b	1408	* @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
AnnaBridge	143:86740a56073b	1409	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1410	* @retval None
AnnaBridge	143:86740a56073b	1411	*/
AnnaBridge	143:86740a56073b	1412	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1413	{
AnnaBridge	143:86740a56073b	1414	__IO uint32_t tmpreg;
AnnaBridge	143:86740a56073b	1415	tmpreg = I2Cx->SR1;
AnnaBridge	143:86740a56073b	1416	(void) tmpreg;
AnnaBridge	143:86740a56073b	1417	tmpreg = I2Cx->SR2;
AnnaBridge	143:86740a56073b	1418	(void) tmpreg;
AnnaBridge	143:86740a56073b	1419	}
AnnaBridge	143:86740a56073b	1420
AnnaBridge	143:86740a56073b	1421	/**
AnnaBridge	143:86740a56073b	1422	* @brief Clear Acknowledge failure flag.
AnnaBridge	143:86740a56073b	1423	* @rmtoll SR1 AF LL_I2C_ClearFlag_AF
AnnaBridge	143:86740a56073b	1424	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1425	* @retval None
AnnaBridge	143:86740a56073b	1426	*/
AnnaBridge	143:86740a56073b	1427	__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1428	{
AnnaBridge	143:86740a56073b	1429	CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
AnnaBridge	143:86740a56073b	1430	}
AnnaBridge	143:86740a56073b	1431
AnnaBridge	143:86740a56073b	1432	/**
AnnaBridge	143:86740a56073b	1433	* @brief Clear Stop detection flag.
AnnaBridge	143:86740a56073b	1434	* @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge	143:86740a56073b	1435	* register followed by a write access to I2Cx_CR1 register.
AnnaBridge	143:86740a56073b	1436	* @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
AnnaBridge	143:86740a56073b	1437	* CR1 PE LL_I2C_ClearFlag_STOP
AnnaBridge	143:86740a56073b	1438	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1439	* @retval None
AnnaBridge	143:86740a56073b	1440	*/
AnnaBridge	143:86740a56073b	1441	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1442	{
AnnaBridge	143:86740a56073b	1443	__IO uint32_t tmpreg;
AnnaBridge	143:86740a56073b	1444	tmpreg = I2Cx->SR1;
AnnaBridge	143:86740a56073b	1445	(void) tmpreg;
AnnaBridge	143:86740a56073b	1446	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge	143:86740a56073b	1447	}
AnnaBridge	143:86740a56073b	1448
AnnaBridge	143:86740a56073b	1449	/**
AnnaBridge	143:86740a56073b	1450	* @brief Clear Bus error flag.
AnnaBridge	143:86740a56073b	1451	* @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
AnnaBridge	143:86740a56073b	1452	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1453	* @retval None
AnnaBridge	143:86740a56073b	1454	*/
AnnaBridge	143:86740a56073b	1455	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1456	{
AnnaBridge	143:86740a56073b	1457	CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
AnnaBridge	143:86740a56073b	1458	}
AnnaBridge	143:86740a56073b	1459
AnnaBridge	143:86740a56073b	1460	/**
AnnaBridge	143:86740a56073b	1461	* @brief Clear Arbitration lost flag.
AnnaBridge	143:86740a56073b	1462	* @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
AnnaBridge	143:86740a56073b	1463	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1464	* @retval None
AnnaBridge	143:86740a56073b	1465	*/
AnnaBridge	143:86740a56073b	1466	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1467	{
AnnaBridge	143:86740a56073b	1468	CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
AnnaBridge	143:86740a56073b	1469	}
AnnaBridge	143:86740a56073b	1470
AnnaBridge	143:86740a56073b	1471	/**
AnnaBridge	143:86740a56073b	1472	* @brief Clear Overrun/Underrun flag.
AnnaBridge	143:86740a56073b	1473	* @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
AnnaBridge	143:86740a56073b	1474	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1475	* @retval None
AnnaBridge	143:86740a56073b	1476	*/
AnnaBridge	143:86740a56073b	1477	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1478	{
AnnaBridge	143:86740a56073b	1479	CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
AnnaBridge	143:86740a56073b	1480	}
AnnaBridge	143:86740a56073b	1481
AnnaBridge	143:86740a56073b	1482	/**
AnnaBridge	143:86740a56073b	1483	* @brief Clear SMBus PEC error flag.
AnnaBridge	143:86740a56073b	1484	* @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
AnnaBridge	143:86740a56073b	1485	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1486	* @retval None
AnnaBridge	143:86740a56073b	1487	*/
AnnaBridge	143:86740a56073b	1488	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1489	{
AnnaBridge	143:86740a56073b	1490	CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
AnnaBridge	143:86740a56073b	1491	}
AnnaBridge	143:86740a56073b	1492
AnnaBridge	143:86740a56073b	1493	/**
AnnaBridge	143:86740a56073b	1494	* @brief Clear SMBus Timeout detection flag.
AnnaBridge	143:86740a56073b	1495	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1496	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1497	* @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
AnnaBridge	143:86740a56073b	1498	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1499	* @retval None
AnnaBridge	143:86740a56073b	1500	*/
AnnaBridge	143:86740a56073b	1501	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1502	{
AnnaBridge	143:86740a56073b	1503	CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
AnnaBridge	143:86740a56073b	1504	}
AnnaBridge	143:86740a56073b	1505
AnnaBridge	143:86740a56073b	1506	/**
AnnaBridge	143:86740a56073b	1507	* @brief Clear SMBus Alert flag.
AnnaBridge	143:86740a56073b	1508	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1509	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1510	* @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
AnnaBridge	143:86740a56073b	1511	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1512	* @retval None
AnnaBridge	143:86740a56073b	1513	*/
AnnaBridge	143:86740a56073b	1514	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1515	{
AnnaBridge	143:86740a56073b	1516	CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
AnnaBridge	143:86740a56073b	1517	}
AnnaBridge	143:86740a56073b	1518
AnnaBridge	143:86740a56073b	1519	/**
AnnaBridge	143:86740a56073b	1520	* @}
AnnaBridge	143:86740a56073b	1521	*/
AnnaBridge	143:86740a56073b	1522
AnnaBridge	143:86740a56073b	1523	/** @defgroup I2C_LL_EF_Data_Management Data_Management
AnnaBridge	143:86740a56073b	1524	* @{
AnnaBridge	143:86740a56073b	1525	*/
AnnaBridge	143:86740a56073b	1526
AnnaBridge	143:86740a56073b	1527	/**
AnnaBridge	143:86740a56073b	1528	* @brief Enable Reset of I2C peripheral.
AnnaBridge	143:86740a56073b	1529	* @rmtoll CR1 SWRST LL_I2C_EnableReset
AnnaBridge	143:86740a56073b	1530	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1531	* @retval None
AnnaBridge	143:86740a56073b	1532	*/
AnnaBridge	143:86740a56073b	1533	__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1534	{
AnnaBridge	143:86740a56073b	1535	SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge	143:86740a56073b	1536	}
AnnaBridge	143:86740a56073b	1537
AnnaBridge	143:86740a56073b	1538	/**
AnnaBridge	143:86740a56073b	1539	* @brief Disable Reset of I2C peripheral.
AnnaBridge	143:86740a56073b	1540	* @rmtoll CR1 SWRST LL_I2C_DisableReset
AnnaBridge	143:86740a56073b	1541	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1542	* @retval None
AnnaBridge	143:86740a56073b	1543	*/
AnnaBridge	143:86740a56073b	1544	__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1545	{
AnnaBridge	143:86740a56073b	1546	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge	143:86740a56073b	1547	}
AnnaBridge	143:86740a56073b	1548
AnnaBridge	143:86740a56073b	1549	/**
AnnaBridge	143:86740a56073b	1550	* @brief Check if the I2C peripheral is under reset state or not.
AnnaBridge	143:86740a56073b	1551	* @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
AnnaBridge	143:86740a56073b	1552	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1553	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1554	*/
AnnaBridge	143:86740a56073b	1555	__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1556	{
AnnaBridge	143:86740a56073b	1557	return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
AnnaBridge	143:86740a56073b	1558	}
AnnaBridge	143:86740a56073b	1559
AnnaBridge	143:86740a56073b	1560	/**
AnnaBridge	143:86740a56073b	1561	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge	143:86740a56073b	1562	* @note Usage in Slave or Master mode.
AnnaBridge	143:86740a56073b	1563	* @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
AnnaBridge	143:86740a56073b	1564	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1565	* @param TypeAcknowledge This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1566	* @arg @ref LL_I2C_ACK
AnnaBridge	143:86740a56073b	1567	* @arg @ref LL_I2C_NACK
AnnaBridge	143:86740a56073b	1568	* @retval None
AnnaBridge	143:86740a56073b	1569	*/
AnnaBridge	143:86740a56073b	1570	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
AnnaBridge	143:86740a56073b	1571	{
AnnaBridge	143:86740a56073b	1572	MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
AnnaBridge	143:86740a56073b	1573	}
AnnaBridge	143:86740a56073b	1574
AnnaBridge	143:86740a56073b	1575	/**
AnnaBridge	143:86740a56073b	1576	* @brief Generate a START or RESTART condition
AnnaBridge	143:86740a56073b	1577	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
AnnaBridge	143:86740a56073b	1578	* This action has no effect when RELOAD is set.
AnnaBridge	143:86740a56073b	1579	* @rmtoll CR1 START LL_I2C_GenerateStartCondition
AnnaBridge	143:86740a56073b	1580	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1581	* @retval None
AnnaBridge	143:86740a56073b	1582	*/
AnnaBridge	143:86740a56073b	1583	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1584	{
AnnaBridge	143:86740a56073b	1585	SET_BIT(I2Cx->CR1, I2C_CR1_START);
AnnaBridge	143:86740a56073b	1586	}
AnnaBridge	143:86740a56073b	1587
AnnaBridge	143:86740a56073b	1588	/**
AnnaBridge	143:86740a56073b	1589	* @brief Generate a STOP condition after the current byte transfer (master mode).
AnnaBridge	143:86740a56073b	1590	* @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
AnnaBridge	143:86740a56073b	1591	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1592	* @retval None
AnnaBridge	143:86740a56073b	1593	*/
AnnaBridge	143:86740a56073b	1594	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1595	{
AnnaBridge	143:86740a56073b	1596	SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
AnnaBridge	143:86740a56073b	1597	}
AnnaBridge	143:86740a56073b	1598
AnnaBridge	143:86740a56073b	1599	/**
AnnaBridge	143:86740a56073b	1600	* @brief Enable bit POS (master/host mode).
AnnaBridge	143:86740a56073b	1601	* @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
AnnaBridge	143:86740a56073b	1602	* @rmtoll CR1 POS LL_I2C_EnableBitPOS
AnnaBridge	143:86740a56073b	1603	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1604	* @retval None
AnnaBridge	143:86740a56073b	1605	*/
AnnaBridge	143:86740a56073b	1606	__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1607	{
AnnaBridge	143:86740a56073b	1608	SET_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge	143:86740a56073b	1609	}
AnnaBridge	143:86740a56073b	1610
AnnaBridge	143:86740a56073b	1611	/**
AnnaBridge	143:86740a56073b	1612	* @brief Disable bit POS (master/host mode).
AnnaBridge	143:86740a56073b	1613	* @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
AnnaBridge	143:86740a56073b	1614	* @rmtoll CR1 POS LL_I2C_DisableBitPOS
AnnaBridge	143:86740a56073b	1615	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1616	* @retval None
AnnaBridge	143:86740a56073b	1617	*/
AnnaBridge	143:86740a56073b	1618	__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1619	{
AnnaBridge	143:86740a56073b	1620	CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge	143:86740a56073b	1621	}
AnnaBridge	143:86740a56073b	1622
AnnaBridge	143:86740a56073b	1623	/**
AnnaBridge	143:86740a56073b	1624	* @brief Check if bit POS is enabled or disabled.
AnnaBridge	143:86740a56073b	1625	* @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
AnnaBridge	143:86740a56073b	1626	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1627	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1628	*/
AnnaBridge	143:86740a56073b	1629	__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1630	{
AnnaBridge	143:86740a56073b	1631	return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
AnnaBridge	143:86740a56073b	1632	}
AnnaBridge	143:86740a56073b	1633
AnnaBridge	143:86740a56073b	1634	/**
AnnaBridge	143:86740a56073b	1635	* @brief Indicate the value of transfer direction.
AnnaBridge	143:86740a56073b	1636	* @note RESET: Bus is in read transfer (peripheral point of view).
AnnaBridge	143:86740a56073b	1637	* SET: Bus is in write transfer (peripheral point of view).
AnnaBridge	143:86740a56073b	1638	* @rmtoll SR2 TRA LL_I2C_GetTransferDirection
AnnaBridge	143:86740a56073b	1639	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1640	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1641	* @arg @ref LL_I2C_DIRECTION_WRITE
AnnaBridge	143:86740a56073b	1642	* @arg @ref LL_I2C_DIRECTION_READ
AnnaBridge	143:86740a56073b	1643	*/
AnnaBridge	143:86740a56073b	1644	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1645	{
AnnaBridge	143:86740a56073b	1646	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
AnnaBridge	143:86740a56073b	1647	}
AnnaBridge	143:86740a56073b	1648
AnnaBridge	143:86740a56073b	1649	/**
AnnaBridge	143:86740a56073b	1650	* @brief Enable DMA last transfer.
AnnaBridge	143:86740a56073b	1651	* @note This action mean that next DMA EOT is the last transfer.
AnnaBridge	143:86740a56073b	1652	* @rmtoll CR2 LAST LL_I2C_EnableLastDMA
AnnaBridge	143:86740a56073b	1653	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1654	* @retval None
AnnaBridge	143:86740a56073b	1655	*/
AnnaBridge	143:86740a56073b	1656	__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1657	{
AnnaBridge	143:86740a56073b	1658	SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge	143:86740a56073b	1659	}
AnnaBridge	143:86740a56073b	1660
AnnaBridge	143:86740a56073b	1661	/**
AnnaBridge	143:86740a56073b	1662	* @brief Disable DMA last transfer.
AnnaBridge	143:86740a56073b	1663	* @note This action mean that next DMA EOT is not the last transfer.
AnnaBridge	143:86740a56073b	1664	* @rmtoll CR2 LAST LL_I2C_DisableLastDMA
AnnaBridge	143:86740a56073b	1665	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1666	* @retval None
AnnaBridge	143:86740a56073b	1667	*/
AnnaBridge	143:86740a56073b	1668	__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1669	{
AnnaBridge	143:86740a56073b	1670	CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge	143:86740a56073b	1671	}
AnnaBridge	143:86740a56073b	1672
AnnaBridge	143:86740a56073b	1673	/**
AnnaBridge	143:86740a56073b	1674	* @brief Check if DMA last transfer is enabled or disabled.
AnnaBridge	143:86740a56073b	1675	* @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
AnnaBridge	143:86740a56073b	1676	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1677	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1678	*/
AnnaBridge	143:86740a56073b	1679	__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1680	{
AnnaBridge	143:86740a56073b	1681	return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
AnnaBridge	143:86740a56073b	1682	}
AnnaBridge	143:86740a56073b	1683
AnnaBridge	143:86740a56073b	1684	/**
AnnaBridge	143:86740a56073b	1685	* @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge	143:86740a56073b	1686	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1687	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1688	* @note This feature is cleared by hardware when the PEC byte is transferred or compared,
AnnaBridge	143:86740a56073b	1689	* or by a START or STOP condition, it is also cleared by software.
AnnaBridge	143:86740a56073b	1690	* @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
AnnaBridge	143:86740a56073b	1691	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1692	* @retval None
AnnaBridge	143:86740a56073b	1693	*/
AnnaBridge	143:86740a56073b	1694	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1695	{
AnnaBridge	143:86740a56073b	1696	SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge	143:86740a56073b	1697	}
AnnaBridge	143:86740a56073b	1698
AnnaBridge	143:86740a56073b	1699	/**
AnnaBridge	143:86740a56073b	1700	* @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge	143:86740a56073b	1701	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1702	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1703	* @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
AnnaBridge	143:86740a56073b	1704	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1705	* @retval None
AnnaBridge	143:86740a56073b	1706	*/
AnnaBridge	143:86740a56073b	1707	__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1708	{
AnnaBridge	143:86740a56073b	1709	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge	143:86740a56073b	1710	}
AnnaBridge	143:86740a56073b	1711
AnnaBridge	143:86740a56073b	1712	/**
AnnaBridge	143:86740a56073b	1713	* @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
AnnaBridge	143:86740a56073b	1714	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1715	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1716	* @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
AnnaBridge	143:86740a56073b	1717	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1718	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1719	*/
AnnaBridge	143:86740a56073b	1720	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1721	{
AnnaBridge	143:86740a56073b	1722	return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
AnnaBridge	143:86740a56073b	1723	}
AnnaBridge	143:86740a56073b	1724
AnnaBridge	143:86740a56073b	1725	/**
AnnaBridge	143:86740a56073b	1726	* @brief Get the SMBus Packet Error byte calculated.
AnnaBridge	143:86740a56073b	1727	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1728	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	143:86740a56073b	1729	* @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
AnnaBridge	143:86740a56073b	1730	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1731	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	143:86740a56073b	1732	*/
AnnaBridge	143:86740a56073b	1733	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1734	{
AnnaBridge	143:86740a56073b	1735	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
AnnaBridge	143:86740a56073b	1736	}
AnnaBridge	143:86740a56073b	1737
AnnaBridge	143:86740a56073b	1738	/**
AnnaBridge	143:86740a56073b	1739	* @brief Read Receive Data register.
AnnaBridge	143:86740a56073b	1740	* @rmtoll DR DR LL_I2C_ReceiveData8
AnnaBridge	143:86740a56073b	1741	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1742	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge	143:86740a56073b	1743	*/
AnnaBridge	143:86740a56073b	1744	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
AnnaBridge	143:86740a56073b	1745	{
AnnaBridge	143:86740a56073b	1746	return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
AnnaBridge	143:86740a56073b	1747	}
AnnaBridge	143:86740a56073b	1748
AnnaBridge	143:86740a56073b	1749	/**
AnnaBridge	143:86740a56073b	1750	* @brief Write in Transmit Data Register .
AnnaBridge	143:86740a56073b	1751	* @rmtoll DR DR LL_I2C_TransmitData8
AnnaBridge	143:86740a56073b	1752	* @param I2Cx I2C Instance.
AnnaBridge	143:86740a56073b	1753	* @param Data Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge	143:86740a56073b	1754	* @retval None
AnnaBridge	143:86740a56073b	1755	*/
AnnaBridge	143:86740a56073b	1756	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
AnnaBridge	143:86740a56073b	1757	{
AnnaBridge	143:86740a56073b	1758	MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
AnnaBridge	143:86740a56073b	1759	}
AnnaBridge	143:86740a56073b	1760
AnnaBridge	143:86740a56073b	1761	/**
AnnaBridge	143:86740a56073b	1762	* @}
AnnaBridge	143:86740a56073b	1763	*/
AnnaBridge	143:86740a56073b	1764
AnnaBridge	143:86740a56073b	1765	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	1766	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	143:86740a56073b	1767	* @{
AnnaBridge	143:86740a56073b	1768	*/
AnnaBridge	143:86740a56073b	1769
AnnaBridge	143:86740a56073b	1770	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
AnnaBridge	143:86740a56073b	1771	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
AnnaBridge	143:86740a56073b	1772	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
AnnaBridge	143:86740a56073b	1773
AnnaBridge	143:86740a56073b	1774
AnnaBridge	143:86740a56073b	1775	/**
AnnaBridge	143:86740a56073b	1776	* @}
AnnaBridge	143:86740a56073b	1777	*/
AnnaBridge	143:86740a56073b	1778	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	143:86740a56073b	1779
AnnaBridge	143:86740a56073b	1780	/**
AnnaBridge	143:86740a56073b	1781	* @}
AnnaBridge	143:86740a56073b	1782	*/
AnnaBridge	143:86740a56073b	1783
AnnaBridge	143:86740a56073b	1784	/**
AnnaBridge	143:86740a56073b	1785	* @}
AnnaBridge	143:86740a56073b	1786	*/
AnnaBridge	143:86740a56073b	1787
AnnaBridge	143:86740a56073b	1788	#endif /* I2C1 \|\| I2C2 */
AnnaBridge	143:86740a56073b	1789
AnnaBridge	143:86740a56073b	1790	/**
AnnaBridge	143:86740a56073b	1791	* @}
AnnaBridge	143:86740a56073b	1792	*/
AnnaBridge	143:86740a56073b	1793
AnnaBridge	143:86740a56073b	1794	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	1795	}
AnnaBridge	143:86740a56073b	1796	#endif
AnnaBridge	143:86740a56073b	1797
AnnaBridge	143:86740a56073b	1798	#endif /* __STM32F1xx_LL_I2C_H */
AnnaBridge	143:86740a56073b	1799
AnnaBridge	143:86740a56073b	1800	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/