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TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f1xx_ll_gpio.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f1xx_ll_gpio.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of GPIO LL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32F1xx_LL_GPIO_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32F1xx_LL_GPIO_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32f1xx.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32F1xx_LL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	#if defined (GPIOA) \|\| defined (GPIOB) \|\| defined (GPIOC) \|\| defined (GPIOD) \|\| defined (GPIOE) \|\| defined (GPIOF) \|\| defined (GPIOG)
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	/** @defgroup GPIO_LL GPIO
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	59	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	60
AnnaBridge	171:3a7713b1edbc	61	/** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
AnnaBridge	171:3a7713b1edbc	62	* @{
AnnaBridge	171:3a7713b1edbc	63	*/
AnnaBridge	171:3a7713b1edbc	64	/* Defines used for Pin Mask Initialization */
AnnaBridge	171:3a7713b1edbc	65	#define GPIO_PIN_MASK_POS 8U
AnnaBridge	171:3a7713b1edbc	66	#define GPIO_PIN_NB 16U
AnnaBridge	171:3a7713b1edbc	67	/**
AnnaBridge	171:3a7713b1edbc	68	* @}
AnnaBridge	171:3a7713b1edbc	69	*/
AnnaBridge	171:3a7713b1edbc	70
AnnaBridge	171:3a7713b1edbc	71	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	72	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	73	/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
AnnaBridge	171:3a7713b1edbc	74	* @{
AnnaBridge	171:3a7713b1edbc	75	*/
AnnaBridge	171:3a7713b1edbc	76
AnnaBridge	171:3a7713b1edbc	77	/**
AnnaBridge	171:3a7713b1edbc	78	* @}
AnnaBridge	171:3a7713b1edbc	79	*/
AnnaBridge	171:3a7713b1edbc	80	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	171:3a7713b1edbc	81
AnnaBridge	171:3a7713b1edbc	82	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	83	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	84	/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
AnnaBridge	171:3a7713b1edbc	85	* @{
AnnaBridge	171:3a7713b1edbc	86	*/
AnnaBridge	171:3a7713b1edbc	87
AnnaBridge	171:3a7713b1edbc	88	/**
AnnaBridge	171:3a7713b1edbc	89	* @brief LL GPIO Init Structure definition
AnnaBridge	171:3a7713b1edbc	90	*/
AnnaBridge	171:3a7713b1edbc	91	typedef struct
AnnaBridge	171:3a7713b1edbc	92	{
AnnaBridge	171:3a7713b1edbc	93	uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
AnnaBridge	171:3a7713b1edbc	94	This parameter can be any value of @ref GPIO_LL_EC_PIN */
AnnaBridge	171:3a7713b1edbc	95
AnnaBridge	171:3a7713b1edbc	96	uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
AnnaBridge	171:3a7713b1edbc	97	This parameter can be a value of @ref GPIO_LL_EC_MODE.
AnnaBridge	171:3a7713b1edbc	98
AnnaBridge	171:3a7713b1edbc	99	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
AnnaBridge	171:3a7713b1edbc	100
AnnaBridge	171:3a7713b1edbc	101	uint32_t Speed; /*!< Specifies the speed for the selected pins.
AnnaBridge	171:3a7713b1edbc	102	This parameter can be a value of @ref GPIO_LL_EC_SPEED.
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
AnnaBridge	171:3a7713b1edbc	105
AnnaBridge	171:3a7713b1edbc	106	uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
AnnaBridge	171:3a7713b1edbc	107	This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
AnnaBridge	171:3a7713b1edbc	108
AnnaBridge	171:3a7713b1edbc	109	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
AnnaBridge	171:3a7713b1edbc	110
AnnaBridge	171:3a7713b1edbc	111	uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
AnnaBridge	171:3a7713b1edbc	112	This parameter can be a value of @ref GPIO_LL_EC_PULL.
AnnaBridge	171:3a7713b1edbc	113
AnnaBridge	171:3a7713b1edbc	114	GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
AnnaBridge	171:3a7713b1edbc	115	} LL_GPIO_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	116
AnnaBridge	171:3a7713b1edbc	117	/**
AnnaBridge	171:3a7713b1edbc	118	* @}
AnnaBridge	171:3a7713b1edbc	119	*/
AnnaBridge	171:3a7713b1edbc	120	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	121
AnnaBridge	171:3a7713b1edbc	122	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	123	/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
AnnaBridge	171:3a7713b1edbc	124	* @{
AnnaBridge	171:3a7713b1edbc	125	*/
AnnaBridge	171:3a7713b1edbc	126
AnnaBridge	171:3a7713b1edbc	127	/** @defgroup GPIO_LL_EC_PIN PIN
AnnaBridge	171:3a7713b1edbc	128	* @{
AnnaBridge	171:3a7713b1edbc	129	*/
AnnaBridge	171:3a7713b1edbc	130	#define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) \| 0x00000001U) /!< Select pin 0 /
AnnaBridge	171:3a7713b1edbc	131	#define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) \| 0x00000002U) /!< Select pin 1 /
AnnaBridge	171:3a7713b1edbc	132	#define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) \| 0x00000004U) /!< Select pin 2 /
AnnaBridge	171:3a7713b1edbc	133	#define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) \| 0x00000008U) /!< Select pin 3 /
AnnaBridge	171:3a7713b1edbc	134	#define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) \| 0x00000010U) /!< Select pin 4 /
AnnaBridge	171:3a7713b1edbc	135	#define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) \| 0x00000020U) /!< Select pin 5 /
AnnaBridge	171:3a7713b1edbc	136	#define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) \| 0x00000040U) /!< Select pin 6 /
AnnaBridge	171:3a7713b1edbc	137	#define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) \| 0x00000080U) /!< Select pin 7 /
AnnaBridge	171:3a7713b1edbc	138	#define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) \| 0x04000001U) /!< Select pin 8 /
AnnaBridge	171:3a7713b1edbc	139	#define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) \| 0x04000002U) /!< Select pin 9 /
AnnaBridge	171:3a7713b1edbc	140	#define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) \| 0x04000004U) /!< Select pin 10 /
AnnaBridge	171:3a7713b1edbc	141	#define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) \| 0x04000008U) /!< Select pin 11 /
AnnaBridge	171:3a7713b1edbc	142	#define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) \| 0x04000010U) /!< Select pin 12 /
AnnaBridge	171:3a7713b1edbc	143	#define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) \| 0x04000020U) /!< Select pin 13 /
AnnaBridge	171:3a7713b1edbc	144	#define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) \| 0x04000040U) /!< Select pin 14 /
AnnaBridge	171:3a7713b1edbc	145	#define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) \| 0x04000080U) /!< Select pin 15 /
AnnaBridge	171:3a7713b1edbc	146	#define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 \| LL_GPIO_PIN_1 \| LL_GPIO_PIN_2 \| \
AnnaBridge	171:3a7713b1edbc	147	LL_GPIO_PIN_3 \| LL_GPIO_PIN_4 \| LL_GPIO_PIN_5 \| \
AnnaBridge	171:3a7713b1edbc	148	LL_GPIO_PIN_6 \| LL_GPIO_PIN_7 \| LL_GPIO_PIN_8 \| \
AnnaBridge	171:3a7713b1edbc	149	LL_GPIO_PIN_9 \| LL_GPIO_PIN_10 \| LL_GPIO_PIN_11 \| \
AnnaBridge	171:3a7713b1edbc	150	LL_GPIO_PIN_12 \| LL_GPIO_PIN_13 \| LL_GPIO_PIN_14 \| \
AnnaBridge	171:3a7713b1edbc	151	LL_GPIO_PIN_15) /!< Select all pins /
AnnaBridge	171:3a7713b1edbc	152	/**
AnnaBridge	171:3a7713b1edbc	153	* @}
AnnaBridge	171:3a7713b1edbc	154	*/
AnnaBridge	171:3a7713b1edbc	155
AnnaBridge	171:3a7713b1edbc	156	/** @defgroup GPIO_LL_EC_MODE Mode
AnnaBridge	171:3a7713b1edbc	157	* @{
AnnaBridge	171:3a7713b1edbc	158	*/
AnnaBridge	171:3a7713b1edbc	159	#define LL_GPIO_MODE_ANALOG 0x00000000U /!< Select analog mode /
AnnaBridge	171:3a7713b1edbc	160	#define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /!< Select floating mode /
AnnaBridge	171:3a7713b1edbc	161	#define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /!< Select input mode /
AnnaBridge	171:3a7713b1edbc	162	#define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /!< Select general purpose output mode /
AnnaBridge	171:3a7713b1edbc	163	#define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 \| GPIO_CRL_MODE0_0) /!< Select alternate function mode /
AnnaBridge	171:3a7713b1edbc	164	/**
AnnaBridge	171:3a7713b1edbc	165	* @}
AnnaBridge	171:3a7713b1edbc	166	*/
AnnaBridge	171:3a7713b1edbc	167
AnnaBridge	171:3a7713b1edbc	168	/** @defgroup GPIO_LL_EC_OUTPUT Output Type
AnnaBridge	171:3a7713b1edbc	169	* @{
AnnaBridge	171:3a7713b1edbc	170	*/
AnnaBridge	171:3a7713b1edbc	171	#define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /!< Select push-pull as output type /
AnnaBridge	171:3a7713b1edbc	172	#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /!< Select open-drain as output type /
AnnaBridge	171:3a7713b1edbc	173	/**
AnnaBridge	171:3a7713b1edbc	174	* @}
AnnaBridge	171:3a7713b1edbc	175	*/
AnnaBridge	171:3a7713b1edbc	176
AnnaBridge	171:3a7713b1edbc	177	/** @defgroup GPIO_LL_EC_SPEED Output Speed
AnnaBridge	171:3a7713b1edbc	178	* @{
AnnaBridge	171:3a7713b1edbc	179	*/
AnnaBridge	171:3a7713b1edbc	180	#define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /!< Select Output mode, max speed 10 MHz /
AnnaBridge	171:3a7713b1edbc	181	#define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /!< Select Output mode, max speed 20 MHz /
AnnaBridge	171:3a7713b1edbc	182	#define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /!< Select Output mode, max speed 50 MHz /
AnnaBridge	171:3a7713b1edbc	183	/**
AnnaBridge	171:3a7713b1edbc	184	* @}
AnnaBridge	171:3a7713b1edbc	185	*/
AnnaBridge	171:3a7713b1edbc	186
AnnaBridge	171:3a7713b1edbc	187	#define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /!< Select I/O low output speed /
AnnaBridge	171:3a7713b1edbc	188	#define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /!< Select I/O medium output speed /
AnnaBridge	171:3a7713b1edbc	189	#define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /!< Select I/O high output speed /
AnnaBridge	171:3a7713b1edbc	190
AnnaBridge	171:3a7713b1edbc	191	/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
AnnaBridge	171:3a7713b1edbc	192	* @{
AnnaBridge	171:3a7713b1edbc	193	*/
AnnaBridge	171:3a7713b1edbc	194	#define LL_GPIO_PULL_DOWN 0x00000000U /!< Select I/O pull down /
AnnaBridge	171:3a7713b1edbc	195	#define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /!< Select I/O pull up /
AnnaBridge	171:3a7713b1edbc	196
AnnaBridge	171:3a7713b1edbc	197	/**
AnnaBridge	171:3a7713b1edbc	198	* @}
AnnaBridge	171:3a7713b1edbc	199	*/
AnnaBridge	171:3a7713b1edbc	200
AnnaBridge	171:3a7713b1edbc	201	/** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
AnnaBridge	171:3a7713b1edbc	202	* @{
AnnaBridge	171:3a7713b1edbc	203	*/
AnnaBridge	171:3a7713b1edbc	204
AnnaBridge	171:3a7713b1edbc	205	#define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /!< EVENTOUT on pin 0 /
AnnaBridge	171:3a7713b1edbc	206	#define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /!< EVENTOUT on pin 1 /
AnnaBridge	171:3a7713b1edbc	207	#define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /!< EVENTOUT on pin 2 /
AnnaBridge	171:3a7713b1edbc	208	#define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /!< EVENTOUT on pin 3 /
AnnaBridge	171:3a7713b1edbc	209	#define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /!< EVENTOUT on pin 4 /
AnnaBridge	171:3a7713b1edbc	210	#define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /!< EVENTOUT on pin 5 /
AnnaBridge	171:3a7713b1edbc	211	#define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /!< EVENTOUT on pin 6 /
AnnaBridge	171:3a7713b1edbc	212	#define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /!< EVENTOUT on pin 7 /
AnnaBridge	171:3a7713b1edbc	213	#define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /!< EVENTOUT on pin 8 /
AnnaBridge	171:3a7713b1edbc	214	#define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /!< EVENTOUT on pin 9 /
AnnaBridge	171:3a7713b1edbc	215	#define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /!< EVENTOUT on pin 10 /
AnnaBridge	171:3a7713b1edbc	216	#define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /!< EVENTOUT on pin 11 /
AnnaBridge	171:3a7713b1edbc	217	#define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /!< EVENTOUT on pin 12 /
AnnaBridge	171:3a7713b1edbc	218	#define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /!< EVENTOUT on pin 13 /
AnnaBridge	171:3a7713b1edbc	219	#define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /!< EVENTOUT on pin 14 /
AnnaBridge	171:3a7713b1edbc	220	#define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /!< EVENTOUT on pin 15 /
AnnaBridge	171:3a7713b1edbc	221
AnnaBridge	171:3a7713b1edbc	222	/**
AnnaBridge	171:3a7713b1edbc	223	* @}
AnnaBridge	171:3a7713b1edbc	224	*/
AnnaBridge	171:3a7713b1edbc	225
AnnaBridge	171:3a7713b1edbc	226	/** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
AnnaBridge	171:3a7713b1edbc	227	* @{
AnnaBridge	171:3a7713b1edbc	228	*/
AnnaBridge	171:3a7713b1edbc	229
AnnaBridge	171:3a7713b1edbc	230	#define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /!< EVENTOUT on port A /
AnnaBridge	171:3a7713b1edbc	231	#define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /!< EVENTOUT on port B /
AnnaBridge	171:3a7713b1edbc	232	#define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /!< EVENTOUT on port C /
AnnaBridge	171:3a7713b1edbc	233	#define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /!< EVENTOUT on port D /
AnnaBridge	171:3a7713b1edbc	234	#define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /!< EVENTOUT on port E /
AnnaBridge	171:3a7713b1edbc	235
AnnaBridge	171:3a7713b1edbc	236	/**
AnnaBridge	171:3a7713b1edbc	237	* @}
AnnaBridge	171:3a7713b1edbc	238	*/
AnnaBridge	171:3a7713b1edbc	239
AnnaBridge	171:3a7713b1edbc	240	/** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
AnnaBridge	171:3a7713b1edbc	241	* @{
AnnaBridge	171:3a7713b1edbc	242	*/
AnnaBridge	171:3a7713b1edbc	243	#define LL_GPIO_AF_EXTI_PORTA 0U /!< EXTI PORT A /
AnnaBridge	171:3a7713b1edbc	244	#define LL_GPIO_AF_EXTI_PORTB 1U /!< EXTI PORT B /
AnnaBridge	171:3a7713b1edbc	245	#define LL_GPIO_AF_EXTI_PORTC 2U /!< EXTI PORT C /
AnnaBridge	171:3a7713b1edbc	246	#define LL_GPIO_AF_EXTI_PORTD 3U /!< EXTI PORT D /
AnnaBridge	171:3a7713b1edbc	247	#define LL_GPIO_AF_EXTI_PORTE 4U /!< EXTI PORT E /
AnnaBridge	171:3a7713b1edbc	248	#define LL_GPIO_AF_EXTI_PORTF 5U /!< EXTI PORT F /
AnnaBridge	171:3a7713b1edbc	249	#define LL_GPIO_AF_EXTI_PORTG 6U /!< EXTI PORT G /
AnnaBridge	171:3a7713b1edbc	250	/**
AnnaBridge	171:3a7713b1edbc	251	* @}
AnnaBridge	171:3a7713b1edbc	252	*/
AnnaBridge	171:3a7713b1edbc	253
AnnaBridge	171:3a7713b1edbc	254	/** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
AnnaBridge	171:3a7713b1edbc	255	* @{
AnnaBridge	171:3a7713b1edbc	256	*/
AnnaBridge	171:3a7713b1edbc	257	#define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U \| 0U) /!< EXTI_POSITION_0 \| EXTICR[0] /
AnnaBridge	171:3a7713b1edbc	258	#define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U \| 0U) /!< EXTI_POSITION_4 \| EXTICR[0] /
AnnaBridge	171:3a7713b1edbc	259	#define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U \| 0U) /!< EXTI_POSITION_8 \| EXTICR[0] /
AnnaBridge	171:3a7713b1edbc	260	#define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U \| 0U) /!< EXTI_POSITION_12 \| EXTICR[0] /
AnnaBridge	171:3a7713b1edbc	261	#define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U \| 1U) /!< EXTI_POSITION_0 \| EXTICR[1] /
AnnaBridge	171:3a7713b1edbc	262	#define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U \| 1U) /!< EXTI_POSITION_4 \| EXTICR[1] /
AnnaBridge	171:3a7713b1edbc	263	#define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U \| 1U) /!< EXTI_POSITION_8 \| EXTICR[1] /
AnnaBridge	171:3a7713b1edbc	264	#define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U \| 1U) /!< EXTI_POSITION_12 \| EXTICR[1] /
AnnaBridge	171:3a7713b1edbc	265	#define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U \| 2U) /!< EXTI_POSITION_0 \| EXTICR[2] /
AnnaBridge	171:3a7713b1edbc	266	#define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U \| 2U) /!< EXTI_POSITION_4 \| EXTICR[2] /
AnnaBridge	171:3a7713b1edbc	267	#define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U \| 2U) /!< EXTI_POSITION_8 \| EXTICR[2] /
AnnaBridge	171:3a7713b1edbc	268	#define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U \| 2U) /!< EXTI_POSITION_12 \| EXTICR[2] /
AnnaBridge	171:3a7713b1edbc	269	#define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U \| 3U) /!< EXTI_POSITION_0 \| EXTICR[3] /
AnnaBridge	171:3a7713b1edbc	270	#define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U \| 3U) /!< EXTI_POSITION_4 \| EXTICR[3] /
AnnaBridge	171:3a7713b1edbc	271	#define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U \| 3U) /!< EXTI_POSITION_8 \| EXTICR[3] /
AnnaBridge	171:3a7713b1edbc	272	#define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U \| 3U) /!< EXTI_POSITION_12 \| EXTICR[3] /
AnnaBridge	171:3a7713b1edbc	273	/**
AnnaBridge	171:3a7713b1edbc	274	* @}
AnnaBridge	171:3a7713b1edbc	275	*/
AnnaBridge	171:3a7713b1edbc	276
AnnaBridge	171:3a7713b1edbc	277	/**
AnnaBridge	171:3a7713b1edbc	278	* @}
AnnaBridge	171:3a7713b1edbc	279	*/
AnnaBridge	171:3a7713b1edbc	280
AnnaBridge	171:3a7713b1edbc	281	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	282	/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
AnnaBridge	171:3a7713b1edbc	283	* @{
AnnaBridge	171:3a7713b1edbc	284	*/
AnnaBridge	171:3a7713b1edbc	285
AnnaBridge	171:3a7713b1edbc	286	/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	171:3a7713b1edbc	287	* @{
AnnaBridge	171:3a7713b1edbc	288	*/
AnnaBridge	171:3a7713b1edbc	289
AnnaBridge	171:3a7713b1edbc	290	/**
AnnaBridge	171:3a7713b1edbc	291	* @brief Write a value in GPIO register
AnnaBridge	171:3a7713b1edbc	292	* @param __INSTANCE__ GPIO Instance
AnnaBridge	171:3a7713b1edbc	293	* @param __REG__ Register to be written
AnnaBridge	171:3a7713b1edbc	294	* @param __VALUE__ Value to be written in the register
AnnaBridge	171:3a7713b1edbc	295	* @retval None
AnnaBridge	171:3a7713b1edbc	296	*/
AnnaBridge	171:3a7713b1edbc	297	#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	171:3a7713b1edbc	298
AnnaBridge	171:3a7713b1edbc	299	/**
AnnaBridge	171:3a7713b1edbc	300	* @brief Read a value in GPIO register
AnnaBridge	171:3a7713b1edbc	301	* @param __INSTANCE__ GPIO Instance
AnnaBridge	171:3a7713b1edbc	302	* @param __REG__ Register to be read
AnnaBridge	171:3a7713b1edbc	303	* @retval Register value
AnnaBridge	171:3a7713b1edbc	304	*/
AnnaBridge	171:3a7713b1edbc	305	#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	171:3a7713b1edbc	306	/**
AnnaBridge	171:3a7713b1edbc	307	* @}
AnnaBridge	171:3a7713b1edbc	308	*/
AnnaBridge	171:3a7713b1edbc	309
AnnaBridge	171:3a7713b1edbc	310	/**
AnnaBridge	171:3a7713b1edbc	311	* @}
AnnaBridge	171:3a7713b1edbc	312	*/
AnnaBridge	171:3a7713b1edbc	313
AnnaBridge	171:3a7713b1edbc	314	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	315	/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
AnnaBridge	171:3a7713b1edbc	316	* @{
AnnaBridge	171:3a7713b1edbc	317	*/
AnnaBridge	171:3a7713b1edbc	318
AnnaBridge	171:3a7713b1edbc	319	/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
AnnaBridge	171:3a7713b1edbc	320	* @{
AnnaBridge	171:3a7713b1edbc	321	*/
AnnaBridge	171:3a7713b1edbc	322
AnnaBridge	171:3a7713b1edbc	323	/**
AnnaBridge	171:3a7713b1edbc	324	* @brief Configure gpio mode for a dedicated pin on dedicated port.
AnnaBridge	171:3a7713b1edbc	325	* @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
AnnaBridge	171:3a7713b1edbc	326	* Alternate function Output.
AnnaBridge	171:3a7713b1edbc	327	* @note Warning: only one pin can be passed as parameter.
AnnaBridge	171:3a7713b1edbc	328	* @rmtoll CRL CNFy LL_GPIO_SetPinMode
AnnaBridge	171:3a7713b1edbc	329	* @rmtoll CRL MODEy LL_GPIO_SetPinMode
AnnaBridge	171:3a7713b1edbc	330	* @rmtoll CRH CNFy LL_GPIO_SetPinMode
AnnaBridge	171:3a7713b1edbc	331	* @rmtoll CRH MODEy LL_GPIO_SetPinMode
AnnaBridge	171:3a7713b1edbc	332	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	333	* @param Pin This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	334	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	335	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	336	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	337	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	338	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	339	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	340	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	341	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	342	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	343	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	344	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	345	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	346	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	347	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	348	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	349	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	350	* @param Mode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	351	* @arg @ref LL_GPIO_MODE_ANALOG
AnnaBridge	171:3a7713b1edbc	352	* @arg @ref LL_GPIO_MODE_FLOATING
AnnaBridge	171:3a7713b1edbc	353	* @arg @ref LL_GPIO_MODE_INPUT
AnnaBridge	171:3a7713b1edbc	354	* @arg @ref LL_GPIO_MODE_OUTPUT
AnnaBridge	171:3a7713b1edbc	355	* @arg @ref LL_GPIO_MODE_ALTERNATE
AnnaBridge	171:3a7713b1edbc	356	* @retval None
AnnaBridge	171:3a7713b1edbc	357	*/
AnnaBridge	171:3a7713b1edbc	358	__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
AnnaBridge	171:3a7713b1edbc	359	{
AnnaBridge	171:3a7713b1edbc	360	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
AnnaBridge	171:3a7713b1edbc	361	MODIFY_REG(pReg, ((GPIO_CRL_CNF0 \| GPIO_CRL_MODE0) << (POSITION_VAL(Pin) 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
AnnaBridge	171:3a7713b1edbc	362	}
AnnaBridge	171:3a7713b1edbc	363
AnnaBridge	171:3a7713b1edbc	364	/**
AnnaBridge	171:3a7713b1edbc	365	* @brief Return gpio mode for a dedicated pin on dedicated port.
AnnaBridge	171:3a7713b1edbc	366	* @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
AnnaBridge	171:3a7713b1edbc	367	* Alternate function Output.
AnnaBridge	171:3a7713b1edbc	368	* @note Warning: only one pin can be passed as parameter.
AnnaBridge	171:3a7713b1edbc	369	* @rmtoll CRL CNFy LL_GPIO_GetPinMode
AnnaBridge	171:3a7713b1edbc	370	* @rmtoll CRL MODEy LL_GPIO_GetPinMode
AnnaBridge	171:3a7713b1edbc	371	* @rmtoll CRH CNFy LL_GPIO_GetPinMode
AnnaBridge	171:3a7713b1edbc	372	* @rmtoll CRH MODEy LL_GPIO_GetPinMode
AnnaBridge	171:3a7713b1edbc	373	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	374	* @param Pin This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	375	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	376	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	377	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	378	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	379	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	380	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	381	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	382	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	383	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	384	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	385	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	386	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	387	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	388	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	389	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	390	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	391	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	392	* @arg @ref LL_GPIO_MODE_ANALOG
AnnaBridge	171:3a7713b1edbc	393	* @arg @ref LL_GPIO_MODE_FLOATING
AnnaBridge	171:3a7713b1edbc	394	* @arg @ref LL_GPIO_MODE_INPUT
AnnaBridge	171:3a7713b1edbc	395	* @arg @ref LL_GPIO_MODE_OUTPUT
AnnaBridge	171:3a7713b1edbc	396	* @arg @ref LL_GPIO_MODE_ALTERNATE
AnnaBridge	171:3a7713b1edbc	397	*/
AnnaBridge	171:3a7713b1edbc	398	__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	399	{
AnnaBridge	171:3a7713b1edbc	400	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
AnnaBridge	171:3a7713b1edbc	401	return (READ_BIT(pReg, ((GPIO_CRL_CNF0 \| GPIO_CRL_MODE0) << (POSITION_VAL(Pin) 4U))) >> (POSITION_VAL(Pin) * 4U));
AnnaBridge	171:3a7713b1edbc	402	}
AnnaBridge	171:3a7713b1edbc	403
AnnaBridge	171:3a7713b1edbc	404	/**
AnnaBridge	171:3a7713b1edbc	405	* @brief Configure gpio speed for a dedicated pin on dedicated port.
AnnaBridge	171:3a7713b1edbc	406	* @note I/O speed can be Low, Medium or Fast speed.
AnnaBridge	171:3a7713b1edbc	407	* @note Warning: only one pin can be passed as parameter.
AnnaBridge	171:3a7713b1edbc	408	* @note Refer to datasheet for frequency specifications and the power
AnnaBridge	171:3a7713b1edbc	409	* supply and load conditions for each speed.
AnnaBridge	171:3a7713b1edbc	410	* @rmtoll CRL MODEy LL_GPIO_SetPinSpeed
AnnaBridge	171:3a7713b1edbc	411	* @rmtoll CRH MODEy LL_GPIO_SetPinSpeed
AnnaBridge	171:3a7713b1edbc	412	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	413	* @param Pin This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	414	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	415	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	416	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	417	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	418	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	419	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	420	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	421	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	422	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	423	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	424	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	425	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	426	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	427	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	428	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	429	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	430	* @param Speed This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	431	* @arg @ref LL_GPIO_SPEED_FREQ_LOW
AnnaBridge	171:3a7713b1edbc	432	* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
AnnaBridge	171:3a7713b1edbc	433	* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
AnnaBridge	171:3a7713b1edbc	434	* @retval None
AnnaBridge	171:3a7713b1edbc	435	*/
AnnaBridge	171:3a7713b1edbc	436	__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
AnnaBridge	171:3a7713b1edbc	437	{
AnnaBridge	171:3a7713b1edbc	438	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
AnnaBridge	171:3a7713b1edbc	439	MODIFY_REG(pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) 4U)),
AnnaBridge	171:3a7713b1edbc	440	(Speed << (POSITION_VAL(Pin) * 4U)));
AnnaBridge	171:3a7713b1edbc	441	}
AnnaBridge	171:3a7713b1edbc	442
AnnaBridge	171:3a7713b1edbc	443	/**
AnnaBridge	171:3a7713b1edbc	444	* @brief Return gpio speed for a dedicated pin on dedicated port.
AnnaBridge	171:3a7713b1edbc	445	* @note I/O speed can be Low, Medium, Fast or High speed.
AnnaBridge	171:3a7713b1edbc	446	* @note Warning: only one pin can be passed as parameter.
AnnaBridge	171:3a7713b1edbc	447	* @note Refer to datasheet for frequency specifications and the power
AnnaBridge	171:3a7713b1edbc	448	* supply and load conditions for each speed.
AnnaBridge	171:3a7713b1edbc	449	* @rmtoll CRL MODEy LL_GPIO_GetPinSpeed
AnnaBridge	171:3a7713b1edbc	450	* @rmtoll CRH MODEy LL_GPIO_GetPinSpeed
AnnaBridge	171:3a7713b1edbc	451	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	452	* @param Pin This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	453	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	454	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	455	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	456	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	457	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	458	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	459	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	460	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	461	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	462	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	463	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	464	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	465	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	466	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	467	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	468	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	469	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	470	* @arg @ref LL_GPIO_SPEED_FREQ_LOW
AnnaBridge	171:3a7713b1edbc	471	* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
AnnaBridge	171:3a7713b1edbc	472	* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
AnnaBridge	171:3a7713b1edbc	473	*/
AnnaBridge	171:3a7713b1edbc	474	__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	475	{
AnnaBridge	171:3a7713b1edbc	476	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
AnnaBridge	171:3a7713b1edbc	477	return (READ_BIT(pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) 4U))) >> (POSITION_VAL(Pin) * 4U));
AnnaBridge	171:3a7713b1edbc	478	}
AnnaBridge	171:3a7713b1edbc	479
AnnaBridge	171:3a7713b1edbc	480	/**
AnnaBridge	171:3a7713b1edbc	481	* @brief Configure gpio output type for several pins on dedicated port.
AnnaBridge	171:3a7713b1edbc	482	* @note Output type as to be set when gpio pin is in output or
AnnaBridge	171:3a7713b1edbc	483	* alternate modes. Possible type are Push-pull or Open-drain.
AnnaBridge	171:3a7713b1edbc	484	* @rmtoll CRL MODEy LL_GPIO_SetPinOutputType
AnnaBridge	171:3a7713b1edbc	485	* @rmtoll CRH MODEy LL_GPIO_SetPinOutputType
AnnaBridge	171:3a7713b1edbc	486	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	487	* @param Pin This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	488	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	489	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	490	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	491	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	492	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	493	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	494	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	495	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	496	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	497	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	498	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	499	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	500	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	501	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	502	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	503	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	504	* @arg @ref LL_GPIO_PIN_ALL
AnnaBridge	171:3a7713b1edbc	505	* @param OutputType This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	506	* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
AnnaBridge	171:3a7713b1edbc	507	* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
AnnaBridge	171:3a7713b1edbc	508	* @retval None
AnnaBridge	171:3a7713b1edbc	509	*/
AnnaBridge	171:3a7713b1edbc	510	__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
AnnaBridge	171:3a7713b1edbc	511	{
AnnaBridge	171:3a7713b1edbc	512	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
AnnaBridge	171:3a7713b1edbc	513	MODIFY_REG(pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) 4U)),
AnnaBridge	171:3a7713b1edbc	514	(OutputType << (POSITION_VAL(Pin) * 4U)));
AnnaBridge	171:3a7713b1edbc	515	}
AnnaBridge	171:3a7713b1edbc	516
AnnaBridge	171:3a7713b1edbc	517	/**
AnnaBridge	171:3a7713b1edbc	518	* @brief Return gpio output type for several pins on dedicated port.
AnnaBridge	171:3a7713b1edbc	519	* @note Output type as to be set when gpio pin is in output or
AnnaBridge	171:3a7713b1edbc	520	* alternate modes. Possible type are Push-pull or Open-drain.
AnnaBridge	171:3a7713b1edbc	521	* @note Warning: only one pin can be passed as parameter.
AnnaBridge	171:3a7713b1edbc	522	* @rmtoll CRL MODEy LL_GPIO_GetPinOutputType
AnnaBridge	171:3a7713b1edbc	523	* @rmtoll CRH MODEy LL_GPIO_GetPinOutputType
AnnaBridge	171:3a7713b1edbc	524	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	525	* @param Pin This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	526	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	527	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	528	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	529	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	530	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	531	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	532	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	533	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	534	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	535	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	536	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	537	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	538	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	539	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	540	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	541	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	542	* @arg @ref LL_GPIO_PIN_ALL
AnnaBridge	171:3a7713b1edbc	543	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	544	* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
AnnaBridge	171:3a7713b1edbc	545	* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
AnnaBridge	171:3a7713b1edbc	546	*/
AnnaBridge	171:3a7713b1edbc	547	__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	548	{
AnnaBridge	171:3a7713b1edbc	549	register uint32_t pReg = (uint32_t )((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
AnnaBridge	171:3a7713b1edbc	550	return (READ_BIT(pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) 4U))) >> (POSITION_VAL(Pin) * 4U));
AnnaBridge	171:3a7713b1edbc	551
AnnaBridge	171:3a7713b1edbc	552	}
AnnaBridge	171:3a7713b1edbc	553
AnnaBridge	171:3a7713b1edbc	554	/**
AnnaBridge	171:3a7713b1edbc	555	* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
AnnaBridge	171:3a7713b1edbc	556	* @note Warning: only one pin can be passed as parameter.
AnnaBridge	171:3a7713b1edbc	557	* @rmtoll ODR ODR LL_GPIO_SetPinPull
AnnaBridge	171:3a7713b1edbc	558	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	559	* @param Pin This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	560	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	561	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	562	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	563	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	564	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	565	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	566	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	567	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	568	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	569	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	570	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	571	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	572	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	573	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	574	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	575	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	576	* @param Pull This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	577	* @arg @ref LL_GPIO_PULL_DOWN
AnnaBridge	171:3a7713b1edbc	578	* @arg @ref LL_GPIO_PULL_UP
AnnaBridge	171:3a7713b1edbc	579	* @retval None
AnnaBridge	171:3a7713b1edbc	580	*/
AnnaBridge	171:3a7713b1edbc	581	__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
AnnaBridge	171:3a7713b1edbc	582	{
AnnaBridge	171:3a7713b1edbc	583	MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
AnnaBridge	171:3a7713b1edbc	584	}
AnnaBridge	171:3a7713b1edbc	585
AnnaBridge	171:3a7713b1edbc	586	/**
AnnaBridge	171:3a7713b1edbc	587	* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
AnnaBridge	171:3a7713b1edbc	588	* @note Warning: only one pin can be passed as parameter.
AnnaBridge	171:3a7713b1edbc	589	* @rmtoll ODR ODR LL_GPIO_GetPinPull
AnnaBridge	171:3a7713b1edbc	590	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	591	* @param Pin This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	592	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	593	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	594	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	595	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	596	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	597	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	598	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	599	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	600	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	601	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	602	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	603	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	604	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	605	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	606	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	607	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	608	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	609	* @arg @ref LL_GPIO_PULL_DOWN
AnnaBridge	171:3a7713b1edbc	610	* @arg @ref LL_GPIO_PULL_UP
AnnaBridge	171:3a7713b1edbc	611	*/
AnnaBridge	171:3a7713b1edbc	612	__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	613	{
AnnaBridge	171:3a7713b1edbc	614	return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
AnnaBridge	171:3a7713b1edbc	615	}
AnnaBridge	171:3a7713b1edbc	616
AnnaBridge	171:3a7713b1edbc	617	/**
AnnaBridge	171:3a7713b1edbc	618	* @brief Lock configuration of several pins for a dedicated port.
AnnaBridge	171:3a7713b1edbc	619	* @note When the lock sequence has been applied on a port bit, the
AnnaBridge	171:3a7713b1edbc	620	* value of this port bit can no longer be modified until the
AnnaBridge	171:3a7713b1edbc	621	* next reset.
AnnaBridge	171:3a7713b1edbc	622	* @note Each lock bit freezes a specific configuration register
AnnaBridge	171:3a7713b1edbc	623	* (control and alternate function registers).
AnnaBridge	171:3a7713b1edbc	624	* @rmtoll LCKR LCKK LL_GPIO_LockPin
AnnaBridge	171:3a7713b1edbc	625	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	626	* @param PinMask This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	627	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	628	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	629	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	630	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	631	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	632	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	633	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	634	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	635	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	636	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	637	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	638	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	639	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	640	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	641	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	642	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	643	* @arg @ref LL_GPIO_PIN_ALL
AnnaBridge	171:3a7713b1edbc	644	* @retval None
AnnaBridge	171:3a7713b1edbc	645	*/
AnnaBridge	171:3a7713b1edbc	646	__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
AnnaBridge	171:3a7713b1edbc	647	{
AnnaBridge	171:3a7713b1edbc	648	__IO uint32_t temp;
AnnaBridge	171:3a7713b1edbc	649	WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK \| ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
AnnaBridge	171:3a7713b1edbc	650	WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
AnnaBridge	171:3a7713b1edbc	651	WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK \| ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
AnnaBridge	171:3a7713b1edbc	652	temp = READ_REG(GPIOx->LCKR);
AnnaBridge	171:3a7713b1edbc	653	(void) temp;
AnnaBridge	171:3a7713b1edbc	654	}
AnnaBridge	171:3a7713b1edbc	655
AnnaBridge	171:3a7713b1edbc	656	/**
AnnaBridge	171:3a7713b1edbc	657	* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
AnnaBridge	171:3a7713b1edbc	658	* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
AnnaBridge	171:3a7713b1edbc	659	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	660	* @param PinMask This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	661	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	662	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	663	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	664	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	665	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	666	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	667	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	668	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	669	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	670	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	671	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	672	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	673	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	674	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	675	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	676	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	677	* @arg @ref LL_GPIO_PIN_ALL
AnnaBridge	171:3a7713b1edbc	678	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	679	*/
AnnaBridge	171:3a7713b1edbc	680	__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
AnnaBridge	171:3a7713b1edbc	681	{
AnnaBridge	171:3a7713b1edbc	682	return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
AnnaBridge	171:3a7713b1edbc	683	}
AnnaBridge	171:3a7713b1edbc	684
AnnaBridge	171:3a7713b1edbc	685	/**
AnnaBridge	171:3a7713b1edbc	686	* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
AnnaBridge	171:3a7713b1edbc	687	* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
AnnaBridge	171:3a7713b1edbc	688	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	689	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	690	*/
AnnaBridge	171:3a7713b1edbc	691	__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
AnnaBridge	171:3a7713b1edbc	692	{
AnnaBridge	171:3a7713b1edbc	693	return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
AnnaBridge	171:3a7713b1edbc	694	}
AnnaBridge	171:3a7713b1edbc	695
AnnaBridge	171:3a7713b1edbc	696	/**
AnnaBridge	171:3a7713b1edbc	697	* @}
AnnaBridge	171:3a7713b1edbc	698	*/
AnnaBridge	171:3a7713b1edbc	699
AnnaBridge	171:3a7713b1edbc	700	/** @defgroup GPIO_LL_EF_Data_Access Data Access
AnnaBridge	171:3a7713b1edbc	701	* @{
AnnaBridge	171:3a7713b1edbc	702	*/
AnnaBridge	171:3a7713b1edbc	703
AnnaBridge	171:3a7713b1edbc	704	/**
AnnaBridge	171:3a7713b1edbc	705	* @brief Return full input data register value for a dedicated port.
AnnaBridge	171:3a7713b1edbc	706	* @rmtoll IDR IDy LL_GPIO_ReadInputPort
AnnaBridge	171:3a7713b1edbc	707	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	708	* @retval Input data register value of port
AnnaBridge	171:3a7713b1edbc	709	*/
AnnaBridge	171:3a7713b1edbc	710	__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
AnnaBridge	171:3a7713b1edbc	711	{
AnnaBridge	171:3a7713b1edbc	712	return (READ_REG(GPIOx->IDR));
AnnaBridge	171:3a7713b1edbc	713	}
AnnaBridge	171:3a7713b1edbc	714
AnnaBridge	171:3a7713b1edbc	715	/**
AnnaBridge	171:3a7713b1edbc	716	* @brief Return if input data level for several pins of dedicated port is high or low.
AnnaBridge	171:3a7713b1edbc	717	* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
AnnaBridge	171:3a7713b1edbc	718	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	719	* @param PinMask This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	720	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	721	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	722	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	723	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	724	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	725	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	726	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	727	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	728	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	729	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	730	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	731	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	732	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	733	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	734	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	735	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	736	* @arg @ref LL_GPIO_PIN_ALL
AnnaBridge	171:3a7713b1edbc	737	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	738	*/
AnnaBridge	171:3a7713b1edbc	739	__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
AnnaBridge	171:3a7713b1edbc	740	{
AnnaBridge	171:3a7713b1edbc	741	return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
AnnaBridge	171:3a7713b1edbc	742	}
AnnaBridge	171:3a7713b1edbc	743
AnnaBridge	171:3a7713b1edbc	744	/**
AnnaBridge	171:3a7713b1edbc	745	* @brief Write output data register for the port.
AnnaBridge	171:3a7713b1edbc	746	* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
AnnaBridge	171:3a7713b1edbc	747	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	748	* @param PortValue Level value for each pin of the port
AnnaBridge	171:3a7713b1edbc	749	* @retval None
AnnaBridge	171:3a7713b1edbc	750	*/
AnnaBridge	171:3a7713b1edbc	751	__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
AnnaBridge	171:3a7713b1edbc	752	{
AnnaBridge	171:3a7713b1edbc	753	WRITE_REG(GPIOx->ODR, PortValue);
AnnaBridge	171:3a7713b1edbc	754	}
AnnaBridge	171:3a7713b1edbc	755
AnnaBridge	171:3a7713b1edbc	756	/**
AnnaBridge	171:3a7713b1edbc	757	* @brief Return full output data register value for a dedicated port.
AnnaBridge	171:3a7713b1edbc	758	* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
AnnaBridge	171:3a7713b1edbc	759	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	760	* @retval Output data register value of port
AnnaBridge	171:3a7713b1edbc	761	*/
AnnaBridge	171:3a7713b1edbc	762	__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
AnnaBridge	171:3a7713b1edbc	763	{
AnnaBridge	171:3a7713b1edbc	764	return (uint32_t)(READ_REG(GPIOx->ODR));
AnnaBridge	171:3a7713b1edbc	765	}
AnnaBridge	171:3a7713b1edbc	766
AnnaBridge	171:3a7713b1edbc	767	/**
AnnaBridge	171:3a7713b1edbc	768	* @brief Return if input data level for several pins of dedicated port is high or low.
AnnaBridge	171:3a7713b1edbc	769	* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
AnnaBridge	171:3a7713b1edbc	770	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	771	* @param PinMask This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	772	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	773	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	774	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	775	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	776	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	777	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	778	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	779	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	780	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	781	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	782	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	783	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	784	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	785	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	786	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	787	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	788	* @arg @ref LL_GPIO_PIN_ALL
AnnaBridge	171:3a7713b1edbc	789	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	790	*/
AnnaBridge	171:3a7713b1edbc	791	__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
AnnaBridge	171:3a7713b1edbc	792	{
AnnaBridge	171:3a7713b1edbc	793	return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
AnnaBridge	171:3a7713b1edbc	794	}
AnnaBridge	171:3a7713b1edbc	795
AnnaBridge	171:3a7713b1edbc	796	/**
AnnaBridge	171:3a7713b1edbc	797	* @brief Set several pins to high level on dedicated gpio port.
AnnaBridge	171:3a7713b1edbc	798	* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
AnnaBridge	171:3a7713b1edbc	799	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	800	* @param PinMask This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	801	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	802	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	803	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	804	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	805	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	806	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	807	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	808	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	809	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	810	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	811	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	812	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	813	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	814	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	815	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	816	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	817	* @arg @ref LL_GPIO_PIN_ALL
AnnaBridge	171:3a7713b1edbc	818	* @retval None
AnnaBridge	171:3a7713b1edbc	819	*/
AnnaBridge	171:3a7713b1edbc	820	__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
AnnaBridge	171:3a7713b1edbc	821	{
AnnaBridge	171:3a7713b1edbc	822	WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
AnnaBridge	171:3a7713b1edbc	823	}
AnnaBridge	171:3a7713b1edbc	824
AnnaBridge	171:3a7713b1edbc	825	/**
AnnaBridge	171:3a7713b1edbc	826	* @brief Set several pins to low level on dedicated gpio port.
AnnaBridge	171:3a7713b1edbc	827	* @rmtoll BRR BRy LL_GPIO_ResetOutputPin
AnnaBridge	171:3a7713b1edbc	828	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	829	* @param PinMask This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	830	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	831	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	832	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	833	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	834	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	835	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	836	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	837	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	838	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	839	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	840	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	841	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	842	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	843	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	844	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	845	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	846	* @arg @ref LL_GPIO_PIN_ALL
AnnaBridge	171:3a7713b1edbc	847	* @retval None
AnnaBridge	171:3a7713b1edbc	848	*/
AnnaBridge	171:3a7713b1edbc	849	__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
AnnaBridge	171:3a7713b1edbc	850	{
AnnaBridge	171:3a7713b1edbc	851	WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
AnnaBridge	171:3a7713b1edbc	852	}
AnnaBridge	171:3a7713b1edbc	853
AnnaBridge	171:3a7713b1edbc	854	/**
AnnaBridge	171:3a7713b1edbc	855	* @brief Toggle data value for several pin of dedicated port.
AnnaBridge	171:3a7713b1edbc	856	* @rmtoll ODR ODy LL_GPIO_TogglePin
AnnaBridge	171:3a7713b1edbc	857	* @param GPIOx GPIO Port
AnnaBridge	171:3a7713b1edbc	858	* @param PinMask This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	859	* @arg @ref LL_GPIO_PIN_0
AnnaBridge	171:3a7713b1edbc	860	* @arg @ref LL_GPIO_PIN_1
AnnaBridge	171:3a7713b1edbc	861	* @arg @ref LL_GPIO_PIN_2
AnnaBridge	171:3a7713b1edbc	862	* @arg @ref LL_GPIO_PIN_3
AnnaBridge	171:3a7713b1edbc	863	* @arg @ref LL_GPIO_PIN_4
AnnaBridge	171:3a7713b1edbc	864	* @arg @ref LL_GPIO_PIN_5
AnnaBridge	171:3a7713b1edbc	865	* @arg @ref LL_GPIO_PIN_6
AnnaBridge	171:3a7713b1edbc	866	* @arg @ref LL_GPIO_PIN_7
AnnaBridge	171:3a7713b1edbc	867	* @arg @ref LL_GPIO_PIN_8
AnnaBridge	171:3a7713b1edbc	868	* @arg @ref LL_GPIO_PIN_9
AnnaBridge	171:3a7713b1edbc	869	* @arg @ref LL_GPIO_PIN_10
AnnaBridge	171:3a7713b1edbc	870	* @arg @ref LL_GPIO_PIN_11
AnnaBridge	171:3a7713b1edbc	871	* @arg @ref LL_GPIO_PIN_12
AnnaBridge	171:3a7713b1edbc	872	* @arg @ref LL_GPIO_PIN_13
AnnaBridge	171:3a7713b1edbc	873	* @arg @ref LL_GPIO_PIN_14
AnnaBridge	171:3a7713b1edbc	874	* @arg @ref LL_GPIO_PIN_15
AnnaBridge	171:3a7713b1edbc	875	* @arg @ref LL_GPIO_PIN_ALL
AnnaBridge	171:3a7713b1edbc	876	* @retval None
AnnaBridge	171:3a7713b1edbc	877	*/
AnnaBridge	171:3a7713b1edbc	878	__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
AnnaBridge	171:3a7713b1edbc	879	{
AnnaBridge	171:3a7713b1edbc	880	WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
AnnaBridge	171:3a7713b1edbc	881	}
AnnaBridge	171:3a7713b1edbc	882
AnnaBridge	171:3a7713b1edbc	883	/**
AnnaBridge	171:3a7713b1edbc	884	* @}
AnnaBridge	171:3a7713b1edbc	885	*/
AnnaBridge	171:3a7713b1edbc	886
AnnaBridge	171:3a7713b1edbc	887	/** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping
AnnaBridge	171:3a7713b1edbc	888	* @brief This section propose definition to remap the alternate function to some other port/pins.
AnnaBridge	171:3a7713b1edbc	889	* @{
AnnaBridge	171:3a7713b1edbc	890	*/
AnnaBridge	171:3a7713b1edbc	891
AnnaBridge	171:3a7713b1edbc	892	/**
AnnaBridge	171:3a7713b1edbc	893	* @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
AnnaBridge	171:3a7713b1edbc	894	* @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1
AnnaBridge	171:3a7713b1edbc	895	* @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
AnnaBridge	171:3a7713b1edbc	896	* @retval None
AnnaBridge	171:3a7713b1edbc	897	*/
AnnaBridge	171:3a7713b1edbc	898	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
AnnaBridge	171:3a7713b1edbc	899	{
AnnaBridge	171:3a7713b1edbc	900	SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
AnnaBridge	171:3a7713b1edbc	901	}
AnnaBridge	171:3a7713b1edbc	902
AnnaBridge	171:3a7713b1edbc	903	/**
AnnaBridge	171:3a7713b1edbc	904	* @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
AnnaBridge	171:3a7713b1edbc	905	* @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1
AnnaBridge	171:3a7713b1edbc	906	* @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
AnnaBridge	171:3a7713b1edbc	907	* @retval None
AnnaBridge	171:3a7713b1edbc	908	*/
AnnaBridge	171:3a7713b1edbc	909	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
AnnaBridge	171:3a7713b1edbc	910	{
AnnaBridge	171:3a7713b1edbc	911	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
AnnaBridge	171:3a7713b1edbc	912	}
AnnaBridge	171:3a7713b1edbc	913
AnnaBridge	171:3a7713b1edbc	914	/**
AnnaBridge	171:3a7713b1edbc	915	* @brief Check if SPI1 has been remaped or not
AnnaBridge	171:3a7713b1edbc	916	* @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1
AnnaBridge	171:3a7713b1edbc	917	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	918	*/
AnnaBridge	171:3a7713b1edbc	919	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void)
AnnaBridge	171:3a7713b1edbc	920	{
AnnaBridge	171:3a7713b1edbc	921	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP));
AnnaBridge	171:3a7713b1edbc	922	}
AnnaBridge	171:3a7713b1edbc	923
AnnaBridge	171:3a7713b1edbc	924	/**
AnnaBridge	171:3a7713b1edbc	925	* @brief Enable the remapping of I2C1 alternate function SCL and SDA.
AnnaBridge	171:3a7713b1edbc	926	* @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1
AnnaBridge	171:3a7713b1edbc	927	* @note ENABLE: Remap (SCL/PB8, SDA/PB9)
AnnaBridge	171:3a7713b1edbc	928	* @retval None
AnnaBridge	171:3a7713b1edbc	929	*/
AnnaBridge	171:3a7713b1edbc	930	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
AnnaBridge	171:3a7713b1edbc	931	{
AnnaBridge	171:3a7713b1edbc	932	SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
AnnaBridge	171:3a7713b1edbc	933	}
AnnaBridge	171:3a7713b1edbc	934
AnnaBridge	171:3a7713b1edbc	935	/**
AnnaBridge	171:3a7713b1edbc	936	* @brief Disable the remapping of I2C1 alternate function SCL and SDA.
AnnaBridge	171:3a7713b1edbc	937	* @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1
AnnaBridge	171:3a7713b1edbc	938	* @note DISABLE: No remap (SCL/PB6, SDA/PB7)
AnnaBridge	171:3a7713b1edbc	939	* @retval None
AnnaBridge	171:3a7713b1edbc	940	*/
AnnaBridge	171:3a7713b1edbc	941	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
AnnaBridge	171:3a7713b1edbc	942	{
AnnaBridge	171:3a7713b1edbc	943	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
AnnaBridge	171:3a7713b1edbc	944	}
AnnaBridge	171:3a7713b1edbc	945
AnnaBridge	171:3a7713b1edbc	946	/**
AnnaBridge	171:3a7713b1edbc	947	* @brief Check if I2C1 has been remaped or not
AnnaBridge	171:3a7713b1edbc	948	* @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1
AnnaBridge	171:3a7713b1edbc	949	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	950	*/
AnnaBridge	171:3a7713b1edbc	951	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void)
AnnaBridge	171:3a7713b1edbc	952	{
AnnaBridge	171:3a7713b1edbc	953	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP));
AnnaBridge	171:3a7713b1edbc	954	}
AnnaBridge	171:3a7713b1edbc	955
AnnaBridge	171:3a7713b1edbc	956	/**
AnnaBridge	171:3a7713b1edbc	957	* @brief Enable the remapping of USART1 alternate function TX and RX.
AnnaBridge	171:3a7713b1edbc	958	* @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1
AnnaBridge	171:3a7713b1edbc	959	* @note ENABLE: Remap (TX/PB6, RX/PB7)
AnnaBridge	171:3a7713b1edbc	960	* @retval None
AnnaBridge	171:3a7713b1edbc	961	*/
AnnaBridge	171:3a7713b1edbc	962	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
AnnaBridge	171:3a7713b1edbc	963	{
AnnaBridge	171:3a7713b1edbc	964	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
AnnaBridge	171:3a7713b1edbc	965	}
AnnaBridge	171:3a7713b1edbc	966
AnnaBridge	171:3a7713b1edbc	967	/**
AnnaBridge	171:3a7713b1edbc	968	* @brief Disable the remapping of USART1 alternate function TX and RX.
AnnaBridge	171:3a7713b1edbc	969	* @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1
AnnaBridge	171:3a7713b1edbc	970	* @note DISABLE: No remap (TX/PA9, RX/PA10)
AnnaBridge	171:3a7713b1edbc	971	* @retval None
AnnaBridge	171:3a7713b1edbc	972	*/
AnnaBridge	171:3a7713b1edbc	973	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
AnnaBridge	171:3a7713b1edbc	974	{
AnnaBridge	171:3a7713b1edbc	975	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
AnnaBridge	171:3a7713b1edbc	976	}
AnnaBridge	171:3a7713b1edbc	977
AnnaBridge	171:3a7713b1edbc	978	/**
AnnaBridge	171:3a7713b1edbc	979	* @brief Check if USART1 has been remaped or not
AnnaBridge	171:3a7713b1edbc	980	* @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1
AnnaBridge	171:3a7713b1edbc	981	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	982	*/
AnnaBridge	171:3a7713b1edbc	983	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void)
AnnaBridge	171:3a7713b1edbc	984	{
AnnaBridge	171:3a7713b1edbc	985	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP));
AnnaBridge	171:3a7713b1edbc	986	}
AnnaBridge	171:3a7713b1edbc	987
AnnaBridge	171:3a7713b1edbc	988	/**
AnnaBridge	171:3a7713b1edbc	989	* @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
AnnaBridge	171:3a7713b1edbc	990	* @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2
AnnaBridge	171:3a7713b1edbc	991	* @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
AnnaBridge	171:3a7713b1edbc	992	* @retval None
AnnaBridge	171:3a7713b1edbc	993	*/
AnnaBridge	171:3a7713b1edbc	994	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
AnnaBridge	171:3a7713b1edbc	995	{
AnnaBridge	171:3a7713b1edbc	996	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
AnnaBridge	171:3a7713b1edbc	997	}
AnnaBridge	171:3a7713b1edbc	998
AnnaBridge	171:3a7713b1edbc	999	/**
AnnaBridge	171:3a7713b1edbc	1000	* @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
AnnaBridge	171:3a7713b1edbc	1001	* @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2
AnnaBridge	171:3a7713b1edbc	1002	* @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
AnnaBridge	171:3a7713b1edbc	1003	* @retval None
AnnaBridge	171:3a7713b1edbc	1004	*/
AnnaBridge	171:3a7713b1edbc	1005	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
AnnaBridge	171:3a7713b1edbc	1006	{
AnnaBridge	171:3a7713b1edbc	1007	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
AnnaBridge	171:3a7713b1edbc	1008	}
AnnaBridge	171:3a7713b1edbc	1009
AnnaBridge	171:3a7713b1edbc	1010	/**
AnnaBridge	171:3a7713b1edbc	1011	* @brief Check if USART2 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1012	* @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2
AnnaBridge	171:3a7713b1edbc	1013	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1014	*/
AnnaBridge	171:3a7713b1edbc	1015	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void)
AnnaBridge	171:3a7713b1edbc	1016	{
AnnaBridge	171:3a7713b1edbc	1017	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP));
AnnaBridge	171:3a7713b1edbc	1018	}
AnnaBridge	171:3a7713b1edbc	1019
AnnaBridge	171:3a7713b1edbc	1020	#if defined (AFIO_MAPR_USART3_REMAP)
AnnaBridge	171:3a7713b1edbc	1021	/**
AnnaBridge	171:3a7713b1edbc	1022	* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
AnnaBridge	171:3a7713b1edbc	1023	* @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3
AnnaBridge	171:3a7713b1edbc	1024	* @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
AnnaBridge	171:3a7713b1edbc	1025	* @retval None
AnnaBridge	171:3a7713b1edbc	1026	*/
AnnaBridge	171:3a7713b1edbc	1027	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
AnnaBridge	171:3a7713b1edbc	1028	{
AnnaBridge	171:3a7713b1edbc	1029	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
AnnaBridge	171:3a7713b1edbc	1030	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP);
AnnaBridge	171:3a7713b1edbc	1031	}
AnnaBridge	171:3a7713b1edbc	1032
AnnaBridge	171:3a7713b1edbc	1033	/**
AnnaBridge	171:3a7713b1edbc	1034	* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
AnnaBridge	171:3a7713b1edbc	1035	* @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3
AnnaBridge	171:3a7713b1edbc	1036	* @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
AnnaBridge	171:3a7713b1edbc	1037	* @retval None
AnnaBridge	171:3a7713b1edbc	1038	*/
AnnaBridge	171:3a7713b1edbc	1039	__STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
AnnaBridge	171:3a7713b1edbc	1040	{
AnnaBridge	171:3a7713b1edbc	1041	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
AnnaBridge	171:3a7713b1edbc	1042	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP);
AnnaBridge	171:3a7713b1edbc	1043	}
AnnaBridge	171:3a7713b1edbc	1044
AnnaBridge	171:3a7713b1edbc	1045	/**
AnnaBridge	171:3a7713b1edbc	1046	* @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
AnnaBridge	171:3a7713b1edbc	1047	* @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3
AnnaBridge	171:3a7713b1edbc	1048	* @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
AnnaBridge	171:3a7713b1edbc	1049	* @retval None
AnnaBridge	171:3a7713b1edbc	1050	*/
AnnaBridge	171:3a7713b1edbc	1051	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
AnnaBridge	171:3a7713b1edbc	1052	{
AnnaBridge	171:3a7713b1edbc	1053	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
AnnaBridge	171:3a7713b1edbc	1054	SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP);
AnnaBridge	171:3a7713b1edbc	1055	}
AnnaBridge	171:3a7713b1edbc	1056	#endif
AnnaBridge	171:3a7713b1edbc	1057
AnnaBridge	171:3a7713b1edbc	1058	/**
AnnaBridge	171:3a7713b1edbc	1059	* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
AnnaBridge	171:3a7713b1edbc	1060	* @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1
AnnaBridge	171:3a7713b1edbc	1061	* @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
AnnaBridge	171:3a7713b1edbc	1062	* @retval None
AnnaBridge	171:3a7713b1edbc	1063	*/
AnnaBridge	171:3a7713b1edbc	1064	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
AnnaBridge	171:3a7713b1edbc	1065	{
AnnaBridge	171:3a7713b1edbc	1066	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
AnnaBridge	171:3a7713b1edbc	1067	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP);
AnnaBridge	171:3a7713b1edbc	1068	}
AnnaBridge	171:3a7713b1edbc	1069
AnnaBridge	171:3a7713b1edbc	1070	/**
AnnaBridge	171:3a7713b1edbc	1071	* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
AnnaBridge	171:3a7713b1edbc	1072	* @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1
AnnaBridge	171:3a7713b1edbc	1073	* @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
AnnaBridge	171:3a7713b1edbc	1074	* @retval None
AnnaBridge	171:3a7713b1edbc	1075	*/
AnnaBridge	171:3a7713b1edbc	1076	__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
AnnaBridge	171:3a7713b1edbc	1077	{
AnnaBridge	171:3a7713b1edbc	1078	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
AnnaBridge	171:3a7713b1edbc	1079	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP);
AnnaBridge	171:3a7713b1edbc	1080	}
AnnaBridge	171:3a7713b1edbc	1081
AnnaBridge	171:3a7713b1edbc	1082	/**
AnnaBridge	171:3a7713b1edbc	1083	* @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
AnnaBridge	171:3a7713b1edbc	1084	* @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1
AnnaBridge	171:3a7713b1edbc	1085	* @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
AnnaBridge	171:3a7713b1edbc	1086	* @retval None
AnnaBridge	171:3a7713b1edbc	1087	*/
AnnaBridge	171:3a7713b1edbc	1088	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
AnnaBridge	171:3a7713b1edbc	1089	{
AnnaBridge	171:3a7713b1edbc	1090	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
AnnaBridge	171:3a7713b1edbc	1091	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP);
AnnaBridge	171:3a7713b1edbc	1092	}
AnnaBridge	171:3a7713b1edbc	1093
AnnaBridge	171:3a7713b1edbc	1094	/**
AnnaBridge	171:3a7713b1edbc	1095	* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
AnnaBridge	171:3a7713b1edbc	1096	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2
AnnaBridge	171:3a7713b1edbc	1097	* @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
AnnaBridge	171:3a7713b1edbc	1098	* @retval None
AnnaBridge	171:3a7713b1edbc	1099	*/
AnnaBridge	171:3a7713b1edbc	1100	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
AnnaBridge	171:3a7713b1edbc	1101	{
AnnaBridge	171:3a7713b1edbc	1102	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
AnnaBridge	171:3a7713b1edbc	1103	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP);
AnnaBridge	171:3a7713b1edbc	1104	}
AnnaBridge	171:3a7713b1edbc	1105
AnnaBridge	171:3a7713b1edbc	1106	/**
AnnaBridge	171:3a7713b1edbc	1107	* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
AnnaBridge	171:3a7713b1edbc	1108	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2
AnnaBridge	171:3a7713b1edbc	1109	* @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
AnnaBridge	171:3a7713b1edbc	1110	* @retval None
AnnaBridge	171:3a7713b1edbc	1111	*/
AnnaBridge	171:3a7713b1edbc	1112	__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
AnnaBridge	171:3a7713b1edbc	1113	{
AnnaBridge	171:3a7713b1edbc	1114	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
AnnaBridge	171:3a7713b1edbc	1115	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2);
AnnaBridge	171:3a7713b1edbc	1116	}
AnnaBridge	171:3a7713b1edbc	1117
AnnaBridge	171:3a7713b1edbc	1118	/**
AnnaBridge	171:3a7713b1edbc	1119	* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
AnnaBridge	171:3a7713b1edbc	1120	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2
AnnaBridge	171:3a7713b1edbc	1121	* @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
AnnaBridge	171:3a7713b1edbc	1122	* @retval None
AnnaBridge	171:3a7713b1edbc	1123	*/
AnnaBridge	171:3a7713b1edbc	1124	__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
AnnaBridge	171:3a7713b1edbc	1125	{
AnnaBridge	171:3a7713b1edbc	1126	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
AnnaBridge	171:3a7713b1edbc	1127	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1);
AnnaBridge	171:3a7713b1edbc	1128	}
AnnaBridge	171:3a7713b1edbc	1129
AnnaBridge	171:3a7713b1edbc	1130	/**
AnnaBridge	171:3a7713b1edbc	1131	* @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
AnnaBridge	171:3a7713b1edbc	1132	* @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2
AnnaBridge	171:3a7713b1edbc	1133	* @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
AnnaBridge	171:3a7713b1edbc	1134	* @retval None
AnnaBridge	171:3a7713b1edbc	1135	*/
AnnaBridge	171:3a7713b1edbc	1136	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
AnnaBridge	171:3a7713b1edbc	1137	{
AnnaBridge	171:3a7713b1edbc	1138	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
AnnaBridge	171:3a7713b1edbc	1139	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP);
AnnaBridge	171:3a7713b1edbc	1140	}
AnnaBridge	171:3a7713b1edbc	1141
AnnaBridge	171:3a7713b1edbc	1142	/**
AnnaBridge	171:3a7713b1edbc	1143	* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
AnnaBridge	171:3a7713b1edbc	1144	* @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3
AnnaBridge	171:3a7713b1edbc	1145	* @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
AnnaBridge	171:3a7713b1edbc	1146	* @note TIM3_ETR on PE0 is not re-mapped.
AnnaBridge	171:3a7713b1edbc	1147	* @retval None
AnnaBridge	171:3a7713b1edbc	1148	*/
AnnaBridge	171:3a7713b1edbc	1149	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
AnnaBridge	171:3a7713b1edbc	1150	{
AnnaBridge	171:3a7713b1edbc	1151	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
AnnaBridge	171:3a7713b1edbc	1152	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP);
AnnaBridge	171:3a7713b1edbc	1153	}
AnnaBridge	171:3a7713b1edbc	1154
AnnaBridge	171:3a7713b1edbc	1155	/**
AnnaBridge	171:3a7713b1edbc	1156	* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
AnnaBridge	171:3a7713b1edbc	1157	* @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3
AnnaBridge	171:3a7713b1edbc	1158	* @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
AnnaBridge	171:3a7713b1edbc	1159	* @note TIM3_ETR on PE0 is not re-mapped.
AnnaBridge	171:3a7713b1edbc	1160	* @retval None
AnnaBridge	171:3a7713b1edbc	1161	*/
AnnaBridge	171:3a7713b1edbc	1162	__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
AnnaBridge	171:3a7713b1edbc	1163	{
AnnaBridge	171:3a7713b1edbc	1164	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
AnnaBridge	171:3a7713b1edbc	1165	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP);
AnnaBridge	171:3a7713b1edbc	1166	}
AnnaBridge	171:3a7713b1edbc	1167
AnnaBridge	171:3a7713b1edbc	1168	/**
AnnaBridge	171:3a7713b1edbc	1169	* @brief Disable the remapping of TIM3 alternate function channels 1 to 4
AnnaBridge	171:3a7713b1edbc	1170	* @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3
AnnaBridge	171:3a7713b1edbc	1171	* @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
AnnaBridge	171:3a7713b1edbc	1172	* @note TIM3_ETR on PE0 is not re-mapped.
AnnaBridge	171:3a7713b1edbc	1173	* @retval None
AnnaBridge	171:3a7713b1edbc	1174	*/
AnnaBridge	171:3a7713b1edbc	1175	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
AnnaBridge	171:3a7713b1edbc	1176	{
AnnaBridge	171:3a7713b1edbc	1177	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
AnnaBridge	171:3a7713b1edbc	1178	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP);
AnnaBridge	171:3a7713b1edbc	1179	}
AnnaBridge	171:3a7713b1edbc	1180
AnnaBridge	171:3a7713b1edbc	1181	#if defined(AFIO_MAPR_TIM4_REMAP)
AnnaBridge	171:3a7713b1edbc	1182	/**
AnnaBridge	171:3a7713b1edbc	1183	* @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
AnnaBridge	171:3a7713b1edbc	1184	* @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4
AnnaBridge	171:3a7713b1edbc	1185	* @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
AnnaBridge	171:3a7713b1edbc	1186	* @note TIM4_ETR on PE0 is not re-mapped.
AnnaBridge	171:3a7713b1edbc	1187	* @retval None
AnnaBridge	171:3a7713b1edbc	1188	*/
AnnaBridge	171:3a7713b1edbc	1189	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
AnnaBridge	171:3a7713b1edbc	1190	{
AnnaBridge	171:3a7713b1edbc	1191	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
AnnaBridge	171:3a7713b1edbc	1192	}
AnnaBridge	171:3a7713b1edbc	1193	/**
AnnaBridge	171:3a7713b1edbc	1194	* @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
AnnaBridge	171:3a7713b1edbc	1195	* @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4
AnnaBridge	171:3a7713b1edbc	1196	* @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
AnnaBridge	171:3a7713b1edbc	1197	* @note TIM4_ETR on PE0 is not re-mapped.
AnnaBridge	171:3a7713b1edbc	1198	* @retval None
AnnaBridge	171:3a7713b1edbc	1199	*/
AnnaBridge	171:3a7713b1edbc	1200	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
AnnaBridge	171:3a7713b1edbc	1201	{
AnnaBridge	171:3a7713b1edbc	1202	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
AnnaBridge	171:3a7713b1edbc	1203	}
AnnaBridge	171:3a7713b1edbc	1204
AnnaBridge	171:3a7713b1edbc	1205	/**
AnnaBridge	171:3a7713b1edbc	1206	* @brief Check if TIM4 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1207	* @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4
AnnaBridge	171:3a7713b1edbc	1208	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1209	*/
AnnaBridge	171:3a7713b1edbc	1210	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void)
AnnaBridge	171:3a7713b1edbc	1211	{
AnnaBridge	171:3a7713b1edbc	1212	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP));
AnnaBridge	171:3a7713b1edbc	1213	}
AnnaBridge	171:3a7713b1edbc	1214	#endif
AnnaBridge	171:3a7713b1edbc	1215
AnnaBridge	171:3a7713b1edbc	1216	#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
AnnaBridge	171:3a7713b1edbc	1217
AnnaBridge	171:3a7713b1edbc	1218	/**
AnnaBridge	171:3a7713b1edbc	1219	* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
AnnaBridge	171:3a7713b1edbc	1220	* @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1
AnnaBridge	171:3a7713b1edbc	1221	* @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
AnnaBridge	171:3a7713b1edbc	1222	* @retval None
AnnaBridge	171:3a7713b1edbc	1223	*/
AnnaBridge	171:3a7713b1edbc	1224	__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
AnnaBridge	171:3a7713b1edbc	1225	{
AnnaBridge	171:3a7713b1edbc	1226	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
AnnaBridge	171:3a7713b1edbc	1227	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1);
AnnaBridge	171:3a7713b1edbc	1228	}
AnnaBridge	171:3a7713b1edbc	1229
AnnaBridge	171:3a7713b1edbc	1230	/**
AnnaBridge	171:3a7713b1edbc	1231	* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
AnnaBridge	171:3a7713b1edbc	1232	* @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1
AnnaBridge	171:3a7713b1edbc	1233	* @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
AnnaBridge	171:3a7713b1edbc	1234	* @retval None
AnnaBridge	171:3a7713b1edbc	1235	*/
AnnaBridge	171:3a7713b1edbc	1236	__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
AnnaBridge	171:3a7713b1edbc	1237	{
AnnaBridge	171:3a7713b1edbc	1238	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
AnnaBridge	171:3a7713b1edbc	1239	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2);
AnnaBridge	171:3a7713b1edbc	1240	}
AnnaBridge	171:3a7713b1edbc	1241
AnnaBridge	171:3a7713b1edbc	1242	/**
AnnaBridge	171:3a7713b1edbc	1243	* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
AnnaBridge	171:3a7713b1edbc	1244	* @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1
AnnaBridge	171:3a7713b1edbc	1245	* @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
AnnaBridge	171:3a7713b1edbc	1246	* @retval None
AnnaBridge	171:3a7713b1edbc	1247	*/
AnnaBridge	171:3a7713b1edbc	1248	__STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
AnnaBridge	171:3a7713b1edbc	1249	{
AnnaBridge	171:3a7713b1edbc	1250	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
AnnaBridge	171:3a7713b1edbc	1251	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3);
AnnaBridge	171:3a7713b1edbc	1252	}
AnnaBridge	171:3a7713b1edbc	1253	#endif
AnnaBridge	171:3a7713b1edbc	1254
AnnaBridge	171:3a7713b1edbc	1255	/**
AnnaBridge	171:3a7713b1edbc	1256	* @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
AnnaBridge	171:3a7713b1edbc	1257	* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
AnnaBridge	171:3a7713b1edbc	1258	* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
AnnaBridge	171:3a7713b1edbc	1259	* on 100-pin and 144-pin packages, no need for remapping).
AnnaBridge	171:3a7713b1edbc	1260	* @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01
AnnaBridge	171:3a7713b1edbc	1261	* @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
AnnaBridge	171:3a7713b1edbc	1262	* @retval None
AnnaBridge	171:3a7713b1edbc	1263	*/
AnnaBridge	171:3a7713b1edbc	1264	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
AnnaBridge	171:3a7713b1edbc	1265	{
AnnaBridge	171:3a7713b1edbc	1266	SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
AnnaBridge	171:3a7713b1edbc	1267	}
AnnaBridge	171:3a7713b1edbc	1268
AnnaBridge	171:3a7713b1edbc	1269	/**
AnnaBridge	171:3a7713b1edbc	1270	* @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
AnnaBridge	171:3a7713b1edbc	1271	* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
AnnaBridge	171:3a7713b1edbc	1272	* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
AnnaBridge	171:3a7713b1edbc	1273	* on 100-pin and 144-pin packages, no need for remapping).
AnnaBridge	171:3a7713b1edbc	1274	* @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01
AnnaBridge	171:3a7713b1edbc	1275	* @note DISABLE: No remapping of PD0 and PD1
AnnaBridge	171:3a7713b1edbc	1276	* @retval None
AnnaBridge	171:3a7713b1edbc	1277	*/
AnnaBridge	171:3a7713b1edbc	1278	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
AnnaBridge	171:3a7713b1edbc	1279	{
AnnaBridge	171:3a7713b1edbc	1280	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
AnnaBridge	171:3a7713b1edbc	1281	}
AnnaBridge	171:3a7713b1edbc	1282
AnnaBridge	171:3a7713b1edbc	1283	/**
AnnaBridge	171:3a7713b1edbc	1284	* @brief Check if PD01 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1285	* @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01
AnnaBridge	171:3a7713b1edbc	1286	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1287	*/
AnnaBridge	171:3a7713b1edbc	1288	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void)
AnnaBridge	171:3a7713b1edbc	1289	{
AnnaBridge	171:3a7713b1edbc	1290	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP));
AnnaBridge	171:3a7713b1edbc	1291	}
AnnaBridge	171:3a7713b1edbc	1292
AnnaBridge	171:3a7713b1edbc	1293	#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
AnnaBridge	171:3a7713b1edbc	1294	/**
AnnaBridge	171:3a7713b1edbc	1295	* @brief Enable the remapping of TIM5CH4.
AnnaBridge	171:3a7713b1edbc	1296	* @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4
AnnaBridge	171:3a7713b1edbc	1297	* @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
AnnaBridge	171:3a7713b1edbc	1298	* @note This function is available only in high density value line devices.
AnnaBridge	171:3a7713b1edbc	1299	* @retval None
AnnaBridge	171:3a7713b1edbc	1300	*/
AnnaBridge	171:3a7713b1edbc	1301	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
AnnaBridge	171:3a7713b1edbc	1302	{
AnnaBridge	171:3a7713b1edbc	1303	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
AnnaBridge	171:3a7713b1edbc	1304	}
AnnaBridge	171:3a7713b1edbc	1305
AnnaBridge	171:3a7713b1edbc	1306	/**
AnnaBridge	171:3a7713b1edbc	1307	* @brief Disable the remapping of TIM5CH4.
AnnaBridge	171:3a7713b1edbc	1308	* @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4
AnnaBridge	171:3a7713b1edbc	1309	* @note DISABLE: TIM5_CH4 is connected to PA3
AnnaBridge	171:3a7713b1edbc	1310	* @note This function is available only in high density value line devices.
AnnaBridge	171:3a7713b1edbc	1311	* @retval None
AnnaBridge	171:3a7713b1edbc	1312	*/
AnnaBridge	171:3a7713b1edbc	1313	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
AnnaBridge	171:3a7713b1edbc	1314	{
AnnaBridge	171:3a7713b1edbc	1315	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
AnnaBridge	171:3a7713b1edbc	1316	}
AnnaBridge	171:3a7713b1edbc	1317
AnnaBridge	171:3a7713b1edbc	1318	/**
AnnaBridge	171:3a7713b1edbc	1319	* @brief Check if TIM5CH4 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1320	* @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4
AnnaBridge	171:3a7713b1edbc	1321	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1322	*/
AnnaBridge	171:3a7713b1edbc	1323	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)
AnnaBridge	171:3a7713b1edbc	1324	{
AnnaBridge	171:3a7713b1edbc	1325	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP));
AnnaBridge	171:3a7713b1edbc	1326	}
AnnaBridge	171:3a7713b1edbc	1327	#endif
AnnaBridge	171:3a7713b1edbc	1328
AnnaBridge	171:3a7713b1edbc	1329	#if defined(AFIO_MAPR_ETH_REMAP)
AnnaBridge	171:3a7713b1edbc	1330	/**
AnnaBridge	171:3a7713b1edbc	1331	* @brief Enable the remapping of Ethernet MAC connections with the PHY.
AnnaBridge	171:3a7713b1edbc	1332	* @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH
AnnaBridge	171:3a7713b1edbc	1333	* @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
AnnaBridge	171:3a7713b1edbc	1334	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1335	* @retval None
AnnaBridge	171:3a7713b1edbc	1336	*/
AnnaBridge	171:3a7713b1edbc	1337	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
AnnaBridge	171:3a7713b1edbc	1338	{
AnnaBridge	171:3a7713b1edbc	1339	SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
AnnaBridge	171:3a7713b1edbc	1340	}
AnnaBridge	171:3a7713b1edbc	1341
AnnaBridge	171:3a7713b1edbc	1342	/**
AnnaBridge	171:3a7713b1edbc	1343	* @brief Disable the remapping of Ethernet MAC connections with the PHY.
AnnaBridge	171:3a7713b1edbc	1344	* @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH
AnnaBridge	171:3a7713b1edbc	1345	* @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
AnnaBridge	171:3a7713b1edbc	1346	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1347	* @retval None
AnnaBridge	171:3a7713b1edbc	1348	*/
AnnaBridge	171:3a7713b1edbc	1349	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
AnnaBridge	171:3a7713b1edbc	1350	{
AnnaBridge	171:3a7713b1edbc	1351	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
AnnaBridge	171:3a7713b1edbc	1352	}
AnnaBridge	171:3a7713b1edbc	1353
AnnaBridge	171:3a7713b1edbc	1354	/**
AnnaBridge	171:3a7713b1edbc	1355	* @brief Check if ETH has been remaped or not
AnnaBridge	171:3a7713b1edbc	1356	* @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH
AnnaBridge	171:3a7713b1edbc	1357	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1358	*/
AnnaBridge	171:3a7713b1edbc	1359	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void)
AnnaBridge	171:3a7713b1edbc	1360	{
AnnaBridge	171:3a7713b1edbc	1361	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP));
AnnaBridge	171:3a7713b1edbc	1362	}
AnnaBridge	171:3a7713b1edbc	1363	#endif
AnnaBridge	171:3a7713b1edbc	1364
AnnaBridge	171:3a7713b1edbc	1365	#if defined(AFIO_MAPR_CAN2_REMAP)
AnnaBridge	171:3a7713b1edbc	1366
AnnaBridge	171:3a7713b1edbc	1367	/**
AnnaBridge	171:3a7713b1edbc	1368	* @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
AnnaBridge	171:3a7713b1edbc	1369	* @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2
AnnaBridge	171:3a7713b1edbc	1370	* @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
AnnaBridge	171:3a7713b1edbc	1371	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1372	* @retval None
AnnaBridge	171:3a7713b1edbc	1373	*/
AnnaBridge	171:3a7713b1edbc	1374	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
AnnaBridge	171:3a7713b1edbc	1375	{
AnnaBridge	171:3a7713b1edbc	1376	SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
AnnaBridge	171:3a7713b1edbc	1377	}
AnnaBridge	171:3a7713b1edbc	1378	/**
AnnaBridge	171:3a7713b1edbc	1379	* @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
AnnaBridge	171:3a7713b1edbc	1380	* @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2
AnnaBridge	171:3a7713b1edbc	1381	* @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
AnnaBridge	171:3a7713b1edbc	1382	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1383	* @retval None
AnnaBridge	171:3a7713b1edbc	1384	*/
AnnaBridge	171:3a7713b1edbc	1385	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
AnnaBridge	171:3a7713b1edbc	1386	{
AnnaBridge	171:3a7713b1edbc	1387	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
AnnaBridge	171:3a7713b1edbc	1388	}
AnnaBridge	171:3a7713b1edbc	1389
AnnaBridge	171:3a7713b1edbc	1390	/**
AnnaBridge	171:3a7713b1edbc	1391	* @brief Check if CAN2 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1392	* @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2
AnnaBridge	171:3a7713b1edbc	1393	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1394	*/
AnnaBridge	171:3a7713b1edbc	1395	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void)
AnnaBridge	171:3a7713b1edbc	1396	{
AnnaBridge	171:3a7713b1edbc	1397	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP));
AnnaBridge	171:3a7713b1edbc	1398	}
AnnaBridge	171:3a7713b1edbc	1399	#endif
AnnaBridge	171:3a7713b1edbc	1400
AnnaBridge	171:3a7713b1edbc	1401	#if defined(AFIO_MAPR_MII_RMII_SEL)
AnnaBridge	171:3a7713b1edbc	1402	/**
AnnaBridge	171:3a7713b1edbc	1403	* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
AnnaBridge	171:3a7713b1edbc	1404	* @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII
AnnaBridge	171:3a7713b1edbc	1405	* @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
AnnaBridge	171:3a7713b1edbc	1406	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1407	* @retval None
AnnaBridge	171:3a7713b1edbc	1408	*/
AnnaBridge	171:3a7713b1edbc	1409	__STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
AnnaBridge	171:3a7713b1edbc	1410	{
AnnaBridge	171:3a7713b1edbc	1411	SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
AnnaBridge	171:3a7713b1edbc	1412	}
AnnaBridge	171:3a7713b1edbc	1413
AnnaBridge	171:3a7713b1edbc	1414	/**
AnnaBridge	171:3a7713b1edbc	1415	* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
AnnaBridge	171:3a7713b1edbc	1416	* @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII
AnnaBridge	171:3a7713b1edbc	1417	* @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
AnnaBridge	171:3a7713b1edbc	1418	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1419	* @retval None
AnnaBridge	171:3a7713b1edbc	1420	*/
AnnaBridge	171:3a7713b1edbc	1421	__STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
AnnaBridge	171:3a7713b1edbc	1422	{
AnnaBridge	171:3a7713b1edbc	1423	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
AnnaBridge	171:3a7713b1edbc	1424	}
AnnaBridge	171:3a7713b1edbc	1425	#endif
AnnaBridge	171:3a7713b1edbc	1426
AnnaBridge	171:3a7713b1edbc	1427	#if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
AnnaBridge	171:3a7713b1edbc	1428	/**
AnnaBridge	171:3a7713b1edbc	1429	* @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
AnnaBridge	171:3a7713b1edbc	1430	* @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ
AnnaBridge	171:3a7713b1edbc	1431	* @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
AnnaBridge	171:3a7713b1edbc	1432	* @retval None
AnnaBridge	171:3a7713b1edbc	1433	*/
AnnaBridge	171:3a7713b1edbc	1434	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
AnnaBridge	171:3a7713b1edbc	1435	{
AnnaBridge	171:3a7713b1edbc	1436	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
AnnaBridge	171:3a7713b1edbc	1437	}
AnnaBridge	171:3a7713b1edbc	1438
AnnaBridge	171:3a7713b1edbc	1439	/**
AnnaBridge	171:3a7713b1edbc	1440	* @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
AnnaBridge	171:3a7713b1edbc	1441	* @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
AnnaBridge	171:3a7713b1edbc	1442	* @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
AnnaBridge	171:3a7713b1edbc	1443	* @retval None
AnnaBridge	171:3a7713b1edbc	1444	*/
AnnaBridge	171:3a7713b1edbc	1445	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
AnnaBridge	171:3a7713b1edbc	1446	{
AnnaBridge	171:3a7713b1edbc	1447	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
AnnaBridge	171:3a7713b1edbc	1448	}
AnnaBridge	171:3a7713b1edbc	1449
AnnaBridge	171:3a7713b1edbc	1450	/**
AnnaBridge	171:3a7713b1edbc	1451	* @brief Check if ADC1_ETRGINJ has been remaped or not
AnnaBridge	171:3a7713b1edbc	1452	* @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
AnnaBridge	171:3a7713b1edbc	1453	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1454	*/
AnnaBridge	171:3a7713b1edbc	1455	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)
AnnaBridge	171:3a7713b1edbc	1456	{
AnnaBridge	171:3a7713b1edbc	1457	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP));
AnnaBridge	171:3a7713b1edbc	1458	}
AnnaBridge	171:3a7713b1edbc	1459	#endif
AnnaBridge	171:3a7713b1edbc	1460
AnnaBridge	171:3a7713b1edbc	1461	#if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
AnnaBridge	171:3a7713b1edbc	1462	/**
AnnaBridge	171:3a7713b1edbc	1463	* @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
AnnaBridge	171:3a7713b1edbc	1464	* @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG
AnnaBridge	171:3a7713b1edbc	1465	* @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
AnnaBridge	171:3a7713b1edbc	1466	* @retval None
AnnaBridge	171:3a7713b1edbc	1467	*/
AnnaBridge	171:3a7713b1edbc	1468	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
AnnaBridge	171:3a7713b1edbc	1469	{
AnnaBridge	171:3a7713b1edbc	1470	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
AnnaBridge	171:3a7713b1edbc	1471	}
AnnaBridge	171:3a7713b1edbc	1472
AnnaBridge	171:3a7713b1edbc	1473	/**
AnnaBridge	171:3a7713b1edbc	1474	* @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
AnnaBridge	171:3a7713b1edbc	1475	* @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
AnnaBridge	171:3a7713b1edbc	1476	* @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
AnnaBridge	171:3a7713b1edbc	1477	* @retval None
AnnaBridge	171:3a7713b1edbc	1478	*/
AnnaBridge	171:3a7713b1edbc	1479	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
AnnaBridge	171:3a7713b1edbc	1480	{
AnnaBridge	171:3a7713b1edbc	1481	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
AnnaBridge	171:3a7713b1edbc	1482	}
AnnaBridge	171:3a7713b1edbc	1483
AnnaBridge	171:3a7713b1edbc	1484	/**
AnnaBridge	171:3a7713b1edbc	1485	* @brief Check if ADC1_ETRGREG has been remaped or not
AnnaBridge	171:3a7713b1edbc	1486	* @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
AnnaBridge	171:3a7713b1edbc	1487	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1488	*/
AnnaBridge	171:3a7713b1edbc	1489	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)
AnnaBridge	171:3a7713b1edbc	1490	{
AnnaBridge	171:3a7713b1edbc	1491	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP));
AnnaBridge	171:3a7713b1edbc	1492	}
AnnaBridge	171:3a7713b1edbc	1493	#endif
AnnaBridge	171:3a7713b1edbc	1494
AnnaBridge	171:3a7713b1edbc	1495	#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
AnnaBridge	171:3a7713b1edbc	1496
AnnaBridge	171:3a7713b1edbc	1497	/**
AnnaBridge	171:3a7713b1edbc	1498	* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
AnnaBridge	171:3a7713b1edbc	1499	* @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ
AnnaBridge	171:3a7713b1edbc	1500	* @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
AnnaBridge	171:3a7713b1edbc	1501	* @retval None
AnnaBridge	171:3a7713b1edbc	1502	*/
AnnaBridge	171:3a7713b1edbc	1503	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
AnnaBridge	171:3a7713b1edbc	1504	{
AnnaBridge	171:3a7713b1edbc	1505	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
AnnaBridge	171:3a7713b1edbc	1506	}
AnnaBridge	171:3a7713b1edbc	1507
AnnaBridge	171:3a7713b1edbc	1508	/**
AnnaBridge	171:3a7713b1edbc	1509	* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
AnnaBridge	171:3a7713b1edbc	1510	* @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
AnnaBridge	171:3a7713b1edbc	1511	* @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
AnnaBridge	171:3a7713b1edbc	1512	* @retval None
AnnaBridge	171:3a7713b1edbc	1513	*/
AnnaBridge	171:3a7713b1edbc	1514	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
AnnaBridge	171:3a7713b1edbc	1515	{
AnnaBridge	171:3a7713b1edbc	1516	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
AnnaBridge	171:3a7713b1edbc	1517	}
AnnaBridge	171:3a7713b1edbc	1518
AnnaBridge	171:3a7713b1edbc	1519	/**
AnnaBridge	171:3a7713b1edbc	1520	* @brief Check if ADC2_ETRGINJ has been remaped or not
AnnaBridge	171:3a7713b1edbc	1521	* @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
AnnaBridge	171:3a7713b1edbc	1522	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1523	*/
AnnaBridge	171:3a7713b1edbc	1524	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)
AnnaBridge	171:3a7713b1edbc	1525	{
AnnaBridge	171:3a7713b1edbc	1526	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP));
AnnaBridge	171:3a7713b1edbc	1527	}
AnnaBridge	171:3a7713b1edbc	1528	#endif
AnnaBridge	171:3a7713b1edbc	1529
AnnaBridge	171:3a7713b1edbc	1530	#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
AnnaBridge	171:3a7713b1edbc	1531
AnnaBridge	171:3a7713b1edbc	1532	/**
AnnaBridge	171:3a7713b1edbc	1533	* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
AnnaBridge	171:3a7713b1edbc	1534	* @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG
AnnaBridge	171:3a7713b1edbc	1535	* @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
AnnaBridge	171:3a7713b1edbc	1536	* @retval None
AnnaBridge	171:3a7713b1edbc	1537	*/
AnnaBridge	171:3a7713b1edbc	1538	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
AnnaBridge	171:3a7713b1edbc	1539	{
AnnaBridge	171:3a7713b1edbc	1540	SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
AnnaBridge	171:3a7713b1edbc	1541	}
AnnaBridge	171:3a7713b1edbc	1542
AnnaBridge	171:3a7713b1edbc	1543	/**
AnnaBridge	171:3a7713b1edbc	1544	* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
AnnaBridge	171:3a7713b1edbc	1545	* @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
AnnaBridge	171:3a7713b1edbc	1546	* @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
AnnaBridge	171:3a7713b1edbc	1547	* @retval None
AnnaBridge	171:3a7713b1edbc	1548	*/
AnnaBridge	171:3a7713b1edbc	1549	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
AnnaBridge	171:3a7713b1edbc	1550	{
AnnaBridge	171:3a7713b1edbc	1551	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
AnnaBridge	171:3a7713b1edbc	1552	}
AnnaBridge	171:3a7713b1edbc	1553
AnnaBridge	171:3a7713b1edbc	1554	/**
AnnaBridge	171:3a7713b1edbc	1555	* @brief Check if ADC2_ETRGREG has been remaped or not
AnnaBridge	171:3a7713b1edbc	1556	* @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
AnnaBridge	171:3a7713b1edbc	1557	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1558	*/
AnnaBridge	171:3a7713b1edbc	1559	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)
AnnaBridge	171:3a7713b1edbc	1560	{
AnnaBridge	171:3a7713b1edbc	1561	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP));
AnnaBridge	171:3a7713b1edbc	1562	}
AnnaBridge	171:3a7713b1edbc	1563	#endif
AnnaBridge	171:3a7713b1edbc	1564
AnnaBridge	171:3a7713b1edbc	1565	/**
AnnaBridge	171:3a7713b1edbc	1566	* @brief Enable the Serial wire JTAG configuration
AnnaBridge	171:3a7713b1edbc	1567	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ
AnnaBridge	171:3a7713b1edbc	1568	* @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
AnnaBridge	171:3a7713b1edbc	1569	* @retval None
AnnaBridge	171:3a7713b1edbc	1570	*/
AnnaBridge	171:3a7713b1edbc	1571	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void)
AnnaBridge	171:3a7713b1edbc	1572	{
AnnaBridge	171:3a7713b1edbc	1573	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
AnnaBridge	171:3a7713b1edbc	1574	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);
AnnaBridge	171:3a7713b1edbc	1575	}
AnnaBridge	171:3a7713b1edbc	1576
AnnaBridge	171:3a7713b1edbc	1577	/**
AnnaBridge	171:3a7713b1edbc	1578	* @brief Enable the Serial wire JTAG configuration
AnnaBridge	171:3a7713b1edbc	1579	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST
AnnaBridge	171:3a7713b1edbc	1580	* @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
AnnaBridge	171:3a7713b1edbc	1581	* @retval None
AnnaBridge	171:3a7713b1edbc	1582	*/
AnnaBridge	171:3a7713b1edbc	1583	__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void)
AnnaBridge	171:3a7713b1edbc	1584	{
AnnaBridge	171:3a7713b1edbc	1585	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
AnnaBridge	171:3a7713b1edbc	1586	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);
AnnaBridge	171:3a7713b1edbc	1587	}
AnnaBridge	171:3a7713b1edbc	1588
AnnaBridge	171:3a7713b1edbc	1589	/**
AnnaBridge	171:3a7713b1edbc	1590	* @brief Enable the Serial wire JTAG configuration
AnnaBridge	171:3a7713b1edbc	1591	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG
AnnaBridge	171:3a7713b1edbc	1592	* @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
AnnaBridge	171:3a7713b1edbc	1593	* @retval None
AnnaBridge	171:3a7713b1edbc	1594	*/
AnnaBridge	171:3a7713b1edbc	1595	__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void)
AnnaBridge	171:3a7713b1edbc	1596	{
AnnaBridge	171:3a7713b1edbc	1597	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
AnnaBridge	171:3a7713b1edbc	1598	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE);
AnnaBridge	171:3a7713b1edbc	1599	}
AnnaBridge	171:3a7713b1edbc	1600
AnnaBridge	171:3a7713b1edbc	1601	/**
AnnaBridge	171:3a7713b1edbc	1602	* @brief Disable the Serial wire JTAG configuration
AnnaBridge	171:3a7713b1edbc	1603	* @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ
AnnaBridge	171:3a7713b1edbc	1604	* @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
AnnaBridge	171:3a7713b1edbc	1605	* @retval None
AnnaBridge	171:3a7713b1edbc	1606	*/
AnnaBridge	171:3a7713b1edbc	1607	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void)
AnnaBridge	171:3a7713b1edbc	1608	{
AnnaBridge	171:3a7713b1edbc	1609	CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
AnnaBridge	171:3a7713b1edbc	1610	SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);
AnnaBridge	171:3a7713b1edbc	1611	}
AnnaBridge	171:3a7713b1edbc	1612
AnnaBridge	171:3a7713b1edbc	1613	#if defined(AFIO_MAPR_SPI3_REMAP)
AnnaBridge	171:3a7713b1edbc	1614
AnnaBridge	171:3a7713b1edbc	1615	/**
AnnaBridge	171:3a7713b1edbc	1616	* @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
AnnaBridge	171:3a7713b1edbc	1617	* @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3
AnnaBridge	171:3a7713b1edbc	1618	* @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
AnnaBridge	171:3a7713b1edbc	1619	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1620	* @retval None
AnnaBridge	171:3a7713b1edbc	1621	*/
AnnaBridge	171:3a7713b1edbc	1622	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
AnnaBridge	171:3a7713b1edbc	1623	{
AnnaBridge	171:3a7713b1edbc	1624	SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
AnnaBridge	171:3a7713b1edbc	1625	}
AnnaBridge	171:3a7713b1edbc	1626
AnnaBridge	171:3a7713b1edbc	1627	/**
AnnaBridge	171:3a7713b1edbc	1628	* @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
AnnaBridge	171:3a7713b1edbc	1629	* @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3
AnnaBridge	171:3a7713b1edbc	1630	* @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
AnnaBridge	171:3a7713b1edbc	1631	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1632	* @retval None
AnnaBridge	171:3a7713b1edbc	1633	*/
AnnaBridge	171:3a7713b1edbc	1634	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
AnnaBridge	171:3a7713b1edbc	1635	{
AnnaBridge	171:3a7713b1edbc	1636	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
AnnaBridge	171:3a7713b1edbc	1637	}
AnnaBridge	171:3a7713b1edbc	1638
AnnaBridge	171:3a7713b1edbc	1639	/**
AnnaBridge	171:3a7713b1edbc	1640	* @brief Check if SPI3 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1641	* @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
AnnaBridge	171:3a7713b1edbc	1642	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1643	*/
AnnaBridge	171:3a7713b1edbc	1644	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void)
AnnaBridge	171:3a7713b1edbc	1645	{
AnnaBridge	171:3a7713b1edbc	1646	return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP));
AnnaBridge	171:3a7713b1edbc	1647	}
AnnaBridge	171:3a7713b1edbc	1648	#endif
AnnaBridge	171:3a7713b1edbc	1649
AnnaBridge	171:3a7713b1edbc	1650	#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
AnnaBridge	171:3a7713b1edbc	1651
AnnaBridge	171:3a7713b1edbc	1652	/**
AnnaBridge	171:3a7713b1edbc	1653	* @brief Control of TIM2_ITR1 internal mapping.
AnnaBridge	171:3a7713b1edbc	1654	* @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB
AnnaBridge	171:3a7713b1edbc	1655	* @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
AnnaBridge	171:3a7713b1edbc	1656	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1657	* @retval None
AnnaBridge	171:3a7713b1edbc	1658	*/
AnnaBridge	171:3a7713b1edbc	1659	__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
AnnaBridge	171:3a7713b1edbc	1660	{
AnnaBridge	171:3a7713b1edbc	1661	SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
AnnaBridge	171:3a7713b1edbc	1662	}
AnnaBridge	171:3a7713b1edbc	1663
AnnaBridge	171:3a7713b1edbc	1664	/**
AnnaBridge	171:3a7713b1edbc	1665	* @brief Control of TIM2_ITR1 internal mapping.
AnnaBridge	171:3a7713b1edbc	1666	* @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
AnnaBridge	171:3a7713b1edbc	1667	* @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
AnnaBridge	171:3a7713b1edbc	1668	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1669	* @retval None
AnnaBridge	171:3a7713b1edbc	1670	*/
AnnaBridge	171:3a7713b1edbc	1671	__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
AnnaBridge	171:3a7713b1edbc	1672	{
AnnaBridge	171:3a7713b1edbc	1673	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
AnnaBridge	171:3a7713b1edbc	1674	}
AnnaBridge	171:3a7713b1edbc	1675	#endif
AnnaBridge	171:3a7713b1edbc	1676
AnnaBridge	171:3a7713b1edbc	1677	#if defined(AFIO_MAPR_PTP_PPS_REMAP)
AnnaBridge	171:3a7713b1edbc	1678
AnnaBridge	171:3a7713b1edbc	1679	/**
AnnaBridge	171:3a7713b1edbc	1680	* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
AnnaBridge	171:3a7713b1edbc	1681	* @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS
AnnaBridge	171:3a7713b1edbc	1682	* @note ENABLE: PTP_PPS is output on PB5 pin.
AnnaBridge	171:3a7713b1edbc	1683	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1684	* @retval None
AnnaBridge	171:3a7713b1edbc	1685	*/
AnnaBridge	171:3a7713b1edbc	1686	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
AnnaBridge	171:3a7713b1edbc	1687	{
AnnaBridge	171:3a7713b1edbc	1688	SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
AnnaBridge	171:3a7713b1edbc	1689	}
AnnaBridge	171:3a7713b1edbc	1690
AnnaBridge	171:3a7713b1edbc	1691	/**
AnnaBridge	171:3a7713b1edbc	1692	* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
AnnaBridge	171:3a7713b1edbc	1693	* @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
AnnaBridge	171:3a7713b1edbc	1694	* @note DISABLE: PTP_PPS not output on PB5 pin.
AnnaBridge	171:3a7713b1edbc	1695	* @note This bit is available only in connectivity line devices and is reserved otherwise.
AnnaBridge	171:3a7713b1edbc	1696	* @retval None
AnnaBridge	171:3a7713b1edbc	1697	*/
AnnaBridge	171:3a7713b1edbc	1698	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
AnnaBridge	171:3a7713b1edbc	1699	{
AnnaBridge	171:3a7713b1edbc	1700	CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
AnnaBridge	171:3a7713b1edbc	1701	}
AnnaBridge	171:3a7713b1edbc	1702	#endif
AnnaBridge	171:3a7713b1edbc	1703
AnnaBridge	171:3a7713b1edbc	1704	#if defined(AFIO_MAPR2_TIM9_REMAP)
AnnaBridge	171:3a7713b1edbc	1705
AnnaBridge	171:3a7713b1edbc	1706	/**
AnnaBridge	171:3a7713b1edbc	1707	* @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
AnnaBridge	171:3a7713b1edbc	1708	* @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9
AnnaBridge	171:3a7713b1edbc	1709	* @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
AnnaBridge	171:3a7713b1edbc	1710	* @retval None
AnnaBridge	171:3a7713b1edbc	1711	*/
AnnaBridge	171:3a7713b1edbc	1712	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void)
AnnaBridge	171:3a7713b1edbc	1713	{
AnnaBridge	171:3a7713b1edbc	1714	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
AnnaBridge	171:3a7713b1edbc	1715	}
AnnaBridge	171:3a7713b1edbc	1716
AnnaBridge	171:3a7713b1edbc	1717	/**
AnnaBridge	171:3a7713b1edbc	1718	* @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
AnnaBridge	171:3a7713b1edbc	1719	* @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9
AnnaBridge	171:3a7713b1edbc	1720	* @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
AnnaBridge	171:3a7713b1edbc	1721	* @retval None
AnnaBridge	171:3a7713b1edbc	1722	*/
AnnaBridge	171:3a7713b1edbc	1723	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void)
AnnaBridge	171:3a7713b1edbc	1724	{
AnnaBridge	171:3a7713b1edbc	1725	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
AnnaBridge	171:3a7713b1edbc	1726	}
AnnaBridge	171:3a7713b1edbc	1727
AnnaBridge	171:3a7713b1edbc	1728	/**
AnnaBridge	171:3a7713b1edbc	1729	* @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not
AnnaBridge	171:3a7713b1edbc	1730	* @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9
AnnaBridge	171:3a7713b1edbc	1731	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1732	*/
AnnaBridge	171:3a7713b1edbc	1733	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void)
AnnaBridge	171:3a7713b1edbc	1734	{
AnnaBridge	171:3a7713b1edbc	1735	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP));
AnnaBridge	171:3a7713b1edbc	1736	}
AnnaBridge	171:3a7713b1edbc	1737	#endif
AnnaBridge	171:3a7713b1edbc	1738
AnnaBridge	171:3a7713b1edbc	1739	#if defined(AFIO_MAPR2_TIM10_REMAP)
AnnaBridge	171:3a7713b1edbc	1740
AnnaBridge	171:3a7713b1edbc	1741	/**
AnnaBridge	171:3a7713b1edbc	1742	* @brief Enable the remapping of TIM10_CH1.
AnnaBridge	171:3a7713b1edbc	1743	* @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10
AnnaBridge	171:3a7713b1edbc	1744	* @note ENABLE: Remap (TIM10_CH1 on PF6).
AnnaBridge	171:3a7713b1edbc	1745	* @retval None
AnnaBridge	171:3a7713b1edbc	1746	*/
AnnaBridge	171:3a7713b1edbc	1747	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void)
AnnaBridge	171:3a7713b1edbc	1748	{
AnnaBridge	171:3a7713b1edbc	1749	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
AnnaBridge	171:3a7713b1edbc	1750	}
AnnaBridge	171:3a7713b1edbc	1751
AnnaBridge	171:3a7713b1edbc	1752	/**
AnnaBridge	171:3a7713b1edbc	1753	* @brief Disable the remapping of TIM10_CH1.
AnnaBridge	171:3a7713b1edbc	1754	* @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10
AnnaBridge	171:3a7713b1edbc	1755	* @note DISABLE: No remap (TIM10_CH1 on PB8).
AnnaBridge	171:3a7713b1edbc	1756	* @retval None
AnnaBridge	171:3a7713b1edbc	1757	*/
AnnaBridge	171:3a7713b1edbc	1758	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void)
AnnaBridge	171:3a7713b1edbc	1759	{
AnnaBridge	171:3a7713b1edbc	1760	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
AnnaBridge	171:3a7713b1edbc	1761	}
AnnaBridge	171:3a7713b1edbc	1762
AnnaBridge	171:3a7713b1edbc	1763	/**
AnnaBridge	171:3a7713b1edbc	1764	* @brief Check if TIM10_CH1 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1765	* @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10
AnnaBridge	171:3a7713b1edbc	1766	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1767	*/
AnnaBridge	171:3a7713b1edbc	1768	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void)
AnnaBridge	171:3a7713b1edbc	1769	{
AnnaBridge	171:3a7713b1edbc	1770	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP));
AnnaBridge	171:3a7713b1edbc	1771	}
AnnaBridge	171:3a7713b1edbc	1772	#endif
AnnaBridge	171:3a7713b1edbc	1773
AnnaBridge	171:3a7713b1edbc	1774	#if defined(AFIO_MAPR2_TIM11_REMAP)
AnnaBridge	171:3a7713b1edbc	1775	/**
AnnaBridge	171:3a7713b1edbc	1776	* @brief Enable the remapping of TIM11_CH1.
AnnaBridge	171:3a7713b1edbc	1777	* @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11
AnnaBridge	171:3a7713b1edbc	1778	* @note ENABLE: Remap (TIM11_CH1 on PF7).
AnnaBridge	171:3a7713b1edbc	1779	* @retval None
AnnaBridge	171:3a7713b1edbc	1780	*/
AnnaBridge	171:3a7713b1edbc	1781	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void)
AnnaBridge	171:3a7713b1edbc	1782	{
AnnaBridge	171:3a7713b1edbc	1783	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
AnnaBridge	171:3a7713b1edbc	1784	}
AnnaBridge	171:3a7713b1edbc	1785
AnnaBridge	171:3a7713b1edbc	1786	/**
AnnaBridge	171:3a7713b1edbc	1787	* @brief Disable the remapping of TIM11_CH1.
AnnaBridge	171:3a7713b1edbc	1788	* @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11
AnnaBridge	171:3a7713b1edbc	1789	* @note DISABLE: No remap (TIM11_CH1 on PB9).
AnnaBridge	171:3a7713b1edbc	1790	* @retval None
AnnaBridge	171:3a7713b1edbc	1791	*/
AnnaBridge	171:3a7713b1edbc	1792	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void)
AnnaBridge	171:3a7713b1edbc	1793	{
AnnaBridge	171:3a7713b1edbc	1794	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
AnnaBridge	171:3a7713b1edbc	1795	}
AnnaBridge	171:3a7713b1edbc	1796
AnnaBridge	171:3a7713b1edbc	1797	/**
AnnaBridge	171:3a7713b1edbc	1798	* @brief Check if TIM11_CH1 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1799	* @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11
AnnaBridge	171:3a7713b1edbc	1800	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1801	*/
AnnaBridge	171:3a7713b1edbc	1802	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void)
AnnaBridge	171:3a7713b1edbc	1803	{
AnnaBridge	171:3a7713b1edbc	1804	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP));
AnnaBridge	171:3a7713b1edbc	1805	}
AnnaBridge	171:3a7713b1edbc	1806	#endif
AnnaBridge	171:3a7713b1edbc	1807
AnnaBridge	171:3a7713b1edbc	1808	#if defined(AFIO_MAPR2_TIM13_REMAP)
AnnaBridge	171:3a7713b1edbc	1809
AnnaBridge	171:3a7713b1edbc	1810	/**
AnnaBridge	171:3a7713b1edbc	1811	* @brief Enable the remapping of TIM13_CH1.
AnnaBridge	171:3a7713b1edbc	1812	* @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13
AnnaBridge	171:3a7713b1edbc	1813	* @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
AnnaBridge	171:3a7713b1edbc	1814	* @retval None
AnnaBridge	171:3a7713b1edbc	1815	*/
AnnaBridge	171:3a7713b1edbc	1816	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void)
AnnaBridge	171:3a7713b1edbc	1817	{
AnnaBridge	171:3a7713b1edbc	1818	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
AnnaBridge	171:3a7713b1edbc	1819	}
AnnaBridge	171:3a7713b1edbc	1820
AnnaBridge	171:3a7713b1edbc	1821	/**
AnnaBridge	171:3a7713b1edbc	1822	* @brief Disable the remapping of TIM13_CH1.
AnnaBridge	171:3a7713b1edbc	1823	* @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13
AnnaBridge	171:3a7713b1edbc	1824	* @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
AnnaBridge	171:3a7713b1edbc	1825	* @retval None
AnnaBridge	171:3a7713b1edbc	1826	*/
AnnaBridge	171:3a7713b1edbc	1827	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void)
AnnaBridge	171:3a7713b1edbc	1828	{
AnnaBridge	171:3a7713b1edbc	1829	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
AnnaBridge	171:3a7713b1edbc	1830	}
AnnaBridge	171:3a7713b1edbc	1831
AnnaBridge	171:3a7713b1edbc	1832	/**
AnnaBridge	171:3a7713b1edbc	1833	* @brief Check if TIM13_CH1 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1834	* @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13
AnnaBridge	171:3a7713b1edbc	1835	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1836	*/
AnnaBridge	171:3a7713b1edbc	1837	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void)
AnnaBridge	171:3a7713b1edbc	1838	{
AnnaBridge	171:3a7713b1edbc	1839	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP));
AnnaBridge	171:3a7713b1edbc	1840	}
AnnaBridge	171:3a7713b1edbc	1841	#endif
AnnaBridge	171:3a7713b1edbc	1842
AnnaBridge	171:3a7713b1edbc	1843	#if defined(AFIO_MAPR2_TIM14_REMAP)
AnnaBridge	171:3a7713b1edbc	1844
AnnaBridge	171:3a7713b1edbc	1845	/**
AnnaBridge	171:3a7713b1edbc	1846	* @brief Enable the remapping of TIM14_CH1.
AnnaBridge	171:3a7713b1edbc	1847	* @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14
AnnaBridge	171:3a7713b1edbc	1848	* @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
AnnaBridge	171:3a7713b1edbc	1849	* @retval None
AnnaBridge	171:3a7713b1edbc	1850	*/
AnnaBridge	171:3a7713b1edbc	1851	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void)
AnnaBridge	171:3a7713b1edbc	1852	{
AnnaBridge	171:3a7713b1edbc	1853	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
AnnaBridge	171:3a7713b1edbc	1854	}
AnnaBridge	171:3a7713b1edbc	1855
AnnaBridge	171:3a7713b1edbc	1856	/**
AnnaBridge	171:3a7713b1edbc	1857	* @brief Disable the remapping of TIM14_CH1.
AnnaBridge	171:3a7713b1edbc	1858	* @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14
AnnaBridge	171:3a7713b1edbc	1859	* @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
AnnaBridge	171:3a7713b1edbc	1860	* @retval None
AnnaBridge	171:3a7713b1edbc	1861	*/
AnnaBridge	171:3a7713b1edbc	1862	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void)
AnnaBridge	171:3a7713b1edbc	1863	{
AnnaBridge	171:3a7713b1edbc	1864	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
AnnaBridge	171:3a7713b1edbc	1865	}
AnnaBridge	171:3a7713b1edbc	1866
AnnaBridge	171:3a7713b1edbc	1867	/**
AnnaBridge	171:3a7713b1edbc	1868	* @brief Check if TIM14_CH1 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1869	* @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14
AnnaBridge	171:3a7713b1edbc	1870	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1871	*/
AnnaBridge	171:3a7713b1edbc	1872	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void)
AnnaBridge	171:3a7713b1edbc	1873	{
AnnaBridge	171:3a7713b1edbc	1874	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP));
AnnaBridge	171:3a7713b1edbc	1875	}
AnnaBridge	171:3a7713b1edbc	1876	#endif
AnnaBridge	171:3a7713b1edbc	1877
AnnaBridge	171:3a7713b1edbc	1878	#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
AnnaBridge	171:3a7713b1edbc	1879
AnnaBridge	171:3a7713b1edbc	1880	/**
AnnaBridge	171:3a7713b1edbc	1881	* @brief Controls the use of the optional FSMC_NADV signal.
AnnaBridge	171:3a7713b1edbc	1882	* @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV
AnnaBridge	171:3a7713b1edbc	1883	* @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
AnnaBridge	171:3a7713b1edbc	1884	* @retval None
AnnaBridge	171:3a7713b1edbc	1885	*/
AnnaBridge	171:3a7713b1edbc	1886	__STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void)
AnnaBridge	171:3a7713b1edbc	1887	{
AnnaBridge	171:3a7713b1edbc	1888	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
AnnaBridge	171:3a7713b1edbc	1889	}
AnnaBridge	171:3a7713b1edbc	1890
AnnaBridge	171:3a7713b1edbc	1891	/**
AnnaBridge	171:3a7713b1edbc	1892	* @brief Controls the use of the optional FSMC_NADV signal.
AnnaBridge	171:3a7713b1edbc	1893	* @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV
AnnaBridge	171:3a7713b1edbc	1894	* @note CONNECTED: The NADV signal is connected to the output (default).
AnnaBridge	171:3a7713b1edbc	1895	* @retval None
AnnaBridge	171:3a7713b1edbc	1896	*/
AnnaBridge	171:3a7713b1edbc	1897	__STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void)
AnnaBridge	171:3a7713b1edbc	1898	{
AnnaBridge	171:3a7713b1edbc	1899	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
AnnaBridge	171:3a7713b1edbc	1900	}
AnnaBridge	171:3a7713b1edbc	1901	#endif
AnnaBridge	171:3a7713b1edbc	1902
AnnaBridge	171:3a7713b1edbc	1903	#if defined(AFIO_MAPR2_TIM15_REMAP)
AnnaBridge	171:3a7713b1edbc	1904
AnnaBridge	171:3a7713b1edbc	1905	/**
AnnaBridge	171:3a7713b1edbc	1906	* @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
AnnaBridge	171:3a7713b1edbc	1907	* @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15
AnnaBridge	171:3a7713b1edbc	1908	* @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
AnnaBridge	171:3a7713b1edbc	1909	* @retval None
AnnaBridge	171:3a7713b1edbc	1910	*/
AnnaBridge	171:3a7713b1edbc	1911	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void)
AnnaBridge	171:3a7713b1edbc	1912	{
AnnaBridge	171:3a7713b1edbc	1913	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
AnnaBridge	171:3a7713b1edbc	1914	}
AnnaBridge	171:3a7713b1edbc	1915	/**
AnnaBridge	171:3a7713b1edbc	1916	* @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
AnnaBridge	171:3a7713b1edbc	1917	* @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15
AnnaBridge	171:3a7713b1edbc	1918	* @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
AnnaBridge	171:3a7713b1edbc	1919	* @retval None
AnnaBridge	171:3a7713b1edbc	1920	*/
AnnaBridge	171:3a7713b1edbc	1921	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void)
AnnaBridge	171:3a7713b1edbc	1922	{
AnnaBridge	171:3a7713b1edbc	1923	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
AnnaBridge	171:3a7713b1edbc	1924	}
AnnaBridge	171:3a7713b1edbc	1925
AnnaBridge	171:3a7713b1edbc	1926	/**
AnnaBridge	171:3a7713b1edbc	1927	* @brief Check if TIM15_CH1 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1928	* @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15
AnnaBridge	171:3a7713b1edbc	1929	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1930	*/
AnnaBridge	171:3a7713b1edbc	1931	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void)
AnnaBridge	171:3a7713b1edbc	1932	{
AnnaBridge	171:3a7713b1edbc	1933	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP));
AnnaBridge	171:3a7713b1edbc	1934	}
AnnaBridge	171:3a7713b1edbc	1935	#endif
AnnaBridge	171:3a7713b1edbc	1936
AnnaBridge	171:3a7713b1edbc	1937	#if defined(AFIO_MAPR2_TIM16_REMAP)
AnnaBridge	171:3a7713b1edbc	1938
AnnaBridge	171:3a7713b1edbc	1939	/**
AnnaBridge	171:3a7713b1edbc	1940	* @brief Enable the remapping of TIM16_CH1.
AnnaBridge	171:3a7713b1edbc	1941	* @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16
AnnaBridge	171:3a7713b1edbc	1942	* @note ENABLE: Remap (TIM16_CH1 on PA6).
AnnaBridge	171:3a7713b1edbc	1943	* @retval None
AnnaBridge	171:3a7713b1edbc	1944	*/
AnnaBridge	171:3a7713b1edbc	1945	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void)
AnnaBridge	171:3a7713b1edbc	1946	{
AnnaBridge	171:3a7713b1edbc	1947	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
AnnaBridge	171:3a7713b1edbc	1948	}
AnnaBridge	171:3a7713b1edbc	1949
AnnaBridge	171:3a7713b1edbc	1950	/**
AnnaBridge	171:3a7713b1edbc	1951	* @brief Disable the remapping of TIM16_CH1.
AnnaBridge	171:3a7713b1edbc	1952	* @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16
AnnaBridge	171:3a7713b1edbc	1953	* @note DISABLE: No remap (TIM16_CH1 on PB8).
AnnaBridge	171:3a7713b1edbc	1954	* @retval None
AnnaBridge	171:3a7713b1edbc	1955	*/
AnnaBridge	171:3a7713b1edbc	1956	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void)
AnnaBridge	171:3a7713b1edbc	1957	{
AnnaBridge	171:3a7713b1edbc	1958	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
AnnaBridge	171:3a7713b1edbc	1959	}
AnnaBridge	171:3a7713b1edbc	1960
AnnaBridge	171:3a7713b1edbc	1961	/**
AnnaBridge	171:3a7713b1edbc	1962	* @brief Check if TIM16_CH1 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1963	* @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16
AnnaBridge	171:3a7713b1edbc	1964	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1965	*/
AnnaBridge	171:3a7713b1edbc	1966	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void)
AnnaBridge	171:3a7713b1edbc	1967	{
AnnaBridge	171:3a7713b1edbc	1968	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP));
AnnaBridge	171:3a7713b1edbc	1969	}
AnnaBridge	171:3a7713b1edbc	1970	#endif
AnnaBridge	171:3a7713b1edbc	1971
AnnaBridge	171:3a7713b1edbc	1972	#if defined(AFIO_MAPR2_TIM17_REMAP)
AnnaBridge	171:3a7713b1edbc	1973
AnnaBridge	171:3a7713b1edbc	1974	/**
AnnaBridge	171:3a7713b1edbc	1975	* @brief Enable the remapping of TIM17_CH1.
AnnaBridge	171:3a7713b1edbc	1976	* @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17
AnnaBridge	171:3a7713b1edbc	1977	* @note ENABLE: Remap (TIM17_CH1 on PA7).
AnnaBridge	171:3a7713b1edbc	1978	* @retval None
AnnaBridge	171:3a7713b1edbc	1979	*/
AnnaBridge	171:3a7713b1edbc	1980	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void)
AnnaBridge	171:3a7713b1edbc	1981	{
AnnaBridge	171:3a7713b1edbc	1982	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
AnnaBridge	171:3a7713b1edbc	1983	}
AnnaBridge	171:3a7713b1edbc	1984
AnnaBridge	171:3a7713b1edbc	1985	/**
AnnaBridge	171:3a7713b1edbc	1986	* @brief Disable the remapping of TIM17_CH1.
AnnaBridge	171:3a7713b1edbc	1987	* @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17
AnnaBridge	171:3a7713b1edbc	1988	* @note DISABLE: No remap (TIM17_CH1 on PB9).
AnnaBridge	171:3a7713b1edbc	1989	* @retval None
AnnaBridge	171:3a7713b1edbc	1990	*/
AnnaBridge	171:3a7713b1edbc	1991	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void)
AnnaBridge	171:3a7713b1edbc	1992	{
AnnaBridge	171:3a7713b1edbc	1993	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
AnnaBridge	171:3a7713b1edbc	1994	}
AnnaBridge	171:3a7713b1edbc	1995
AnnaBridge	171:3a7713b1edbc	1996	/**
AnnaBridge	171:3a7713b1edbc	1997	* @brief Check if TIM17_CH1 has been remaped or not
AnnaBridge	171:3a7713b1edbc	1998	* @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17
AnnaBridge	171:3a7713b1edbc	1999	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2000	*/
AnnaBridge	171:3a7713b1edbc	2001	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void)
AnnaBridge	171:3a7713b1edbc	2002	{
AnnaBridge	171:3a7713b1edbc	2003	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP));
AnnaBridge	171:3a7713b1edbc	2004	}
AnnaBridge	171:3a7713b1edbc	2005	#endif
AnnaBridge	171:3a7713b1edbc	2006
AnnaBridge	171:3a7713b1edbc	2007	#if defined(AFIO_MAPR2_CEC_REMAP)
AnnaBridge	171:3a7713b1edbc	2008
AnnaBridge	171:3a7713b1edbc	2009	/**
AnnaBridge	171:3a7713b1edbc	2010	* @brief Enable the remapping of CEC.
AnnaBridge	171:3a7713b1edbc	2011	* @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC
AnnaBridge	171:3a7713b1edbc	2012	* @note ENABLE: Remap (CEC on PB10).
AnnaBridge	171:3a7713b1edbc	2013	* @retval None
AnnaBridge	171:3a7713b1edbc	2014	*/
AnnaBridge	171:3a7713b1edbc	2015	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void)
AnnaBridge	171:3a7713b1edbc	2016	{
AnnaBridge	171:3a7713b1edbc	2017	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
AnnaBridge	171:3a7713b1edbc	2018	}
AnnaBridge	171:3a7713b1edbc	2019
AnnaBridge	171:3a7713b1edbc	2020	/**
AnnaBridge	171:3a7713b1edbc	2021	* @brief Disable the remapping of CEC.
AnnaBridge	171:3a7713b1edbc	2022	* @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC
AnnaBridge	171:3a7713b1edbc	2023	* @note DISABLE: No remap (CEC on PB8).
AnnaBridge	171:3a7713b1edbc	2024	* @retval None
AnnaBridge	171:3a7713b1edbc	2025	*/
AnnaBridge	171:3a7713b1edbc	2026	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void)
AnnaBridge	171:3a7713b1edbc	2027	{
AnnaBridge	171:3a7713b1edbc	2028	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
AnnaBridge	171:3a7713b1edbc	2029	}
AnnaBridge	171:3a7713b1edbc	2030
AnnaBridge	171:3a7713b1edbc	2031	/**
AnnaBridge	171:3a7713b1edbc	2032	* @brief Check if CEC has been remaped or not
AnnaBridge	171:3a7713b1edbc	2033	* @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC
AnnaBridge	171:3a7713b1edbc	2034	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2035	*/
AnnaBridge	171:3a7713b1edbc	2036	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void)
AnnaBridge	171:3a7713b1edbc	2037	{
AnnaBridge	171:3a7713b1edbc	2038	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP));
AnnaBridge	171:3a7713b1edbc	2039	}
AnnaBridge	171:3a7713b1edbc	2040	#endif
AnnaBridge	171:3a7713b1edbc	2041
AnnaBridge	171:3a7713b1edbc	2042	#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
AnnaBridge	171:3a7713b1edbc	2043
AnnaBridge	171:3a7713b1edbc	2044	/**
AnnaBridge	171:3a7713b1edbc	2045	* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
AnnaBridge	171:3a7713b1edbc	2046	* @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA
AnnaBridge	171:3a7713b1edbc	2047	* @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
AnnaBridge	171:3a7713b1edbc	2048	* @retval None
AnnaBridge	171:3a7713b1edbc	2049	*/
AnnaBridge	171:3a7713b1edbc	2050	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void)
AnnaBridge	171:3a7713b1edbc	2051	{
AnnaBridge	171:3a7713b1edbc	2052	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
AnnaBridge	171:3a7713b1edbc	2053	}
AnnaBridge	171:3a7713b1edbc	2054
AnnaBridge	171:3a7713b1edbc	2055	/**
AnnaBridge	171:3a7713b1edbc	2056	* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
AnnaBridge	171:3a7713b1edbc	2057	* @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA
AnnaBridge	171:3a7713b1edbc	2058	* @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
AnnaBridge	171:3a7713b1edbc	2059	* @retval None
AnnaBridge	171:3a7713b1edbc	2060	*/
AnnaBridge	171:3a7713b1edbc	2061	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void)
AnnaBridge	171:3a7713b1edbc	2062	{
AnnaBridge	171:3a7713b1edbc	2063	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
AnnaBridge	171:3a7713b1edbc	2064	}
AnnaBridge	171:3a7713b1edbc	2065
AnnaBridge	171:3a7713b1edbc	2066	/**
AnnaBridge	171:3a7713b1edbc	2067	* @brief Check if TIM1DMA has been remaped or not
AnnaBridge	171:3a7713b1edbc	2068	* @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA
AnnaBridge	171:3a7713b1edbc	2069	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2070	*/
AnnaBridge	171:3a7713b1edbc	2071	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)
AnnaBridge	171:3a7713b1edbc	2072	{
AnnaBridge	171:3a7713b1edbc	2073	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP));
AnnaBridge	171:3a7713b1edbc	2074	}
AnnaBridge	171:3a7713b1edbc	2075	#endif
AnnaBridge	171:3a7713b1edbc	2076
AnnaBridge	171:3a7713b1edbc	2077	#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
AnnaBridge	171:3a7713b1edbc	2078
AnnaBridge	171:3a7713b1edbc	2079	/**
AnnaBridge	171:3a7713b1edbc	2080	* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
AnnaBridge	171:3a7713b1edbc	2081	* @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA
AnnaBridge	171:3a7713b1edbc	2082	* @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
AnnaBridge	171:3a7713b1edbc	2083	* @retval None
AnnaBridge	171:3a7713b1edbc	2084	*/
AnnaBridge	171:3a7713b1edbc	2085	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)
AnnaBridge	171:3a7713b1edbc	2086	{
AnnaBridge	171:3a7713b1edbc	2087	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
AnnaBridge	171:3a7713b1edbc	2088	}
AnnaBridge	171:3a7713b1edbc	2089
AnnaBridge	171:3a7713b1edbc	2090	/**
AnnaBridge	171:3a7713b1edbc	2091	* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
AnnaBridge	171:3a7713b1edbc	2092	* @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA
AnnaBridge	171:3a7713b1edbc	2093	* @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
AnnaBridge	171:3a7713b1edbc	2094	* @retval None
AnnaBridge	171:3a7713b1edbc	2095	*/
AnnaBridge	171:3a7713b1edbc	2096	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)
AnnaBridge	171:3a7713b1edbc	2097	{
AnnaBridge	171:3a7713b1edbc	2098	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
AnnaBridge	171:3a7713b1edbc	2099	}
AnnaBridge	171:3a7713b1edbc	2100
AnnaBridge	171:3a7713b1edbc	2101	/**
AnnaBridge	171:3a7713b1edbc	2102	* @brief Check if TIM67DACDMA has been remaped or not
AnnaBridge	171:3a7713b1edbc	2103	* @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA
AnnaBridge	171:3a7713b1edbc	2104	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2105	*/
AnnaBridge	171:3a7713b1edbc	2106	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)
AnnaBridge	171:3a7713b1edbc	2107	{
AnnaBridge	171:3a7713b1edbc	2108	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP));
AnnaBridge	171:3a7713b1edbc	2109	}
AnnaBridge	171:3a7713b1edbc	2110	#endif
AnnaBridge	171:3a7713b1edbc	2111
AnnaBridge	171:3a7713b1edbc	2112	#if defined(AFIO_MAPR2_TIM12_REMAP)
AnnaBridge	171:3a7713b1edbc	2113
AnnaBridge	171:3a7713b1edbc	2114	/**
AnnaBridge	171:3a7713b1edbc	2115	* @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
AnnaBridge	171:3a7713b1edbc	2116	* @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12
AnnaBridge	171:3a7713b1edbc	2117	* @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
AnnaBridge	171:3a7713b1edbc	2118	* @note This bit is available only in high density value line devices.
AnnaBridge	171:3a7713b1edbc	2119	* @retval None
AnnaBridge	171:3a7713b1edbc	2120	*/
AnnaBridge	171:3a7713b1edbc	2121	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void)
AnnaBridge	171:3a7713b1edbc	2122	{
AnnaBridge	171:3a7713b1edbc	2123	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
AnnaBridge	171:3a7713b1edbc	2124	}
AnnaBridge	171:3a7713b1edbc	2125
AnnaBridge	171:3a7713b1edbc	2126	/**
AnnaBridge	171:3a7713b1edbc	2127	* @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
AnnaBridge	171:3a7713b1edbc	2128	* @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12
AnnaBridge	171:3a7713b1edbc	2129	* @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
AnnaBridge	171:3a7713b1edbc	2130	* @note This bit is available only in high density value line devices.
AnnaBridge	171:3a7713b1edbc	2131	* @retval None
AnnaBridge	171:3a7713b1edbc	2132	*/
AnnaBridge	171:3a7713b1edbc	2133	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void)
AnnaBridge	171:3a7713b1edbc	2134	{
AnnaBridge	171:3a7713b1edbc	2135	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
AnnaBridge	171:3a7713b1edbc	2136	}
AnnaBridge	171:3a7713b1edbc	2137
AnnaBridge	171:3a7713b1edbc	2138	/**
AnnaBridge	171:3a7713b1edbc	2139	* @brief Check if TIM12_CH1 has been remaped or not
AnnaBridge	171:3a7713b1edbc	2140	* @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12
AnnaBridge	171:3a7713b1edbc	2141	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2142	*/
AnnaBridge	171:3a7713b1edbc	2143	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void)
AnnaBridge	171:3a7713b1edbc	2144	{
AnnaBridge	171:3a7713b1edbc	2145	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP));
AnnaBridge	171:3a7713b1edbc	2146	}
AnnaBridge	171:3a7713b1edbc	2147	#endif
AnnaBridge	171:3a7713b1edbc	2148
AnnaBridge	171:3a7713b1edbc	2149	#if defined(AFIO_MAPR2_MISC_REMAP)
AnnaBridge	171:3a7713b1edbc	2150
AnnaBridge	171:3a7713b1edbc	2151	/**
AnnaBridge	171:3a7713b1edbc	2152	* @brief Miscellaneous features remapping.
AnnaBridge	171:3a7713b1edbc	2153	* This bit is set and cleared by software. It controls miscellaneous features.
AnnaBridge	171:3a7713b1edbc	2154	* The DMA2 channel 5 interrupt position in the vector table.
AnnaBridge	171:3a7713b1edbc	2155	* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
AnnaBridge	171:3a7713b1edbc	2156	* @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC
AnnaBridge	171:3a7713b1edbc	2157	* @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
AnnaBridge	171:3a7713b1edbc	2158	* selected as DAC Trigger 3, TIM15 triggers TIM1/3.
AnnaBridge	171:3a7713b1edbc	2159	* @note This bit is available only in high density value line devices.
AnnaBridge	171:3a7713b1edbc	2160	* @retval None
AnnaBridge	171:3a7713b1edbc	2161	*/
AnnaBridge	171:3a7713b1edbc	2162	__STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void)
AnnaBridge	171:3a7713b1edbc	2163	{
AnnaBridge	171:3a7713b1edbc	2164	SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
AnnaBridge	171:3a7713b1edbc	2165	}
AnnaBridge	171:3a7713b1edbc	2166
AnnaBridge	171:3a7713b1edbc	2167	/**
AnnaBridge	171:3a7713b1edbc	2168	* @brief Miscellaneous features remapping.
AnnaBridge	171:3a7713b1edbc	2169	* This bit is set and cleared by software. It controls miscellaneous features.
AnnaBridge	171:3a7713b1edbc	2170	* The DMA2 channel 5 interrupt position in the vector table.
AnnaBridge	171:3a7713b1edbc	2171	* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
AnnaBridge	171:3a7713b1edbc	2172	* @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC
AnnaBridge	171:3a7713b1edbc	2173	* @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
AnnaBridge	171:3a7713b1edbc	2174	* event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
AnnaBridge	171:3a7713b1edbc	2175	* @note This bit is available only in high density value line devices.
AnnaBridge	171:3a7713b1edbc	2176	* @retval None
AnnaBridge	171:3a7713b1edbc	2177	*/
AnnaBridge	171:3a7713b1edbc	2178	__STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void)
AnnaBridge	171:3a7713b1edbc	2179	{
AnnaBridge	171:3a7713b1edbc	2180	CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
AnnaBridge	171:3a7713b1edbc	2181	}
AnnaBridge	171:3a7713b1edbc	2182
AnnaBridge	171:3a7713b1edbc	2183	/**
AnnaBridge	171:3a7713b1edbc	2184	* @brief Check if MISC has been remaped or not
AnnaBridge	171:3a7713b1edbc	2185	* @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC
AnnaBridge	171:3a7713b1edbc	2186	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2187	*/
AnnaBridge	171:3a7713b1edbc	2188	__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void)
AnnaBridge	171:3a7713b1edbc	2189	{
AnnaBridge	171:3a7713b1edbc	2190	return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP));
AnnaBridge	171:3a7713b1edbc	2191	}
AnnaBridge	171:3a7713b1edbc	2192	#endif
AnnaBridge	171:3a7713b1edbc	2193
AnnaBridge	171:3a7713b1edbc	2194	/**
AnnaBridge	171:3a7713b1edbc	2195	* @}
AnnaBridge	171:3a7713b1edbc	2196	*/
AnnaBridge	171:3a7713b1edbc	2197
AnnaBridge	171:3a7713b1edbc	2198	/** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration
AnnaBridge	171:3a7713b1edbc	2199	* @brief This section propose definition to Configure EVENTOUT Cortex feature .
AnnaBridge	171:3a7713b1edbc	2200	* @{
AnnaBridge	171:3a7713b1edbc	2201	*/
AnnaBridge	171:3a7713b1edbc	2202
AnnaBridge	171:3a7713b1edbc	2203	/**
AnnaBridge	171:3a7713b1edbc	2204	* @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
AnnaBridge	171:3a7713b1edbc	2205	* @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n
AnnaBridge	171:3a7713b1edbc	2206	* EVCR PIN LL_GPIO_AF_ConfigEventout
AnnaBridge	171:3a7713b1edbc	2207	* @param LL_GPIO_PortSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2208	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A
AnnaBridge	171:3a7713b1edbc	2209	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B
AnnaBridge	171:3a7713b1edbc	2210	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C
AnnaBridge	171:3a7713b1edbc	2211	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D
AnnaBridge	171:3a7713b1edbc	2212	* @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E
AnnaBridge	171:3a7713b1edbc	2213	* @param LL_GPIO_PinSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2214	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0
AnnaBridge	171:3a7713b1edbc	2215	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1
AnnaBridge	171:3a7713b1edbc	2216	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2
AnnaBridge	171:3a7713b1edbc	2217	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3
AnnaBridge	171:3a7713b1edbc	2218	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4
AnnaBridge	171:3a7713b1edbc	2219	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5
AnnaBridge	171:3a7713b1edbc	2220	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6
AnnaBridge	171:3a7713b1edbc	2221	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7
AnnaBridge	171:3a7713b1edbc	2222	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8
AnnaBridge	171:3a7713b1edbc	2223	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9
AnnaBridge	171:3a7713b1edbc	2224	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10
AnnaBridge	171:3a7713b1edbc	2225	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11
AnnaBridge	171:3a7713b1edbc	2226	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12
AnnaBridge	171:3a7713b1edbc	2227	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13
AnnaBridge	171:3a7713b1edbc	2228	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14
AnnaBridge	171:3a7713b1edbc	2229	* @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15
AnnaBridge	171:3a7713b1edbc	2230	* @retval None
AnnaBridge	171:3a7713b1edbc	2231	*/
AnnaBridge	171:3a7713b1edbc	2232	__STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
AnnaBridge	171:3a7713b1edbc	2233	{
AnnaBridge	171:3a7713b1edbc	2234	MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) \| (AFIO_EVCR_PIN), (LL_GPIO_PortSource) \| (LL_GPIO_PinSource));
AnnaBridge	171:3a7713b1edbc	2235	}
AnnaBridge	171:3a7713b1edbc	2236
AnnaBridge	171:3a7713b1edbc	2237	/**
AnnaBridge	171:3a7713b1edbc	2238	* @brief Enables the Event Output.
AnnaBridge	171:3a7713b1edbc	2239	* @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout
AnnaBridge	171:3a7713b1edbc	2240	* @retval None
AnnaBridge	171:3a7713b1edbc	2241	*/
AnnaBridge	171:3a7713b1edbc	2242	__STATIC_INLINE void LL_GPIO_AF_EnableEventout(void)
AnnaBridge	171:3a7713b1edbc	2243	{
AnnaBridge	171:3a7713b1edbc	2244	SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
AnnaBridge	171:3a7713b1edbc	2245	}
AnnaBridge	171:3a7713b1edbc	2246
AnnaBridge	171:3a7713b1edbc	2247	/**
AnnaBridge	171:3a7713b1edbc	2248	* @brief Disables the Event Output.
AnnaBridge	171:3a7713b1edbc	2249	* @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout
AnnaBridge	171:3a7713b1edbc	2250	* @retval None
AnnaBridge	171:3a7713b1edbc	2251	*/
AnnaBridge	171:3a7713b1edbc	2252	__STATIC_INLINE void LL_GPIO_AF_DisableEventout(void)
AnnaBridge	171:3a7713b1edbc	2253	{
AnnaBridge	171:3a7713b1edbc	2254	CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
AnnaBridge	171:3a7713b1edbc	2255	}
AnnaBridge	171:3a7713b1edbc	2256
AnnaBridge	171:3a7713b1edbc	2257	/**
AnnaBridge	171:3a7713b1edbc	2258	* @}
AnnaBridge	171:3a7713b1edbc	2259	*/
AnnaBridge	171:3a7713b1edbc	2260	/** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt
AnnaBridge	171:3a7713b1edbc	2261	* @brief This section Configure source input for the EXTI external interrupt .
AnnaBridge	171:3a7713b1edbc	2262	* @{
AnnaBridge	171:3a7713b1edbc	2263	*/
AnnaBridge	171:3a7713b1edbc	2264
AnnaBridge	171:3a7713b1edbc	2265	/**
AnnaBridge	171:3a7713b1edbc	2266	* @brief Configure source input for the EXTI external interrupt.
AnnaBridge	171:3a7713b1edbc	2267	* @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	2268	* AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	2269	* AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	2270	* AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource
AnnaBridge	171:3a7713b1edbc	2271	* @param Port This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2272	* @arg @ref LL_GPIO_AF_EXTI_PORTA
AnnaBridge	171:3a7713b1edbc	2273	* @arg @ref LL_GPIO_AF_EXTI_PORTB
AnnaBridge	171:3a7713b1edbc	2274	* @arg @ref LL_GPIO_AF_EXTI_PORTC
AnnaBridge	171:3a7713b1edbc	2275	* @arg @ref LL_GPIO_AF_EXTI_PORTD
AnnaBridge	171:3a7713b1edbc	2276	* @arg @ref LL_GPIO_AF_EXTI_PORTE
AnnaBridge	171:3a7713b1edbc	2277	* @arg @ref LL_GPIO_AF_EXTI_PORTF
AnnaBridge	171:3a7713b1edbc	2278	* @arg @ref LL_GPIO_AF_EXTI_PORTG
AnnaBridge	171:3a7713b1edbc	2279	* @param Line This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2280	* @arg @ref LL_GPIO_AF_EXTI_LINE0
AnnaBridge	171:3a7713b1edbc	2281	* @arg @ref LL_GPIO_AF_EXTI_LINE1
AnnaBridge	171:3a7713b1edbc	2282	* @arg @ref LL_GPIO_AF_EXTI_LINE2
AnnaBridge	171:3a7713b1edbc	2283	* @arg @ref LL_GPIO_AF_EXTI_LINE3
AnnaBridge	171:3a7713b1edbc	2284	* @arg @ref LL_GPIO_AF_EXTI_LINE4
AnnaBridge	171:3a7713b1edbc	2285	* @arg @ref LL_GPIO_AF_EXTI_LINE5
AnnaBridge	171:3a7713b1edbc	2286	* @arg @ref LL_GPIO_AF_EXTI_LINE6
AnnaBridge	171:3a7713b1edbc	2287	* @arg @ref LL_GPIO_AF_EXTI_LINE7
AnnaBridge	171:3a7713b1edbc	2288	* @arg @ref LL_GPIO_AF_EXTI_LINE8
AnnaBridge	171:3a7713b1edbc	2289	* @arg @ref LL_GPIO_AF_EXTI_LINE9
AnnaBridge	171:3a7713b1edbc	2290	* @arg @ref LL_GPIO_AF_EXTI_LINE10
AnnaBridge	171:3a7713b1edbc	2291	* @arg @ref LL_GPIO_AF_EXTI_LINE11
AnnaBridge	171:3a7713b1edbc	2292	* @arg @ref LL_GPIO_AF_EXTI_LINE12
AnnaBridge	171:3a7713b1edbc	2293	* @arg @ref LL_GPIO_AF_EXTI_LINE13
AnnaBridge	171:3a7713b1edbc	2294	* @arg @ref LL_GPIO_AF_EXTI_LINE14
AnnaBridge	171:3a7713b1edbc	2295	* @arg @ref LL_GPIO_AF_EXTI_LINE15
AnnaBridge	171:3a7713b1edbc	2296	* @retval None
AnnaBridge	171:3a7713b1edbc	2297	*/
AnnaBridge	171:3a7713b1edbc	2298	__STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line)
AnnaBridge	171:3a7713b1edbc	2299	{
AnnaBridge	171:3a7713b1edbc	2300	MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
AnnaBridge	171:3a7713b1edbc	2301	}
AnnaBridge	171:3a7713b1edbc	2302
AnnaBridge	171:3a7713b1edbc	2303	/**
AnnaBridge	171:3a7713b1edbc	2304	* @brief Get the configured defined for specific EXTI Line
AnnaBridge	171:3a7713b1edbc	2305	* @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	2306	* AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	2307	* AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	2308	* AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource
AnnaBridge	171:3a7713b1edbc	2309	* @param Line This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2310	* @arg @ref LL_GPIO_AF_EXTI_LINE0
AnnaBridge	171:3a7713b1edbc	2311	* @arg @ref LL_GPIO_AF_EXTI_LINE1
AnnaBridge	171:3a7713b1edbc	2312	* @arg @ref LL_GPIO_AF_EXTI_LINE2
AnnaBridge	171:3a7713b1edbc	2313	* @arg @ref LL_GPIO_AF_EXTI_LINE3
AnnaBridge	171:3a7713b1edbc	2314	* @arg @ref LL_GPIO_AF_EXTI_LINE4
AnnaBridge	171:3a7713b1edbc	2315	* @arg @ref LL_GPIO_AF_EXTI_LINE5
AnnaBridge	171:3a7713b1edbc	2316	* @arg @ref LL_GPIO_AF_EXTI_LINE6
AnnaBridge	171:3a7713b1edbc	2317	* @arg @ref LL_GPIO_AF_EXTI_LINE7
AnnaBridge	171:3a7713b1edbc	2318	* @arg @ref LL_GPIO_AF_EXTI_LINE8
AnnaBridge	171:3a7713b1edbc	2319	* @arg @ref LL_GPIO_AF_EXTI_LINE9
AnnaBridge	171:3a7713b1edbc	2320	* @arg @ref LL_GPIO_AF_EXTI_LINE10
AnnaBridge	171:3a7713b1edbc	2321	* @arg @ref LL_GPIO_AF_EXTI_LINE11
AnnaBridge	171:3a7713b1edbc	2322	* @arg @ref LL_GPIO_AF_EXTI_LINE12
AnnaBridge	171:3a7713b1edbc	2323	* @arg @ref LL_GPIO_AF_EXTI_LINE13
AnnaBridge	171:3a7713b1edbc	2324	* @arg @ref LL_GPIO_AF_EXTI_LINE14
AnnaBridge	171:3a7713b1edbc	2325	* @arg @ref LL_GPIO_AF_EXTI_LINE15
AnnaBridge	171:3a7713b1edbc	2326	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2327	* @arg @ref LL_GPIO_AF_EXTI_PORTA
AnnaBridge	171:3a7713b1edbc	2328	* @arg @ref LL_GPIO_AF_EXTI_PORTB
AnnaBridge	171:3a7713b1edbc	2329	* @arg @ref LL_GPIO_AF_EXTI_PORTC
AnnaBridge	171:3a7713b1edbc	2330	* @arg @ref LL_GPIO_AF_EXTI_PORTD
AnnaBridge	171:3a7713b1edbc	2331	* @arg @ref LL_GPIO_AF_EXTI_PORTE
AnnaBridge	171:3a7713b1edbc	2332	* @arg @ref LL_GPIO_AF_EXTI_PORTF
AnnaBridge	171:3a7713b1edbc	2333	* @arg @ref LL_GPIO_AF_EXTI_PORTG
AnnaBridge	171:3a7713b1edbc	2334	*/
AnnaBridge	171:3a7713b1edbc	2335	__STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line)
AnnaBridge	171:3a7713b1edbc	2336	{
AnnaBridge	171:3a7713b1edbc	2337	return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
AnnaBridge	171:3a7713b1edbc	2338	}
AnnaBridge	171:3a7713b1edbc	2339
AnnaBridge	171:3a7713b1edbc	2340	/**
AnnaBridge	171:3a7713b1edbc	2341	* @}
AnnaBridge	171:3a7713b1edbc	2342	*/
AnnaBridge	171:3a7713b1edbc	2343
AnnaBridge	171:3a7713b1edbc	2344	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	2345	/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	171:3a7713b1edbc	2346	* @{
AnnaBridge	171:3a7713b1edbc	2347	*/
AnnaBridge	171:3a7713b1edbc	2348
AnnaBridge	171:3a7713b1edbc	2349	ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
AnnaBridge	171:3a7713b1edbc	2350	ErrorStatus LL_GPIO_Init(GPIO_TypeDef GPIOx, LL_GPIO_InitTypeDef GPIO_InitStruct);
AnnaBridge	171:3a7713b1edbc	2351	void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
AnnaBridge	171:3a7713b1edbc	2352
AnnaBridge	171:3a7713b1edbc	2353	/**
AnnaBridge	171:3a7713b1edbc	2354	* @}
AnnaBridge	171:3a7713b1edbc	2355	*/
AnnaBridge	171:3a7713b1edbc	2356	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	2357
AnnaBridge	171:3a7713b1edbc	2358	/**
AnnaBridge	171:3a7713b1edbc	2359	* @}
AnnaBridge	171:3a7713b1edbc	2360	*/
AnnaBridge	171:3a7713b1edbc	2361
AnnaBridge	171:3a7713b1edbc	2362	/**
AnnaBridge	171:3a7713b1edbc	2363	* @}
AnnaBridge	171:3a7713b1edbc	2364	*/
AnnaBridge	171:3a7713b1edbc	2365
AnnaBridge	171:3a7713b1edbc	2366	#endif /* defined (GPIOA) \|\| defined (GPIOB) \|\| defined (GPIOC) \|\| defined (GPIOD) \|\| defined (GPIOE) \|\| defined (GPIOF) \|\| defined (GPIOG) */
AnnaBridge	171:3a7713b1edbc	2367	/**
AnnaBridge	171:3a7713b1edbc	2368	* @}
AnnaBridge	171:3a7713b1edbc	2369	*/
AnnaBridge	171:3a7713b1edbc	2370
AnnaBridge	171:3a7713b1edbc	2371	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	2372	}
AnnaBridge	171:3a7713b1edbc	2373	#endif
AnnaBridge	171:3a7713b1edbc	2374
AnnaBridge	171:3a7713b1edbc	2375	#endif /* __STM32F1xx_LL_GPIO_H */
AnnaBridge	171:3a7713b1edbc	2376
AnnaBridge	171:3a7713b1edbc	2377	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/