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TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f1xx_ll_fsmc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f1xx_ll_fsmc.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of FSMC HAL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32F1xx_LL_FSMC_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32F1xx_LL_FSMC_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32f1xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32F1xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	#if defined(FSMC_BANK1)
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	/** @addtogroup FSMC_LL
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57
AnnaBridge	171:3a7713b1edbc	58	/* Exported typedef ----------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	59
AnnaBridge	171:3a7713b1edbc	60	/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types
AnnaBridge	171:3a7713b1edbc	61	* @{
AnnaBridge	171:3a7713b1edbc	62	*/
AnnaBridge	171:3a7713b1edbc	63
AnnaBridge	171:3a7713b1edbc	64	/**
AnnaBridge	171:3a7713b1edbc	65	* @brief FSMC NORSRAM Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	66	*/
AnnaBridge	171:3a7713b1edbc	67	typedef struct
AnnaBridge	171:3a7713b1edbc	68	{
AnnaBridge	171:3a7713b1edbc	69	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
AnnaBridge	171:3a7713b1edbc	70	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
AnnaBridge	171:3a7713b1edbc	71
AnnaBridge	171:3a7713b1edbc	72	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
AnnaBridge	171:3a7713b1edbc	73	multiplexed on the data bus or not.
AnnaBridge	171:3a7713b1edbc	74	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
AnnaBridge	171:3a7713b1edbc	75
AnnaBridge	171:3a7713b1edbc	76	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
AnnaBridge	171:3a7713b1edbc	77	the corresponding memory device.
AnnaBridge	171:3a7713b1edbc	78	This parameter can be a value of @ref FSMC_Memory_Type */
AnnaBridge	171:3a7713b1edbc	79
AnnaBridge	171:3a7713b1edbc	80	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	171:3a7713b1edbc	81	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
AnnaBridge	171:3a7713b1edbc	82
AnnaBridge	171:3a7713b1edbc	83	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
AnnaBridge	171:3a7713b1edbc	84	valid only with synchronous burst Flash memories.
AnnaBridge	171:3a7713b1edbc	85	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
AnnaBridge	171:3a7713b1edbc	86
AnnaBridge	171:3a7713b1edbc	87	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
AnnaBridge	171:3a7713b1edbc	88	the Flash memory in burst mode.
AnnaBridge	171:3a7713b1edbc	89	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
AnnaBridge	171:3a7713b1edbc	90
AnnaBridge	171:3a7713b1edbc	91	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
AnnaBridge	171:3a7713b1edbc	92	memory, valid only when accessing Flash memories in burst mode.
AnnaBridge	171:3a7713b1edbc	93	This parameter can be a value of @ref FSMC_Wrap_Mode */
AnnaBridge	171:3a7713b1edbc	94
AnnaBridge	171:3a7713b1edbc	95	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
AnnaBridge	171:3a7713b1edbc	96	clock cycle before the wait state or during the wait state,
AnnaBridge	171:3a7713b1edbc	97	valid only when accessing memories in burst mode.
AnnaBridge	171:3a7713b1edbc	98	This parameter can be a value of @ref FSMC_Wait_Timing */
AnnaBridge	171:3a7713b1edbc	99
AnnaBridge	171:3a7713b1edbc	100	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
AnnaBridge	171:3a7713b1edbc	101	This parameter can be a value of @ref FSMC_Write_Operation */
AnnaBridge	171:3a7713b1edbc	102
AnnaBridge	171:3a7713b1edbc	103	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
AnnaBridge	171:3a7713b1edbc	104	signal, valid for Flash memory access in burst mode.
AnnaBridge	171:3a7713b1edbc	105	This parameter can be a value of @ref FSMC_Wait_Signal */
AnnaBridge	171:3a7713b1edbc	106
AnnaBridge	171:3a7713b1edbc	107	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
AnnaBridge	171:3a7713b1edbc	108	This parameter can be a value of @ref FSMC_Extended_Mode */
AnnaBridge	171:3a7713b1edbc	109
AnnaBridge	171:3a7713b1edbc	110	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
AnnaBridge	171:3a7713b1edbc	111	valid only with asynchronous Flash memories.
AnnaBridge	171:3a7713b1edbc	112	This parameter can be a value of @ref FSMC_AsynchronousWait */
AnnaBridge	171:3a7713b1edbc	113
AnnaBridge	171:3a7713b1edbc	114	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
AnnaBridge	171:3a7713b1edbc	115	This parameter can be a value of @ref FSMC_Write_Burst */
AnnaBridge	171:3a7713b1edbc	116
AnnaBridge	171:3a7713b1edbc	117	}FSMC_NORSRAM_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	118
AnnaBridge	171:3a7713b1edbc	119	/**
AnnaBridge	171:3a7713b1edbc	120	* @brief FSMC NORSRAM Timing parameters structure definition
AnnaBridge	171:3a7713b1edbc	121	*/
AnnaBridge	171:3a7713b1edbc	122	typedef struct
AnnaBridge	171:3a7713b1edbc	123	{
AnnaBridge	171:3a7713b1edbc	124	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	125	the duration of the address setup time.
AnnaBridge	171:3a7713b1edbc	126	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	171:3a7713b1edbc	127	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	128
AnnaBridge	171:3a7713b1edbc	129	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	130	the duration of the address hold time.
AnnaBridge	171:3a7713b1edbc	131	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
AnnaBridge	171:3a7713b1edbc	132	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	133
AnnaBridge	171:3a7713b1edbc	134	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	135	the duration of the data setup time.
AnnaBridge	171:3a7713b1edbc	136	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
AnnaBridge	171:3a7713b1edbc	137	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
AnnaBridge	171:3a7713b1edbc	138	NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	139
AnnaBridge	171:3a7713b1edbc	140	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	141	the duration of the bus turnaround.
AnnaBridge	171:3a7713b1edbc	142	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	171:3a7713b1edbc	143	@note This parameter is only used for multiplexed NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	144
AnnaBridge	171:3a7713b1edbc	145	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
AnnaBridge	171:3a7713b1edbc	146	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
AnnaBridge	171:3a7713b1edbc	147	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
AnnaBridge	171:3a7713b1edbc	148	accesses. */
AnnaBridge	171:3a7713b1edbc	149
AnnaBridge	171:3a7713b1edbc	150	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
AnnaBridge	171:3a7713b1edbc	151	to the memory before getting the first data.
AnnaBridge	171:3a7713b1edbc	152	The parameter value depends on the memory type as shown below:
AnnaBridge	171:3a7713b1edbc	153	- It must be set to 0 in case of a CRAM
AnnaBridge	171:3a7713b1edbc	154	- It is don't care in asynchronous NOR, SRAM or ROM accesses
AnnaBridge	171:3a7713b1edbc	155	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
AnnaBridge	171:3a7713b1edbc	156	with synchronous burst mode enable */
AnnaBridge	171:3a7713b1edbc	157
AnnaBridge	171:3a7713b1edbc	158	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
AnnaBridge	171:3a7713b1edbc	159	This parameter can be a value of @ref FSMC_Access_Mode */
AnnaBridge	171:3a7713b1edbc	160
AnnaBridge	171:3a7713b1edbc	161	}FSMC_NORSRAM_TimingTypeDef;
AnnaBridge	171:3a7713b1edbc	162
AnnaBridge	171:3a7713b1edbc	163	#if (defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
AnnaBridge	171:3a7713b1edbc	164	/**
AnnaBridge	171:3a7713b1edbc	165	* @brief FSMC NAND Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	166	*/
AnnaBridge	171:3a7713b1edbc	167	typedef struct
AnnaBridge	171:3a7713b1edbc	168	{
AnnaBridge	171:3a7713b1edbc	169	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
AnnaBridge	171:3a7713b1edbc	170	This parameter can be a value of @ref FSMC_NAND_Bank */
AnnaBridge	171:3a7713b1edbc	171
AnnaBridge	171:3a7713b1edbc	172	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
AnnaBridge	171:3a7713b1edbc	173	This parameter can be any value of @ref FSMC_Wait_feature */
AnnaBridge	171:3a7713b1edbc	174
AnnaBridge	171:3a7713b1edbc	175	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	171:3a7713b1edbc	176	This parameter can be any value of @ref FSMC_NAND_Data_Width */
AnnaBridge	171:3a7713b1edbc	177
AnnaBridge	171:3a7713b1edbc	178	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
AnnaBridge	171:3a7713b1edbc	179	This parameter can be any value of @ref FSMC_ECC */
AnnaBridge	171:3a7713b1edbc	180
AnnaBridge	171:3a7713b1edbc	181	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
AnnaBridge	171:3a7713b1edbc	182	This parameter can be any value of @ref FSMC_ECC_Page_Size */
AnnaBridge	171:3a7713b1edbc	183
AnnaBridge	171:3a7713b1edbc	184	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	171:3a7713b1edbc	185	delay between CLE low and RE low.
AnnaBridge	171:3a7713b1edbc	186	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	187
AnnaBridge	171:3a7713b1edbc	188	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	171:3a7713b1edbc	189	delay between ALE low and RE low.
AnnaBridge	171:3a7713b1edbc	190	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	191
AnnaBridge	171:3a7713b1edbc	192	}FSMC_NAND_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	193
AnnaBridge	171:3a7713b1edbc	194	/**
AnnaBridge	171:3a7713b1edbc	195	* @brief FSMC NAND/PCCARD Timing parameters structure definition
AnnaBridge	171:3a7713b1edbc	196	*/
AnnaBridge	171:3a7713b1edbc	197	typedef struct
AnnaBridge	171:3a7713b1edbc	198	{
AnnaBridge	171:3a7713b1edbc	199	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
AnnaBridge	171:3a7713b1edbc	200	the command assertion for NAND-Flash read or write access
AnnaBridge	171:3a7713b1edbc	201	to common/Attribute or I/O memory space (depending on
AnnaBridge	171:3a7713b1edbc	202	the memory space timing to be configured).
AnnaBridge	171:3a7713b1edbc	203	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	204
AnnaBridge	171:3a7713b1edbc	205	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
AnnaBridge	171:3a7713b1edbc	206	command for NAND-Flash read or write access to
AnnaBridge	171:3a7713b1edbc	207	common/Attribute or I/O memory space (depending on the
AnnaBridge	171:3a7713b1edbc	208	memory space timing to be configured).
AnnaBridge	171:3a7713b1edbc	209	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	210
AnnaBridge	171:3a7713b1edbc	211	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
AnnaBridge	171:3a7713b1edbc	212	(and data for write access) after the command de-assertion
AnnaBridge	171:3a7713b1edbc	213	for NAND-Flash read or write access to common/Attribute
AnnaBridge	171:3a7713b1edbc	214	or I/O memory space (depending on the memory space timing
AnnaBridge	171:3a7713b1edbc	215	to be configured).
AnnaBridge	171:3a7713b1edbc	216	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	217
AnnaBridge	171:3a7713b1edbc	218	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
AnnaBridge	171:3a7713b1edbc	219	data bus is kept in HiZ after the start of a NAND-Flash
AnnaBridge	171:3a7713b1edbc	220	write access to common/Attribute or I/O memory space (depending
AnnaBridge	171:3a7713b1edbc	221	on the memory space timing to be configured).
AnnaBridge	171:3a7713b1edbc	222	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	223
AnnaBridge	171:3a7713b1edbc	224	}FSMC_NAND_PCC_TimingTypeDef;
AnnaBridge	171:3a7713b1edbc	225
AnnaBridge	171:3a7713b1edbc	226	/**
AnnaBridge	171:3a7713b1edbc	227	* @brief FSMC NAND Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	228	*/
AnnaBridge	171:3a7713b1edbc	229	typedef struct
AnnaBridge	171:3a7713b1edbc	230	{
AnnaBridge	171:3a7713b1edbc	231	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
AnnaBridge	171:3a7713b1edbc	232	This parameter can be any value of @ref FSMC_Wait_feature */
AnnaBridge	171:3a7713b1edbc	233
AnnaBridge	171:3a7713b1edbc	234	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	171:3a7713b1edbc	235	delay between CLE low and RE low.
AnnaBridge	171:3a7713b1edbc	236	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	237
AnnaBridge	171:3a7713b1edbc	238	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	171:3a7713b1edbc	239	delay between ALE low and RE low.
AnnaBridge	171:3a7713b1edbc	240	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	241
AnnaBridge	171:3a7713b1edbc	242	}FSMC_PCCARD_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	243	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	244	/**
AnnaBridge	171:3a7713b1edbc	245	* @}
AnnaBridge	171:3a7713b1edbc	246	*/
AnnaBridge	171:3a7713b1edbc	247
AnnaBridge	171:3a7713b1edbc	248	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	249
AnnaBridge	171:3a7713b1edbc	250	/** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants
AnnaBridge	171:3a7713b1edbc	251	* @{
AnnaBridge	171:3a7713b1edbc	252	*/
AnnaBridge	171:3a7713b1edbc	253
AnnaBridge	171:3a7713b1edbc	254	/** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
AnnaBridge	171:3a7713b1edbc	255	* @{
AnnaBridge	171:3a7713b1edbc	256	*/
AnnaBridge	171:3a7713b1edbc	257	/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
AnnaBridge	171:3a7713b1edbc	258	* @{
AnnaBridge	171:3a7713b1edbc	259	*/
AnnaBridge	171:3a7713b1edbc	260	#define FSMC_NORSRAM_BANK1 0x00000000U
AnnaBridge	171:3a7713b1edbc	261	#define FSMC_NORSRAM_BANK2 0x00000002U
AnnaBridge	171:3a7713b1edbc	262	#define FSMC_NORSRAM_BANK3 0x00000004U
AnnaBridge	171:3a7713b1edbc	263	#define FSMC_NORSRAM_BANK4 0x00000006U
AnnaBridge	171:3a7713b1edbc	264	/**
AnnaBridge	171:3a7713b1edbc	265	* @}
AnnaBridge	171:3a7713b1edbc	266	*/
AnnaBridge	171:3a7713b1edbc	267
AnnaBridge	171:3a7713b1edbc	268	/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
AnnaBridge	171:3a7713b1edbc	269	* @{
AnnaBridge	171:3a7713b1edbc	270	*/
AnnaBridge	171:3a7713b1edbc	271	#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	272	#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN)
AnnaBridge	171:3a7713b1edbc	273	/**
AnnaBridge	171:3a7713b1edbc	274	* @}
AnnaBridge	171:3a7713b1edbc	275	*/
AnnaBridge	171:3a7713b1edbc	276
AnnaBridge	171:3a7713b1edbc	277	/** @defgroup FSMC_Memory_Type FSMC Memory Type
AnnaBridge	171:3a7713b1edbc	278	* @{
AnnaBridge	171:3a7713b1edbc	279	*/
AnnaBridge	171:3a7713b1edbc	280	#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
AnnaBridge	171:3a7713b1edbc	281	#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0)
AnnaBridge	171:3a7713b1edbc	282	#define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1)
AnnaBridge	171:3a7713b1edbc	283	/**
AnnaBridge	171:3a7713b1edbc	284	* @}
AnnaBridge	171:3a7713b1edbc	285	*/
AnnaBridge	171:3a7713b1edbc	286
AnnaBridge	171:3a7713b1edbc	287	/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
AnnaBridge	171:3a7713b1edbc	288	* @{
AnnaBridge	171:3a7713b1edbc	289	*/
AnnaBridge	171:3a7713b1edbc	290	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	171:3a7713b1edbc	291	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0)
AnnaBridge	171:3a7713b1edbc	292	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1)
AnnaBridge	171:3a7713b1edbc	293	/**
AnnaBridge	171:3a7713b1edbc	294	* @}
AnnaBridge	171:3a7713b1edbc	295	*/
AnnaBridge	171:3a7713b1edbc	296
AnnaBridge	171:3a7713b1edbc	297	/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
AnnaBridge	171:3a7713b1edbc	298	* @{
AnnaBridge	171:3a7713b1edbc	299	*/
AnnaBridge	171:3a7713b1edbc	300	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN)
AnnaBridge	171:3a7713b1edbc	301	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	302	/**
AnnaBridge	171:3a7713b1edbc	303	* @}
AnnaBridge	171:3a7713b1edbc	304	*/
AnnaBridge	171:3a7713b1edbc	305
AnnaBridge	171:3a7713b1edbc	306	/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
AnnaBridge	171:3a7713b1edbc	307	* @{
AnnaBridge	171:3a7713b1edbc	308	*/
AnnaBridge	171:3a7713b1edbc	309	#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	310	#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN)
AnnaBridge	171:3a7713b1edbc	311	/**
AnnaBridge	171:3a7713b1edbc	312	* @}
AnnaBridge	171:3a7713b1edbc	313	*/
AnnaBridge	171:3a7713b1edbc	314
AnnaBridge	171:3a7713b1edbc	315	/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
AnnaBridge	171:3a7713b1edbc	316	* @{
AnnaBridge	171:3a7713b1edbc	317	*/
AnnaBridge	171:3a7713b1edbc	318	#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
AnnaBridge	171:3a7713b1edbc	319	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL)
AnnaBridge	171:3a7713b1edbc	320	/**
AnnaBridge	171:3a7713b1edbc	321	* @}
AnnaBridge	171:3a7713b1edbc	322	*/
AnnaBridge	171:3a7713b1edbc	323
AnnaBridge	171:3a7713b1edbc	324	/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
AnnaBridge	171:3a7713b1edbc	325	* @{
AnnaBridge	171:3a7713b1edbc	326	*/
AnnaBridge	171:3a7713b1edbc	327	#define FSMC_WRAP_MODE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	328	#define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD)
AnnaBridge	171:3a7713b1edbc	329	/**
AnnaBridge	171:3a7713b1edbc	330	* @}
AnnaBridge	171:3a7713b1edbc	331	*/
AnnaBridge	171:3a7713b1edbc	332
AnnaBridge	171:3a7713b1edbc	333	/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
AnnaBridge	171:3a7713b1edbc	334	* @{
AnnaBridge	171:3a7713b1edbc	335	*/
AnnaBridge	171:3a7713b1edbc	336	#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
AnnaBridge	171:3a7713b1edbc	337	#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG)
AnnaBridge	171:3a7713b1edbc	338	/**
AnnaBridge	171:3a7713b1edbc	339	* @}
AnnaBridge	171:3a7713b1edbc	340	*/
AnnaBridge	171:3a7713b1edbc	341
AnnaBridge	171:3a7713b1edbc	342	/** @defgroup FSMC_Write_Operation FSMC Write Operation
AnnaBridge	171:3a7713b1edbc	343	* @{
AnnaBridge	171:3a7713b1edbc	344	*/
AnnaBridge	171:3a7713b1edbc	345	#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	346	#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN)
AnnaBridge	171:3a7713b1edbc	347	/**
AnnaBridge	171:3a7713b1edbc	348	* @}
AnnaBridge	171:3a7713b1edbc	349	*/
AnnaBridge	171:3a7713b1edbc	350
AnnaBridge	171:3a7713b1edbc	351	/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
AnnaBridge	171:3a7713b1edbc	352	* @{
AnnaBridge	171:3a7713b1edbc	353	*/
AnnaBridge	171:3a7713b1edbc	354	#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	355	#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN)
AnnaBridge	171:3a7713b1edbc	356	/**
AnnaBridge	171:3a7713b1edbc	357	* @}
AnnaBridge	171:3a7713b1edbc	358	*/
AnnaBridge	171:3a7713b1edbc	359
AnnaBridge	171:3a7713b1edbc	360	/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
AnnaBridge	171:3a7713b1edbc	361	* @{
AnnaBridge	171:3a7713b1edbc	362	*/
AnnaBridge	171:3a7713b1edbc	363	#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	364	#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD)
AnnaBridge	171:3a7713b1edbc	365	/**
AnnaBridge	171:3a7713b1edbc	366	* @}
AnnaBridge	171:3a7713b1edbc	367	*/
AnnaBridge	171:3a7713b1edbc	368
AnnaBridge	171:3a7713b1edbc	369	/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
AnnaBridge	171:3a7713b1edbc	370	* @{
AnnaBridge	171:3a7713b1edbc	371	*/
AnnaBridge	171:3a7713b1edbc	372	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	373	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT)
AnnaBridge	171:3a7713b1edbc	374	/**
AnnaBridge	171:3a7713b1edbc	375	* @}
AnnaBridge	171:3a7713b1edbc	376	*/
AnnaBridge	171:3a7713b1edbc	377
AnnaBridge	171:3a7713b1edbc	378	/** @defgroup FSMC_Write_Burst FSMC Write Burst
AnnaBridge	171:3a7713b1edbc	379	* @{
AnnaBridge	171:3a7713b1edbc	380	*/
AnnaBridge	171:3a7713b1edbc	381	#define FSMC_WRITE_BURST_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	382	#define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW)
AnnaBridge	171:3a7713b1edbc	383	/**
AnnaBridge	171:3a7713b1edbc	384	* @}
AnnaBridge	171:3a7713b1edbc	385	*/
AnnaBridge	171:3a7713b1edbc	386
AnnaBridge	171:3a7713b1edbc	387	/** @defgroup FSMC_Access_Mode FSMC Access Mode
AnnaBridge	171:3a7713b1edbc	388	* @{
AnnaBridge	171:3a7713b1edbc	389	*/
AnnaBridge	171:3a7713b1edbc	390	#define FSMC_ACCESS_MODE_A 0x00000000U
AnnaBridge	171:3a7713b1edbc	391	#define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0)
AnnaBridge	171:3a7713b1edbc	392	#define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1)
AnnaBridge	171:3a7713b1edbc	393	#define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 \| FSMC_BTRx_ACCMOD_1))
AnnaBridge	171:3a7713b1edbc	394	/**
AnnaBridge	171:3a7713b1edbc	395	* @}
AnnaBridge	171:3a7713b1edbc	396	*/
AnnaBridge	171:3a7713b1edbc	397
AnnaBridge	171:3a7713b1edbc	398	/**
AnnaBridge	171:3a7713b1edbc	399	* @}
AnnaBridge	171:3a7713b1edbc	400	*/
AnnaBridge	171:3a7713b1edbc	401
AnnaBridge	171:3a7713b1edbc	402	#if (defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
AnnaBridge	171:3a7713b1edbc	403	/** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller
AnnaBridge	171:3a7713b1edbc	404	* @{
AnnaBridge	171:3a7713b1edbc	405	*/
AnnaBridge	171:3a7713b1edbc	406	/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
AnnaBridge	171:3a7713b1edbc	407	* @{
AnnaBridge	171:3a7713b1edbc	408	*/
AnnaBridge	171:3a7713b1edbc	409	#define FSMC_NAND_BANK2 0x00000010U
AnnaBridge	171:3a7713b1edbc	410	#define FSMC_NAND_BANK3 0x00000100U
AnnaBridge	171:3a7713b1edbc	411	/**
AnnaBridge	171:3a7713b1edbc	412	* @}
AnnaBridge	171:3a7713b1edbc	413	*/
AnnaBridge	171:3a7713b1edbc	414
AnnaBridge	171:3a7713b1edbc	415	/** @defgroup FSMC_Wait_feature FSMC Wait feature
AnnaBridge	171:3a7713b1edbc	416	* @{
AnnaBridge	171:3a7713b1edbc	417	*/
AnnaBridge	171:3a7713b1edbc	418	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	419	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FSMC_PCRx_PWAITEN)
AnnaBridge	171:3a7713b1edbc	420	/**
AnnaBridge	171:3a7713b1edbc	421	* @}
AnnaBridge	171:3a7713b1edbc	422	*/
AnnaBridge	171:3a7713b1edbc	423
AnnaBridge	171:3a7713b1edbc	424	/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
AnnaBridge	171:3a7713b1edbc	425	* @{
AnnaBridge	171:3a7713b1edbc	426	*/
AnnaBridge	171:3a7713b1edbc	427	#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
AnnaBridge	171:3a7713b1edbc	428	#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FSMC_PCRx_PTYP)
AnnaBridge	171:3a7713b1edbc	429	/**
AnnaBridge	171:3a7713b1edbc	430	* @}
AnnaBridge	171:3a7713b1edbc	431	*/
AnnaBridge	171:3a7713b1edbc	432
AnnaBridge	171:3a7713b1edbc	433	/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
AnnaBridge	171:3a7713b1edbc	434	* @{
AnnaBridge	171:3a7713b1edbc	435	*/
AnnaBridge	171:3a7713b1edbc	436	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	171:3a7713b1edbc	437	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_PCRx_PWID_0)
AnnaBridge	171:3a7713b1edbc	438	/**
AnnaBridge	171:3a7713b1edbc	439	* @}
AnnaBridge	171:3a7713b1edbc	440	*/
AnnaBridge	171:3a7713b1edbc	441
AnnaBridge	171:3a7713b1edbc	442	/** @defgroup FSMC_ECC FSMC NAND ECC
AnnaBridge	171:3a7713b1edbc	443	* @{
AnnaBridge	171:3a7713b1edbc	444	*/
AnnaBridge	171:3a7713b1edbc	445	#define FSMC_NAND_ECC_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	446	#define FSMC_NAND_ECC_ENABLE ((uint32_t)FSMC_PCRx_ECCEN)
AnnaBridge	171:3a7713b1edbc	447	/**
AnnaBridge	171:3a7713b1edbc	448	* @}
AnnaBridge	171:3a7713b1edbc	449	*/
AnnaBridge	171:3a7713b1edbc	450
AnnaBridge	171:3a7713b1edbc	451	/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
AnnaBridge	171:3a7713b1edbc	452	* @{
AnnaBridge	171:3a7713b1edbc	453	*/
AnnaBridge	171:3a7713b1edbc	454	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
AnnaBridge	171:3a7713b1edbc	455	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FSMC_PCRx_ECCPS_0)
AnnaBridge	171:3a7713b1edbc	456	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FSMC_PCRx_ECCPS_1)
AnnaBridge	171:3a7713b1edbc	457	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FSMC_PCRx_ECCPS_0\|FSMC_PCRx_ECCPS_1)
AnnaBridge	171:3a7713b1edbc	458	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FSMC_PCRx_ECCPS_2)
AnnaBridge	171:3a7713b1edbc	459	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FSMC_PCRx_ECCPS_0\|FSMC_PCRx_ECCPS_2)
AnnaBridge	171:3a7713b1edbc	460	/**
AnnaBridge	171:3a7713b1edbc	461	* @}
AnnaBridge	171:3a7713b1edbc	462	*/
AnnaBridge	171:3a7713b1edbc	463
AnnaBridge	171:3a7713b1edbc	464	/**
AnnaBridge	171:3a7713b1edbc	465	* @}
AnnaBridge	171:3a7713b1edbc	466	*/
AnnaBridge	171:3a7713b1edbc	467	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	468
AnnaBridge	171:3a7713b1edbc	469	/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
AnnaBridge	171:3a7713b1edbc	470	* @brief FSMC Interrupt definition
AnnaBridge	171:3a7713b1edbc	471	* @{
AnnaBridge	171:3a7713b1edbc	472	*/
AnnaBridge	171:3a7713b1edbc	473	#define FSMC_IT_RISING_EDGE ((uint32_t)FSMC_SRx_IREN)
AnnaBridge	171:3a7713b1edbc	474	#define FSMC_IT_LEVEL ((uint32_t)FSMC_SRx_ILEN)
AnnaBridge	171:3a7713b1edbc	475	#define FSMC_IT_FALLING_EDGE ((uint32_t)FSMC_SRx_IFEN)
AnnaBridge	171:3a7713b1edbc	476	/**
AnnaBridge	171:3a7713b1edbc	477	* @}
AnnaBridge	171:3a7713b1edbc	478	*/
AnnaBridge	171:3a7713b1edbc	479
AnnaBridge	171:3a7713b1edbc	480	/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
AnnaBridge	171:3a7713b1edbc	481	* @brief FSMC Flag definition
AnnaBridge	171:3a7713b1edbc	482	* @{
AnnaBridge	171:3a7713b1edbc	483	*/
AnnaBridge	171:3a7713b1edbc	484	#define FSMC_FLAG_RISING_EDGE ((uint32_t)FSMC_SRx_IRS)
AnnaBridge	171:3a7713b1edbc	485	#define FSMC_FLAG_LEVEL ((uint32_t)FSMC_SRx_ILS)
AnnaBridge	171:3a7713b1edbc	486	#define FSMC_FLAG_FALLING_EDGE ((uint32_t)FSMC_SRx_IFS)
AnnaBridge	171:3a7713b1edbc	487	#define FSMC_FLAG_FEMPT ((uint32_t)FSMC_SRx_FEMPT)
AnnaBridge	171:3a7713b1edbc	488	/**
AnnaBridge	171:3a7713b1edbc	489	* @}
AnnaBridge	171:3a7713b1edbc	490	*/
AnnaBridge	171:3a7713b1edbc	491
AnnaBridge	171:3a7713b1edbc	492	/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
AnnaBridge	171:3a7713b1edbc	493	* @{
AnnaBridge	171:3a7713b1edbc	494	*/
AnnaBridge	171:3a7713b1edbc	495	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
AnnaBridge	171:3a7713b1edbc	496	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
AnnaBridge	171:3a7713b1edbc	497	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
AnnaBridge	171:3a7713b1edbc	498	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
AnnaBridge	171:3a7713b1edbc	499
AnnaBridge	171:3a7713b1edbc	500	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
AnnaBridge	171:3a7713b1edbc	501	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
AnnaBridge	171:3a7713b1edbc	502	#define FSMC_NAND_DEVICE FSMC_Bank2_3
AnnaBridge	171:3a7713b1edbc	503	#define FSMC_PCCARD_DEVICE FSMC_Bank4
AnnaBridge	171:3a7713b1edbc	504	/**
AnnaBridge	171:3a7713b1edbc	505	* @}
AnnaBridge	171:3a7713b1edbc	506	*/
AnnaBridge	171:3a7713b1edbc	507
AnnaBridge	171:3a7713b1edbc	508	/**
AnnaBridge	171:3a7713b1edbc	509	* @}
AnnaBridge	171:3a7713b1edbc	510	*/
AnnaBridge	171:3a7713b1edbc	511
AnnaBridge	171:3a7713b1edbc	512	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	513	/** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
AnnaBridge	171:3a7713b1edbc	514	* @{
AnnaBridge	171:3a7713b1edbc	515	*/
AnnaBridge	171:3a7713b1edbc	516
AnnaBridge	171:3a7713b1edbc	517	/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
AnnaBridge	171:3a7713b1edbc	518	* @brief macros to handle NOR device enable/disable and read/write operations
AnnaBridge	171:3a7713b1edbc	519	* @{
AnnaBridge	171:3a7713b1edbc	520	*/
AnnaBridge	171:3a7713b1edbc	521
AnnaBridge	171:3a7713b1edbc	522	/**
AnnaBridge	171:3a7713b1edbc	523	* @brief Enable the NORSRAM device access.
AnnaBridge	171:3a7713b1edbc	524	* @param __INSTANCE__: FSMC_NORSRAM Instance
AnnaBridge	171:3a7713b1edbc	525	* @param __BANK__: FSMC_NORSRAM Bank
AnnaBridge	171:3a7713b1edbc	526	* @retval none
AnnaBridge	171:3a7713b1edbc	527	*/
AnnaBridge	171:3a7713b1edbc	528	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
AnnaBridge	171:3a7713b1edbc	529
AnnaBridge	171:3a7713b1edbc	530	/**
AnnaBridge	171:3a7713b1edbc	531	* @brief Disable the NORSRAM device access.
AnnaBridge	171:3a7713b1edbc	532	* @param __INSTANCE__: FSMC_NORSRAM Instance
AnnaBridge	171:3a7713b1edbc	533	* @param __BANK__: FSMC_NORSRAM Bank
AnnaBridge	171:3a7713b1edbc	534	* @retval none
AnnaBridge	171:3a7713b1edbc	535	*/
AnnaBridge	171:3a7713b1edbc	536	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
AnnaBridge	171:3a7713b1edbc	537
AnnaBridge	171:3a7713b1edbc	538	/**
AnnaBridge	171:3a7713b1edbc	539	* @}
AnnaBridge	171:3a7713b1edbc	540	*/
AnnaBridge	171:3a7713b1edbc	541
AnnaBridge	171:3a7713b1edbc	542	#if (defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
AnnaBridge	171:3a7713b1edbc	543	/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
AnnaBridge	171:3a7713b1edbc	544	* @brief macros to handle NAND device enable/disable
AnnaBridge	171:3a7713b1edbc	545	* @{
AnnaBridge	171:3a7713b1edbc	546	*/
AnnaBridge	171:3a7713b1edbc	547
AnnaBridge	171:3a7713b1edbc	548	/**
AnnaBridge	171:3a7713b1edbc	549	* @brief Enable the NAND device access.
AnnaBridge	171:3a7713b1edbc	550	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	551	* @param __BANK__: FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	552	* @retval None
AnnaBridge	171:3a7713b1edbc	553	*/
AnnaBridge	171:3a7713b1edbc	554	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
AnnaBridge	171:3a7713b1edbc	555	SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
AnnaBridge	171:3a7713b1edbc	556
AnnaBridge	171:3a7713b1edbc	557	/**
AnnaBridge	171:3a7713b1edbc	558	* @brief Disable the NAND device access.
AnnaBridge	171:3a7713b1edbc	559	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	560	* @param __BANK__: FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	561	* @retval None
AnnaBridge	171:3a7713b1edbc	562	*/
AnnaBridge	171:3a7713b1edbc	563	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
AnnaBridge	171:3a7713b1edbc	564	CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
AnnaBridge	171:3a7713b1edbc	565	/**
AnnaBridge	171:3a7713b1edbc	566	* @}
AnnaBridge	171:3a7713b1edbc	567	*/
AnnaBridge	171:3a7713b1edbc	568
AnnaBridge	171:3a7713b1edbc	569	/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
AnnaBridge	171:3a7713b1edbc	570	* @brief macros to handle PCCARD read/write operations
AnnaBridge	171:3a7713b1edbc	571	* @{
AnnaBridge	171:3a7713b1edbc	572	*/
AnnaBridge	171:3a7713b1edbc	573	/**
AnnaBridge	171:3a7713b1edbc	574	* @brief Enable the PCCARD device access.
AnnaBridge	171:3a7713b1edbc	575	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	576	* @retval None
AnnaBridge	171:3a7713b1edbc	577	*/
AnnaBridge	171:3a7713b1edbc	578	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
AnnaBridge	171:3a7713b1edbc	579
AnnaBridge	171:3a7713b1edbc	580	/**
AnnaBridge	171:3a7713b1edbc	581	* @brief Disable the PCCARD device access.
AnnaBridge	171:3a7713b1edbc	582	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	583	* @retval None
AnnaBridge	171:3a7713b1edbc	584	*/
AnnaBridge	171:3a7713b1edbc	585	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
AnnaBridge	171:3a7713b1edbc	586	/**
AnnaBridge	171:3a7713b1edbc	587	* @}
AnnaBridge	171:3a7713b1edbc	588	*/
AnnaBridge	171:3a7713b1edbc	589
AnnaBridge	171:3a7713b1edbc	590	/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
AnnaBridge	171:3a7713b1edbc	591	* @brief macros to handle FSMC flags and interrupts
AnnaBridge	171:3a7713b1edbc	592	* @{
AnnaBridge	171:3a7713b1edbc	593	*/
AnnaBridge	171:3a7713b1edbc	594
AnnaBridge	171:3a7713b1edbc	595	/**
AnnaBridge	171:3a7713b1edbc	596	* @brief Enable the NAND device interrupt.
AnnaBridge	171:3a7713b1edbc	597	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	598	* @param __BANK__: FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	599	* @param __INTERRUPT__: FSMC_NAND interrupt
AnnaBridge	171:3a7713b1edbc	600	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	601	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	171:3a7713b1edbc	602	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	171:3a7713b1edbc	603	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	171:3a7713b1edbc	604	* @retval None
AnnaBridge	171:3a7713b1edbc	605	*/
AnnaBridge	171:3a7713b1edbc	606	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
AnnaBridge	171:3a7713b1edbc	607	SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
AnnaBridge	171:3a7713b1edbc	608
AnnaBridge	171:3a7713b1edbc	609	/**
AnnaBridge	171:3a7713b1edbc	610	* @brief Disable the NAND device interrupt.
AnnaBridge	171:3a7713b1edbc	611	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	612	* @param __BANK__: FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	613	* @param __INTERRUPT__: FSMC_NAND interrupt
AnnaBridge	171:3a7713b1edbc	614	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	615	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	171:3a7713b1edbc	616	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	171:3a7713b1edbc	617	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	171:3a7713b1edbc	618	* @retval None
AnnaBridge	171:3a7713b1edbc	619	*/
AnnaBridge	171:3a7713b1edbc	620	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
AnnaBridge	171:3a7713b1edbc	621	CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
AnnaBridge	171:3a7713b1edbc	622
AnnaBridge	171:3a7713b1edbc	623	/**
AnnaBridge	171:3a7713b1edbc	624	* @brief Get flag status of the NAND device.
AnnaBridge	171:3a7713b1edbc	625	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	626	* @param __BANK__ : FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	627	* @param __FLAG__ : FSMC_NAND flag
AnnaBridge	171:3a7713b1edbc	628	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	629	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	171:3a7713b1edbc	630	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	171:3a7713b1edbc	631	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	171:3a7713b1edbc	632	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	171:3a7713b1edbc	633	* @retval The state of FLAG (SET or RESET).
AnnaBridge	171:3a7713b1edbc	634	*/
AnnaBridge	171:3a7713b1edbc	635	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
AnnaBridge	171:3a7713b1edbc	636	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
AnnaBridge	171:3a7713b1edbc	637	/**
AnnaBridge	171:3a7713b1edbc	638	* @brief Clear flag status of the NAND device.
AnnaBridge	171:3a7713b1edbc	639	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	640	* @param __BANK__: FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	641	* @param __FLAG__: FSMC_NAND flag
AnnaBridge	171:3a7713b1edbc	642	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	643	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	171:3a7713b1edbc	644	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	171:3a7713b1edbc	645	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	171:3a7713b1edbc	646	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	171:3a7713b1edbc	647	* @retval None
AnnaBridge	171:3a7713b1edbc	648	*/
AnnaBridge	171:3a7713b1edbc	649	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
AnnaBridge	171:3a7713b1edbc	650	CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	/**
AnnaBridge	171:3a7713b1edbc	653	* @brief Enable the PCCARD device interrupt.
AnnaBridge	171:3a7713b1edbc	654	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	655	* @param __INTERRUPT__: FSMC_PCCARD interrupt
AnnaBridge	171:3a7713b1edbc	656	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	657	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	171:3a7713b1edbc	658	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	171:3a7713b1edbc	659	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	171:3a7713b1edbc	660	* @retval None
AnnaBridge	171:3a7713b1edbc	661	*/
AnnaBridge	171:3a7713b1edbc	662	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	663
AnnaBridge	171:3a7713b1edbc	664	/**
AnnaBridge	171:3a7713b1edbc	665	* @brief Disable the PCCARD device interrupt.
AnnaBridge	171:3a7713b1edbc	666	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	667	* @param __INTERRUPT__: FSMC_PCCARD interrupt
AnnaBridge	171:3a7713b1edbc	668	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	669	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	171:3a7713b1edbc	670	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	171:3a7713b1edbc	671	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	171:3a7713b1edbc	672	* @retval None
AnnaBridge	171:3a7713b1edbc	673	*/
AnnaBridge	171:3a7713b1edbc	674	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	675
AnnaBridge	171:3a7713b1edbc	676	/**
AnnaBridge	171:3a7713b1edbc	677	* @brief Get flag status of the PCCARD device.
AnnaBridge	171:3a7713b1edbc	678	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	679	* @param __FLAG__: FSMC_PCCARD flag
AnnaBridge	171:3a7713b1edbc	680	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	681	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	171:3a7713b1edbc	682	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	171:3a7713b1edbc	683	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	171:3a7713b1edbc	684	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	171:3a7713b1edbc	685	* @retval The state of FLAG (SET or RESET).
AnnaBridge	171:3a7713b1edbc	686	*/
AnnaBridge	171:3a7713b1edbc	687	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
AnnaBridge	171:3a7713b1edbc	688
AnnaBridge	171:3a7713b1edbc	689	/**
AnnaBridge	171:3a7713b1edbc	690	* @brief Clear flag status of the PCCARD device.
AnnaBridge	171:3a7713b1edbc	691	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	692	* @param __FLAG__: FSMC_PCCARD flag
AnnaBridge	171:3a7713b1edbc	693	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	694	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	171:3a7713b1edbc	695	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	171:3a7713b1edbc	696	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	171:3a7713b1edbc	697	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	171:3a7713b1edbc	698	* @retval None
AnnaBridge	171:3a7713b1edbc	699	*/
AnnaBridge	171:3a7713b1edbc	700	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
AnnaBridge	171:3a7713b1edbc	701
AnnaBridge	171:3a7713b1edbc	702	/**
AnnaBridge	171:3a7713b1edbc	703	* @}
AnnaBridge	171:3a7713b1edbc	704	*/
AnnaBridge	171:3a7713b1edbc	705	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	706
AnnaBridge	171:3a7713b1edbc	707	/**
AnnaBridge	171:3a7713b1edbc	708	* @}
AnnaBridge	171:3a7713b1edbc	709	*/
AnnaBridge	171:3a7713b1edbc	710
AnnaBridge	171:3a7713b1edbc	711	/** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros
AnnaBridge	171:3a7713b1edbc	712	* @{
AnnaBridge	171:3a7713b1edbc	713	*/
AnnaBridge	171:3a7713b1edbc	714	#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) \|\| \
AnnaBridge	171:3a7713b1edbc	715	((__BANK__) == FSMC_NORSRAM_BANK2) \|\| \
AnnaBridge	171:3a7713b1edbc	716	((__BANK__) == FSMC_NORSRAM_BANK3) \|\| \
AnnaBridge	171:3a7713b1edbc	717	((__BANK__) == FSMC_NORSRAM_BANK4))
AnnaBridge	171:3a7713b1edbc	718
AnnaBridge	171:3a7713b1edbc	719	#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	720	((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
AnnaBridge	171:3a7713b1edbc	721
AnnaBridge	171:3a7713b1edbc	722	#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) \|\| \
AnnaBridge	171:3a7713b1edbc	723	((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
AnnaBridge	171:3a7713b1edbc	724	((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
AnnaBridge	171:3a7713b1edbc	725
AnnaBridge	171:3a7713b1edbc	726	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	171:3a7713b1edbc	727	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	171:3a7713b1edbc	728	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
AnnaBridge	171:3a7713b1edbc	729
AnnaBridge	171:3a7713b1edbc	730	#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	731	((__BURST__) == FSMC_WRITE_BURST_ENABLE))
AnnaBridge	171:3a7713b1edbc	732
AnnaBridge	171:3a7713b1edbc	733	#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) \|\| \
AnnaBridge	171:3a7713b1edbc	734	((__MODE__) == FSMC_ACCESS_MODE_B) \|\| \
AnnaBridge	171:3a7713b1edbc	735	((__MODE__) == FSMC_ACCESS_MODE_C) \|\| \
AnnaBridge	171:3a7713b1edbc	736	((__MODE__) == FSMC_ACCESS_MODE_D))
AnnaBridge	171:3a7713b1edbc	737
AnnaBridge	171:3a7713b1edbc	738	#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) \|\| \
AnnaBridge	171:3a7713b1edbc	739	((__BANK__) == FSMC_NAND_BANK3))
AnnaBridge	171:3a7713b1edbc	740
AnnaBridge	171:3a7713b1edbc	741	#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	742	((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
AnnaBridge	171:3a7713b1edbc	743
AnnaBridge	171:3a7713b1edbc	744	#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	171:3a7713b1edbc	745	((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
AnnaBridge	171:3a7713b1edbc	746
AnnaBridge	171:3a7713b1edbc	747	#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	748	((__STATE__) == FSMC_NAND_ECC_ENABLE))
AnnaBridge	171:3a7713b1edbc	749
AnnaBridge	171:3a7713b1edbc	750	#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	751	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	752	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	753	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	754	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	755	((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
AnnaBridge	171:3a7713b1edbc	756
AnnaBridge	171:3a7713b1edbc	757	/** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
AnnaBridge	171:3a7713b1edbc	758	* @{
AnnaBridge	171:3a7713b1edbc	759	*/
AnnaBridge	171:3a7713b1edbc	760	#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
AnnaBridge	171:3a7713b1edbc	761	/**
AnnaBridge	171:3a7713b1edbc	762	* @}
AnnaBridge	171:3a7713b1edbc	763	*/
AnnaBridge	171:3a7713b1edbc	764
AnnaBridge	171:3a7713b1edbc	765	/** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
AnnaBridge	171:3a7713b1edbc	766	* @{
AnnaBridge	171:3a7713b1edbc	767	*/
AnnaBridge	171:3a7713b1edbc	768	#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
AnnaBridge	171:3a7713b1edbc	769	/**
AnnaBridge	171:3a7713b1edbc	770	* @}
AnnaBridge	171:3a7713b1edbc	771	*/
AnnaBridge	171:3a7713b1edbc	772
AnnaBridge	171:3a7713b1edbc	773	/** @defgroup FSMC_Setup_Time FSMC_Setup_Time
AnnaBridge	171:3a7713b1edbc	774	* @{
AnnaBridge	171:3a7713b1edbc	775	*/
AnnaBridge	171:3a7713b1edbc	776	#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255U)
AnnaBridge	171:3a7713b1edbc	777	/**
AnnaBridge	171:3a7713b1edbc	778	* @}
AnnaBridge	171:3a7713b1edbc	779	*/
AnnaBridge	171:3a7713b1edbc	780
AnnaBridge	171:3a7713b1edbc	781	/** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
AnnaBridge	171:3a7713b1edbc	782	* @{
AnnaBridge	171:3a7713b1edbc	783	*/
AnnaBridge	171:3a7713b1edbc	784	#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255U)
AnnaBridge	171:3a7713b1edbc	785	/**
AnnaBridge	171:3a7713b1edbc	786	* @}
AnnaBridge	171:3a7713b1edbc	787	*/
AnnaBridge	171:3a7713b1edbc	788
AnnaBridge	171:3a7713b1edbc	789	/** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
AnnaBridge	171:3a7713b1edbc	790	* @{
AnnaBridge	171:3a7713b1edbc	791	*/
AnnaBridge	171:3a7713b1edbc	792	#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255U)
AnnaBridge	171:3a7713b1edbc	793	/**
AnnaBridge	171:3a7713b1edbc	794	* @}
AnnaBridge	171:3a7713b1edbc	795	*/
AnnaBridge	171:3a7713b1edbc	796
AnnaBridge	171:3a7713b1edbc	797	/** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time
AnnaBridge	171:3a7713b1edbc	798	* @{
AnnaBridge	171:3a7713b1edbc	799	*/
AnnaBridge	171:3a7713b1edbc	800	#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255U)
AnnaBridge	171:3a7713b1edbc	801	/**
AnnaBridge	171:3a7713b1edbc	802	* @}
AnnaBridge	171:3a7713b1edbc	803	*/
AnnaBridge	171:3a7713b1edbc	804
AnnaBridge	171:3a7713b1edbc	805	/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
AnnaBridge	171:3a7713b1edbc	806	* @{
AnnaBridge	171:3a7713b1edbc	807	*/
AnnaBridge	171:3a7713b1edbc	808	#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
AnnaBridge	171:3a7713b1edbc	809	/**
AnnaBridge	171:3a7713b1edbc	810	* @}
AnnaBridge	171:3a7713b1edbc	811	*/
AnnaBridge	171:3a7713b1edbc	812
AnnaBridge	171:3a7713b1edbc	813	/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
AnnaBridge	171:3a7713b1edbc	814	* @{
AnnaBridge	171:3a7713b1edbc	815	*/
AnnaBridge	171:3a7713b1edbc	816	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
AnnaBridge	171:3a7713b1edbc	817	/**
AnnaBridge	171:3a7713b1edbc	818	* @}
AnnaBridge	171:3a7713b1edbc	819	*/
AnnaBridge	171:3a7713b1edbc	820
AnnaBridge	171:3a7713b1edbc	821	/** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance
AnnaBridge	171:3a7713b1edbc	822	* @{
AnnaBridge	171:3a7713b1edbc	823	*/
AnnaBridge	171:3a7713b1edbc	824	#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
AnnaBridge	171:3a7713b1edbc	825	/**
AnnaBridge	171:3a7713b1edbc	826	* @}
AnnaBridge	171:3a7713b1edbc	827	*/
AnnaBridge	171:3a7713b1edbc	828
AnnaBridge	171:3a7713b1edbc	829	/** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance
AnnaBridge	171:3a7713b1edbc	830	* @{
AnnaBridge	171:3a7713b1edbc	831	*/
AnnaBridge	171:3a7713b1edbc	832	#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
AnnaBridge	171:3a7713b1edbc	833
AnnaBridge	171:3a7713b1edbc	834	/**
AnnaBridge	171:3a7713b1edbc	835	* @}
AnnaBridge	171:3a7713b1edbc	836	*/
AnnaBridge	171:3a7713b1edbc	837	#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	838	((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
AnnaBridge	171:3a7713b1edbc	839
AnnaBridge	171:3a7713b1edbc	840	#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
AnnaBridge	171:3a7713b1edbc	841	((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
AnnaBridge	171:3a7713b1edbc	842
AnnaBridge	171:3a7713b1edbc	843	#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	844	((__MODE__) == FSMC_WRAP_MODE_ENABLE))
AnnaBridge	171:3a7713b1edbc	845
AnnaBridge	171:3a7713b1edbc	846	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
AnnaBridge	171:3a7713b1edbc	847	((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
AnnaBridge	171:3a7713b1edbc	848
AnnaBridge	171:3a7713b1edbc	849	#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	850	((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
AnnaBridge	171:3a7713b1edbc	851
AnnaBridge	171:3a7713b1edbc	852	#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	853	((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
AnnaBridge	171:3a7713b1edbc	854
AnnaBridge	171:3a7713b1edbc	855	#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	856	((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
AnnaBridge	171:3a7713b1edbc	857
AnnaBridge	171:3a7713b1edbc	858	#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	859	((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
AnnaBridge	171:3a7713b1edbc	860
AnnaBridge	171:3a7713b1edbc	861	#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
AnnaBridge	171:3a7713b1edbc	862
AnnaBridge	171:3a7713b1edbc	863	/** @defgroup FSMC_Data_Latency FSMC Data Latency
AnnaBridge	171:3a7713b1edbc	864	* @{
AnnaBridge	171:3a7713b1edbc	865	*/
AnnaBridge	171:3a7713b1edbc	866	#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
AnnaBridge	171:3a7713b1edbc	867	/**
AnnaBridge	171:3a7713b1edbc	868	* @}
AnnaBridge	171:3a7713b1edbc	869	*/
AnnaBridge	171:3a7713b1edbc	870
AnnaBridge	171:3a7713b1edbc	871	/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
AnnaBridge	171:3a7713b1edbc	872	* @{
AnnaBridge	171:3a7713b1edbc	873	*/
AnnaBridge	171:3a7713b1edbc	874	#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	171:3a7713b1edbc	875	/**
AnnaBridge	171:3a7713b1edbc	876	* @}
AnnaBridge	171:3a7713b1edbc	877	*/
AnnaBridge	171:3a7713b1edbc	878
AnnaBridge	171:3a7713b1edbc	879	/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
AnnaBridge	171:3a7713b1edbc	880	* @{
AnnaBridge	171:3a7713b1edbc	881	*/
AnnaBridge	171:3a7713b1edbc	882	#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
AnnaBridge	171:3a7713b1edbc	883	/**
AnnaBridge	171:3a7713b1edbc	884	* @}
AnnaBridge	171:3a7713b1edbc	885	*/
AnnaBridge	171:3a7713b1edbc	886
AnnaBridge	171:3a7713b1edbc	887	/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
AnnaBridge	171:3a7713b1edbc	888	* @{
AnnaBridge	171:3a7713b1edbc	889	*/
AnnaBridge	171:3a7713b1edbc	890	#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
AnnaBridge	171:3a7713b1edbc	891	/**
AnnaBridge	171:3a7713b1edbc	892	* @}
AnnaBridge	171:3a7713b1edbc	893	*/
AnnaBridge	171:3a7713b1edbc	894
AnnaBridge	171:3a7713b1edbc	895	/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
AnnaBridge	171:3a7713b1edbc	896	* @{
AnnaBridge	171:3a7713b1edbc	897	*/
AnnaBridge	171:3a7713b1edbc	898	#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	171:3a7713b1edbc	899	/**
AnnaBridge	171:3a7713b1edbc	900	* @}
AnnaBridge	171:3a7713b1edbc	901	*/
AnnaBridge	171:3a7713b1edbc	902
AnnaBridge	171:3a7713b1edbc	903	/**
AnnaBridge	171:3a7713b1edbc	904	* @}
AnnaBridge	171:3a7713b1edbc	905	*/
AnnaBridge	171:3a7713b1edbc	906
AnnaBridge	171:3a7713b1edbc	907	/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
AnnaBridge	171:3a7713b1edbc	908	* @{
AnnaBridge	171:3a7713b1edbc	909	*/
AnnaBridge	171:3a7713b1edbc	910
AnnaBridge	171:3a7713b1edbc	911	/* ----------------------- FSMC registers bit mask --------------------------- */
AnnaBridge	171:3a7713b1edbc	912	#if (defined (STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
AnnaBridge	171:3a7713b1edbc	913	/* --- PCR Register ---*/
AnnaBridge	171:3a7713b1edbc	914	/* PCR register clear mask */
AnnaBridge	171:3a7713b1edbc	915	#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN \| FSMC_PCRx_PBKEN \| \
AnnaBridge	171:3a7713b1edbc	916	FSMC_PCRx_PTYP \| FSMC_PCRx_PWID \| \
AnnaBridge	171:3a7713b1edbc	917	FSMC_PCRx_ECCEN \| FSMC_PCRx_TCLR \| \
AnnaBridge	171:3a7713b1edbc	918	FSMC_PCRx_TAR \| FSMC_PCRx_ECCPS))
AnnaBridge	171:3a7713b1edbc	919
AnnaBridge	171:3a7713b1edbc	920	/* --- PMEM Register ---*/
AnnaBridge	171:3a7713b1edbc	921	/* PMEM register clear mask */
AnnaBridge	171:3a7713b1edbc	922	#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx \| FSMC_PMEMx_MEMWAITx \|\
AnnaBridge	171:3a7713b1edbc	923	FSMC_PMEMx_MEMHOLDx \| FSMC_PMEMx_MEMHIZx))
AnnaBridge	171:3a7713b1edbc	924
AnnaBridge	171:3a7713b1edbc	925	/* --- PATT Register ---*/
AnnaBridge	171:3a7713b1edbc	926	/* PATT register clear mask */
AnnaBridge	171:3a7713b1edbc	927	#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx \| FSMC_PATTx_ATTWAITx \|\
AnnaBridge	171:3a7713b1edbc	928	FSMC_PATTx_ATTHOLDx \| FSMC_PATTx_ATTHIZx))
AnnaBridge	171:3a7713b1edbc	929
AnnaBridge	171:3a7713b1edbc	930	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	931	/* --- BCR Register ---*/
AnnaBridge	171:3a7713b1edbc	932	/* BCR register clear mask */
AnnaBridge	171:3a7713b1edbc	933	#define BCR_CLEAR_MASK ((uint32_t)(FSMC_BCRx_FACCEN \| FSMC_BCRx_MUXEN \| \
AnnaBridge	171:3a7713b1edbc	934	FSMC_BCRx_MTYP \| FSMC_BCRx_MWID \| \
AnnaBridge	171:3a7713b1edbc	935	FSMC_BCRx_BURSTEN \| FSMC_BCRx_WAITPOL \| \
AnnaBridge	171:3a7713b1edbc	936	FSMC_BCRx_WRAPMOD \| FSMC_BCRx_WAITCFG \| \
AnnaBridge	171:3a7713b1edbc	937	FSMC_BCRx_WREN \| FSMC_BCRx_WAITEN \| \
AnnaBridge	171:3a7713b1edbc	938	FSMC_BCRx_EXTMOD \| FSMC_BCRx_ASYNCWAIT \| \
AnnaBridge	171:3a7713b1edbc	939	FSMC_BCRx_CBURSTRW))
AnnaBridge	171:3a7713b1edbc	940	/* --- BTR Register ---*/
AnnaBridge	171:3a7713b1edbc	941	/* BTR register clear mask */
AnnaBridge	171:3a7713b1edbc	942	#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET \| FSMC_BTRx_ADDHLD \|\
AnnaBridge	171:3a7713b1edbc	943	FSMC_BTRx_DATAST \| FSMC_BTRx_BUSTURN \|\
AnnaBridge	171:3a7713b1edbc	944	FSMC_BTRx_CLKDIV \| FSMC_BTRx_DATLAT \|\
AnnaBridge	171:3a7713b1edbc	945	FSMC_BTRx_ACCMOD))
AnnaBridge	171:3a7713b1edbc	946
AnnaBridge	171:3a7713b1edbc	947	/* --- BWTR Register ---*/
AnnaBridge	171:3a7713b1edbc	948	/* BWTR register clear mask */
AnnaBridge	171:3a7713b1edbc	949	#if (defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
AnnaBridge	171:3a7713b1edbc	950	#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET \| FSMC_BWTRx_ADDHLD \| \
AnnaBridge	171:3a7713b1edbc	951	FSMC_BWTRx_DATAST \| FSMC_BWTRx_ACCMOD \| \
AnnaBridge	171:3a7713b1edbc	952	FSMC_BWTRx_BUSTURN))
AnnaBridge	171:3a7713b1edbc	953	#else
AnnaBridge	171:3a7713b1edbc	954	#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET \| FSMC_BWTRx_ADDHLD \| \
AnnaBridge	171:3a7713b1edbc	955	FSMC_BWTRx_DATAST \| FSMC_BWTRx_ACCMOD \| \
AnnaBridge	171:3a7713b1edbc	956	FSMC_BWTRx_CLKDIV \| FSMC_BWTRx_DATLAT))
AnnaBridge	171:3a7713b1edbc	957	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	958
AnnaBridge	171:3a7713b1edbc	959	/* --- PIO4 Register ---*/
AnnaBridge	171:3a7713b1edbc	960	/* PIO4 register clear mask */
AnnaBridge	171:3a7713b1edbc	961	#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 \| FSMC_PIO4_IOWAIT4 \| \
AnnaBridge	171:3a7713b1edbc	962	FSMC_PIO4_IOHOLD4 \| FSMC_PIO4_IOHIZ4))
AnnaBridge	171:3a7713b1edbc	963	/**
AnnaBridge	171:3a7713b1edbc	964	* @}
AnnaBridge	171:3a7713b1edbc	965	*/
AnnaBridge	171:3a7713b1edbc	966	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	967
AnnaBridge	171:3a7713b1edbc	968	/** @addtogroup FSMC_LL_Exported_Functions
AnnaBridge	171:3a7713b1edbc	969	* @{
AnnaBridge	171:3a7713b1edbc	970	*/
AnnaBridge	171:3a7713b1edbc	971
AnnaBridge	171:3a7713b1edbc	972	/** @addtogroup FSMC_NORSRAM
AnnaBridge	171:3a7713b1edbc	973	* @{
AnnaBridge	171:3a7713b1edbc	974	*/
AnnaBridge	171:3a7713b1edbc	975
AnnaBridge	171:3a7713b1edbc	976	/** @addtogroup FSMC_NORSRAM_Group1
AnnaBridge	171:3a7713b1edbc	977	* @{
AnnaBridge	171:3a7713b1edbc	978	*/
AnnaBridge	171:3a7713b1edbc	979	/* FSMC_NORSRAM Controller functions ******************************************/
AnnaBridge	171:3a7713b1edbc	980	/* Initialization/de-initialization functions */
AnnaBridge	171:3a7713b1edbc	981	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_InitTypeDef Init);
AnnaBridge	171:3a7713b1edbc	982	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	983	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
AnnaBridge	171:3a7713b1edbc	984	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	985	/**
AnnaBridge	171:3a7713b1edbc	986	* @}
AnnaBridge	171:3a7713b1edbc	987	*/
AnnaBridge	171:3a7713b1edbc	988
AnnaBridge	171:3a7713b1edbc	989	/** @addtogroup FSMC_NORSRAM_Group2
AnnaBridge	171:3a7713b1edbc	990	* @{
AnnaBridge	171:3a7713b1edbc	991	*/
AnnaBridge	171:3a7713b1edbc	992	/* FSMC_NORSRAM Control functions */
AnnaBridge	171:3a7713b1edbc	993	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	994	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	995	/**
AnnaBridge	171:3a7713b1edbc	996	* @}
AnnaBridge	171:3a7713b1edbc	997	*/
AnnaBridge	171:3a7713b1edbc	998
AnnaBridge	171:3a7713b1edbc	999	/**
AnnaBridge	171:3a7713b1edbc	1000	* @}
AnnaBridge	171:3a7713b1edbc	1001	*/
AnnaBridge	171:3a7713b1edbc	1002
AnnaBridge	171:3a7713b1edbc	1003	#if (defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG))
AnnaBridge	171:3a7713b1edbc	1004	/** @addtogroup FSMC_NAND
AnnaBridge	171:3a7713b1edbc	1005	* @{
AnnaBridge	171:3a7713b1edbc	1006	*/
AnnaBridge	171:3a7713b1edbc	1007
AnnaBridge	171:3a7713b1edbc	1008	/* FSMC_NAND Controller functions **********************************************/
AnnaBridge	171:3a7713b1edbc	1009	/* Initialization/de-initialization functions */
AnnaBridge	171:3a7713b1edbc	1010	/** @addtogroup FSMC_NAND_Exported_Functions_Group1
AnnaBridge	171:3a7713b1edbc	1011	* @{
AnnaBridge	171:3a7713b1edbc	1012	*/
AnnaBridge	171:3a7713b1edbc	1013	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
AnnaBridge	171:3a7713b1edbc	1014	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1015	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1016	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1017	/**
AnnaBridge	171:3a7713b1edbc	1018	* @}
AnnaBridge	171:3a7713b1edbc	1019	*/
AnnaBridge	171:3a7713b1edbc	1020
AnnaBridge	171:3a7713b1edbc	1021	/* FSMC_NAND Control functions */
AnnaBridge	171:3a7713b1edbc	1022	/** @addtogroup FSMC_NAND_Exported_Functions_Group2
AnnaBridge	171:3a7713b1edbc	1023	* @{
AnnaBridge	171:3a7713b1edbc	1024	*/
AnnaBridge	171:3a7713b1edbc	1025	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1026	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1027	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
AnnaBridge	171:3a7713b1edbc	1028	/**
AnnaBridge	171:3a7713b1edbc	1029	* @}
AnnaBridge	171:3a7713b1edbc	1030	*/
AnnaBridge	171:3a7713b1edbc	1031
AnnaBridge	171:3a7713b1edbc	1032	/**
AnnaBridge	171:3a7713b1edbc	1033	* @}
AnnaBridge	171:3a7713b1edbc	1034	*/
AnnaBridge	171:3a7713b1edbc	1035
AnnaBridge	171:3a7713b1edbc	1036	/** @addtogroup FSMC_PCCARD
AnnaBridge	171:3a7713b1edbc	1037	* @{
AnnaBridge	171:3a7713b1edbc	1038	*/
AnnaBridge	171:3a7713b1edbc	1039
AnnaBridge	171:3a7713b1edbc	1040	/* FSMC_PCCARD Controller functions ********************************************/
AnnaBridge	171:3a7713b1edbc	1041	/* Initialization/de-initialization functions */
AnnaBridge	171:3a7713b1edbc	1042	/** @addtogroup FSMC_PCCARD_Exported_Functions_Group1
AnnaBridge	171:3a7713b1edbc	1043	* @{
AnnaBridge	171:3a7713b1edbc	1044	*/
AnnaBridge	171:3a7713b1edbc	1045	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
AnnaBridge	171:3a7713b1edbc	1046	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	171:3a7713b1edbc	1047	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	171:3a7713b1edbc	1048	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	171:3a7713b1edbc	1049	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
AnnaBridge	171:3a7713b1edbc	1050	/**
AnnaBridge	171:3a7713b1edbc	1051	* @}
AnnaBridge	171:3a7713b1edbc	1052	*/
AnnaBridge	171:3a7713b1edbc	1053
AnnaBridge	171:3a7713b1edbc	1054	/**
AnnaBridge	171:3a7713b1edbc	1055	* @}
AnnaBridge	171:3a7713b1edbc	1056	*/
AnnaBridge	171:3a7713b1edbc	1057	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1058
AnnaBridge	171:3a7713b1edbc	1059	/**
AnnaBridge	171:3a7713b1edbc	1060	* @}
AnnaBridge	171:3a7713b1edbc	1061	*/
AnnaBridge	171:3a7713b1edbc	1062
AnnaBridge	171:3a7713b1edbc	1063	/**
AnnaBridge	171:3a7713b1edbc	1064	* @}
AnnaBridge	171:3a7713b1edbc	1065	*/
AnnaBridge	171:3a7713b1edbc	1066	#endif /* FSMC_BANK1 */
AnnaBridge	171:3a7713b1edbc	1067
AnnaBridge	171:3a7713b1edbc	1068	/**
AnnaBridge	171:3a7713b1edbc	1069	* @}
AnnaBridge	171:3a7713b1edbc	1070	*/
AnnaBridge	171:3a7713b1edbc	1071
AnnaBridge	171:3a7713b1edbc	1072	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1073	}
AnnaBridge	171:3a7713b1edbc	1074	#endif
AnnaBridge	171:3a7713b1edbc	1075
AnnaBridge	171:3a7713b1edbc	1076	#endif /* __STM32F1xx_LL_FSMC_H */
AnnaBridge	171:3a7713b1edbc	1077
AnnaBridge	171:3a7713b1edbc	1078	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	171:3a7713b1edbc	1079