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TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f1xx_hal_gpio_ex.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f1xx_hal_gpio_ex.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of GPIO HAL Extension module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F1xx_HAL_GPIO_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F1xx_HAL_GPIO_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f1xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F1xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 49 | */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | /** @defgroup GPIOEx GPIOEx |
| AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 53 | */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 56 | |
| AnnaBridge | 171:3a7713b1edbc | 57 | /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 58 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 59 | */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | |
| AnnaBridge | 171:3a7713b1edbc | 61 | /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration |
| AnnaBridge | 171:3a7713b1edbc | 62 | * @brief This section propose definition to use the Cortex EVENTOUT signal. |
| AnnaBridge | 171:3a7713b1edbc | 63 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 64 | */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | |
| AnnaBridge | 171:3a7713b1edbc | 66 | /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin |
| AnnaBridge | 171:3a7713b1edbc | 67 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 68 | */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | |
| AnnaBridge | 171:3a7713b1edbc | 70 | #define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | #define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | #define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | #define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | #define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | #define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | #define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | #define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | #define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | #define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | |
| AnnaBridge | 171:3a7713b1edbc | 87 | #define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \ |
| AnnaBridge | 171:3a7713b1edbc | 88 | ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 89 | ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 90 | ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \ |
| AnnaBridge | 171:3a7713b1edbc | 91 | ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \ |
| AnnaBridge | 171:3a7713b1edbc | 92 | ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 93 | ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \ |
| AnnaBridge | 171:3a7713b1edbc | 94 | ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \ |
| AnnaBridge | 171:3a7713b1edbc | 95 | ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 96 | ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \ |
| AnnaBridge | 171:3a7713b1edbc | 97 | ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \ |
| AnnaBridge | 171:3a7713b1edbc | 98 | ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \ |
| AnnaBridge | 171:3a7713b1edbc | 99 | ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \ |
| AnnaBridge | 171:3a7713b1edbc | 100 | ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \ |
| AnnaBridge | 171:3a7713b1edbc | 101 | ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \ |
| AnnaBridge | 171:3a7713b1edbc | 102 | ((__PIN__) == AFIO_EVENTOUT_PIN_15)) |
| AnnaBridge | 171:3a7713b1edbc | 103 | /** |
| AnnaBridge | 171:3a7713b1edbc | 104 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 105 | */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | |
| AnnaBridge | 171:3a7713b1edbc | 107 | /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port |
| AnnaBridge | 171:3a7713b1edbc | 108 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 109 | */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | |
| AnnaBridge | 171:3a7713b1edbc | 111 | #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \ |
| AnnaBridge | 171:3a7713b1edbc | 118 | ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 119 | ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \ |
| AnnaBridge | 171:3a7713b1edbc | 120 | ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \ |
| AnnaBridge | 171:3a7713b1edbc | 121 | ((__PORT__) == AFIO_EVENTOUT_PORT_E)) |
| AnnaBridge | 171:3a7713b1edbc | 122 | /** |
| AnnaBridge | 171:3a7713b1edbc | 123 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 124 | */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | |
| AnnaBridge | 171:3a7713b1edbc | 126 | /** |
| AnnaBridge | 171:3a7713b1edbc | 127 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 128 | */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | |
| AnnaBridge | 171:3a7713b1edbc | 130 | /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping |
| AnnaBridge | 171:3a7713b1edbc | 131 | * @brief This section propose definition to remap the alternate function to some other port/pins. |
| AnnaBridge | 171:3a7713b1edbc | 132 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 133 | */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | |
| AnnaBridge | 171:3a7713b1edbc | 135 | /** |
| AnnaBridge | 171:3a7713b1edbc | 136 | * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
| AnnaBridge | 171:3a7713b1edbc | 137 | * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) |
| AnnaBridge | 171:3a7713b1edbc | 138 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 139 | */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 141 | |
| AnnaBridge | 171:3a7713b1edbc | 142 | /** |
| AnnaBridge | 171:3a7713b1edbc | 143 | * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
| AnnaBridge | 171:3a7713b1edbc | 144 | * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) |
| AnnaBridge | 171:3a7713b1edbc | 145 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 146 | */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 148 | |
| AnnaBridge | 171:3a7713b1edbc | 149 | /** |
| AnnaBridge | 171:3a7713b1edbc | 150 | * @brief Enable the remapping of I2C1 alternate function SCL and SDA. |
| AnnaBridge | 171:3a7713b1edbc | 151 | * @note ENABLE: Remap (SCL/PB8, SDA/PB9) |
| AnnaBridge | 171:3a7713b1edbc | 152 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 153 | */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 155 | |
| AnnaBridge | 171:3a7713b1edbc | 156 | /** |
| AnnaBridge | 171:3a7713b1edbc | 157 | * @brief Disable the remapping of I2C1 alternate function SCL and SDA. |
| AnnaBridge | 171:3a7713b1edbc | 158 | * @note DISABLE: No remap (SCL/PB6, SDA/PB7) |
| AnnaBridge | 171:3a7713b1edbc | 159 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 160 | */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 162 | |
| AnnaBridge | 171:3a7713b1edbc | 163 | /** |
| AnnaBridge | 171:3a7713b1edbc | 164 | * @brief Enable the remapping of USART1 alternate function TX and RX. |
| AnnaBridge | 171:3a7713b1edbc | 165 | * @note ENABLE: Remap (TX/PB6, RX/PB7) |
| AnnaBridge | 171:3a7713b1edbc | 166 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 167 | */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 169 | |
| AnnaBridge | 171:3a7713b1edbc | 170 | /** |
| AnnaBridge | 171:3a7713b1edbc | 171 | * @brief Disable the remapping of USART1 alternate function TX and RX. |
| AnnaBridge | 171:3a7713b1edbc | 172 | * @note DISABLE: No remap (TX/PA9, RX/PA10) |
| AnnaBridge | 171:3a7713b1edbc | 173 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 174 | */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 176 | |
| AnnaBridge | 171:3a7713b1edbc | 177 | /** |
| AnnaBridge | 171:3a7713b1edbc | 178 | * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
| AnnaBridge | 171:3a7713b1edbc | 179 | * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) |
| AnnaBridge | 171:3a7713b1edbc | 180 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 181 | */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 183 | |
| AnnaBridge | 171:3a7713b1edbc | 184 | /** |
| AnnaBridge | 171:3a7713b1edbc | 185 | * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
| AnnaBridge | 171:3a7713b1edbc | 186 | * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) |
| AnnaBridge | 171:3a7713b1edbc | 187 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 188 | */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 190 | |
| AnnaBridge | 171:3a7713b1edbc | 191 | /** |
| AnnaBridge | 171:3a7713b1edbc | 192 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| AnnaBridge | 171:3a7713b1edbc | 193 | * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) |
| AnnaBridge | 171:3a7713b1edbc | 194 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 195 | */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 197 | |
| AnnaBridge | 171:3a7713b1edbc | 198 | /** |
| AnnaBridge | 171:3a7713b1edbc | 199 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| AnnaBridge | 171:3a7713b1edbc | 200 | * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) |
| AnnaBridge | 171:3a7713b1edbc | 201 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 202 | */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 204 | |
| AnnaBridge | 171:3a7713b1edbc | 205 | /** |
| AnnaBridge | 171:3a7713b1edbc | 206 | * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| AnnaBridge | 171:3a7713b1edbc | 207 | * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) |
| AnnaBridge | 171:3a7713b1edbc | 208 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 209 | */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 211 | |
| AnnaBridge | 171:3a7713b1edbc | 212 | /** |
| AnnaBridge | 171:3a7713b1edbc | 213 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| AnnaBridge | 171:3a7713b1edbc | 214 | * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) |
| AnnaBridge | 171:3a7713b1edbc | 215 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 216 | */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 218 | |
| AnnaBridge | 171:3a7713b1edbc | 219 | /** |
| AnnaBridge | 171:3a7713b1edbc | 220 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| AnnaBridge | 171:3a7713b1edbc | 221 | * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) |
| AnnaBridge | 171:3a7713b1edbc | 222 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 223 | */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 225 | |
| AnnaBridge | 171:3a7713b1edbc | 226 | /** |
| AnnaBridge | 171:3a7713b1edbc | 227 | * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| AnnaBridge | 171:3a7713b1edbc | 228 | * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) |
| AnnaBridge | 171:3a7713b1edbc | 229 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 230 | */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 232 | |
| AnnaBridge | 171:3a7713b1edbc | 233 | /** |
| AnnaBridge | 171:3a7713b1edbc | 234 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| AnnaBridge | 171:3a7713b1edbc | 235 | * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) |
| AnnaBridge | 171:3a7713b1edbc | 236 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 237 | */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 239 | |
| AnnaBridge | 171:3a7713b1edbc | 240 | /** |
| AnnaBridge | 171:3a7713b1edbc | 241 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| AnnaBridge | 171:3a7713b1edbc | 242 | * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) |
| AnnaBridge | 171:3a7713b1edbc | 243 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 244 | */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 246 | |
| AnnaBridge | 171:3a7713b1edbc | 247 | /** |
| AnnaBridge | 171:3a7713b1edbc | 248 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| AnnaBridge | 171:3a7713b1edbc | 249 | * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) |
| AnnaBridge | 171:3a7713b1edbc | 250 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 251 | */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 253 | |
| AnnaBridge | 171:3a7713b1edbc | 254 | /** |
| AnnaBridge | 171:3a7713b1edbc | 255 | * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| AnnaBridge | 171:3a7713b1edbc | 256 | * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) |
| AnnaBridge | 171:3a7713b1edbc | 257 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 258 | */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 260 | |
| AnnaBridge | 171:3a7713b1edbc | 261 | /** |
| AnnaBridge | 171:3a7713b1edbc | 262 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
| AnnaBridge | 171:3a7713b1edbc | 263 | * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) |
| AnnaBridge | 171:3a7713b1edbc | 264 | * @note TIM3_ETR on PE0 is not re-mapped. |
| AnnaBridge | 171:3a7713b1edbc | 265 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 266 | */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 268 | |
| AnnaBridge | 171:3a7713b1edbc | 269 | /** |
| AnnaBridge | 171:3a7713b1edbc | 270 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
| AnnaBridge | 171:3a7713b1edbc | 271 | * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) |
| AnnaBridge | 171:3a7713b1edbc | 272 | * @note TIM3_ETR on PE0 is not re-mapped. |
| AnnaBridge | 171:3a7713b1edbc | 273 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 274 | */ |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 276 | |
| AnnaBridge | 171:3a7713b1edbc | 277 | /** |
| AnnaBridge | 171:3a7713b1edbc | 278 | * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 |
| AnnaBridge | 171:3a7713b1edbc | 279 | * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) |
| AnnaBridge | 171:3a7713b1edbc | 280 | * @note TIM3_ETR on PE0 is not re-mapped. |
| AnnaBridge | 171:3a7713b1edbc | 281 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 282 | */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 284 | |
| AnnaBridge | 171:3a7713b1edbc | 285 | /** |
| AnnaBridge | 171:3a7713b1edbc | 286 | * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. |
| AnnaBridge | 171:3a7713b1edbc | 287 | * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) |
| AnnaBridge | 171:3a7713b1edbc | 288 | * @note TIM4_ETR on PE0 is not re-mapped. |
| AnnaBridge | 171:3a7713b1edbc | 289 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 290 | */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 292 | |
| AnnaBridge | 171:3a7713b1edbc | 293 | /** |
| AnnaBridge | 171:3a7713b1edbc | 294 | * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. |
| AnnaBridge | 171:3a7713b1edbc | 295 | * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) |
| AnnaBridge | 171:3a7713b1edbc | 296 | * @note TIM4_ETR on PE0 is not re-mapped. |
| AnnaBridge | 171:3a7713b1edbc | 297 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 298 | */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 300 | |
| AnnaBridge | 171:3a7713b1edbc | 301 | #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) |
| AnnaBridge | 171:3a7713b1edbc | 302 | |
| AnnaBridge | 171:3a7713b1edbc | 303 | /** |
| AnnaBridge | 171:3a7713b1edbc | 304 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| AnnaBridge | 171:3a7713b1edbc | 305 | * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 |
| AnnaBridge | 171:3a7713b1edbc | 306 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 307 | */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 309 | |
| AnnaBridge | 171:3a7713b1edbc | 310 | /** |
| AnnaBridge | 171:3a7713b1edbc | 311 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| AnnaBridge | 171:3a7713b1edbc | 312 | * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) |
| AnnaBridge | 171:3a7713b1edbc | 313 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 314 | */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 316 | |
| AnnaBridge | 171:3a7713b1edbc | 317 | /** |
| AnnaBridge | 171:3a7713b1edbc | 318 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| AnnaBridge | 171:3a7713b1edbc | 319 | * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 |
| AnnaBridge | 171:3a7713b1edbc | 320 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 321 | */ |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 323 | |
| AnnaBridge | 171:3a7713b1edbc | 324 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 325 | |
| AnnaBridge | 171:3a7713b1edbc | 326 | /** |
| AnnaBridge | 171:3a7713b1edbc | 327 | * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used |
| AnnaBridge | 171:3a7713b1edbc | 328 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
| AnnaBridge | 171:3a7713b1edbc | 329 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
| AnnaBridge | 171:3a7713b1edbc | 330 | * on 100-pin and 144-pin packages, no need for remapping). |
| AnnaBridge | 171:3a7713b1edbc | 331 | * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. |
| AnnaBridge | 171:3a7713b1edbc | 332 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 333 | */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 335 | |
| AnnaBridge | 171:3a7713b1edbc | 336 | /** |
| AnnaBridge | 171:3a7713b1edbc | 337 | * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used |
| AnnaBridge | 171:3a7713b1edbc | 338 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
| AnnaBridge | 171:3a7713b1edbc | 339 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
| AnnaBridge | 171:3a7713b1edbc | 340 | * on 100-pin and 144-pin packages, no need for remapping). |
| AnnaBridge | 171:3a7713b1edbc | 341 | * @note DISABLE: No remapping of PD0 and PD1 |
| AnnaBridge | 171:3a7713b1edbc | 342 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 343 | */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 345 | |
| AnnaBridge | 171:3a7713b1edbc | 346 | #if defined(AFIO_MAPR_TIM5CH4_IREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 347 | /** |
| AnnaBridge | 171:3a7713b1edbc | 348 | * @brief Enable the remapping of TIM5CH4. |
| AnnaBridge | 171:3a7713b1edbc | 349 | * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. |
| AnnaBridge | 171:3a7713b1edbc | 350 | * @note This function is available only in high density value line devices. |
| AnnaBridge | 171:3a7713b1edbc | 351 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 352 | */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 354 | |
| AnnaBridge | 171:3a7713b1edbc | 355 | /** |
| AnnaBridge | 171:3a7713b1edbc | 356 | * @brief Disable the remapping of TIM5CH4. |
| AnnaBridge | 171:3a7713b1edbc | 357 | * @note DISABLE: TIM5_CH4 is connected to PA3 |
| AnnaBridge | 171:3a7713b1edbc | 358 | * @note This function is available only in high density value line devices. |
| AnnaBridge | 171:3a7713b1edbc | 359 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 360 | */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 362 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 363 | |
| AnnaBridge | 171:3a7713b1edbc | 364 | #if defined(AFIO_MAPR_ETH_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 365 | /** |
| AnnaBridge | 171:3a7713b1edbc | 366 | * @brief Enable the remapping of Ethernet MAC connections with the PHY. |
| AnnaBridge | 171:3a7713b1edbc | 367 | * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) |
| AnnaBridge | 171:3a7713b1edbc | 368 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 369 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 370 | */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 372 | |
| AnnaBridge | 171:3a7713b1edbc | 373 | /** |
| AnnaBridge | 171:3a7713b1edbc | 374 | * @brief Disable the remapping of Ethernet MAC connections with the PHY. |
| AnnaBridge | 171:3a7713b1edbc | 375 | * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) |
| AnnaBridge | 171:3a7713b1edbc | 376 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 377 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 378 | */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 380 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 381 | |
| AnnaBridge | 171:3a7713b1edbc | 382 | #if defined(AFIO_MAPR_CAN2_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 383 | |
| AnnaBridge | 171:3a7713b1edbc | 384 | /** |
| AnnaBridge | 171:3a7713b1edbc | 385 | * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
| AnnaBridge | 171:3a7713b1edbc | 386 | * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) |
| AnnaBridge | 171:3a7713b1edbc | 387 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 388 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 389 | */ |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 391 | |
| AnnaBridge | 171:3a7713b1edbc | 392 | /** |
| AnnaBridge | 171:3a7713b1edbc | 393 | * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
| AnnaBridge | 171:3a7713b1edbc | 394 | * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) |
| AnnaBridge | 171:3a7713b1edbc | 395 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 396 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 397 | */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 399 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 400 | |
| AnnaBridge | 171:3a7713b1edbc | 401 | #if defined(AFIO_MAPR_MII_RMII_SEL) |
| AnnaBridge | 171:3a7713b1edbc | 402 | /** |
| AnnaBridge | 171:3a7713b1edbc | 403 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
| AnnaBridge | 171:3a7713b1edbc | 404 | * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY |
| AnnaBridge | 171:3a7713b1edbc | 405 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 406 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 407 | */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL) |
| AnnaBridge | 171:3a7713b1edbc | 409 | |
| AnnaBridge | 171:3a7713b1edbc | 410 | /** |
| AnnaBridge | 171:3a7713b1edbc | 411 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
| AnnaBridge | 171:3a7713b1edbc | 412 | * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY |
| AnnaBridge | 171:3a7713b1edbc | 413 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 414 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 415 | */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL) |
| AnnaBridge | 171:3a7713b1edbc | 417 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 418 | |
| AnnaBridge | 171:3a7713b1edbc | 419 | /** |
| AnnaBridge | 171:3a7713b1edbc | 420 | * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
| AnnaBridge | 171:3a7713b1edbc | 421 | * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. |
| AnnaBridge | 171:3a7713b1edbc | 422 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 423 | */ |
| AnnaBridge | 171:3a7713b1edbc | 424 | #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 425 | |
| AnnaBridge | 171:3a7713b1edbc | 426 | /** |
| AnnaBridge | 171:3a7713b1edbc | 427 | * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
| AnnaBridge | 171:3a7713b1edbc | 428 | * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 |
| AnnaBridge | 171:3a7713b1edbc | 429 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 430 | */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 432 | |
| AnnaBridge | 171:3a7713b1edbc | 433 | /** |
| AnnaBridge | 171:3a7713b1edbc | 434 | * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
| AnnaBridge | 171:3a7713b1edbc | 435 | * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. |
| AnnaBridge | 171:3a7713b1edbc | 436 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 437 | */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 439 | |
| AnnaBridge | 171:3a7713b1edbc | 440 | /** |
| AnnaBridge | 171:3a7713b1edbc | 441 | * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
| AnnaBridge | 171:3a7713b1edbc | 442 | * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 |
| AnnaBridge | 171:3a7713b1edbc | 443 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 444 | */ |
| AnnaBridge | 171:3a7713b1edbc | 445 | #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 446 | |
| AnnaBridge | 171:3a7713b1edbc | 447 | #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 448 | |
| AnnaBridge | 171:3a7713b1edbc | 449 | /** |
| AnnaBridge | 171:3a7713b1edbc | 450 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
| AnnaBridge | 171:3a7713b1edbc | 451 | * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. |
| AnnaBridge | 171:3a7713b1edbc | 452 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 453 | */ |
| AnnaBridge | 171:3a7713b1edbc | 454 | #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 455 | |
| AnnaBridge | 171:3a7713b1edbc | 456 | /** |
| AnnaBridge | 171:3a7713b1edbc | 457 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
| AnnaBridge | 171:3a7713b1edbc | 458 | * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 |
| AnnaBridge | 171:3a7713b1edbc | 459 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 460 | */ |
| AnnaBridge | 171:3a7713b1edbc | 461 | #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 462 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 463 | |
| AnnaBridge | 171:3a7713b1edbc | 464 | #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 465 | |
| AnnaBridge | 171:3a7713b1edbc | 466 | /** |
| AnnaBridge | 171:3a7713b1edbc | 467 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| AnnaBridge | 171:3a7713b1edbc | 468 | * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. |
| AnnaBridge | 171:3a7713b1edbc | 469 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 470 | */ |
| AnnaBridge | 171:3a7713b1edbc | 471 | #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 472 | |
| AnnaBridge | 171:3a7713b1edbc | 473 | /** |
| AnnaBridge | 171:3a7713b1edbc | 474 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| AnnaBridge | 171:3a7713b1edbc | 475 | * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 |
| AnnaBridge | 171:3a7713b1edbc | 476 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 477 | */ |
| AnnaBridge | 171:3a7713b1edbc | 478 | #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 479 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 480 | |
| AnnaBridge | 171:3a7713b1edbc | 481 | /** |
| AnnaBridge | 171:3a7713b1edbc | 482 | * @brief Enable the Serial wire JTAG configuration |
| AnnaBridge | 171:3a7713b1edbc | 483 | * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State |
| AnnaBridge | 171:3a7713b1edbc | 484 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 485 | */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | #define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET) |
| AnnaBridge | 171:3a7713b1edbc | 487 | |
| AnnaBridge | 171:3a7713b1edbc | 488 | /** |
| AnnaBridge | 171:3a7713b1edbc | 489 | * @brief Enable the Serial wire JTAG configuration |
| AnnaBridge | 171:3a7713b1edbc | 490 | * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
| AnnaBridge | 171:3a7713b1edbc | 491 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 492 | */ |
| AnnaBridge | 171:3a7713b1edbc | 493 | #define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST) |
| AnnaBridge | 171:3a7713b1edbc | 494 | |
| AnnaBridge | 171:3a7713b1edbc | 495 | /** |
| AnnaBridge | 171:3a7713b1edbc | 496 | * @brief Enable the Serial wire JTAG configuration |
| AnnaBridge | 171:3a7713b1edbc | 497 | * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled |
| AnnaBridge | 171:3a7713b1edbc | 498 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 499 | */ |
| AnnaBridge | 171:3a7713b1edbc | 500 | |
| AnnaBridge | 171:3a7713b1edbc | 501 | #define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE) |
| AnnaBridge | 171:3a7713b1edbc | 502 | |
| AnnaBridge | 171:3a7713b1edbc | 503 | /** |
| AnnaBridge | 171:3a7713b1edbc | 504 | * @brief Disable the Serial wire JTAG configuration |
| AnnaBridge | 171:3a7713b1edbc | 505 | * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled |
| AnnaBridge | 171:3a7713b1edbc | 506 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 507 | */ |
| AnnaBridge | 171:3a7713b1edbc | 508 | #define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE) |
| AnnaBridge | 171:3a7713b1edbc | 509 | |
| AnnaBridge | 171:3a7713b1edbc | 510 | #if defined(AFIO_MAPR_SPI3_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 511 | |
| AnnaBridge | 171:3a7713b1edbc | 512 | /** |
| AnnaBridge | 171:3a7713b1edbc | 513 | * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
| AnnaBridge | 171:3a7713b1edbc | 514 | * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) |
| AnnaBridge | 171:3a7713b1edbc | 515 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 516 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 517 | */ |
| AnnaBridge | 171:3a7713b1edbc | 518 | #define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 519 | |
| AnnaBridge | 171:3a7713b1edbc | 520 | /** |
| AnnaBridge | 171:3a7713b1edbc | 521 | * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
| AnnaBridge | 171:3a7713b1edbc | 522 | * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). |
| AnnaBridge | 171:3a7713b1edbc | 523 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 524 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 525 | */ |
| AnnaBridge | 171:3a7713b1edbc | 526 | #define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 527 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 528 | |
| AnnaBridge | 171:3a7713b1edbc | 529 | #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 530 | |
| AnnaBridge | 171:3a7713b1edbc | 531 | /** |
| AnnaBridge | 171:3a7713b1edbc | 532 | * @brief Control of TIM2_ITR1 internal mapping. |
| AnnaBridge | 171:3a7713b1edbc | 533 | * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. |
| AnnaBridge | 171:3a7713b1edbc | 534 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 535 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 536 | */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | #define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 538 | |
| AnnaBridge | 171:3a7713b1edbc | 539 | /** |
| AnnaBridge | 171:3a7713b1edbc | 540 | * @brief Control of TIM2_ITR1 internal mapping. |
| AnnaBridge | 171:3a7713b1edbc | 541 | * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. |
| AnnaBridge | 171:3a7713b1edbc | 542 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 543 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 544 | */ |
| AnnaBridge | 171:3a7713b1edbc | 545 | #define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP) |
| AnnaBridge | 171:3a7713b1edbc | 546 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 547 | |
| AnnaBridge | 171:3a7713b1edbc | 548 | #if defined(AFIO_MAPR_PTP_PPS_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 549 | |
| AnnaBridge | 171:3a7713b1edbc | 550 | /** |
| AnnaBridge | 171:3a7713b1edbc | 551 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| AnnaBridge | 171:3a7713b1edbc | 552 | * @note ENABLE: PTP_PPS is output on PB5 pin. |
| AnnaBridge | 171:3a7713b1edbc | 553 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 554 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 555 | */ |
| AnnaBridge | 171:3a7713b1edbc | 556 | #define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 557 | |
| AnnaBridge | 171:3a7713b1edbc | 558 | /** |
| AnnaBridge | 171:3a7713b1edbc | 559 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| AnnaBridge | 171:3a7713b1edbc | 560 | * @note DISABLE: PTP_PPS not output on PB5 pin. |
| AnnaBridge | 171:3a7713b1edbc | 561 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| AnnaBridge | 171:3a7713b1edbc | 562 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 563 | */ |
| AnnaBridge | 171:3a7713b1edbc | 564 | #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 565 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 566 | |
| AnnaBridge | 171:3a7713b1edbc | 567 | #if defined(AFIO_MAPR2_TIM9_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 568 | |
| AnnaBridge | 171:3a7713b1edbc | 569 | /** |
| AnnaBridge | 171:3a7713b1edbc | 570 | * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. |
| AnnaBridge | 171:3a7713b1edbc | 571 | * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). |
| AnnaBridge | 171:3a7713b1edbc | 572 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 573 | */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | #define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 575 | |
| AnnaBridge | 171:3a7713b1edbc | 576 | /** |
| AnnaBridge | 171:3a7713b1edbc | 577 | * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. |
| AnnaBridge | 171:3a7713b1edbc | 578 | * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). |
| AnnaBridge | 171:3a7713b1edbc | 579 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 580 | */ |
| AnnaBridge | 171:3a7713b1edbc | 581 | #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 582 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 583 | |
| AnnaBridge | 171:3a7713b1edbc | 584 | #if defined(AFIO_MAPR2_TIM10_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 585 | |
| AnnaBridge | 171:3a7713b1edbc | 586 | /** |
| AnnaBridge | 171:3a7713b1edbc | 587 | * @brief Enable the remapping of TIM10_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 588 | * @note ENABLE: Remap (TIM10_CH1 on PF6). |
| AnnaBridge | 171:3a7713b1edbc | 589 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 590 | */ |
| AnnaBridge | 171:3a7713b1edbc | 591 | #define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 592 | |
| AnnaBridge | 171:3a7713b1edbc | 593 | /** |
| AnnaBridge | 171:3a7713b1edbc | 594 | * @brief Disable the remapping of TIM10_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 595 | * @note DISABLE: No remap (TIM10_CH1 on PB8). |
| AnnaBridge | 171:3a7713b1edbc | 596 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 597 | */ |
| AnnaBridge | 171:3a7713b1edbc | 598 | #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 599 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 600 | |
| AnnaBridge | 171:3a7713b1edbc | 601 | #if defined(AFIO_MAPR2_TIM11_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 602 | /** |
| AnnaBridge | 171:3a7713b1edbc | 603 | * @brief Enable the remapping of TIM11_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 604 | * @note ENABLE: Remap (TIM11_CH1 on PF7). |
| AnnaBridge | 171:3a7713b1edbc | 605 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 606 | */ |
| AnnaBridge | 171:3a7713b1edbc | 607 | #define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 608 | |
| AnnaBridge | 171:3a7713b1edbc | 609 | /** |
| AnnaBridge | 171:3a7713b1edbc | 610 | * @brief Disable the remapping of TIM11_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 611 | * @note DISABLE: No remap (TIM11_CH1 on PB9). |
| AnnaBridge | 171:3a7713b1edbc | 612 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 613 | */ |
| AnnaBridge | 171:3a7713b1edbc | 614 | #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 615 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 616 | |
| AnnaBridge | 171:3a7713b1edbc | 617 | #if defined(AFIO_MAPR2_TIM13_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 618 | |
| AnnaBridge | 171:3a7713b1edbc | 619 | /** |
| AnnaBridge | 171:3a7713b1edbc | 620 | * @brief Enable the remapping of TIM13_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 621 | * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). |
| AnnaBridge | 171:3a7713b1edbc | 622 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 623 | */ |
| AnnaBridge | 171:3a7713b1edbc | 624 | #define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 625 | |
| AnnaBridge | 171:3a7713b1edbc | 626 | /** |
| AnnaBridge | 171:3a7713b1edbc | 627 | * @brief Disable the remapping of TIM13_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 628 | * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). |
| AnnaBridge | 171:3a7713b1edbc | 629 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 630 | */ |
| AnnaBridge | 171:3a7713b1edbc | 631 | #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 632 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 633 | |
| AnnaBridge | 171:3a7713b1edbc | 634 | #if defined(AFIO_MAPR2_TIM14_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 635 | |
| AnnaBridge | 171:3a7713b1edbc | 636 | /** |
| AnnaBridge | 171:3a7713b1edbc | 637 | * @brief Enable the remapping of TIM14_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 638 | * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). |
| AnnaBridge | 171:3a7713b1edbc | 639 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 640 | */ |
| AnnaBridge | 171:3a7713b1edbc | 641 | #define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 642 | |
| AnnaBridge | 171:3a7713b1edbc | 643 | /** |
| AnnaBridge | 171:3a7713b1edbc | 644 | * @brief Disable the remapping of TIM14_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 645 | * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). |
| AnnaBridge | 171:3a7713b1edbc | 646 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 647 | */ |
| AnnaBridge | 171:3a7713b1edbc | 648 | #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 649 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 650 | |
| AnnaBridge | 171:3a7713b1edbc | 651 | #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 652 | |
| AnnaBridge | 171:3a7713b1edbc | 653 | /** |
| AnnaBridge | 171:3a7713b1edbc | 654 | * @brief Controls the use of the optional FSMC_NADV signal. |
| AnnaBridge | 171:3a7713b1edbc | 655 | * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 656 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 657 | */ |
| AnnaBridge | 171:3a7713b1edbc | 658 | #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 659 | |
| AnnaBridge | 171:3a7713b1edbc | 660 | /** |
| AnnaBridge | 171:3a7713b1edbc | 661 | * @brief Controls the use of the optional FSMC_NADV signal. |
| AnnaBridge | 171:3a7713b1edbc | 662 | * @note CONNECTED: The NADV signal is connected to the output (default). |
| AnnaBridge | 171:3a7713b1edbc | 663 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 664 | */ |
| AnnaBridge | 171:3a7713b1edbc | 665 | #define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 666 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 667 | |
| AnnaBridge | 171:3a7713b1edbc | 668 | #if defined(AFIO_MAPR2_TIM15_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 669 | |
| AnnaBridge | 171:3a7713b1edbc | 670 | /** |
| AnnaBridge | 171:3a7713b1edbc | 671 | * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. |
| AnnaBridge | 171:3a7713b1edbc | 672 | * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). |
| AnnaBridge | 171:3a7713b1edbc | 673 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 674 | */ |
| AnnaBridge | 171:3a7713b1edbc | 675 | #define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 676 | |
| AnnaBridge | 171:3a7713b1edbc | 677 | /** |
| AnnaBridge | 171:3a7713b1edbc | 678 | * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. |
| AnnaBridge | 171:3a7713b1edbc | 679 | * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). |
| AnnaBridge | 171:3a7713b1edbc | 680 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 681 | */ |
| AnnaBridge | 171:3a7713b1edbc | 682 | #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 683 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 684 | |
| AnnaBridge | 171:3a7713b1edbc | 685 | #if defined(AFIO_MAPR2_TIM16_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 686 | |
| AnnaBridge | 171:3a7713b1edbc | 687 | /** |
| AnnaBridge | 171:3a7713b1edbc | 688 | * @brief Enable the remapping of TIM16_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 689 | * @note ENABLE: Remap (TIM16_CH1 on PA6). |
| AnnaBridge | 171:3a7713b1edbc | 690 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 691 | */ |
| AnnaBridge | 171:3a7713b1edbc | 692 | #define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 693 | |
| AnnaBridge | 171:3a7713b1edbc | 694 | /** |
| AnnaBridge | 171:3a7713b1edbc | 695 | * @brief Disable the remapping of TIM16_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 696 | * @note DISABLE: No remap (TIM16_CH1 on PB8). |
| AnnaBridge | 171:3a7713b1edbc | 697 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 698 | */ |
| AnnaBridge | 171:3a7713b1edbc | 699 | #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 700 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 701 | |
| AnnaBridge | 171:3a7713b1edbc | 702 | #if defined(AFIO_MAPR2_TIM17_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 703 | |
| AnnaBridge | 171:3a7713b1edbc | 704 | /** |
| AnnaBridge | 171:3a7713b1edbc | 705 | * @brief Enable the remapping of TIM17_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 706 | * @note ENABLE: Remap (TIM17_CH1 on PA7). |
| AnnaBridge | 171:3a7713b1edbc | 707 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 708 | */ |
| AnnaBridge | 171:3a7713b1edbc | 709 | #define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 710 | |
| AnnaBridge | 171:3a7713b1edbc | 711 | /** |
| AnnaBridge | 171:3a7713b1edbc | 712 | * @brief Disable the remapping of TIM17_CH1. |
| AnnaBridge | 171:3a7713b1edbc | 713 | * @note DISABLE: No remap (TIM17_CH1 on PB9). |
| AnnaBridge | 171:3a7713b1edbc | 714 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 715 | */ |
| AnnaBridge | 171:3a7713b1edbc | 716 | #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 717 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 718 | |
| AnnaBridge | 171:3a7713b1edbc | 719 | #if defined(AFIO_MAPR2_CEC_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 720 | |
| AnnaBridge | 171:3a7713b1edbc | 721 | /** |
| AnnaBridge | 171:3a7713b1edbc | 722 | * @brief Enable the remapping of CEC. |
| AnnaBridge | 171:3a7713b1edbc | 723 | * @note ENABLE: Remap (CEC on PB10). |
| AnnaBridge | 171:3a7713b1edbc | 724 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 725 | */ |
| AnnaBridge | 171:3a7713b1edbc | 726 | #define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 727 | |
| AnnaBridge | 171:3a7713b1edbc | 728 | /** |
| AnnaBridge | 171:3a7713b1edbc | 729 | * @brief Disable the remapping of CEC. |
| AnnaBridge | 171:3a7713b1edbc | 730 | * @note DISABLE: No remap (CEC on PB8). |
| AnnaBridge | 171:3a7713b1edbc | 731 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 732 | */ |
| AnnaBridge | 171:3a7713b1edbc | 733 | #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 734 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 735 | |
| AnnaBridge | 171:3a7713b1edbc | 736 | #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 737 | |
| AnnaBridge | 171:3a7713b1edbc | 738 | /** |
| AnnaBridge | 171:3a7713b1edbc | 739 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
| AnnaBridge | 171:3a7713b1edbc | 740 | * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) |
| AnnaBridge | 171:3a7713b1edbc | 741 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 742 | */ |
| AnnaBridge | 171:3a7713b1edbc | 743 | #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 744 | |
| AnnaBridge | 171:3a7713b1edbc | 745 | /** |
| AnnaBridge | 171:3a7713b1edbc | 746 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
| AnnaBridge | 171:3a7713b1edbc | 747 | * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). |
| AnnaBridge | 171:3a7713b1edbc | 748 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 749 | */ |
| AnnaBridge | 171:3a7713b1edbc | 750 | #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 751 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 752 | |
| AnnaBridge | 171:3a7713b1edbc | 753 | #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 754 | |
| AnnaBridge | 171:3a7713b1edbc | 755 | /** |
| AnnaBridge | 171:3a7713b1edbc | 756 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
| AnnaBridge | 171:3a7713b1edbc | 757 | * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) |
| AnnaBridge | 171:3a7713b1edbc | 758 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 759 | */ |
| AnnaBridge | 171:3a7713b1edbc | 760 | #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 761 | |
| AnnaBridge | 171:3a7713b1edbc | 762 | /** |
| AnnaBridge | 171:3a7713b1edbc | 763 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
| AnnaBridge | 171:3a7713b1edbc | 764 | * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) |
| AnnaBridge | 171:3a7713b1edbc | 765 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 766 | */ |
| AnnaBridge | 171:3a7713b1edbc | 767 | #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 768 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 769 | |
| AnnaBridge | 171:3a7713b1edbc | 770 | #if defined(AFIO_MAPR2_TIM12_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 771 | |
| AnnaBridge | 171:3a7713b1edbc | 772 | /** |
| AnnaBridge | 171:3a7713b1edbc | 773 | * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. |
| AnnaBridge | 171:3a7713b1edbc | 774 | * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). |
| AnnaBridge | 171:3a7713b1edbc | 775 | * @note This bit is available only in high density value line devices. |
| AnnaBridge | 171:3a7713b1edbc | 776 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 777 | */ |
| AnnaBridge | 171:3a7713b1edbc | 778 | #define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 779 | |
| AnnaBridge | 171:3a7713b1edbc | 780 | /** |
| AnnaBridge | 171:3a7713b1edbc | 781 | * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. |
| AnnaBridge | 171:3a7713b1edbc | 782 | * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). |
| AnnaBridge | 171:3a7713b1edbc | 783 | * @note This bit is available only in high density value line devices. |
| AnnaBridge | 171:3a7713b1edbc | 784 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 785 | */ |
| AnnaBridge | 171:3a7713b1edbc | 786 | #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 787 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 788 | |
| AnnaBridge | 171:3a7713b1edbc | 789 | #if defined(AFIO_MAPR2_MISC_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 790 | |
| AnnaBridge | 171:3a7713b1edbc | 791 | /** |
| AnnaBridge | 171:3a7713b1edbc | 792 | * @brief Miscellaneous features remapping. |
| AnnaBridge | 171:3a7713b1edbc | 793 | * This bit is set and cleared by software. It controls miscellaneous features. |
| AnnaBridge | 171:3a7713b1edbc | 794 | * The DMA2 channel 5 interrupt position in the vector table. |
| AnnaBridge | 171:3a7713b1edbc | 795 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
| AnnaBridge | 171:3a7713b1edbc | 796 | * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is |
| AnnaBridge | 171:3a7713b1edbc | 797 | * selected as DAC Trigger 3, TIM15 triggers TIM1/3. |
| AnnaBridge | 171:3a7713b1edbc | 798 | * @note This bit is available only in high density value line devices. |
| AnnaBridge | 171:3a7713b1edbc | 799 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 800 | */ |
| AnnaBridge | 171:3a7713b1edbc | 801 | #define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 802 | |
| AnnaBridge | 171:3a7713b1edbc | 803 | /** |
| AnnaBridge | 171:3a7713b1edbc | 804 | * @brief Miscellaneous features remapping. |
| AnnaBridge | 171:3a7713b1edbc | 805 | * This bit is set and cleared by software. It controls miscellaneous features. |
| AnnaBridge | 171:3a7713b1edbc | 806 | * The DMA2 channel 5 interrupt position in the vector table. |
| AnnaBridge | 171:3a7713b1edbc | 807 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
| AnnaBridge | 171:3a7713b1edbc | 808 | * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO |
| AnnaBridge | 171:3a7713b1edbc | 809 | * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. |
| AnnaBridge | 171:3a7713b1edbc | 810 | * @note This bit is available only in high density value line devices. |
| AnnaBridge | 171:3a7713b1edbc | 811 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 812 | */ |
| AnnaBridge | 171:3a7713b1edbc | 813 | #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
| AnnaBridge | 171:3a7713b1edbc | 814 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 815 | |
| AnnaBridge | 171:3a7713b1edbc | 816 | /** |
| AnnaBridge | 171:3a7713b1edbc | 817 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 818 | */ |
| AnnaBridge | 171:3a7713b1edbc | 819 | |
| AnnaBridge | 171:3a7713b1edbc | 820 | /** |
| AnnaBridge | 171:3a7713b1edbc | 821 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 822 | */ |
| AnnaBridge | 171:3a7713b1edbc | 823 | |
| AnnaBridge | 171:3a7713b1edbc | 824 | /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 825 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 826 | */ |
| AnnaBridge | 171:3a7713b1edbc | 827 | #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) |
| AnnaBridge | 171:3a7713b1edbc | 828 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ |
| AnnaBridge | 171:3a7713b1edbc | 829 | ((__GPIOx__) == (GPIOB))? 1U :\ |
| AnnaBridge | 171:3a7713b1edbc | 830 | ((__GPIOx__) == (GPIOC))? 2U :3U) |
| AnnaBridge | 171:3a7713b1edbc | 831 | #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) |
| AnnaBridge | 171:3a7713b1edbc | 832 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ |
| AnnaBridge | 171:3a7713b1edbc | 833 | ((__GPIOx__) == (GPIOB))? 1U :\ |
| AnnaBridge | 171:3a7713b1edbc | 834 | ((__GPIOx__) == (GPIOC))? 2U :\ |
| AnnaBridge | 171:3a7713b1edbc | 835 | ((__GPIOx__) == (GPIOD))? 3U :4U) |
| AnnaBridge | 171:3a7713b1edbc | 836 | #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
| AnnaBridge | 171:3a7713b1edbc | 837 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ |
| AnnaBridge | 171:3a7713b1edbc | 838 | ((__GPIOx__) == (GPIOB))? 1U :\ |
| AnnaBridge | 171:3a7713b1edbc | 839 | ((__GPIOx__) == (GPIOC))? 2U :\ |
| AnnaBridge | 171:3a7713b1edbc | 840 | ((__GPIOx__) == (GPIOD))? 3U :\ |
| AnnaBridge | 171:3a7713b1edbc | 841 | ((__GPIOx__) == (GPIOE))? 4U :\ |
| AnnaBridge | 171:3a7713b1edbc | 842 | ((__GPIOx__) == (GPIOF))? 5U :6U) |
| AnnaBridge | 171:3a7713b1edbc | 843 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 844 | |
| AnnaBridge | 171:3a7713b1edbc | 845 | #define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ |
| AnnaBridge | 171:3a7713b1edbc | 846 | tmpreg |= AFIO_MAPR_SWJ_CFG; \ |
| AnnaBridge | 171:3a7713b1edbc | 847 | tmpreg |= REMAP_PIN; \ |
| AnnaBridge | 171:3a7713b1edbc | 848 | AFIO->MAPR = tmpreg; \ |
| AnnaBridge | 171:3a7713b1edbc | 849 | }while(0U) |
| AnnaBridge | 171:3a7713b1edbc | 850 | |
| AnnaBridge | 171:3a7713b1edbc | 851 | #define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ |
| AnnaBridge | 171:3a7713b1edbc | 852 | tmpreg |= AFIO_MAPR_SWJ_CFG; \ |
| AnnaBridge | 171:3a7713b1edbc | 853 | tmpreg &= ~REMAP_PIN; \ |
| AnnaBridge | 171:3a7713b1edbc | 854 | AFIO->MAPR = tmpreg; \ |
| AnnaBridge | 171:3a7713b1edbc | 855 | }while(0U) |
| AnnaBridge | 171:3a7713b1edbc | 856 | |
| AnnaBridge | 171:3a7713b1edbc | 857 | #define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \ |
| AnnaBridge | 171:3a7713b1edbc | 858 | tmpreg &= ~REMAP_PIN_MASK; \ |
| AnnaBridge | 171:3a7713b1edbc | 859 | tmpreg |= AFIO_MAPR_SWJ_CFG; \ |
| AnnaBridge | 171:3a7713b1edbc | 860 | tmpreg |= REMAP_PIN; \ |
| AnnaBridge | 171:3a7713b1edbc | 861 | AFIO->MAPR = tmpreg; \ |
| AnnaBridge | 171:3a7713b1edbc | 862 | }while(0U) |
| AnnaBridge | 171:3a7713b1edbc | 863 | |
| AnnaBridge | 171:3a7713b1edbc | 864 | #define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \ |
| AnnaBridge | 171:3a7713b1edbc | 865 | tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \ |
| AnnaBridge | 171:3a7713b1edbc | 866 | tmpreg |= DBGAFR_SWJCFG; \ |
| AnnaBridge | 171:3a7713b1edbc | 867 | AFIO->MAPR = tmpreg; \ |
| AnnaBridge | 171:3a7713b1edbc | 868 | }while(0U) |
| AnnaBridge | 171:3a7713b1edbc | 869 | |
| AnnaBridge | 171:3a7713b1edbc | 870 | /** |
| AnnaBridge | 171:3a7713b1edbc | 871 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 872 | */ |
| AnnaBridge | 171:3a7713b1edbc | 873 | |
| AnnaBridge | 171:3a7713b1edbc | 874 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 875 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 876 | |
| AnnaBridge | 171:3a7713b1edbc | 877 | /** @addtogroup GPIOEx_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 878 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 879 | */ |
| AnnaBridge | 171:3a7713b1edbc | 880 | |
| AnnaBridge | 171:3a7713b1edbc | 881 | /** @addtogroup GPIOEx_Exported_Functions_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 882 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 883 | */ |
| AnnaBridge | 171:3a7713b1edbc | 884 | void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource); |
| AnnaBridge | 171:3a7713b1edbc | 885 | void HAL_GPIOEx_EnableEventout(void); |
| AnnaBridge | 171:3a7713b1edbc | 886 | void HAL_GPIOEx_DisableEventout(void); |
| AnnaBridge | 171:3a7713b1edbc | 887 | |
| AnnaBridge | 171:3a7713b1edbc | 888 | /** |
| AnnaBridge | 171:3a7713b1edbc | 889 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 890 | */ |
| AnnaBridge | 171:3a7713b1edbc | 891 | |
| AnnaBridge | 171:3a7713b1edbc | 892 | /** |
| AnnaBridge | 171:3a7713b1edbc | 893 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 894 | */ |
| AnnaBridge | 171:3a7713b1edbc | 895 | |
| AnnaBridge | 171:3a7713b1edbc | 896 | /** |
| AnnaBridge | 171:3a7713b1edbc | 897 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 898 | */ |
| AnnaBridge | 171:3a7713b1edbc | 899 | |
| AnnaBridge | 171:3a7713b1edbc | 900 | /** |
| AnnaBridge | 171:3a7713b1edbc | 901 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 902 | */ |
| AnnaBridge | 171:3a7713b1edbc | 903 | |
| AnnaBridge | 171:3a7713b1edbc | 904 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 905 | } |
| AnnaBridge | 171:3a7713b1edbc | 906 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 907 | |
| AnnaBridge | 171:3a7713b1edbc | 908 | #endif /* __STM32F1xx_HAL_GPIO_EX_H */ |
| AnnaBridge | 171:3a7713b1edbc | 909 | |
| AnnaBridge | 171:3a7713b1edbc | 910 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
