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TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f1xx_hal_flash_ex.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f1xx_hal_flash_ex.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of Flash HAL Extended module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F1xx_HAL_FLASH_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F1xx_HAL_FLASH_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f1xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F1xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 49 | */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup FLASHEx |
| AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 53 | */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | |
| AnnaBridge | 171:3a7713b1edbc | 55 | /** @addtogroup FLASHEx_Private_Constants |
| AnnaBridge | 171:3a7713b1edbc | 56 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 57 | */ |
| AnnaBridge | 171:3a7713b1edbc | 58 | |
| AnnaBridge | 171:3a7713b1edbc | 59 | #define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U |
| AnnaBridge | 171:3a7713b1edbc | 60 | #define OBR_REG_INDEX 1U |
| AnnaBridge | 171:3a7713b1edbc | 61 | #define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP)) |
| AnnaBridge | 171:3a7713b1edbc | 62 | |
| AnnaBridge | 171:3a7713b1edbc | 63 | /** |
| AnnaBridge | 171:3a7713b1edbc | 64 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 65 | */ |
| AnnaBridge | 171:3a7713b1edbc | 66 | |
| AnnaBridge | 171:3a7713b1edbc | 67 | /** @addtogroup FLASHEx_Private_Macros |
| AnnaBridge | 171:3a7713b1edbc | 68 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 69 | */ |
| AnnaBridge | 171:3a7713b1edbc | 70 | |
| AnnaBridge | 171:3a7713b1edbc | 71 | #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE)) |
| AnnaBridge | 171:3a7713b1edbc | 72 | |
| AnnaBridge | 171:3a7713b1edbc | 73 | #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) |
| AnnaBridge | 171:3a7713b1edbc | 74 | |
| AnnaBridge | 171:3a7713b1edbc | 75 | #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 76 | |
| AnnaBridge | 171:3a7713b1edbc | 77 | #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) |
| AnnaBridge | 171:3a7713b1edbc | 78 | |
| AnnaBridge | 171:3a7713b1edbc | 79 | #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) |
| AnnaBridge | 171:3a7713b1edbc | 80 | |
| AnnaBridge | 171:3a7713b1edbc | 81 | #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) |
| AnnaBridge | 171:3a7713b1edbc | 82 | |
| AnnaBridge | 171:3a7713b1edbc | 83 | #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) |
| AnnaBridge | 171:3a7713b1edbc | 84 | |
| AnnaBridge | 171:3a7713b1edbc | 85 | #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) |
| AnnaBridge | 171:3a7713b1edbc | 86 | |
| AnnaBridge | 171:3a7713b1edbc | 87 | #if defined(FLASH_BANK2_END) |
| AnnaBridge | 171:3a7713b1edbc | 88 | #define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) |
| AnnaBridge | 171:3a7713b1edbc | 89 | #endif /* FLASH_BANK2_END */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | |
| AnnaBridge | 171:3a7713b1edbc | 91 | /* Low Density */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \ |
| AnnaBridge | 171:3a7713b1edbc | 94 | ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU)) |
| AnnaBridge | 171:3a7713b1edbc | 95 | #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | |
| AnnaBridge | 171:3a7713b1edbc | 97 | /* Medium Density */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ |
| AnnaBridge | 171:3a7713b1edbc | 100 | (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \ |
| AnnaBridge | 171:3a7713b1edbc | 101 | (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \ |
| AnnaBridge | 171:3a7713b1edbc | 102 | ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU)))) |
| AnnaBridge | 171:3a7713b1edbc | 103 | #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ |
| AnnaBridge | 171:3a7713b1edbc | 104 | |
| AnnaBridge | 171:3a7713b1edbc | 105 | /* High Density */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \ |
| AnnaBridge | 171:3a7713b1edbc | 108 | (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \ |
| AnnaBridge | 171:3a7713b1edbc | 109 | ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU))) |
| AnnaBridge | 171:3a7713b1edbc | 110 | #endif /* STM32F100xE || STM32F101xE || STM32F103xE */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | |
| AnnaBridge | 171:3a7713b1edbc | 112 | /* XL Density */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | #if defined(FLASH_BANK2_END) |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \ |
| AnnaBridge | 171:3a7713b1edbc | 115 | ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU)) |
| AnnaBridge | 171:3a7713b1edbc | 116 | #endif /* FLASH_BANK2_END */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | |
| AnnaBridge | 171:3a7713b1edbc | 118 | /* Connectivity Line */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | #if (defined(STM32F105xC) || defined(STM32F107xC)) |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \ |
| AnnaBridge | 171:3a7713b1edbc | 121 | (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ |
| AnnaBridge | 171:3a7713b1edbc | 122 | ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU))) |
| AnnaBridge | 171:3a7713b1edbc | 123 | #endif /* STM32F105xC || STM32F107xC */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) |
| AnnaBridge | 171:3a7713b1edbc | 126 | |
| AnnaBridge | 171:3a7713b1edbc | 127 | #if defined(FLASH_BANK2_END) |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 129 | ((BANK) == FLASH_BANK_2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 130 | ((BANK) == FLASH_BANK_BOTH)) |
| AnnaBridge | 171:3a7713b1edbc | 131 | #else |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) |
| AnnaBridge | 171:3a7713b1edbc | 133 | #endif /* FLASH_BANK2_END */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | |
| AnnaBridge | 171:3a7713b1edbc | 135 | /* Low Density */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 138 | ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU))) |
| AnnaBridge | 171:3a7713b1edbc | 139 | |
| AnnaBridge | 171:3a7713b1edbc | 140 | #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | |
| AnnaBridge | 171:3a7713b1edbc | 142 | /* Medium Density */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 145 | ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 146 | ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 147 | ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) |
| AnnaBridge | 171:3a7713b1edbc | 148 | |
| AnnaBridge | 171:3a7713b1edbc | 149 | #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ |
| AnnaBridge | 171:3a7713b1edbc | 150 | |
| AnnaBridge | 171:3a7713b1edbc | 151 | /* High Density */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 154 | ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 155 | ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) |
| AnnaBridge | 171:3a7713b1edbc | 156 | |
| AnnaBridge | 171:3a7713b1edbc | 157 | #endif /* STM32F100xE || STM32F101xE || STM32F103xE */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | |
| AnnaBridge | 171:3a7713b1edbc | 159 | /* XL Density */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | #if defined(FLASH_BANK2_END) |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 162 | ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU))) |
| AnnaBridge | 171:3a7713b1edbc | 163 | |
| AnnaBridge | 171:3a7713b1edbc | 164 | #endif /* FLASH_BANK2_END */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | |
| AnnaBridge | 171:3a7713b1edbc | 166 | /* Connectivity Line */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #if (defined(STM32F105xC) || defined(STM32F107xC)) |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 169 | ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 170 | ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) |
| AnnaBridge | 171:3a7713b1edbc | 171 | |
| AnnaBridge | 171:3a7713b1edbc | 172 | #endif /* STM32F105xC || STM32F107xC */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | |
| AnnaBridge | 171:3a7713b1edbc | 174 | /** |
| AnnaBridge | 171:3a7713b1edbc | 175 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 176 | */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | |
| AnnaBridge | 171:3a7713b1edbc | 178 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 179 | /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 180 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 181 | */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | |
| AnnaBridge | 171:3a7713b1edbc | 183 | /** |
| AnnaBridge | 171:3a7713b1edbc | 184 | * @brief FLASH Erase structure definition |
| AnnaBridge | 171:3a7713b1edbc | 185 | */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 187 | { |
| AnnaBridge | 171:3a7713b1edbc | 188 | uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. |
| AnnaBridge | 171:3a7713b1edbc | 189 | This parameter can be a value of @ref FLASHEx_Type_Erase */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | |
| AnnaBridge | 171:3a7713b1edbc | 191 | uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. |
| AnnaBridge | 171:3a7713b1edbc | 192 | This parameter must be a value of @ref FLASHEx_Banks */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | |
| AnnaBridge | 171:3a7713b1edbc | 194 | uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled |
| AnnaBridge | 171:3a7713b1edbc | 195 | This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END |
| AnnaBridge | 171:3a7713b1edbc | 196 | (x = 1 or 2 depending on devices)*/ |
| AnnaBridge | 171:3a7713b1edbc | 197 | |
| AnnaBridge | 171:3a7713b1edbc | 198 | uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. |
| AnnaBridge | 171:3a7713b1edbc | 199 | This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ |
| AnnaBridge | 171:3a7713b1edbc | 200 | |
| AnnaBridge | 171:3a7713b1edbc | 201 | } FLASH_EraseInitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 202 | |
| AnnaBridge | 171:3a7713b1edbc | 203 | /** |
| AnnaBridge | 171:3a7713b1edbc | 204 | * @brief FLASH Options bytes program structure definition |
| AnnaBridge | 171:3a7713b1edbc | 205 | */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 207 | { |
| AnnaBridge | 171:3a7713b1edbc | 208 | uint32_t OptionType; /*!< OptionType: Option byte to be configured. |
| AnnaBridge | 171:3a7713b1edbc | 209 | This parameter can be a value of @ref FLASHEx_OB_Type */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | |
| AnnaBridge | 171:3a7713b1edbc | 211 | uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. |
| AnnaBridge | 171:3a7713b1edbc | 212 | This parameter can be a value of @ref FLASHEx_OB_WRP_State */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | |
| AnnaBridge | 171:3a7713b1edbc | 214 | uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected |
| AnnaBridge | 171:3a7713b1edbc | 215 | This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | |
| AnnaBridge | 171:3a7713b1edbc | 217 | uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. |
| AnnaBridge | 171:3a7713b1edbc | 218 | This parameter must be a value of @ref FLASHEx_Banks */ |
| AnnaBridge | 171:3a7713b1edbc | 219 | |
| AnnaBridge | 171:3a7713b1edbc | 220 | uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. |
| AnnaBridge | 171:3a7713b1edbc | 221 | This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | |
| AnnaBridge | 171:3a7713b1edbc | 223 | #if defined(FLASH_BANK2_END) |
| AnnaBridge | 171:3a7713b1edbc | 224 | uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: |
| AnnaBridge | 171:3a7713b1edbc | 225 | IWDG / STOP / STDBY / BOOT1 |
| AnnaBridge | 171:3a7713b1edbc | 226 | This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, |
| AnnaBridge | 171:3a7713b1edbc | 227 | @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #else |
| AnnaBridge | 171:3a7713b1edbc | 229 | uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: |
| AnnaBridge | 171:3a7713b1edbc | 230 | IWDG / STOP / STDBY |
| AnnaBridge | 171:3a7713b1edbc | 231 | This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, |
| AnnaBridge | 171:3a7713b1edbc | 232 | @ref FLASHEx_OB_nRST_STDBY */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #endif /* FLASH_BANK2_END */ |
| AnnaBridge | 171:3a7713b1edbc | 234 | |
| AnnaBridge | 171:3a7713b1edbc | 235 | uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed |
| AnnaBridge | 171:3a7713b1edbc | 236 | This parameter can be a value of @ref FLASHEx_OB_Data_Address */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | |
| AnnaBridge | 171:3a7713b1edbc | 238 | uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA |
| AnnaBridge | 171:3a7713b1edbc | 239 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | } FLASH_OBProgramInitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 241 | |
| AnnaBridge | 171:3a7713b1edbc | 242 | /** |
| AnnaBridge | 171:3a7713b1edbc | 243 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 244 | */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | |
| AnnaBridge | 171:3a7713b1edbc | 246 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 247 | /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 248 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 249 | */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | |
| AnnaBridge | 171:3a7713b1edbc | 251 | /** @defgroup FLASHEx_Constants FLASH Constants |
| AnnaBridge | 171:3a7713b1edbc | 252 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 253 | */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | |
| AnnaBridge | 171:3a7713b1edbc | 255 | /** @defgroup FLASHEx_Page_Size Page Size |
| AnnaBridge | 171:3a7713b1edbc | 256 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 257 | */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define FLASH_PAGE_SIZE 0x400U |
| AnnaBridge | 171:3a7713b1edbc | 260 | #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | |
| AnnaBridge | 171:3a7713b1edbc | 263 | #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define FLASH_PAGE_SIZE 0x800U |
| AnnaBridge | 171:3a7713b1edbc | 265 | #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | /* STM32F101xG || STM32F103xG */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | /* STM32F105xC || STM32F107xC */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | |
| AnnaBridge | 171:3a7713b1edbc | 269 | /** |
| AnnaBridge | 171:3a7713b1edbc | 270 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 271 | */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | |
| AnnaBridge | 171:3a7713b1edbc | 273 | /** @defgroup FLASHEx_Type_Erase Type Erase |
| AnnaBridge | 171:3a7713b1edbc | 274 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 275 | */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/ |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define FLASH_TYPEERASE_MASSERASE 0x02U /*!<Flash mass erase activation*/ |
| AnnaBridge | 171:3a7713b1edbc | 278 | |
| AnnaBridge | 171:3a7713b1edbc | 279 | /** |
| AnnaBridge | 171:3a7713b1edbc | 280 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 281 | */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | |
| AnnaBridge | 171:3a7713b1edbc | 283 | /** @defgroup FLASHEx_Banks Banks |
| AnnaBridge | 171:3a7713b1edbc | 284 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 285 | */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | #if defined(FLASH_BANK2_END) |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define FLASH_BANK_1 1U /*!< Bank 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define FLASH_BANK_2 2U /*!< Bank 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | |
| AnnaBridge | 171:3a7713b1edbc | 291 | #else |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define FLASH_BANK_1 1U /*!< Bank 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 294 | /** |
| AnnaBridge | 171:3a7713b1edbc | 295 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 296 | */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | |
| AnnaBridge | 171:3a7713b1edbc | 298 | /** |
| AnnaBridge | 171:3a7713b1edbc | 299 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 300 | */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | |
| AnnaBridge | 171:3a7713b1edbc | 302 | /** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants |
| AnnaBridge | 171:3a7713b1edbc | 303 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 304 | */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | |
| AnnaBridge | 171:3a7713b1edbc | 306 | /** @defgroup FLASHEx_OB_Type Option Bytes Type |
| AnnaBridge | 171:3a7713b1edbc | 307 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 308 | */ |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define OPTIONBYTE_WRP 0x01U /*!<WRP option byte configuration*/ |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define OPTIONBYTE_RDP 0x02U /*!<RDP option byte configuration*/ |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define OPTIONBYTE_USER 0x04U /*!<USER option byte configuration*/ |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define OPTIONBYTE_DATA 0x08U /*!<DATA option byte configuration*/ |
| AnnaBridge | 171:3a7713b1edbc | 313 | |
| AnnaBridge | 171:3a7713b1edbc | 314 | /** |
| AnnaBridge | 171:3a7713b1edbc | 315 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 316 | */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | |
| AnnaBridge | 171:3a7713b1edbc | 318 | /** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State |
| AnnaBridge | 171:3a7713b1edbc | 319 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 320 | */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define OB_WRPSTATE_DISABLE 0x00U /*!<Disable the write protection of the desired pages*/ |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define OB_WRPSTATE_ENABLE 0x01U /*!<Enable the write protection of the desired pagess*/ |
| AnnaBridge | 171:3a7713b1edbc | 323 | |
| AnnaBridge | 171:3a7713b1edbc | 324 | /** |
| AnnaBridge | 171:3a7713b1edbc | 325 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 326 | */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | |
| AnnaBridge | 171:3a7713b1edbc | 328 | /** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection |
| AnnaBridge | 171:3a7713b1edbc | 329 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 330 | */ |
| AnnaBridge | 171:3a7713b1edbc | 331 | /* STM32 Low and Medium density devices */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \ |
| AnnaBridge | 171:3a7713b1edbc | 333 | || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \ |
| AnnaBridge | 171:3a7713b1edbc | 334 | || defined(STM32F103xB) |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */ |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define OB_WRP_PAGES12TO15 0x00000008U /*!< Write protection of page 12 to 15 */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define OB_WRP_PAGES16TO19 0x00000010U /*!< Write protection of page 16 to 19 */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define OB_WRP_PAGES20TO23 0x00000020U /*!< Write protection of page 20 to 23 */ |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define OB_WRP_PAGES24TO27 0x00000040U /*!< Write protection of page 24 to 27 */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | #define OB_WRP_PAGES28TO31 0x00000080U /*!< Write protection of page 28 to 31 */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
| AnnaBridge | 171:3a7713b1edbc | 345 | |
| AnnaBridge | 171:3a7713b1edbc | 346 | /* STM32 Medium-density devices */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | #if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define OB_WRP_PAGES32TO35 0x00000100U /*!< Write protection of page 32 to 35 */ |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define OB_WRP_PAGES36TO39 0x00000200U /*!< Write protection of page 36 to 39 */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define OB_WRP_PAGES40TO43 0x00000400U /*!< Write protection of page 40 to 43 */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define OB_WRP_PAGES44TO47 0x00000800U /*!< Write protection of page 44 to 47 */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define OB_WRP_PAGES48TO51 0x00001000U /*!< Write protection of page 48 to 51 */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define OB_WRP_PAGES52TO55 0x00002000U /*!< Write protection of page 52 to 55 */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define OB_WRP_PAGES56TO59 0x00004000U /*!< Write protection of page 56 to 59 */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define OB_WRP_PAGES60TO63 0x00008000U /*!< Write protection of page 60 to 63 */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define OB_WRP_PAGES64TO67 0x00010000U /*!< Write protection of page 64 to 67 */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define OB_WRP_PAGES68TO71 0x00020000U /*!< Write protection of page 68 to 71 */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define OB_WRP_PAGES72TO75 0x00040000U /*!< Write protection of page 72 to 75 */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define OB_WRP_PAGES76TO79 0x00080000U /*!< Write protection of page 76 to 79 */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define OB_WRP_PAGES80TO83 0x00100000U /*!< Write protection of page 80 to 83 */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define OB_WRP_PAGES84TO87 0x00200000U /*!< Write protection of page 84 to 87 */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define OB_WRP_PAGES88TO91 0x00400000U /*!< Write protection of page 88 to 91 */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define OB_WRP_PAGES92TO95 0x00800000U /*!< Write protection of page 92 to 95 */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define OB_WRP_PAGES96TO99 0x01000000U /*!< Write protection of page 96 to 99 */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define OB_WRP_PAGES100TO103 0x02000000U /*!< Write protection of page 100 to 103 */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define OB_WRP_PAGES104TO107 0x04000000U /*!< Write protection of page 104 to 107 */ |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define OB_WRP_PAGES108TO111 0x08000000U /*!< Write protection of page 108 to 111 */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define OB_WRP_PAGES112TO115 0x10000000U /*!< Write protection of page 112 to 115 */ |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define OB_WRP_PAGES116TO119 0x20000000U /*!< Write protection of page 115 to 119 */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define OB_WRP_PAGES120TO123 0x40000000U /*!< Write protection of page 120 to 123 */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */ |
| AnnaBridge | 171:3a7713b1edbc | 372 | #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | |
| AnnaBridge | 171:3a7713b1edbc | 374 | |
| AnnaBridge | 171:3a7713b1edbc | 375 | /* STM32 High-density, XL-density and Connectivity line devices */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \ |
| AnnaBridge | 171:3a7713b1edbc | 377 | || defined(STM32F101xG) || defined(STM32F103xG) \ |
| AnnaBridge | 171:3a7713b1edbc | 378 | || defined(STM32F105xC) || defined(STM32F107xC) |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */ |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define OB_WRP_PAGES6TO7 0x00000008U /*!< Write protection of page 6 TO 7 */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define OB_WRP_PAGES8TO9 0x00000010U /*!< Write protection of page 8 TO 9 */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define OB_WRP_PAGES10TO11 0x00000020U /*!< Write protection of page 10 TO 11 */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define OB_WRP_PAGES12TO13 0x00000040U /*!< Write protection of page 12 TO 13 */ |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define OB_WRP_PAGES14TO15 0x00000080U /*!< Write protection of page 14 TO 15 */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define OB_WRP_PAGES16TO17 0x00000100U /*!< Write protection of page 16 TO 17 */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define OB_WRP_PAGES18TO19 0x00000200U /*!< Write protection of page 18 TO 19 */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define OB_WRP_PAGES20TO21 0x00000400U /*!< Write protection of page 20 TO 21 */ |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define OB_WRP_PAGES22TO23 0x00000800U /*!< Write protection of page 22 TO 23 */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define OB_WRP_PAGES24TO25 0x00001000U /*!< Write protection of page 24 TO 25 */ |
| AnnaBridge | 171:3a7713b1edbc | 392 | #define OB_WRP_PAGES26TO27 0x00002000U /*!< Write protection of page 26 TO 27 */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | #define OB_WRP_PAGES28TO29 0x00004000U /*!< Write protection of page 28 TO 29 */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define OB_WRP_PAGES30TO31 0x00008000U /*!< Write protection of page 30 TO 31 */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define OB_WRP_PAGES32TO33 0x00010000U /*!< Write protection of page 32 TO 33 */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define OB_WRP_PAGES34TO35 0x00020000U /*!< Write protection of page 34 TO 35 */ |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define OB_WRP_PAGES36TO37 0x00040000U /*!< Write protection of page 36 TO 37 */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define OB_WRP_PAGES38TO39 0x00080000U /*!< Write protection of page 38 TO 39 */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define OB_WRP_PAGES40TO41 0x00100000U /*!< Write protection of page 40 TO 41 */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define OB_WRP_PAGES42TO43 0x00200000U /*!< Write protection of page 42 TO 43 */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define OB_WRP_PAGES44TO45 0x00400000U /*!< Write protection of page 44 TO 45 */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define OB_WRP_PAGES46TO47 0x00800000U /*!< Write protection of page 46 TO 47 */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define OB_WRP_PAGES48TO49 0x01000000U /*!< Write protection of page 48 TO 49 */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define OB_WRP_PAGES50TO51 0x02000000U /*!< Write protection of page 50 TO 51 */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define OB_WRP_PAGES52TO53 0x04000000U /*!< Write protection of page 52 TO 53 */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define OB_WRP_PAGES54TO55 0x08000000U /*!< Write protection of page 54 TO 55 */ |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define OB_WRP_PAGES56TO57 0x10000000U /*!< Write protection of page 56 TO 57 */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define OB_WRP_PAGES58TO59 0x20000000U /*!< Write protection of page 58 TO 59 */ |
| AnnaBridge | 171:3a7713b1edbc | 409 | #define OB_WRP_PAGES60TO61 0x40000000U /*!< Write protection of page 60 TO 61 */ |
| AnnaBridge | 171:3a7713b1edbc | 410 | #define OB_WRP_PAGES62TO127 0x80000000U /*!< Write protection of page 62 TO 127 */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define OB_WRP_PAGES62TO255 0x80000000U /*!< Write protection of page 62 TO 255 */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define OB_WRP_PAGES62TO511 0x80000000U /*!< Write protection of page 62 TO 511 */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | /* STM32F101xG || STM32F103xG */ |
| AnnaBridge | 171:3a7713b1edbc | 415 | /* STM32F105xC || STM32F107xC */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define OB_WRP_ALLPAGES 0xFFFFFFFFU /*!< Write protection of all Pages */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | |
| AnnaBridge | 171:3a7713b1edbc | 419 | /* Low Density */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) |
| AnnaBridge | 171:3a7713b1edbc | 421 | #define OB_WRP_PAGES0TO31MASK 0x000000FFU |
| AnnaBridge | 171:3a7713b1edbc | 422 | #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
| AnnaBridge | 171:3a7713b1edbc | 423 | |
| AnnaBridge | 171:3a7713b1edbc | 424 | /* Medium Density */ |
| AnnaBridge | 171:3a7713b1edbc | 425 | #if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) |
| AnnaBridge | 171:3a7713b1edbc | 426 | #define OB_WRP_PAGES0TO31MASK 0x000000FFU |
| AnnaBridge | 171:3a7713b1edbc | 427 | #define OB_WRP_PAGES32TO63MASK 0x0000FF00U |
| AnnaBridge | 171:3a7713b1edbc | 428 | #define OB_WRP_PAGES64TO95MASK 0x00FF0000U |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define OB_WRP_PAGES96TO127MASK 0xFF000000U |
| AnnaBridge | 171:3a7713b1edbc | 430 | #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ |
| AnnaBridge | 171:3a7713b1edbc | 431 | |
| AnnaBridge | 171:3a7713b1edbc | 432 | /* High Density */ |
| AnnaBridge | 171:3a7713b1edbc | 433 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) |
| AnnaBridge | 171:3a7713b1edbc | 434 | #define OB_WRP_PAGES0TO15MASK 0x000000FFU |
| AnnaBridge | 171:3a7713b1edbc | 435 | #define OB_WRP_PAGES16TO31MASK 0x0000FF00U |
| AnnaBridge | 171:3a7713b1edbc | 436 | #define OB_WRP_PAGES32TO47MASK 0x00FF0000U |
| AnnaBridge | 171:3a7713b1edbc | 437 | #define OB_WRP_PAGES48TO255MASK 0xFF000000U |
| AnnaBridge | 171:3a7713b1edbc | 438 | #endif /* STM32F100xE || STM32F101xE || STM32F103xE */ |
| AnnaBridge | 171:3a7713b1edbc | 439 | |
| AnnaBridge | 171:3a7713b1edbc | 440 | /* XL Density */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | #if defined(STM32F101xG) || defined(STM32F103xG) |
| AnnaBridge | 171:3a7713b1edbc | 442 | #define OB_WRP_PAGES0TO15MASK 0x000000FFU |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define OB_WRP_PAGES16TO31MASK 0x0000FF00U |
| AnnaBridge | 171:3a7713b1edbc | 444 | #define OB_WRP_PAGES32TO47MASK 0x00FF0000U |
| AnnaBridge | 171:3a7713b1edbc | 445 | #define OB_WRP_PAGES48TO511MASK 0xFF000000U |
| AnnaBridge | 171:3a7713b1edbc | 446 | #endif /* STM32F101xG || STM32F103xG */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | |
| AnnaBridge | 171:3a7713b1edbc | 448 | /* Connectivity line devices */ |
| AnnaBridge | 171:3a7713b1edbc | 449 | #if defined(STM32F105xC) || defined(STM32F107xC) |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define OB_WRP_PAGES0TO15MASK 0x000000FFU |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define OB_WRP_PAGES16TO31MASK 0x0000FF00U |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define OB_WRP_PAGES32TO47MASK 0x00FF0000U |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define OB_WRP_PAGES48TO127MASK 0xFF000000U |
| AnnaBridge | 171:3a7713b1edbc | 454 | #endif /* STM32F105xC || STM32F107xC */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | |
| AnnaBridge | 171:3a7713b1edbc | 456 | /** |
| AnnaBridge | 171:3a7713b1edbc | 457 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 458 | */ |
| AnnaBridge | 171:3a7713b1edbc | 459 | |
| AnnaBridge | 171:3a7713b1edbc | 460 | /** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection |
| AnnaBridge | 171:3a7713b1edbc | 461 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 462 | */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define OB_RDP_LEVEL_0 ((uint8_t)0xA5) |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define OB_RDP_LEVEL_1 ((uint8_t)0x00) |
| AnnaBridge | 171:3a7713b1edbc | 465 | /** |
| AnnaBridge | 171:3a7713b1edbc | 466 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 467 | */ |
| AnnaBridge | 171:3a7713b1edbc | 468 | |
| AnnaBridge | 171:3a7713b1edbc | 469 | /** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog |
| AnnaBridge | 171:3a7713b1edbc | 470 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 471 | */ |
| AnnaBridge | 171:3a7713b1edbc | 472 | #define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ |
| AnnaBridge | 171:3a7713b1edbc | 473 | #define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ |
| AnnaBridge | 171:3a7713b1edbc | 474 | /** |
| AnnaBridge | 171:3a7713b1edbc | 475 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 476 | */ |
| AnnaBridge | 171:3a7713b1edbc | 477 | |
| AnnaBridge | 171:3a7713b1edbc | 478 | /** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP |
| AnnaBridge | 171:3a7713b1edbc | 479 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 480 | */ |
| AnnaBridge | 171:3a7713b1edbc | 481 | #define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 482 | #define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 483 | /** |
| AnnaBridge | 171:3a7713b1edbc | 484 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 485 | */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | |
| AnnaBridge | 171:3a7713b1edbc | 487 | /** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY |
| AnnaBridge | 171:3a7713b1edbc | 488 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 489 | */ |
| AnnaBridge | 171:3a7713b1edbc | 490 | #define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ |
| AnnaBridge | 171:3a7713b1edbc | 491 | #define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ |
| AnnaBridge | 171:3a7713b1edbc | 492 | /** |
| AnnaBridge | 171:3a7713b1edbc | 493 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 494 | */ |
| AnnaBridge | 171:3a7713b1edbc | 495 | |
| AnnaBridge | 171:3a7713b1edbc | 496 | #if defined(FLASH_BANK2_END) |
| AnnaBridge | 171:3a7713b1edbc | 497 | /** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1 |
| AnnaBridge | 171:3a7713b1edbc | 498 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 499 | */ |
| AnnaBridge | 171:3a7713b1edbc | 500 | #define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */ |
| AnnaBridge | 171:3a7713b1edbc | 501 | #define OB_BOOT1_SET ((uint16_t)0x0008) /*!< BOOT1 Set */ |
| AnnaBridge | 171:3a7713b1edbc | 502 | /** |
| AnnaBridge | 171:3a7713b1edbc | 503 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 504 | */ |
| AnnaBridge | 171:3a7713b1edbc | 505 | #endif /* FLASH_BANK2_END */ |
| AnnaBridge | 171:3a7713b1edbc | 506 | |
| AnnaBridge | 171:3a7713b1edbc | 507 | /** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address |
| AnnaBridge | 171:3a7713b1edbc | 508 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 509 | */ |
| AnnaBridge | 171:3a7713b1edbc | 510 | #define OB_DATA_ADDRESS_DATA0 0x1FFFF804U |
| AnnaBridge | 171:3a7713b1edbc | 511 | #define OB_DATA_ADDRESS_DATA1 0x1FFFF806U |
| AnnaBridge | 171:3a7713b1edbc | 512 | /** |
| AnnaBridge | 171:3a7713b1edbc | 513 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 514 | */ |
| AnnaBridge | 171:3a7713b1edbc | 515 | |
| AnnaBridge | 171:3a7713b1edbc | 516 | /** |
| AnnaBridge | 171:3a7713b1edbc | 517 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 518 | */ |
| AnnaBridge | 171:3a7713b1edbc | 519 | |
| AnnaBridge | 171:3a7713b1edbc | 520 | /** @addtogroup FLASHEx_Constants |
| AnnaBridge | 171:3a7713b1edbc | 521 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 522 | */ |
| AnnaBridge | 171:3a7713b1edbc | 523 | |
| AnnaBridge | 171:3a7713b1edbc | 524 | /** @defgroup FLASH_Flag_definition Flag definition |
| AnnaBridge | 171:3a7713b1edbc | 525 | * @brief Flag definition |
| AnnaBridge | 171:3a7713b1edbc | 526 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 527 | */ |
| AnnaBridge | 171:3a7713b1edbc | 528 | #if defined(FLASH_BANK2_END) |
| AnnaBridge | 171:3a7713b1edbc | 529 | #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */ |
| AnnaBridge | 171:3a7713b1edbc | 530 | #define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */ |
| AnnaBridge | 171:3a7713b1edbc | 531 | #define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */ |
| AnnaBridge | 171:3a7713b1edbc | 532 | #define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */ |
| AnnaBridge | 171:3a7713b1edbc | 533 | |
| AnnaBridge | 171:3a7713b1edbc | 534 | #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */ |
| AnnaBridge | 171:3a7713b1edbc | 535 | #define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */ |
| AnnaBridge | 171:3a7713b1edbc | 536 | #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */ |
| AnnaBridge | 171:3a7713b1edbc | 538 | |
| AnnaBridge | 171:3a7713b1edbc | 539 | #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16U) /*!< FLASH Bank2 Busy flag */ |
| AnnaBridge | 171:3a7713b1edbc | 540 | #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16U) /*!< FLASH Bank2 Programming error flag */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag */ |
| AnnaBridge | 171:3a7713b1edbc | 542 | #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16U) /*!< FLASH Bank2 End of Operation flag */ |
| AnnaBridge | 171:3a7713b1edbc | 543 | |
| AnnaBridge | 171:3a7713b1edbc | 544 | #else |
| AnnaBridge | 171:3a7713b1edbc | 545 | |
| AnnaBridge | 171:3a7713b1edbc | 546 | #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ |
| AnnaBridge | 171:3a7713b1edbc | 547 | #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */ |
| AnnaBridge | 171:3a7713b1edbc | 548 | #define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */ |
| AnnaBridge | 171:3a7713b1edbc | 549 | #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ |
| AnnaBridge | 171:3a7713b1edbc | 550 | |
| AnnaBridge | 171:3a7713b1edbc | 551 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 552 | #define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error */ |
| AnnaBridge | 171:3a7713b1edbc | 553 | /** |
| AnnaBridge | 171:3a7713b1edbc | 554 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 555 | */ |
| AnnaBridge | 171:3a7713b1edbc | 556 | |
| AnnaBridge | 171:3a7713b1edbc | 557 | /** @defgroup FLASH_Interrupt_definition Interrupt definition |
| AnnaBridge | 171:3a7713b1edbc | 558 | * @brief FLASH Interrupt definition |
| AnnaBridge | 171:3a7713b1edbc | 559 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 560 | */ |
| AnnaBridge | 171:3a7713b1edbc | 561 | #if defined(FLASH_BANK2_END) |
| AnnaBridge | 171:3a7713b1edbc | 562 | #define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */ |
| AnnaBridge | 171:3a7713b1edbc | 563 | #define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */ |
| AnnaBridge | 171:3a7713b1edbc | 564 | |
| AnnaBridge | 171:3a7713b1edbc | 565 | #define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | #define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */ |
| AnnaBridge | 171:3a7713b1edbc | 567 | |
| AnnaBridge | 171:3a7713b1edbc | 568 | #define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */ |
| AnnaBridge | 171:3a7713b1edbc | 569 | #define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2 */ |
| AnnaBridge | 171:3a7713b1edbc | 570 | |
| AnnaBridge | 171:3a7713b1edbc | 571 | #else |
| AnnaBridge | 171:3a7713b1edbc | 572 | |
| AnnaBridge | 171:3a7713b1edbc | 573 | #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | #define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */ |
| AnnaBridge | 171:3a7713b1edbc | 575 | |
| AnnaBridge | 171:3a7713b1edbc | 576 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 577 | /** |
| AnnaBridge | 171:3a7713b1edbc | 578 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 579 | */ |
| AnnaBridge | 171:3a7713b1edbc | 580 | |
| AnnaBridge | 171:3a7713b1edbc | 581 | /** |
| AnnaBridge | 171:3a7713b1edbc | 582 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 583 | */ |
| AnnaBridge | 171:3a7713b1edbc | 584 | |
| AnnaBridge | 171:3a7713b1edbc | 585 | |
| AnnaBridge | 171:3a7713b1edbc | 586 | /** |
| AnnaBridge | 171:3a7713b1edbc | 587 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 588 | */ |
| AnnaBridge | 171:3a7713b1edbc | 589 | |
| AnnaBridge | 171:3a7713b1edbc | 590 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 591 | /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 592 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 593 | */ |
| AnnaBridge | 171:3a7713b1edbc | 594 | |
| AnnaBridge | 171:3a7713b1edbc | 595 | /** @defgroup FLASH_Interrupt Interrupt |
| AnnaBridge | 171:3a7713b1edbc | 596 | * @brief macros to handle FLASH interrupts |
| AnnaBridge | 171:3a7713b1edbc | 597 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 598 | */ |
| AnnaBridge | 171:3a7713b1edbc | 599 | |
| AnnaBridge | 171:3a7713b1edbc | 600 | #if defined(FLASH_BANK2_END) |
| AnnaBridge | 171:3a7713b1edbc | 601 | /** |
| AnnaBridge | 171:3a7713b1edbc | 602 | * @brief Enable the specified FLASH interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 603 | * @param __INTERRUPT__ FLASH interrupt |
| AnnaBridge | 171:3a7713b1edbc | 604 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 605 | * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 606 | * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 607 | * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 608 | * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 609 | * @retval none |
| AnnaBridge | 171:3a7713b1edbc | 610 | */ |
| AnnaBridge | 171:3a7713b1edbc | 611 | #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \ |
| AnnaBridge | 171:3a7713b1edbc | 612 | /* Enable Bank1 IT */ \ |
| AnnaBridge | 171:3a7713b1edbc | 613 | SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ |
| AnnaBridge | 171:3a7713b1edbc | 614 | /* Enable Bank2 IT */ \ |
| AnnaBridge | 171:3a7713b1edbc | 615 | SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ |
| AnnaBridge | 171:3a7713b1edbc | 616 | } while(0U) |
| AnnaBridge | 171:3a7713b1edbc | 617 | |
| AnnaBridge | 171:3a7713b1edbc | 618 | /** |
| AnnaBridge | 171:3a7713b1edbc | 619 | * @brief Disable the specified FLASH interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 620 | * @param __INTERRUPT__ FLASH interrupt |
| AnnaBridge | 171:3a7713b1edbc | 621 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 622 | * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 623 | * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 624 | * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 625 | * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 626 | * @retval none |
| AnnaBridge | 171:3a7713b1edbc | 627 | */ |
| AnnaBridge | 171:3a7713b1edbc | 628 | #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ |
| AnnaBridge | 171:3a7713b1edbc | 629 | /* Disable Bank1 IT */ \ |
| AnnaBridge | 171:3a7713b1edbc | 630 | CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ |
| AnnaBridge | 171:3a7713b1edbc | 631 | /* Disable Bank2 IT */ \ |
| AnnaBridge | 171:3a7713b1edbc | 632 | CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ |
| AnnaBridge | 171:3a7713b1edbc | 633 | } while(0U) |
| AnnaBridge | 171:3a7713b1edbc | 634 | |
| AnnaBridge | 171:3a7713b1edbc | 635 | /** |
| AnnaBridge | 171:3a7713b1edbc | 636 | * @brief Get the specified FLASH flag status. |
| AnnaBridge | 171:3a7713b1edbc | 637 | * @param __FLAG__ specifies the FLASH flag to check. |
| AnnaBridge | 171:3a7713b1edbc | 638 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 639 | * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 640 | * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 641 | * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 642 | * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 643 | * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 644 | * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 645 | * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 646 | * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 647 | * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
| AnnaBridge | 171:3a7713b1edbc | 648 | * @retval The new state of __FLAG__ (SET or RESET). |
| AnnaBridge | 171:3a7713b1edbc | 649 | */ |
| AnnaBridge | 171:3a7713b1edbc | 650 | #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 651 | (FLASH->OBR & FLASH_OBR_OPTERR) : \ |
| AnnaBridge | 171:3a7713b1edbc | 652 | ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \ |
| AnnaBridge | 171:3a7713b1edbc | 653 | (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \ |
| AnnaBridge | 171:3a7713b1edbc | 654 | (FLASH->SR2 & ((__FLAG__) >> 16U)))) |
| AnnaBridge | 171:3a7713b1edbc | 655 | |
| AnnaBridge | 171:3a7713b1edbc | 656 | /** |
| AnnaBridge | 171:3a7713b1edbc | 657 | * @brief Clear the specified FLASH flag. |
| AnnaBridge | 171:3a7713b1edbc | 658 | * @param __FLAG__ specifies the FLASH flags to clear. |
| AnnaBridge | 171:3a7713b1edbc | 659 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 660 | * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 661 | * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 662 | * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 663 | * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 |
| AnnaBridge | 171:3a7713b1edbc | 664 | * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 665 | * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 666 | * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 667 | * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 |
| AnnaBridge | 171:3a7713b1edbc | 668 | * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
| AnnaBridge | 171:3a7713b1edbc | 669 | * @retval none |
| AnnaBridge | 171:3a7713b1edbc | 670 | */ |
| AnnaBridge | 171:3a7713b1edbc | 671 | #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ |
| AnnaBridge | 171:3a7713b1edbc | 672 | /* Clear FLASH_FLAG_OPTVERR flag */ \ |
| AnnaBridge | 171:3a7713b1edbc | 673 | if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ |
| AnnaBridge | 171:3a7713b1edbc | 674 | { \ |
| AnnaBridge | 171:3a7713b1edbc | 675 | CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ |
| AnnaBridge | 171:3a7713b1edbc | 676 | } \ |
| AnnaBridge | 171:3a7713b1edbc | 677 | else { \ |
| AnnaBridge | 171:3a7713b1edbc | 678 | /* Clear Flag in Bank1 */ \ |
| AnnaBridge | 171:3a7713b1edbc | 679 | if (((__FLAG__) & SR_FLAG_MASK) != RESET) \ |
| AnnaBridge | 171:3a7713b1edbc | 680 | { \ |
| AnnaBridge | 171:3a7713b1edbc | 681 | FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \ |
| AnnaBridge | 171:3a7713b1edbc | 682 | } \ |
| AnnaBridge | 171:3a7713b1edbc | 683 | /* Clear Flag in Bank2 */ \ |
| AnnaBridge | 171:3a7713b1edbc | 684 | if (((__FLAG__) >> 16U) != RESET) \ |
| AnnaBridge | 171:3a7713b1edbc | 685 | { \ |
| AnnaBridge | 171:3a7713b1edbc | 686 | FLASH->SR2 = ((__FLAG__) >> 16U); \ |
| AnnaBridge | 171:3a7713b1edbc | 687 | } \ |
| AnnaBridge | 171:3a7713b1edbc | 688 | } \ |
| AnnaBridge | 171:3a7713b1edbc | 689 | } while(0U) |
| AnnaBridge | 171:3a7713b1edbc | 690 | #else |
| AnnaBridge | 171:3a7713b1edbc | 691 | /** |
| AnnaBridge | 171:3a7713b1edbc | 692 | * @brief Enable the specified FLASH interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 693 | * @param __INTERRUPT__ FLASH interrupt |
| AnnaBridge | 171:3a7713b1edbc | 694 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 695 | * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt |
| AnnaBridge | 171:3a7713b1edbc | 696 | * @arg @ref FLASH_IT_ERR Error Interrupt |
| AnnaBridge | 171:3a7713b1edbc | 697 | * @retval none |
| AnnaBridge | 171:3a7713b1edbc | 698 | */ |
| AnnaBridge | 171:3a7713b1edbc | 699 | #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 700 | |
| AnnaBridge | 171:3a7713b1edbc | 701 | /** |
| AnnaBridge | 171:3a7713b1edbc | 702 | * @brief Disable the specified FLASH interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 703 | * @param __INTERRUPT__ FLASH interrupt |
| AnnaBridge | 171:3a7713b1edbc | 704 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 705 | * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt |
| AnnaBridge | 171:3a7713b1edbc | 706 | * @arg @ref FLASH_IT_ERR Error Interrupt |
| AnnaBridge | 171:3a7713b1edbc | 707 | * @retval none |
| AnnaBridge | 171:3a7713b1edbc | 708 | */ |
| AnnaBridge | 171:3a7713b1edbc | 709 | #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 710 | |
| AnnaBridge | 171:3a7713b1edbc | 711 | /** |
| AnnaBridge | 171:3a7713b1edbc | 712 | * @brief Get the specified FLASH flag status. |
| AnnaBridge | 171:3a7713b1edbc | 713 | * @param __FLAG__ specifies the FLASH flag to check. |
| AnnaBridge | 171:3a7713b1edbc | 714 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 715 | * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag |
| AnnaBridge | 171:3a7713b1edbc | 716 | * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag |
| AnnaBridge | 171:3a7713b1edbc | 717 | * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag |
| AnnaBridge | 171:3a7713b1edbc | 718 | * @arg @ref FLASH_FLAG_BSY FLASH Busy flag |
| AnnaBridge | 171:3a7713b1edbc | 719 | * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
| AnnaBridge | 171:3a7713b1edbc | 720 | * @retval The new state of __FLAG__ (SET or RESET). |
| AnnaBridge | 171:3a7713b1edbc | 721 | */ |
| AnnaBridge | 171:3a7713b1edbc | 722 | #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ |
| AnnaBridge | 171:3a7713b1edbc | 723 | (FLASH->OBR & FLASH_OBR_OPTERR) : \ |
| AnnaBridge | 171:3a7713b1edbc | 724 | (FLASH->SR & (__FLAG__))) |
| AnnaBridge | 171:3a7713b1edbc | 725 | /** |
| AnnaBridge | 171:3a7713b1edbc | 726 | * @brief Clear the specified FLASH flag. |
| AnnaBridge | 171:3a7713b1edbc | 727 | * @param __FLAG__ specifies the FLASH flags to clear. |
| AnnaBridge | 171:3a7713b1edbc | 728 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 729 | * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag |
| AnnaBridge | 171:3a7713b1edbc | 730 | * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag |
| AnnaBridge | 171:3a7713b1edbc | 731 | * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag |
| AnnaBridge | 171:3a7713b1edbc | 732 | * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
| AnnaBridge | 171:3a7713b1edbc | 733 | * @retval none |
| AnnaBridge | 171:3a7713b1edbc | 734 | */ |
| AnnaBridge | 171:3a7713b1edbc | 735 | #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ |
| AnnaBridge | 171:3a7713b1edbc | 736 | /* Clear FLASH_FLAG_OPTVERR flag */ \ |
| AnnaBridge | 171:3a7713b1edbc | 737 | if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ |
| AnnaBridge | 171:3a7713b1edbc | 738 | { \ |
| AnnaBridge | 171:3a7713b1edbc | 739 | CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ |
| AnnaBridge | 171:3a7713b1edbc | 740 | } \ |
| AnnaBridge | 171:3a7713b1edbc | 741 | else { \ |
| AnnaBridge | 171:3a7713b1edbc | 742 | /* Clear Flag in Bank1 */ \ |
| AnnaBridge | 171:3a7713b1edbc | 743 | FLASH->SR = (__FLAG__); \ |
| AnnaBridge | 171:3a7713b1edbc | 744 | } \ |
| AnnaBridge | 171:3a7713b1edbc | 745 | } while(0U) |
| AnnaBridge | 171:3a7713b1edbc | 746 | |
| AnnaBridge | 171:3a7713b1edbc | 747 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 748 | |
| AnnaBridge | 171:3a7713b1edbc | 749 | /** |
| AnnaBridge | 171:3a7713b1edbc | 750 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 751 | */ |
| AnnaBridge | 171:3a7713b1edbc | 752 | |
| AnnaBridge | 171:3a7713b1edbc | 753 | /** |
| AnnaBridge | 171:3a7713b1edbc | 754 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 755 | */ |
| AnnaBridge | 171:3a7713b1edbc | 756 | |
| AnnaBridge | 171:3a7713b1edbc | 757 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 758 | /** @addtogroup FLASHEx_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 759 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 760 | */ |
| AnnaBridge | 171:3a7713b1edbc | 761 | |
| AnnaBridge | 171:3a7713b1edbc | 762 | /** @addtogroup FLASHEx_Exported_Functions_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 763 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 764 | */ |
| AnnaBridge | 171:3a7713b1edbc | 765 | /* IO operation functions *****************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 766 | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); |
| AnnaBridge | 171:3a7713b1edbc | 767 | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); |
| AnnaBridge | 171:3a7713b1edbc | 768 | |
| AnnaBridge | 171:3a7713b1edbc | 769 | /** |
| AnnaBridge | 171:3a7713b1edbc | 770 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 771 | */ |
| AnnaBridge | 171:3a7713b1edbc | 772 | |
| AnnaBridge | 171:3a7713b1edbc | 773 | /** @addtogroup FLASHEx_Exported_Functions_Group2 |
| AnnaBridge | 171:3a7713b1edbc | 774 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 775 | */ |
| AnnaBridge | 171:3a7713b1edbc | 776 | /* Peripheral Control functions ***********************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 777 | HAL_StatusTypeDef HAL_FLASHEx_OBErase(void); |
| AnnaBridge | 171:3a7713b1edbc | 778 | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); |
| AnnaBridge | 171:3a7713b1edbc | 779 | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); |
| AnnaBridge | 171:3a7713b1edbc | 780 | uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress); |
| AnnaBridge | 171:3a7713b1edbc | 781 | /** |
| AnnaBridge | 171:3a7713b1edbc | 782 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 783 | */ |
| AnnaBridge | 171:3a7713b1edbc | 784 | |
| AnnaBridge | 171:3a7713b1edbc | 785 | /** |
| AnnaBridge | 171:3a7713b1edbc | 786 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 787 | */ |
| AnnaBridge | 171:3a7713b1edbc | 788 | |
| AnnaBridge | 171:3a7713b1edbc | 789 | /** |
| AnnaBridge | 171:3a7713b1edbc | 790 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 791 | */ |
| AnnaBridge | 171:3a7713b1edbc | 792 | |
| AnnaBridge | 171:3a7713b1edbc | 793 | /** |
| AnnaBridge | 171:3a7713b1edbc | 794 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 795 | */ |
| AnnaBridge | 171:3a7713b1edbc | 796 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 797 | } |
| AnnaBridge | 171:3a7713b1edbc | 798 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 799 | |
| AnnaBridge | 171:3a7713b1edbc | 800 | #endif /* __STM32F1xx_HAL_FLASH_EX_H */ |
| AnnaBridge | 171:3a7713b1edbc | 801 | |
| AnnaBridge | 171:3a7713b1edbc | 802 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
