mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_pwr.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f1xx_ll_pwr.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of PWR LL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F1xx_LL_PWR_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F1xx_LL_PWR_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f1xx.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32F1xx_LL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 #if defined(PWR)
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /** @defgroup PWR_LL PWR
AnnaBridge 171:3a7713b1edbc 54 * @{
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 59 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 60 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 61 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 62 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 63 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
AnnaBridge 171:3a7713b1edbc 64 * @{
AnnaBridge 171:3a7713b1edbc 65 */
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge 171:3a7713b1edbc 68 * @brief Flags defines which can be used with LL_PWR_WriteReg function
AnnaBridge 171:3a7713b1edbc 69 * @{
AnnaBridge 171:3a7713b1edbc 70 */
AnnaBridge 171:3a7713b1edbc 71 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
AnnaBridge 171:3a7713b1edbc 72 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
AnnaBridge 171:3a7713b1edbc 73 /**
AnnaBridge 171:3a7713b1edbc 74 * @}
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 171:3a7713b1edbc 78 * @brief Flags defines which can be used with LL_PWR_ReadReg function
AnnaBridge 171:3a7713b1edbc 79 * @{
AnnaBridge 171:3a7713b1edbc 80 */
AnnaBridge 171:3a7713b1edbc 81 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
AnnaBridge 171:3a7713b1edbc 82 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
AnnaBridge 171:3a7713b1edbc 83 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
AnnaBridge 171:3a7713b1edbc 84 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
AnnaBridge 171:3a7713b1edbc 85 /**
AnnaBridge 171:3a7713b1edbc 86 * @}
AnnaBridge 171:3a7713b1edbc 87 */
AnnaBridge 171:3a7713b1edbc 88
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
AnnaBridge 171:3a7713b1edbc 91 * @{
AnnaBridge 171:3a7713b1edbc 92 */
AnnaBridge 171:3a7713b1edbc 93 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
AnnaBridge 171:3a7713b1edbc 94 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
AnnaBridge 171:3a7713b1edbc 95 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
AnnaBridge 171:3a7713b1edbc 96 /**
AnnaBridge 171:3a7713b1edbc 97 * @}
AnnaBridge 171:3a7713b1edbc 98 */
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
AnnaBridge 171:3a7713b1edbc 101 * @{
AnnaBridge 171:3a7713b1edbc 102 */
AnnaBridge 171:3a7713b1edbc 103 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
AnnaBridge 171:3a7713b1edbc 104 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
AnnaBridge 171:3a7713b1edbc 105 /**
AnnaBridge 171:3a7713b1edbc 106 * @}
AnnaBridge 171:3a7713b1edbc 107 */
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
AnnaBridge 171:3a7713b1edbc 110 * @{
AnnaBridge 171:3a7713b1edbc 111 */
AnnaBridge 171:3a7713b1edbc 112 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
AnnaBridge 171:3a7713b1edbc 113 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
AnnaBridge 171:3a7713b1edbc 114 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
AnnaBridge 171:3a7713b1edbc 115 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
AnnaBridge 171:3a7713b1edbc 116 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
AnnaBridge 171:3a7713b1edbc 117 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
AnnaBridge 171:3a7713b1edbc 118 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
AnnaBridge 171:3a7713b1edbc 119 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
AnnaBridge 171:3a7713b1edbc 120 /**
AnnaBridge 171:3a7713b1edbc 121 * @}
AnnaBridge 171:3a7713b1edbc 122 */
AnnaBridge 171:3a7713b1edbc 123 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
AnnaBridge 171:3a7713b1edbc 124 * @{
AnnaBridge 171:3a7713b1edbc 125 */
AnnaBridge 171:3a7713b1edbc 126 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
AnnaBridge 171:3a7713b1edbc 127 /**
AnnaBridge 171:3a7713b1edbc 128 * @}
AnnaBridge 171:3a7713b1edbc 129 */
AnnaBridge 171:3a7713b1edbc 130
AnnaBridge 171:3a7713b1edbc 131 /**
AnnaBridge 171:3a7713b1edbc 132 * @}
AnnaBridge 171:3a7713b1edbc 133 */
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 137 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
AnnaBridge 171:3a7713b1edbc 138 * @{
AnnaBridge 171:3a7713b1edbc 139 */
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
AnnaBridge 171:3a7713b1edbc 142 * @{
AnnaBridge 171:3a7713b1edbc 143 */
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 /**
AnnaBridge 171:3a7713b1edbc 146 * @brief Write a value in PWR register
AnnaBridge 171:3a7713b1edbc 147 * @param __REG__ Register to be written
AnnaBridge 171:3a7713b1edbc 148 * @param __VALUE__ Value to be written in the register
AnnaBridge 171:3a7713b1edbc 149 * @retval None
AnnaBridge 171:3a7713b1edbc 150 */
AnnaBridge 171:3a7713b1edbc 151 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 /**
AnnaBridge 171:3a7713b1edbc 154 * @brief Read a value in PWR register
AnnaBridge 171:3a7713b1edbc 155 * @param __REG__ Register to be read
AnnaBridge 171:3a7713b1edbc 156 * @retval Register value
AnnaBridge 171:3a7713b1edbc 157 */
AnnaBridge 171:3a7713b1edbc 158 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
AnnaBridge 171:3a7713b1edbc 159 /**
AnnaBridge 171:3a7713b1edbc 160 * @}
AnnaBridge 171:3a7713b1edbc 161 */
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 /**
AnnaBridge 171:3a7713b1edbc 164 * @}
AnnaBridge 171:3a7713b1edbc 165 */
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 168 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
AnnaBridge 171:3a7713b1edbc 169 * @{
AnnaBridge 171:3a7713b1edbc 170 */
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 /** @defgroup PWR_LL_EF_Configuration Configuration
AnnaBridge 171:3a7713b1edbc 173 * @{
AnnaBridge 171:3a7713b1edbc 174 */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 /**
AnnaBridge 171:3a7713b1edbc 177 * @brief Enable access to the backup domain
AnnaBridge 171:3a7713b1edbc 178 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
AnnaBridge 171:3a7713b1edbc 179 * @retval None
AnnaBridge 171:3a7713b1edbc 180 */
AnnaBridge 171:3a7713b1edbc 181 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
AnnaBridge 171:3a7713b1edbc 182 {
AnnaBridge 171:3a7713b1edbc 183 SET_BIT(PWR->CR, PWR_CR_DBP);
AnnaBridge 171:3a7713b1edbc 184 }
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 /**
AnnaBridge 171:3a7713b1edbc 187 * @brief Disable access to the backup domain
AnnaBridge 171:3a7713b1edbc 188 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
AnnaBridge 171:3a7713b1edbc 189 * @retval None
AnnaBridge 171:3a7713b1edbc 190 */
AnnaBridge 171:3a7713b1edbc 191 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
AnnaBridge 171:3a7713b1edbc 192 {
AnnaBridge 171:3a7713b1edbc 193 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
AnnaBridge 171:3a7713b1edbc 194 }
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 /**
AnnaBridge 171:3a7713b1edbc 197 * @brief Check if the backup domain is enabled
AnnaBridge 171:3a7713b1edbc 198 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
AnnaBridge 171:3a7713b1edbc 199 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 200 */
AnnaBridge 171:3a7713b1edbc 201 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
AnnaBridge 171:3a7713b1edbc 202 {
AnnaBridge 171:3a7713b1edbc 203 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
AnnaBridge 171:3a7713b1edbc 204 }
AnnaBridge 171:3a7713b1edbc 205
AnnaBridge 171:3a7713b1edbc 206 /**
AnnaBridge 171:3a7713b1edbc 207 * @brief Set voltage Regulator mode during deep sleep mode
AnnaBridge 171:3a7713b1edbc 208 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
AnnaBridge 171:3a7713b1edbc 209 * @param RegulMode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 210 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
AnnaBridge 171:3a7713b1edbc 211 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
AnnaBridge 171:3a7713b1edbc 212 * @retval None
AnnaBridge 171:3a7713b1edbc 213 */
AnnaBridge 171:3a7713b1edbc 214 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
AnnaBridge 171:3a7713b1edbc 215 {
AnnaBridge 171:3a7713b1edbc 216 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
AnnaBridge 171:3a7713b1edbc 217 }
AnnaBridge 171:3a7713b1edbc 218
AnnaBridge 171:3a7713b1edbc 219 /**
AnnaBridge 171:3a7713b1edbc 220 * @brief Get voltage Regulator mode during deep sleep mode
AnnaBridge 171:3a7713b1edbc 221 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
AnnaBridge 171:3a7713b1edbc 222 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 223 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
AnnaBridge 171:3a7713b1edbc 224 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
AnnaBridge 171:3a7713b1edbc 225 */
AnnaBridge 171:3a7713b1edbc 226 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
AnnaBridge 171:3a7713b1edbc 227 {
AnnaBridge 171:3a7713b1edbc 228 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
AnnaBridge 171:3a7713b1edbc 229 }
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /**
AnnaBridge 171:3a7713b1edbc 232 * @brief Set Power Down mode when CPU enters deepsleep
AnnaBridge 171:3a7713b1edbc 233 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
AnnaBridge 171:3a7713b1edbc 234 * @rmtoll CR LPDS LL_PWR_SetPowerMode
AnnaBridge 171:3a7713b1edbc 235 * @param PDMode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 236 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
AnnaBridge 171:3a7713b1edbc 237 * @arg @ref LL_PWR_MODE_STOP_LPREGU
AnnaBridge 171:3a7713b1edbc 238 * @arg @ref LL_PWR_MODE_STANDBY
AnnaBridge 171:3a7713b1edbc 239 * @retval None
AnnaBridge 171:3a7713b1edbc 240 */
AnnaBridge 171:3a7713b1edbc 241 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
AnnaBridge 171:3a7713b1edbc 242 {
AnnaBridge 171:3a7713b1edbc 243 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
AnnaBridge 171:3a7713b1edbc 244 }
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 /**
AnnaBridge 171:3a7713b1edbc 247 * @brief Get Power Down mode when CPU enters deepsleep
AnnaBridge 171:3a7713b1edbc 248 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
AnnaBridge 171:3a7713b1edbc 249 * @rmtoll CR LPDS LL_PWR_GetPowerMode
AnnaBridge 171:3a7713b1edbc 250 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 251 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
AnnaBridge 171:3a7713b1edbc 252 * @arg @ref LL_PWR_MODE_STOP_LPREGU
AnnaBridge 171:3a7713b1edbc 253 * @arg @ref LL_PWR_MODE_STANDBY
AnnaBridge 171:3a7713b1edbc 254 */
AnnaBridge 171:3a7713b1edbc 255 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
AnnaBridge 171:3a7713b1edbc 256 {
AnnaBridge 171:3a7713b1edbc 257 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
AnnaBridge 171:3a7713b1edbc 258 }
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 /**
AnnaBridge 171:3a7713b1edbc 261 * @brief Configure the voltage threshold detected by the Power Voltage Detector
AnnaBridge 171:3a7713b1edbc 262 * @rmtoll CR PLS LL_PWR_SetPVDLevel
AnnaBridge 171:3a7713b1edbc 263 * @param PVDLevel This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 264 * @arg @ref LL_PWR_PVDLEVEL_0
AnnaBridge 171:3a7713b1edbc 265 * @arg @ref LL_PWR_PVDLEVEL_1
AnnaBridge 171:3a7713b1edbc 266 * @arg @ref LL_PWR_PVDLEVEL_2
AnnaBridge 171:3a7713b1edbc 267 * @arg @ref LL_PWR_PVDLEVEL_3
AnnaBridge 171:3a7713b1edbc 268 * @arg @ref LL_PWR_PVDLEVEL_4
AnnaBridge 171:3a7713b1edbc 269 * @arg @ref LL_PWR_PVDLEVEL_5
AnnaBridge 171:3a7713b1edbc 270 * @arg @ref LL_PWR_PVDLEVEL_6
AnnaBridge 171:3a7713b1edbc 271 * @arg @ref LL_PWR_PVDLEVEL_7
AnnaBridge 171:3a7713b1edbc 272 * @retval None
AnnaBridge 171:3a7713b1edbc 273 */
AnnaBridge 171:3a7713b1edbc 274 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
AnnaBridge 171:3a7713b1edbc 275 {
AnnaBridge 171:3a7713b1edbc 276 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
AnnaBridge 171:3a7713b1edbc 277 }
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 /**
AnnaBridge 171:3a7713b1edbc 280 * @brief Get the voltage threshold detection
AnnaBridge 171:3a7713b1edbc 281 * @rmtoll CR PLS LL_PWR_GetPVDLevel
AnnaBridge 171:3a7713b1edbc 282 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 283 * @arg @ref LL_PWR_PVDLEVEL_0
AnnaBridge 171:3a7713b1edbc 284 * @arg @ref LL_PWR_PVDLEVEL_1
AnnaBridge 171:3a7713b1edbc 285 * @arg @ref LL_PWR_PVDLEVEL_2
AnnaBridge 171:3a7713b1edbc 286 * @arg @ref LL_PWR_PVDLEVEL_3
AnnaBridge 171:3a7713b1edbc 287 * @arg @ref LL_PWR_PVDLEVEL_4
AnnaBridge 171:3a7713b1edbc 288 * @arg @ref LL_PWR_PVDLEVEL_5
AnnaBridge 171:3a7713b1edbc 289 * @arg @ref LL_PWR_PVDLEVEL_6
AnnaBridge 171:3a7713b1edbc 290 * @arg @ref LL_PWR_PVDLEVEL_7
AnnaBridge 171:3a7713b1edbc 291 */
AnnaBridge 171:3a7713b1edbc 292 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
AnnaBridge 171:3a7713b1edbc 293 {
AnnaBridge 171:3a7713b1edbc 294 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
AnnaBridge 171:3a7713b1edbc 295 }
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 /**
AnnaBridge 171:3a7713b1edbc 298 * @brief Enable Power Voltage Detector
AnnaBridge 171:3a7713b1edbc 299 * @rmtoll CR PVDE LL_PWR_EnablePVD
AnnaBridge 171:3a7713b1edbc 300 * @retval None
AnnaBridge 171:3a7713b1edbc 301 */
AnnaBridge 171:3a7713b1edbc 302 __STATIC_INLINE void LL_PWR_EnablePVD(void)
AnnaBridge 171:3a7713b1edbc 303 {
AnnaBridge 171:3a7713b1edbc 304 SET_BIT(PWR->CR, PWR_CR_PVDE);
AnnaBridge 171:3a7713b1edbc 305 }
AnnaBridge 171:3a7713b1edbc 306
AnnaBridge 171:3a7713b1edbc 307 /**
AnnaBridge 171:3a7713b1edbc 308 * @brief Disable Power Voltage Detector
AnnaBridge 171:3a7713b1edbc 309 * @rmtoll CR PVDE LL_PWR_DisablePVD
AnnaBridge 171:3a7713b1edbc 310 * @retval None
AnnaBridge 171:3a7713b1edbc 311 */
AnnaBridge 171:3a7713b1edbc 312 __STATIC_INLINE void LL_PWR_DisablePVD(void)
AnnaBridge 171:3a7713b1edbc 313 {
AnnaBridge 171:3a7713b1edbc 314 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
AnnaBridge 171:3a7713b1edbc 315 }
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 /**
AnnaBridge 171:3a7713b1edbc 318 * @brief Check if Power Voltage Detector is enabled
AnnaBridge 171:3a7713b1edbc 319 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
AnnaBridge 171:3a7713b1edbc 320 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 321 */
AnnaBridge 171:3a7713b1edbc 322 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
AnnaBridge 171:3a7713b1edbc 323 {
AnnaBridge 171:3a7713b1edbc 324 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
AnnaBridge 171:3a7713b1edbc 325 }
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 /**
AnnaBridge 171:3a7713b1edbc 328 * @brief Enable the WakeUp PINx functionality
AnnaBridge 171:3a7713b1edbc 329 * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
AnnaBridge 171:3a7713b1edbc 330 * @param WakeUpPin This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 331 * @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge 171:3a7713b1edbc 332 * @retval None
AnnaBridge 171:3a7713b1edbc 333 */
AnnaBridge 171:3a7713b1edbc 334 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
AnnaBridge 171:3a7713b1edbc 335 {
AnnaBridge 171:3a7713b1edbc 336 SET_BIT(PWR->CSR, WakeUpPin);
AnnaBridge 171:3a7713b1edbc 337 }
AnnaBridge 171:3a7713b1edbc 338
AnnaBridge 171:3a7713b1edbc 339 /**
AnnaBridge 171:3a7713b1edbc 340 * @brief Disable the WakeUp PINx functionality
AnnaBridge 171:3a7713b1edbc 341 * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
AnnaBridge 171:3a7713b1edbc 342 * @param WakeUpPin This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 343 * @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge 171:3a7713b1edbc 344 * @retval None
AnnaBridge 171:3a7713b1edbc 345 */
AnnaBridge 171:3a7713b1edbc 346 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
AnnaBridge 171:3a7713b1edbc 347 {
AnnaBridge 171:3a7713b1edbc 348 CLEAR_BIT(PWR->CSR, WakeUpPin);
AnnaBridge 171:3a7713b1edbc 349 }
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 /**
AnnaBridge 171:3a7713b1edbc 352 * @brief Check if the WakeUp PINx functionality is enabled
AnnaBridge 171:3a7713b1edbc 353 * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
AnnaBridge 171:3a7713b1edbc 354 * @param WakeUpPin This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 355 * @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge 171:3a7713b1edbc 356 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 357 */
AnnaBridge 171:3a7713b1edbc 358 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
AnnaBridge 171:3a7713b1edbc 359 {
AnnaBridge 171:3a7713b1edbc 360 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
AnnaBridge 171:3a7713b1edbc 361 }
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363
AnnaBridge 171:3a7713b1edbc 364 /**
AnnaBridge 171:3a7713b1edbc 365 * @}
AnnaBridge 171:3a7713b1edbc 366 */
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
AnnaBridge 171:3a7713b1edbc 369 * @{
AnnaBridge 171:3a7713b1edbc 370 */
AnnaBridge 171:3a7713b1edbc 371
AnnaBridge 171:3a7713b1edbc 372 /**
AnnaBridge 171:3a7713b1edbc 373 * @brief Get Wake-up Flag
AnnaBridge 171:3a7713b1edbc 374 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
AnnaBridge 171:3a7713b1edbc 375 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 376 */
AnnaBridge 171:3a7713b1edbc 377 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
AnnaBridge 171:3a7713b1edbc 378 {
AnnaBridge 171:3a7713b1edbc 379 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
AnnaBridge 171:3a7713b1edbc 380 }
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382 /**
AnnaBridge 171:3a7713b1edbc 383 * @brief Get Standby Flag
AnnaBridge 171:3a7713b1edbc 384 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
AnnaBridge 171:3a7713b1edbc 385 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 386 */
AnnaBridge 171:3a7713b1edbc 387 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
AnnaBridge 171:3a7713b1edbc 388 {
AnnaBridge 171:3a7713b1edbc 389 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
AnnaBridge 171:3a7713b1edbc 390 }
AnnaBridge 171:3a7713b1edbc 391
AnnaBridge 171:3a7713b1edbc 392 /**
AnnaBridge 171:3a7713b1edbc 393 * @brief Indicate whether VDD voltage is below the selected PVD threshold
AnnaBridge 171:3a7713b1edbc 394 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
AnnaBridge 171:3a7713b1edbc 395 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 396 */
AnnaBridge 171:3a7713b1edbc 397 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
AnnaBridge 171:3a7713b1edbc 398 {
AnnaBridge 171:3a7713b1edbc 399 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
AnnaBridge 171:3a7713b1edbc 400 }
AnnaBridge 171:3a7713b1edbc 401
AnnaBridge 171:3a7713b1edbc 402 /**
AnnaBridge 171:3a7713b1edbc 403 * @brief Clear Standby Flag
AnnaBridge 171:3a7713b1edbc 404 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
AnnaBridge 171:3a7713b1edbc 405 * @retval None
AnnaBridge 171:3a7713b1edbc 406 */
AnnaBridge 171:3a7713b1edbc 407 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
AnnaBridge 171:3a7713b1edbc 408 {
AnnaBridge 171:3a7713b1edbc 409 SET_BIT(PWR->CR, PWR_CR_CSBF);
AnnaBridge 171:3a7713b1edbc 410 }
AnnaBridge 171:3a7713b1edbc 411
AnnaBridge 171:3a7713b1edbc 412 /**
AnnaBridge 171:3a7713b1edbc 413 * @brief Clear Wake-up Flags
AnnaBridge 171:3a7713b1edbc 414 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
AnnaBridge 171:3a7713b1edbc 415 * @retval None
AnnaBridge 171:3a7713b1edbc 416 */
AnnaBridge 171:3a7713b1edbc 417 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
AnnaBridge 171:3a7713b1edbc 418 {
AnnaBridge 171:3a7713b1edbc 419 SET_BIT(PWR->CR, PWR_CR_CWUF);
AnnaBridge 171:3a7713b1edbc 420 }
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422 /**
AnnaBridge 171:3a7713b1edbc 423 * @}
AnnaBridge 171:3a7713b1edbc 424 */
AnnaBridge 171:3a7713b1edbc 425
AnnaBridge 171:3a7713b1edbc 426 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 427 /** @defgroup PWR_LL_EF_Init De-initialization function
AnnaBridge 171:3a7713b1edbc 428 * @{
AnnaBridge 171:3a7713b1edbc 429 */
AnnaBridge 171:3a7713b1edbc 430 ErrorStatus LL_PWR_DeInit(void);
AnnaBridge 171:3a7713b1edbc 431 /**
AnnaBridge 171:3a7713b1edbc 432 * @}
AnnaBridge 171:3a7713b1edbc 433 */
AnnaBridge 171:3a7713b1edbc 434 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 171:3a7713b1edbc 435
AnnaBridge 171:3a7713b1edbc 436 /**
AnnaBridge 171:3a7713b1edbc 437 * @}
AnnaBridge 171:3a7713b1edbc 438 */
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440 /**
AnnaBridge 171:3a7713b1edbc 441 * @}
AnnaBridge 171:3a7713b1edbc 442 */
AnnaBridge 171:3a7713b1edbc 443
AnnaBridge 171:3a7713b1edbc 444 #endif /* defined(PWR) */
AnnaBridge 171:3a7713b1edbc 445
AnnaBridge 171:3a7713b1edbc 446 /**
AnnaBridge 171:3a7713b1edbc 447 * @}
AnnaBridge 171:3a7713b1edbc 448 */
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 451 }
AnnaBridge 171:3a7713b1edbc 452 #endif
AnnaBridge 171:3a7713b1edbc 453
AnnaBridge 171:3a7713b1edbc 454 #endif /* __STM32F1xx_LL_PWR_H */
AnnaBridge 171:3a7713b1edbc 455
AnnaBridge 171:3a7713b1edbc 456 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/