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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

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AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f1xx_hal_i2s.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of I2S HAL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F1xx_HAL_I2S_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F1xx_HAL_I2S_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 47 #include "stm32f1xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /** @addtogroup STM32F1xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 50 * @{
AnnaBridge 171:3a7713b1edbc 51 */
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /** @addtogroup I2S
AnnaBridge 171:3a7713b1edbc 54 * @{
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 58 /** @defgroup I2S_Exported_Types I2S Exported Types
AnnaBridge 171:3a7713b1edbc 59 * @{
AnnaBridge 171:3a7713b1edbc 60 */
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 /**
AnnaBridge 171:3a7713b1edbc 63 * @brief I2S Init structure definition
AnnaBridge 171:3a7713b1edbc 64 */
AnnaBridge 171:3a7713b1edbc 65 typedef struct
AnnaBridge 171:3a7713b1edbc 66 {
AnnaBridge 171:3a7713b1edbc 67 uint32_t Mode; /*!< Specifies the I2S operating mode.
AnnaBridge 171:3a7713b1edbc 68 This parameter can be a value of @ref I2S_Mode */
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
AnnaBridge 171:3a7713b1edbc 71 This parameter can be a value of @ref I2S_Standard */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
AnnaBridge 171:3a7713b1edbc 74 This parameter can be a value of @ref I2S_Data_Format */
AnnaBridge 171:3a7713b1edbc 75
AnnaBridge 171:3a7713b1edbc 76 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
AnnaBridge 171:3a7713b1edbc 77 This parameter can be a value of @ref I2S_MCLK_Output */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
AnnaBridge 171:3a7713b1edbc 80 This parameter can be a value of @ref I2S_Audio_Frequency */
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
AnnaBridge 171:3a7713b1edbc 83 This parameter can be a value of @ref I2S_Clock_Polarity */
AnnaBridge 171:3a7713b1edbc 84 }I2S_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 85
AnnaBridge 171:3a7713b1edbc 86 /**
AnnaBridge 171:3a7713b1edbc 87 * @brief HAL State structures definition
AnnaBridge 171:3a7713b1edbc 88 */
AnnaBridge 171:3a7713b1edbc 89 typedef enum
AnnaBridge 171:3a7713b1edbc 90 {
AnnaBridge 171:3a7713b1edbc 91 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
AnnaBridge 171:3a7713b1edbc 92 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
AnnaBridge 171:3a7713b1edbc 93 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
AnnaBridge 171:3a7713b1edbc 94 HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
AnnaBridge 171:3a7713b1edbc 95 HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
AnnaBridge 171:3a7713b1edbc 96 HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
AnnaBridge 171:3a7713b1edbc 97 HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
AnnaBridge 171:3a7713b1edbc 98 HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 }HAL_I2S_StateTypeDef;
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 /**
AnnaBridge 171:3a7713b1edbc 103 * @brief I2S handle Structure definition
AnnaBridge 171:3a7713b1edbc 104 */
AnnaBridge 171:3a7713b1edbc 105 typedef struct __I2S_HandleTypeDef
AnnaBridge 171:3a7713b1edbc 106 {
AnnaBridge 171:3a7713b1edbc 107 SPI_TypeDef *Instance; /*!< I2S registers base address */
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109 I2S_InitTypeDef Init; /*!< I2S communication parameters */
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117 uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
AnnaBridge 171:3a7713b1edbc 122 (This field is initialized at the
AnnaBridge 171:3a7713b1edbc 123 same value as transfer size at the
AnnaBridge 171:3a7713b1edbc 124 beginning of the transfer and
AnnaBridge 171:3a7713b1edbc 125 decremented when a sample is received
AnnaBridge 171:3a7713b1edbc 126 NbSamplesReceived = RxBufferSize-RxBufferCount) */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 void (*IrqHandlerISR) (struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136 __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 __IO uint32_t ErrorCode; /*!< I2S Error code
AnnaBridge 171:3a7713b1edbc 139 This parameter can be a value of @ref I2S_ErrorCode */
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141 }I2S_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 142 /**
AnnaBridge 171:3a7713b1edbc 143 * @}
AnnaBridge 171:3a7713b1edbc 144 */
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 147 /** @defgroup I2S_Exported_Constants I2S Exported Constants
AnnaBridge 171:3a7713b1edbc 148 * @{
AnnaBridge 171:3a7713b1edbc 149 */
AnnaBridge 171:3a7713b1edbc 150 /**
AnnaBridge 171:3a7713b1edbc 151 * @defgroup I2S_ErrorCode I2S Error Code
AnnaBridge 171:3a7713b1edbc 152 * @{
AnnaBridge 171:3a7713b1edbc 153 */
AnnaBridge 171:3a7713b1edbc 154 #define HAL_I2S_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 171:3a7713b1edbc 155 #define HAL_I2S_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
AnnaBridge 171:3a7713b1edbc 156 #define HAL_I2S_ERROR_OVR 0x00000002U /*!< OVR error */
AnnaBridge 171:3a7713b1edbc 157 #define HAL_I2S_ERROR_UDR 0x00000004U /*!< UDR error */
AnnaBridge 171:3a7713b1edbc 158 #define HAL_I2S_ERROR_DMA 0x00000008U /*!< DMA transfer error */
AnnaBridge 171:3a7713b1edbc 159 #define HAL_I2S_ERROR_PRESCALER 0x00000010U /*!< Prescaler Calculation error */
AnnaBridge 171:3a7713b1edbc 160 /**
AnnaBridge 171:3a7713b1edbc 161 * @}
AnnaBridge 171:3a7713b1edbc 162 */
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 /** @defgroup I2S_Mode I2S Mode
AnnaBridge 171:3a7713b1edbc 165 * @{
AnnaBridge 171:3a7713b1edbc 166 */
AnnaBridge 171:3a7713b1edbc 167 #define I2S_MODE_SLAVE_TX 0x00000000U
AnnaBridge 171:3a7713b1edbc 168 #define I2S_MODE_SLAVE_RX ((uint32_t)SPI_I2SCFGR_I2SCFG_0)
AnnaBridge 171:3a7713b1edbc 169 #define I2S_MODE_MASTER_TX ((uint32_t)SPI_I2SCFGR_I2SCFG_1)
AnnaBridge 171:3a7713b1edbc 170 #define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
AnnaBridge 171:3a7713b1edbc 171 /**
AnnaBridge 171:3a7713b1edbc 172 * @}
AnnaBridge 171:3a7713b1edbc 173 */
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 /** @defgroup I2S_Standard I2S Standard
AnnaBridge 171:3a7713b1edbc 176 * @{
AnnaBridge 171:3a7713b1edbc 177 */
AnnaBridge 171:3a7713b1edbc 178 #define I2S_STANDARD_PHILIPS 0x00000000U
AnnaBridge 171:3a7713b1edbc 179 #define I2S_STANDARD_MSB ((uint32_t)SPI_I2SCFGR_I2SSTD_0)
AnnaBridge 171:3a7713b1edbc 180 #define I2S_STANDARD_LSB ((uint32_t)SPI_I2SCFGR_I2SSTD_1)
AnnaBridge 171:3a7713b1edbc 181 #define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
AnnaBridge 171:3a7713b1edbc 182 #define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
AnnaBridge 171:3a7713b1edbc 183 /**
AnnaBridge 171:3a7713b1edbc 184 * @}
AnnaBridge 171:3a7713b1edbc 185 */
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 /** @defgroup I2S_Data_Format I2S Data Format
AnnaBridge 171:3a7713b1edbc 188 * @{
AnnaBridge 171:3a7713b1edbc 189 */
AnnaBridge 171:3a7713b1edbc 190 #define I2S_DATAFORMAT_16B 0x00000000U
AnnaBridge 171:3a7713b1edbc 191 #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)SPI_I2SCFGR_CHLEN)
AnnaBridge 171:3a7713b1edbc 192 #define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
AnnaBridge 171:3a7713b1edbc 193 #define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
AnnaBridge 171:3a7713b1edbc 194 /**
AnnaBridge 171:3a7713b1edbc 195 * @}
AnnaBridge 171:3a7713b1edbc 196 */
AnnaBridge 171:3a7713b1edbc 197
AnnaBridge 171:3a7713b1edbc 198 /** @defgroup I2S_MCLK_Output I2S Mclk Output
AnnaBridge 171:3a7713b1edbc 199 * @{
AnnaBridge 171:3a7713b1edbc 200 */
AnnaBridge 171:3a7713b1edbc 201 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
AnnaBridge 171:3a7713b1edbc 202 #define I2S_MCLKOUTPUT_DISABLE 0x00000000U
AnnaBridge 171:3a7713b1edbc 203 /**
AnnaBridge 171:3a7713b1edbc 204 * @}
AnnaBridge 171:3a7713b1edbc 205 */
AnnaBridge 171:3a7713b1edbc 206
AnnaBridge 171:3a7713b1edbc 207 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
AnnaBridge 171:3a7713b1edbc 208 * @{
AnnaBridge 171:3a7713b1edbc 209 */
AnnaBridge 171:3a7713b1edbc 210 #define I2S_AUDIOFREQ_192K 192000U
AnnaBridge 171:3a7713b1edbc 211 #define I2S_AUDIOFREQ_96K 96000U
AnnaBridge 171:3a7713b1edbc 212 #define I2S_AUDIOFREQ_48K 48000U
AnnaBridge 171:3a7713b1edbc 213 #define I2S_AUDIOFREQ_44K 44100U
AnnaBridge 171:3a7713b1edbc 214 #define I2S_AUDIOFREQ_32K 32000U
AnnaBridge 171:3a7713b1edbc 215 #define I2S_AUDIOFREQ_22K 22050U
AnnaBridge 171:3a7713b1edbc 216 #define I2S_AUDIOFREQ_16K 16000U
AnnaBridge 171:3a7713b1edbc 217 #define I2S_AUDIOFREQ_11K 11025U
AnnaBridge 171:3a7713b1edbc 218 #define I2S_AUDIOFREQ_8K 8000U
AnnaBridge 171:3a7713b1edbc 219 #define I2S_AUDIOFREQ_DEFAULT 2U
AnnaBridge 171:3a7713b1edbc 220 /**
AnnaBridge 171:3a7713b1edbc 221 * @}
AnnaBridge 171:3a7713b1edbc 222 */
AnnaBridge 171:3a7713b1edbc 223
AnnaBridge 171:3a7713b1edbc 224 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
AnnaBridge 171:3a7713b1edbc 225 * @{
AnnaBridge 171:3a7713b1edbc 226 */
AnnaBridge 171:3a7713b1edbc 227 #define I2S_CPOL_LOW 0x00000000U
AnnaBridge 171:3a7713b1edbc 228 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
AnnaBridge 171:3a7713b1edbc 229 /**
AnnaBridge 171:3a7713b1edbc 230 * @}
AnnaBridge 171:3a7713b1edbc 231 */
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
AnnaBridge 171:3a7713b1edbc 234 * @{
AnnaBridge 171:3a7713b1edbc 235 */
AnnaBridge 171:3a7713b1edbc 236 #define I2S_IT_TXE SPI_CR2_TXEIE
AnnaBridge 171:3a7713b1edbc 237 #define I2S_IT_RXNE SPI_CR2_RXNEIE
AnnaBridge 171:3a7713b1edbc 238 #define I2S_IT_ERR SPI_CR2_ERRIE
AnnaBridge 171:3a7713b1edbc 239 /**
AnnaBridge 171:3a7713b1edbc 240 * @}
AnnaBridge 171:3a7713b1edbc 241 */
AnnaBridge 171:3a7713b1edbc 242
AnnaBridge 171:3a7713b1edbc 243 /** @defgroup I2S_Flags_Definition I2S Flags Definition
AnnaBridge 171:3a7713b1edbc 244 * @{
AnnaBridge 171:3a7713b1edbc 245 */
AnnaBridge 171:3a7713b1edbc 246 #define I2S_FLAG_TXE SPI_SR_TXE
AnnaBridge 171:3a7713b1edbc 247 #define I2S_FLAG_RXNE SPI_SR_RXNE
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249 #define I2S_FLAG_UDR SPI_SR_UDR
AnnaBridge 171:3a7713b1edbc 250 #define I2S_FLAG_OVR SPI_SR_OVR
AnnaBridge 171:3a7713b1edbc 251 #define I2S_FLAG_FRE SPI_SR_FRE
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
AnnaBridge 171:3a7713b1edbc 254 #define I2S_FLAG_BSY SPI_SR_BSY
AnnaBridge 171:3a7713b1edbc 255 /**
AnnaBridge 171:3a7713b1edbc 256 * @}
AnnaBridge 171:3a7713b1edbc 257 */
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 /**
AnnaBridge 171:3a7713b1edbc 260 * @}
AnnaBridge 171:3a7713b1edbc 261 */
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 264 /** @defgroup I2S_Exported_Macros I2S Exported Macros
AnnaBridge 171:3a7713b1edbc 265 * @{
AnnaBridge 171:3a7713b1edbc 266 */
AnnaBridge 171:3a7713b1edbc 267
AnnaBridge 171:3a7713b1edbc 268 /** @brief Reset I2S handle state
AnnaBridge 171:3a7713b1edbc 269 * @param __HANDLE__: specifies the I2S Handle.
AnnaBridge 171:3a7713b1edbc 270 * @retval None
AnnaBridge 171:3a7713b1edbc 271 */
AnnaBridge 171:3a7713b1edbc 272 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274 /** @brief Enable the specified SPI peripheral (in I2S mode).
AnnaBridge 171:3a7713b1edbc 275 * @param __HANDLE__: specifies the I2S Handle.
AnnaBridge 171:3a7713b1edbc 276 * @retval None
AnnaBridge 171:3a7713b1edbc 277 */
AnnaBridge 171:3a7713b1edbc 278 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
AnnaBridge 171:3a7713b1edbc 279
AnnaBridge 171:3a7713b1edbc 280 /** @brief Disable the specified SPI peripheral (in I2S mode).
AnnaBridge 171:3a7713b1edbc 281 * @param __HANDLE__: specifies the I2S Handle.
AnnaBridge 171:3a7713b1edbc 282 * @retval None
AnnaBridge 171:3a7713b1edbc 283 */
AnnaBridge 171:3a7713b1edbc 284 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 /** @brief Enable the specified I2S interrupts.
AnnaBridge 171:3a7713b1edbc 287 * @param __HANDLE__: specifies the I2S Handle.
AnnaBridge 171:3a7713b1edbc 288 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
AnnaBridge 171:3a7713b1edbc 289 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 290 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
AnnaBridge 171:3a7713b1edbc 291 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
AnnaBridge 171:3a7713b1edbc 292 * @arg I2S_IT_ERR: Error interrupt enable
AnnaBridge 171:3a7713b1edbc 293 * @retval None
AnnaBridge 171:3a7713b1edbc 294 */
AnnaBridge 171:3a7713b1edbc 295 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 /** @brief Disable the specified I2S interrupts.
AnnaBridge 171:3a7713b1edbc 298 * @param __HANDLE__: specifies the I2S Handle.
AnnaBridge 171:3a7713b1edbc 299 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
AnnaBridge 171:3a7713b1edbc 300 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 301 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
AnnaBridge 171:3a7713b1edbc 302 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
AnnaBridge 171:3a7713b1edbc 303 * @arg I2S_IT_ERR: Error interrupt enable
AnnaBridge 171:3a7713b1edbc 304 * @retval None
AnnaBridge 171:3a7713b1edbc 305 */
AnnaBridge 171:3a7713b1edbc 306 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 309 * @param __HANDLE__: specifies the I2S Handle.
AnnaBridge 171:3a7713b1edbc 310 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
AnnaBridge 171:3a7713b1edbc 311 * @param __INTERRUPT__: specifies the I2S interrupt source to check.
AnnaBridge 171:3a7713b1edbc 312 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 313 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
AnnaBridge 171:3a7713b1edbc 314 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
AnnaBridge 171:3a7713b1edbc 315 * @arg I2S_IT_ERR: Error interrupt enable
AnnaBridge 171:3a7713b1edbc 316 * @retval The new state of __IT__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 317 */
AnnaBridge 171:3a7713b1edbc 318 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 /** @brief Checks whether the specified I2S flag is set or not.
AnnaBridge 171:3a7713b1edbc 321 * @param __HANDLE__: specifies the I2S Handle.
AnnaBridge 171:3a7713b1edbc 322 * @param __FLAG__: specifies the flag to check.
AnnaBridge 171:3a7713b1edbc 323 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 324 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
AnnaBridge 171:3a7713b1edbc 325 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
AnnaBridge 171:3a7713b1edbc 326 * @arg I2S_FLAG_UDR: Underrun flag
AnnaBridge 171:3a7713b1edbc 327 * @arg I2S_FLAG_OVR: Overrun flag
AnnaBridge 171:3a7713b1edbc 328 * @arg I2S_FLAG_FRE: Frame error flag
AnnaBridge 171:3a7713b1edbc 329 * @arg I2S_FLAG_CHSIDE: Channel Side flag
AnnaBridge 171:3a7713b1edbc 330 * @arg I2S_FLAG_BSY: Busy flag
AnnaBridge 171:3a7713b1edbc 331 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 332 */
AnnaBridge 171:3a7713b1edbc 333 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
AnnaBridge 171:3a7713b1edbc 334
AnnaBridge 171:3a7713b1edbc 335 /** @brief Clears the I2S OVR pending flag.
AnnaBridge 171:3a7713b1edbc 336 * @param __HANDLE__: specifies the I2S Handle.
AnnaBridge 171:3a7713b1edbc 337 * @retval None
AnnaBridge 171:3a7713b1edbc 338 */
AnnaBridge 171:3a7713b1edbc 339 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 340 do{ \
AnnaBridge 171:3a7713b1edbc 341 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 171:3a7713b1edbc 342 tmpreg = (__HANDLE__)->Instance->DR; \
AnnaBridge 171:3a7713b1edbc 343 tmpreg = (__HANDLE__)->Instance->SR; \
AnnaBridge 171:3a7713b1edbc 344 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 345 } while(0U)
AnnaBridge 171:3a7713b1edbc 346
AnnaBridge 171:3a7713b1edbc 347 /** @brief Clears the I2S UDR pending flag.
AnnaBridge 171:3a7713b1edbc 348 * @param __HANDLE__: specifies the I2S Handle.
AnnaBridge 171:3a7713b1edbc 349 * @retval None
AnnaBridge 171:3a7713b1edbc 350 */
AnnaBridge 171:3a7713b1edbc 351 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 352 do{ \
AnnaBridge 171:3a7713b1edbc 353 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 171:3a7713b1edbc 354 tmpreg = (__HANDLE__)->Instance->SR; \
AnnaBridge 171:3a7713b1edbc 355 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 356 } while(0U)
AnnaBridge 171:3a7713b1edbc 357 /**
AnnaBridge 171:3a7713b1edbc 358 * @}
AnnaBridge 171:3a7713b1edbc 359 */
AnnaBridge 171:3a7713b1edbc 360
AnnaBridge 171:3a7713b1edbc 361 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 362 /** @addtogroup I2S_Exported_Functions
AnnaBridge 171:3a7713b1edbc 363 * @{
AnnaBridge 171:3a7713b1edbc 364 */
AnnaBridge 171:3a7713b1edbc 365
AnnaBridge 171:3a7713b1edbc 366 /** @addtogroup I2S_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 367 * @{
AnnaBridge 171:3a7713b1edbc 368 */
AnnaBridge 171:3a7713b1edbc 369 /* Initialization/de-initialization functions ********************************/
AnnaBridge 171:3a7713b1edbc 370 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 371 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 372 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 373 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 374 /**
AnnaBridge 171:3a7713b1edbc 375 * @}
AnnaBridge 171:3a7713b1edbc 376 */
AnnaBridge 171:3a7713b1edbc 377
AnnaBridge 171:3a7713b1edbc 378 /** @addtogroup I2S_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 379 * @{
AnnaBridge 171:3a7713b1edbc 380 */
AnnaBridge 171:3a7713b1edbc 381 /* I/O operation functions ***************************************************/
AnnaBridge 171:3a7713b1edbc 382 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 383 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 384 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 385
AnnaBridge 171:3a7713b1edbc 386 /* Non-Blocking mode: Interrupt */
AnnaBridge 171:3a7713b1edbc 387 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
AnnaBridge 171:3a7713b1edbc 388 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
AnnaBridge 171:3a7713b1edbc 389 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 390
AnnaBridge 171:3a7713b1edbc 391 /* Non-Blocking mode: DMA */
AnnaBridge 171:3a7713b1edbc 392 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
AnnaBridge 171:3a7713b1edbc 393 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
AnnaBridge 171:3a7713b1edbc 394
AnnaBridge 171:3a7713b1edbc 395 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 396 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 397 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 398
AnnaBridge 171:3a7713b1edbc 399 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
AnnaBridge 171:3a7713b1edbc 400 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 401 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 402 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 403 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 404 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 405 /**
AnnaBridge 171:3a7713b1edbc 406 * @}
AnnaBridge 171:3a7713b1edbc 407 */
AnnaBridge 171:3a7713b1edbc 408
AnnaBridge 171:3a7713b1edbc 409 /** @addtogroup I2S_Exported_Functions_Group3
AnnaBridge 171:3a7713b1edbc 410 * @{
AnnaBridge 171:3a7713b1edbc 411 */
AnnaBridge 171:3a7713b1edbc 412 /* Peripheral Control and State functions ************************************/
AnnaBridge 171:3a7713b1edbc 413 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 414 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
AnnaBridge 171:3a7713b1edbc 415 /**
AnnaBridge 171:3a7713b1edbc 416 * @}
AnnaBridge 171:3a7713b1edbc 417 */
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 /**
AnnaBridge 171:3a7713b1edbc 420 * @}
AnnaBridge 171:3a7713b1edbc 421 */
AnnaBridge 171:3a7713b1edbc 422
AnnaBridge 171:3a7713b1edbc 423 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 424 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 425 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 426 /** @defgroup I2S_Private_Constants I2S Private Constants
AnnaBridge 171:3a7713b1edbc 427 * @{
AnnaBridge 171:3a7713b1edbc 428 */
AnnaBridge 171:3a7713b1edbc 429
AnnaBridge 171:3a7713b1edbc 430 /**
AnnaBridge 171:3a7713b1edbc 431 * @}
AnnaBridge 171:3a7713b1edbc 432 */
AnnaBridge 171:3a7713b1edbc 433
AnnaBridge 171:3a7713b1edbc 434 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 435 /** @defgroup I2S_Private_Macros I2S Private Macros
AnnaBridge 171:3a7713b1edbc 436 * @{
AnnaBridge 171:3a7713b1edbc 437 */
AnnaBridge 171:3a7713b1edbc 438 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
AnnaBridge 171:3a7713b1edbc 439 ((MODE) == I2S_MODE_SLAVE_RX) || \
AnnaBridge 171:3a7713b1edbc 440 ((MODE) == I2S_MODE_MASTER_TX) || \
AnnaBridge 171:3a7713b1edbc 441 ((MODE) == I2S_MODE_MASTER_RX))
AnnaBridge 171:3a7713b1edbc 442
AnnaBridge 171:3a7713b1edbc 443 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
AnnaBridge 171:3a7713b1edbc 444 ((STANDARD) == I2S_STANDARD_MSB) || \
AnnaBridge 171:3a7713b1edbc 445 ((STANDARD) == I2S_STANDARD_LSB) || \
AnnaBridge 171:3a7713b1edbc 446 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
AnnaBridge 171:3a7713b1edbc 447 ((STANDARD) == I2S_STANDARD_PCM_LONG))
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
AnnaBridge 171:3a7713b1edbc 450 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
AnnaBridge 171:3a7713b1edbc 451 ((FORMAT) == I2S_DATAFORMAT_24B) || \
AnnaBridge 171:3a7713b1edbc 452 ((FORMAT) == I2S_DATAFORMAT_32B))
AnnaBridge 171:3a7713b1edbc 453
AnnaBridge 171:3a7713b1edbc 454 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 455 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
AnnaBridge 171:3a7713b1edbc 458 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
AnnaBridge 171:3a7713b1edbc 459 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
AnnaBridge 171:3a7713b1edbc 460
AnnaBridge 171:3a7713b1edbc 461 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
AnnaBridge 171:3a7713b1edbc 462 ((CPOL) == I2S_CPOL_HIGH))
AnnaBridge 171:3a7713b1edbc 463 /**
AnnaBridge 171:3a7713b1edbc 464 * @}
AnnaBridge 171:3a7713b1edbc 465 */
AnnaBridge 171:3a7713b1edbc 466
AnnaBridge 171:3a7713b1edbc 467 /* Private Fonctions ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 468 /** @defgroup I2S_Private_Functions I2S Private Functions
AnnaBridge 171:3a7713b1edbc 469 * @{
AnnaBridge 171:3a7713b1edbc 470 */
AnnaBridge 171:3a7713b1edbc 471 /* Private functions are defined in stm32f1xx_hal_i2s.c file */
AnnaBridge 171:3a7713b1edbc 472 /**
AnnaBridge 171:3a7713b1edbc 473 * @}
AnnaBridge 171:3a7713b1edbc 474 */
AnnaBridge 171:3a7713b1edbc 475
AnnaBridge 171:3a7713b1edbc 476 /**
AnnaBridge 171:3a7713b1edbc 477 * @}
AnnaBridge 171:3a7713b1edbc 478 */
AnnaBridge 171:3a7713b1edbc 479
AnnaBridge 171:3a7713b1edbc 480 /**
AnnaBridge 171:3a7713b1edbc 481 * @}
AnnaBridge 171:3a7713b1edbc 482 */
AnnaBridge 171:3a7713b1edbc 483 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
AnnaBridge 171:3a7713b1edbc 484
AnnaBridge 171:3a7713b1edbc 485 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 486 }
AnnaBridge 171:3a7713b1edbc 487 #endif
AnnaBridge 171:3a7713b1edbc 488
AnnaBridge 171:3a7713b1edbc 489 #endif /* __STM32F1xx_HAL_I2S_H */
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/