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TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/stm32f0xx_ll_pwr.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f0xx_ll_pwr.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of PWR LL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F0xx_LL_PWR_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F0xx_LL_PWR_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f0xx.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F0xx_LL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | #if defined(PWR) |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | /** @defgroup PWR_LL PWR |
AnnaBridge | 171:3a7713b1edbc | 54 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 55 | */ |
AnnaBridge | 171:3a7713b1edbc | 56 | |
AnnaBridge | 171:3a7713b1edbc | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 59 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 60 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 61 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 62 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 63 | /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 64 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 65 | */ |
AnnaBridge | 171:3a7713b1edbc | 66 | |
AnnaBridge | 171:3a7713b1edbc | 67 | /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines |
AnnaBridge | 171:3a7713b1edbc | 68 | * @brief Flags defines which can be used with LL_PWR_WriteReg function |
AnnaBridge | 171:3a7713b1edbc | 69 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 70 | */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ |
AnnaBridge | 171:3a7713b1edbc | 73 | /** |
AnnaBridge | 171:3a7713b1edbc | 74 | * @} |
AnnaBridge | 171:3a7713b1edbc | 75 | */ |
AnnaBridge | 171:3a7713b1edbc | 76 | |
AnnaBridge | 171:3a7713b1edbc | 77 | /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines |
AnnaBridge | 171:3a7713b1edbc | 78 | * @brief Flags defines which can be used with LL_PWR_ReadReg function |
AnnaBridge | 171:3a7713b1edbc | 79 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 80 | */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #if defined(PWR_PVD_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 84 | #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #endif /* PWR_PVD_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #if defined(PWR_CSR_VREFINTRDYF) |
AnnaBridge | 171:3a7713b1edbc | 87 | #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #endif /* PWR_CSR_VREFINTRDYF */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #if defined(PWR_CSR_EWUP3) |
AnnaBridge | 171:3a7713b1edbc | 92 | #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ |
AnnaBridge | 171:3a7713b1edbc | 93 | #endif /* PWR_CSR_EWUP3 */ |
AnnaBridge | 171:3a7713b1edbc | 94 | #if defined(PWR_CSR_EWUP4) |
AnnaBridge | 171:3a7713b1edbc | 95 | #define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */ |
AnnaBridge | 171:3a7713b1edbc | 96 | #endif /* PWR_CSR_EWUP4 */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #if defined(PWR_CSR_EWUP5) |
AnnaBridge | 171:3a7713b1edbc | 98 | #define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */ |
AnnaBridge | 171:3a7713b1edbc | 99 | #endif /* PWR_CSR_EWUP5 */ |
AnnaBridge | 171:3a7713b1edbc | 100 | #if defined(PWR_CSR_EWUP6) |
AnnaBridge | 171:3a7713b1edbc | 101 | #define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */ |
AnnaBridge | 171:3a7713b1edbc | 102 | #endif /* PWR_CSR_EWUP6 */ |
AnnaBridge | 171:3a7713b1edbc | 103 | #if defined(PWR_CSR_EWUP7) |
AnnaBridge | 171:3a7713b1edbc | 104 | #define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */ |
AnnaBridge | 171:3a7713b1edbc | 105 | #endif /* PWR_CSR_EWUP7 */ |
AnnaBridge | 171:3a7713b1edbc | 106 | #if defined(PWR_CSR_EWUP8) |
AnnaBridge | 171:3a7713b1edbc | 107 | #define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #endif /* PWR_CSR_EWUP8 */ |
AnnaBridge | 171:3a7713b1edbc | 109 | /** |
AnnaBridge | 171:3a7713b1edbc | 110 | * @} |
AnnaBridge | 171:3a7713b1edbc | 111 | */ |
AnnaBridge | 171:3a7713b1edbc | 112 | |
AnnaBridge | 171:3a7713b1edbc | 113 | |
AnnaBridge | 171:3a7713b1edbc | 114 | /** @defgroup PWR_LL_EC_MODE_PWR Mode Power |
AnnaBridge | 171:3a7713b1edbc | 115 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 116 | */ |
AnnaBridge | 171:3a7713b1edbc | 117 | #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ |
AnnaBridge | 171:3a7713b1edbc | 118 | #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ |
AnnaBridge | 171:3a7713b1edbc | 119 | #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ |
AnnaBridge | 171:3a7713b1edbc | 120 | /** |
AnnaBridge | 171:3a7713b1edbc | 121 | * @} |
AnnaBridge | 171:3a7713b1edbc | 122 | */ |
AnnaBridge | 171:3a7713b1edbc | 123 | |
AnnaBridge | 171:3a7713b1edbc | 124 | #if defined(PWR_CR_LPDS) |
AnnaBridge | 171:3a7713b1edbc | 125 | /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode |
AnnaBridge | 171:3a7713b1edbc | 126 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 127 | */ |
AnnaBridge | 171:3a7713b1edbc | 128 | #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ |
AnnaBridge | 171:3a7713b1edbc | 129 | #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ |
AnnaBridge | 171:3a7713b1edbc | 130 | /** |
AnnaBridge | 171:3a7713b1edbc | 131 | * @} |
AnnaBridge | 171:3a7713b1edbc | 132 | */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #endif /* PWR_CR_LPDS */ |
AnnaBridge | 171:3a7713b1edbc | 134 | |
AnnaBridge | 171:3a7713b1edbc | 135 | #if defined(PWR_PVD_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 136 | /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level |
AnnaBridge | 171:3a7713b1edbc | 137 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 138 | */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */ |
AnnaBridge | 171:3a7713b1edbc | 140 | #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */ |
AnnaBridge | 171:3a7713b1edbc | 146 | #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */ |
AnnaBridge | 171:3a7713b1edbc | 147 | /** |
AnnaBridge | 171:3a7713b1edbc | 148 | * @} |
AnnaBridge | 171:3a7713b1edbc | 149 | */ |
AnnaBridge | 171:3a7713b1edbc | 150 | #endif /* PWR_PVD_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 151 | /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins |
AnnaBridge | 171:3a7713b1edbc | 152 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 153 | */ |
AnnaBridge | 171:3a7713b1edbc | 154 | #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ |
AnnaBridge | 171:3a7713b1edbc | 156 | #if defined(PWR_CSR_EWUP3) |
AnnaBridge | 171:3a7713b1edbc | 157 | #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ |
AnnaBridge | 171:3a7713b1edbc | 158 | #endif /* PWR_CSR_EWUP3 */ |
AnnaBridge | 171:3a7713b1edbc | 159 | #if defined(PWR_CSR_EWUP4) |
AnnaBridge | 171:3a7713b1edbc | 160 | #define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #endif /* PWR_CSR_EWUP4 */ |
AnnaBridge | 171:3a7713b1edbc | 162 | #if defined(PWR_CSR_EWUP5) |
AnnaBridge | 171:3a7713b1edbc | 163 | #define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */ |
AnnaBridge | 171:3a7713b1edbc | 164 | #endif /* PWR_CSR_EWUP5 */ |
AnnaBridge | 171:3a7713b1edbc | 165 | #if defined(PWR_CSR_EWUP6) |
AnnaBridge | 171:3a7713b1edbc | 166 | #define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */ |
AnnaBridge | 171:3a7713b1edbc | 167 | #endif /* PWR_CSR_EWUP6 */ |
AnnaBridge | 171:3a7713b1edbc | 168 | #if defined(PWR_CSR_EWUP7) |
AnnaBridge | 171:3a7713b1edbc | 169 | #define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */ |
AnnaBridge | 171:3a7713b1edbc | 170 | #endif /* PWR_CSR_EWUP7 */ |
AnnaBridge | 171:3a7713b1edbc | 171 | #if defined(PWR_CSR_EWUP8) |
AnnaBridge | 171:3a7713b1edbc | 172 | #define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */ |
AnnaBridge | 171:3a7713b1edbc | 173 | #endif /* PWR_CSR_EWUP8 */ |
AnnaBridge | 171:3a7713b1edbc | 174 | /** |
AnnaBridge | 171:3a7713b1edbc | 175 | * @} |
AnnaBridge | 171:3a7713b1edbc | 176 | */ |
AnnaBridge | 171:3a7713b1edbc | 177 | |
AnnaBridge | 171:3a7713b1edbc | 178 | /** |
AnnaBridge | 171:3a7713b1edbc | 179 | * @} |
AnnaBridge | 171:3a7713b1edbc | 180 | */ |
AnnaBridge | 171:3a7713b1edbc | 181 | |
AnnaBridge | 171:3a7713b1edbc | 182 | |
AnnaBridge | 171:3a7713b1edbc | 183 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 184 | /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 185 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 186 | */ |
AnnaBridge | 171:3a7713b1edbc | 187 | |
AnnaBridge | 171:3a7713b1edbc | 188 | /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros |
AnnaBridge | 171:3a7713b1edbc | 189 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 190 | */ |
AnnaBridge | 171:3a7713b1edbc | 191 | |
AnnaBridge | 171:3a7713b1edbc | 192 | /** |
AnnaBridge | 171:3a7713b1edbc | 193 | * @brief Write a value in PWR register |
AnnaBridge | 171:3a7713b1edbc | 194 | * @param __REG__ Register to be written |
AnnaBridge | 171:3a7713b1edbc | 195 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 171:3a7713b1edbc | 196 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 197 | */ |
AnnaBridge | 171:3a7713b1edbc | 198 | #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) |
AnnaBridge | 171:3a7713b1edbc | 199 | |
AnnaBridge | 171:3a7713b1edbc | 200 | /** |
AnnaBridge | 171:3a7713b1edbc | 201 | * @brief Read a value in PWR register |
AnnaBridge | 171:3a7713b1edbc | 202 | * @param __REG__ Register to be read |
AnnaBridge | 171:3a7713b1edbc | 203 | * @retval Register value |
AnnaBridge | 171:3a7713b1edbc | 204 | */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) |
AnnaBridge | 171:3a7713b1edbc | 206 | /** |
AnnaBridge | 171:3a7713b1edbc | 207 | * @} |
AnnaBridge | 171:3a7713b1edbc | 208 | */ |
AnnaBridge | 171:3a7713b1edbc | 209 | |
AnnaBridge | 171:3a7713b1edbc | 210 | /** |
AnnaBridge | 171:3a7713b1edbc | 211 | * @} |
AnnaBridge | 171:3a7713b1edbc | 212 | */ |
AnnaBridge | 171:3a7713b1edbc | 213 | |
AnnaBridge | 171:3a7713b1edbc | 214 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 215 | /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions |
AnnaBridge | 171:3a7713b1edbc | 216 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 217 | */ |
AnnaBridge | 171:3a7713b1edbc | 218 | |
AnnaBridge | 171:3a7713b1edbc | 219 | /** @defgroup PWR_LL_EF_Configuration Configuration |
AnnaBridge | 171:3a7713b1edbc | 220 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 221 | */ |
AnnaBridge | 171:3a7713b1edbc | 222 | |
AnnaBridge | 171:3a7713b1edbc | 223 | /** |
AnnaBridge | 171:3a7713b1edbc | 224 | * @brief Enable access to the backup domain |
AnnaBridge | 171:3a7713b1edbc | 225 | * @rmtoll CR DBP LL_PWR_EnableBkUpAccess |
AnnaBridge | 171:3a7713b1edbc | 226 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 227 | */ |
AnnaBridge | 171:3a7713b1edbc | 228 | __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) |
AnnaBridge | 171:3a7713b1edbc | 229 | { |
AnnaBridge | 171:3a7713b1edbc | 230 | SET_BIT(PWR->CR, PWR_CR_DBP); |
AnnaBridge | 171:3a7713b1edbc | 231 | } |
AnnaBridge | 171:3a7713b1edbc | 232 | |
AnnaBridge | 171:3a7713b1edbc | 233 | /** |
AnnaBridge | 171:3a7713b1edbc | 234 | * @brief Disable access to the backup domain |
AnnaBridge | 171:3a7713b1edbc | 235 | * @rmtoll CR DBP LL_PWR_DisableBkUpAccess |
AnnaBridge | 171:3a7713b1edbc | 236 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 237 | */ |
AnnaBridge | 171:3a7713b1edbc | 238 | __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) |
AnnaBridge | 171:3a7713b1edbc | 239 | { |
AnnaBridge | 171:3a7713b1edbc | 240 | CLEAR_BIT(PWR->CR, PWR_CR_DBP); |
AnnaBridge | 171:3a7713b1edbc | 241 | } |
AnnaBridge | 171:3a7713b1edbc | 242 | |
AnnaBridge | 171:3a7713b1edbc | 243 | /** |
AnnaBridge | 171:3a7713b1edbc | 244 | * @brief Check if the backup domain is enabled |
AnnaBridge | 171:3a7713b1edbc | 245 | * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess |
AnnaBridge | 171:3a7713b1edbc | 246 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 247 | */ |
AnnaBridge | 171:3a7713b1edbc | 248 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) |
AnnaBridge | 171:3a7713b1edbc | 249 | { |
AnnaBridge | 171:3a7713b1edbc | 250 | return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); |
AnnaBridge | 171:3a7713b1edbc | 251 | } |
AnnaBridge | 171:3a7713b1edbc | 252 | |
AnnaBridge | 171:3a7713b1edbc | 253 | #if defined(PWR_CR_LPDS) |
AnnaBridge | 171:3a7713b1edbc | 254 | /** |
AnnaBridge | 171:3a7713b1edbc | 255 | * @brief Set voltage Regulator mode during deep sleep mode |
AnnaBridge | 171:3a7713b1edbc | 256 | * @rmtoll CR LPDS LL_PWR_SetRegulModeDS |
AnnaBridge | 171:3a7713b1edbc | 257 | * @param RegulMode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 258 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
AnnaBridge | 171:3a7713b1edbc | 259 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
AnnaBridge | 171:3a7713b1edbc | 260 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 261 | */ |
AnnaBridge | 171:3a7713b1edbc | 262 | __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) |
AnnaBridge | 171:3a7713b1edbc | 263 | { |
AnnaBridge | 171:3a7713b1edbc | 264 | MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); |
AnnaBridge | 171:3a7713b1edbc | 265 | } |
AnnaBridge | 171:3a7713b1edbc | 266 | |
AnnaBridge | 171:3a7713b1edbc | 267 | /** |
AnnaBridge | 171:3a7713b1edbc | 268 | * @brief Get voltage Regulator mode during deep sleep mode |
AnnaBridge | 171:3a7713b1edbc | 269 | * @rmtoll CR LPDS LL_PWR_GetRegulModeDS |
AnnaBridge | 171:3a7713b1edbc | 270 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 271 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
AnnaBridge | 171:3a7713b1edbc | 272 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
AnnaBridge | 171:3a7713b1edbc | 273 | */ |
AnnaBridge | 171:3a7713b1edbc | 274 | __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) |
AnnaBridge | 171:3a7713b1edbc | 275 | { |
AnnaBridge | 171:3a7713b1edbc | 276 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); |
AnnaBridge | 171:3a7713b1edbc | 277 | } |
AnnaBridge | 171:3a7713b1edbc | 278 | #endif /* PWR_CR_LPDS */ |
AnnaBridge | 171:3a7713b1edbc | 279 | |
AnnaBridge | 171:3a7713b1edbc | 280 | /** |
AnnaBridge | 171:3a7713b1edbc | 281 | * @brief Set Power Down mode when CPU enters deepsleep |
AnnaBridge | 171:3a7713b1edbc | 282 | * @rmtoll CR PDDS LL_PWR_SetPowerMode\n |
AnnaBridge | 171:3a7713b1edbc | 283 | * @rmtoll CR LPDS LL_PWR_SetPowerMode |
AnnaBridge | 171:3a7713b1edbc | 284 | * @param PDMode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 285 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
AnnaBridge | 171:3a7713b1edbc | 286 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
AnnaBridge | 171:3a7713b1edbc | 287 | * @arg @ref LL_PWR_MODE_STANDBY |
AnnaBridge | 171:3a7713b1edbc | 288 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 289 | */ |
AnnaBridge | 171:3a7713b1edbc | 290 | __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) |
AnnaBridge | 171:3a7713b1edbc | 291 | { |
AnnaBridge | 171:3a7713b1edbc | 292 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); |
AnnaBridge | 171:3a7713b1edbc | 293 | } |
AnnaBridge | 171:3a7713b1edbc | 294 | |
AnnaBridge | 171:3a7713b1edbc | 295 | /** |
AnnaBridge | 171:3a7713b1edbc | 296 | * @brief Get Power Down mode when CPU enters deepsleep |
AnnaBridge | 171:3a7713b1edbc | 297 | * @rmtoll CR PDDS LL_PWR_GetPowerMode\n |
AnnaBridge | 171:3a7713b1edbc | 298 | * @rmtoll CR LPDS LL_PWR_GetPowerMode |
AnnaBridge | 171:3a7713b1edbc | 299 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 300 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
AnnaBridge | 171:3a7713b1edbc | 301 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
AnnaBridge | 171:3a7713b1edbc | 302 | * @arg @ref LL_PWR_MODE_STANDBY |
AnnaBridge | 171:3a7713b1edbc | 303 | */ |
AnnaBridge | 171:3a7713b1edbc | 304 | __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) |
AnnaBridge | 171:3a7713b1edbc | 305 | { |
AnnaBridge | 171:3a7713b1edbc | 306 | return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); |
AnnaBridge | 171:3a7713b1edbc | 307 | } |
AnnaBridge | 171:3a7713b1edbc | 308 | |
AnnaBridge | 171:3a7713b1edbc | 309 | #if defined(PWR_PVD_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 310 | /** |
AnnaBridge | 171:3a7713b1edbc | 311 | * @brief Configure the voltage threshold detected by the Power Voltage Detector |
AnnaBridge | 171:3a7713b1edbc | 312 | * @rmtoll CR PLS LL_PWR_SetPVDLevel |
AnnaBridge | 171:3a7713b1edbc | 313 | * @param PVDLevel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 314 | * @arg @ref LL_PWR_PVDLEVEL_0 |
AnnaBridge | 171:3a7713b1edbc | 315 | * @arg @ref LL_PWR_PVDLEVEL_1 |
AnnaBridge | 171:3a7713b1edbc | 316 | * @arg @ref LL_PWR_PVDLEVEL_2 |
AnnaBridge | 171:3a7713b1edbc | 317 | * @arg @ref LL_PWR_PVDLEVEL_3 |
AnnaBridge | 171:3a7713b1edbc | 318 | * @arg @ref LL_PWR_PVDLEVEL_4 |
AnnaBridge | 171:3a7713b1edbc | 319 | * @arg @ref LL_PWR_PVDLEVEL_5 |
AnnaBridge | 171:3a7713b1edbc | 320 | * @arg @ref LL_PWR_PVDLEVEL_6 |
AnnaBridge | 171:3a7713b1edbc | 321 | * @arg @ref LL_PWR_PVDLEVEL_7 |
AnnaBridge | 171:3a7713b1edbc | 322 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 323 | */ |
AnnaBridge | 171:3a7713b1edbc | 324 | __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) |
AnnaBridge | 171:3a7713b1edbc | 325 | { |
AnnaBridge | 171:3a7713b1edbc | 326 | MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); |
AnnaBridge | 171:3a7713b1edbc | 327 | } |
AnnaBridge | 171:3a7713b1edbc | 328 | |
AnnaBridge | 171:3a7713b1edbc | 329 | /** |
AnnaBridge | 171:3a7713b1edbc | 330 | * @brief Get the voltage threshold detection |
AnnaBridge | 171:3a7713b1edbc | 331 | * @rmtoll CR PLS LL_PWR_GetPVDLevel |
AnnaBridge | 171:3a7713b1edbc | 332 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 333 | * @arg @ref LL_PWR_PVDLEVEL_0 |
AnnaBridge | 171:3a7713b1edbc | 334 | * @arg @ref LL_PWR_PVDLEVEL_1 |
AnnaBridge | 171:3a7713b1edbc | 335 | * @arg @ref LL_PWR_PVDLEVEL_2 |
AnnaBridge | 171:3a7713b1edbc | 336 | * @arg @ref LL_PWR_PVDLEVEL_3 |
AnnaBridge | 171:3a7713b1edbc | 337 | * @arg @ref LL_PWR_PVDLEVEL_4 |
AnnaBridge | 171:3a7713b1edbc | 338 | * @arg @ref LL_PWR_PVDLEVEL_5 |
AnnaBridge | 171:3a7713b1edbc | 339 | * @arg @ref LL_PWR_PVDLEVEL_6 |
AnnaBridge | 171:3a7713b1edbc | 340 | * @arg @ref LL_PWR_PVDLEVEL_7 |
AnnaBridge | 171:3a7713b1edbc | 341 | */ |
AnnaBridge | 171:3a7713b1edbc | 342 | __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) |
AnnaBridge | 171:3a7713b1edbc | 343 | { |
AnnaBridge | 171:3a7713b1edbc | 344 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); |
AnnaBridge | 171:3a7713b1edbc | 345 | } |
AnnaBridge | 171:3a7713b1edbc | 346 | |
AnnaBridge | 171:3a7713b1edbc | 347 | /** |
AnnaBridge | 171:3a7713b1edbc | 348 | * @brief Enable Power Voltage Detector |
AnnaBridge | 171:3a7713b1edbc | 349 | * @rmtoll CR PVDE LL_PWR_EnablePVD |
AnnaBridge | 171:3a7713b1edbc | 350 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 351 | */ |
AnnaBridge | 171:3a7713b1edbc | 352 | __STATIC_INLINE void LL_PWR_EnablePVD(void) |
AnnaBridge | 171:3a7713b1edbc | 353 | { |
AnnaBridge | 171:3a7713b1edbc | 354 | SET_BIT(PWR->CR, PWR_CR_PVDE); |
AnnaBridge | 171:3a7713b1edbc | 355 | } |
AnnaBridge | 171:3a7713b1edbc | 356 | |
AnnaBridge | 171:3a7713b1edbc | 357 | /** |
AnnaBridge | 171:3a7713b1edbc | 358 | * @brief Disable Power Voltage Detector |
AnnaBridge | 171:3a7713b1edbc | 359 | * @rmtoll CR PVDE LL_PWR_DisablePVD |
AnnaBridge | 171:3a7713b1edbc | 360 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 361 | */ |
AnnaBridge | 171:3a7713b1edbc | 362 | __STATIC_INLINE void LL_PWR_DisablePVD(void) |
AnnaBridge | 171:3a7713b1edbc | 363 | { |
AnnaBridge | 171:3a7713b1edbc | 364 | CLEAR_BIT(PWR->CR, PWR_CR_PVDE); |
AnnaBridge | 171:3a7713b1edbc | 365 | } |
AnnaBridge | 171:3a7713b1edbc | 366 | |
AnnaBridge | 171:3a7713b1edbc | 367 | /** |
AnnaBridge | 171:3a7713b1edbc | 368 | * @brief Check if Power Voltage Detector is enabled |
AnnaBridge | 171:3a7713b1edbc | 369 | * @rmtoll CR PVDE LL_PWR_IsEnabledPVD |
AnnaBridge | 171:3a7713b1edbc | 370 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 371 | */ |
AnnaBridge | 171:3a7713b1edbc | 372 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) |
AnnaBridge | 171:3a7713b1edbc | 373 | { |
AnnaBridge | 171:3a7713b1edbc | 374 | return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); |
AnnaBridge | 171:3a7713b1edbc | 375 | } |
AnnaBridge | 171:3a7713b1edbc | 376 | #endif /* PWR_PVD_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 377 | |
AnnaBridge | 171:3a7713b1edbc | 378 | /** |
AnnaBridge | 171:3a7713b1edbc | 379 | * @brief Enable the WakeUp PINx functionality |
AnnaBridge | 171:3a7713b1edbc | 380 | * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 381 | * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 382 | * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 383 | * @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 384 | * @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 385 | * @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 386 | * @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 387 | * @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin |
AnnaBridge | 171:3a7713b1edbc | 388 | * @param WakeUpPin This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 389 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
AnnaBridge | 171:3a7713b1edbc | 390 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
AnnaBridge | 171:3a7713b1edbc | 391 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
AnnaBridge | 171:3a7713b1edbc | 392 | * @arg @ref LL_PWR_WAKEUP_PIN4 (*) |
AnnaBridge | 171:3a7713b1edbc | 393 | * @arg @ref LL_PWR_WAKEUP_PIN5 (*) |
AnnaBridge | 171:3a7713b1edbc | 394 | * @arg @ref LL_PWR_WAKEUP_PIN6 (*) |
AnnaBridge | 171:3a7713b1edbc | 395 | * @arg @ref LL_PWR_WAKEUP_PIN7 (*) |
AnnaBridge | 171:3a7713b1edbc | 396 | * @arg @ref LL_PWR_WAKEUP_PIN8 (*) |
AnnaBridge | 171:3a7713b1edbc | 397 | * |
AnnaBridge | 171:3a7713b1edbc | 398 | * (*) not available on all devices |
AnnaBridge | 171:3a7713b1edbc | 399 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 400 | */ |
AnnaBridge | 171:3a7713b1edbc | 401 | __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) |
AnnaBridge | 171:3a7713b1edbc | 402 | { |
AnnaBridge | 171:3a7713b1edbc | 403 | SET_BIT(PWR->CSR, WakeUpPin); |
AnnaBridge | 171:3a7713b1edbc | 404 | } |
AnnaBridge | 171:3a7713b1edbc | 405 | |
AnnaBridge | 171:3a7713b1edbc | 406 | /** |
AnnaBridge | 171:3a7713b1edbc | 407 | * @brief Disable the WakeUp PINx functionality |
AnnaBridge | 171:3a7713b1edbc | 408 | * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 409 | * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 410 | * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 411 | * @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 412 | * @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 413 | * @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 414 | * @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 415 | * @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin |
AnnaBridge | 171:3a7713b1edbc | 416 | * @param WakeUpPin This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 417 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
AnnaBridge | 171:3a7713b1edbc | 418 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
AnnaBridge | 171:3a7713b1edbc | 419 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
AnnaBridge | 171:3a7713b1edbc | 420 | * @arg @ref LL_PWR_WAKEUP_PIN4 (*) |
AnnaBridge | 171:3a7713b1edbc | 421 | * @arg @ref LL_PWR_WAKEUP_PIN5 (*) |
AnnaBridge | 171:3a7713b1edbc | 422 | * @arg @ref LL_PWR_WAKEUP_PIN6 (*) |
AnnaBridge | 171:3a7713b1edbc | 423 | * @arg @ref LL_PWR_WAKEUP_PIN7 (*) |
AnnaBridge | 171:3a7713b1edbc | 424 | * @arg @ref LL_PWR_WAKEUP_PIN8 (*) |
AnnaBridge | 171:3a7713b1edbc | 425 | * |
AnnaBridge | 171:3a7713b1edbc | 426 | * (*) not available on all devices |
AnnaBridge | 171:3a7713b1edbc | 427 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 428 | */ |
AnnaBridge | 171:3a7713b1edbc | 429 | __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) |
AnnaBridge | 171:3a7713b1edbc | 430 | { |
AnnaBridge | 171:3a7713b1edbc | 431 | CLEAR_BIT(PWR->CSR, WakeUpPin); |
AnnaBridge | 171:3a7713b1edbc | 432 | } |
AnnaBridge | 171:3a7713b1edbc | 433 | |
AnnaBridge | 171:3a7713b1edbc | 434 | /** |
AnnaBridge | 171:3a7713b1edbc | 435 | * @brief Check if the WakeUp PINx functionality is enabled |
AnnaBridge | 171:3a7713b1edbc | 436 | * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 437 | * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 438 | * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 439 | * @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 440 | * @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 441 | * @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 442 | * @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n |
AnnaBridge | 171:3a7713b1edbc | 443 | * @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin |
AnnaBridge | 171:3a7713b1edbc | 444 | * @param WakeUpPin This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 445 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
AnnaBridge | 171:3a7713b1edbc | 446 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
AnnaBridge | 171:3a7713b1edbc | 447 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
AnnaBridge | 171:3a7713b1edbc | 448 | * @arg @ref LL_PWR_WAKEUP_PIN4 (*) |
AnnaBridge | 171:3a7713b1edbc | 449 | * @arg @ref LL_PWR_WAKEUP_PIN5 (*) |
AnnaBridge | 171:3a7713b1edbc | 450 | * @arg @ref LL_PWR_WAKEUP_PIN6 (*) |
AnnaBridge | 171:3a7713b1edbc | 451 | * @arg @ref LL_PWR_WAKEUP_PIN7 (*) |
AnnaBridge | 171:3a7713b1edbc | 452 | * @arg @ref LL_PWR_WAKEUP_PIN8 (*) |
AnnaBridge | 171:3a7713b1edbc | 453 | * |
AnnaBridge | 171:3a7713b1edbc | 454 | * (*) not available on all devices |
AnnaBridge | 171:3a7713b1edbc | 455 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 456 | */ |
AnnaBridge | 171:3a7713b1edbc | 457 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) |
AnnaBridge | 171:3a7713b1edbc | 458 | { |
AnnaBridge | 171:3a7713b1edbc | 459 | return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); |
AnnaBridge | 171:3a7713b1edbc | 460 | } |
AnnaBridge | 171:3a7713b1edbc | 461 | |
AnnaBridge | 171:3a7713b1edbc | 462 | |
AnnaBridge | 171:3a7713b1edbc | 463 | /** |
AnnaBridge | 171:3a7713b1edbc | 464 | * @} |
AnnaBridge | 171:3a7713b1edbc | 465 | */ |
AnnaBridge | 171:3a7713b1edbc | 466 | |
AnnaBridge | 171:3a7713b1edbc | 467 | /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management |
AnnaBridge | 171:3a7713b1edbc | 468 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 469 | */ |
AnnaBridge | 171:3a7713b1edbc | 470 | |
AnnaBridge | 171:3a7713b1edbc | 471 | /** |
AnnaBridge | 171:3a7713b1edbc | 472 | * @brief Get Wake-up Flag |
AnnaBridge | 171:3a7713b1edbc | 473 | * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU |
AnnaBridge | 171:3a7713b1edbc | 474 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 475 | */ |
AnnaBridge | 171:3a7713b1edbc | 476 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) |
AnnaBridge | 171:3a7713b1edbc | 477 | { |
AnnaBridge | 171:3a7713b1edbc | 478 | return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); |
AnnaBridge | 171:3a7713b1edbc | 479 | } |
AnnaBridge | 171:3a7713b1edbc | 480 | |
AnnaBridge | 171:3a7713b1edbc | 481 | /** |
AnnaBridge | 171:3a7713b1edbc | 482 | * @brief Get Standby Flag |
AnnaBridge | 171:3a7713b1edbc | 483 | * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB |
AnnaBridge | 171:3a7713b1edbc | 484 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 485 | */ |
AnnaBridge | 171:3a7713b1edbc | 486 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) |
AnnaBridge | 171:3a7713b1edbc | 487 | { |
AnnaBridge | 171:3a7713b1edbc | 488 | return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); |
AnnaBridge | 171:3a7713b1edbc | 489 | } |
AnnaBridge | 171:3a7713b1edbc | 490 | |
AnnaBridge | 171:3a7713b1edbc | 491 | #if defined(PWR_PVD_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 492 | /** |
AnnaBridge | 171:3a7713b1edbc | 493 | * @brief Indicate whether VDD voltage is below the selected PVD threshold |
AnnaBridge | 171:3a7713b1edbc | 494 | * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO |
AnnaBridge | 171:3a7713b1edbc | 495 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 496 | */ |
AnnaBridge | 171:3a7713b1edbc | 497 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) |
AnnaBridge | 171:3a7713b1edbc | 498 | { |
AnnaBridge | 171:3a7713b1edbc | 499 | return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); |
AnnaBridge | 171:3a7713b1edbc | 500 | } |
AnnaBridge | 171:3a7713b1edbc | 501 | #endif /* PWR_PVD_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 502 | |
AnnaBridge | 171:3a7713b1edbc | 503 | #if defined(PWR_CSR_VREFINTRDYF) |
AnnaBridge | 171:3a7713b1edbc | 504 | /** |
AnnaBridge | 171:3a7713b1edbc | 505 | * @brief Get Internal Reference VrefInt Flag |
AnnaBridge | 171:3a7713b1edbc | 506 | * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY |
AnnaBridge | 171:3a7713b1edbc | 507 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 508 | */ |
AnnaBridge | 171:3a7713b1edbc | 509 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) |
AnnaBridge | 171:3a7713b1edbc | 510 | { |
AnnaBridge | 171:3a7713b1edbc | 511 | return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); |
AnnaBridge | 171:3a7713b1edbc | 512 | } |
AnnaBridge | 171:3a7713b1edbc | 513 | #endif /* PWR_CSR_VREFINTRDYF */ |
AnnaBridge | 171:3a7713b1edbc | 514 | /** |
AnnaBridge | 171:3a7713b1edbc | 515 | * @brief Clear Standby Flag |
AnnaBridge | 171:3a7713b1edbc | 516 | * @rmtoll CR CSBF LL_PWR_ClearFlag_SB |
AnnaBridge | 171:3a7713b1edbc | 517 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 518 | */ |
AnnaBridge | 171:3a7713b1edbc | 519 | __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) |
AnnaBridge | 171:3a7713b1edbc | 520 | { |
AnnaBridge | 171:3a7713b1edbc | 521 | SET_BIT(PWR->CR, PWR_CR_CSBF); |
AnnaBridge | 171:3a7713b1edbc | 522 | } |
AnnaBridge | 171:3a7713b1edbc | 523 | |
AnnaBridge | 171:3a7713b1edbc | 524 | /** |
AnnaBridge | 171:3a7713b1edbc | 525 | * @brief Clear Wake-up Flags |
AnnaBridge | 171:3a7713b1edbc | 526 | * @rmtoll CR CWUF LL_PWR_ClearFlag_WU |
AnnaBridge | 171:3a7713b1edbc | 527 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 528 | */ |
AnnaBridge | 171:3a7713b1edbc | 529 | __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) |
AnnaBridge | 171:3a7713b1edbc | 530 | { |
AnnaBridge | 171:3a7713b1edbc | 531 | SET_BIT(PWR->CR, PWR_CR_CWUF); |
AnnaBridge | 171:3a7713b1edbc | 532 | } |
AnnaBridge | 171:3a7713b1edbc | 533 | |
AnnaBridge | 171:3a7713b1edbc | 534 | /** |
AnnaBridge | 171:3a7713b1edbc | 535 | * @} |
AnnaBridge | 171:3a7713b1edbc | 536 | */ |
AnnaBridge | 171:3a7713b1edbc | 537 | |
AnnaBridge | 171:3a7713b1edbc | 538 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 539 | /** @defgroup PWR_LL_EF_Init De-initialization function |
AnnaBridge | 171:3a7713b1edbc | 540 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 541 | */ |
AnnaBridge | 171:3a7713b1edbc | 542 | ErrorStatus LL_PWR_DeInit(void); |
AnnaBridge | 171:3a7713b1edbc | 543 | /** |
AnnaBridge | 171:3a7713b1edbc | 544 | * @} |
AnnaBridge | 171:3a7713b1edbc | 545 | */ |
AnnaBridge | 171:3a7713b1edbc | 546 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 547 | |
AnnaBridge | 171:3a7713b1edbc | 548 | /** |
AnnaBridge | 171:3a7713b1edbc | 549 | * @} |
AnnaBridge | 171:3a7713b1edbc | 550 | */ |
AnnaBridge | 171:3a7713b1edbc | 551 | |
AnnaBridge | 171:3a7713b1edbc | 552 | /** |
AnnaBridge | 171:3a7713b1edbc | 553 | * @} |
AnnaBridge | 171:3a7713b1edbc | 554 | */ |
AnnaBridge | 171:3a7713b1edbc | 555 | |
AnnaBridge | 171:3a7713b1edbc | 556 | #endif /* defined(PWR) */ |
AnnaBridge | 171:3a7713b1edbc | 557 | |
AnnaBridge | 171:3a7713b1edbc | 558 | /** |
AnnaBridge | 171:3a7713b1edbc | 559 | * @} |
AnnaBridge | 171:3a7713b1edbc | 560 | */ |
AnnaBridge | 171:3a7713b1edbc | 561 | |
AnnaBridge | 171:3a7713b1edbc | 562 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 563 | } |
AnnaBridge | 171:3a7713b1edbc | 564 | #endif |
AnnaBridge | 171:3a7713b1edbc | 565 | |
AnnaBridge | 171:3a7713b1edbc | 566 | #endif /* __STM32F0xx_LL_PWR_H */ |
AnnaBridge | 171:3a7713b1edbc | 567 | |
AnnaBridge | 171:3a7713b1edbc | 568 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |