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TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l1xx_ll_fsmc.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32l1xx_ll_fsmc.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of FSMC HAL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32L1xx_LL_FSMC_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32L1xx_LL_FSMC_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32l1xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32L1xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 49 | */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | #if defined(FSMC_BANK1) |
| AnnaBridge | 171:3a7713b1edbc | 52 | |
| AnnaBridge | 171:3a7713b1edbc | 53 | /** @addtogroup FSMC_LL |
| AnnaBridge | 171:3a7713b1edbc | 54 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 55 | */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | |
| AnnaBridge | 171:3a7713b1edbc | 57 | /** @addtogroup FSMC_LL_Private_Macros |
| AnnaBridge | 171:3a7713b1edbc | 58 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 59 | */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | |
| AnnaBridge | 171:3a7713b1edbc | 61 | #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 62 | ((__BANK__) == FSMC_NORSRAM_BANK2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 63 | ((__BANK__) == FSMC_NORSRAM_BANK3) || \ |
| AnnaBridge | 171:3a7713b1edbc | 64 | ((__BANK__) == FSMC_NORSRAM_BANK4)) |
| AnnaBridge | 171:3a7713b1edbc | 65 | |
| AnnaBridge | 171:3a7713b1edbc | 66 | #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 67 | ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 68 | |
| AnnaBridge | 171:3a7713b1edbc | 69 | #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ |
| AnnaBridge | 171:3a7713b1edbc | 70 | ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
| AnnaBridge | 171:3a7713b1edbc | 71 | ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) |
| AnnaBridge | 171:3a7713b1edbc | 72 | |
| AnnaBridge | 171:3a7713b1edbc | 73 | #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 74 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| AnnaBridge | 171:3a7713b1edbc | 75 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| AnnaBridge | 171:3a7713b1edbc | 76 | |
| AnnaBridge | 171:3a7713b1edbc | 77 | #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 78 | ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 79 | |
| AnnaBridge | 171:3a7713b1edbc | 80 | #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ |
| AnnaBridge | 171:3a7713b1edbc | 81 | ((__MODE__) == FSMC_ACCESS_MODE_B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 82 | ((__MODE__) == FSMC_ACCESS_MODE_C) || \ |
| AnnaBridge | 171:3a7713b1edbc | 83 | ((__MODE__) == FSMC_ACCESS_MODE_D)) |
| AnnaBridge | 171:3a7713b1edbc | 84 | |
| AnnaBridge | 171:3a7713b1edbc | 85 | |
| AnnaBridge | 171:3a7713b1edbc | 86 | /** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance |
| AnnaBridge | 171:3a7713b1edbc | 87 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 88 | */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) |
| AnnaBridge | 171:3a7713b1edbc | 91 | |
| AnnaBridge | 171:3a7713b1edbc | 92 | /** |
| AnnaBridge | 171:3a7713b1edbc | 93 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 94 | */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | |
| AnnaBridge | 171:3a7713b1edbc | 96 | /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance |
| AnnaBridge | 171:3a7713b1edbc | 97 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 98 | */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) |
| AnnaBridge | 171:3a7713b1edbc | 101 | |
| AnnaBridge | 171:3a7713b1edbc | 102 | /** |
| AnnaBridge | 171:3a7713b1edbc | 103 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 104 | */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 107 | ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 108 | |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| AnnaBridge | 171:3a7713b1edbc | 110 | ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| AnnaBridge | 171:3a7713b1edbc | 111 | |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 113 | ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 114 | |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
| AnnaBridge | 171:3a7713b1edbc | 116 | ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) |
| AnnaBridge | 171:3a7713b1edbc | 117 | |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 119 | ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 120 | |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 122 | ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 123 | |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 125 | ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 126 | |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 128 | ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 129 | |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) |
| AnnaBridge | 171:3a7713b1edbc | 131 | |
| AnnaBridge | 171:3a7713b1edbc | 132 | /** @defgroup FSMC_Data_Latency FSMC Data Latency |
| AnnaBridge | 171:3a7713b1edbc | 133 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 134 | */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) |
| AnnaBridge | 171:3a7713b1edbc | 136 | /** |
| AnnaBridge | 171:3a7713b1edbc | 137 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 138 | */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | |
| AnnaBridge | 171:3a7713b1edbc | 140 | /** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time |
| AnnaBridge | 171:3a7713b1edbc | 141 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 142 | */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) |
| AnnaBridge | 171:3a7713b1edbc | 144 | /** |
| AnnaBridge | 171:3a7713b1edbc | 145 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 146 | */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | |
| AnnaBridge | 171:3a7713b1edbc | 148 | /** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time |
| AnnaBridge | 171:3a7713b1edbc | 149 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 150 | */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) |
| AnnaBridge | 171:3a7713b1edbc | 152 | /** |
| AnnaBridge | 171:3a7713b1edbc | 153 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 154 | */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | |
| AnnaBridge | 171:3a7713b1edbc | 156 | /** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time |
| AnnaBridge | 171:3a7713b1edbc | 157 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 158 | */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) |
| AnnaBridge | 171:3a7713b1edbc | 160 | /** |
| AnnaBridge | 171:3a7713b1edbc | 161 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 162 | */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | |
| AnnaBridge | 171:3a7713b1edbc | 164 | /** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration |
| AnnaBridge | 171:3a7713b1edbc | 165 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 166 | */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) |
| AnnaBridge | 171:3a7713b1edbc | 168 | /** |
| AnnaBridge | 171:3a7713b1edbc | 169 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 170 | */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | |
| AnnaBridge | 171:3a7713b1edbc | 172 | /** |
| AnnaBridge | 171:3a7713b1edbc | 173 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 174 | */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | |
| AnnaBridge | 171:3a7713b1edbc | 176 | /* Exported typedef ----------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 177 | |
| AnnaBridge | 171:3a7713b1edbc | 178 | /** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 179 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 180 | */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef |
| AnnaBridge | 171:3a7713b1edbc | 184 | |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
| AnnaBridge | 171:3a7713b1edbc | 187 | |
| AnnaBridge | 171:3a7713b1edbc | 188 | /** |
| AnnaBridge | 171:3a7713b1edbc | 189 | * @brief FSMC_NORSRAM Configuration Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 190 | */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 192 | { |
| AnnaBridge | 171:3a7713b1edbc | 193 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| AnnaBridge | 171:3a7713b1edbc | 194 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | |
| AnnaBridge | 171:3a7713b1edbc | 196 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
| AnnaBridge | 171:3a7713b1edbc | 197 | multiplexed on the data bus or not. |
| AnnaBridge | 171:3a7713b1edbc | 198 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | |
| AnnaBridge | 171:3a7713b1edbc | 200 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
| AnnaBridge | 171:3a7713b1edbc | 201 | the corresponding memory device. |
| AnnaBridge | 171:3a7713b1edbc | 202 | This parameter can be a value of @ref FSMC_Memory_Type */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | |
| AnnaBridge | 171:3a7713b1edbc | 204 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| AnnaBridge | 171:3a7713b1edbc | 205 | This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | |
| AnnaBridge | 171:3a7713b1edbc | 207 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| AnnaBridge | 171:3a7713b1edbc | 208 | valid only with synchronous burst Flash memories. |
| AnnaBridge | 171:3a7713b1edbc | 209 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | |
| AnnaBridge | 171:3a7713b1edbc | 211 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| AnnaBridge | 171:3a7713b1edbc | 212 | the Flash memory in burst mode. |
| AnnaBridge | 171:3a7713b1edbc | 213 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | |
| AnnaBridge | 171:3a7713b1edbc | 215 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
| AnnaBridge | 171:3a7713b1edbc | 216 | memory, valid only when accessing Flash memories in burst mode. |
| AnnaBridge | 171:3a7713b1edbc | 217 | This parameter can be a value of @ref FSMC_Wrap_Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | |
| AnnaBridge | 171:3a7713b1edbc | 219 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| AnnaBridge | 171:3a7713b1edbc | 220 | clock cycle before the wait state or during the wait state, |
| AnnaBridge | 171:3a7713b1edbc | 221 | valid only when accessing memories in burst mode. |
| AnnaBridge | 171:3a7713b1edbc | 222 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | |
| AnnaBridge | 171:3a7713b1edbc | 224 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
| AnnaBridge | 171:3a7713b1edbc | 225 | This parameter can be a value of @ref FSMC_Write_Operation */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | |
| AnnaBridge | 171:3a7713b1edbc | 227 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
| AnnaBridge | 171:3a7713b1edbc | 228 | signal, valid for Flash memory access in burst mode. |
| AnnaBridge | 171:3a7713b1edbc | 229 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | |
| AnnaBridge | 171:3a7713b1edbc | 231 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
| AnnaBridge | 171:3a7713b1edbc | 232 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | |
| AnnaBridge | 171:3a7713b1edbc | 234 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| AnnaBridge | 171:3a7713b1edbc | 235 | valid only with asynchronous Flash memories. |
| AnnaBridge | 171:3a7713b1edbc | 236 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | |
| AnnaBridge | 171:3a7713b1edbc | 238 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
| AnnaBridge | 171:3a7713b1edbc | 239 | This parameter can be a value of @ref FSMC_Write_Burst */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | |
| AnnaBridge | 171:3a7713b1edbc | 241 | }FSMC_NORSRAM_InitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 242 | |
| AnnaBridge | 171:3a7713b1edbc | 243 | /** |
| AnnaBridge | 171:3a7713b1edbc | 244 | * @brief FSMC_NORSRAM Timing parameters structure definition |
| AnnaBridge | 171:3a7713b1edbc | 245 | */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 247 | { |
| AnnaBridge | 171:3a7713b1edbc | 248 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 171:3a7713b1edbc | 249 | the duration of the address setup time. |
| AnnaBridge | 171:3a7713b1edbc | 250 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| AnnaBridge | 171:3a7713b1edbc | 251 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | |
| AnnaBridge | 171:3a7713b1edbc | 253 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 171:3a7713b1edbc | 254 | the duration of the address hold time. |
| AnnaBridge | 171:3a7713b1edbc | 255 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| AnnaBridge | 171:3a7713b1edbc | 256 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| AnnaBridge | 171:3a7713b1edbc | 257 | |
| AnnaBridge | 171:3a7713b1edbc | 258 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 171:3a7713b1edbc | 259 | the duration of the data setup time. |
| AnnaBridge | 171:3a7713b1edbc | 260 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| AnnaBridge | 171:3a7713b1edbc | 261 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| AnnaBridge | 171:3a7713b1edbc | 262 | NOR Flash memories. */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | |
| AnnaBridge | 171:3a7713b1edbc | 264 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 171:3a7713b1edbc | 265 | the duration of the bus turnaround. |
| AnnaBridge | 171:3a7713b1edbc | 266 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| AnnaBridge | 171:3a7713b1edbc | 267 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | |
| AnnaBridge | 171:3a7713b1edbc | 269 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
| AnnaBridge | 171:3a7713b1edbc | 270 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
| AnnaBridge | 171:3a7713b1edbc | 271 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| AnnaBridge | 171:3a7713b1edbc | 272 | accesses. */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | |
| AnnaBridge | 171:3a7713b1edbc | 274 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
| AnnaBridge | 171:3a7713b1edbc | 275 | to the memory before getting the first data. |
| AnnaBridge | 171:3a7713b1edbc | 276 | The parameter value depends on the memory type as shown below: |
| AnnaBridge | 171:3a7713b1edbc | 277 | - It must be set to 0 in case of a CRAM |
| AnnaBridge | 171:3a7713b1edbc | 278 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| AnnaBridge | 171:3a7713b1edbc | 279 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
| AnnaBridge | 171:3a7713b1edbc | 280 | with synchronous burst mode enable */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | |
| AnnaBridge | 171:3a7713b1edbc | 282 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
| AnnaBridge | 171:3a7713b1edbc | 283 | This parameter can be a value of @ref FSMC_Access_Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | |
| AnnaBridge | 171:3a7713b1edbc | 285 | }FSMC_NORSRAM_TimingTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 286 | |
| AnnaBridge | 171:3a7713b1edbc | 287 | /** |
| AnnaBridge | 171:3a7713b1edbc | 288 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 289 | */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | |
| AnnaBridge | 171:3a7713b1edbc | 291 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 292 | |
| AnnaBridge | 171:3a7713b1edbc | 293 | /** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 294 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 295 | */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | |
| AnnaBridge | 171:3a7713b1edbc | 297 | /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants |
| AnnaBridge | 171:3a7713b1edbc | 298 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 299 | */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | |
| AnnaBridge | 171:3a7713b1edbc | 301 | /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank |
| AnnaBridge | 171:3a7713b1edbc | 302 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 303 | */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define FSMC_NORSRAM_BANK1 (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define FSMC_NORSRAM_BANK2 (0x00000002U) |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define FSMC_NORSRAM_BANK3 (0x00000004U) |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define FSMC_NORSRAM_BANK4 (0x00000006U) |
| AnnaBridge | 171:3a7713b1edbc | 308 | |
| AnnaBridge | 171:3a7713b1edbc | 309 | /** |
| AnnaBridge | 171:3a7713b1edbc | 310 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 311 | */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | |
| AnnaBridge | 171:3a7713b1edbc | 313 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing |
| AnnaBridge | 171:3a7713b1edbc | 314 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 315 | */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN) |
| AnnaBridge | 171:3a7713b1edbc | 319 | |
| AnnaBridge | 171:3a7713b1edbc | 320 | /** |
| AnnaBridge | 171:3a7713b1edbc | 321 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 322 | */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | |
| AnnaBridge | 171:3a7713b1edbc | 324 | /** @defgroup FSMC_Memory_Type FSMC Memory Type |
| AnnaBridge | 171:3a7713b1edbc | 325 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 326 | */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define FSMC_MEMORY_TYPE_SRAM (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0) |
| AnnaBridge | 171:3a7713b1edbc | 330 | #define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1) |
| AnnaBridge | 171:3a7713b1edbc | 331 | |
| AnnaBridge | 171:3a7713b1edbc | 332 | /** |
| AnnaBridge | 171:3a7713b1edbc | 333 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 334 | */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | |
| AnnaBridge | 171:3a7713b1edbc | 336 | /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width |
| AnnaBridge | 171:3a7713b1edbc | 337 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 338 | */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0) |
| AnnaBridge | 171:3a7713b1edbc | 342 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1) |
| AnnaBridge | 171:3a7713b1edbc | 343 | |
| AnnaBridge | 171:3a7713b1edbc | 344 | /** |
| AnnaBridge | 171:3a7713b1edbc | 345 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 346 | */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | |
| AnnaBridge | 171:3a7713b1edbc | 348 | /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access |
| AnnaBridge | 171:3a7713b1edbc | 349 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 350 | */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN) |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 354 | /** |
| AnnaBridge | 171:3a7713b1edbc | 355 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 356 | */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | |
| AnnaBridge | 171:3a7713b1edbc | 358 | /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode |
| AnnaBridge | 171:3a7713b1edbc | 359 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 360 | */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN) |
| AnnaBridge | 171:3a7713b1edbc | 364 | |
| AnnaBridge | 171:3a7713b1edbc | 365 | /** |
| AnnaBridge | 171:3a7713b1edbc | 366 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 367 | */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | |
| AnnaBridge | 171:3a7713b1edbc | 369 | |
| AnnaBridge | 171:3a7713b1edbc | 370 | /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity |
| AnnaBridge | 171:3a7713b1edbc | 371 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 372 | */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | |
| AnnaBridge | 171:3a7713b1edbc | 374 | #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL) |
| AnnaBridge | 171:3a7713b1edbc | 376 | |
| AnnaBridge | 171:3a7713b1edbc | 377 | /** |
| AnnaBridge | 171:3a7713b1edbc | 378 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 379 | */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | |
| AnnaBridge | 171:3a7713b1edbc | 381 | /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode |
| AnnaBridge | 171:3a7713b1edbc | 382 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 383 | */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define FSMC_WRAP_MODE_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD) |
| AnnaBridge | 171:3a7713b1edbc | 387 | |
| AnnaBridge | 171:3a7713b1edbc | 388 | /** |
| AnnaBridge | 171:3a7713b1edbc | 389 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 390 | */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | |
| AnnaBridge | 171:3a7713b1edbc | 392 | /** @defgroup FSMC_Wait_Timing FSMC Wait Timing |
| AnnaBridge | 171:3a7713b1edbc | 393 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 394 | */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG) |
| AnnaBridge | 171:3a7713b1edbc | 398 | |
| AnnaBridge | 171:3a7713b1edbc | 399 | /** |
| AnnaBridge | 171:3a7713b1edbc | 400 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 401 | */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | |
| AnnaBridge | 171:3a7713b1edbc | 403 | /** @defgroup FSMC_Write_Operation FSMC Write Operation |
| AnnaBridge | 171:3a7713b1edbc | 404 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 405 | */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN) |
| AnnaBridge | 171:3a7713b1edbc | 409 | |
| AnnaBridge | 171:3a7713b1edbc | 410 | /** |
| AnnaBridge | 171:3a7713b1edbc | 411 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 412 | */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | |
| AnnaBridge | 171:3a7713b1edbc | 414 | /** @defgroup FSMC_Wait_Signal FSMC Wait Signal |
| AnnaBridge | 171:3a7713b1edbc | 415 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 416 | */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | |
| AnnaBridge | 171:3a7713b1edbc | 418 | #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN) |
| AnnaBridge | 171:3a7713b1edbc | 420 | |
| AnnaBridge | 171:3a7713b1edbc | 421 | /** |
| AnnaBridge | 171:3a7713b1edbc | 422 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 423 | */ |
| AnnaBridge | 171:3a7713b1edbc | 424 | |
| AnnaBridge | 171:3a7713b1edbc | 425 | /** @defgroup FSMC_Extended_Mode FSMC Extended Mode |
| AnnaBridge | 171:3a7713b1edbc | 426 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 427 | */ |
| AnnaBridge | 171:3a7713b1edbc | 428 | |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 430 | #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD) |
| AnnaBridge | 171:3a7713b1edbc | 431 | |
| AnnaBridge | 171:3a7713b1edbc | 432 | /** |
| AnnaBridge | 171:3a7713b1edbc | 433 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 434 | */ |
| AnnaBridge | 171:3a7713b1edbc | 435 | |
| AnnaBridge | 171:3a7713b1edbc | 436 | /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait |
| AnnaBridge | 171:3a7713b1edbc | 437 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 438 | */ |
| AnnaBridge | 171:3a7713b1edbc | 439 | |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT) |
| AnnaBridge | 171:3a7713b1edbc | 442 | |
| AnnaBridge | 171:3a7713b1edbc | 443 | /** |
| AnnaBridge | 171:3a7713b1edbc | 444 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 445 | */ |
| AnnaBridge | 171:3a7713b1edbc | 446 | |
| AnnaBridge | 171:3a7713b1edbc | 447 | /** @defgroup FSMC_Write_Burst FSMC Write Burst |
| AnnaBridge | 171:3a7713b1edbc | 448 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 449 | */ |
| AnnaBridge | 171:3a7713b1edbc | 450 | |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define FSMC_WRITE_BURST_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW) |
| AnnaBridge | 171:3a7713b1edbc | 453 | |
| AnnaBridge | 171:3a7713b1edbc | 454 | /** |
| AnnaBridge | 171:3a7713b1edbc | 455 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 456 | */ |
| AnnaBridge | 171:3a7713b1edbc | 457 | |
| AnnaBridge | 171:3a7713b1edbc | 458 | /** @defgroup FSMC_Access_Mode FSMC Access Mode |
| AnnaBridge | 171:3a7713b1edbc | 459 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 460 | */ |
| AnnaBridge | 171:3a7713b1edbc | 461 | |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define FSMC_ACCESS_MODE_A (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0) |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1) |
| AnnaBridge | 171:3a7713b1edbc | 465 | #define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1)) |
| AnnaBridge | 171:3a7713b1edbc | 466 | |
| AnnaBridge | 171:3a7713b1edbc | 467 | /** |
| AnnaBridge | 171:3a7713b1edbc | 468 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 469 | */ |
| AnnaBridge | 171:3a7713b1edbc | 470 | |
| AnnaBridge | 171:3a7713b1edbc | 471 | /** |
| AnnaBridge | 171:3a7713b1edbc | 472 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 473 | */ |
| AnnaBridge | 171:3a7713b1edbc | 474 | |
| AnnaBridge | 171:3a7713b1edbc | 475 | |
| AnnaBridge | 171:3a7713b1edbc | 476 | /** |
| AnnaBridge | 171:3a7713b1edbc | 477 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 478 | */ |
| AnnaBridge | 171:3a7713b1edbc | 479 | |
| AnnaBridge | 171:3a7713b1edbc | 480 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 481 | |
| AnnaBridge | 171:3a7713b1edbc | 482 | /** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 483 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 484 | */ |
| AnnaBridge | 171:3a7713b1edbc | 485 | |
| AnnaBridge | 171:3a7713b1edbc | 486 | /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 487 | * @brief macros to handle NOR device enable/disable and read/write operations |
| AnnaBridge | 171:3a7713b1edbc | 488 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 489 | */ |
| AnnaBridge | 171:3a7713b1edbc | 490 | |
| AnnaBridge | 171:3a7713b1edbc | 491 | /** |
| AnnaBridge | 171:3a7713b1edbc | 492 | * @brief Enable the NORSRAM device access. |
| AnnaBridge | 171:3a7713b1edbc | 493 | * @param __INSTANCE__ FSMC_NORSRAM Instance |
| AnnaBridge | 171:3a7713b1edbc | 494 | * @param __BANK__ FSMC_NORSRAM Bank |
| AnnaBridge | 171:3a7713b1edbc | 495 | * @retval none |
| AnnaBridge | 171:3a7713b1edbc | 496 | */ |
| AnnaBridge | 171:3a7713b1edbc | 497 | #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) |
| AnnaBridge | 171:3a7713b1edbc | 498 | |
| AnnaBridge | 171:3a7713b1edbc | 499 | /** |
| AnnaBridge | 171:3a7713b1edbc | 500 | * @brief Disable the NORSRAM device access. |
| AnnaBridge | 171:3a7713b1edbc | 501 | * @param __INSTANCE__ FSMC_NORSRAM Instance |
| AnnaBridge | 171:3a7713b1edbc | 502 | * @param __BANK__ FSMC_NORSRAM Bank |
| AnnaBridge | 171:3a7713b1edbc | 503 | * @retval none |
| AnnaBridge | 171:3a7713b1edbc | 504 | */ |
| AnnaBridge | 171:3a7713b1edbc | 505 | #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) |
| AnnaBridge | 171:3a7713b1edbc | 506 | |
| AnnaBridge | 171:3a7713b1edbc | 507 | /** |
| AnnaBridge | 171:3a7713b1edbc | 508 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 509 | */ |
| AnnaBridge | 171:3a7713b1edbc | 510 | |
| AnnaBridge | 171:3a7713b1edbc | 511 | |
| AnnaBridge | 171:3a7713b1edbc | 512 | /** |
| AnnaBridge | 171:3a7713b1edbc | 513 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 514 | */ |
| AnnaBridge | 171:3a7713b1edbc | 515 | |
| AnnaBridge | 171:3a7713b1edbc | 516 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 517 | |
| AnnaBridge | 171:3a7713b1edbc | 518 | /** @addtogroup FSMC_LL_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 519 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 520 | */ |
| AnnaBridge | 171:3a7713b1edbc | 521 | |
| AnnaBridge | 171:3a7713b1edbc | 522 | /** @addtogroup FSMC_NORSRAM |
| AnnaBridge | 171:3a7713b1edbc | 523 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 524 | */ |
| AnnaBridge | 171:3a7713b1edbc | 525 | |
| AnnaBridge | 171:3a7713b1edbc | 526 | /** @addtogroup FSMC_NORSRAM_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 527 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 528 | */ |
| AnnaBridge | 171:3a7713b1edbc | 529 | |
| AnnaBridge | 171:3a7713b1edbc | 530 | /* FSMC_NORSRAM Controller functions ******************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 531 | /* Initialization/de-initialization functions */ |
| AnnaBridge | 171:3a7713b1edbc | 532 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); |
| AnnaBridge | 171:3a7713b1edbc | 533 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| AnnaBridge | 171:3a7713b1edbc | 534 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
| AnnaBridge | 171:3a7713b1edbc | 535 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| AnnaBridge | 171:3a7713b1edbc | 536 | |
| AnnaBridge | 171:3a7713b1edbc | 537 | /** |
| AnnaBridge | 171:3a7713b1edbc | 538 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 539 | */ |
| AnnaBridge | 171:3a7713b1edbc | 540 | |
| AnnaBridge | 171:3a7713b1edbc | 541 | /** @addtogroup FSMC_NORSRAM_Group2 |
| AnnaBridge | 171:3a7713b1edbc | 542 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 543 | */ |
| AnnaBridge | 171:3a7713b1edbc | 544 | |
| AnnaBridge | 171:3a7713b1edbc | 545 | /* FSMC_NORSRAM Control functions */ |
| AnnaBridge | 171:3a7713b1edbc | 546 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 171:3a7713b1edbc | 547 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 171:3a7713b1edbc | 548 | |
| AnnaBridge | 171:3a7713b1edbc | 549 | /** |
| AnnaBridge | 171:3a7713b1edbc | 550 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 551 | */ |
| AnnaBridge | 171:3a7713b1edbc | 552 | |
| AnnaBridge | 171:3a7713b1edbc | 553 | /** |
| AnnaBridge | 171:3a7713b1edbc | 554 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 555 | */ |
| AnnaBridge | 171:3a7713b1edbc | 556 | |
| AnnaBridge | 171:3a7713b1edbc | 557 | /** |
| AnnaBridge | 171:3a7713b1edbc | 558 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 559 | */ |
| AnnaBridge | 171:3a7713b1edbc | 560 | |
| AnnaBridge | 171:3a7713b1edbc | 561 | /** |
| AnnaBridge | 171:3a7713b1edbc | 562 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 563 | */ |
| AnnaBridge | 171:3a7713b1edbc | 564 | |
| AnnaBridge | 171:3a7713b1edbc | 565 | #endif /* FSMC_BANK1 */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | |
| AnnaBridge | 171:3a7713b1edbc | 567 | /** |
| AnnaBridge | 171:3a7713b1edbc | 568 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 569 | */ |
| AnnaBridge | 171:3a7713b1edbc | 570 | |
| AnnaBridge | 171:3a7713b1edbc | 571 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 572 | } |
| AnnaBridge | 171:3a7713b1edbc | 573 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 574 | |
| AnnaBridge | 171:3a7713b1edbc | 575 | #endif /* __STM32L1xx_LL_FSMC_H */ |
| AnnaBridge | 171:3a7713b1edbc | 576 | |
| AnnaBridge | 171:3a7713b1edbc | 577 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 171:3a7713b1edbc | 578 |
