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TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/stm32l1xx_ll_rcc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32l1xx_ll_rcc.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of RCC LL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32L1xx_LL_RCC_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32L1xx_LL_RCC_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32l1xx.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32L1xx_LL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	#if defined(RCC)
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	/** @defgroup RCC_LL RCC
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	59	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	60	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
AnnaBridge	171:3a7713b1edbc	61	* @{
AnnaBridge	171:3a7713b1edbc	62	*/
AnnaBridge	171:3a7713b1edbc	63	/* Defines used for the bit position in the register and perform offsets*/
AnnaBridge	171:3a7713b1edbc	64	#define RCC_POSITION_MSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL) /!< field position in register RCC_ICSCR /
AnnaBridge	171:3a7713b1edbc	65	#define RCC_POSITION_MSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM) /!< field position in register RCC_ICSCR /
AnnaBridge	171:3a7713b1edbc	66	#define RCC_POSITION_MSIRANGE (uint32_t)POSITION_VAL(RCC_ICSCR_MSIRANGE) /!< field position in register RCC_ICSCR /
AnnaBridge	171:3a7713b1edbc	67	#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /!< field position in register RCC_CFGR /
AnnaBridge	171:3a7713b1edbc	68	#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /!< field position in register RCC_CFGR /
AnnaBridge	171:3a7713b1edbc	69	#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /!< field position in register RCC_CFGR /
AnnaBridge	171:3a7713b1edbc	70	#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL) /!< field position in register RCC_ICSCR /
AnnaBridge	171:3a7713b1edbc	71	#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM) /!< field position in register RCC_ICSCR /
AnnaBridge	171:3a7713b1edbc	72	#define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /!< field position in register RCC_CFGR /
AnnaBridge	171:3a7713b1edbc	73	#define RCC_POSITION_PLLDIV (uint32_t)POSITION_VAL(RCC_CFGR_PLLDIV) /!< field position in register RCC_CFGR /
AnnaBridge	171:3a7713b1edbc	74
AnnaBridge	171:3a7713b1edbc	75	/**
AnnaBridge	171:3a7713b1edbc	76	* @}
AnnaBridge	171:3a7713b1edbc	77	*/
AnnaBridge	171:3a7713b1edbc	78
AnnaBridge	171:3a7713b1edbc	79	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	80	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	81	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	82	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
AnnaBridge	171:3a7713b1edbc	83	* @{
AnnaBridge	171:3a7713b1edbc	84	*/
AnnaBridge	171:3a7713b1edbc	85
AnnaBridge	171:3a7713b1edbc	86	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
AnnaBridge	171:3a7713b1edbc	87	* @{
AnnaBridge	171:3a7713b1edbc	88	*/
AnnaBridge	171:3a7713b1edbc	89
AnnaBridge	171:3a7713b1edbc	90	/**
AnnaBridge	171:3a7713b1edbc	91	* @brief RCC Clocks Frequency Structure
AnnaBridge	171:3a7713b1edbc	92	*/
AnnaBridge	171:3a7713b1edbc	93	typedef struct
AnnaBridge	171:3a7713b1edbc	94	{
AnnaBridge	171:3a7713b1edbc	95	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
AnnaBridge	171:3a7713b1edbc	96	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
AnnaBridge	171:3a7713b1edbc	97	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
AnnaBridge	171:3a7713b1edbc	98	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
AnnaBridge	171:3a7713b1edbc	99	} LL_RCC_ClocksTypeDef;
AnnaBridge	171:3a7713b1edbc	100
AnnaBridge	171:3a7713b1edbc	101	/**
AnnaBridge	171:3a7713b1edbc	102	* @}
AnnaBridge	171:3a7713b1edbc	103	*/
AnnaBridge	171:3a7713b1edbc	104
AnnaBridge	171:3a7713b1edbc	105	/**
AnnaBridge	171:3a7713b1edbc	106	* @}
AnnaBridge	171:3a7713b1edbc	107	*/
AnnaBridge	171:3a7713b1edbc	108	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	109
AnnaBridge	171:3a7713b1edbc	110	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	111	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
AnnaBridge	171:3a7713b1edbc	112	* @{
AnnaBridge	171:3a7713b1edbc	113	*/
AnnaBridge	171:3a7713b1edbc	114
AnnaBridge	171:3a7713b1edbc	115	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
AnnaBridge	171:3a7713b1edbc	116	* @brief Defines used to adapt values of different oscillators
AnnaBridge	171:3a7713b1edbc	117	* @note These values could be modified in the user environment according to
AnnaBridge	171:3a7713b1edbc	118	* HW set-up.
AnnaBridge	171:3a7713b1edbc	119	* @{
AnnaBridge	171:3a7713b1edbc	120	*/
AnnaBridge	171:3a7713b1edbc	121	#if !defined (HSE_VALUE)
AnnaBridge	171:3a7713b1edbc	122	#define HSE_VALUE 8000000U /!< Value of the HSE oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	123	#endif /* HSE_VALUE */
AnnaBridge	171:3a7713b1edbc	124
AnnaBridge	171:3a7713b1edbc	125	#if !defined (HSI_VALUE)
AnnaBridge	171:3a7713b1edbc	126	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	127	#endif /* HSI_VALUE */
AnnaBridge	171:3a7713b1edbc	128
AnnaBridge	171:3a7713b1edbc	129	#if !defined (LSE_VALUE)
AnnaBridge	171:3a7713b1edbc	130	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	131	#endif /* LSE_VALUE */
AnnaBridge	171:3a7713b1edbc	132
AnnaBridge	171:3a7713b1edbc	133	#if !defined (LSI_VALUE)
AnnaBridge	171:3a7713b1edbc	134	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	135	#endif /* LSI_VALUE */
AnnaBridge	171:3a7713b1edbc	136	/**
AnnaBridge	171:3a7713b1edbc	137	* @}
AnnaBridge	171:3a7713b1edbc	138	*/
AnnaBridge	171:3a7713b1edbc	139
AnnaBridge	171:3a7713b1edbc	140	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	171:3a7713b1edbc	141	* @brief Flags defines which can be used with LL_RCC_WriteReg function
AnnaBridge	171:3a7713b1edbc	142	* @{
AnnaBridge	171:3a7713b1edbc	143	*/
AnnaBridge	171:3a7713b1edbc	144	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	145	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	146	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	147	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	148	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	149	#define LL_RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC /!< MSI Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	150	#if defined(RCC_LSECSS_SUPPORT)
AnnaBridge	171:3a7713b1edbc	151	#define LL_RCC_CIR_LSECSSC RCC_CIR_LSECSSC /!< LSE Clock Security System Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	152	#endif /* RCC_LSECSS_SUPPORT */
AnnaBridge	171:3a7713b1edbc	153	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	154	/**
AnnaBridge	171:3a7713b1edbc	155	* @}
AnnaBridge	171:3a7713b1edbc	156	*/
AnnaBridge	171:3a7713b1edbc	157
AnnaBridge	171:3a7713b1edbc	158	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	171:3a7713b1edbc	159	* @brief Flags defines which can be used with LL_RCC_ReadReg function
AnnaBridge	171:3a7713b1edbc	160	* @{
AnnaBridge	171:3a7713b1edbc	161	*/
AnnaBridge	171:3a7713b1edbc	162	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	163	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	164	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	165	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	166	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	167	#define LL_RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF /!< MSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	168	#if defined(RCC_LSECSS_SUPPORT)
AnnaBridge	171:3a7713b1edbc	169	#define LL_RCC_CIR_LSECSSF RCC_CIR_LSECSSF /!< LSE Clock Security System Interrupt flag /
AnnaBridge	171:3a7713b1edbc	170	#endif /* RCC_LSECSS_SUPPORT */
AnnaBridge	171:3a7713b1edbc	171	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
AnnaBridge	171:3a7713b1edbc	172	#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /!< OBL reset flag /
AnnaBridge	171:3a7713b1edbc	173	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
AnnaBridge	171:3a7713b1edbc	174	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
AnnaBridge	171:3a7713b1edbc	175	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
AnnaBridge	171:3a7713b1edbc	176	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
AnnaBridge	171:3a7713b1edbc	177	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
AnnaBridge	171:3a7713b1edbc	178	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
AnnaBridge	171:3a7713b1edbc	179	/**
AnnaBridge	171:3a7713b1edbc	180	* @}
AnnaBridge	171:3a7713b1edbc	181	*/
AnnaBridge	171:3a7713b1edbc	182
AnnaBridge	171:3a7713b1edbc	183	/** @defgroup RCC_LL_EC_IT IT Defines
AnnaBridge	171:3a7713b1edbc	184	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
AnnaBridge	171:3a7713b1edbc	185	* @{
AnnaBridge	171:3a7713b1edbc	186	*/
AnnaBridge	171:3a7713b1edbc	187	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	188	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	189	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	190	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	191	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	192	#define LL_RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE /!< MSI Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	193	#if defined(RCC_LSECSS_SUPPORT)
AnnaBridge	171:3a7713b1edbc	194	#define LL_RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE /!< LSE CSS Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	195	#endif /* RCC_LSECSS_SUPPORT */
AnnaBridge	171:3a7713b1edbc	196	/**
AnnaBridge	171:3a7713b1edbc	197	* @}
AnnaBridge	171:3a7713b1edbc	198	*/
AnnaBridge	171:3a7713b1edbc	199
AnnaBridge	171:3a7713b1edbc	200	/** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
AnnaBridge	171:3a7713b1edbc	201	* @{
AnnaBridge	171:3a7713b1edbc	202	*/
AnnaBridge	171:3a7713b1edbc	203	#define LL_RCC_RTC_HSE_DIV_2 0x00000000U /!< HSE is divided by 2 for RTC clock /
AnnaBridge	171:3a7713b1edbc	204	#define LL_RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /!< HSE is divided by 4 for RTC clock /
AnnaBridge	171:3a7713b1edbc	205	#define LL_RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /!< HSE is divided by 8 for RTC clock /
AnnaBridge	171:3a7713b1edbc	206	#define LL_RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /!< HSE is divided by 16 for RTC clock /
AnnaBridge	171:3a7713b1edbc	207	/**
AnnaBridge	171:3a7713b1edbc	208	* @}
AnnaBridge	171:3a7713b1edbc	209	*/
AnnaBridge	171:3a7713b1edbc	210
AnnaBridge	171:3a7713b1edbc	211	/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
AnnaBridge	171:3a7713b1edbc	212	* @{
AnnaBridge	171:3a7713b1edbc	213	*/
AnnaBridge	171:3a7713b1edbc	214	#define LL_RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
AnnaBridge	171:3a7713b1edbc	215	#define LL_RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz/
AnnaBridge	171:3a7713b1edbc	216	#define LL_RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
AnnaBridge	171:3a7713b1edbc	217	#define LL_RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
AnnaBridge	171:3a7713b1edbc	218	#define LL_RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
AnnaBridge	171:3a7713b1edbc	219	#define LL_RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
AnnaBridge	171:3a7713b1edbc	220	#define LL_RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
AnnaBridge	171:3a7713b1edbc	221	/**
AnnaBridge	171:3a7713b1edbc	222	* @}
AnnaBridge	171:3a7713b1edbc	223	*/
AnnaBridge	171:3a7713b1edbc	224
AnnaBridge	171:3a7713b1edbc	225	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
AnnaBridge	171:3a7713b1edbc	226	* @{
AnnaBridge	171:3a7713b1edbc	227	*/
AnnaBridge	171:3a7713b1edbc	228	#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
AnnaBridge	171:3a7713b1edbc	229	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	171:3a7713b1edbc	230	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	171:3a7713b1edbc	231	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	171:3a7713b1edbc	232	/**
AnnaBridge	171:3a7713b1edbc	233	* @}
AnnaBridge	171:3a7713b1edbc	234	*/
AnnaBridge	171:3a7713b1edbc	235
AnnaBridge	171:3a7713b1edbc	236	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
AnnaBridge	171:3a7713b1edbc	237	* @{
AnnaBridge	171:3a7713b1edbc	238	*/
AnnaBridge	171:3a7713b1edbc	239	#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
AnnaBridge	171:3a7713b1edbc	240	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	171:3a7713b1edbc	241	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	171:3a7713b1edbc	242	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	171:3a7713b1edbc	243	/**
AnnaBridge	171:3a7713b1edbc	244	* @}
AnnaBridge	171:3a7713b1edbc	245	*/
AnnaBridge	171:3a7713b1edbc	246
AnnaBridge	171:3a7713b1edbc	247	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
AnnaBridge	171:3a7713b1edbc	248	* @{
AnnaBridge	171:3a7713b1edbc	249	*/
AnnaBridge	171:3a7713b1edbc	250	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	171:3a7713b1edbc	251	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	252	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	253	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	254	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	255	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	171:3a7713b1edbc	256	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	171:3a7713b1edbc	257	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	171:3a7713b1edbc	258	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	171:3a7713b1edbc	259	/**
AnnaBridge	171:3a7713b1edbc	260	* @}
AnnaBridge	171:3a7713b1edbc	261	*/
AnnaBridge	171:3a7713b1edbc	262
AnnaBridge	171:3a7713b1edbc	263	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
AnnaBridge	171:3a7713b1edbc	264	* @{
AnnaBridge	171:3a7713b1edbc	265	*/
AnnaBridge	171:3a7713b1edbc	266	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	171:3a7713b1edbc	267	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	268	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	269	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	270	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	271	/**
AnnaBridge	171:3a7713b1edbc	272	* @}
AnnaBridge	171:3a7713b1edbc	273	*/
AnnaBridge	171:3a7713b1edbc	274
AnnaBridge	171:3a7713b1edbc	275	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
AnnaBridge	171:3a7713b1edbc	276	* @{
AnnaBridge	171:3a7713b1edbc	277	*/
AnnaBridge	171:3a7713b1edbc	278	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
AnnaBridge	171:3a7713b1edbc	279	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	280	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	281	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	282	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	283	/**
AnnaBridge	171:3a7713b1edbc	284	* @}
AnnaBridge	171:3a7713b1edbc	285	*/
AnnaBridge	171:3a7713b1edbc	286
AnnaBridge	171:3a7713b1edbc	287	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
AnnaBridge	171:3a7713b1edbc	288	* @{
AnnaBridge	171:3a7713b1edbc	289	*/
AnnaBridge	171:3a7713b1edbc	290	#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /!< MCO output disabled, no clock on MCO /
AnnaBridge	171:3a7713b1edbc	291	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /!< SYSCLK selection as MCO source /
AnnaBridge	171:3a7713b1edbc	292	#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /!< HSI selection as MCO source /
AnnaBridge	171:3a7713b1edbc	293	#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_MSI /!< MSI selection as MCO source /
AnnaBridge	171:3a7713b1edbc	294	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /!< HSE selection as MCO source /
AnnaBridge	171:3a7713b1edbc	295	#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /!< LSI selection as MCO source /
AnnaBridge	171:3a7713b1edbc	296	#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /!< LSE selection as MCO source /
AnnaBridge	171:3a7713b1edbc	297	#define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /!< PLLCLK selection as MCO source /
AnnaBridge	171:3a7713b1edbc	298	/**
AnnaBridge	171:3a7713b1edbc	299	* @}
AnnaBridge	171:3a7713b1edbc	300	*/
AnnaBridge	171:3a7713b1edbc	301
AnnaBridge	171:3a7713b1edbc	302	/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
AnnaBridge	171:3a7713b1edbc	303	* @{
AnnaBridge	171:3a7713b1edbc	304	*/
AnnaBridge	171:3a7713b1edbc	305	#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO Clock divided by 1 /
AnnaBridge	171:3a7713b1edbc	306	#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO Clock divided by 2 /
AnnaBridge	171:3a7713b1edbc	307	#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO Clock divided by 4 /
AnnaBridge	171:3a7713b1edbc	308	#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO Clock divided by 8 /
AnnaBridge	171:3a7713b1edbc	309	#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO Clock divided by 16 /
AnnaBridge	171:3a7713b1edbc	310	/**
AnnaBridge	171:3a7713b1edbc	311	* @}
AnnaBridge	171:3a7713b1edbc	312	*/
AnnaBridge	171:3a7713b1edbc	313	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	314	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
AnnaBridge	171:3a7713b1edbc	315	* @{
AnnaBridge	171:3a7713b1edbc	316	*/
AnnaBridge	171:3a7713b1edbc	317	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	171:3a7713b1edbc	318	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
AnnaBridge	171:3a7713b1edbc	319	/**
AnnaBridge	171:3a7713b1edbc	320	* @}
AnnaBridge	171:3a7713b1edbc	321	*/
AnnaBridge	171:3a7713b1edbc	322	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	323
AnnaBridge	171:3a7713b1edbc	324
AnnaBridge	171:3a7713b1edbc	325
AnnaBridge	171:3a7713b1edbc	326	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
AnnaBridge	171:3a7713b1edbc	327	* @{
AnnaBridge	171:3a7713b1edbc	328	*/
AnnaBridge	171:3a7713b1edbc	329	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	330	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	331	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	332	#define LL_RCC_RTC_CLKSOURCE_HSE RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by a programmable prescaler
AnnaBridge	171:3a7713b1edbc	333	(selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */
AnnaBridge	171:3a7713b1edbc	334	/**
AnnaBridge	171:3a7713b1edbc	335	* @}
AnnaBridge	171:3a7713b1edbc	336	*/
AnnaBridge	171:3a7713b1edbc	337
AnnaBridge	171:3a7713b1edbc	338	/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
AnnaBridge	171:3a7713b1edbc	339	* @{
AnnaBridge	171:3a7713b1edbc	340	*/
AnnaBridge	171:3a7713b1edbc	341	#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /!< PLL input clock 3 */
AnnaBridge	171:3a7713b1edbc	342	#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /!< PLL input clock 4 */
AnnaBridge	171:3a7713b1edbc	343	#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /!< PLL input clock 6 */
AnnaBridge	171:3a7713b1edbc	344	#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /!< PLL input clock 8 */
AnnaBridge	171:3a7713b1edbc	345	#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /!< PLL input clock 12 */
AnnaBridge	171:3a7713b1edbc	346	#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /!< PLL input clock 16 */
AnnaBridge	171:3a7713b1edbc	347	#define LL_RCC_PLL_MUL_24 RCC_CFGR_PLLMUL24 /!< PLL input clock 24 */
AnnaBridge	171:3a7713b1edbc	348	#define LL_RCC_PLL_MUL_32 RCC_CFGR_PLLMUL32 /!< PLL input clock 32 */
AnnaBridge	171:3a7713b1edbc	349	#define LL_RCC_PLL_MUL_48 RCC_CFGR_PLLMUL48 /!< PLL input clock 48 */
AnnaBridge	171:3a7713b1edbc	350	/**
AnnaBridge	171:3a7713b1edbc	351	* @}
AnnaBridge	171:3a7713b1edbc	352	*/
AnnaBridge	171:3a7713b1edbc	353
AnnaBridge	171:3a7713b1edbc	354	/** @defgroup RCC_LL_EC_PLL_DIV PLL division factor
AnnaBridge	171:3a7713b1edbc	355	* @{
AnnaBridge	171:3a7713b1edbc	356	*/
AnnaBridge	171:3a7713b1edbc	357	#define LL_RCC_PLL_DIV_2 RCC_CFGR_PLLDIV2 /!< PLL clock output = PLLVCO / 2 /
AnnaBridge	171:3a7713b1edbc	358	#define LL_RCC_PLL_DIV_3 RCC_CFGR_PLLDIV3 /!< PLL clock output = PLLVCO / 3 /
AnnaBridge	171:3a7713b1edbc	359	#define LL_RCC_PLL_DIV_4 RCC_CFGR_PLLDIV4 /!< PLL clock output = PLLVCO / 4 /
AnnaBridge	171:3a7713b1edbc	360	/**
AnnaBridge	171:3a7713b1edbc	361	* @}
AnnaBridge	171:3a7713b1edbc	362	*/
AnnaBridge	171:3a7713b1edbc	363
AnnaBridge	171:3a7713b1edbc	364	/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
AnnaBridge	171:3a7713b1edbc	365	* @{
AnnaBridge	171:3a7713b1edbc	366	*/
AnnaBridge	171:3a7713b1edbc	367	#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	368	#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	369	/**
AnnaBridge	171:3a7713b1edbc	370	* @}
AnnaBridge	171:3a7713b1edbc	371	*/
AnnaBridge	171:3a7713b1edbc	372
AnnaBridge	171:3a7713b1edbc	373	/**
AnnaBridge	171:3a7713b1edbc	374	* @}
AnnaBridge	171:3a7713b1edbc	375	*/
AnnaBridge	171:3a7713b1edbc	376
AnnaBridge	171:3a7713b1edbc	377	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	378	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
AnnaBridge	171:3a7713b1edbc	379	* @{
AnnaBridge	171:3a7713b1edbc	380	*/
AnnaBridge	171:3a7713b1edbc	381
AnnaBridge	171:3a7713b1edbc	382	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	171:3a7713b1edbc	383	* @{
AnnaBridge	171:3a7713b1edbc	384	*/
AnnaBridge	171:3a7713b1edbc	385
AnnaBridge	171:3a7713b1edbc	386	/**
AnnaBridge	171:3a7713b1edbc	387	* @brief Write a value in RCC register
AnnaBridge	171:3a7713b1edbc	388	* @param __REG__ Register to be written
AnnaBridge	171:3a7713b1edbc	389	* @param __VALUE__ Value to be written in the register
AnnaBridge	171:3a7713b1edbc	390	* @retval None
AnnaBridge	171:3a7713b1edbc	391	*/
AnnaBridge	171:3a7713b1edbc	392	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
AnnaBridge	171:3a7713b1edbc	393
AnnaBridge	171:3a7713b1edbc	394	/**
AnnaBridge	171:3a7713b1edbc	395	* @brief Read a value in RCC register
AnnaBridge	171:3a7713b1edbc	396	* @param __REG__ Register to be read
AnnaBridge	171:3a7713b1edbc	397	* @retval Register value
AnnaBridge	171:3a7713b1edbc	398	*/
AnnaBridge	171:3a7713b1edbc	399	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
AnnaBridge	171:3a7713b1edbc	400	/**
AnnaBridge	171:3a7713b1edbc	401	* @}
AnnaBridge	171:3a7713b1edbc	402	*/
AnnaBridge	171:3a7713b1edbc	403
AnnaBridge	171:3a7713b1edbc	404	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
AnnaBridge	171:3a7713b1edbc	405	* @{
AnnaBridge	171:3a7713b1edbc	406	*/
AnnaBridge	171:3a7713b1edbc	407
AnnaBridge	171:3a7713b1edbc	408	/**
AnnaBridge	171:3a7713b1edbc	409	* @brief Helper macro to calculate the PLLCLK frequency
AnnaBridge	171:3a7713b1edbc	410	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,
AnnaBridge	171:3a7713b1edbc	411	* @ref LL_RCC_PLL_GetMultiplicator (),
AnnaBridge	171:3a7713b1edbc	412	* @ref LL_RCC_PLL_GetDivider ());
AnnaBridge	171:3a7713b1edbc	413	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	171:3a7713b1edbc	414	* @param __PLLMUL__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	415	* @arg @ref LL_RCC_PLL_MUL_3
AnnaBridge	171:3a7713b1edbc	416	* @arg @ref LL_RCC_PLL_MUL_4
AnnaBridge	171:3a7713b1edbc	417	* @arg @ref LL_RCC_PLL_MUL_6
AnnaBridge	171:3a7713b1edbc	418	* @arg @ref LL_RCC_PLL_MUL_8
AnnaBridge	171:3a7713b1edbc	419	* @arg @ref LL_RCC_PLL_MUL_12
AnnaBridge	171:3a7713b1edbc	420	* @arg @ref LL_RCC_PLL_MUL_16
AnnaBridge	171:3a7713b1edbc	421	* @arg @ref LL_RCC_PLL_MUL_24
AnnaBridge	171:3a7713b1edbc	422	* @arg @ref LL_RCC_PLL_MUL_32
AnnaBridge	171:3a7713b1edbc	423	* @arg @ref LL_RCC_PLL_MUL_48
AnnaBridge	171:3a7713b1edbc	424	* @param __PLLDIV__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	425	* @arg @ref LL_RCC_PLL_DIV_2
AnnaBridge	171:3a7713b1edbc	426	* @arg @ref LL_RCC_PLL_DIV_3
AnnaBridge	171:3a7713b1edbc	427	* @arg @ref LL_RCC_PLL_DIV_4
AnnaBridge	171:3a7713b1edbc	428	* @retval PLL clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	429	*/
AnnaBridge	171:3a7713b1edbc	430	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_POSITION_PLLMUL]) / (((__PLLDIV__) >> RCC_POSITION_PLLDIV)+1U))
AnnaBridge	171:3a7713b1edbc	431
AnnaBridge	171:3a7713b1edbc	432	/**
AnnaBridge	171:3a7713b1edbc	433	* @brief Helper macro to calculate the HCLK frequency
AnnaBridge	171:3a7713b1edbc	434	* @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
AnnaBridge	171:3a7713b1edbc	435	* ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
AnnaBridge	171:3a7713b1edbc	436	* @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
AnnaBridge	171:3a7713b1edbc	437	* @param __AHBPRESCALER__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	438	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	171:3a7713b1edbc	439	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	171:3a7713b1edbc	440	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	171:3a7713b1edbc	441	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	171:3a7713b1edbc	442	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	171:3a7713b1edbc	443	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	171:3a7713b1edbc	444	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	171:3a7713b1edbc	445	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	171:3a7713b1edbc	446	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	171:3a7713b1edbc	447	* @retval HCLK clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	448	*/
AnnaBridge	171:3a7713b1edbc	449	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
AnnaBridge	171:3a7713b1edbc	450
AnnaBridge	171:3a7713b1edbc	451	/**
AnnaBridge	171:3a7713b1edbc	452	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
AnnaBridge	171:3a7713b1edbc	453	* @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
AnnaBridge	171:3a7713b1edbc	454	* ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
AnnaBridge	171:3a7713b1edbc	455	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	171:3a7713b1edbc	456	* @param __APB1PRESCALER__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	457	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	171:3a7713b1edbc	458	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	171:3a7713b1edbc	459	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	171:3a7713b1edbc	460	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	171:3a7713b1edbc	461	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	171:3a7713b1edbc	462	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	463	*/
AnnaBridge	171:3a7713b1edbc	464	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
AnnaBridge	171:3a7713b1edbc	465
AnnaBridge	171:3a7713b1edbc	466	/**
AnnaBridge	171:3a7713b1edbc	467	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
AnnaBridge	171:3a7713b1edbc	468	* @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
AnnaBridge	171:3a7713b1edbc	469	* ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
AnnaBridge	171:3a7713b1edbc	470	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	171:3a7713b1edbc	471	* @param __APB2PRESCALER__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	472	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	171:3a7713b1edbc	473	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	171:3a7713b1edbc	474	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	171:3a7713b1edbc	475	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	171:3a7713b1edbc	476	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	171:3a7713b1edbc	477	* @retval PCLK2 clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	478	*/
AnnaBridge	171:3a7713b1edbc	479	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
AnnaBridge	171:3a7713b1edbc	480
AnnaBridge	171:3a7713b1edbc	481	/**
AnnaBridge	171:3a7713b1edbc	482	* @brief Helper macro to calculate the MSI frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	483	* @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange
AnnaBridge	171:3a7713b1edbc	484	* ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange())
AnnaBridge	171:3a7713b1edbc	485	* @param __MSIRANGE__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	486	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	171:3a7713b1edbc	487	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	171:3a7713b1edbc	488	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	171:3a7713b1edbc	489	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	171:3a7713b1edbc	490	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	171:3a7713b1edbc	491	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	171:3a7713b1edbc	492	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	171:3a7713b1edbc	493	* @retval MSI clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	494	*/
AnnaBridge	171:3a7713b1edbc	495	#define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1U << (((__MSIRANGE__) >> RCC_POSITION_MSIRANGE) + 1U))))
AnnaBridge	171:3a7713b1edbc	496
AnnaBridge	171:3a7713b1edbc	497	/**
AnnaBridge	171:3a7713b1edbc	498	* @}
AnnaBridge	171:3a7713b1edbc	499	*/
AnnaBridge	171:3a7713b1edbc	500
AnnaBridge	171:3a7713b1edbc	501	/**
AnnaBridge	171:3a7713b1edbc	502	* @}
AnnaBridge	171:3a7713b1edbc	503	*/
AnnaBridge	171:3a7713b1edbc	504
AnnaBridge	171:3a7713b1edbc	505	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	506	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
AnnaBridge	171:3a7713b1edbc	507	* @{
AnnaBridge	171:3a7713b1edbc	508	*/
AnnaBridge	171:3a7713b1edbc	509
AnnaBridge	171:3a7713b1edbc	510	/** @defgroup RCC_LL_EF_HSE HSE
AnnaBridge	171:3a7713b1edbc	511	* @{
AnnaBridge	171:3a7713b1edbc	512	*/
AnnaBridge	171:3a7713b1edbc	513
AnnaBridge	171:3a7713b1edbc	514	/**
AnnaBridge	171:3a7713b1edbc	515	* @brief Enable the Clock Security System.
AnnaBridge	171:3a7713b1edbc	516	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
AnnaBridge	171:3a7713b1edbc	517	* @retval None
AnnaBridge	171:3a7713b1edbc	518	*/
AnnaBridge	171:3a7713b1edbc	519	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
AnnaBridge	171:3a7713b1edbc	520	{
AnnaBridge	171:3a7713b1edbc	521	SET_BIT(RCC->CR, RCC_CR_CSSON);
AnnaBridge	171:3a7713b1edbc	522	}
AnnaBridge	171:3a7713b1edbc	523
AnnaBridge	171:3a7713b1edbc	524	/**
AnnaBridge	171:3a7713b1edbc	525	* @brief Disable the Clock Security System.
AnnaBridge	171:3a7713b1edbc	526	* @note Cannot be disabled in HSE is ready (only by hardware)
AnnaBridge	171:3a7713b1edbc	527	* @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
AnnaBridge	171:3a7713b1edbc	528	* @retval None
AnnaBridge	171:3a7713b1edbc	529	*/
AnnaBridge	171:3a7713b1edbc	530	__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
AnnaBridge	171:3a7713b1edbc	531	{
AnnaBridge	171:3a7713b1edbc	532	CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
AnnaBridge	171:3a7713b1edbc	533	}
AnnaBridge	171:3a7713b1edbc	534
AnnaBridge	171:3a7713b1edbc	535	/**
AnnaBridge	171:3a7713b1edbc	536	* @brief Enable HSE external oscillator (HSE Bypass)
AnnaBridge	171:3a7713b1edbc	537	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
AnnaBridge	171:3a7713b1edbc	538	* @retval None
AnnaBridge	171:3a7713b1edbc	539	*/
AnnaBridge	171:3a7713b1edbc	540	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
AnnaBridge	171:3a7713b1edbc	541	{
AnnaBridge	171:3a7713b1edbc	542	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	171:3a7713b1edbc	543	}
AnnaBridge	171:3a7713b1edbc	544
AnnaBridge	171:3a7713b1edbc	545	/**
AnnaBridge	171:3a7713b1edbc	546	* @brief Disable HSE external oscillator (HSE Bypass)
AnnaBridge	171:3a7713b1edbc	547	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
AnnaBridge	171:3a7713b1edbc	548	* @retval None
AnnaBridge	171:3a7713b1edbc	549	*/
AnnaBridge	171:3a7713b1edbc	550	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
AnnaBridge	171:3a7713b1edbc	551	{
AnnaBridge	171:3a7713b1edbc	552	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	171:3a7713b1edbc	553	}
AnnaBridge	171:3a7713b1edbc	554
AnnaBridge	171:3a7713b1edbc	555	/**
AnnaBridge	171:3a7713b1edbc	556	* @brief Enable HSE crystal oscillator (HSE ON)
AnnaBridge	171:3a7713b1edbc	557	* @rmtoll CR HSEON LL_RCC_HSE_Enable
AnnaBridge	171:3a7713b1edbc	558	* @retval None
AnnaBridge	171:3a7713b1edbc	559	*/
AnnaBridge	171:3a7713b1edbc	560	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
AnnaBridge	171:3a7713b1edbc	561	{
AnnaBridge	171:3a7713b1edbc	562	SET_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	171:3a7713b1edbc	563	}
AnnaBridge	171:3a7713b1edbc	564
AnnaBridge	171:3a7713b1edbc	565	/**
AnnaBridge	171:3a7713b1edbc	566	* @brief Disable HSE crystal oscillator (HSE ON)
AnnaBridge	171:3a7713b1edbc	567	* @rmtoll CR HSEON LL_RCC_HSE_Disable
AnnaBridge	171:3a7713b1edbc	568	* @retval None
AnnaBridge	171:3a7713b1edbc	569	*/
AnnaBridge	171:3a7713b1edbc	570	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
AnnaBridge	171:3a7713b1edbc	571	{
AnnaBridge	171:3a7713b1edbc	572	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	171:3a7713b1edbc	573	}
AnnaBridge	171:3a7713b1edbc	574
AnnaBridge	171:3a7713b1edbc	575	/**
AnnaBridge	171:3a7713b1edbc	576	* @brief Check if HSE oscillator Ready
AnnaBridge	171:3a7713b1edbc	577	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
AnnaBridge	171:3a7713b1edbc	578	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	579	*/
AnnaBridge	171:3a7713b1edbc	580	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
AnnaBridge	171:3a7713b1edbc	581	{
AnnaBridge	171:3a7713b1edbc	582	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
AnnaBridge	171:3a7713b1edbc	583	}
AnnaBridge	171:3a7713b1edbc	584
AnnaBridge	171:3a7713b1edbc	585	/**
AnnaBridge	171:3a7713b1edbc	586	* @brief Configure the RTC prescaler (divider)
AnnaBridge	171:3a7713b1edbc	587	* @rmtoll CR RTCPRE LL_RCC_SetRTC_HSEPrescaler
AnnaBridge	171:3a7713b1edbc	588	* @param Div This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	589	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	171:3a7713b1edbc	590	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	171:3a7713b1edbc	591	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	171:3a7713b1edbc	592	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	171:3a7713b1edbc	593	* @retval None
AnnaBridge	171:3a7713b1edbc	594	*/
AnnaBridge	171:3a7713b1edbc	595	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)
AnnaBridge	171:3a7713b1edbc	596	{
AnnaBridge	171:3a7713b1edbc	597	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div);
AnnaBridge	171:3a7713b1edbc	598	}
AnnaBridge	171:3a7713b1edbc	599
AnnaBridge	171:3a7713b1edbc	600	/**
AnnaBridge	171:3a7713b1edbc	601	* @brief Get the RTC divider (prescaler)
AnnaBridge	171:3a7713b1edbc	602	* @rmtoll CR RTCPRE LL_RCC_GetRTC_HSEPrescaler
AnnaBridge	171:3a7713b1edbc	603	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	604	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	171:3a7713b1edbc	605	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	171:3a7713b1edbc	606	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	171:3a7713b1edbc	607	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	171:3a7713b1edbc	608	*/
AnnaBridge	171:3a7713b1edbc	609	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
AnnaBridge	171:3a7713b1edbc	610	{
AnnaBridge	171:3a7713b1edbc	611	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE));
AnnaBridge	171:3a7713b1edbc	612	}
AnnaBridge	171:3a7713b1edbc	613
AnnaBridge	171:3a7713b1edbc	614	/**
AnnaBridge	171:3a7713b1edbc	615	* @}
AnnaBridge	171:3a7713b1edbc	616	*/
AnnaBridge	171:3a7713b1edbc	617
AnnaBridge	171:3a7713b1edbc	618	/** @defgroup RCC_LL_EF_HSI HSI
AnnaBridge	171:3a7713b1edbc	619	* @{
AnnaBridge	171:3a7713b1edbc	620	*/
AnnaBridge	171:3a7713b1edbc	621
AnnaBridge	171:3a7713b1edbc	622	/**
AnnaBridge	171:3a7713b1edbc	623	* @brief Enable HSI oscillator
AnnaBridge	171:3a7713b1edbc	624	* @rmtoll CR HSION LL_RCC_HSI_Enable
AnnaBridge	171:3a7713b1edbc	625	* @retval None
AnnaBridge	171:3a7713b1edbc	626	*/
AnnaBridge	171:3a7713b1edbc	627	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
AnnaBridge	171:3a7713b1edbc	628	{
AnnaBridge	171:3a7713b1edbc	629	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	171:3a7713b1edbc	630	}
AnnaBridge	171:3a7713b1edbc	631
AnnaBridge	171:3a7713b1edbc	632	/**
AnnaBridge	171:3a7713b1edbc	633	* @brief Disable HSI oscillator
AnnaBridge	171:3a7713b1edbc	634	* @rmtoll CR HSION LL_RCC_HSI_Disable
AnnaBridge	171:3a7713b1edbc	635	* @retval None
AnnaBridge	171:3a7713b1edbc	636	*/
AnnaBridge	171:3a7713b1edbc	637	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
AnnaBridge	171:3a7713b1edbc	638	{
AnnaBridge	171:3a7713b1edbc	639	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	171:3a7713b1edbc	640	}
AnnaBridge	171:3a7713b1edbc	641
AnnaBridge	171:3a7713b1edbc	642	/**
AnnaBridge	171:3a7713b1edbc	643	* @brief Check if HSI clock is ready
AnnaBridge	171:3a7713b1edbc	644	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
AnnaBridge	171:3a7713b1edbc	645	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	646	*/
AnnaBridge	171:3a7713b1edbc	647	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
AnnaBridge	171:3a7713b1edbc	648	{
AnnaBridge	171:3a7713b1edbc	649	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
AnnaBridge	171:3a7713b1edbc	650	}
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	/**
AnnaBridge	171:3a7713b1edbc	653	* @brief Get HSI Calibration value
AnnaBridge	171:3a7713b1edbc	654	* @note When HSITRIM is written, HSICAL is updated with the sum of
AnnaBridge	171:3a7713b1edbc	655	* HSITRIM and the factory trim value
AnnaBridge	171:3a7713b1edbc	656	* @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
AnnaBridge	171:3a7713b1edbc	657	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	171:3a7713b1edbc	658	*/
AnnaBridge	171:3a7713b1edbc	659	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
AnnaBridge	171:3a7713b1edbc	660	{
AnnaBridge	171:3a7713b1edbc	661	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
AnnaBridge	171:3a7713b1edbc	662	}
AnnaBridge	171:3a7713b1edbc	663
AnnaBridge	171:3a7713b1edbc	664	/**
AnnaBridge	171:3a7713b1edbc	665	* @brief Set HSI Calibration trimming
AnnaBridge	171:3a7713b1edbc	666	* @note user-programmable trimming value that is added to the HSICAL
AnnaBridge	171:3a7713b1edbc	667	* @note Default value is 16, which, when added to the HSICAL value,
AnnaBridge	171:3a7713b1edbc	668	* should trim the HSI to 16 MHz +/- 1 %
AnnaBridge	171:3a7713b1edbc	669	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
AnnaBridge	171:3a7713b1edbc	670	* @param Value between Min_Data = 0x00 and Max_Data = 0x1F
AnnaBridge	171:3a7713b1edbc	671	* @retval None
AnnaBridge	171:3a7713b1edbc	672	*/
AnnaBridge	171:3a7713b1edbc	673	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	171:3a7713b1edbc	674	{
AnnaBridge	171:3a7713b1edbc	675	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
AnnaBridge	171:3a7713b1edbc	676	}
AnnaBridge	171:3a7713b1edbc	677
AnnaBridge	171:3a7713b1edbc	678	/**
AnnaBridge	171:3a7713b1edbc	679	* @brief Get HSI Calibration trimming
AnnaBridge	171:3a7713b1edbc	680	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
AnnaBridge	171:3a7713b1edbc	681	* @retval Between Min_Data = 0x00 and Max_Data = 0x1F
AnnaBridge	171:3a7713b1edbc	682	*/
AnnaBridge	171:3a7713b1edbc	683	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
AnnaBridge	171:3a7713b1edbc	684	{
AnnaBridge	171:3a7713b1edbc	685	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
AnnaBridge	171:3a7713b1edbc	686	}
AnnaBridge	171:3a7713b1edbc	687
AnnaBridge	171:3a7713b1edbc	688	/**
AnnaBridge	171:3a7713b1edbc	689	* @}
AnnaBridge	171:3a7713b1edbc	690	*/
AnnaBridge	171:3a7713b1edbc	691
AnnaBridge	171:3a7713b1edbc	692	/** @defgroup RCC_LL_EF_LSE LSE
AnnaBridge	171:3a7713b1edbc	693	* @{
AnnaBridge	171:3a7713b1edbc	694	*/
AnnaBridge	171:3a7713b1edbc	695
AnnaBridge	171:3a7713b1edbc	696	/**
AnnaBridge	171:3a7713b1edbc	697	* @brief Enable Low Speed External (LSE) crystal.
AnnaBridge	171:3a7713b1edbc	698	* @rmtoll CSR LSEON LL_RCC_LSE_Enable
AnnaBridge	171:3a7713b1edbc	699	* @retval None
AnnaBridge	171:3a7713b1edbc	700	*/
AnnaBridge	171:3a7713b1edbc	701	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
AnnaBridge	171:3a7713b1edbc	702	{
AnnaBridge	171:3a7713b1edbc	703	SET_BIT(RCC->CSR, RCC_CSR_LSEON);
AnnaBridge	171:3a7713b1edbc	704	}
AnnaBridge	171:3a7713b1edbc	705
AnnaBridge	171:3a7713b1edbc	706	/**
AnnaBridge	171:3a7713b1edbc	707	* @brief Disable Low Speed External (LSE) crystal.
AnnaBridge	171:3a7713b1edbc	708	* @rmtoll CSR LSEON LL_RCC_LSE_Disable
AnnaBridge	171:3a7713b1edbc	709	* @retval None
AnnaBridge	171:3a7713b1edbc	710	*/
AnnaBridge	171:3a7713b1edbc	711	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
AnnaBridge	171:3a7713b1edbc	712	{
AnnaBridge	171:3a7713b1edbc	713	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);
AnnaBridge	171:3a7713b1edbc	714	}
AnnaBridge	171:3a7713b1edbc	715
AnnaBridge	171:3a7713b1edbc	716	/**
AnnaBridge	171:3a7713b1edbc	717	* @brief Enable external clock source (LSE bypass).
AnnaBridge	171:3a7713b1edbc	718	* @rmtoll CSR LSEBYP LL_RCC_LSE_EnableBypass
AnnaBridge	171:3a7713b1edbc	719	* @retval None
AnnaBridge	171:3a7713b1edbc	720	*/
AnnaBridge	171:3a7713b1edbc	721	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
AnnaBridge	171:3a7713b1edbc	722	{
AnnaBridge	171:3a7713b1edbc	723	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);
AnnaBridge	171:3a7713b1edbc	724	}
AnnaBridge	171:3a7713b1edbc	725
AnnaBridge	171:3a7713b1edbc	726	/**
AnnaBridge	171:3a7713b1edbc	727	* @brief Disable external clock source (LSE bypass).
AnnaBridge	171:3a7713b1edbc	728	* @rmtoll CSR LSEBYP LL_RCC_LSE_DisableBypass
AnnaBridge	171:3a7713b1edbc	729	* @retval None
AnnaBridge	171:3a7713b1edbc	730	*/
AnnaBridge	171:3a7713b1edbc	731	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
AnnaBridge	171:3a7713b1edbc	732	{
AnnaBridge	171:3a7713b1edbc	733	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);
AnnaBridge	171:3a7713b1edbc	734	}
AnnaBridge	171:3a7713b1edbc	735
AnnaBridge	171:3a7713b1edbc	736	#if defined(RCC_LSECSS_SUPPORT)
AnnaBridge	171:3a7713b1edbc	737	/**
AnnaBridge	171:3a7713b1edbc	738	* @brief Enable Clock security system on LSE.
AnnaBridge	171:3a7713b1edbc	739	* @rmtoll CSR LSECSSON LL_RCC_LSE_EnableCSS
AnnaBridge	171:3a7713b1edbc	740	* @retval None
AnnaBridge	171:3a7713b1edbc	741	*/
AnnaBridge	171:3a7713b1edbc	742	__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
AnnaBridge	171:3a7713b1edbc	743	{
AnnaBridge	171:3a7713b1edbc	744	SET_BIT(RCC->CSR, RCC_CSR_LSECSSON);
AnnaBridge	171:3a7713b1edbc	745	}
AnnaBridge	171:3a7713b1edbc	746
AnnaBridge	171:3a7713b1edbc	747	/**
AnnaBridge	171:3a7713b1edbc	748	* @brief Disable Clock security system on LSE.
AnnaBridge	171:3a7713b1edbc	749	* @note Clock security system can be disabled only after a LSE
AnnaBridge	171:3a7713b1edbc	750	* failure detection. In that case it MUST be disabled by software.
AnnaBridge	171:3a7713b1edbc	751	* @rmtoll CSR LSECSSON LL_RCC_LSE_DisableCSS
AnnaBridge	171:3a7713b1edbc	752	* @retval None
AnnaBridge	171:3a7713b1edbc	753	*/
AnnaBridge	171:3a7713b1edbc	754	__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
AnnaBridge	171:3a7713b1edbc	755	{
AnnaBridge	171:3a7713b1edbc	756	CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON);
AnnaBridge	171:3a7713b1edbc	757	}
AnnaBridge	171:3a7713b1edbc	758
AnnaBridge	171:3a7713b1edbc	759	#endif /* RCC_LSECSS_SUPPORT */
AnnaBridge	171:3a7713b1edbc	760	/**
AnnaBridge	171:3a7713b1edbc	761	* @brief Check if LSE oscillator Ready
AnnaBridge	171:3a7713b1edbc	762	* @rmtoll CSR LSERDY LL_RCC_LSE_IsReady
AnnaBridge	171:3a7713b1edbc	763	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	764	*/
AnnaBridge	171:3a7713b1edbc	765	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
AnnaBridge	171:3a7713b1edbc	766	{
AnnaBridge	171:3a7713b1edbc	767	return (READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == (RCC_CSR_LSERDY));
AnnaBridge	171:3a7713b1edbc	768	}
AnnaBridge	171:3a7713b1edbc	769
AnnaBridge	171:3a7713b1edbc	770	#if defined(RCC_LSECSS_SUPPORT)
AnnaBridge	171:3a7713b1edbc	771	/**
AnnaBridge	171:3a7713b1edbc	772	* @brief Check if CSS on LSE failure Detection
AnnaBridge	171:3a7713b1edbc	773	* @rmtoll CSR LSECSSD LL_RCC_LSE_IsCSSDetected
AnnaBridge	171:3a7713b1edbc	774	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	775	*/
AnnaBridge	171:3a7713b1edbc	776	__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
AnnaBridge	171:3a7713b1edbc	777	{
AnnaBridge	171:3a7713b1edbc	778	return (READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == (RCC_CSR_LSECSSD));
AnnaBridge	171:3a7713b1edbc	779	}
AnnaBridge	171:3a7713b1edbc	780
AnnaBridge	171:3a7713b1edbc	781	#endif /* RCC_LSECSS_SUPPORT */
AnnaBridge	171:3a7713b1edbc	782	/**
AnnaBridge	171:3a7713b1edbc	783	* @}
AnnaBridge	171:3a7713b1edbc	784	*/
AnnaBridge	171:3a7713b1edbc	785
AnnaBridge	171:3a7713b1edbc	786	/** @defgroup RCC_LL_EF_LSI LSI
AnnaBridge	171:3a7713b1edbc	787	* @{
AnnaBridge	171:3a7713b1edbc	788	*/
AnnaBridge	171:3a7713b1edbc	789
AnnaBridge	171:3a7713b1edbc	790	/**
AnnaBridge	171:3a7713b1edbc	791	* @brief Enable LSI Oscillator
AnnaBridge	171:3a7713b1edbc	792	* @rmtoll CSR LSION LL_RCC_LSI_Enable
AnnaBridge	171:3a7713b1edbc	793	* @retval None
AnnaBridge	171:3a7713b1edbc	794	*/
AnnaBridge	171:3a7713b1edbc	795	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
AnnaBridge	171:3a7713b1edbc	796	{
AnnaBridge	171:3a7713b1edbc	797	SET_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	171:3a7713b1edbc	798	}
AnnaBridge	171:3a7713b1edbc	799
AnnaBridge	171:3a7713b1edbc	800	/**
AnnaBridge	171:3a7713b1edbc	801	* @brief Disable LSI Oscillator
AnnaBridge	171:3a7713b1edbc	802	* @rmtoll CSR LSION LL_RCC_LSI_Disable
AnnaBridge	171:3a7713b1edbc	803	* @retval None
AnnaBridge	171:3a7713b1edbc	804	*/
AnnaBridge	171:3a7713b1edbc	805	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
AnnaBridge	171:3a7713b1edbc	806	{
AnnaBridge	171:3a7713b1edbc	807	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	171:3a7713b1edbc	808	}
AnnaBridge	171:3a7713b1edbc	809
AnnaBridge	171:3a7713b1edbc	810	/**
AnnaBridge	171:3a7713b1edbc	811	* @brief Check if LSI is Ready
AnnaBridge	171:3a7713b1edbc	812	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
AnnaBridge	171:3a7713b1edbc	813	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	814	*/
AnnaBridge	171:3a7713b1edbc	815	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
AnnaBridge	171:3a7713b1edbc	816	{
AnnaBridge	171:3a7713b1edbc	817	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
AnnaBridge	171:3a7713b1edbc	818	}
AnnaBridge	171:3a7713b1edbc	819
AnnaBridge	171:3a7713b1edbc	820	/**
AnnaBridge	171:3a7713b1edbc	821	* @}
AnnaBridge	171:3a7713b1edbc	822	*/
AnnaBridge	171:3a7713b1edbc	823
AnnaBridge	171:3a7713b1edbc	824	/** @defgroup RCC_LL_EF_MSI MSI
AnnaBridge	171:3a7713b1edbc	825	* @{
AnnaBridge	171:3a7713b1edbc	826	*/
AnnaBridge	171:3a7713b1edbc	827
AnnaBridge	171:3a7713b1edbc	828	/**
AnnaBridge	171:3a7713b1edbc	829	* @brief Enable MSI oscillator
AnnaBridge	171:3a7713b1edbc	830	* @rmtoll CR MSION LL_RCC_MSI_Enable
AnnaBridge	171:3a7713b1edbc	831	* @retval None
AnnaBridge	171:3a7713b1edbc	832	*/
AnnaBridge	171:3a7713b1edbc	833	__STATIC_INLINE void LL_RCC_MSI_Enable(void)
AnnaBridge	171:3a7713b1edbc	834	{
AnnaBridge	171:3a7713b1edbc	835	SET_BIT(RCC->CR, RCC_CR_MSION);
AnnaBridge	171:3a7713b1edbc	836	}
AnnaBridge	171:3a7713b1edbc	837
AnnaBridge	171:3a7713b1edbc	838	/**
AnnaBridge	171:3a7713b1edbc	839	* @brief Disable MSI oscillator
AnnaBridge	171:3a7713b1edbc	840	* @rmtoll CR MSION LL_RCC_MSI_Disable
AnnaBridge	171:3a7713b1edbc	841	* @retval None
AnnaBridge	171:3a7713b1edbc	842	*/
AnnaBridge	171:3a7713b1edbc	843	__STATIC_INLINE void LL_RCC_MSI_Disable(void)
AnnaBridge	171:3a7713b1edbc	844	{
AnnaBridge	171:3a7713b1edbc	845	CLEAR_BIT(RCC->CR, RCC_CR_MSION);
AnnaBridge	171:3a7713b1edbc	846	}
AnnaBridge	171:3a7713b1edbc	847
AnnaBridge	171:3a7713b1edbc	848	/**
AnnaBridge	171:3a7713b1edbc	849	* @brief Check if MSI oscillator Ready
AnnaBridge	171:3a7713b1edbc	850	* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
AnnaBridge	171:3a7713b1edbc	851	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	852	*/
AnnaBridge	171:3a7713b1edbc	853	__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
AnnaBridge	171:3a7713b1edbc	854	{
AnnaBridge	171:3a7713b1edbc	855	return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
AnnaBridge	171:3a7713b1edbc	856	}
AnnaBridge	171:3a7713b1edbc	857
AnnaBridge	171:3a7713b1edbc	858	/**
AnnaBridge	171:3a7713b1edbc	859	* @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
AnnaBridge	171:3a7713b1edbc	860	* @rmtoll ICSCR MSIRANGE LL_RCC_MSI_SetRange
AnnaBridge	171:3a7713b1edbc	861	* @param Range This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	862	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	171:3a7713b1edbc	863	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	171:3a7713b1edbc	864	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	171:3a7713b1edbc	865	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	171:3a7713b1edbc	866	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	171:3a7713b1edbc	867	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	171:3a7713b1edbc	868	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	171:3a7713b1edbc	869	* @retval None
AnnaBridge	171:3a7713b1edbc	870	*/
AnnaBridge	171:3a7713b1edbc	871	__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
AnnaBridge	171:3a7713b1edbc	872	{
AnnaBridge	171:3a7713b1edbc	873	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
AnnaBridge	171:3a7713b1edbc	874	}
AnnaBridge	171:3a7713b1edbc	875
AnnaBridge	171:3a7713b1edbc	876	/**
AnnaBridge	171:3a7713b1edbc	877	* @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
AnnaBridge	171:3a7713b1edbc	878	* @rmtoll ICSCR MSIRANGE LL_RCC_MSI_GetRange
AnnaBridge	171:3a7713b1edbc	879	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	880	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	171:3a7713b1edbc	881	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	171:3a7713b1edbc	882	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	171:3a7713b1edbc	883	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	171:3a7713b1edbc	884	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	171:3a7713b1edbc	885	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	171:3a7713b1edbc	886	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	171:3a7713b1edbc	887	*/
AnnaBridge	171:3a7713b1edbc	888	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
AnnaBridge	171:3a7713b1edbc	889	{
AnnaBridge	171:3a7713b1edbc	890	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
AnnaBridge	171:3a7713b1edbc	891	}
AnnaBridge	171:3a7713b1edbc	892
AnnaBridge	171:3a7713b1edbc	893	/**
AnnaBridge	171:3a7713b1edbc	894	* @brief Get MSI Calibration value
AnnaBridge	171:3a7713b1edbc	895	* @note When MSITRIM is written, MSICAL is updated with the sum of
AnnaBridge	171:3a7713b1edbc	896	* MSITRIM and the factory trim value
AnnaBridge	171:3a7713b1edbc	897	* @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
AnnaBridge	171:3a7713b1edbc	898	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	171:3a7713b1edbc	899	*/
AnnaBridge	171:3a7713b1edbc	900	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
AnnaBridge	171:3a7713b1edbc	901	{
AnnaBridge	171:3a7713b1edbc	902	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL);
AnnaBridge	171:3a7713b1edbc	903	}
AnnaBridge	171:3a7713b1edbc	904
AnnaBridge	171:3a7713b1edbc	905	/**
AnnaBridge	171:3a7713b1edbc	906	* @brief Set MSI Calibration trimming
AnnaBridge	171:3a7713b1edbc	907	* @note user-programmable trimming value that is added to the MSICAL
AnnaBridge	171:3a7713b1edbc	908	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
AnnaBridge	171:3a7713b1edbc	909	* @param Value between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	171:3a7713b1edbc	910	* @retval None
AnnaBridge	171:3a7713b1edbc	911	*/
AnnaBridge	171:3a7713b1edbc	912	__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	171:3a7713b1edbc	913	{
AnnaBridge	171:3a7713b1edbc	914	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM);
AnnaBridge	171:3a7713b1edbc	915	}
AnnaBridge	171:3a7713b1edbc	916
AnnaBridge	171:3a7713b1edbc	917	/**
AnnaBridge	171:3a7713b1edbc	918	* @brief Get MSI Calibration trimming
AnnaBridge	171:3a7713b1edbc	919	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
AnnaBridge	171:3a7713b1edbc	920	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	171:3a7713b1edbc	921	*/
AnnaBridge	171:3a7713b1edbc	922	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
AnnaBridge	171:3a7713b1edbc	923	{
AnnaBridge	171:3a7713b1edbc	924	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM);
AnnaBridge	171:3a7713b1edbc	925	}
AnnaBridge	171:3a7713b1edbc	926
AnnaBridge	171:3a7713b1edbc	927	/**
AnnaBridge	171:3a7713b1edbc	928	* @}
AnnaBridge	171:3a7713b1edbc	929	*/
AnnaBridge	171:3a7713b1edbc	930
AnnaBridge	171:3a7713b1edbc	931	/** @defgroup RCC_LL_EF_System System
AnnaBridge	171:3a7713b1edbc	932	* @{
AnnaBridge	171:3a7713b1edbc	933	*/
AnnaBridge	171:3a7713b1edbc	934
AnnaBridge	171:3a7713b1edbc	935	/**
AnnaBridge	171:3a7713b1edbc	936	* @brief Configure the system clock source
AnnaBridge	171:3a7713b1edbc	937	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
AnnaBridge	171:3a7713b1edbc	938	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	939	* @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
AnnaBridge	171:3a7713b1edbc	940	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	941	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	942	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
AnnaBridge	171:3a7713b1edbc	943	* @retval None
AnnaBridge	171:3a7713b1edbc	944	*/
AnnaBridge	171:3a7713b1edbc	945	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	946	{
AnnaBridge	171:3a7713b1edbc	947	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
AnnaBridge	171:3a7713b1edbc	948	}
AnnaBridge	171:3a7713b1edbc	949
AnnaBridge	171:3a7713b1edbc	950	/**
AnnaBridge	171:3a7713b1edbc	951	* @brief Get the system clock source
AnnaBridge	171:3a7713b1edbc	952	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
AnnaBridge	171:3a7713b1edbc	953	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	954	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
AnnaBridge	171:3a7713b1edbc	955	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
AnnaBridge	171:3a7713b1edbc	956	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
AnnaBridge	171:3a7713b1edbc	957	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
AnnaBridge	171:3a7713b1edbc	958	*/
AnnaBridge	171:3a7713b1edbc	959	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
AnnaBridge	171:3a7713b1edbc	960	{
AnnaBridge	171:3a7713b1edbc	961	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
AnnaBridge	171:3a7713b1edbc	962	}
AnnaBridge	171:3a7713b1edbc	963
AnnaBridge	171:3a7713b1edbc	964	/**
AnnaBridge	171:3a7713b1edbc	965	* @brief Set AHB prescaler
AnnaBridge	171:3a7713b1edbc	966	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
AnnaBridge	171:3a7713b1edbc	967	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	968	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	171:3a7713b1edbc	969	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	171:3a7713b1edbc	970	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	171:3a7713b1edbc	971	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	171:3a7713b1edbc	972	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	171:3a7713b1edbc	973	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	171:3a7713b1edbc	974	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	171:3a7713b1edbc	975	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	171:3a7713b1edbc	976	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	171:3a7713b1edbc	977	* @retval None
AnnaBridge	171:3a7713b1edbc	978	*/
AnnaBridge	171:3a7713b1edbc	979	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	980	{
AnnaBridge	171:3a7713b1edbc	981	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
AnnaBridge	171:3a7713b1edbc	982	}
AnnaBridge	171:3a7713b1edbc	983
AnnaBridge	171:3a7713b1edbc	984	/**
AnnaBridge	171:3a7713b1edbc	985	* @brief Set APB1 prescaler
AnnaBridge	171:3a7713b1edbc	986	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
AnnaBridge	171:3a7713b1edbc	987	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	988	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	171:3a7713b1edbc	989	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	171:3a7713b1edbc	990	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	171:3a7713b1edbc	991	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	171:3a7713b1edbc	992	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	171:3a7713b1edbc	993	* @retval None
AnnaBridge	171:3a7713b1edbc	994	*/
AnnaBridge	171:3a7713b1edbc	995	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	996	{
AnnaBridge	171:3a7713b1edbc	997	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
AnnaBridge	171:3a7713b1edbc	998	}
AnnaBridge	171:3a7713b1edbc	999
AnnaBridge	171:3a7713b1edbc	1000	/**
AnnaBridge	171:3a7713b1edbc	1001	* @brief Set APB2 prescaler
AnnaBridge	171:3a7713b1edbc	1002	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
AnnaBridge	171:3a7713b1edbc	1003	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1004	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	171:3a7713b1edbc	1005	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	171:3a7713b1edbc	1006	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	171:3a7713b1edbc	1007	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	171:3a7713b1edbc	1008	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	171:3a7713b1edbc	1009	* @retval None
AnnaBridge	171:3a7713b1edbc	1010	*/
AnnaBridge	171:3a7713b1edbc	1011	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	1012	{
AnnaBridge	171:3a7713b1edbc	1013	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
AnnaBridge	171:3a7713b1edbc	1014	}
AnnaBridge	171:3a7713b1edbc	1015
AnnaBridge	171:3a7713b1edbc	1016	/**
AnnaBridge	171:3a7713b1edbc	1017	* @brief Get AHB prescaler
AnnaBridge	171:3a7713b1edbc	1018	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
AnnaBridge	171:3a7713b1edbc	1019	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1020	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	171:3a7713b1edbc	1021	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	171:3a7713b1edbc	1022	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	171:3a7713b1edbc	1023	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	171:3a7713b1edbc	1024	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	171:3a7713b1edbc	1025	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	171:3a7713b1edbc	1026	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	171:3a7713b1edbc	1027	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	171:3a7713b1edbc	1028	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	171:3a7713b1edbc	1029	*/
AnnaBridge	171:3a7713b1edbc	1030	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
AnnaBridge	171:3a7713b1edbc	1031	{
AnnaBridge	171:3a7713b1edbc	1032	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
AnnaBridge	171:3a7713b1edbc	1033	}
AnnaBridge	171:3a7713b1edbc	1034
AnnaBridge	171:3a7713b1edbc	1035	/**
AnnaBridge	171:3a7713b1edbc	1036	* @brief Get APB1 prescaler
AnnaBridge	171:3a7713b1edbc	1037	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
AnnaBridge	171:3a7713b1edbc	1038	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1039	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	171:3a7713b1edbc	1040	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	171:3a7713b1edbc	1041	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	171:3a7713b1edbc	1042	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	171:3a7713b1edbc	1043	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	171:3a7713b1edbc	1044	*/
AnnaBridge	171:3a7713b1edbc	1045	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
AnnaBridge	171:3a7713b1edbc	1046	{
AnnaBridge	171:3a7713b1edbc	1047	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
AnnaBridge	171:3a7713b1edbc	1048	}
AnnaBridge	171:3a7713b1edbc	1049
AnnaBridge	171:3a7713b1edbc	1050	/**
AnnaBridge	171:3a7713b1edbc	1051	* @brief Get APB2 prescaler
AnnaBridge	171:3a7713b1edbc	1052	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
AnnaBridge	171:3a7713b1edbc	1053	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1054	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	171:3a7713b1edbc	1055	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	171:3a7713b1edbc	1056	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	171:3a7713b1edbc	1057	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	171:3a7713b1edbc	1058	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	171:3a7713b1edbc	1059	*/
AnnaBridge	171:3a7713b1edbc	1060	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
AnnaBridge	171:3a7713b1edbc	1061	{
AnnaBridge	171:3a7713b1edbc	1062	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
AnnaBridge	171:3a7713b1edbc	1063	}
AnnaBridge	171:3a7713b1edbc	1064
AnnaBridge	171:3a7713b1edbc	1065	/**
AnnaBridge	171:3a7713b1edbc	1066	* @}
AnnaBridge	171:3a7713b1edbc	1067	*/
AnnaBridge	171:3a7713b1edbc	1068
AnnaBridge	171:3a7713b1edbc	1069	/** @defgroup RCC_LL_EF_MCO MCO
AnnaBridge	171:3a7713b1edbc	1070	* @{
AnnaBridge	171:3a7713b1edbc	1071	*/
AnnaBridge	171:3a7713b1edbc	1072
AnnaBridge	171:3a7713b1edbc	1073	/**
AnnaBridge	171:3a7713b1edbc	1074	* @brief Configure MCOx
AnnaBridge	171:3a7713b1edbc	1075	* @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
AnnaBridge	171:3a7713b1edbc	1076	* CFGR MCOPRE LL_RCC_ConfigMCO
AnnaBridge	171:3a7713b1edbc	1077	* @param MCOxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1078	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
AnnaBridge	171:3a7713b1edbc	1079	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	1080	* @arg @ref LL_RCC_MCO1SOURCE_HSI
AnnaBridge	171:3a7713b1edbc	1081	* @arg @ref LL_RCC_MCO1SOURCE_MSI
AnnaBridge	171:3a7713b1edbc	1082	* @arg @ref LL_RCC_MCO1SOURCE_HSE
AnnaBridge	171:3a7713b1edbc	1083	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
AnnaBridge	171:3a7713b1edbc	1084	* @arg @ref LL_RCC_MCO1SOURCE_LSI
AnnaBridge	171:3a7713b1edbc	1085	* @arg @ref LL_RCC_MCO1SOURCE_LSE
AnnaBridge	171:3a7713b1edbc	1086	* @param MCOxPrescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1087	* @arg @ref LL_RCC_MCO1_DIV_1
AnnaBridge	171:3a7713b1edbc	1088	* @arg @ref LL_RCC_MCO1_DIV_2
AnnaBridge	171:3a7713b1edbc	1089	* @arg @ref LL_RCC_MCO1_DIV_4
AnnaBridge	171:3a7713b1edbc	1090	* @arg @ref LL_RCC_MCO1_DIV_8
AnnaBridge	171:3a7713b1edbc	1091	* @arg @ref LL_RCC_MCO1_DIV_16
AnnaBridge	171:3a7713b1edbc	1092	* @retval None
AnnaBridge	171:3a7713b1edbc	1093	*/
AnnaBridge	171:3a7713b1edbc	1094	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
AnnaBridge	171:3a7713b1edbc	1095	{
AnnaBridge	171:3a7713b1edbc	1096	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE, MCOxSource \| MCOxPrescaler);
AnnaBridge	171:3a7713b1edbc	1097	}
AnnaBridge	171:3a7713b1edbc	1098
AnnaBridge	171:3a7713b1edbc	1099	/**
AnnaBridge	171:3a7713b1edbc	1100	* @}
AnnaBridge	171:3a7713b1edbc	1101	*/
AnnaBridge	171:3a7713b1edbc	1102
AnnaBridge	171:3a7713b1edbc	1103
AnnaBridge	171:3a7713b1edbc	1104
AnnaBridge	171:3a7713b1edbc	1105	/** @defgroup RCC_LL_EF_RTC RTC
AnnaBridge	171:3a7713b1edbc	1106	* @{
AnnaBridge	171:3a7713b1edbc	1107	*/
AnnaBridge	171:3a7713b1edbc	1108
AnnaBridge	171:3a7713b1edbc	1109	/**
AnnaBridge	171:3a7713b1edbc	1110	* @brief Set RTC Clock Source
AnnaBridge	171:3a7713b1edbc	1111	* @note Once the RTC clock source has been selected, it cannot be changed any more unless
AnnaBridge	171:3a7713b1edbc	1112	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
AnnaBridge	171:3a7713b1edbc	1113	* set). The RTCRST bit can be used to reset them.
AnnaBridge	171:3a7713b1edbc	1114	* @rmtoll CSR RTCSEL LL_RCC_SetRTCClockSource
AnnaBridge	171:3a7713b1edbc	1115	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1116	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	171:3a7713b1edbc	1117	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	1118	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	171:3a7713b1edbc	1119	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	1120	* @retval None
AnnaBridge	171:3a7713b1edbc	1121	*/
AnnaBridge	171:3a7713b1edbc	1122	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	1123	{
AnnaBridge	171:3a7713b1edbc	1124	MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source);
AnnaBridge	171:3a7713b1edbc	1125	}
AnnaBridge	171:3a7713b1edbc	1126
AnnaBridge	171:3a7713b1edbc	1127	/**
AnnaBridge	171:3a7713b1edbc	1128	* @brief Get RTC Clock Source
AnnaBridge	171:3a7713b1edbc	1129	* @rmtoll CSR RTCSEL LL_RCC_GetRTCClockSource
AnnaBridge	171:3a7713b1edbc	1130	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1131	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	171:3a7713b1edbc	1132	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	1133	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	171:3a7713b1edbc	1134	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	1135	*/
AnnaBridge	171:3a7713b1edbc	1136	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
AnnaBridge	171:3a7713b1edbc	1137	{
AnnaBridge	171:3a7713b1edbc	1138	return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL));
AnnaBridge	171:3a7713b1edbc	1139	}
AnnaBridge	171:3a7713b1edbc	1140
AnnaBridge	171:3a7713b1edbc	1141	/**
AnnaBridge	171:3a7713b1edbc	1142	* @brief Enable RTC
AnnaBridge	171:3a7713b1edbc	1143	* @rmtoll CSR RTCEN LL_RCC_EnableRTC
AnnaBridge	171:3a7713b1edbc	1144	* @retval None
AnnaBridge	171:3a7713b1edbc	1145	*/
AnnaBridge	171:3a7713b1edbc	1146	__STATIC_INLINE void LL_RCC_EnableRTC(void)
AnnaBridge	171:3a7713b1edbc	1147	{
AnnaBridge	171:3a7713b1edbc	1148	SET_BIT(RCC->CSR, RCC_CSR_RTCEN);
AnnaBridge	171:3a7713b1edbc	1149	}
AnnaBridge	171:3a7713b1edbc	1150
AnnaBridge	171:3a7713b1edbc	1151	/**
AnnaBridge	171:3a7713b1edbc	1152	* @brief Disable RTC
AnnaBridge	171:3a7713b1edbc	1153	* @rmtoll CSR RTCEN LL_RCC_DisableRTC
AnnaBridge	171:3a7713b1edbc	1154	* @retval None
AnnaBridge	171:3a7713b1edbc	1155	*/
AnnaBridge	171:3a7713b1edbc	1156	__STATIC_INLINE void LL_RCC_DisableRTC(void)
AnnaBridge	171:3a7713b1edbc	1157	{
AnnaBridge	171:3a7713b1edbc	1158	CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN);
AnnaBridge	171:3a7713b1edbc	1159	}
AnnaBridge	171:3a7713b1edbc	1160
AnnaBridge	171:3a7713b1edbc	1161	/**
AnnaBridge	171:3a7713b1edbc	1162	* @brief Check if RTC has been enabled or not
AnnaBridge	171:3a7713b1edbc	1163	* @rmtoll CSR RTCEN LL_RCC_IsEnabledRTC
AnnaBridge	171:3a7713b1edbc	1164	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1165	*/
AnnaBridge	171:3a7713b1edbc	1166	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
AnnaBridge	171:3a7713b1edbc	1167	{
AnnaBridge	171:3a7713b1edbc	1168	return (READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == (RCC_CSR_RTCEN));
AnnaBridge	171:3a7713b1edbc	1169	}
AnnaBridge	171:3a7713b1edbc	1170
AnnaBridge	171:3a7713b1edbc	1171	/**
AnnaBridge	171:3a7713b1edbc	1172	* @brief Force the Backup domain reset
AnnaBridge	171:3a7713b1edbc	1173	* @rmtoll CSR RTCRST LL_RCC_ForceBackupDomainReset
AnnaBridge	171:3a7713b1edbc	1174	* @retval None
AnnaBridge	171:3a7713b1edbc	1175	*/
AnnaBridge	171:3a7713b1edbc	1176	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
AnnaBridge	171:3a7713b1edbc	1177	{
AnnaBridge	171:3a7713b1edbc	1178	SET_BIT(RCC->CSR, RCC_CSR_RTCRST);
AnnaBridge	171:3a7713b1edbc	1179	}
AnnaBridge	171:3a7713b1edbc	1180
AnnaBridge	171:3a7713b1edbc	1181	/**
AnnaBridge	171:3a7713b1edbc	1182	* @brief Release the Backup domain reset
AnnaBridge	171:3a7713b1edbc	1183	* @rmtoll CSR RTCRST LL_RCC_ReleaseBackupDomainReset
AnnaBridge	171:3a7713b1edbc	1184	* @retval None
AnnaBridge	171:3a7713b1edbc	1185	*/
AnnaBridge	171:3a7713b1edbc	1186	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
AnnaBridge	171:3a7713b1edbc	1187	{
AnnaBridge	171:3a7713b1edbc	1188	CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST);
AnnaBridge	171:3a7713b1edbc	1189	}
AnnaBridge	171:3a7713b1edbc	1190
AnnaBridge	171:3a7713b1edbc	1191	/**
AnnaBridge	171:3a7713b1edbc	1192	* @}
AnnaBridge	171:3a7713b1edbc	1193	*/
AnnaBridge	171:3a7713b1edbc	1194
AnnaBridge	171:3a7713b1edbc	1195	/** @defgroup RCC_LL_EF_PLL PLL
AnnaBridge	171:3a7713b1edbc	1196	* @{
AnnaBridge	171:3a7713b1edbc	1197	*/
AnnaBridge	171:3a7713b1edbc	1198
AnnaBridge	171:3a7713b1edbc	1199	/**
AnnaBridge	171:3a7713b1edbc	1200	* @brief Enable PLL
AnnaBridge	171:3a7713b1edbc	1201	* @rmtoll CR PLLON LL_RCC_PLL_Enable
AnnaBridge	171:3a7713b1edbc	1202	* @retval None
AnnaBridge	171:3a7713b1edbc	1203	*/
AnnaBridge	171:3a7713b1edbc	1204	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
AnnaBridge	171:3a7713b1edbc	1205	{
AnnaBridge	171:3a7713b1edbc	1206	SET_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	171:3a7713b1edbc	1207	}
AnnaBridge	171:3a7713b1edbc	1208
AnnaBridge	171:3a7713b1edbc	1209	/**
AnnaBridge	171:3a7713b1edbc	1210	* @brief Disable PLL
AnnaBridge	171:3a7713b1edbc	1211	* @note Cannot be disabled if the PLL clock is used as the system clock
AnnaBridge	171:3a7713b1edbc	1212	* @rmtoll CR PLLON LL_RCC_PLL_Disable
AnnaBridge	171:3a7713b1edbc	1213	* @retval None
AnnaBridge	171:3a7713b1edbc	1214	*/
AnnaBridge	171:3a7713b1edbc	1215	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
AnnaBridge	171:3a7713b1edbc	1216	{
AnnaBridge	171:3a7713b1edbc	1217	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	171:3a7713b1edbc	1218	}
AnnaBridge	171:3a7713b1edbc	1219
AnnaBridge	171:3a7713b1edbc	1220	/**
AnnaBridge	171:3a7713b1edbc	1221	* @brief Check if PLL Ready
AnnaBridge	171:3a7713b1edbc	1222	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
AnnaBridge	171:3a7713b1edbc	1223	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1224	*/
AnnaBridge	171:3a7713b1edbc	1225	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
AnnaBridge	171:3a7713b1edbc	1226	{
AnnaBridge	171:3a7713b1edbc	1227	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
AnnaBridge	171:3a7713b1edbc	1228	}
AnnaBridge	171:3a7713b1edbc	1229
AnnaBridge	171:3a7713b1edbc	1230	/**
AnnaBridge	171:3a7713b1edbc	1231	* @brief Configure PLL used for SYSCLK Domain
AnnaBridge	171:3a7713b1edbc	1232	* @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	171:3a7713b1edbc	1233	* CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	171:3a7713b1edbc	1234	* CFGR PLLDIV LL_RCC_PLL_ConfigDomain_SYS
AnnaBridge	171:3a7713b1edbc	1235	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1236	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	1237	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	1238	* @param PLLMul This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1239	* @arg @ref LL_RCC_PLL_MUL_3
AnnaBridge	171:3a7713b1edbc	1240	* @arg @ref LL_RCC_PLL_MUL_4
AnnaBridge	171:3a7713b1edbc	1241	* @arg @ref LL_RCC_PLL_MUL_6
AnnaBridge	171:3a7713b1edbc	1242	* @arg @ref LL_RCC_PLL_MUL_8
AnnaBridge	171:3a7713b1edbc	1243	* @arg @ref LL_RCC_PLL_MUL_12
AnnaBridge	171:3a7713b1edbc	1244	* @arg @ref LL_RCC_PLL_MUL_16
AnnaBridge	171:3a7713b1edbc	1245	* @arg @ref LL_RCC_PLL_MUL_24
AnnaBridge	171:3a7713b1edbc	1246	* @arg @ref LL_RCC_PLL_MUL_32
AnnaBridge	171:3a7713b1edbc	1247	* @arg @ref LL_RCC_PLL_MUL_48
AnnaBridge	171:3a7713b1edbc	1248	* @param PLLDiv This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1249	* @arg @ref LL_RCC_PLL_DIV_2
AnnaBridge	171:3a7713b1edbc	1250	* @arg @ref LL_RCC_PLL_DIV_3
AnnaBridge	171:3a7713b1edbc	1251	* @arg @ref LL_RCC_PLL_DIV_4
AnnaBridge	171:3a7713b1edbc	1252	* @retval None
AnnaBridge	171:3a7713b1edbc	1253	*/
AnnaBridge	171:3a7713b1edbc	1254	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
AnnaBridge	171:3a7713b1edbc	1255	{
AnnaBridge	171:3a7713b1edbc	1256	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV, Source \| PLLMul \| PLLDiv);
AnnaBridge	171:3a7713b1edbc	1257	}
AnnaBridge	171:3a7713b1edbc	1258
AnnaBridge	171:3a7713b1edbc	1259	/**
AnnaBridge	171:3a7713b1edbc	1260	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	171:3a7713b1edbc	1261	* @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
AnnaBridge	171:3a7713b1edbc	1262	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1263	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	1264	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	1265	*/
AnnaBridge	171:3a7713b1edbc	1266	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
AnnaBridge	171:3a7713b1edbc	1267	{
AnnaBridge	171:3a7713b1edbc	1268	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
AnnaBridge	171:3a7713b1edbc	1269	}
AnnaBridge	171:3a7713b1edbc	1270
AnnaBridge	171:3a7713b1edbc	1271	/**
AnnaBridge	171:3a7713b1edbc	1272	* @brief Get PLL multiplication Factor
AnnaBridge	171:3a7713b1edbc	1273	* @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
AnnaBridge	171:3a7713b1edbc	1274	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1275	* @arg @ref LL_RCC_PLL_MUL_3
AnnaBridge	171:3a7713b1edbc	1276	* @arg @ref LL_RCC_PLL_MUL_4
AnnaBridge	171:3a7713b1edbc	1277	* @arg @ref LL_RCC_PLL_MUL_6
AnnaBridge	171:3a7713b1edbc	1278	* @arg @ref LL_RCC_PLL_MUL_8
AnnaBridge	171:3a7713b1edbc	1279	* @arg @ref LL_RCC_PLL_MUL_12
AnnaBridge	171:3a7713b1edbc	1280	* @arg @ref LL_RCC_PLL_MUL_16
AnnaBridge	171:3a7713b1edbc	1281	* @arg @ref LL_RCC_PLL_MUL_24
AnnaBridge	171:3a7713b1edbc	1282	* @arg @ref LL_RCC_PLL_MUL_32
AnnaBridge	171:3a7713b1edbc	1283	* @arg @ref LL_RCC_PLL_MUL_48
AnnaBridge	171:3a7713b1edbc	1284	*/
AnnaBridge	171:3a7713b1edbc	1285	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
AnnaBridge	171:3a7713b1edbc	1286	{
AnnaBridge	171:3a7713b1edbc	1287	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
AnnaBridge	171:3a7713b1edbc	1288	}
AnnaBridge	171:3a7713b1edbc	1289
AnnaBridge	171:3a7713b1edbc	1290	/**
AnnaBridge	171:3a7713b1edbc	1291	* @brief Get Division factor for the main PLL and other PLL
AnnaBridge	171:3a7713b1edbc	1292	* @rmtoll CFGR PLLDIV LL_RCC_PLL_GetDivider
AnnaBridge	171:3a7713b1edbc	1293	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1294	* @arg @ref LL_RCC_PLL_DIV_2
AnnaBridge	171:3a7713b1edbc	1295	* @arg @ref LL_RCC_PLL_DIV_3
AnnaBridge	171:3a7713b1edbc	1296	* @arg @ref LL_RCC_PLL_DIV_4
AnnaBridge	171:3a7713b1edbc	1297	*/
AnnaBridge	171:3a7713b1edbc	1298	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
AnnaBridge	171:3a7713b1edbc	1299	{
AnnaBridge	171:3a7713b1edbc	1300	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
AnnaBridge	171:3a7713b1edbc	1301	}
AnnaBridge	171:3a7713b1edbc	1302
AnnaBridge	171:3a7713b1edbc	1303	/**
AnnaBridge	171:3a7713b1edbc	1304	* @}
AnnaBridge	171:3a7713b1edbc	1305	*/
AnnaBridge	171:3a7713b1edbc	1306
AnnaBridge	171:3a7713b1edbc	1307	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	171:3a7713b1edbc	1308	* @{
AnnaBridge	171:3a7713b1edbc	1309	*/
AnnaBridge	171:3a7713b1edbc	1310
AnnaBridge	171:3a7713b1edbc	1311	/**
AnnaBridge	171:3a7713b1edbc	1312	* @brief Clear LSI ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1313	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
AnnaBridge	171:3a7713b1edbc	1314	* @retval None
AnnaBridge	171:3a7713b1edbc	1315	*/
AnnaBridge	171:3a7713b1edbc	1316	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1317	{
AnnaBridge	171:3a7713b1edbc	1318	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
AnnaBridge	171:3a7713b1edbc	1319	}
AnnaBridge	171:3a7713b1edbc	1320
AnnaBridge	171:3a7713b1edbc	1321	/**
AnnaBridge	171:3a7713b1edbc	1322	* @brief Clear LSE ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1323	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
AnnaBridge	171:3a7713b1edbc	1324	* @retval None
AnnaBridge	171:3a7713b1edbc	1325	*/
AnnaBridge	171:3a7713b1edbc	1326	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	1327	{
AnnaBridge	171:3a7713b1edbc	1328	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
AnnaBridge	171:3a7713b1edbc	1329	}
AnnaBridge	171:3a7713b1edbc	1330
AnnaBridge	171:3a7713b1edbc	1331	/**
AnnaBridge	171:3a7713b1edbc	1332	* @brief Clear MSI ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1333	* @rmtoll CIR MSIRDYC LL_RCC_ClearFlag_MSIRDY
AnnaBridge	171:3a7713b1edbc	1334	* @retval None
AnnaBridge	171:3a7713b1edbc	1335	*/
AnnaBridge	171:3a7713b1edbc	1336	__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1337	{
AnnaBridge	171:3a7713b1edbc	1338	SET_BIT(RCC->CIR, RCC_CIR_MSIRDYC);
AnnaBridge	171:3a7713b1edbc	1339	}
AnnaBridge	171:3a7713b1edbc	1340
AnnaBridge	171:3a7713b1edbc	1341	/**
AnnaBridge	171:3a7713b1edbc	1342	* @brief Clear HSI ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1343	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
AnnaBridge	171:3a7713b1edbc	1344	* @retval None
AnnaBridge	171:3a7713b1edbc	1345	*/
AnnaBridge	171:3a7713b1edbc	1346	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1347	{
AnnaBridge	171:3a7713b1edbc	1348	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
AnnaBridge	171:3a7713b1edbc	1349	}
AnnaBridge	171:3a7713b1edbc	1350
AnnaBridge	171:3a7713b1edbc	1351	/**
AnnaBridge	171:3a7713b1edbc	1352	* @brief Clear HSE ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1353	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
AnnaBridge	171:3a7713b1edbc	1354	* @retval None
AnnaBridge	171:3a7713b1edbc	1355	*/
AnnaBridge	171:3a7713b1edbc	1356	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	1357	{
AnnaBridge	171:3a7713b1edbc	1358	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
AnnaBridge	171:3a7713b1edbc	1359	}
AnnaBridge	171:3a7713b1edbc	1360
AnnaBridge	171:3a7713b1edbc	1361	/**
AnnaBridge	171:3a7713b1edbc	1362	* @brief Clear PLL ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1363	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
AnnaBridge	171:3a7713b1edbc	1364	* @retval None
AnnaBridge	171:3a7713b1edbc	1365	*/
AnnaBridge	171:3a7713b1edbc	1366	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	1367	{
AnnaBridge	171:3a7713b1edbc	1368	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
AnnaBridge	171:3a7713b1edbc	1369	}
AnnaBridge	171:3a7713b1edbc	1370
AnnaBridge	171:3a7713b1edbc	1371	/**
AnnaBridge	171:3a7713b1edbc	1372	* @brief Clear Clock security system interrupt flag
AnnaBridge	171:3a7713b1edbc	1373	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
AnnaBridge	171:3a7713b1edbc	1374	* @retval None
AnnaBridge	171:3a7713b1edbc	1375	*/
AnnaBridge	171:3a7713b1edbc	1376	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
AnnaBridge	171:3a7713b1edbc	1377	{
AnnaBridge	171:3a7713b1edbc	1378	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
AnnaBridge	171:3a7713b1edbc	1379	}
AnnaBridge	171:3a7713b1edbc	1380
AnnaBridge	171:3a7713b1edbc	1381	#if defined(RCC_LSECSS_SUPPORT)
AnnaBridge	171:3a7713b1edbc	1382	/**
AnnaBridge	171:3a7713b1edbc	1383	* @brief Clear LSE Clock security system interrupt flag
AnnaBridge	171:3a7713b1edbc	1384	* @rmtoll CIR LSECSSC LL_RCC_ClearFlag_LSECSS
AnnaBridge	171:3a7713b1edbc	1385	* @retval None
AnnaBridge	171:3a7713b1edbc	1386	*/
AnnaBridge	171:3a7713b1edbc	1387	__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
AnnaBridge	171:3a7713b1edbc	1388	{
AnnaBridge	171:3a7713b1edbc	1389	SET_BIT(RCC->CIR, RCC_CIR_LSECSSC);
AnnaBridge	171:3a7713b1edbc	1390	}
AnnaBridge	171:3a7713b1edbc	1391
AnnaBridge	171:3a7713b1edbc	1392	#endif /* RCC_LSECSS_SUPPORT */
AnnaBridge	171:3a7713b1edbc	1393	/**
AnnaBridge	171:3a7713b1edbc	1394	* @brief Check if LSI ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1395	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
AnnaBridge	171:3a7713b1edbc	1396	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1397	*/
AnnaBridge	171:3a7713b1edbc	1398	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1399	{
AnnaBridge	171:3a7713b1edbc	1400	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
AnnaBridge	171:3a7713b1edbc	1401	}
AnnaBridge	171:3a7713b1edbc	1402
AnnaBridge	171:3a7713b1edbc	1403	/**
AnnaBridge	171:3a7713b1edbc	1404	* @brief Check if LSE ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1405	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
AnnaBridge	171:3a7713b1edbc	1406	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1407	*/
AnnaBridge	171:3a7713b1edbc	1408	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	1409	{
AnnaBridge	171:3a7713b1edbc	1410	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
AnnaBridge	171:3a7713b1edbc	1411	}
AnnaBridge	171:3a7713b1edbc	1412
AnnaBridge	171:3a7713b1edbc	1413	/**
AnnaBridge	171:3a7713b1edbc	1414	* @brief Check if MSI ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1415	* @rmtoll CIR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
AnnaBridge	171:3a7713b1edbc	1416	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1417	*/
AnnaBridge	171:3a7713b1edbc	1418	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1419	{
AnnaBridge	171:3a7713b1edbc	1420	return (READ_BIT(RCC->CIR, RCC_CIR_MSIRDYF) == (RCC_CIR_MSIRDYF));
AnnaBridge	171:3a7713b1edbc	1421	}
AnnaBridge	171:3a7713b1edbc	1422
AnnaBridge	171:3a7713b1edbc	1423	/**
AnnaBridge	171:3a7713b1edbc	1424	* @brief Check if HSI ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1425	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
AnnaBridge	171:3a7713b1edbc	1426	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1427	*/
AnnaBridge	171:3a7713b1edbc	1428	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1429	{
AnnaBridge	171:3a7713b1edbc	1430	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
AnnaBridge	171:3a7713b1edbc	1431	}
AnnaBridge	171:3a7713b1edbc	1432
AnnaBridge	171:3a7713b1edbc	1433	/**
AnnaBridge	171:3a7713b1edbc	1434	* @brief Check if HSE ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1435	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
AnnaBridge	171:3a7713b1edbc	1436	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1437	*/
AnnaBridge	171:3a7713b1edbc	1438	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	1439	{
AnnaBridge	171:3a7713b1edbc	1440	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
AnnaBridge	171:3a7713b1edbc	1441	}
AnnaBridge	171:3a7713b1edbc	1442
AnnaBridge	171:3a7713b1edbc	1443	/**
AnnaBridge	171:3a7713b1edbc	1444	* @brief Check if PLL ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1445	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
AnnaBridge	171:3a7713b1edbc	1446	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1447	*/
AnnaBridge	171:3a7713b1edbc	1448	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	1449	{
AnnaBridge	171:3a7713b1edbc	1450	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
AnnaBridge	171:3a7713b1edbc	1451	}
AnnaBridge	171:3a7713b1edbc	1452
AnnaBridge	171:3a7713b1edbc	1453	/**
AnnaBridge	171:3a7713b1edbc	1454	* @brief Check if Clock security system interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1455	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
AnnaBridge	171:3a7713b1edbc	1456	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1457	*/
AnnaBridge	171:3a7713b1edbc	1458	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
AnnaBridge	171:3a7713b1edbc	1459	{
AnnaBridge	171:3a7713b1edbc	1460	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
AnnaBridge	171:3a7713b1edbc	1461	}
AnnaBridge	171:3a7713b1edbc	1462
AnnaBridge	171:3a7713b1edbc	1463	#if defined(RCC_LSECSS_SUPPORT)
AnnaBridge	171:3a7713b1edbc	1464	/**
AnnaBridge	171:3a7713b1edbc	1465	* @brief Check if LSE Clock security system interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1466	* @rmtoll CIR LSECSSF LL_RCC_IsActiveFlag_LSECSS
AnnaBridge	171:3a7713b1edbc	1467	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1468	*/
AnnaBridge	171:3a7713b1edbc	1469	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
AnnaBridge	171:3a7713b1edbc	1470	{
AnnaBridge	171:3a7713b1edbc	1471	return (READ_BIT(RCC->CIR, RCC_CIR_LSECSSF) == (RCC_CIR_LSECSSF));
AnnaBridge	171:3a7713b1edbc	1472	}
AnnaBridge	171:3a7713b1edbc	1473
AnnaBridge	171:3a7713b1edbc	1474	#endif /* RCC_LSECSS_SUPPORT */
AnnaBridge	171:3a7713b1edbc	1475	/**
AnnaBridge	171:3a7713b1edbc	1476	* @brief Check if RCC flag Independent Watchdog reset is set or not.
AnnaBridge	171:3a7713b1edbc	1477	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
AnnaBridge	171:3a7713b1edbc	1478	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1479	*/
AnnaBridge	171:3a7713b1edbc	1480	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
AnnaBridge	171:3a7713b1edbc	1481	{
AnnaBridge	171:3a7713b1edbc	1482	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
AnnaBridge	171:3a7713b1edbc	1483	}
AnnaBridge	171:3a7713b1edbc	1484
AnnaBridge	171:3a7713b1edbc	1485	/**
AnnaBridge	171:3a7713b1edbc	1486	* @brief Check if RCC flag Low Power reset is set or not.
AnnaBridge	171:3a7713b1edbc	1487	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
AnnaBridge	171:3a7713b1edbc	1488	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1489	*/
AnnaBridge	171:3a7713b1edbc	1490	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
AnnaBridge	171:3a7713b1edbc	1491	{
AnnaBridge	171:3a7713b1edbc	1492	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
AnnaBridge	171:3a7713b1edbc	1493	}
AnnaBridge	171:3a7713b1edbc	1494
AnnaBridge	171:3a7713b1edbc	1495	/**
AnnaBridge	171:3a7713b1edbc	1496	* @brief Check if RCC flag is set or not.
AnnaBridge	171:3a7713b1edbc	1497	* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
AnnaBridge	171:3a7713b1edbc	1498	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1499	*/
AnnaBridge	171:3a7713b1edbc	1500	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
AnnaBridge	171:3a7713b1edbc	1501	{
AnnaBridge	171:3a7713b1edbc	1502	return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
AnnaBridge	171:3a7713b1edbc	1503	}
AnnaBridge	171:3a7713b1edbc	1504
AnnaBridge	171:3a7713b1edbc	1505	/**
AnnaBridge	171:3a7713b1edbc	1506	* @brief Check if RCC flag Pin reset is set or not.
AnnaBridge	171:3a7713b1edbc	1507	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
AnnaBridge	171:3a7713b1edbc	1508	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1509	*/
AnnaBridge	171:3a7713b1edbc	1510	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
AnnaBridge	171:3a7713b1edbc	1511	{
AnnaBridge	171:3a7713b1edbc	1512	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
AnnaBridge	171:3a7713b1edbc	1513	}
AnnaBridge	171:3a7713b1edbc	1514
AnnaBridge	171:3a7713b1edbc	1515	/**
AnnaBridge	171:3a7713b1edbc	1516	* @brief Check if RCC flag POR/PDR reset is set or not.
AnnaBridge	171:3a7713b1edbc	1517	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
AnnaBridge	171:3a7713b1edbc	1518	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1519	*/
AnnaBridge	171:3a7713b1edbc	1520	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
AnnaBridge	171:3a7713b1edbc	1521	{
AnnaBridge	171:3a7713b1edbc	1522	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
AnnaBridge	171:3a7713b1edbc	1523	}
AnnaBridge	171:3a7713b1edbc	1524
AnnaBridge	171:3a7713b1edbc	1525	/**
AnnaBridge	171:3a7713b1edbc	1526	* @brief Check if RCC flag Software reset is set or not.
AnnaBridge	171:3a7713b1edbc	1527	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
AnnaBridge	171:3a7713b1edbc	1528	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1529	*/
AnnaBridge	171:3a7713b1edbc	1530	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
AnnaBridge	171:3a7713b1edbc	1531	{
AnnaBridge	171:3a7713b1edbc	1532	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
AnnaBridge	171:3a7713b1edbc	1533	}
AnnaBridge	171:3a7713b1edbc	1534
AnnaBridge	171:3a7713b1edbc	1535	/**
AnnaBridge	171:3a7713b1edbc	1536	* @brief Check if RCC flag Window Watchdog reset is set or not.
AnnaBridge	171:3a7713b1edbc	1537	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
AnnaBridge	171:3a7713b1edbc	1538	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1539	*/
AnnaBridge	171:3a7713b1edbc	1540	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
AnnaBridge	171:3a7713b1edbc	1541	{
AnnaBridge	171:3a7713b1edbc	1542	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
AnnaBridge	171:3a7713b1edbc	1543	}
AnnaBridge	171:3a7713b1edbc	1544
AnnaBridge	171:3a7713b1edbc	1545	/**
AnnaBridge	171:3a7713b1edbc	1546	* @brief Set RMVF bit to clear the reset flags.
AnnaBridge	171:3a7713b1edbc	1547	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
AnnaBridge	171:3a7713b1edbc	1548	* @retval None
AnnaBridge	171:3a7713b1edbc	1549	*/
AnnaBridge	171:3a7713b1edbc	1550	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
AnnaBridge	171:3a7713b1edbc	1551	{
AnnaBridge	171:3a7713b1edbc	1552	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
AnnaBridge	171:3a7713b1edbc	1553	}
AnnaBridge	171:3a7713b1edbc	1554
AnnaBridge	171:3a7713b1edbc	1555	/**
AnnaBridge	171:3a7713b1edbc	1556	* @}
AnnaBridge	171:3a7713b1edbc	1557	*/
AnnaBridge	171:3a7713b1edbc	1558
AnnaBridge	171:3a7713b1edbc	1559	/** @defgroup RCC_LL_EF_IT_Management IT Management
AnnaBridge	171:3a7713b1edbc	1560	* @{
AnnaBridge	171:3a7713b1edbc	1561	*/
AnnaBridge	171:3a7713b1edbc	1562
AnnaBridge	171:3a7713b1edbc	1563	/**
AnnaBridge	171:3a7713b1edbc	1564	* @brief Enable LSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1565	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
AnnaBridge	171:3a7713b1edbc	1566	* @retval None
AnnaBridge	171:3a7713b1edbc	1567	*/
AnnaBridge	171:3a7713b1edbc	1568	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1569	{
AnnaBridge	171:3a7713b1edbc	1570	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	171:3a7713b1edbc	1571	}
AnnaBridge	171:3a7713b1edbc	1572
AnnaBridge	171:3a7713b1edbc	1573	/**
AnnaBridge	171:3a7713b1edbc	1574	* @brief Enable LSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1575	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
AnnaBridge	171:3a7713b1edbc	1576	* @retval None
AnnaBridge	171:3a7713b1edbc	1577	*/
AnnaBridge	171:3a7713b1edbc	1578	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	1579	{
AnnaBridge	171:3a7713b1edbc	1580	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	171:3a7713b1edbc	1581	}
AnnaBridge	171:3a7713b1edbc	1582
AnnaBridge	171:3a7713b1edbc	1583	/**
AnnaBridge	171:3a7713b1edbc	1584	* @brief Enable MSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1585	* @rmtoll CIR MSIRDYIE LL_RCC_EnableIT_MSIRDY
AnnaBridge	171:3a7713b1edbc	1586	* @retval None
AnnaBridge	171:3a7713b1edbc	1587	*/
AnnaBridge	171:3a7713b1edbc	1588	__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1589	{
AnnaBridge	171:3a7713b1edbc	1590	SET_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
AnnaBridge	171:3a7713b1edbc	1591	}
AnnaBridge	171:3a7713b1edbc	1592
AnnaBridge	171:3a7713b1edbc	1593	/**
AnnaBridge	171:3a7713b1edbc	1594	* @brief Enable HSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1595	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
AnnaBridge	171:3a7713b1edbc	1596	* @retval None
AnnaBridge	171:3a7713b1edbc	1597	*/
AnnaBridge	171:3a7713b1edbc	1598	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1599	{
AnnaBridge	171:3a7713b1edbc	1600	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	171:3a7713b1edbc	1601	}
AnnaBridge	171:3a7713b1edbc	1602
AnnaBridge	171:3a7713b1edbc	1603	/**
AnnaBridge	171:3a7713b1edbc	1604	* @brief Enable HSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1605	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
AnnaBridge	171:3a7713b1edbc	1606	* @retval None
AnnaBridge	171:3a7713b1edbc	1607	*/
AnnaBridge	171:3a7713b1edbc	1608	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	1609	{
AnnaBridge	171:3a7713b1edbc	1610	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	171:3a7713b1edbc	1611	}
AnnaBridge	171:3a7713b1edbc	1612
AnnaBridge	171:3a7713b1edbc	1613	/**
AnnaBridge	171:3a7713b1edbc	1614	* @brief Enable PLL ready interrupt
AnnaBridge	171:3a7713b1edbc	1615	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
AnnaBridge	171:3a7713b1edbc	1616	* @retval None
AnnaBridge	171:3a7713b1edbc	1617	*/
AnnaBridge	171:3a7713b1edbc	1618	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	1619	{
AnnaBridge	171:3a7713b1edbc	1620	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	171:3a7713b1edbc	1621	}
AnnaBridge	171:3a7713b1edbc	1622
AnnaBridge	171:3a7713b1edbc	1623	#if defined(RCC_LSECSS_SUPPORT)
AnnaBridge	171:3a7713b1edbc	1624	/**
AnnaBridge	171:3a7713b1edbc	1625	* @brief Enable LSE clock security system interrupt
AnnaBridge	171:3a7713b1edbc	1626	* @rmtoll CIR LSECSSIE LL_RCC_EnableIT_LSECSS
AnnaBridge	171:3a7713b1edbc	1627	* @retval None
AnnaBridge	171:3a7713b1edbc	1628	*/
AnnaBridge	171:3a7713b1edbc	1629	__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
AnnaBridge	171:3a7713b1edbc	1630	{
AnnaBridge	171:3a7713b1edbc	1631	SET_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
AnnaBridge	171:3a7713b1edbc	1632	}
AnnaBridge	171:3a7713b1edbc	1633
AnnaBridge	171:3a7713b1edbc	1634	#endif /* RCC_LSECSS_SUPPORT */
AnnaBridge	171:3a7713b1edbc	1635	/**
AnnaBridge	171:3a7713b1edbc	1636	* @brief Disable LSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1637	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
AnnaBridge	171:3a7713b1edbc	1638	* @retval None
AnnaBridge	171:3a7713b1edbc	1639	*/
AnnaBridge	171:3a7713b1edbc	1640	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1641	{
AnnaBridge	171:3a7713b1edbc	1642	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	171:3a7713b1edbc	1643	}
AnnaBridge	171:3a7713b1edbc	1644
AnnaBridge	171:3a7713b1edbc	1645	/**
AnnaBridge	171:3a7713b1edbc	1646	* @brief Disable LSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1647	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
AnnaBridge	171:3a7713b1edbc	1648	* @retval None
AnnaBridge	171:3a7713b1edbc	1649	*/
AnnaBridge	171:3a7713b1edbc	1650	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	1651	{
AnnaBridge	171:3a7713b1edbc	1652	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	171:3a7713b1edbc	1653	}
AnnaBridge	171:3a7713b1edbc	1654
AnnaBridge	171:3a7713b1edbc	1655	/**
AnnaBridge	171:3a7713b1edbc	1656	* @brief Disable MSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1657	* @rmtoll CIR MSIRDYIE LL_RCC_DisableIT_MSIRDY
AnnaBridge	171:3a7713b1edbc	1658	* @retval None
AnnaBridge	171:3a7713b1edbc	1659	*/
AnnaBridge	171:3a7713b1edbc	1660	__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1661	{
AnnaBridge	171:3a7713b1edbc	1662	CLEAR_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
AnnaBridge	171:3a7713b1edbc	1663	}
AnnaBridge	171:3a7713b1edbc	1664
AnnaBridge	171:3a7713b1edbc	1665	/**
AnnaBridge	171:3a7713b1edbc	1666	* @brief Disable HSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1667	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
AnnaBridge	171:3a7713b1edbc	1668	* @retval None
AnnaBridge	171:3a7713b1edbc	1669	*/
AnnaBridge	171:3a7713b1edbc	1670	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1671	{
AnnaBridge	171:3a7713b1edbc	1672	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	171:3a7713b1edbc	1673	}
AnnaBridge	171:3a7713b1edbc	1674
AnnaBridge	171:3a7713b1edbc	1675	/**
AnnaBridge	171:3a7713b1edbc	1676	* @brief Disable HSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1677	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
AnnaBridge	171:3a7713b1edbc	1678	* @retval None
AnnaBridge	171:3a7713b1edbc	1679	*/
AnnaBridge	171:3a7713b1edbc	1680	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	1681	{
AnnaBridge	171:3a7713b1edbc	1682	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	171:3a7713b1edbc	1683	}
AnnaBridge	171:3a7713b1edbc	1684
AnnaBridge	171:3a7713b1edbc	1685	/**
AnnaBridge	171:3a7713b1edbc	1686	* @brief Disable PLL ready interrupt
AnnaBridge	171:3a7713b1edbc	1687	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
AnnaBridge	171:3a7713b1edbc	1688	* @retval None
AnnaBridge	171:3a7713b1edbc	1689	*/
AnnaBridge	171:3a7713b1edbc	1690	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	1691	{
AnnaBridge	171:3a7713b1edbc	1692	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	171:3a7713b1edbc	1693	}
AnnaBridge	171:3a7713b1edbc	1694
AnnaBridge	171:3a7713b1edbc	1695	#if defined(RCC_LSECSS_SUPPORT)
AnnaBridge	171:3a7713b1edbc	1696	/**
AnnaBridge	171:3a7713b1edbc	1697	* @brief Disable LSE clock security system interrupt
AnnaBridge	171:3a7713b1edbc	1698	* @rmtoll CIR LSECSSIE LL_RCC_DisableIT_LSECSS
AnnaBridge	171:3a7713b1edbc	1699	* @retval None
AnnaBridge	171:3a7713b1edbc	1700	*/
AnnaBridge	171:3a7713b1edbc	1701	__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
AnnaBridge	171:3a7713b1edbc	1702	{
AnnaBridge	171:3a7713b1edbc	1703	CLEAR_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
AnnaBridge	171:3a7713b1edbc	1704	}
AnnaBridge	171:3a7713b1edbc	1705
AnnaBridge	171:3a7713b1edbc	1706	#endif /* RCC_LSECSS_SUPPORT */
AnnaBridge	171:3a7713b1edbc	1707	/**
AnnaBridge	171:3a7713b1edbc	1708	* @brief Checks if LSI ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1709	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
AnnaBridge	171:3a7713b1edbc	1710	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1711	*/
AnnaBridge	171:3a7713b1edbc	1712	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1713	{
AnnaBridge	171:3a7713b1edbc	1714	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
AnnaBridge	171:3a7713b1edbc	1715	}
AnnaBridge	171:3a7713b1edbc	1716
AnnaBridge	171:3a7713b1edbc	1717	/**
AnnaBridge	171:3a7713b1edbc	1718	* @brief Checks if LSE ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1719	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
AnnaBridge	171:3a7713b1edbc	1720	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1721	*/
AnnaBridge	171:3a7713b1edbc	1722	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	1723	{
AnnaBridge	171:3a7713b1edbc	1724	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
AnnaBridge	171:3a7713b1edbc	1725	}
AnnaBridge	171:3a7713b1edbc	1726
AnnaBridge	171:3a7713b1edbc	1727	/**
AnnaBridge	171:3a7713b1edbc	1728	* @brief Checks if MSI ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1729	* @rmtoll CIR MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
AnnaBridge	171:3a7713b1edbc	1730	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1731	*/
AnnaBridge	171:3a7713b1edbc	1732	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1733	{
AnnaBridge	171:3a7713b1edbc	1734	return (READ_BIT(RCC->CIR, RCC_CIR_MSIRDYIE) == (RCC_CIR_MSIRDYIE));
AnnaBridge	171:3a7713b1edbc	1735	}
AnnaBridge	171:3a7713b1edbc	1736
AnnaBridge	171:3a7713b1edbc	1737	/**
AnnaBridge	171:3a7713b1edbc	1738	* @brief Checks if HSI ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1739	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
AnnaBridge	171:3a7713b1edbc	1740	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1741	*/
AnnaBridge	171:3a7713b1edbc	1742	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1743	{
AnnaBridge	171:3a7713b1edbc	1744	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
AnnaBridge	171:3a7713b1edbc	1745	}
AnnaBridge	171:3a7713b1edbc	1746
AnnaBridge	171:3a7713b1edbc	1747	/**
AnnaBridge	171:3a7713b1edbc	1748	* @brief Checks if HSE ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1749	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
AnnaBridge	171:3a7713b1edbc	1750	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1751	*/
AnnaBridge	171:3a7713b1edbc	1752	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	1753	{
AnnaBridge	171:3a7713b1edbc	1754	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
AnnaBridge	171:3a7713b1edbc	1755	}
AnnaBridge	171:3a7713b1edbc	1756
AnnaBridge	171:3a7713b1edbc	1757	/**
AnnaBridge	171:3a7713b1edbc	1758	* @brief Checks if PLL ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1759	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
AnnaBridge	171:3a7713b1edbc	1760	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1761	*/
AnnaBridge	171:3a7713b1edbc	1762	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	1763	{
AnnaBridge	171:3a7713b1edbc	1764	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
AnnaBridge	171:3a7713b1edbc	1765	}
AnnaBridge	171:3a7713b1edbc	1766
AnnaBridge	171:3a7713b1edbc	1767	#if defined(RCC_LSECSS_SUPPORT)
AnnaBridge	171:3a7713b1edbc	1768	/**
AnnaBridge	171:3a7713b1edbc	1769	* @brief Checks if LSECSS interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1770	* @rmtoll CIR LSECSSIE LL_RCC_IsEnabledIT_LSECSS
AnnaBridge	171:3a7713b1edbc	1771	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1772	*/
AnnaBridge	171:3a7713b1edbc	1773	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
AnnaBridge	171:3a7713b1edbc	1774	{
AnnaBridge	171:3a7713b1edbc	1775	return (READ_BIT(RCC->CIR, RCC_CIR_LSECSSIE) == (RCC_CIR_LSECSSIE));
AnnaBridge	171:3a7713b1edbc	1776	}
AnnaBridge	171:3a7713b1edbc	1777
AnnaBridge	171:3a7713b1edbc	1778	#endif /* RCC_LSECSS_SUPPORT */
AnnaBridge	171:3a7713b1edbc	1779	/**
AnnaBridge	171:3a7713b1edbc	1780	* @}
AnnaBridge	171:3a7713b1edbc	1781	*/
AnnaBridge	171:3a7713b1edbc	1782
AnnaBridge	171:3a7713b1edbc	1783	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	1784	/** @defgroup RCC_LL_EF_Init De-initialization function
AnnaBridge	171:3a7713b1edbc	1785	* @{
AnnaBridge	171:3a7713b1edbc	1786	*/
AnnaBridge	171:3a7713b1edbc	1787	ErrorStatus LL_RCC_DeInit(void);
AnnaBridge	171:3a7713b1edbc	1788	/**
AnnaBridge	171:3a7713b1edbc	1789	* @}
AnnaBridge	171:3a7713b1edbc	1790	*/
AnnaBridge	171:3a7713b1edbc	1791
AnnaBridge	171:3a7713b1edbc	1792	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
AnnaBridge	171:3a7713b1edbc	1793	* @{
AnnaBridge	171:3a7713b1edbc	1794	*/
AnnaBridge	171:3a7713b1edbc	1795	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
AnnaBridge	171:3a7713b1edbc	1796	/**
AnnaBridge	171:3a7713b1edbc	1797	* @}
AnnaBridge	171:3a7713b1edbc	1798	*/
AnnaBridge	171:3a7713b1edbc	1799	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	1800
AnnaBridge	171:3a7713b1edbc	1801	/**
AnnaBridge	171:3a7713b1edbc	1802	* @}
AnnaBridge	171:3a7713b1edbc	1803	*/
AnnaBridge	171:3a7713b1edbc	1804
AnnaBridge	171:3a7713b1edbc	1805	/**
AnnaBridge	171:3a7713b1edbc	1806	* @}
AnnaBridge	171:3a7713b1edbc	1807	*/
AnnaBridge	171:3a7713b1edbc	1808
AnnaBridge	171:3a7713b1edbc	1809	#endif /* RCC */
AnnaBridge	171:3a7713b1edbc	1810
AnnaBridge	171:3a7713b1edbc	1811	/**
AnnaBridge	171:3a7713b1edbc	1812	* @}
AnnaBridge	171:3a7713b1edbc	1813	*/
AnnaBridge	171:3a7713b1edbc	1814
AnnaBridge	171:3a7713b1edbc	1815	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1816	}
AnnaBridge	171:3a7713b1edbc	1817	#endif
AnnaBridge	171:3a7713b1edbc	1818
AnnaBridge	171:3a7713b1edbc	1819	#endif /* __STM32L1xx_LL_RCC_H */
AnnaBridge	171:3a7713b1edbc	1820
AnnaBridge	171:3a7713b1edbc	1821	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/