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TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/stm32l1xx_hal_tim.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32l1xx_hal_tim.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of TIM HAL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32L1xx_HAL_TIM_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32L1xx_HAL_TIM_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32l1xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32L1xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	/** @addtogroup TIM
AnnaBridge	171:3a7713b1edbc	52	* @{
AnnaBridge	171:3a7713b1edbc	53	*/
AnnaBridge	171:3a7713b1edbc	54
AnnaBridge	171:3a7713b1edbc	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	56	/** @defgroup TIM_Exported_Types TIM Exported Types
AnnaBridge	171:3a7713b1edbc	57	* @{
AnnaBridge	171:3a7713b1edbc	58	*/
AnnaBridge	171:3a7713b1edbc	59	/**
AnnaBridge	171:3a7713b1edbc	60	* @brief TIM Time base Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	61	*/
AnnaBridge	171:3a7713b1edbc	62	typedef struct
AnnaBridge	171:3a7713b1edbc	63	{
AnnaBridge	171:3a7713b1edbc	64	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	171:3a7713b1edbc	65	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge	171:3a7713b1edbc	66
AnnaBridge	171:3a7713b1edbc	67	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	171:3a7713b1edbc	68	This parameter can be a value of @ref TIM_Counter_Mode */
AnnaBridge	171:3a7713b1edbc	69
AnnaBridge	171:3a7713b1edbc	70	uint32_t Period; /*!< Specifies the period value to be loaded into the active
AnnaBridge	171:3a7713b1edbc	71	Auto-Reload Register at the next update event.
AnnaBridge	171:3a7713b1edbc	72	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
AnnaBridge	171:3a7713b1edbc	73
AnnaBridge	171:3a7713b1edbc	74	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	171:3a7713b1edbc	75	This parameter can be a value of @ref TIM_ClockDivision */
AnnaBridge	171:3a7713b1edbc	76
AnnaBridge	171:3a7713b1edbc	77	} TIM_Base_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	78
AnnaBridge	171:3a7713b1edbc	79	/**
AnnaBridge	171:3a7713b1edbc	80	* @brief TIM Output Compare Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	81	*/
AnnaBridge	171:3a7713b1edbc	82	typedef struct
AnnaBridge	171:3a7713b1edbc	83	{
AnnaBridge	171:3a7713b1edbc	84	uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge	171:3a7713b1edbc	85	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge	171:3a7713b1edbc	86
AnnaBridge	171:3a7713b1edbc	87	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge	171:3a7713b1edbc	88	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge	171:3a7713b1edbc	89
AnnaBridge	171:3a7713b1edbc	90	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	171:3a7713b1edbc	91	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge	171:3a7713b1edbc	92
AnnaBridge	171:3a7713b1edbc	93	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
AnnaBridge	171:3a7713b1edbc	94	This parameter can be a value of @ref TIM_Output_Fast_State
AnnaBridge	171:3a7713b1edbc	95	@note This parameter is valid only in PWM1 and PWM2 mode. */
AnnaBridge	171:3a7713b1edbc	96
AnnaBridge	171:3a7713b1edbc	97	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	171:3a7713b1edbc	98	This parameter can be a value of @ref TIM_Output_Compare_Idle_State. */
AnnaBridge	171:3a7713b1edbc	99	} TIM_OC_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	100
AnnaBridge	171:3a7713b1edbc	101	/**
AnnaBridge	171:3a7713b1edbc	102	* @brief TIM One Pulse Mode Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	103	*/
AnnaBridge	171:3a7713b1edbc	104	typedef struct
AnnaBridge	171:3a7713b1edbc	105	{
AnnaBridge	171:3a7713b1edbc	106	uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge	171:3a7713b1edbc	107	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge	171:3a7713b1edbc	108
AnnaBridge	171:3a7713b1edbc	109	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge	171:3a7713b1edbc	110	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge	171:3a7713b1edbc	111
AnnaBridge	171:3a7713b1edbc	112	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	171:3a7713b1edbc	113	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge	171:3a7713b1edbc	114
AnnaBridge	171:3a7713b1edbc	115	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	171:3a7713b1edbc	116	This parameter can be a value of @ref TIM_Output_Compare_Idle_State. */
AnnaBridge	171:3a7713b1edbc	117
AnnaBridge	171:3a7713b1edbc	118	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	171:3a7713b1edbc	119	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	171:3a7713b1edbc	120
AnnaBridge	171:3a7713b1edbc	121	uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge	171:3a7713b1edbc	122	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	171:3a7713b1edbc	123
AnnaBridge	171:3a7713b1edbc	124	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	171:3a7713b1edbc	125	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	171:3a7713b1edbc	126	} TIM_OnePulse_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	127
AnnaBridge	171:3a7713b1edbc	128
AnnaBridge	171:3a7713b1edbc	129	/**
AnnaBridge	171:3a7713b1edbc	130	* @brief TIM Input Capture Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	131	*/
AnnaBridge	171:3a7713b1edbc	132	typedef struct
AnnaBridge	171:3a7713b1edbc	133	{
AnnaBridge	171:3a7713b1edbc	134	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	171:3a7713b1edbc	135	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	171:3a7713b1edbc	136
AnnaBridge	171:3a7713b1edbc	137	uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge	171:3a7713b1edbc	138	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	171:3a7713b1edbc	139
AnnaBridge	171:3a7713b1edbc	140	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	171:3a7713b1edbc	141	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge	171:3a7713b1edbc	142
AnnaBridge	171:3a7713b1edbc	143	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	171:3a7713b1edbc	144	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	171:3a7713b1edbc	145	} TIM_IC_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	146
AnnaBridge	171:3a7713b1edbc	147	/**
AnnaBridge	171:3a7713b1edbc	148	* @brief TIM Encoder Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	149	*/
AnnaBridge	171:3a7713b1edbc	150	typedef struct
AnnaBridge	171:3a7713b1edbc	151	{
AnnaBridge	171:3a7713b1edbc	152	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
AnnaBridge	171:3a7713b1edbc	153	This parameter can be a value of @ref TIM_Encoder_Mode */
AnnaBridge	171:3a7713b1edbc	154
AnnaBridge	171:3a7713b1edbc	155	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	171:3a7713b1edbc	156	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	171:3a7713b1edbc	157
AnnaBridge	171:3a7713b1edbc	158	uint32_t IC1Selection; /*!< Specifies the input.
AnnaBridge	171:3a7713b1edbc	159	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	171:3a7713b1edbc	160
AnnaBridge	171:3a7713b1edbc	161	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	171:3a7713b1edbc	162	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge	171:3a7713b1edbc	163
AnnaBridge	171:3a7713b1edbc	164	uint32_t IC1Filter; /*!< Specifies the input capture filter.
AnnaBridge	171:3a7713b1edbc	165	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	171:3a7713b1edbc	166
AnnaBridge	171:3a7713b1edbc	167	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	171:3a7713b1edbc	168	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	171:3a7713b1edbc	169
AnnaBridge	171:3a7713b1edbc	170	uint32_t IC2Selection; /*!< Specifies the input.
AnnaBridge	171:3a7713b1edbc	171	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	171:3a7713b1edbc	172
AnnaBridge	171:3a7713b1edbc	173	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	171:3a7713b1edbc	174	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge	171:3a7713b1edbc	175
AnnaBridge	171:3a7713b1edbc	176	uint32_t IC2Filter; /*!< Specifies the input capture filter.
AnnaBridge	171:3a7713b1edbc	177	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	171:3a7713b1edbc	178	} TIM_Encoder_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	179
AnnaBridge	171:3a7713b1edbc	180
AnnaBridge	171:3a7713b1edbc	181	/**
AnnaBridge	171:3a7713b1edbc	182	* @brief TIM Clock Configuration Handle Structure definition
AnnaBridge	171:3a7713b1edbc	183	*/
AnnaBridge	171:3a7713b1edbc	184	typedef struct
AnnaBridge	171:3a7713b1edbc	185	{
AnnaBridge	171:3a7713b1edbc	186	uint32_t ClockSource; /*!< TIM clock sources
AnnaBridge	171:3a7713b1edbc	187	This parameter can be a value of @ref TIM_Clock_Source */
AnnaBridge	171:3a7713b1edbc	188	uint32_t ClockPolarity; /*!< TIM clock polarity
AnnaBridge	171:3a7713b1edbc	189	This parameter can be a value of @ref TIM_Clock_Polarity */
AnnaBridge	171:3a7713b1edbc	190	uint32_t ClockPrescaler; /*!< TIM clock prescaler
AnnaBridge	171:3a7713b1edbc	191	This parameter can be a value of @ref TIM_Clock_Prescaler */
AnnaBridge	171:3a7713b1edbc	192	uint32_t ClockFilter; /*!< TIM clock filter
AnnaBridge	171:3a7713b1edbc	193	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	171:3a7713b1edbc	194	}TIM_ClockConfigTypeDef;
AnnaBridge	171:3a7713b1edbc	195
AnnaBridge	171:3a7713b1edbc	196	/**
AnnaBridge	171:3a7713b1edbc	197	* @brief TIM Clear Input Configuration Handle Structure definition
AnnaBridge	171:3a7713b1edbc	198	*/
AnnaBridge	171:3a7713b1edbc	199	typedef struct
AnnaBridge	171:3a7713b1edbc	200	{
AnnaBridge	171:3a7713b1edbc	201	uint32_t ClearInputState; /*!< TIM clear Input state
AnnaBridge	171:3a7713b1edbc	202	This parameter can be ENABLE or DISABLE */
AnnaBridge	171:3a7713b1edbc	203	uint32_t ClearInputSource; /*!< TIM clear Input sources
AnnaBridge	171:3a7713b1edbc	204	This parameter can be a value of @ref TIM_ClearInput_Source */
AnnaBridge	171:3a7713b1edbc	205	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
AnnaBridge	171:3a7713b1edbc	206	This parameter can be a value of @ref TIM_ClearInput_Polarity */
AnnaBridge	171:3a7713b1edbc	207	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
AnnaBridge	171:3a7713b1edbc	208	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
AnnaBridge	171:3a7713b1edbc	209	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
AnnaBridge	171:3a7713b1edbc	210	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	171:3a7713b1edbc	211	}TIM_ClearInputConfigTypeDef;
AnnaBridge	171:3a7713b1edbc	212
AnnaBridge	171:3a7713b1edbc	213	/**
AnnaBridge	171:3a7713b1edbc	214	* @brief TIM Slave configuration Structure definition
AnnaBridge	171:3a7713b1edbc	215	*/
AnnaBridge	171:3a7713b1edbc	216	typedef struct {
AnnaBridge	171:3a7713b1edbc	217	uint32_t SlaveMode; /*!< Slave mode selection
AnnaBridge	171:3a7713b1edbc	218	This parameter can be a value of @ref TIM_Slave_Mode */
AnnaBridge	171:3a7713b1edbc	219	uint32_t InputTrigger; /*!< Input Trigger source
AnnaBridge	171:3a7713b1edbc	220	This parameter can be a value of @ref TIM_Trigger_Selection */
AnnaBridge	171:3a7713b1edbc	221	uint32_t TriggerPolarity; /*!< Input Trigger polarity
AnnaBridge	171:3a7713b1edbc	222	This parameter can be a value of @ref TIM_Trigger_Polarity */
AnnaBridge	171:3a7713b1edbc	223	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
AnnaBridge	171:3a7713b1edbc	224	This parameter can be a value of @ref TIM_Trigger_Prescaler */
AnnaBridge	171:3a7713b1edbc	225	uint32_t TriggerFilter; /*!< Input trigger filter
AnnaBridge	171:3a7713b1edbc	226	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	171:3a7713b1edbc	227
AnnaBridge	171:3a7713b1edbc	228	}TIM_SlaveConfigTypeDef;
AnnaBridge	171:3a7713b1edbc	229
AnnaBridge	171:3a7713b1edbc	230	/**
AnnaBridge	171:3a7713b1edbc	231	* @brief HAL State structures definition
AnnaBridge	171:3a7713b1edbc	232	*/
AnnaBridge	171:3a7713b1edbc	233	typedef enum
AnnaBridge	171:3a7713b1edbc	234	{
AnnaBridge	171:3a7713b1edbc	235	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
AnnaBridge	171:3a7713b1edbc	236	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
AnnaBridge	171:3a7713b1edbc	237	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
AnnaBridge	171:3a7713b1edbc	238	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
AnnaBridge	171:3a7713b1edbc	239	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
AnnaBridge	171:3a7713b1edbc	240	}HAL_TIM_StateTypeDef;
AnnaBridge	171:3a7713b1edbc	241
AnnaBridge	171:3a7713b1edbc	242	/**
AnnaBridge	171:3a7713b1edbc	243	* @brief HAL Active channel structures definition
AnnaBridge	171:3a7713b1edbc	244	*/
AnnaBridge	171:3a7713b1edbc	245	typedef enum
AnnaBridge	171:3a7713b1edbc	246	{
AnnaBridge	171:3a7713b1edbc	247	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
AnnaBridge	171:3a7713b1edbc	248	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
AnnaBridge	171:3a7713b1edbc	249	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
AnnaBridge	171:3a7713b1edbc	250	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
AnnaBridge	171:3a7713b1edbc	251	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
AnnaBridge	171:3a7713b1edbc	252	}HAL_TIM_ActiveChannel;
AnnaBridge	171:3a7713b1edbc	253
AnnaBridge	171:3a7713b1edbc	254	/**
AnnaBridge	171:3a7713b1edbc	255	* @brief TIM Time Base Handle Structure definition
AnnaBridge	171:3a7713b1edbc	256	*/
AnnaBridge	171:3a7713b1edbc	257	typedef struct
AnnaBridge	171:3a7713b1edbc	258	{
AnnaBridge	171:3a7713b1edbc	259	TIM_TypeDef Instance; /!< Register base address */
AnnaBridge	171:3a7713b1edbc	260	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
AnnaBridge	171:3a7713b1edbc	261	HAL_TIM_ActiveChannel Channel; /!< Active channel /
AnnaBridge	171:3a7713b1edbc	262	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
AnnaBridge	171:3a7713b1edbc	263	This array is accessed by a @ref TIM_DMA_Handle_index */
AnnaBridge	171:3a7713b1edbc	264	HAL_LockTypeDef Lock; /!< Locking object /
AnnaBridge	171:3a7713b1edbc	265	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
AnnaBridge	171:3a7713b1edbc	266	}TIM_HandleTypeDef;
AnnaBridge	171:3a7713b1edbc	267
AnnaBridge	171:3a7713b1edbc	268	/**
AnnaBridge	171:3a7713b1edbc	269	* @}
AnnaBridge	171:3a7713b1edbc	270	*/
AnnaBridge	171:3a7713b1edbc	271
AnnaBridge	171:3a7713b1edbc	272	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	273	/** @defgroup TIM_Exported_Constants TIM Exported Constants
AnnaBridge	171:3a7713b1edbc	274	* @{
AnnaBridge	171:3a7713b1edbc	275	*/
AnnaBridge	171:3a7713b1edbc	276
AnnaBridge	171:3a7713b1edbc	277	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
AnnaBridge	171:3a7713b1edbc	278	* @{
AnnaBridge	171:3a7713b1edbc	279	*/
AnnaBridge	171:3a7713b1edbc	280	#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /!< Polarity for TIx source /
AnnaBridge	171:3a7713b1edbc	281	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
AnnaBridge	171:3a7713b1edbc	282	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
AnnaBridge	171:3a7713b1edbc	283	/**
AnnaBridge	171:3a7713b1edbc	284	* @}
AnnaBridge	171:3a7713b1edbc	285	*/
AnnaBridge	171:3a7713b1edbc	286
AnnaBridge	171:3a7713b1edbc	287	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
AnnaBridge	171:3a7713b1edbc	288	* @{
AnnaBridge	171:3a7713b1edbc	289	*/
AnnaBridge	171:3a7713b1edbc	290	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
AnnaBridge	171:3a7713b1edbc	291	#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /!< Polarity for ETR source /
AnnaBridge	171:3a7713b1edbc	292	/**
AnnaBridge	171:3a7713b1edbc	293	* @}
AnnaBridge	171:3a7713b1edbc	294	*/
AnnaBridge	171:3a7713b1edbc	295
AnnaBridge	171:3a7713b1edbc	296	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
AnnaBridge	171:3a7713b1edbc	297	* @{
AnnaBridge	171:3a7713b1edbc	298	*/
AnnaBridge	171:3a7713b1edbc	299	#define TIM_ETRPRESCALER_DIV1 (0x0000U) /!< No prescaler is used /
AnnaBridge	171:3a7713b1edbc	300	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
AnnaBridge	171:3a7713b1edbc	301	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
AnnaBridge	171:3a7713b1edbc	302	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
AnnaBridge	171:3a7713b1edbc	303	/**
AnnaBridge	171:3a7713b1edbc	304	* @}
AnnaBridge	171:3a7713b1edbc	305	*/
AnnaBridge	171:3a7713b1edbc	306
AnnaBridge	171:3a7713b1edbc	307	/** @defgroup TIM_Counter_Mode TIM Counter Mode
AnnaBridge	171:3a7713b1edbc	308	* @{
AnnaBridge	171:3a7713b1edbc	309	*/
AnnaBridge	171:3a7713b1edbc	310	#define TIM_COUNTERMODE_UP (0x0000U)
AnnaBridge	171:3a7713b1edbc	311	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
AnnaBridge	171:3a7713b1edbc	312	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
AnnaBridge	171:3a7713b1edbc	313	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
AnnaBridge	171:3a7713b1edbc	314	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
AnnaBridge	171:3a7713b1edbc	315	/**
AnnaBridge	171:3a7713b1edbc	316	* @}
AnnaBridge	171:3a7713b1edbc	317	*/
AnnaBridge	171:3a7713b1edbc	318
AnnaBridge	171:3a7713b1edbc	319	/** @defgroup TIM_ClockDivision TIM ClockDivision
AnnaBridge	171:3a7713b1edbc	320	* @{
AnnaBridge	171:3a7713b1edbc	321	*/
AnnaBridge	171:3a7713b1edbc	322	#define TIM_CLOCKDIVISION_DIV1 (0x0000U)
AnnaBridge	171:3a7713b1edbc	323	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
AnnaBridge	171:3a7713b1edbc	324	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
AnnaBridge	171:3a7713b1edbc	325	/**
AnnaBridge	171:3a7713b1edbc	326	* @}
AnnaBridge	171:3a7713b1edbc	327	*/
AnnaBridge	171:3a7713b1edbc	328
AnnaBridge	171:3a7713b1edbc	329	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
AnnaBridge	171:3a7713b1edbc	330	* @{
AnnaBridge	171:3a7713b1edbc	331	*/
AnnaBridge	171:3a7713b1edbc	332	#define TIM_OCMODE_TIMING (0x0000U)
AnnaBridge	171:3a7713b1edbc	333	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
AnnaBridge	171:3a7713b1edbc	334	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
AnnaBridge	171:3a7713b1edbc	335	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
AnnaBridge	171:3a7713b1edbc	336	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
AnnaBridge	171:3a7713b1edbc	337	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
AnnaBridge	171:3a7713b1edbc	338	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
AnnaBridge	171:3a7713b1edbc	339	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
AnnaBridge	171:3a7713b1edbc	340	/**
AnnaBridge	171:3a7713b1edbc	341	* @}
AnnaBridge	171:3a7713b1edbc	342	*/
AnnaBridge	171:3a7713b1edbc	343
AnnaBridge	171:3a7713b1edbc	344	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
AnnaBridge	171:3a7713b1edbc	345	* @{
AnnaBridge	171:3a7713b1edbc	346	*/
AnnaBridge	171:3a7713b1edbc	347	#define TIM_OCFAST_DISABLE (0x0000U)
AnnaBridge	171:3a7713b1edbc	348	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
AnnaBridge	171:3a7713b1edbc	349	/**
AnnaBridge	171:3a7713b1edbc	350	* @}
AnnaBridge	171:3a7713b1edbc	351	*/
AnnaBridge	171:3a7713b1edbc	352
AnnaBridge	171:3a7713b1edbc	353	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
AnnaBridge	171:3a7713b1edbc	354	* @{
AnnaBridge	171:3a7713b1edbc	355	*/
AnnaBridge	171:3a7713b1edbc	356	#define TIM_OCPOLARITY_HIGH (0x0000U)
AnnaBridge	171:3a7713b1edbc	357	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
AnnaBridge	171:3a7713b1edbc	358	/**
AnnaBridge	171:3a7713b1edbc	359	* @}
AnnaBridge	171:3a7713b1edbc	360	*/
AnnaBridge	171:3a7713b1edbc	361
AnnaBridge	171:3a7713b1edbc	362	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
AnnaBridge	171:3a7713b1edbc	363	* @{
AnnaBridge	171:3a7713b1edbc	364	*/
AnnaBridge	171:3a7713b1edbc	365	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
AnnaBridge	171:3a7713b1edbc	366	#define TIM_OCIDLESTATE_RESET (0x0000U)
AnnaBridge	171:3a7713b1edbc	367	/**
AnnaBridge	171:3a7713b1edbc	368	* @}
AnnaBridge	171:3a7713b1edbc	369	*/
AnnaBridge	171:3a7713b1edbc	370
AnnaBridge	171:3a7713b1edbc	371	/** @defgroup TIM_Channel TIM Channel
AnnaBridge	171:3a7713b1edbc	372	* @{
AnnaBridge	171:3a7713b1edbc	373	*/
AnnaBridge	171:3a7713b1edbc	374	#define TIM_CHANNEL_1 (0x0000U)
AnnaBridge	171:3a7713b1edbc	375	#define TIM_CHANNEL_2 (0x0004U)
AnnaBridge	171:3a7713b1edbc	376	#define TIM_CHANNEL_3 (0x0008U)
AnnaBridge	171:3a7713b1edbc	377	#define TIM_CHANNEL_4 (0x000CU)
AnnaBridge	171:3a7713b1edbc	378	#define TIM_CHANNEL_ALL (0x0018U)
AnnaBridge	171:3a7713b1edbc	379	/**
AnnaBridge	171:3a7713b1edbc	380	* @}
AnnaBridge	171:3a7713b1edbc	381	*/
AnnaBridge	171:3a7713b1edbc	382
AnnaBridge	171:3a7713b1edbc	383	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
AnnaBridge	171:3a7713b1edbc	384	* @{
AnnaBridge	171:3a7713b1edbc	385	*/
AnnaBridge	171:3a7713b1edbc	386	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
AnnaBridge	171:3a7713b1edbc	387	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
AnnaBridge	171:3a7713b1edbc	388	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
AnnaBridge	171:3a7713b1edbc	389	/**
AnnaBridge	171:3a7713b1edbc	390	* @}
AnnaBridge	171:3a7713b1edbc	391	*/
AnnaBridge	171:3a7713b1edbc	392
AnnaBridge	171:3a7713b1edbc	393	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
AnnaBridge	171:3a7713b1edbc	394	* @{
AnnaBridge	171:3a7713b1edbc	395	*/
AnnaBridge	171:3a7713b1edbc	396	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge	171:3a7713b1edbc	397	connected to IC1, IC2, IC3 or IC4, respectively */
AnnaBridge	171:3a7713b1edbc	398	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge	171:3a7713b1edbc	399	connected to IC2, IC1, IC4 or IC3, respectively */
AnnaBridge	171:3a7713b1edbc	400	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
AnnaBridge	171:3a7713b1edbc	401	/**
AnnaBridge	171:3a7713b1edbc	402	* @}
AnnaBridge	171:3a7713b1edbc	403	*/
AnnaBridge	171:3a7713b1edbc	404
AnnaBridge	171:3a7713b1edbc	405	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
AnnaBridge	171:3a7713b1edbc	406	* @{
AnnaBridge	171:3a7713b1edbc	407	*/
AnnaBridge	171:3a7713b1edbc	408	#define TIM_ICPSC_DIV1 (0x0000U) /!< Capture performed each time an edge is detected on the capture input /
AnnaBridge	171:3a7713b1edbc	409	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
AnnaBridge	171:3a7713b1edbc	410	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
AnnaBridge	171:3a7713b1edbc	411	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
AnnaBridge	171:3a7713b1edbc	412	/**
AnnaBridge	171:3a7713b1edbc	413	* @}
AnnaBridge	171:3a7713b1edbc	414	*/
AnnaBridge	171:3a7713b1edbc	415
AnnaBridge	171:3a7713b1edbc	416	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
AnnaBridge	171:3a7713b1edbc	417	* @{
AnnaBridge	171:3a7713b1edbc	418	*/
AnnaBridge	171:3a7713b1edbc	419	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
AnnaBridge	171:3a7713b1edbc	420	#define TIM_OPMODE_REPETITIVE (0x0000U)
AnnaBridge	171:3a7713b1edbc	421	/**
AnnaBridge	171:3a7713b1edbc	422	* @}
AnnaBridge	171:3a7713b1edbc	423	*/
AnnaBridge	171:3a7713b1edbc	424
AnnaBridge	171:3a7713b1edbc	425	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
AnnaBridge	171:3a7713b1edbc	426	* @{
AnnaBridge	171:3a7713b1edbc	427	*/
AnnaBridge	171:3a7713b1edbc	428	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
AnnaBridge	171:3a7713b1edbc	429	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
AnnaBridge	171:3a7713b1edbc	430	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
AnnaBridge	171:3a7713b1edbc	431	/**
AnnaBridge	171:3a7713b1edbc	432	* @}
AnnaBridge	171:3a7713b1edbc	433	*/
AnnaBridge	171:3a7713b1edbc	434
AnnaBridge	171:3a7713b1edbc	435	/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
AnnaBridge	171:3a7713b1edbc	436	* @{
AnnaBridge	171:3a7713b1edbc	437	*/
AnnaBridge	171:3a7713b1edbc	438	#define TIM_IT_UPDATE (TIM_DIER_UIE)
AnnaBridge	171:3a7713b1edbc	439	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
AnnaBridge	171:3a7713b1edbc	440	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
AnnaBridge	171:3a7713b1edbc	441	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
AnnaBridge	171:3a7713b1edbc	442	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
AnnaBridge	171:3a7713b1edbc	443	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
AnnaBridge	171:3a7713b1edbc	444	/**
AnnaBridge	171:3a7713b1edbc	445	* @}
AnnaBridge	171:3a7713b1edbc	446	*/
AnnaBridge	171:3a7713b1edbc	447
AnnaBridge	171:3a7713b1edbc	448	/** @defgroup TIM_DMA_sources TIM DMA Sources
AnnaBridge	171:3a7713b1edbc	449	* @{
AnnaBridge	171:3a7713b1edbc	450	*/
AnnaBridge	171:3a7713b1edbc	451	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
AnnaBridge	171:3a7713b1edbc	452	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
AnnaBridge	171:3a7713b1edbc	453	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
AnnaBridge	171:3a7713b1edbc	454	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
AnnaBridge	171:3a7713b1edbc	455	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
AnnaBridge	171:3a7713b1edbc	456	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
AnnaBridge	171:3a7713b1edbc	457	/**
AnnaBridge	171:3a7713b1edbc	458	* @}
AnnaBridge	171:3a7713b1edbc	459	*/
AnnaBridge	171:3a7713b1edbc	460
AnnaBridge	171:3a7713b1edbc	461	/** @defgroup TIM_Event_Source TIM Event Source
AnnaBridge	171:3a7713b1edbc	462	* @{
AnnaBridge	171:3a7713b1edbc	463	*/
AnnaBridge	171:3a7713b1edbc	464	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
AnnaBridge	171:3a7713b1edbc	465	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
AnnaBridge	171:3a7713b1edbc	466	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
AnnaBridge	171:3a7713b1edbc	467	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
AnnaBridge	171:3a7713b1edbc	468	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
AnnaBridge	171:3a7713b1edbc	469	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
AnnaBridge	171:3a7713b1edbc	470	/**
AnnaBridge	171:3a7713b1edbc	471	* @}
AnnaBridge	171:3a7713b1edbc	472	*/
AnnaBridge	171:3a7713b1edbc	473
AnnaBridge	171:3a7713b1edbc	474	/** @defgroup TIM_Flag_definition TIM Flag Definition
AnnaBridge	171:3a7713b1edbc	475	* @{
AnnaBridge	171:3a7713b1edbc	476	*/
AnnaBridge	171:3a7713b1edbc	477	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
AnnaBridge	171:3a7713b1edbc	478	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
AnnaBridge	171:3a7713b1edbc	479	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
AnnaBridge	171:3a7713b1edbc	480	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
AnnaBridge	171:3a7713b1edbc	481	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
AnnaBridge	171:3a7713b1edbc	482	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
AnnaBridge	171:3a7713b1edbc	483	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
AnnaBridge	171:3a7713b1edbc	484	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
AnnaBridge	171:3a7713b1edbc	485	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
AnnaBridge	171:3a7713b1edbc	486	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
AnnaBridge	171:3a7713b1edbc	487	/**
AnnaBridge	171:3a7713b1edbc	488	* @}
AnnaBridge	171:3a7713b1edbc	489	*/
AnnaBridge	171:3a7713b1edbc	490
AnnaBridge	171:3a7713b1edbc	491	/** @defgroup TIM_Clock_Source TIM Clock Source
AnnaBridge	171:3a7713b1edbc	492	* @{
AnnaBridge	171:3a7713b1edbc	493	*/
AnnaBridge	171:3a7713b1edbc	494	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
AnnaBridge	171:3a7713b1edbc	495	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
AnnaBridge	171:3a7713b1edbc	496	#define TIM_CLOCKSOURCE_ITR0 (0x0000U)
AnnaBridge	171:3a7713b1edbc	497	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
AnnaBridge	171:3a7713b1edbc	498	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
AnnaBridge	171:3a7713b1edbc	499	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
AnnaBridge	171:3a7713b1edbc	500	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
AnnaBridge	171:3a7713b1edbc	501	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
AnnaBridge	171:3a7713b1edbc	502	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
AnnaBridge	171:3a7713b1edbc	503	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
AnnaBridge	171:3a7713b1edbc	504	/**
AnnaBridge	171:3a7713b1edbc	505	* @}
AnnaBridge	171:3a7713b1edbc	506	*/
AnnaBridge	171:3a7713b1edbc	507
AnnaBridge	171:3a7713b1edbc	508	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
AnnaBridge	171:3a7713b1edbc	509	* @{
AnnaBridge	171:3a7713b1edbc	510	*/
AnnaBridge	171:3a7713b1edbc	511	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
AnnaBridge	171:3a7713b1edbc	512	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
AnnaBridge	171:3a7713b1edbc	513	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
AnnaBridge	171:3a7713b1edbc	514	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
AnnaBridge	171:3a7713b1edbc	515	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
AnnaBridge	171:3a7713b1edbc	516	/**
AnnaBridge	171:3a7713b1edbc	517	* @}
AnnaBridge	171:3a7713b1edbc	518	*/
AnnaBridge	171:3a7713b1edbc	519
AnnaBridge	171:3a7713b1edbc	520	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
AnnaBridge	171:3a7713b1edbc	521	* @{
AnnaBridge	171:3a7713b1edbc	522	*/
AnnaBridge	171:3a7713b1edbc	523	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
AnnaBridge	171:3a7713b1edbc	524	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
AnnaBridge	171:3a7713b1edbc	525	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
AnnaBridge	171:3a7713b1edbc	526	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
AnnaBridge	171:3a7713b1edbc	527	/**
AnnaBridge	171:3a7713b1edbc	528	* @}
AnnaBridge	171:3a7713b1edbc	529	*/
AnnaBridge	171:3a7713b1edbc	530
AnnaBridge	171:3a7713b1edbc	531	/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
AnnaBridge	171:3a7713b1edbc	532	* @{
AnnaBridge	171:3a7713b1edbc	533	*/
AnnaBridge	171:3a7713b1edbc	534	#define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
AnnaBridge	171:3a7713b1edbc	535	#define TIM_CLEARINPUTSOURCE_OCREFCLR (0x0002U)
AnnaBridge	171:3a7713b1edbc	536	#define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
AnnaBridge	171:3a7713b1edbc	537	/**
AnnaBridge	171:3a7713b1edbc	538	* @}
AnnaBridge	171:3a7713b1edbc	539	*/
AnnaBridge	171:3a7713b1edbc	540
AnnaBridge	171:3a7713b1edbc	541	/** @defgroup TIM_ClearInput_Polarity TIM ClearInput Polarity
AnnaBridge	171:3a7713b1edbc	542	* @{
AnnaBridge	171:3a7713b1edbc	543	*/
AnnaBridge	171:3a7713b1edbc	544	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
AnnaBridge	171:3a7713b1edbc	545	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
AnnaBridge	171:3a7713b1edbc	546	/**
AnnaBridge	171:3a7713b1edbc	547	* @}
AnnaBridge	171:3a7713b1edbc	548	*/
AnnaBridge	171:3a7713b1edbc	549
AnnaBridge	171:3a7713b1edbc	550	/** @defgroup TIM_ClearInput_Prescaler TIM ClearInput Prescaler
AnnaBridge	171:3a7713b1edbc	551	* @{
AnnaBridge	171:3a7713b1edbc	552	*/
AnnaBridge	171:3a7713b1edbc	553	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
AnnaBridge	171:3a7713b1edbc	554	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
AnnaBridge	171:3a7713b1edbc	555	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
AnnaBridge	171:3a7713b1edbc	556	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
AnnaBridge	171:3a7713b1edbc	557	/**
AnnaBridge	171:3a7713b1edbc	558	* @}
AnnaBridge	171:3a7713b1edbc	559	*/
AnnaBridge	171:3a7713b1edbc	560
AnnaBridge	171:3a7713b1edbc	561	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
AnnaBridge	171:3a7713b1edbc	562	* @{
AnnaBridge	171:3a7713b1edbc	563	*/
AnnaBridge	171:3a7713b1edbc	564	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
AnnaBridge	171:3a7713b1edbc	565	#define TIM_OSSR_DISABLE (0x0000U)
AnnaBridge	171:3a7713b1edbc	566	/**
AnnaBridge	171:3a7713b1edbc	567	* @}
AnnaBridge	171:3a7713b1edbc	568	*/
AnnaBridge	171:3a7713b1edbc	569
AnnaBridge	171:3a7713b1edbc	570	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
AnnaBridge	171:3a7713b1edbc	571	* @{
AnnaBridge	171:3a7713b1edbc	572	*/
AnnaBridge	171:3a7713b1edbc	573	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
AnnaBridge	171:3a7713b1edbc	574	#define TIM_OSSI_DISABLE (0x0000U)
AnnaBridge	171:3a7713b1edbc	575	/**
AnnaBridge	171:3a7713b1edbc	576	* @}
AnnaBridge	171:3a7713b1edbc	577	*/
AnnaBridge	171:3a7713b1edbc	578
AnnaBridge	171:3a7713b1edbc	579	/** @defgroup TIM_Lock_level TIM Lock level
AnnaBridge	171:3a7713b1edbc	580	* @{
AnnaBridge	171:3a7713b1edbc	581	*/
AnnaBridge	171:3a7713b1edbc	582	#define TIM_LOCKLEVEL_OFF (0x0000U)
AnnaBridge	171:3a7713b1edbc	583	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
AnnaBridge	171:3a7713b1edbc	584	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
AnnaBridge	171:3a7713b1edbc	585	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
AnnaBridge	171:3a7713b1edbc	586	/**
AnnaBridge	171:3a7713b1edbc	587	* @}
AnnaBridge	171:3a7713b1edbc	588	*/
AnnaBridge	171:3a7713b1edbc	589
AnnaBridge	171:3a7713b1edbc	590	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
AnnaBridge	171:3a7713b1edbc	591	* @{
AnnaBridge	171:3a7713b1edbc	592	*/
AnnaBridge	171:3a7713b1edbc	593	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
AnnaBridge	171:3a7713b1edbc	594	#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
AnnaBridge	171:3a7713b1edbc	595	/**
AnnaBridge	171:3a7713b1edbc	596	* @}
AnnaBridge	171:3a7713b1edbc	597	*/
AnnaBridge	171:3a7713b1edbc	598
AnnaBridge	171:3a7713b1edbc	599	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
AnnaBridge	171:3a7713b1edbc	600	* @{
AnnaBridge	171:3a7713b1edbc	601	*/
AnnaBridge	171:3a7713b1edbc	602	#define TIM_TRGO_RESET (0x0000U)
AnnaBridge	171:3a7713b1edbc	603	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
AnnaBridge	171:3a7713b1edbc	604	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
AnnaBridge	171:3a7713b1edbc	605	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
AnnaBridge	171:3a7713b1edbc	606	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
AnnaBridge	171:3a7713b1edbc	607	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
AnnaBridge	171:3a7713b1edbc	608	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
AnnaBridge	171:3a7713b1edbc	609	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
AnnaBridge	171:3a7713b1edbc	610	/**
AnnaBridge	171:3a7713b1edbc	611	* @}
AnnaBridge	171:3a7713b1edbc	612	*/
AnnaBridge	171:3a7713b1edbc	613
AnnaBridge	171:3a7713b1edbc	614	/** @defgroup TIM_Slave_Mode TIM Slave Mode
AnnaBridge	171:3a7713b1edbc	615	* @{
AnnaBridge	171:3a7713b1edbc	616	*/
AnnaBridge	171:3a7713b1edbc	617	#define TIM_SLAVEMODE_DISABLE (0x0000U)
AnnaBridge	171:3a7713b1edbc	618	#define TIM_SLAVEMODE_RESET (0x0004U)
AnnaBridge	171:3a7713b1edbc	619	#define TIM_SLAVEMODE_GATED (0x0005U)
AnnaBridge	171:3a7713b1edbc	620	#define TIM_SLAVEMODE_TRIGGER (0x0006U)
AnnaBridge	171:3a7713b1edbc	621	#define TIM_SLAVEMODE_EXTERNAL1 (0x0007U)
AnnaBridge	171:3a7713b1edbc	622	/**
AnnaBridge	171:3a7713b1edbc	623	* @}
AnnaBridge	171:3a7713b1edbc	624	*/
AnnaBridge	171:3a7713b1edbc	625
AnnaBridge	171:3a7713b1edbc	626	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
AnnaBridge	171:3a7713b1edbc	627	* @{
AnnaBridge	171:3a7713b1edbc	628	*/
AnnaBridge	171:3a7713b1edbc	629	#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
AnnaBridge	171:3a7713b1edbc	630	#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
AnnaBridge	171:3a7713b1edbc	631	/**
AnnaBridge	171:3a7713b1edbc	632	* @}
AnnaBridge	171:3a7713b1edbc	633	*/
AnnaBridge	171:3a7713b1edbc	634
AnnaBridge	171:3a7713b1edbc	635	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
AnnaBridge	171:3a7713b1edbc	636	* @{
AnnaBridge	171:3a7713b1edbc	637	*/
AnnaBridge	171:3a7713b1edbc	638	#define TIM_TS_ITR0 (0x0000U)
AnnaBridge	171:3a7713b1edbc	639	#define TIM_TS_ITR1 (0x0010U)
AnnaBridge	171:3a7713b1edbc	640	#define TIM_TS_ITR2 (0x0020U)
AnnaBridge	171:3a7713b1edbc	641	#define TIM_TS_ITR3 (0x0030U)
AnnaBridge	171:3a7713b1edbc	642	#define TIM_TS_TI1F_ED (0x0040U)
AnnaBridge	171:3a7713b1edbc	643	#define TIM_TS_TI1FP1 (0x0050U)
AnnaBridge	171:3a7713b1edbc	644	#define TIM_TS_TI2FP2 (0x0060U)
AnnaBridge	171:3a7713b1edbc	645	#define TIM_TS_ETRF (0x0070U)
AnnaBridge	171:3a7713b1edbc	646	#define TIM_TS_NONE (0xFFFFU)
AnnaBridge	171:3a7713b1edbc	647	/**
AnnaBridge	171:3a7713b1edbc	648	* @}
AnnaBridge	171:3a7713b1edbc	649	*/
AnnaBridge	171:3a7713b1edbc	650
AnnaBridge	171:3a7713b1edbc	651	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
AnnaBridge	171:3a7713b1edbc	652	* @{
AnnaBridge	171:3a7713b1edbc	653	*/
AnnaBridge	171:3a7713b1edbc	654	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
AnnaBridge	171:3a7713b1edbc	655	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
AnnaBridge	171:3a7713b1edbc	656	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
AnnaBridge	171:3a7713b1edbc	657	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
AnnaBridge	171:3a7713b1edbc	658	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
AnnaBridge	171:3a7713b1edbc	659	/**
AnnaBridge	171:3a7713b1edbc	660	* @}
AnnaBridge	171:3a7713b1edbc	661	*/
AnnaBridge	171:3a7713b1edbc	662
AnnaBridge	171:3a7713b1edbc	663	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
AnnaBridge	171:3a7713b1edbc	664	* @{
AnnaBridge	171:3a7713b1edbc	665	*/
AnnaBridge	171:3a7713b1edbc	666	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
AnnaBridge	171:3a7713b1edbc	667	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
AnnaBridge	171:3a7713b1edbc	668	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
AnnaBridge	171:3a7713b1edbc	669	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
AnnaBridge	171:3a7713b1edbc	670	/**
AnnaBridge	171:3a7713b1edbc	671	* @}
AnnaBridge	171:3a7713b1edbc	672	*/
AnnaBridge	171:3a7713b1edbc	673
AnnaBridge	171:3a7713b1edbc	674	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
AnnaBridge	171:3a7713b1edbc	675	* @{
AnnaBridge	171:3a7713b1edbc	676	*/
AnnaBridge	171:3a7713b1edbc	677	#define TIM_TI1SELECTION_CH1 (0x0000U)
AnnaBridge	171:3a7713b1edbc	678	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
AnnaBridge	171:3a7713b1edbc	679	/**
AnnaBridge	171:3a7713b1edbc	680	* @}
AnnaBridge	171:3a7713b1edbc	681	*/
AnnaBridge	171:3a7713b1edbc	682
AnnaBridge	171:3a7713b1edbc	683	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
AnnaBridge	171:3a7713b1edbc	684	* @{
AnnaBridge	171:3a7713b1edbc	685	*/
AnnaBridge	171:3a7713b1edbc	686	#define TIM_DMABASE_CR1 (0x00000000U)
AnnaBridge	171:3a7713b1edbc	687	#define TIM_DMABASE_CR2 (0x00000001U)
AnnaBridge	171:3a7713b1edbc	688	#define TIM_DMABASE_SMCR (0x00000002U)
AnnaBridge	171:3a7713b1edbc	689	#define TIM_DMABASE_DIER (0x00000003U)
AnnaBridge	171:3a7713b1edbc	690	#define TIM_DMABASE_SR (0x00000004U)
AnnaBridge	171:3a7713b1edbc	691	#define TIM_DMABASE_EGR (0x00000005U)
AnnaBridge	171:3a7713b1edbc	692	#define TIM_DMABASE_CCMR1 (0x00000006U)
AnnaBridge	171:3a7713b1edbc	693	#define TIM_DMABASE_CCMR2 (0x00000007U)
AnnaBridge	171:3a7713b1edbc	694	#define TIM_DMABASE_CCER (0x00000008U)
AnnaBridge	171:3a7713b1edbc	695	#define TIM_DMABASE_CNT (0x00000009U)
AnnaBridge	171:3a7713b1edbc	696	#define TIM_DMABASE_PSC (0x0000000AU)
AnnaBridge	171:3a7713b1edbc	697	#define TIM_DMABASE_ARR (0x0000000BU)
AnnaBridge	171:3a7713b1edbc	698	#define TIM_DMABASE_CCR1 (0x0000000DU)
AnnaBridge	171:3a7713b1edbc	699	#define TIM_DMABASE_CCR2 (0x0000000EU)
AnnaBridge	171:3a7713b1edbc	700	#define TIM_DMABASE_CCR3 (0x0000000FU)
AnnaBridge	171:3a7713b1edbc	701	#define TIM_DMABASE_CCR4 (0x00000010U)
AnnaBridge	171:3a7713b1edbc	702	#define TIM_DMABASE_DCR (0x00000012U)
AnnaBridge	171:3a7713b1edbc	703	#define TIM_DMABASE_OR (0x00000013U)
AnnaBridge	171:3a7713b1edbc	704	/**
AnnaBridge	171:3a7713b1edbc	705	* @}
AnnaBridge	171:3a7713b1edbc	706	*/
AnnaBridge	171:3a7713b1edbc	707
AnnaBridge	171:3a7713b1edbc	708	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
AnnaBridge	171:3a7713b1edbc	709	* @{
AnnaBridge	171:3a7713b1edbc	710	*/
AnnaBridge	171:3a7713b1edbc	711	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
AnnaBridge	171:3a7713b1edbc	712	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
AnnaBridge	171:3a7713b1edbc	713	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
AnnaBridge	171:3a7713b1edbc	714	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
AnnaBridge	171:3a7713b1edbc	715	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
AnnaBridge	171:3a7713b1edbc	716	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
AnnaBridge	171:3a7713b1edbc	717	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
AnnaBridge	171:3a7713b1edbc	718	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
AnnaBridge	171:3a7713b1edbc	719	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
AnnaBridge	171:3a7713b1edbc	720	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
AnnaBridge	171:3a7713b1edbc	721	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
AnnaBridge	171:3a7713b1edbc	722	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
AnnaBridge	171:3a7713b1edbc	723	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
AnnaBridge	171:3a7713b1edbc	724	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
AnnaBridge	171:3a7713b1edbc	725	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
AnnaBridge	171:3a7713b1edbc	726	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
AnnaBridge	171:3a7713b1edbc	727	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
AnnaBridge	171:3a7713b1edbc	728	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
AnnaBridge	171:3a7713b1edbc	729	/**
AnnaBridge	171:3a7713b1edbc	730	* @}
AnnaBridge	171:3a7713b1edbc	731	*/
AnnaBridge	171:3a7713b1edbc	732
AnnaBridge	171:3a7713b1edbc	733	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
AnnaBridge	171:3a7713b1edbc	734	* @{
AnnaBridge	171:3a7713b1edbc	735	*/
AnnaBridge	171:3a7713b1edbc	736	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
AnnaBridge	171:3a7713b1edbc	737	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
AnnaBridge	171:3a7713b1edbc	738	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
AnnaBridge	171:3a7713b1edbc	739	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
AnnaBridge	171:3a7713b1edbc	740	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
AnnaBridge	171:3a7713b1edbc	741	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
AnnaBridge	171:3a7713b1edbc	742	/**
AnnaBridge	171:3a7713b1edbc	743	* @}
AnnaBridge	171:3a7713b1edbc	744	*/
AnnaBridge	171:3a7713b1edbc	745
AnnaBridge	171:3a7713b1edbc	746	/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
AnnaBridge	171:3a7713b1edbc	747	* @{
AnnaBridge	171:3a7713b1edbc	748	*/
AnnaBridge	171:3a7713b1edbc	749	#define TIM_CCx_ENABLE (0x0001U)
AnnaBridge	171:3a7713b1edbc	750	#define TIM_CCx_DISABLE (0x0000U)
AnnaBridge	171:3a7713b1edbc	751	/**
AnnaBridge	171:3a7713b1edbc	752	* @}
AnnaBridge	171:3a7713b1edbc	753	*/
AnnaBridge	171:3a7713b1edbc	754
AnnaBridge	171:3a7713b1edbc	755	/**
AnnaBridge	171:3a7713b1edbc	756	* @}
AnnaBridge	171:3a7713b1edbc	757	*/
AnnaBridge	171:3a7713b1edbc	758
AnnaBridge	171:3a7713b1edbc	759	/* Private Constants -----------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	760	/** @defgroup TIM_Private_Constants TIM Private Constants
AnnaBridge	171:3a7713b1edbc	761	* @{
AnnaBridge	171:3a7713b1edbc	762	*/
AnnaBridge	171:3a7713b1edbc	763
AnnaBridge	171:3a7713b1edbc	764	/* The counter of a timer instance is disabled only if all the CCx
AnnaBridge	171:3a7713b1edbc	765	channels have been disabled */
AnnaBridge	171:3a7713b1edbc	766	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
AnnaBridge	171:3a7713b1edbc	767	/**
AnnaBridge	171:3a7713b1edbc	768	* @}
AnnaBridge	171:3a7713b1edbc	769	*/
AnnaBridge	171:3a7713b1edbc	770
AnnaBridge	171:3a7713b1edbc	771	/* Private Macros -----------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	772	/** @defgroup TIM_Private_Macros TIM Private Macros
AnnaBridge	171:3a7713b1edbc	773	* @{
AnnaBridge	171:3a7713b1edbc	774	*/
AnnaBridge	171:3a7713b1edbc	775
AnnaBridge	171:3a7713b1edbc	776	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
AnnaBridge	171:3a7713b1edbc	777	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
AnnaBridge	171:3a7713b1edbc	778	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
AnnaBridge	171:3a7713b1edbc	779	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
AnnaBridge	171:3a7713b1edbc	780	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
AnnaBridge	171:3a7713b1edbc	781
AnnaBridge	171:3a7713b1edbc	782	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
AnnaBridge	171:3a7713b1edbc	783	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	784	((DIV) == TIM_CLOCKDIVISION_DIV4))
AnnaBridge	171:3a7713b1edbc	785
AnnaBridge	171:3a7713b1edbc	786	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
AnnaBridge	171:3a7713b1edbc	787	((MODE) == TIM_OCMODE_PWM2))
AnnaBridge	171:3a7713b1edbc	788
AnnaBridge	171:3a7713b1edbc	789	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
AnnaBridge	171:3a7713b1edbc	790	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
AnnaBridge	171:3a7713b1edbc	791	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
AnnaBridge	171:3a7713b1edbc	792	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
AnnaBridge	171:3a7713b1edbc	793	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
AnnaBridge	171:3a7713b1edbc	794	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
AnnaBridge	171:3a7713b1edbc	795
AnnaBridge	171:3a7713b1edbc	796	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	797	((STATE) == TIM_OCFAST_ENABLE))
AnnaBridge	171:3a7713b1edbc	798
AnnaBridge	171:3a7713b1edbc	799	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
AnnaBridge	171:3a7713b1edbc	800	((POLARITY) == TIM_OCPOLARITY_LOW))
AnnaBridge	171:3a7713b1edbc	801
AnnaBridge	171:3a7713b1edbc	802	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
AnnaBridge	171:3a7713b1edbc	803	((STATE) == TIM_OCIDLESTATE_RESET))
AnnaBridge	171:3a7713b1edbc	804
AnnaBridge	171:3a7713b1edbc	805	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
AnnaBridge	171:3a7713b1edbc	806	((CHANNEL) == TIM_CHANNEL_2) \|\| \
AnnaBridge	171:3a7713b1edbc	807	((CHANNEL) == TIM_CHANNEL_3) \|\| \
AnnaBridge	171:3a7713b1edbc	808	((CHANNEL) == TIM_CHANNEL_4) \|\| \
AnnaBridge	171:3a7713b1edbc	809	((CHANNEL) == TIM_CHANNEL_ALL))
AnnaBridge	171:3a7713b1edbc	810
AnnaBridge	171:3a7713b1edbc	811	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
AnnaBridge	171:3a7713b1edbc	812	((CHANNEL) == TIM_CHANNEL_2))
AnnaBridge	171:3a7713b1edbc	813
AnnaBridge	171:3a7713b1edbc	814	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
AnnaBridge	171:3a7713b1edbc	815	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
AnnaBridge	171:3a7713b1edbc	816	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
AnnaBridge	171:3a7713b1edbc	817
AnnaBridge	171:3a7713b1edbc	818	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
AnnaBridge	171:3a7713b1edbc	819	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
AnnaBridge	171:3a7713b1edbc	820	((SELECTION) == TIM_ICSELECTION_TRC))
AnnaBridge	171:3a7713b1edbc	821
AnnaBridge	171:3a7713b1edbc	822	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
AnnaBridge	171:3a7713b1edbc	823	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	824	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	825	((PRESCALER) == TIM_ICPSC_DIV8))
AnnaBridge	171:3a7713b1edbc	826
AnnaBridge	171:3a7713b1edbc	827	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
AnnaBridge	171:3a7713b1edbc	828	((MODE) == TIM_OPMODE_REPETITIVE))
AnnaBridge	171:3a7713b1edbc	829
AnnaBridge	171:3a7713b1edbc	830	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
AnnaBridge	171:3a7713b1edbc	831	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
AnnaBridge	171:3a7713b1edbc	832	((MODE) == TIM_ENCODERMODE_TI12))
AnnaBridge	171:3a7713b1edbc	833
AnnaBridge	171:3a7713b1edbc	834	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
AnnaBridge	171:3a7713b1edbc	835
AnnaBridge	171:3a7713b1edbc	836	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
AnnaBridge	171:3a7713b1edbc	837
AnnaBridge	171:3a7713b1edbc	838	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
AnnaBridge	171:3a7713b1edbc	839	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
AnnaBridge	171:3a7713b1edbc	840	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
AnnaBridge	171:3a7713b1edbc	841	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
AnnaBridge	171:3a7713b1edbc	842	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
AnnaBridge	171:3a7713b1edbc	843	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
AnnaBridge	171:3a7713b1edbc	844	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
AnnaBridge	171:3a7713b1edbc	845	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
AnnaBridge	171:3a7713b1edbc	846	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
AnnaBridge	171:3a7713b1edbc	847	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
AnnaBridge	171:3a7713b1edbc	848
AnnaBridge	171:3a7713b1edbc	849	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
AnnaBridge	171:3a7713b1edbc	850	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
AnnaBridge	171:3a7713b1edbc	851	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
AnnaBridge	171:3a7713b1edbc	852	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
AnnaBridge	171:3a7713b1edbc	853	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
AnnaBridge	171:3a7713b1edbc	854
AnnaBridge	171:3a7713b1edbc	855	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
AnnaBridge	171:3a7713b1edbc	856	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	857	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	858	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
AnnaBridge	171:3a7713b1edbc	859
AnnaBridge	171:3a7713b1edbc	860	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
AnnaBridge	171:3a7713b1edbc	861
AnnaBridge	171:3a7713b1edbc	862	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
AnnaBridge	171:3a7713b1edbc	863	((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) \|\| \
AnnaBridge	171:3a7713b1edbc	864	((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
AnnaBridge	171:3a7713b1edbc	865
AnnaBridge	171:3a7713b1edbc	866	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
AnnaBridge	171:3a7713b1edbc	867	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
AnnaBridge	171:3a7713b1edbc	868
AnnaBridge	171:3a7713b1edbc	869	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
AnnaBridge	171:3a7713b1edbc	870	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	871	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	872	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
AnnaBridge	171:3a7713b1edbc	873
AnnaBridge	171:3a7713b1edbc	874	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
AnnaBridge	171:3a7713b1edbc	875
AnnaBridge	171:3a7713b1edbc	876	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	877	((STATE) == TIM_OSSR_DISABLE))
AnnaBridge	171:3a7713b1edbc	878
AnnaBridge	171:3a7713b1edbc	879	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	880	((STATE) == TIM_OSSI_DISABLE))
AnnaBridge	171:3a7713b1edbc	881
AnnaBridge	171:3a7713b1edbc	882	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
AnnaBridge	171:3a7713b1edbc	883	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
AnnaBridge	171:3a7713b1edbc	884	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
AnnaBridge	171:3a7713b1edbc	885	((LEVEL) == TIM_LOCKLEVEL_3))
AnnaBridge	171:3a7713b1edbc	886
AnnaBridge	171:3a7713b1edbc	887	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	888	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
AnnaBridge	171:3a7713b1edbc	889
AnnaBridge	171:3a7713b1edbc	890	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
AnnaBridge	171:3a7713b1edbc	891	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	892	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
AnnaBridge	171:3a7713b1edbc	893	((SOURCE) == TIM_TRGO_OC1) \|\| \
AnnaBridge	171:3a7713b1edbc	894	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
AnnaBridge	171:3a7713b1edbc	895	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
AnnaBridge	171:3a7713b1edbc	896	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
AnnaBridge	171:3a7713b1edbc	897	((SOURCE) == TIM_TRGO_OC4REF))
AnnaBridge	171:3a7713b1edbc	898
AnnaBridge	171:3a7713b1edbc	899	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	900	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
AnnaBridge	171:3a7713b1edbc	901	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
AnnaBridge	171:3a7713b1edbc	902	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
AnnaBridge	171:3a7713b1edbc	903	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
AnnaBridge	171:3a7713b1edbc	904
AnnaBridge	171:3a7713b1edbc	905	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	906	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
AnnaBridge	171:3a7713b1edbc	907
AnnaBridge	171:3a7713b1edbc	908	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
AnnaBridge	171:3a7713b1edbc	909	((SELECTION) == TIM_TS_ITR1) \|\| \
AnnaBridge	171:3a7713b1edbc	910	((SELECTION) == TIM_TS_ITR2) \|\| \
AnnaBridge	171:3a7713b1edbc	911	((SELECTION) == TIM_TS_ITR3) \|\| \
AnnaBridge	171:3a7713b1edbc	912	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
AnnaBridge	171:3a7713b1edbc	913	((SELECTION) == TIM_TS_TI1FP1) \|\| \
AnnaBridge	171:3a7713b1edbc	914	((SELECTION) == TIM_TS_TI2FP2) \|\| \
AnnaBridge	171:3a7713b1edbc	915	((SELECTION) == TIM_TS_ETRF))
AnnaBridge	171:3a7713b1edbc	916
AnnaBridge	171:3a7713b1edbc	917	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
AnnaBridge	171:3a7713b1edbc	918	((SELECTION) == TIM_TS_ITR1) \|\| \
AnnaBridge	171:3a7713b1edbc	919	((SELECTION) == TIM_TS_ITR2) \|\| \
AnnaBridge	171:3a7713b1edbc	920	((SELECTION) == TIM_TS_ITR3) \|\| \
AnnaBridge	171:3a7713b1edbc	921	((SELECTION) == TIM_TS_NONE))
AnnaBridge	171:3a7713b1edbc	922
AnnaBridge	171:3a7713b1edbc	923	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
AnnaBridge	171:3a7713b1edbc	924	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
AnnaBridge	171:3a7713b1edbc	925	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
AnnaBridge	171:3a7713b1edbc	926	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
AnnaBridge	171:3a7713b1edbc	927	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
AnnaBridge	171:3a7713b1edbc	928
AnnaBridge	171:3a7713b1edbc	929	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
AnnaBridge	171:3a7713b1edbc	930	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	931	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	932	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
AnnaBridge	171:3a7713b1edbc	933
AnnaBridge	171:3a7713b1edbc	934	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
AnnaBridge	171:3a7713b1edbc	935
AnnaBridge	171:3a7713b1edbc	936	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
AnnaBridge	171:3a7713b1edbc	937	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
AnnaBridge	171:3a7713b1edbc	938
AnnaBridge	171:3a7713b1edbc	939	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
AnnaBridge	171:3a7713b1edbc	940	((BASE) == TIM_DMABASE_CR2) \|\| \
AnnaBridge	171:3a7713b1edbc	941	((BASE) == TIM_DMABASE_SMCR) \|\| \
AnnaBridge	171:3a7713b1edbc	942	((BASE) == TIM_DMABASE_DIER) \|\| \
AnnaBridge	171:3a7713b1edbc	943	((BASE) == TIM_DMABASE_SR) \|\| \
AnnaBridge	171:3a7713b1edbc	944	((BASE) == TIM_DMABASE_EGR) \|\| \
AnnaBridge	171:3a7713b1edbc	945	((BASE) == TIM_DMABASE_CCMR1) \|\| \
AnnaBridge	171:3a7713b1edbc	946	((BASE) == TIM_DMABASE_CCMR2) \|\| \
AnnaBridge	171:3a7713b1edbc	947	((BASE) == TIM_DMABASE_CCER) \|\| \
AnnaBridge	171:3a7713b1edbc	948	((BASE) == TIM_DMABASE_CNT) \|\| \
AnnaBridge	171:3a7713b1edbc	949	((BASE) == TIM_DMABASE_PSC) \|\| \
AnnaBridge	171:3a7713b1edbc	950	((BASE) == TIM_DMABASE_ARR) \|\| \
AnnaBridge	171:3a7713b1edbc	951	((BASE) == TIM_DMABASE_CCR1) \|\| \
AnnaBridge	171:3a7713b1edbc	952	((BASE) == TIM_DMABASE_CCR2) \|\| \
AnnaBridge	171:3a7713b1edbc	953	((BASE) == TIM_DMABASE_CCR3) \|\| \
AnnaBridge	171:3a7713b1edbc	954	((BASE) == TIM_DMABASE_CCR4) \|\| \
AnnaBridge	171:3a7713b1edbc	955	((BASE) == TIM_DMABASE_DCR) \|\| \
AnnaBridge	171:3a7713b1edbc	956	((BASE) == TIM_DMABASE_OR))
AnnaBridge	171:3a7713b1edbc	957
AnnaBridge	171:3a7713b1edbc	958	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
AnnaBridge	171:3a7713b1edbc	959	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	960	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	961	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	962	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	963	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	964	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	965	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	966	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	967	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	968	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	969	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	970	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	971	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	972	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	973	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	974	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
AnnaBridge	171:3a7713b1edbc	975	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
AnnaBridge	171:3a7713b1edbc	976
AnnaBridge	171:3a7713b1edbc	977	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
AnnaBridge	171:3a7713b1edbc	978
AnnaBridge	171:3a7713b1edbc	979	/** @brief Set TIM IC prescaler
AnnaBridge	171:3a7713b1edbc	980	* @param __HANDLE__: TIM handle
AnnaBridge	171:3a7713b1edbc	981	* @param __CHANNEL__: specifies TIM Channel
AnnaBridge	171:3a7713b1edbc	982	* @param __ICPSC__: specifies the prescaler value.
AnnaBridge	171:3a7713b1edbc	983	* @retval None
AnnaBridge	171:3a7713b1edbc	984	*/
AnnaBridge	171:3a7713b1edbc	985	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge	171:3a7713b1edbc	986	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
AnnaBridge	171:3a7713b1edbc	987	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
AnnaBridge	171:3a7713b1edbc	988	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
AnnaBridge	171:3a7713b1edbc	989	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
AnnaBridge	171:3a7713b1edbc	990
AnnaBridge	171:3a7713b1edbc	991	/** @brief Reset TIM IC prescaler
AnnaBridge	171:3a7713b1edbc	992	* @param __HANDLE__: TIM handle
AnnaBridge	171:3a7713b1edbc	993	* @param __CHANNEL__: specifies TIM Channel
AnnaBridge	171:3a7713b1edbc	994	* @retval None
AnnaBridge	171:3a7713b1edbc	995	*/
AnnaBridge	171:3a7713b1edbc	996	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
AnnaBridge	171:3a7713b1edbc	997	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
AnnaBridge	171:3a7713b1edbc	998	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
AnnaBridge	171:3a7713b1edbc	999	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
AnnaBridge	171:3a7713b1edbc	1000	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
AnnaBridge	171:3a7713b1edbc	1001
AnnaBridge	171:3a7713b1edbc	1002
AnnaBridge	171:3a7713b1edbc	1003	/** @brief Set TIM IC polarity
AnnaBridge	171:3a7713b1edbc	1004	* @param __HANDLE__: TIM handle
AnnaBridge	171:3a7713b1edbc	1005	* @param __CHANNEL__: specifies TIM Channel
AnnaBridge	171:3a7713b1edbc	1006	* @param __POLARITY__: specifies TIM Channel Polarity
AnnaBridge	171:3a7713b1edbc	1007	* @retval None
AnnaBridge	171:3a7713b1edbc	1008	*/
AnnaBridge	171:3a7713b1edbc	1009	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge	171:3a7713b1edbc	1010	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
AnnaBridge	171:3a7713b1edbc	1011	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
AnnaBridge	171:3a7713b1edbc	1012	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
AnnaBridge	171:3a7713b1edbc	1013	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
AnnaBridge	171:3a7713b1edbc	1014
AnnaBridge	171:3a7713b1edbc	1015	/** @brief Reset TIM IC polarity
AnnaBridge	171:3a7713b1edbc	1016	* @param __HANDLE__: TIM handle
AnnaBridge	171:3a7713b1edbc	1017	* @param __CHANNEL__: specifies TIM Channel
AnnaBridge	171:3a7713b1edbc	1018	* @retval None
AnnaBridge	171:3a7713b1edbc	1019	*/
AnnaBridge	171:3a7713b1edbc	1020	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
AnnaBridge	171:3a7713b1edbc	1021	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
AnnaBridge	171:3a7713b1edbc	1022	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
AnnaBridge	171:3a7713b1edbc	1023	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
AnnaBridge	171:3a7713b1edbc	1024	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
AnnaBridge	171:3a7713b1edbc	1025
AnnaBridge	171:3a7713b1edbc	1026	/**
AnnaBridge	171:3a7713b1edbc	1027	* @}
AnnaBridge	171:3a7713b1edbc	1028	*/
AnnaBridge	171:3a7713b1edbc	1029
AnnaBridge	171:3a7713b1edbc	1030	/* Private Functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1031
AnnaBridge	171:3a7713b1edbc	1032	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1033	/** @defgroup TIM_Exported_Macros TIM Exported Macros
AnnaBridge	171:3a7713b1edbc	1034	* @{
AnnaBridge	171:3a7713b1edbc	1035	*/
AnnaBridge	171:3a7713b1edbc	1036
AnnaBridge	171:3a7713b1edbc	1037	/** @brief Reset TIM handle state
AnnaBridge	171:3a7713b1edbc	1038	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1039	* @retval None
AnnaBridge	171:3a7713b1edbc	1040	*/
AnnaBridge	171:3a7713b1edbc	1041	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
AnnaBridge	171:3a7713b1edbc	1042
AnnaBridge	171:3a7713b1edbc	1043	/**
AnnaBridge	171:3a7713b1edbc	1044	* @brief Enable the TIM peripheral.
AnnaBridge	171:3a7713b1edbc	1045	* @param __HANDLE__: TIM handle
AnnaBridge	171:3a7713b1edbc	1046	* @retval None
AnnaBridge	171:3a7713b1edbc	1047	*/
AnnaBridge	171:3a7713b1edbc	1048	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
AnnaBridge	171:3a7713b1edbc	1049
AnnaBridge	171:3a7713b1edbc	1050	/**
AnnaBridge	171:3a7713b1edbc	1051	* @brief Disable the TIM peripheral.
AnnaBridge	171:3a7713b1edbc	1052	* @param __HANDLE__: TIM handle
AnnaBridge	171:3a7713b1edbc	1053	* @retval None
AnnaBridge	171:3a7713b1edbc	1054	*/
AnnaBridge	171:3a7713b1edbc	1055	#define __HAL_TIM_DISABLE(__HANDLE__) \
AnnaBridge	171:3a7713b1edbc	1056	do { \
AnnaBridge	171:3a7713b1edbc	1057	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
AnnaBridge	171:3a7713b1edbc	1058	{ \
AnnaBridge	171:3a7713b1edbc	1059	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
AnnaBridge	171:3a7713b1edbc	1060	} \
AnnaBridge	171:3a7713b1edbc	1061	} while(0)
AnnaBridge	171:3a7713b1edbc	1062
AnnaBridge	171:3a7713b1edbc	1063	/**
AnnaBridge	171:3a7713b1edbc	1064	* @brief Enables the specified TIM interrupt.
AnnaBridge	171:3a7713b1edbc	1065	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	171:3a7713b1edbc	1066	* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
AnnaBridge	171:3a7713b1edbc	1067	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1068	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	171:3a7713b1edbc	1069	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge	171:3a7713b1edbc	1070	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge	171:3a7713b1edbc	1071	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge	171:3a7713b1edbc	1072	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	171:3a7713b1edbc	1073	* @arg TIM_IT_COM: Commutation interrupt
AnnaBridge	171:3a7713b1edbc	1074	* @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge	171:3a7713b1edbc	1075	* @retval None
AnnaBridge	171:3a7713b1edbc	1076	*/
AnnaBridge	171:3a7713b1edbc	1077	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1078
AnnaBridge	171:3a7713b1edbc	1079	/**
AnnaBridge	171:3a7713b1edbc	1080	* @brief Disables the specified TIM interrupt.
AnnaBridge	171:3a7713b1edbc	1081	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	171:3a7713b1edbc	1082	* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
AnnaBridge	171:3a7713b1edbc	1083	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1084	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	171:3a7713b1edbc	1085	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge	171:3a7713b1edbc	1086	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge	171:3a7713b1edbc	1087	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge	171:3a7713b1edbc	1088	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	171:3a7713b1edbc	1089	* @arg TIM_IT_COM: Commutation interrupt
AnnaBridge	171:3a7713b1edbc	1090	* @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge	171:3a7713b1edbc	1091	* @retval None
AnnaBridge	171:3a7713b1edbc	1092	*/
AnnaBridge	171:3a7713b1edbc	1093	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1094
AnnaBridge	171:3a7713b1edbc	1095	/**
AnnaBridge	171:3a7713b1edbc	1096	* @brief Enables the specified DMA request.
AnnaBridge	171:3a7713b1edbc	1097	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	171:3a7713b1edbc	1098	* @param __DMA__: specifies the TIM DMA request to enable.
AnnaBridge	171:3a7713b1edbc	1099	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1100	* @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge	171:3a7713b1edbc	1101	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge	171:3a7713b1edbc	1102	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge	171:3a7713b1edbc	1103	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge	171:3a7713b1edbc	1104	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge	171:3a7713b1edbc	1105	* @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge	171:3a7713b1edbc	1106	* @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge	171:3a7713b1edbc	1107	* @retval None
AnnaBridge	171:3a7713b1edbc	1108	*/
AnnaBridge	171:3a7713b1edbc	1109	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
AnnaBridge	171:3a7713b1edbc	1110
AnnaBridge	171:3a7713b1edbc	1111	/**
AnnaBridge	171:3a7713b1edbc	1112	* @brief Disables the specified DMA request.
AnnaBridge	171:3a7713b1edbc	1113	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	171:3a7713b1edbc	1114	* @param __DMA__: specifies the TIM DMA request to disable.
AnnaBridge	171:3a7713b1edbc	1115	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1116	* @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge	171:3a7713b1edbc	1117	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge	171:3a7713b1edbc	1118	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge	171:3a7713b1edbc	1119	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge	171:3a7713b1edbc	1120	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge	171:3a7713b1edbc	1121	* @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge	171:3a7713b1edbc	1122	* @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge	171:3a7713b1edbc	1123	* @retval None
AnnaBridge	171:3a7713b1edbc	1124	*/
AnnaBridge	171:3a7713b1edbc	1125	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
AnnaBridge	171:3a7713b1edbc	1126
AnnaBridge	171:3a7713b1edbc	1127	/**
AnnaBridge	171:3a7713b1edbc	1128	* @brief Checks whether the specified TIM interrupt flag is set or not.
AnnaBridge	171:3a7713b1edbc	1129	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	171:3a7713b1edbc	1130	* @param __FLAG__: specifies the TIM interrupt flag to check.
AnnaBridge	171:3a7713b1edbc	1131	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1132	* @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge	171:3a7713b1edbc	1133	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge	171:3a7713b1edbc	1134	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge	171:3a7713b1edbc	1135	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge	171:3a7713b1edbc	1136	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge	171:3a7713b1edbc	1137	* @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge	171:3a7713b1edbc	1138	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge	171:3a7713b1edbc	1139	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge	171:3a7713b1edbc	1140	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge	171:3a7713b1edbc	1141	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge	171:3a7713b1edbc	1142	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge	171:3a7713b1edbc	1143	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	171:3a7713b1edbc	1144	*/
AnnaBridge	171:3a7713b1edbc	1145	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge	171:3a7713b1edbc	1146
AnnaBridge	171:3a7713b1edbc	1147	/**
AnnaBridge	171:3a7713b1edbc	1148	* @brief Clears the specified TIM interrupt flag.
AnnaBridge	171:3a7713b1edbc	1149	* @param __HANDLE__: specifies the TIM Handle.
AnnaBridge	171:3a7713b1edbc	1150	* @param __FLAG__: specifies the TIM interrupt flag to clear.
AnnaBridge	171:3a7713b1edbc	1151	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1152	* @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge	171:3a7713b1edbc	1153	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge	171:3a7713b1edbc	1154	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge	171:3a7713b1edbc	1155	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge	171:3a7713b1edbc	1156	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge	171:3a7713b1edbc	1157	* @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge	171:3a7713b1edbc	1158	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge	171:3a7713b1edbc	1159	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge	171:3a7713b1edbc	1160	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge	171:3a7713b1edbc	1161	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge	171:3a7713b1edbc	1162	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge	171:3a7713b1edbc	1163	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	171:3a7713b1edbc	1164	*/
AnnaBridge	171:3a7713b1edbc	1165	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
AnnaBridge	171:3a7713b1edbc	1166
AnnaBridge	171:3a7713b1edbc	1167	/**
AnnaBridge	171:3a7713b1edbc	1168	* @brief Checks whether the specified TIM interrupt has occurred or not.
AnnaBridge	171:3a7713b1edbc	1169	* @param __HANDLE__: TIM handle
AnnaBridge	171:3a7713b1edbc	1170	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
AnnaBridge	171:3a7713b1edbc	1171	* @retval The state of TIM_IT (SET or RESET).
AnnaBridge	171:3a7713b1edbc	1172	*/
AnnaBridge	171:3a7713b1edbc	1173	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge	171:3a7713b1edbc	1174
AnnaBridge	171:3a7713b1edbc	1175	/**
AnnaBridge	171:3a7713b1edbc	1176	* @brief Clear the TIM interrupt pending bits
AnnaBridge	171:3a7713b1edbc	1177	* @param __HANDLE__: TIM handle
AnnaBridge	171:3a7713b1edbc	1178	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge	171:3a7713b1edbc	1179	* @retval None
AnnaBridge	171:3a7713b1edbc	1180	*/
AnnaBridge	171:3a7713b1edbc	1181	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1182
AnnaBridge	171:3a7713b1edbc	1183	/**
AnnaBridge	171:3a7713b1edbc	1184	* @brief Indicates whether or not the TIM Counter is used as downcounter
AnnaBridge	171:3a7713b1edbc	1185	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1186	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
AnnaBridge	171:3a7713b1edbc	1187	* @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
AnnaBridge	171:3a7713b1edbc	1188	mode.
AnnaBridge	171:3a7713b1edbc	1189	*/
AnnaBridge	171:3a7713b1edbc	1190	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
AnnaBridge	171:3a7713b1edbc	1191
AnnaBridge	171:3a7713b1edbc	1192	/**
AnnaBridge	171:3a7713b1edbc	1193	* @brief Sets the TIM active prescaler register value on update event.
AnnaBridge	171:3a7713b1edbc	1194	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1195	* @param __PRESC__: specifies the active prescaler register new value.
AnnaBridge	171:3a7713b1edbc	1196	* @retval None
AnnaBridge	171:3a7713b1edbc	1197	*/
AnnaBridge	171:3a7713b1edbc	1198	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
AnnaBridge	171:3a7713b1edbc	1199
AnnaBridge	171:3a7713b1edbc	1200	/**
AnnaBridge	171:3a7713b1edbc	1201	* @brief Sets the TIM Capture Compare Register value on runtime without
AnnaBridge	171:3a7713b1edbc	1202	* calling another time ConfigChannel function.
AnnaBridge	171:3a7713b1edbc	1203	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1204	* @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge	171:3a7713b1edbc	1205	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1206	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge	171:3a7713b1edbc	1207	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge	171:3a7713b1edbc	1208	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge	171:3a7713b1edbc	1209	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge	171:3a7713b1edbc	1210	* @param __COMPARE__: specifies the Capture Compare register new value.
AnnaBridge	171:3a7713b1edbc	1211	* @retval None
AnnaBridge	171:3a7713b1edbc	1212	*/
AnnaBridge	171:3a7713b1edbc	1213	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
AnnaBridge	171:3a7713b1edbc	1214	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
AnnaBridge	171:3a7713b1edbc	1215
AnnaBridge	171:3a7713b1edbc	1216	/**
AnnaBridge	171:3a7713b1edbc	1217	* @brief Gets the TIM Capture Compare Register value on runtime
AnnaBridge	171:3a7713b1edbc	1218	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1219	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
AnnaBridge	171:3a7713b1edbc	1220	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1221	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
AnnaBridge	171:3a7713b1edbc	1222	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
AnnaBridge	171:3a7713b1edbc	1223	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
AnnaBridge	171:3a7713b1edbc	1224	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge	171:3a7713b1edbc	1225	* @retval None
AnnaBridge	171:3a7713b1edbc	1226	*/
AnnaBridge	171:3a7713b1edbc	1227	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
AnnaBridge	171:3a7713b1edbc	1228	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
AnnaBridge	171:3a7713b1edbc	1229
AnnaBridge	171:3a7713b1edbc	1230	/**
AnnaBridge	171:3a7713b1edbc	1231	* @brief Sets the TIM Counter Register value on runtime.
AnnaBridge	171:3a7713b1edbc	1232	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1233	* @param __COUNTER__: specifies the Counter register new value.
AnnaBridge	171:3a7713b1edbc	1234	* @retval None
AnnaBridge	171:3a7713b1edbc	1235	*/
AnnaBridge	171:3a7713b1edbc	1236	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
AnnaBridge	171:3a7713b1edbc	1237
AnnaBridge	171:3a7713b1edbc	1238	/**
AnnaBridge	171:3a7713b1edbc	1239	* @brief Gets the TIM Counter Register value on runtime.
AnnaBridge	171:3a7713b1edbc	1240	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1241	* @retval None
AnnaBridge	171:3a7713b1edbc	1242	*/
AnnaBridge	171:3a7713b1edbc	1243	#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
AnnaBridge	171:3a7713b1edbc	1244	((__HANDLE__)->Instance->CNT)
AnnaBridge	171:3a7713b1edbc	1245
AnnaBridge	171:3a7713b1edbc	1246	/**
AnnaBridge	171:3a7713b1edbc	1247	* @brief Sets the TIM Autoreload Register value on runtime without calling
AnnaBridge	171:3a7713b1edbc	1248	* another time any Init function.
AnnaBridge	171:3a7713b1edbc	1249	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1250	* @param __AUTORELOAD__: specifies the Counter register new value.
AnnaBridge	171:3a7713b1edbc	1251	* @retval None
AnnaBridge	171:3a7713b1edbc	1252	*/
AnnaBridge	171:3a7713b1edbc	1253	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
AnnaBridge	171:3a7713b1edbc	1254	do{ \
AnnaBridge	171:3a7713b1edbc	1255	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
AnnaBridge	171:3a7713b1edbc	1256	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
AnnaBridge	171:3a7713b1edbc	1257	} while(0)
AnnaBridge	171:3a7713b1edbc	1258
AnnaBridge	171:3a7713b1edbc	1259	/**
AnnaBridge	171:3a7713b1edbc	1260	* @brief Gets the TIM Autoreload Register value on runtime
AnnaBridge	171:3a7713b1edbc	1261	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1262	* @retval None
AnnaBridge	171:3a7713b1edbc	1263	*/
AnnaBridge	171:3a7713b1edbc	1264	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
AnnaBridge	171:3a7713b1edbc	1265	((__HANDLE__)->Instance->ARR)
AnnaBridge	171:3a7713b1edbc	1266
AnnaBridge	171:3a7713b1edbc	1267	/**
AnnaBridge	171:3a7713b1edbc	1268	* @brief Sets the TIM Clock Division value on runtime without calling
AnnaBridge	171:3a7713b1edbc	1269	* another time any Init function.
AnnaBridge	171:3a7713b1edbc	1270	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1271	* @param __CKD__: specifies the clock division value.
AnnaBridge	171:3a7713b1edbc	1272	* This parameter can be one of the following value:
AnnaBridge	171:3a7713b1edbc	1273	* @arg TIM_CLOCKDIVISION_DIV1
AnnaBridge	171:3a7713b1edbc	1274	* @arg TIM_CLOCKDIVISION_DIV2
AnnaBridge	171:3a7713b1edbc	1275	* @arg TIM_CLOCKDIVISION_DIV4
AnnaBridge	171:3a7713b1edbc	1276	* @retval None
AnnaBridge	171:3a7713b1edbc	1277	*/
AnnaBridge	171:3a7713b1edbc	1278	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
AnnaBridge	171:3a7713b1edbc	1279	do{ \
AnnaBridge	171:3a7713b1edbc	1280	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
AnnaBridge	171:3a7713b1edbc	1281	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
AnnaBridge	171:3a7713b1edbc	1282	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
AnnaBridge	171:3a7713b1edbc	1283	} while(0)
AnnaBridge	171:3a7713b1edbc	1284
AnnaBridge	171:3a7713b1edbc	1285	/**
AnnaBridge	171:3a7713b1edbc	1286	* @brief Gets the TIM Clock Division value on runtime
AnnaBridge	171:3a7713b1edbc	1287	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1288	* @retval None
AnnaBridge	171:3a7713b1edbc	1289	*/
AnnaBridge	171:3a7713b1edbc	1290	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
AnnaBridge	171:3a7713b1edbc	1291	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
AnnaBridge	171:3a7713b1edbc	1292
AnnaBridge	171:3a7713b1edbc	1293	/**
AnnaBridge	171:3a7713b1edbc	1294	* @brief Sets the TIM Input Capture prescaler on runtime without calling
AnnaBridge	171:3a7713b1edbc	1295	* another time HAL_TIM_IC_ConfigChannel() function.
AnnaBridge	171:3a7713b1edbc	1296	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1297	* @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge	171:3a7713b1edbc	1298	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1299	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge	171:3a7713b1edbc	1300	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge	171:3a7713b1edbc	1301	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge	171:3a7713b1edbc	1302	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge	171:3a7713b1edbc	1303	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
AnnaBridge	171:3a7713b1edbc	1304	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1305	* @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge	171:3a7713b1edbc	1306	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge	171:3a7713b1edbc	1307	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge	171:3a7713b1edbc	1308	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge	171:3a7713b1edbc	1309	* @retval None
AnnaBridge	171:3a7713b1edbc	1310	*/
AnnaBridge	171:3a7713b1edbc	1311	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge	171:3a7713b1edbc	1312	do{ \
AnnaBridge	171:3a7713b1edbc	1313	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
AnnaBridge	171:3a7713b1edbc	1314	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
AnnaBridge	171:3a7713b1edbc	1315	} while(0)
AnnaBridge	171:3a7713b1edbc	1316
AnnaBridge	171:3a7713b1edbc	1317	/**
AnnaBridge	171:3a7713b1edbc	1318	* @brief Gets the TIM Input Capture prescaler on runtime
AnnaBridge	171:3a7713b1edbc	1319	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1320	* @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge	171:3a7713b1edbc	1321	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1322	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
AnnaBridge	171:3a7713b1edbc	1323	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
AnnaBridge	171:3a7713b1edbc	1324	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
AnnaBridge	171:3a7713b1edbc	1325	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
AnnaBridge	171:3a7713b1edbc	1326	* @retval None
AnnaBridge	171:3a7713b1edbc	1327	*/
AnnaBridge	171:3a7713b1edbc	1328	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
AnnaBridge	171:3a7713b1edbc	1329	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
AnnaBridge	171:3a7713b1edbc	1330	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
AnnaBridge	171:3a7713b1edbc	1331	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
AnnaBridge	171:3a7713b1edbc	1332	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
AnnaBridge	171:3a7713b1edbc	1333
AnnaBridge	171:3a7713b1edbc	1334	/**
AnnaBridge	171:3a7713b1edbc	1335	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge	171:3a7713b1edbc	1336	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1337	* @note When the USR bit of the TIMx_CR1 register is set, only counter
AnnaBridge	171:3a7713b1edbc	1338	* overflow/underflow generates an update interrupt or DMA request (if
AnnaBridge	171:3a7713b1edbc	1339	* enabled)
AnnaBridge	171:3a7713b1edbc	1340	* @retval None
AnnaBridge	171:3a7713b1edbc	1341	*/
AnnaBridge	171:3a7713b1edbc	1342	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
AnnaBridge	171:3a7713b1edbc	1343	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
AnnaBridge	171:3a7713b1edbc	1344
AnnaBridge	171:3a7713b1edbc	1345	/**
AnnaBridge	171:3a7713b1edbc	1346	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge	171:3a7713b1edbc	1347	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1348	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
AnnaBridge	171:3a7713b1edbc	1349	* following events generate an update interrupt or DMA request (if
AnnaBridge	171:3a7713b1edbc	1350	* enabled):
AnnaBridge	171:3a7713b1edbc	1351	* (+) Counter overflow/underflow
AnnaBridge	171:3a7713b1edbc	1352	* (+) Setting the UG bit
AnnaBridge	171:3a7713b1edbc	1353	* (+) Update generation through the slave mode controller
AnnaBridge	171:3a7713b1edbc	1354	* @retval None
AnnaBridge	171:3a7713b1edbc	1355	*/
AnnaBridge	171:3a7713b1edbc	1356	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
AnnaBridge	171:3a7713b1edbc	1357	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
AnnaBridge	171:3a7713b1edbc	1358
AnnaBridge	171:3a7713b1edbc	1359	/**
AnnaBridge	171:3a7713b1edbc	1360	* @brief Sets the TIM Capture x input polarity on runtime.
AnnaBridge	171:3a7713b1edbc	1361	* @param __HANDLE__: TIM handle.
AnnaBridge	171:3a7713b1edbc	1362	* @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge	171:3a7713b1edbc	1363	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1364	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge	171:3a7713b1edbc	1365	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge	171:3a7713b1edbc	1366	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge	171:3a7713b1edbc	1367	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge	171:3a7713b1edbc	1368	* @param __POLARITY__: Polarity for TIx source
AnnaBridge	171:3a7713b1edbc	1369	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
AnnaBridge	171:3a7713b1edbc	1370	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
AnnaBridge	171:3a7713b1edbc	1371	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
AnnaBridge	171:3a7713b1edbc	1372	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
AnnaBridge	171:3a7713b1edbc	1373	* @retval None
AnnaBridge	171:3a7713b1edbc	1374	*/
AnnaBridge	171:3a7713b1edbc	1375	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge	171:3a7713b1edbc	1376	do{ \
AnnaBridge	171:3a7713b1edbc	1377	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
AnnaBridge	171:3a7713b1edbc	1378	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
AnnaBridge	171:3a7713b1edbc	1379	}while(0)
AnnaBridge	171:3a7713b1edbc	1380
AnnaBridge	171:3a7713b1edbc	1381	/**
AnnaBridge	171:3a7713b1edbc	1382	* @}
AnnaBridge	171:3a7713b1edbc	1383	*/
AnnaBridge	171:3a7713b1edbc	1384
AnnaBridge	171:3a7713b1edbc	1385	/* Include TIM HAL Extension module */
AnnaBridge	171:3a7713b1edbc	1386	#include "stm32l1xx_hal_tim_ex.h"
AnnaBridge	171:3a7713b1edbc	1387
AnnaBridge	171:3a7713b1edbc	1388	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1389	/** @addtogroup TIM_Exported_Functions
AnnaBridge	171:3a7713b1edbc	1390	* @{
AnnaBridge	171:3a7713b1edbc	1391	*/
AnnaBridge	171:3a7713b1edbc	1392
AnnaBridge	171:3a7713b1edbc	1393	/** @addtogroup TIM_Exported_Functions_Group1
AnnaBridge	171:3a7713b1edbc	1394	* @{
AnnaBridge	171:3a7713b1edbc	1395	*/
AnnaBridge	171:3a7713b1edbc	1396	/* Time Base functions ********************************************************/
AnnaBridge	171:3a7713b1edbc	1397	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1398	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1399	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1400	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1401	/* Blocking mode: Polling */
AnnaBridge	171:3a7713b1edbc	1402	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1403	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1404	/* Non-Blocking mode: Interrupt */
AnnaBridge	171:3a7713b1edbc	1405	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1406	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1407	/* Non-Blocking mode: DMA */
AnnaBridge	171:3a7713b1edbc	1408	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
AnnaBridge	171:3a7713b1edbc	1409	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1410	/**
AnnaBridge	171:3a7713b1edbc	1411	* @}
AnnaBridge	171:3a7713b1edbc	1412	*/
AnnaBridge	171:3a7713b1edbc	1413
AnnaBridge	171:3a7713b1edbc	1414	/** @addtogroup TIM_Exported_Functions_Group2
AnnaBridge	171:3a7713b1edbc	1415	* @{
AnnaBridge	171:3a7713b1edbc	1416	*/
AnnaBridge	171:3a7713b1edbc	1417	/* Timer Output Compare functions **********************************************/
AnnaBridge	171:3a7713b1edbc	1418	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1419	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1420	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1421	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1422	/* Blocking mode: Polling */
AnnaBridge	171:3a7713b1edbc	1423	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1424	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1425	/* Non-Blocking mode: Interrupt */
AnnaBridge	171:3a7713b1edbc	1426	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1427	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1428	/* Non-Blocking mode: DMA */
AnnaBridge	171:3a7713b1edbc	1429	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
AnnaBridge	171:3a7713b1edbc	1430	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1431
AnnaBridge	171:3a7713b1edbc	1432	/**
AnnaBridge	171:3a7713b1edbc	1433	* @}
AnnaBridge	171:3a7713b1edbc	1434	*/
AnnaBridge	171:3a7713b1edbc	1435
AnnaBridge	171:3a7713b1edbc	1436	/** @addtogroup TIM_Exported_Functions_Group3
AnnaBridge	171:3a7713b1edbc	1437	* @{
AnnaBridge	171:3a7713b1edbc	1438	*/
AnnaBridge	171:3a7713b1edbc	1439	/* Timer PWM functions *********************************************************/
AnnaBridge	171:3a7713b1edbc	1440	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1441	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1442	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1443	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1444	/* Blocking mode: Polling */
AnnaBridge	171:3a7713b1edbc	1445	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1446	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1447	/* Non-Blocking mode: Interrupt */
AnnaBridge	171:3a7713b1edbc	1448	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1449	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1450	/* Non-Blocking mode: DMA */
AnnaBridge	171:3a7713b1edbc	1451	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
AnnaBridge	171:3a7713b1edbc	1452	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1453	/**
AnnaBridge	171:3a7713b1edbc	1454	* @}
AnnaBridge	171:3a7713b1edbc	1455	*/
AnnaBridge	171:3a7713b1edbc	1456
AnnaBridge	171:3a7713b1edbc	1457	/** @addtogroup TIM_Exported_Functions_Group4
AnnaBridge	171:3a7713b1edbc	1458	* @{
AnnaBridge	171:3a7713b1edbc	1459	*/
AnnaBridge	171:3a7713b1edbc	1460	/* Timer Input Capture functions ***********************************************/
AnnaBridge	171:3a7713b1edbc	1461	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1462	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1463	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1464	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1465	/* Blocking mode: Polling */
AnnaBridge	171:3a7713b1edbc	1466	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1467	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1468	/* Non-Blocking mode: Interrupt */
AnnaBridge	171:3a7713b1edbc	1469	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1470	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1471	/* Non-Blocking mode: DMA */
AnnaBridge	171:3a7713b1edbc	1472	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
AnnaBridge	171:3a7713b1edbc	1473	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1474	/**
AnnaBridge	171:3a7713b1edbc	1475	* @}
AnnaBridge	171:3a7713b1edbc	1476	*/
AnnaBridge	171:3a7713b1edbc	1477
AnnaBridge	171:3a7713b1edbc	1478	/** @addtogroup TIM_Exported_Functions_Group5
AnnaBridge	171:3a7713b1edbc	1479	* @{
AnnaBridge	171:3a7713b1edbc	1480	*/
AnnaBridge	171:3a7713b1edbc	1481	/* Timer One Pulse functions ***************************************************/
AnnaBridge	171:3a7713b1edbc	1482	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
AnnaBridge	171:3a7713b1edbc	1483	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1484	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1485	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1486	/* Blocking mode: Polling */
AnnaBridge	171:3a7713b1edbc	1487	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	171:3a7713b1edbc	1488	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	171:3a7713b1edbc	1489	/* Non-Blocking mode: Interrupt */
AnnaBridge	171:3a7713b1edbc	1490	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	171:3a7713b1edbc	1491	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	171:3a7713b1edbc	1492	/**
AnnaBridge	171:3a7713b1edbc	1493	* @}
AnnaBridge	171:3a7713b1edbc	1494	*/
AnnaBridge	171:3a7713b1edbc	1495
AnnaBridge	171:3a7713b1edbc	1496	/** @addtogroup TIM_Exported_Functions_Group6
AnnaBridge	171:3a7713b1edbc	1497	* @{
AnnaBridge	171:3a7713b1edbc	1498	*/
AnnaBridge	171:3a7713b1edbc	1499	/* Timer Encoder functions *****************************************************/
AnnaBridge	171:3a7713b1edbc	1500	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
AnnaBridge	171:3a7713b1edbc	1501	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1502	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1503	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1504	/* Blocking mode: Polling */
AnnaBridge	171:3a7713b1edbc	1505	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1506	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1507	/* Non-Blocking mode: Interrupt */
AnnaBridge	171:3a7713b1edbc	1508	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1509	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1510	/* Non-Blocking mode: DMA */
AnnaBridge	171:3a7713b1edbc	1511	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
AnnaBridge	171:3a7713b1edbc	1512	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1513
AnnaBridge	171:3a7713b1edbc	1514	/**
AnnaBridge	171:3a7713b1edbc	1515	* @}
AnnaBridge	171:3a7713b1edbc	1516	*/
AnnaBridge	171:3a7713b1edbc	1517
AnnaBridge	171:3a7713b1edbc	1518	/** @addtogroup TIM_Exported_Functions_Group7
AnnaBridge	171:3a7713b1edbc	1519	* @{
AnnaBridge	171:3a7713b1edbc	1520	*/
AnnaBridge	171:3a7713b1edbc	1521	/* Interrupt Handler functions **********************************************/
AnnaBridge	171:3a7713b1edbc	1522	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1523	/**
AnnaBridge	171:3a7713b1edbc	1524	* @}
AnnaBridge	171:3a7713b1edbc	1525	*/
AnnaBridge	171:3a7713b1edbc	1526
AnnaBridge	171:3a7713b1edbc	1527	/** @addtogroup TIM_Exported_Functions_Group8
AnnaBridge	171:3a7713b1edbc	1528	* @{
AnnaBridge	171:3a7713b1edbc	1529	*/
AnnaBridge	171:3a7713b1edbc	1530	/* Control functions *********************************************************/
AnnaBridge	171:3a7713b1edbc	1531	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1532	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1533	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1534	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
AnnaBridge	171:3a7713b1edbc	1535	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1536	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
AnnaBridge	171:3a7713b1edbc	1537	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
AnnaBridge	171:3a7713b1edbc	1538	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
AnnaBridge	171:3a7713b1edbc	1539	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
AnnaBridge	171:3a7713b1edbc	1540	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge	171:3a7713b1edbc	1541	uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge	171:3a7713b1edbc	1542	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge	171:3a7713b1edbc	1543	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge	171:3a7713b1edbc	1544	uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge	171:3a7713b1edbc	1545	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge	171:3a7713b1edbc	1546	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
AnnaBridge	171:3a7713b1edbc	1547	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1548
AnnaBridge	171:3a7713b1edbc	1549	/**
AnnaBridge	171:3a7713b1edbc	1550	* @}
AnnaBridge	171:3a7713b1edbc	1551	*/
AnnaBridge	171:3a7713b1edbc	1552
AnnaBridge	171:3a7713b1edbc	1553	/** @addtogroup TIM_Exported_Functions_Group9
AnnaBridge	171:3a7713b1edbc	1554	* @{
AnnaBridge	171:3a7713b1edbc	1555	*/
AnnaBridge	171:3a7713b1edbc	1556	/* Callback in non blocking modes (Interrupt and DMA) *************************/
AnnaBridge	171:3a7713b1edbc	1557	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1558	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1559	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1560	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1561	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1562	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1563	/**
AnnaBridge	171:3a7713b1edbc	1564	* @}
AnnaBridge	171:3a7713b1edbc	1565	*/
AnnaBridge	171:3a7713b1edbc	1566
AnnaBridge	171:3a7713b1edbc	1567	/** @addtogroup TIM_Exported_Functions_Group10
AnnaBridge	171:3a7713b1edbc	1568	* @{
AnnaBridge	171:3a7713b1edbc	1569	*/
AnnaBridge	171:3a7713b1edbc	1570	/* Peripheral State functions **************************************************/
AnnaBridge	171:3a7713b1edbc	1571	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1572	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1573	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1574	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1575	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1576	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	171:3a7713b1edbc	1577
AnnaBridge	171:3a7713b1edbc	1578	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
AnnaBridge	171:3a7713b1edbc	1579	void TIM_DMAError(DMA_HandleTypeDef *hdma);
AnnaBridge	171:3a7713b1edbc	1580	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
AnnaBridge	171:3a7713b1edbc	1581
AnnaBridge	171:3a7713b1edbc	1582	/**
AnnaBridge	171:3a7713b1edbc	1583	* @}
AnnaBridge	171:3a7713b1edbc	1584	*/
AnnaBridge	171:3a7713b1edbc	1585
AnnaBridge	171:3a7713b1edbc	1586	/**
AnnaBridge	171:3a7713b1edbc	1587	* @}
AnnaBridge	171:3a7713b1edbc	1588	*/
AnnaBridge	171:3a7713b1edbc	1589
AnnaBridge	171:3a7713b1edbc	1590	/**
AnnaBridge	171:3a7713b1edbc	1591	* @}
AnnaBridge	171:3a7713b1edbc	1592	*/
AnnaBridge	171:3a7713b1edbc	1593
AnnaBridge	171:3a7713b1edbc	1594	/**
AnnaBridge	171:3a7713b1edbc	1595	* @}
AnnaBridge	171:3a7713b1edbc	1596	*/
AnnaBridge	171:3a7713b1edbc	1597
AnnaBridge	171:3a7713b1edbc	1598	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1599	}
AnnaBridge	171:3a7713b1edbc	1600	#endif
AnnaBridge	171:3a7713b1edbc	1601
AnnaBridge	171:3a7713b1edbc	1602	#endif /* __STM32L1xx_HAL_TIM_H */
AnnaBridge	171:3a7713b1edbc	1603
AnnaBridge	171:3a7713b1edbc	1604	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/