mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32630FTHR/TOOLCHAIN_IAR/pt_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * @file
AnnaBridge 171:3a7713b1edbc 3 * @brief Type definitions for the Pulse Train Engine.
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 */
AnnaBridge 171:3a7713b1edbc 6 /* ****************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 10 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 11 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 13 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 14 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 17 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 25 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 29 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 32 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 33 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 35 * ownership rights.
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * $Date: 2016-10-10 19:27:24 -0500 (Mon, 10 Oct 2016) $
AnnaBridge 171:3a7713b1edbc 38 * $Revision: 24669 $
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 **************************************************************************** */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /* Define to prevent redundant inclusion */
AnnaBridge 171:3a7713b1edbc 43 #ifndef _MXC_PT_REGS_H_
AnnaBridge 171:3a7713b1edbc 44 #define _MXC_PT_REGS_H_
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* **** Includes **** */
AnnaBridge 171:3a7713b1edbc 47 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 50 extern "C" {
AnnaBridge 171:3a7713b1edbc 51 #endif
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54 ///@cond
AnnaBridge 171:3a7713b1edbc 55 /*
AnnaBridge 171:3a7713b1edbc 56 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 57 */
AnnaBridge 171:3a7713b1edbc 58 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 59 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 60 #endif
AnnaBridge 171:3a7713b1edbc 61 #ifndef __I
AnnaBridge 171:3a7713b1edbc 62 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 63 #endif
AnnaBridge 171:3a7713b1edbc 64 #ifndef __O
AnnaBridge 171:3a7713b1edbc 65 #define __O volatile
AnnaBridge 171:3a7713b1edbc 66 #endif
AnnaBridge 171:3a7713b1edbc 67 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 68 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 69 #endif
AnnaBridge 171:3a7713b1edbc 70 ///@endcond
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 /**
AnnaBridge 171:3a7713b1edbc 73 * @ingroup pulsetrain
AnnaBridge 171:3a7713b1edbc 74 * @defgroup pulsetrain_registers Registers
AnnaBridge 171:3a7713b1edbc 75 * @brief Registers, Bit Masks and Bit Positions
AnnaBridge 171:3a7713b1edbc 76 * @{
AnnaBridge 171:3a7713b1edbc 77 */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 /**
AnnaBridge 171:3a7713b1edbc 80 * Structure type for the Pulse Train Global module registers allowing direct 32-bit access to each register.
AnnaBridge 171:3a7713b1edbc 81 */
AnnaBridge 171:3a7713b1edbc 82 typedef struct {
AnnaBridge 171:3a7713b1edbc 83 __IO uint32_t enable; /**< <tt>\b 0x0000:</tt> \c PTG_ENABLE Register - Global Enable/Disable Controls for All Pulse Trains. */
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t resync; /**< <tt>\b 0x0004:</tt> \c PTG_RESYNC Register - Global Resync (All Pulse Trains) Control. */
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> \c PTG_INTFL Register - Pulse Train Interrupt Flags. */
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t inten; /**< <tt>\b 0x000C:</tt> \c PTG_INTEN Register - Pulse Train Interrupt Enable/Disable. */
AnnaBridge 171:3a7713b1edbc 87 } mxc_ptg_regs_t;
AnnaBridge 171:3a7713b1edbc 88
AnnaBridge 171:3a7713b1edbc 89 /**
AnnaBridge 171:3a7713b1edbc 90 * Structure type for the Pulse Train configuration registers allowing direct 32-bit access to each register.
AnnaBridge 171:3a7713b1edbc 91 */
AnnaBridge 171:3a7713b1edbc 92 typedef struct {
AnnaBridge 171:3a7713b1edbc 93 __IO uint32_t rate_length; /**< <tt>\b 0x0000:</tt>\c PT_RATE_LENGTH Register - Pulse Train Configuration. */
AnnaBridge 171:3a7713b1edbc 94 __IO uint32_t train; /**< <tt>\b 0x0004:</tt>\c PT_TRAIN Register - Pulse Train Output Pattern. */
AnnaBridge 171:3a7713b1edbc 95 __IO uint32_t loop; /**< <tt>\b 0x0008:</tt>\c PT_LOOP Register - Pulse Train Loop Configuration. */
AnnaBridge 171:3a7713b1edbc 96 __IO uint32_t restart; /**< <tt>\b 0x000C:</tt>\c PT_RESTART Register - Pulse Train Auto-Restart Configuration. */
AnnaBridge 171:3a7713b1edbc 97 } mxc_pt_regs_t;
AnnaBridge 171:3a7713b1edbc 98 /**@} end of pulsetrain_registers group*/
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 /*
AnnaBridge 171:3a7713b1edbc 101 Register offsets for module PT.
AnnaBridge 171:3a7713b1edbc 102 */
AnnaBridge 171:3a7713b1edbc 103 /**
AnnaBridge 171:3a7713b1edbc 104 * @ingroup pulsetrain_registers
AnnaBridge 171:3a7713b1edbc 105 * @defgroup PTG_Register_Offsets Global Register Offsets
AnnaBridge 171:3a7713b1edbc 106 * @brief Pluse Train Global Control Register Offsets from the Pulse Train Global Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 107 * @{
AnnaBridge 171:3a7713b1edbc 108 */
AnnaBridge 171:3a7713b1edbc 109 #define MXC_R_PTG_OFFS_ENABLE ((uint32_t)0x00000000UL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x0000</tt> */
AnnaBridge 171:3a7713b1edbc 110 #define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x0004</tt> */
AnnaBridge 171:3a7713b1edbc 111 #define MXC_R_PTG_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x0008</tt> */
AnnaBridge 171:3a7713b1edbc 112 #define MXC_R_PTG_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x000C</tt> */
AnnaBridge 171:3a7713b1edbc 113 /**@} end of group PTG_Register_Offsets*/
AnnaBridge 171:3a7713b1edbc 114 /**
AnnaBridge 171:3a7713b1edbc 115 * @ingroup pulsetrain_registers
AnnaBridge 171:3a7713b1edbc 116 * @defgroup PT_Register_Offsets Register Offsets: Configuration
AnnaBridge 171:3a7713b1edbc 117 * @brief Pluse Train Configuration Register Offsets from the Pulse Train Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 118 * @{
AnnaBridge 171:3a7713b1edbc 119 */
AnnaBridge 171:3a7713b1edbc 120 #define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x0000</tt> */
AnnaBridge 171:3a7713b1edbc 121 #define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x0004</tt> */
AnnaBridge 171:3a7713b1edbc 122 #define MXC_R_PT_OFFS_LOOP ((uint32_t)0x00000008UL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x0008</tt> */
AnnaBridge 171:3a7713b1edbc 123 #define MXC_R_PT_OFFS_RESTART ((uint32_t)0x0000000CUL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x000C</tt> */
AnnaBridge 171:3a7713b1edbc 124 /**@} end of group PT_Register_Offsets*/
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 /*
AnnaBridge 171:3a7713b1edbc 127 Field positions and masks for module PT.
AnnaBridge 171:3a7713b1edbc 128 */
AnnaBridge 171:3a7713b1edbc 129 /**
AnnaBridge 171:3a7713b1edbc 130 * @ingroup pulsetrain_registers
AnnaBridge 171:3a7713b1edbc 131 * @defgroup PT_ENABLE_Register PT_ENABLE
AnnaBridge 171:3a7713b1edbc 132 * @brief Field Positions and Masks
AnnaBridge 171:3a7713b1edbc 133 * @{
AnnaBridge 171:3a7713b1edbc 134 */
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_PT_ENABLE_PT0_POS 0 /**< PT0 Position */
AnnaBridge 171:3a7713b1edbc 136 #define MXC_F_PT_ENABLE_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT0_POS)) /**< PT0 Mask */
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_PT_ENABLE_PT1_POS 1 /**< PT1 Position */
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_PT_ENABLE_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT1_POS)) /**< PT1 Mask */
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_PT_ENABLE_PT2_POS 2 /**< PT2 Position */
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_PT_ENABLE_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT2_POS)) /**< PT2 Mask */
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_PT_ENABLE_PT3_POS 3 /**< PT3 Position */
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_PT_ENABLE_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT3_POS)) /**< PT3 Mask */
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_PT_ENABLE_PT4_POS 4 /**< PT4 Position */
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_PT_ENABLE_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT4_POS)) /**< PT4 Mask */
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_PT_ENABLE_PT5_POS 5 /**< PT5 Position */
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_PT_ENABLE_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT5_POS)) /**< PT5 Mask */
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_PT_ENABLE_PT6_POS 6 /**< PT6 Position */
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_PT_ENABLE_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT6_POS)) /**< PT6 Mask */
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_PT_ENABLE_PT7_POS 7 /**< PT7 Position */
AnnaBridge 171:3a7713b1edbc 150 #define MXC_F_PT_ENABLE_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT7_POS)) /**< PT7 Mask */
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_PT_ENABLE_PT8_POS 8 /**< PT8 Position */
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_PT_ENABLE_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT8_POS)) /**< PT8 Mask */
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_PT_ENABLE_PT9_POS 9 /**< PT9 Position */
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_PT_ENABLE_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT9_POS)) /**< PT9 Mask */
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_PT_ENABLE_PT10_POS 10 /**< PT10 Position */
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_PT_ENABLE_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT10_POS)) /**< PT10 Mask */
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_PT_ENABLE_PT11_POS 11 /**< PT11 Position */
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_PT_ENABLE_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT11_POS)) /**< PT11 Mask */
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_PT_ENABLE_PT12_POS 12 /**< PT12 Position */
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_PT_ENABLE_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT12_POS)) /**< PT12 Mask */
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_PT_ENABLE_PT13_POS 13 /**< PT13 Position */
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_PT_ENABLE_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT13_POS)) /**< PT13 Mask */
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_PT_ENABLE_PT14_POS 14 /**< PT14 Position */
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_PT_ENABLE_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT14_POS)) /**< PT14 Mask */
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_PT_ENABLE_PT15_POS 15 /**< PT15 Position */
AnnaBridge 171:3a7713b1edbc 166 #define MXC_F_PT_ENABLE_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT15_POS)) /**< PT15 Mask */
AnnaBridge 171:3a7713b1edbc 167 /**@} PT_ENABLE_Register*/
AnnaBridge 171:3a7713b1edbc 168 /**
AnnaBridge 171:3a7713b1edbc 169 * @ingroup pulsetrain_registers
AnnaBridge 171:3a7713b1edbc 170 * @defgroup PT_RESYNC_Register PT_RESYNC
AnnaBridge 171:3a7713b1edbc 171 * @brief Field Positions and Masks
AnnaBridge 171:3a7713b1edbc 172 * @{
AnnaBridge 171:3a7713b1edbc 173 */
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_PT_RESYNC_PT0_POS 0 /**< PT0 Position */
AnnaBridge 171:3a7713b1edbc 175 #define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS)) /**< PT0 Mask */
AnnaBridge 171:3a7713b1edbc 176 #define MXC_F_PT_RESYNC_PT1_POS 1 /**< PT1 Position */
AnnaBridge 171:3a7713b1edbc 177 #define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS)) /**< PT1 Mask */
AnnaBridge 171:3a7713b1edbc 178 #define MXC_F_PT_RESYNC_PT2_POS 2 /**< PT2 Position */
AnnaBridge 171:3a7713b1edbc 179 #define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS)) /**< PT2 Mask */
AnnaBridge 171:3a7713b1edbc 180 #define MXC_F_PT_RESYNC_PT3_POS 3 /**< PT3 Position */
AnnaBridge 171:3a7713b1edbc 181 #define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS)) /**< PT3 Mask */
AnnaBridge 171:3a7713b1edbc 182 #define MXC_F_PT_RESYNC_PT4_POS 4 /**< PT4 Position */
AnnaBridge 171:3a7713b1edbc 183 #define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS)) /**< PT4 Mask */
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_PT_RESYNC_PT5_POS 5 /**< PT5 Position */
AnnaBridge 171:3a7713b1edbc 185 #define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS)) /**< PT5 Mask */
AnnaBridge 171:3a7713b1edbc 186 #define MXC_F_PT_RESYNC_PT6_POS 6 /**< PT6 Position */
AnnaBridge 171:3a7713b1edbc 187 #define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS)) /**< PT6 Mask */
AnnaBridge 171:3a7713b1edbc 188 #define MXC_F_PT_RESYNC_PT7_POS 7 /**< PT7 Position */
AnnaBridge 171:3a7713b1edbc 189 #define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS)) /**< PT7 Mask */
AnnaBridge 171:3a7713b1edbc 190 #define MXC_F_PT_RESYNC_PT8_POS 8 /**< PT8 Position */
AnnaBridge 171:3a7713b1edbc 191 #define MXC_F_PT_RESYNC_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT8_POS)) /**< PT8 Mask */
AnnaBridge 171:3a7713b1edbc 192 #define MXC_F_PT_RESYNC_PT9_POS 9 /**< PT9 Position */
AnnaBridge 171:3a7713b1edbc 193 #define MXC_F_PT_RESYNC_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT9_POS)) /**< PT9 Mask */
AnnaBridge 171:3a7713b1edbc 194 #define MXC_F_PT_RESYNC_PT10_POS 10 /**< PT10 Position */
AnnaBridge 171:3a7713b1edbc 195 #define MXC_F_PT_RESYNC_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT10_POS)) /**< PT10 Mask */
AnnaBridge 171:3a7713b1edbc 196 #define MXC_F_PT_RESYNC_PT11_POS 11 /**< PT11 Position */
AnnaBridge 171:3a7713b1edbc 197 #define MXC_F_PT_RESYNC_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT11_POS)) /**< PT11 Mask */
AnnaBridge 171:3a7713b1edbc 198 #define MXC_F_PT_RESYNC_PT12_POS 12 /**< PT12 Position */
AnnaBridge 171:3a7713b1edbc 199 #define MXC_F_PT_RESYNC_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT12_POS)) /**< PT12 Mask */
AnnaBridge 171:3a7713b1edbc 200 #define MXC_F_PT_RESYNC_PT13_POS 13 /**< PT13 Position */
AnnaBridge 171:3a7713b1edbc 201 #define MXC_F_PT_RESYNC_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT13_POS)) /**< PT13 Mask */
AnnaBridge 171:3a7713b1edbc 202 #define MXC_F_PT_RESYNC_PT14_POS 14 /**< PT14 Position */
AnnaBridge 171:3a7713b1edbc 203 #define MXC_F_PT_RESYNC_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT14_POS)) /**< PT14 Mask */
AnnaBridge 171:3a7713b1edbc 204 #define MXC_F_PT_RESYNC_PT15_POS 15 /**< PT15 Position */
AnnaBridge 171:3a7713b1edbc 205 #define MXC_F_PT_RESYNC_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT15_POS)) /**< PT15 Mask */
AnnaBridge 171:3a7713b1edbc 206 /**@} PT_RESYNC_Register*/
AnnaBridge 171:3a7713b1edbc 207 /**
AnnaBridge 171:3a7713b1edbc 208 * @ingroup pulsetrain_registers
AnnaBridge 171:3a7713b1edbc 209 * @defgroup PT_INTFL_Register PT_INTFL
AnnaBridge 171:3a7713b1edbc 210 * @brief Field Positions and Masks
AnnaBridge 171:3a7713b1edbc 211 * @{
AnnaBridge 171:3a7713b1edbc 212 */
AnnaBridge 171:3a7713b1edbc 213 #define MXC_F_PT_INTFL_PT0_POS 0 /**< PT0 Position */
AnnaBridge 171:3a7713b1edbc 214 #define MXC_F_PT_INTFL_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT0_POS)) /**< PT0 Mask */
AnnaBridge 171:3a7713b1edbc 215 #define MXC_F_PT_INTFL_PT1_POS 1 /**< PT1 Position */
AnnaBridge 171:3a7713b1edbc 216 #define MXC_F_PT_INTFL_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT1_POS)) /**< PT1 Mask */
AnnaBridge 171:3a7713b1edbc 217 #define MXC_F_PT_INTFL_PT2_POS 2 /**< PT2 Position */
AnnaBridge 171:3a7713b1edbc 218 #define MXC_F_PT_INTFL_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT2_POS)) /**< PT2 Mask */
AnnaBridge 171:3a7713b1edbc 219 #define MXC_F_PT_INTFL_PT3_POS 3 /**< PT3 Position */
AnnaBridge 171:3a7713b1edbc 220 #define MXC_F_PT_INTFL_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT3_POS)) /**< PT3 Mask */
AnnaBridge 171:3a7713b1edbc 221 #define MXC_F_PT_INTFL_PT4_POS 4 /**< PT4 Position */
AnnaBridge 171:3a7713b1edbc 222 #define MXC_F_PT_INTFL_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT4_POS)) /**< PT4 Mask */
AnnaBridge 171:3a7713b1edbc 223 #define MXC_F_PT_INTFL_PT5_POS 5 /**< PT5 Position */
AnnaBridge 171:3a7713b1edbc 224 #define MXC_F_PT_INTFL_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT5_POS)) /**< PT5 Mask */
AnnaBridge 171:3a7713b1edbc 225 #define MXC_F_PT_INTFL_PT6_POS 6 /**< PT6 Position */
AnnaBridge 171:3a7713b1edbc 226 #define MXC_F_PT_INTFL_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT6_POS)) /**< PT6 Mask */
AnnaBridge 171:3a7713b1edbc 227 #define MXC_F_PT_INTFL_PT7_POS 7 /**< PT7 Position */
AnnaBridge 171:3a7713b1edbc 228 #define MXC_F_PT_INTFL_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT7_POS)) /**< PT7 Mask */
AnnaBridge 171:3a7713b1edbc 229 #define MXC_F_PT_INTFL_PT8_POS 8 /**< PT8 Position */
AnnaBridge 171:3a7713b1edbc 230 #define MXC_F_PT_INTFL_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT8_POS)) /**< PT8 Mask */
AnnaBridge 171:3a7713b1edbc 231 #define MXC_F_PT_INTFL_PT9_POS 9 /**< PT9 Position */
AnnaBridge 171:3a7713b1edbc 232 #define MXC_F_PT_INTFL_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT9_POS)) /**< PT9 Mask */
AnnaBridge 171:3a7713b1edbc 233 #define MXC_F_PT_INTFL_PT10_POS 10 /**< PT10 Position */
AnnaBridge 171:3a7713b1edbc 234 #define MXC_F_PT_INTFL_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT10_POS)) /**< PT10 Mask */
AnnaBridge 171:3a7713b1edbc 235 #define MXC_F_PT_INTFL_PT11_POS 11 /**< PT11 Position */
AnnaBridge 171:3a7713b1edbc 236 #define MXC_F_PT_INTFL_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT11_POS)) /**< PT11 Mask */
AnnaBridge 171:3a7713b1edbc 237 #define MXC_F_PT_INTFL_PT12_POS 12 /**< PT12 Position */
AnnaBridge 171:3a7713b1edbc 238 #define MXC_F_PT_INTFL_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT12_POS)) /**< PT12 Mask */
AnnaBridge 171:3a7713b1edbc 239 #define MXC_F_PT_INTFL_PT13_POS 13 /**< PT13 Position */
AnnaBridge 171:3a7713b1edbc 240 #define MXC_F_PT_INTFL_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT13_POS)) /**< PT13 Mask */
AnnaBridge 171:3a7713b1edbc 241 #define MXC_F_PT_INTFL_PT14_POS 14 /**< PT14 Position */
AnnaBridge 171:3a7713b1edbc 242 #define MXC_F_PT_INTFL_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT14_POS)) /**< PT14 Mask */
AnnaBridge 171:3a7713b1edbc 243 #define MXC_F_PT_INTFL_PT15_POS 15 /**< PT15 Position */
AnnaBridge 171:3a7713b1edbc 244 #define MXC_F_PT_INTFL_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT15_POS)) /**< PT15 Mask */
AnnaBridge 171:3a7713b1edbc 245 /**@} PT_INTFL_Register*/
AnnaBridge 171:3a7713b1edbc 246 /**
AnnaBridge 171:3a7713b1edbc 247 * @ingroup pulsetrain_registers
AnnaBridge 171:3a7713b1edbc 248 * @defgroup PT_INTEN_Register PT_INTEN
AnnaBridge 171:3a7713b1edbc 249 * @brief Field Positions and Masks
AnnaBridge 171:3a7713b1edbc 250 * @{
AnnaBridge 171:3a7713b1edbc 251 */
AnnaBridge 171:3a7713b1edbc 252 #define MXC_F_PT_INTEN_PT0_POS 0 /**< PT0 Position */
AnnaBridge 171:3a7713b1edbc 253 #define MXC_F_PT_INTEN_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT0_POS)) /**< PT0 Mask */
AnnaBridge 171:3a7713b1edbc 254 #define MXC_F_PT_INTEN_PT1_POS 1 /**< PT1 Position */
AnnaBridge 171:3a7713b1edbc 255 #define MXC_F_PT_INTEN_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT1_POS)) /**< PT1 Mask */
AnnaBridge 171:3a7713b1edbc 256 #define MXC_F_PT_INTEN_PT2_POS 2 /**< PT2 Position */
AnnaBridge 171:3a7713b1edbc 257 #define MXC_F_PT_INTEN_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT2_POS)) /**< PT2 Mask */
AnnaBridge 171:3a7713b1edbc 258 #define MXC_F_PT_INTEN_PT3_POS 3 /**< PT3 Position */
AnnaBridge 171:3a7713b1edbc 259 #define MXC_F_PT_INTEN_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT3_POS)) /**< PT3 Mask */
AnnaBridge 171:3a7713b1edbc 260 #define MXC_F_PT_INTEN_PT4_POS 4 /**< PT4 Position */
AnnaBridge 171:3a7713b1edbc 261 #define MXC_F_PT_INTEN_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT4_POS)) /**< PT4 Mask */
AnnaBridge 171:3a7713b1edbc 262 #define MXC_F_PT_INTEN_PT5_POS 5 /**< PT5 Position */
AnnaBridge 171:3a7713b1edbc 263 #define MXC_F_PT_INTEN_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT5_POS)) /**< PT5 Mask */
AnnaBridge 171:3a7713b1edbc 264 #define MXC_F_PT_INTEN_PT6_POS 6 /**< PT6 Position */
AnnaBridge 171:3a7713b1edbc 265 #define MXC_F_PT_INTEN_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT6_POS)) /**< PT6 Mask */
AnnaBridge 171:3a7713b1edbc 266 #define MXC_F_PT_INTEN_PT7_POS 7 /**< PT7 Position */
AnnaBridge 171:3a7713b1edbc 267 #define MXC_F_PT_INTEN_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT7_POS)) /**< PT7 Mask */
AnnaBridge 171:3a7713b1edbc 268 #define MXC_F_PT_INTEN_PT8_POS 8 /**< PT8 Position */
AnnaBridge 171:3a7713b1edbc 269 #define MXC_F_PT_INTEN_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT8_POS)) /**< PT8 Mask */
AnnaBridge 171:3a7713b1edbc 270 #define MXC_F_PT_INTEN_PT9_POS 9 /**< PT9 Position */
AnnaBridge 171:3a7713b1edbc 271 #define MXC_F_PT_INTEN_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT9_POS)) /**< PT9 Mask */
AnnaBridge 171:3a7713b1edbc 272 #define MXC_F_PT_INTEN_PT10_POS 10 /**< PT10 Position*/
AnnaBridge 171:3a7713b1edbc 273 #define MXC_F_PT_INTEN_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT10_POS)) /**< PT10 Mask */
AnnaBridge 171:3a7713b1edbc 274 #define MXC_F_PT_INTEN_PT11_POS 11 /**< PT11 Position*/
AnnaBridge 171:3a7713b1edbc 275 #define MXC_F_PT_INTEN_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT11_POS)) /**< PT11 Mask */
AnnaBridge 171:3a7713b1edbc 276 #define MXC_F_PT_INTEN_PT12_POS 12 /**< PT12 Position*/
AnnaBridge 171:3a7713b1edbc 277 #define MXC_F_PT_INTEN_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT12_POS)) /**< PT12 Mask */
AnnaBridge 171:3a7713b1edbc 278 #define MXC_F_PT_INTEN_PT13_POS 13 /**< PT13 Position*/
AnnaBridge 171:3a7713b1edbc 279 #define MXC_F_PT_INTEN_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT13_POS)) /**< PT13 Mask */
AnnaBridge 171:3a7713b1edbc 280 #define MXC_F_PT_INTEN_PT14_POS 14 /**< PT14 Position*/
AnnaBridge 171:3a7713b1edbc 281 #define MXC_F_PT_INTEN_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT14_POS)) /**< PT14 Mask */
AnnaBridge 171:3a7713b1edbc 282 #define MXC_F_PT_INTEN_PT15_POS 15 /**< PT15 Position*/
AnnaBridge 171:3a7713b1edbc 283 #define MXC_F_PT_INTEN_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT15_POS)) /**< PT15 Mask */
AnnaBridge 171:3a7713b1edbc 284 /**@} PT_INTEN_Register*/
AnnaBridge 171:3a7713b1edbc 285 /**
AnnaBridge 171:3a7713b1edbc 286 * @ingroup pulsetrain_registers
AnnaBridge 171:3a7713b1edbc 287 * @defgroup PT_RATE_LENGTH_Register PT_RATE_LENGTH
AnnaBridge 171:3a7713b1edbc 288 * @brief Field Positions and Masks
AnnaBridge 171:3a7713b1edbc 289 * @{
AnnaBridge 171:3a7713b1edbc 290 */
AnnaBridge 171:3a7713b1edbc 291 #define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 /**< RATE_CONTROL Position */
AnnaBridge 171:3a7713b1edbc 292 #define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) /**< RATE_CONTROL Mask */
AnnaBridge 171:3a7713b1edbc 293 #define MXC_F_PT_RATE_LENGTH_MODE_POS 27 /**< MODE Position */
AnnaBridge 171:3a7713b1edbc 294 #define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< MODE Mask */
AnnaBridge 171:3a7713b1edbc 295 /**@} PT_RATE_Register*/
AnnaBridge 171:3a7713b1edbc 296 /**
AnnaBridge 171:3a7713b1edbc 297 * @ingroup pulsetrain_registers
AnnaBridge 171:3a7713b1edbc 298 * @defgroup PT_LOOP_Register PT_LOOP
AnnaBridge 171:3a7713b1edbc 299 * @brief Field Positions and Masks
AnnaBridge 171:3a7713b1edbc 300 * @{
AnnaBridge 171:3a7713b1edbc 301 */
AnnaBridge 171:3a7713b1edbc 302 #define MXC_F_PT_LOOP_COUNT_POS 0 /**< COUNT Position */
AnnaBridge 171:3a7713b1edbc 303 #define MXC_F_PT_LOOP_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_PT_LOOP_COUNT_POS)) /**< COUNT Mask */
AnnaBridge 171:3a7713b1edbc 304 #define MXC_F_PT_LOOP_DELAY_POS 16 /**< DELAY Position */
AnnaBridge 171:3a7713b1edbc 305 #define MXC_F_PT_LOOP_DELAY ((uint32_t)(0x00000FFFUL << MXC_F_PT_LOOP_DELAY_POS)) /**< DELAY Mask */
AnnaBridge 171:3a7713b1edbc 306 /**@}PT_LOOP_Register*/
AnnaBridge 171:3a7713b1edbc 307 /**
AnnaBridge 171:3a7713b1edbc 308 * @ingroup pulsetrain_registers
AnnaBridge 171:3a7713b1edbc 309 * @defgroup PT_RESTART_Register PT_RESTART
AnnaBridge 171:3a7713b1edbc 310 * @brief Field Positions and Masks
AnnaBridge 171:3a7713b1edbc 311 * @{
AnnaBridge 171:3a7713b1edbc 312 */
AnnaBridge 171:3a7713b1edbc 313 #define MXC_F_PT_RESTART_PT_X_SELECT_POS 0 /**< PT_X_SELECT Position */
AnnaBridge 171:3a7713b1edbc 314 #define MXC_F_PT_RESTART_PT_X_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_X_SELECT_POS)) /**< PT_X_SELECT Mask */
AnnaBridge 171:3a7713b1edbc 315 #define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS 7 /**< ON_PT_X_LOOP_EXIT Position */
AnnaBridge 171:3a7713b1edbc 316 #define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS)) /**< ON_PT_X_LOOP_EXIT Mask */
AnnaBridge 171:3a7713b1edbc 317 #define MXC_F_PT_RESTART_PT_Y_SELECT_POS 8 /**< PT_Y_SELECT Position */
AnnaBridge 171:3a7713b1edbc 318 #define MXC_F_PT_RESTART_PT_Y_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_Y_SELECT_POS)) /**< PT_Y_SELECT Mask */
AnnaBridge 171:3a7713b1edbc 319 #define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS 15 /**< ON_PT_Y_LOOP_EXIT Position */
AnnaBridge 171:3a7713b1edbc 320 #define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS)) /**< ON_PT_Y_LOOP_EXIT Mask */
AnnaBridge 171:3a7713b1edbc 321 /**@} PT_RESTART_Register */
AnnaBridge 171:3a7713b1edbc 322
AnnaBridge 171:3a7713b1edbc 323
AnnaBridge 171:3a7713b1edbc 324 /*
AnnaBridge 171:3a7713b1edbc 325 Field values and shifted values for module PT.
AnnaBridge 171:3a7713b1edbc 326 */
AnnaBridge 171:3a7713b1edbc 327 /**
AnnaBridge 171:3a7713b1edbc 328 * @ingroup PT_RATE_LENGTH_Register
AnnaBridge 171:3a7713b1edbc 329 * @defgroup pt_mode_v_sv Mode Field Values and Shifted Values
AnnaBridge 171:3a7713b1edbc 330 * @brief Mode selection values and shifted values to set the PT_RATE_LENGTH register MODE Field.
AnnaBridge 171:3a7713b1edbc 331 */
AnnaBridge 171:3a7713b1edbc 332 #define MXC_V_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(0x00000000UL)) /**< Value for 32-BIT. */
AnnaBridge 171:3a7713b1edbc 333 #define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x00000001UL)) /**< Value for SQUARE_WAVE. */
AnnaBridge 171:3a7713b1edbc 334 #define MXC_V_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(0x00000002UL)) /**< Value for 2-BIT. */
AnnaBridge 171:3a7713b1edbc 335 #define MXC_V_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(0x00000003UL)) /**< Value for 3-BIT. */
AnnaBridge 171:3a7713b1edbc 336 #define MXC_V_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(0x00000004UL)) /**< Value for 4-BIT. */
AnnaBridge 171:3a7713b1edbc 337 #define MXC_V_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(0x00000005UL)) /**< Value for 5-BIT. */
AnnaBridge 171:3a7713b1edbc 338 #define MXC_V_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(0x00000006UL)) /**< Value for 6-BIT. */
AnnaBridge 171:3a7713b1edbc 339 #define MXC_V_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(0x00000007UL)) /**< Value for 7-BIT. */
AnnaBridge 171:3a7713b1edbc 340 #define MXC_V_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(0x00000008UL)) /**< Value for 8-BIT. */
AnnaBridge 171:3a7713b1edbc 341 #define MXC_V_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(0x00000009UL)) /**< Value for 9-BIT. */
AnnaBridge 171:3a7713b1edbc 342 #define MXC_V_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(0x0000000AUL)) /**< Value for 10-BIT. */
AnnaBridge 171:3a7713b1edbc 343 #define MXC_V_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(0x0000000BUL)) /**< Value for 11-BIT. */
AnnaBridge 171:3a7713b1edbc 344 #define MXC_V_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(0x0000000CUL)) /**< Value for 12-BIT. */
AnnaBridge 171:3a7713b1edbc 345 #define MXC_V_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(0x0000000DUL)) /**< Value for 13-BIT. */
AnnaBridge 171:3a7713b1edbc 346 #define MXC_V_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(0x0000000EUL)) /**< Value for 14-BIT. */
AnnaBridge 171:3a7713b1edbc 347 #define MXC_V_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(0x0000000FUL)) /**< Value for 15-BIT. */
AnnaBridge 171:3a7713b1edbc 348 #define MXC_V_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(0x00000010UL)) /**< Value for 16-BIT. */
AnnaBridge 171:3a7713b1edbc 349 #define MXC_V_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(0x00000011UL)) /**< Value for 17-BIT. */
AnnaBridge 171:3a7713b1edbc 350 #define MXC_V_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(0x00000012UL)) /**< Value for 18-BIT. */
AnnaBridge 171:3a7713b1edbc 351 #define MXC_V_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(0x00000013UL)) /**< Value for 19-BIT. */
AnnaBridge 171:3a7713b1edbc 352 #define MXC_V_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(0x00000014UL)) /**< Value for 20-BIT. */
AnnaBridge 171:3a7713b1edbc 353 #define MXC_V_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(0x00000015UL)) /**< Value for 21-BIT. */
AnnaBridge 171:3a7713b1edbc 354 #define MXC_V_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(0x00000016UL)) /**< Value for 22-BIT. */
AnnaBridge 171:3a7713b1edbc 355 #define MXC_V_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(0x00000017UL)) /**< Value for 23-BIT. */
AnnaBridge 171:3a7713b1edbc 356 #define MXC_V_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(0x00000018UL)) /**< Value for 24-BIT. */
AnnaBridge 171:3a7713b1edbc 357 #define MXC_V_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(0x00000019UL)) /**< Value for 25-BIT. */
AnnaBridge 171:3a7713b1edbc 358 #define MXC_V_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(0x0000001AUL)) /**< Value for 26-BIT. */
AnnaBridge 171:3a7713b1edbc 359 #define MXC_V_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(0x0000001BUL)) /**< Value for 27-BIT. */
AnnaBridge 171:3a7713b1edbc 360 #define MXC_V_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(0x0000001CUL)) /**< Value for 28-BIT. */
AnnaBridge 171:3a7713b1edbc 361 #define MXC_V_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(0x0000001DUL)) /**< Value for 29-BIT. */
AnnaBridge 171:3a7713b1edbc 362 #define MXC_V_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(0x0000001EUL)) /**< Value for 30-BIT. */
AnnaBridge 171:3a7713b1edbc 363 #define MXC_V_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(0x0000001FUL)) /**< Value for 31-BIT. */
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365 #define MXC_S_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 32-BIT. */
AnnaBridge 171:3a7713b1edbc 366 #define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for SQUARE_WAVE. */
AnnaBridge 171:3a7713b1edbc 367 #define MXC_S_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 2-BIT. */
AnnaBridge 171:3a7713b1edbc 368 #define MXC_S_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 3-BIT. */
AnnaBridge 171:3a7713b1edbc 369 #define MXC_S_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 4-BIT. */
AnnaBridge 171:3a7713b1edbc 370 #define MXC_S_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 5-BIT. */
AnnaBridge 171:3a7713b1edbc 371 #define MXC_S_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 6-BIT. */
AnnaBridge 171:3a7713b1edbc 372 #define MXC_S_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 7-BIT. */
AnnaBridge 171:3a7713b1edbc 373 #define MXC_S_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 8-BIT. */
AnnaBridge 171:3a7713b1edbc 374 #define MXC_S_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 9-BIT. */
AnnaBridge 171:3a7713b1edbc 375 #define MXC_S_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 10-BIT. */
AnnaBridge 171:3a7713b1edbc 376 #define MXC_S_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 11-BIT. */
AnnaBridge 171:3a7713b1edbc 377 #define MXC_S_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 12-BIT. */
AnnaBridge 171:3a7713b1edbc 378 #define MXC_S_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 13-BIT. */
AnnaBridge 171:3a7713b1edbc 379 #define MXC_S_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 14-BIT. */
AnnaBridge 171:3a7713b1edbc 380 #define MXC_S_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 15-BIT. */
AnnaBridge 171:3a7713b1edbc 381 #define MXC_S_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 16-BIT. */
AnnaBridge 171:3a7713b1edbc 382 #define MXC_S_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 17-BIT. */
AnnaBridge 171:3a7713b1edbc 383 #define MXC_S_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 18-BIT. */
AnnaBridge 171:3a7713b1edbc 384 #define MXC_S_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 19-BIT. */
AnnaBridge 171:3a7713b1edbc 385 #define MXC_S_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 20-BIT. */
AnnaBridge 171:3a7713b1edbc 386 #define MXC_S_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 21-BIT. */
AnnaBridge 171:3a7713b1edbc 387 #define MXC_S_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 22-BIT. */
AnnaBridge 171:3a7713b1edbc 388 #define MXC_S_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 23-BIT. */
AnnaBridge 171:3a7713b1edbc 389 #define MXC_S_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 24-BIT. */
AnnaBridge 171:3a7713b1edbc 390 #define MXC_S_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 25-BIT. */
AnnaBridge 171:3a7713b1edbc 391 #define MXC_S_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 26-BIT. */
AnnaBridge 171:3a7713b1edbc 392 #define MXC_S_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 27-BIT. */
AnnaBridge 171:3a7713b1edbc 393 #define MXC_S_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 28-BIT. */
AnnaBridge 171:3a7713b1edbc 394 #define MXC_S_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 29-BIT. */
AnnaBridge 171:3a7713b1edbc 395 #define MXC_S_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 30-BIT. */
AnnaBridge 171:3a7713b1edbc 396 #define MXC_S_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 31-BIT. */
AnnaBridge 171:3a7713b1edbc 397 /**@} pt_mode_v_sv*/
AnnaBridge 171:3a7713b1edbc 398
AnnaBridge 171:3a7713b1edbc 399 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 400 }
AnnaBridge 171:3a7713b1edbc 401 #endif
AnnaBridge 171:3a7713b1edbc 402
AnnaBridge 171:3a7713b1edbc 403 #endif /* _MXC_PT_REGS_H_ */
AnnaBridge 171:3a7713b1edbc 404