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TARGET_MAX32630FTHR/TOOLCHAIN_IAR/gpio_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * @file
AnnaBridge 171:3a7713b1edbc 3 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
AnnaBridge 171:3a7713b1edbc 4 */
AnnaBridge 171:3a7713b1edbc 5
AnnaBridge 171:3a7713b1edbc 6 /* ****************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 10 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 11 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 13 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 14 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 17 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 25 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 29 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 32 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 33 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 35 * ownership rights.
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * $Date: 2016-10-10 18:56:06 -0500 (Mon, 10 Oct 2016) $
AnnaBridge 171:3a7713b1edbc 38 * $Revision: 24659 $
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 *************************************************************************** */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /* Define to prevent redundant inclusion */
AnnaBridge 171:3a7713b1edbc 43 #ifndef _MXC_GPIO_REGS_H_
AnnaBridge 171:3a7713b1edbc 44 #define _MXC_GPIO_REGS_H_
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* **** Includes **** */
AnnaBridge 171:3a7713b1edbc 47 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 50 extern "C" {
AnnaBridge 171:3a7713b1edbc 51 #endif
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 ///@cond
AnnaBridge 171:3a7713b1edbc 54 /*
AnnaBridge 171:3a7713b1edbc 55 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 56 */
AnnaBridge 171:3a7713b1edbc 57 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 58 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 59 #endif
AnnaBridge 171:3a7713b1edbc 60 #ifndef __I
AnnaBridge 171:3a7713b1edbc 61 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 62 #endif
AnnaBridge 171:3a7713b1edbc 63 #ifndef __O
AnnaBridge 171:3a7713b1edbc 64 #define __O volatile
AnnaBridge 171:3a7713b1edbc 65 #endif
AnnaBridge 171:3a7713b1edbc 66 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 67 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 68 #endif
AnnaBridge 171:3a7713b1edbc 69 ///@endcond
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /* **** Definitions **** */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /**
AnnaBridge 171:3a7713b1edbc 74 * @ingroup gpio
AnnaBridge 171:3a7713b1edbc 75 * @defgroup gpio_registers Registers
AnnaBridge 171:3a7713b1edbc 76 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
AnnaBridge 171:3a7713b1edbc 77 * @{
AnnaBridge 171:3a7713b1edbc 78 */
AnnaBridge 171:3a7713b1edbc 79
AnnaBridge 171:3a7713b1edbc 80 /*
AnnaBridge 171:3a7713b1edbc 81 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 171:3a7713b1edbc 82 access to each register in module.
AnnaBridge 171:3a7713b1edbc 83 */
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 /**
AnnaBridge 171:3a7713b1edbc 86 * Structure type to access the GPIO Registers
AnnaBridge 171:3a7713b1edbc 87 */
AnnaBridge 171:3a7713b1edbc 88 typedef struct {
AnnaBridge 171:3a7713b1edbc 89 __IO uint32_t rst_mode[16]; /**< <tt>\b 0x0000-0x003C</tt> GPIO_RST_MODE_P[0..15] Registers - Power-On Reset Output Drive Mode */
AnnaBridge 171:3a7713b1edbc 90 __IO uint32_t free[16]; /**< <tt>\b 0x0040-0x007C</tt> GPIO_FREE_P[0..15] Registers - Free for GPIO Operation Flags */
AnnaBridge 171:3a7713b1edbc 91 __IO uint32_t out_mode[16]; /**< <tt>\b 0x0080-0x00BC</tt> GPIO_OUT_MODE_P[0..15] Registers - Output Drive Mode */
AnnaBridge 171:3a7713b1edbc 92 __IO uint32_t out_val[16]; /**< <tt>\b 0x00C0-0x00FC</tt> GPIO_OUT_VAL_P[0..15] Registers - GPIO Output Value */
AnnaBridge 171:3a7713b1edbc 93 __IO uint32_t func_sel[16]; /**< <tt>\b 0x0100-0x013C</tt> GPIO_FUNC_SEL_P[0..15] Registers - GPIO Function Select */
AnnaBridge 171:3a7713b1edbc 94 __IO uint32_t in_mode[16]; /**< <tt>\b 0x0140-0x017C</tt> GPIO_IN_MODE_P[0..15] Registers - GPIO Input Monitoring Mode */
AnnaBridge 171:3a7713b1edbc 95 __IO uint32_t in_val[16]; /**< <tt>\b 0x0180-0x01BC</tt> GPIO_IN_VAL_P[0..15] Registers - GPIO Input Value */
AnnaBridge 171:3a7713b1edbc 96 __IO uint32_t int_mode[16]; /**< <tt>\b 0x01C0-0x01FC</tt> GPIO_INT_MODE_P[0..15] Registers - Interrupt Detection Mode */
AnnaBridge 171:3a7713b1edbc 97 __IO uint32_t intfl[16]; /**< <tt>\b 0x0200-0x023C</tt> GPIO_INTFL_P[0..15] Registers - Interrupt Flags */
AnnaBridge 171:3a7713b1edbc 98 __IO uint32_t inten[16]; /**< <tt>\b 0x0240-0x027C</tt> GPIO_INTEN_P[0..15] Registers - Interrupt Enables */
AnnaBridge 171:3a7713b1edbc 99 } mxc_gpio_regs_t;
AnnaBridge 171:3a7713b1edbc 100 /**@} end of gpio_registers group */
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 /*
AnnaBridge 171:3a7713b1edbc 103 Register offsets for module GPIO.
AnnaBridge 171:3a7713b1edbc 104 */
AnnaBridge 171:3a7713b1edbc 105 /**
AnnaBridge 171:3a7713b1edbc 106 * @ingroup gpio_registers
AnnaBridge 171:3a7713b1edbc 107 * @defgroup GPIO_Register_Offsets Register Offsets
AnnaBridge 171:3a7713b1edbc 108 * @brief GPIO Register Offsets from the GPIO Base Address.
AnnaBridge 171:3a7713b1edbc 109 * @{
AnnaBridge 171:3a7713b1edbc 110 */
AnnaBridge 171:3a7713b1edbc 111 /**
AnnaBridge 171:3a7713b1edbc 112 * @ingroup GPIO_Register_Offsets
AnnaBridge 171:3a7713b1edbc 113 * @defgroup gpio_rst_mode_offsets Registers GPIO_RST_MODE_P[0..15] Offsets
AnnaBridge 171:3a7713b1edbc 114 * @brief GPIO_RST_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 115 * @{
AnnaBridge 171:3a7713b1edbc 116 */
AnnaBridge 171:3a7713b1edbc 117 #define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt>\b 0x0000</tt> */
AnnaBridge 171:3a7713b1edbc 118 #define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt>\b 0x0004</tt> */
AnnaBridge 171:3a7713b1edbc 119 #define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt>\b 0x0008</tt> */
AnnaBridge 171:3a7713b1edbc 120 #define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt>\b 0x000C</tt> */
AnnaBridge 171:3a7713b1edbc 121 #define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt>\b 0x0010</tt> */
AnnaBridge 171:3a7713b1edbc 122 #define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt>\b 0x0014</tt> */
AnnaBridge 171:3a7713b1edbc 123 #define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt>\b 0x0018</tt> */
AnnaBridge 171:3a7713b1edbc 124 #define MXC_R_GPIO_OFFS_RST_MODE_P7 ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt>\b 0x001C</tt> */
AnnaBridge 171:3a7713b1edbc 125 #define MXC_R_GPIO_OFFS_RST_MODE_P8 ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt>\b 0x0020</tt> */
AnnaBridge 171:3a7713b1edbc 126 #define MXC_R_GPIO_OFFS_RST_MODE_P9 ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt>\b 0x0024</tt> */
AnnaBridge 171:3a7713b1edbc 127 #define MXC_R_GPIO_OFFS_RST_MODE_P10 ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt>\b 0x0028</tt> */
AnnaBridge 171:3a7713b1edbc 128 #define MXC_R_GPIO_OFFS_RST_MODE_P11 ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt>\b 0x002C</tt> */
AnnaBridge 171:3a7713b1edbc 129 #define MXC_R_GPIO_OFFS_RST_MODE_P12 ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt>\b 0x0030</tt> */
AnnaBridge 171:3a7713b1edbc 130 #define MXC_R_GPIO_OFFS_RST_MODE_P13 ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt>\b 0x0034</tt> */
AnnaBridge 171:3a7713b1edbc 131 #define MXC_R_GPIO_OFFS_RST_MODE_P14 ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt>\b 0x0038</tt> */
AnnaBridge 171:3a7713b1edbc 132 #define MXC_R_GPIO_OFFS_RST_MODE_P15 ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt>\b 0x003C</tt> */
AnnaBridge 171:3a7713b1edbc 133 /**@} end of gpio_rst_mode group */
AnnaBridge 171:3a7713b1edbc 134 /**
AnnaBridge 171:3a7713b1edbc 135 * @ingroup GPIO_Register_Offsets
AnnaBridge 171:3a7713b1edbc 136 * @defgroup gpio_free_offsets Registers GPIO_FREE_P[0..15] Offsets
AnnaBridge 171:3a7713b1edbc 137 * @brief GPIO_FREE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 138 * @{
AnnaBridge 171:3a7713b1edbc 139 */
AnnaBridge 171:3a7713b1edbc 140 #define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt>\b 0x0040</tt> */
AnnaBridge 171:3a7713b1edbc 141 #define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) /**< Offset from GPIO Base Address: <tt>\b 0x0044</tt> */
AnnaBridge 171:3a7713b1edbc 142 #define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt>\b 0x0048</tt> */
AnnaBridge 171:3a7713b1edbc 143 #define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt>\b 0x004C</tt> */
AnnaBridge 171:3a7713b1edbc 144 #define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt>\b 0x0050</tt> */
AnnaBridge 171:3a7713b1edbc 145 #define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt>\b 0x0054</tt> */
AnnaBridge 171:3a7713b1edbc 146 #define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) /**< Offset from GPIO Base Address: <tt>\b 0x0058</tt> */
AnnaBridge 171:3a7713b1edbc 147 #define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt>\b 0x005C</tt> */
AnnaBridge 171:3a7713b1edbc 148 #define MXC_R_GPIO_OFFS_FREE_P8 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt>\b 0x0060</tt> */
AnnaBridge 171:3a7713b1edbc 149 #define MXC_R_GPIO_OFFS_FREE_P9 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt>\b 0x0064</tt> */
AnnaBridge 171:3a7713b1edbc 150 #define MXC_R_GPIO_OFFS_FREE_P10 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt>\b 0x0068</tt> */
AnnaBridge 171:3a7713b1edbc 151 #define MXC_R_GPIO_OFFS_FREE_P11 ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt>\b 0x006C</tt> */
AnnaBridge 171:3a7713b1edbc 152 #define MXC_R_GPIO_OFFS_FREE_P12 ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt>\b 0x0070</tt> */
AnnaBridge 171:3a7713b1edbc 153 #define MXC_R_GPIO_OFFS_FREE_P13 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt>\b 0x0074</tt> */
AnnaBridge 171:3a7713b1edbc 154 #define MXC_R_GPIO_OFFS_FREE_P14 ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt>\b 0x0078</tt> */
AnnaBridge 171:3a7713b1edbc 155 #define MXC_R_GPIO_OFFS_FREE_P15 ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt>\b 0x007C</tt> */
AnnaBridge 171:3a7713b1edbc 156 /**@} end of gpio_free group */
AnnaBridge 171:3a7713b1edbc 157 /**
AnnaBridge 171:3a7713b1edbc 158 * @ingroup GPIO_Register_Offsets
AnnaBridge 171:3a7713b1edbc 159 * @defgroup gpio_out_mode_offsets GPIO_OUT_MODE_P[0..15] Registers
AnnaBridge 171:3a7713b1edbc 160 * @brief GPIO_OUT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 161 * @{
AnnaBridge 171:3a7713b1edbc 162 */
AnnaBridge 171:3a7713b1edbc 163 #define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) /**< Offset from GPIO Base Address: <tt>\b 0x0080</tt> */
AnnaBridge 171:3a7713b1edbc 164 #define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) /**< Offset from GPIO Base Address: <tt>\b 0x0084</tt> */
AnnaBridge 171:3a7713b1edbc 165 #define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) /**< Offset from GPIO Base Address: <tt>\b 0x0088</tt> */
AnnaBridge 171:3a7713b1edbc 166 #define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) /**< Offset from GPIO Base Address: <tt>\b 0x008C</tt> */
AnnaBridge 171:3a7713b1edbc 167 #define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) /**< Offset from GPIO Base Address: <tt>\b 0x0090</tt> */
AnnaBridge 171:3a7713b1edbc 168 #define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) /**< Offset from GPIO Base Address: <tt>\b 0x0094</tt> */
AnnaBridge 171:3a7713b1edbc 169 #define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) /**< Offset from GPIO Base Address: <tt>\b 0x0098</tt> */
AnnaBridge 171:3a7713b1edbc 170 #define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL) /**< Offset from GPIO Base Address: <tt>\b 0x009C</tt> */
AnnaBridge 171:3a7713b1edbc 171 #define MXC_R_GPIO_OFFS_OUT_MODE_P8 ((uint32_t)0x000000A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A0</tt> */
AnnaBridge 171:3a7713b1edbc 172 #define MXC_R_GPIO_OFFS_OUT_MODE_P9 ((uint32_t)0x000000A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A4</tt> */
AnnaBridge 171:3a7713b1edbc 173 #define MXC_R_GPIO_OFFS_OUT_MODE_P10 ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A8</tt> */
AnnaBridge 171:3a7713b1edbc 174 #define MXC_R_GPIO_OFFS_OUT_MODE_P11 ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x00AC</tt> */
AnnaBridge 171:3a7713b1edbc 175 #define MXC_R_GPIO_OFFS_OUT_MODE_P12 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B0</tt> */
AnnaBridge 171:3a7713b1edbc 176 #define MXC_R_GPIO_OFFS_OUT_MODE_P13 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B4</tt> */
AnnaBridge 171:3a7713b1edbc 177 #define MXC_R_GPIO_OFFS_OUT_MODE_P14 ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B8</tt> */
AnnaBridge 171:3a7713b1edbc 178 #define MXC_R_GPIO_OFFS_OUT_MODE_P15 ((uint32_t)0x000000BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00BC</tt> */
AnnaBridge 171:3a7713b1edbc 179 /**@} end of gpio_out_mode group */
AnnaBridge 171:3a7713b1edbc 180 /**
AnnaBridge 171:3a7713b1edbc 181 * @ingroup GPIO_Register_Offsets
AnnaBridge 171:3a7713b1edbc 182 * @defgroup gpio_out_val_offsets GPIO_OUT_VAL_P[0..15] Registers
AnnaBridge 171:3a7713b1edbc 183 * @brief GPIO_OUT_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 184 * @{
AnnaBridge 171:3a7713b1edbc 185 */
AnnaBridge 171:3a7713b1edbc 186 #define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C0</tt> */
AnnaBridge 171:3a7713b1edbc 187 #define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C4</tt> */
AnnaBridge 171:3a7713b1edbc 188 #define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C8</tt> */
AnnaBridge 171:3a7713b1edbc 189 #define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00CC</tt> */
AnnaBridge 171:3a7713b1edbc 190 #define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D0</tt> */
AnnaBridge 171:3a7713b1edbc 191 #define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D4</tt> */
AnnaBridge 171:3a7713b1edbc 192 #define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D8</tt> */
AnnaBridge 171:3a7713b1edbc 193 #define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00DC</tt> */
AnnaBridge 171:3a7713b1edbc 194 #define MXC_R_GPIO_OFFS_OUT_VAL_P8 ((uint32_t)0x000000E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E0</tt> */
AnnaBridge 171:3a7713b1edbc 195 #define MXC_R_GPIO_OFFS_OUT_VAL_P9 ((uint32_t)0x000000E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E4</tt> */
AnnaBridge 171:3a7713b1edbc 196 #define MXC_R_GPIO_OFFS_OUT_VAL_P10 ((uint32_t)0x000000E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E8</tt> */
AnnaBridge 171:3a7713b1edbc 197 #define MXC_R_GPIO_OFFS_OUT_VAL_P11 ((uint32_t)0x000000ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x00EC</tt> */
AnnaBridge 171:3a7713b1edbc 198 #define MXC_R_GPIO_OFFS_OUT_VAL_P12 ((uint32_t)0x000000F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F0</tt> */
AnnaBridge 171:3a7713b1edbc 199 #define MXC_R_GPIO_OFFS_OUT_VAL_P13 ((uint32_t)0x000000F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F4</tt> */
AnnaBridge 171:3a7713b1edbc 200 #define MXC_R_GPIO_OFFS_OUT_VAL_P14 ((uint32_t)0x000000F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F8</tt> */
AnnaBridge 171:3a7713b1edbc 201 #define MXC_R_GPIO_OFFS_OUT_VAL_P15 ((uint32_t)0x000000FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00FC</tt> */
AnnaBridge 171:3a7713b1edbc 202 /**@} end of gpio_out_val group */
AnnaBridge 171:3a7713b1edbc 203 /**
AnnaBridge 171:3a7713b1edbc 204 * @ingroup GPIO_Register_Offsets
AnnaBridge 171:3a7713b1edbc 205 * @defgroup gpio_func_sel_offsets GPIO_FUNC_SEL_P[0..15] Registers
AnnaBridge 171:3a7713b1edbc 206 * @brief GPIO_FUNC_SEL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 207 * @{
AnnaBridge 171:3a7713b1edbc 208 */
AnnaBridge 171:3a7713b1edbc 209 #define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) /**< Offset from GPIO Base Address: <tt>\b 0x0100</tt> */
AnnaBridge 171:3a7713b1edbc 210 #define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) /**< Offset from GPIO Base Address: <tt>\b 0x0104</tt> */
AnnaBridge 171:3a7713b1edbc 211 #define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) /**< Offset from GPIO Base Address: <tt>\b 0x0108</tt> */
AnnaBridge 171:3a7713b1edbc 212 #define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL) /**< Offset from GPIO Base Address: <tt>\b 0x010C</tt> */
AnnaBridge 171:3a7713b1edbc 213 #define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL) /**< Offset from GPIO Base Address: <tt>\b 0x0110</tt> */
AnnaBridge 171:3a7713b1edbc 214 #define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL) /**< Offset from GPIO Base Address: <tt>\b 0x0114</tt> */
AnnaBridge 171:3a7713b1edbc 215 #define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) /**< Offset from GPIO Base Address: <tt>\b 0x0118</tt> */
AnnaBridge 171:3a7713b1edbc 216 #define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL) /**< Offset from GPIO Base Address: <tt>\b 0x011C</tt> */
AnnaBridge 171:3a7713b1edbc 217 #define MXC_R_GPIO_OFFS_FUNC_SEL_P8 ((uint32_t)0x00000120UL) /**< Offset from GPIO Base Address: <tt>\b 0x0120</tt> */
AnnaBridge 171:3a7713b1edbc 218 #define MXC_R_GPIO_OFFS_FUNC_SEL_P9 ((uint32_t)0x00000124UL) /**< Offset from GPIO Base Address: <tt>\b 0x0124</tt> */
AnnaBridge 171:3a7713b1edbc 219 #define MXC_R_GPIO_OFFS_FUNC_SEL_P10 ((uint32_t)0x00000128UL) /**< Offset from GPIO Base Address: <tt>\b 0x0128</tt> */
AnnaBridge 171:3a7713b1edbc 220 #define MXC_R_GPIO_OFFS_FUNC_SEL_P11 ((uint32_t)0x0000012CUL) /**< Offset from GPIO Base Address: <tt>\b 0x012C</tt> */
AnnaBridge 171:3a7713b1edbc 221 #define MXC_R_GPIO_OFFS_FUNC_SEL_P12 ((uint32_t)0x00000130UL) /**< Offset from GPIO Base Address: <tt>\b 0x0130</tt> */
AnnaBridge 171:3a7713b1edbc 222 #define MXC_R_GPIO_OFFS_FUNC_SEL_P13 ((uint32_t)0x00000134UL) /**< Offset from GPIO Base Address: <tt>\b 0x0134</tt> */
AnnaBridge 171:3a7713b1edbc 223 #define MXC_R_GPIO_OFFS_FUNC_SEL_P14 ((uint32_t)0x00000138UL) /**< Offset from GPIO Base Address: <tt>\b 0x0138</tt> */
AnnaBridge 171:3a7713b1edbc 224 #define MXC_R_GPIO_OFFS_FUNC_SEL_P15 ((uint32_t)0x0000013CUL) /**< Offset from GPIO Base Address: <tt>\b 0x013C</tt> */
AnnaBridge 171:3a7713b1edbc 225 /**@} end of gpio_func_sel */
AnnaBridge 171:3a7713b1edbc 226 /**
AnnaBridge 171:3a7713b1edbc 227 * @ingroup GPIO_Register_Offsets
AnnaBridge 171:3a7713b1edbc 228 * @defgroup gpio_in_mode_offsets GPIO_IN_MODE_P[0..15] Registers
AnnaBridge 171:3a7713b1edbc 229 * @brief GPIO_IN_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 230 * @{
AnnaBridge 171:3a7713b1edbc 231 */
AnnaBridge 171:3a7713b1edbc 232 #define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) /**< Offset from GPIO Base Address: <tt>\b 0x0140</tt> */
AnnaBridge 171:3a7713b1edbc 233 #define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) /**< Offset from GPIO Base Address: <tt>\b 0x0144</tt> */
AnnaBridge 171:3a7713b1edbc 234 #define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) /**< Offset from GPIO Base Address: <tt>\b 0x0148</tt> */
AnnaBridge 171:3a7713b1edbc 235 #define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) /**< Offset from GPIO Base Address: <tt>\b 0x014C</tt> */
AnnaBridge 171:3a7713b1edbc 236 #define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) /**< Offset from GPIO Base Address: <tt>\b 0x0150</tt> */
AnnaBridge 171:3a7713b1edbc 237 #define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) /**< Offset from GPIO Base Address: <tt>\b 0x0154</tt> */
AnnaBridge 171:3a7713b1edbc 238 #define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) /**< Offset from GPIO Base Address: <tt>\b 0x0158</tt> */
AnnaBridge 171:3a7713b1edbc 239 #define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL) /**< Offset from GPIO Base Address: <tt>\b 0x015C</tt> */
AnnaBridge 171:3a7713b1edbc 240 #define MXC_R_GPIO_OFFS_IN_MODE_P8 ((uint32_t)0x00000160UL) /**< Offset from GPIO Base Address: <tt>\b 0x0160</tt> */
AnnaBridge 171:3a7713b1edbc 241 #define MXC_R_GPIO_OFFS_IN_MODE_P9 ((uint32_t)0x00000164UL) /**< Offset from GPIO Base Address: <tt>\b 0x0164</tt> */
AnnaBridge 171:3a7713b1edbc 242 #define MXC_R_GPIO_OFFS_IN_MODE_P10 ((uint32_t)0x00000168UL) /**< Offset from GPIO Base Address: <tt>\b 0x0168</tt> */
AnnaBridge 171:3a7713b1edbc 243 #define MXC_R_GPIO_OFFS_IN_MODE_P11 ((uint32_t)0x0000016CUL) /**< Offset from GPIO Base Address: <tt>\b 0x016C</tt> */
AnnaBridge 171:3a7713b1edbc 244 #define MXC_R_GPIO_OFFS_IN_MODE_P12 ((uint32_t)0x00000170UL) /**< Offset from GPIO Base Address: <tt>\b 0x0170</tt> */
AnnaBridge 171:3a7713b1edbc 245 #define MXC_R_GPIO_OFFS_IN_MODE_P13 ((uint32_t)0x00000174UL) /**< Offset from GPIO Base Address: <tt>\b 0x0174</tt> */
AnnaBridge 171:3a7713b1edbc 246 #define MXC_R_GPIO_OFFS_IN_MODE_P14 ((uint32_t)0x00000178UL) /**< Offset from GPIO Base Address: <tt>\b 0x0178</tt> */
AnnaBridge 171:3a7713b1edbc 247 #define MXC_R_GPIO_OFFS_IN_MODE_P15 ((uint32_t)0x0000017CUL) /**< Offset from GPIO Base Address: <tt>\b 0x017C</tt> */
AnnaBridge 171:3a7713b1edbc 248 /**@} end of gpio_in_mode group */
AnnaBridge 171:3a7713b1edbc 249 /**
AnnaBridge 171:3a7713b1edbc 250 * @ingroup GPIO_Register_Offsets
AnnaBridge 171:3a7713b1edbc 251 * @defgroup gpio_in_val_offsets GPIO_IN_VAL_P[0..15] Registers
AnnaBridge 171:3a7713b1edbc 252 * @brief GPIO_IN_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 253 * @{
AnnaBridge 171:3a7713b1edbc 254 */
AnnaBridge 171:3a7713b1edbc 255 #define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) /**< Offset from GPIO Base Address: <tt>\b 0x0180</tt> */
AnnaBridge 171:3a7713b1edbc 256 #define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) /**< Offset from GPIO Base Address: <tt>\b 0x0184</tt> */
AnnaBridge 171:3a7713b1edbc 257 #define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) /**< Offset from GPIO Base Address: <tt>\b 0x0188</tt> */
AnnaBridge 171:3a7713b1edbc 258 #define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) /**< Offset from GPIO Base Address: <tt>\b 0x018C</tt> */
AnnaBridge 171:3a7713b1edbc 259 #define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) /**< Offset from GPIO Base Address: <tt>\b 0x0190</tt> */
AnnaBridge 171:3a7713b1edbc 260 #define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) /**< Offset from GPIO Base Address: <tt>\b 0x0194</tt> */
AnnaBridge 171:3a7713b1edbc 261 #define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) /**< Offset from GPIO Base Address: <tt>\b 0x0198</tt> */
AnnaBridge 171:3a7713b1edbc 262 #define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL) /**< Offset from GPIO Base Address: <tt>\b 0x019C</tt> */
AnnaBridge 171:3a7713b1edbc 263 #define MXC_R_GPIO_OFFS_IN_VAL_P8 ((uint32_t)0x000001A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A0</tt> */
AnnaBridge 171:3a7713b1edbc 264 #define MXC_R_GPIO_OFFS_IN_VAL_P9 ((uint32_t)0x000001A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A4</tt> */
AnnaBridge 171:3a7713b1edbc 265 #define MXC_R_GPIO_OFFS_IN_VAL_P10 ((uint32_t)0x000001A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A8</tt> */
AnnaBridge 171:3a7713b1edbc 266 #define MXC_R_GPIO_OFFS_IN_VAL_P11 ((uint32_t)0x000001ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x01AC</tt> */
AnnaBridge 171:3a7713b1edbc 267 #define MXC_R_GPIO_OFFS_IN_VAL_P12 ((uint32_t)0x000001B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B0</tt> */
AnnaBridge 171:3a7713b1edbc 268 #define MXC_R_GPIO_OFFS_IN_VAL_P13 ((uint32_t)0x000001B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B4</tt> */
AnnaBridge 171:3a7713b1edbc 269 #define MXC_R_GPIO_OFFS_IN_VAL_P14 ((uint32_t)0x000001B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B8</tt> */
AnnaBridge 171:3a7713b1edbc 270 #define MXC_R_GPIO_OFFS_IN_VAL_P15 ((uint32_t)0x000001BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01BC</tt> */
AnnaBridge 171:3a7713b1edbc 271 /**@} end of gpio_in_val group */
AnnaBridge 171:3a7713b1edbc 272 /**
AnnaBridge 171:3a7713b1edbc 273 * @ingroup GPIO_Register_Offsets
AnnaBridge 171:3a7713b1edbc 274 * @defgroup gpio_int_mode_offsets GPIO_INT_MODE_P[0..15] Registers
AnnaBridge 171:3a7713b1edbc 275 * @brief GPIO_INT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 276 * @{
AnnaBridge 171:3a7713b1edbc 277 */
AnnaBridge 171:3a7713b1edbc 278 #define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C0</tt> */
AnnaBridge 171:3a7713b1edbc 279 #define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C4</tt> */
AnnaBridge 171:3a7713b1edbc 280 #define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C8</tt> */
AnnaBridge 171:3a7713b1edbc 281 #define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01CC</tt> */
AnnaBridge 171:3a7713b1edbc 282 #define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D0</tt> */
AnnaBridge 171:3a7713b1edbc 283 #define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D4</tt> */
AnnaBridge 171:3a7713b1edbc 284 #define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D8</tt> */
AnnaBridge 171:3a7713b1edbc 285 #define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01DC</tt> */
AnnaBridge 171:3a7713b1edbc 286 #define MXC_R_GPIO_OFFS_INT_MODE_P8 ((uint32_t)0x000001E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E0</tt> */
AnnaBridge 171:3a7713b1edbc 287 #define MXC_R_GPIO_OFFS_INT_MODE_P9 ((uint32_t)0x000001E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E4</tt> */
AnnaBridge 171:3a7713b1edbc 288 #define MXC_R_GPIO_OFFS_INT_MODE_P10 ((uint32_t)0x000001E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E8</tt> */
AnnaBridge 171:3a7713b1edbc 289 #define MXC_R_GPIO_OFFS_INT_MODE_P11 ((uint32_t)0x000001ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x01EC</tt> */
AnnaBridge 171:3a7713b1edbc 290 #define MXC_R_GPIO_OFFS_INT_MODE_P12 ((uint32_t)0x000001F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F0</tt> */
AnnaBridge 171:3a7713b1edbc 291 #define MXC_R_GPIO_OFFS_INT_MODE_P13 ((uint32_t)0x000001F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F4</tt> */
AnnaBridge 171:3a7713b1edbc 292 #define MXC_R_GPIO_OFFS_INT_MODE_P14 ((uint32_t)0x000001F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F8</tt> */
AnnaBridge 171:3a7713b1edbc 293 #define MXC_R_GPIO_OFFS_INT_MODE_P15 ((uint32_t)0x000001FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01FC</tt> */
AnnaBridge 171:3a7713b1edbc 294 /**@} end of gpio_int_mode group */
AnnaBridge 171:3a7713b1edbc 295 /**
AnnaBridge 171:3a7713b1edbc 296 * @ingroup GPIO_Register_Offsets
AnnaBridge 171:3a7713b1edbc 297 * @defgroup gpio_int_flag_offsets GPIO_INTFL_P[0..15] Registers
AnnaBridge 171:3a7713b1edbc 298 * @brief GPIO_INTFL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 299 * @{
AnnaBridge 171:3a7713b1edbc 300 */
AnnaBridge 171:3a7713b1edbc 301 #define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) /**< Offset from GPIO Base Address: <tt>\b 0x0200</tt> */
AnnaBridge 171:3a7713b1edbc 302 #define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) /**< Offset from GPIO Base Address: <tt>\b 0x0204</tt> */
AnnaBridge 171:3a7713b1edbc 303 #define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) /**< Offset from GPIO Base Address: <tt>\b 0x0208</tt> */
AnnaBridge 171:3a7713b1edbc 304 #define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) /**< Offset from GPIO Base Address: <tt>\b 0x020C</tt> */
AnnaBridge 171:3a7713b1edbc 305 #define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) /**< Offset from GPIO Base Address: <tt>\b 0x0210</tt> */
AnnaBridge 171:3a7713b1edbc 306 #define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) /**< Offset from GPIO Base Address: <tt>\b 0x0214</tt> */
AnnaBridge 171:3a7713b1edbc 307 #define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) /**< Offset from GPIO Base Address: <tt>\b 0x0218</tt> */
AnnaBridge 171:3a7713b1edbc 308 #define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL) /**< Offset from GPIO Base Address: <tt>\b 0x021C</tt> */
AnnaBridge 171:3a7713b1edbc 309 #define MXC_R_GPIO_OFFS_INTFL_P8 ((uint32_t)0x00000220UL) /**< Offset from GPIO Base Address: <tt>\b 0x0220</tt> */
AnnaBridge 171:3a7713b1edbc 310 #define MXC_R_GPIO_OFFS_INTFL_P9 ((uint32_t)0x00000224UL) /**< Offset from GPIO Base Address: <tt>\b 0x0224</tt> */
AnnaBridge 171:3a7713b1edbc 311 #define MXC_R_GPIO_OFFS_INTFL_P10 ((uint32_t)0x00000228UL) /**< Offset from GPIO Base Address: <tt>\b 0x0228</tt> */
AnnaBridge 171:3a7713b1edbc 312 #define MXC_R_GPIO_OFFS_INTFL_P11 ((uint32_t)0x0000022CUL) /**< Offset from GPIO Base Address: <tt>\b 0x022C</tt> */
AnnaBridge 171:3a7713b1edbc 313 #define MXC_R_GPIO_OFFS_INTFL_P12 ((uint32_t)0x00000230UL) /**< Offset from GPIO Base Address: <tt>\b 0x0230</tt> */
AnnaBridge 171:3a7713b1edbc 314 #define MXC_R_GPIO_OFFS_INTFL_P13 ((uint32_t)0x00000234UL) /**< Offset from GPIO Base Address: <tt>\b 0x0234</tt> */
AnnaBridge 171:3a7713b1edbc 315 #define MXC_R_GPIO_OFFS_INTFL_P14 ((uint32_t)0x00000238UL) /**< Offset from GPIO Base Address: <tt>\b 0x0238</tt> */
AnnaBridge 171:3a7713b1edbc 316 #define MXC_R_GPIO_OFFS_INTFL_P15 ((uint32_t)0x0000023CUL) /**< Offset from GPIO Base Address: <tt>\b 0x023C</tt> */
AnnaBridge 171:3a7713b1edbc 317 /**@} end of gpio_int_flag group */
AnnaBridge 171:3a7713b1edbc 318 /**
AnnaBridge 171:3a7713b1edbc 319 * @ingroup GPIO_Register_Offsets
AnnaBridge 171:3a7713b1edbc 320 * @defgroup gpio_int_enable_offsets GPIO_INTEN_P[0..15] Registers
AnnaBridge 171:3a7713b1edbc 321 * @brief GPIO_INTEN_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 322 * @{
AnnaBridge 171:3a7713b1edbc 323 */
AnnaBridge 171:3a7713b1edbc 324 #define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) /**< Offset from GPIO Base Address: <tt>\b 0x0240</tt> */
AnnaBridge 171:3a7713b1edbc 325 #define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) /**< Offset from GPIO Base Address: <tt>\b 0x0244</tt> */
AnnaBridge 171:3a7713b1edbc 326 #define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) /**< Offset from GPIO Base Address: <tt>\b 0x0248</tt> */
AnnaBridge 171:3a7713b1edbc 327 #define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) /**< Offset from GPIO Base Address: <tt>\b 0x024C</tt> */
AnnaBridge 171:3a7713b1edbc 328 #define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) /**< Offset from GPIO Base Address: <tt>\b 0x0250</tt> */
AnnaBridge 171:3a7713b1edbc 329 #define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) /**< Offset from GPIO Base Address: <tt>\b 0x0254</tt> */
AnnaBridge 171:3a7713b1edbc 330 #define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) /**< Offset from GPIO Base Address: <tt>\b 0x0258</tt> */
AnnaBridge 171:3a7713b1edbc 331 #define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL) /**< Offset from GPIO Base Address: <tt>\b 0x025C</tt> */
AnnaBridge 171:3a7713b1edbc 332 #define MXC_R_GPIO_OFFS_INTEN_P8 ((uint32_t)0x00000260UL) /**< Offset from GPIO Base Address: <tt>\b 0x0260</tt> */
AnnaBridge 171:3a7713b1edbc 333 #define MXC_R_GPIO_OFFS_INTEN_P9 ((uint32_t)0x00000264UL) /**< Offset from GPIO Base Address: <tt>\b 0x0264</tt> */
AnnaBridge 171:3a7713b1edbc 334 #define MXC_R_GPIO_OFFS_INTEN_P10 ((uint32_t)0x00000268UL) /**< Offset from GPIO Base Address: <tt>\b 0x0268</tt> */
AnnaBridge 171:3a7713b1edbc 335 #define MXC_R_GPIO_OFFS_INTEN_P11 ((uint32_t)0x0000026CUL) /**< Offset from GPIO Base Address: <tt>\b 0x026C</tt> */
AnnaBridge 171:3a7713b1edbc 336 #define MXC_R_GPIO_OFFS_INTEN_P12 ((uint32_t)0x00000270UL) /**< Offset from GPIO Base Address: <tt>\b 0x0270</tt> */
AnnaBridge 171:3a7713b1edbc 337 #define MXC_R_GPIO_OFFS_INTEN_P13 ((uint32_t)0x00000274UL) /**< Offset from GPIO Base Address: <tt>\b 0x0274</tt> */
AnnaBridge 171:3a7713b1edbc 338 #define MXC_R_GPIO_OFFS_INTEN_P14 ((uint32_t)0x00000278UL) /**< Offset from GPIO Base Address: <tt>\b 0x0278</tt> */
AnnaBridge 171:3a7713b1edbc 339 #define MXC_R_GPIO_OFFS_INTEN_P15 ((uint32_t)0x0000027CUL) /**< Offset from GPIO Base Address: <tt>\b 0x027C</tt> */
AnnaBridge 171:3a7713b1edbc 340 /**@}*/
AnnaBridge 171:3a7713b1edbc 341 /**@} end of GPIO_Register_Offsets */
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 /*
AnnaBridge 171:3a7713b1edbc 344 Field positions and masks for module GPIO.
AnnaBridge 171:3a7713b1edbc 345 */
AnnaBridge 171:3a7713b1edbc 346 /**
AnnaBridge 171:3a7713b1edbc 347 * @ingroup gpio_registers
AnnaBridge 171:3a7713b1edbc 348 * @defgroup GPIO_RST_MODE_Register GPIO_RST_MODE
AnnaBridge 171:3a7713b1edbc 349 * @brief Field Positions and Bit Masks for the GPIO_RST_MODE register.
AnnaBridge 171:3a7713b1edbc 350 * @{
AnnaBridge 171:3a7713b1edbc 351 */
AnnaBridge 171:3a7713b1edbc 352 #define MXC_F_GPIO_RST_MODE_PIN0_POS 0 /**< PIN0 Position */
AnnaBridge 171:3a7713b1edbc 353 #define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS)) /**< PIN0 Mask */
AnnaBridge 171:3a7713b1edbc 354 #define MXC_F_GPIO_RST_MODE_PIN1_POS 4 /**< PIN1 Position */
AnnaBridge 171:3a7713b1edbc 355 #define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS)) /**< PIN1 Mask */
AnnaBridge 171:3a7713b1edbc 356 #define MXC_F_GPIO_RST_MODE_PIN2_POS 8 /**< PIN2 Position */
AnnaBridge 171:3a7713b1edbc 357 #define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS)) /**< PIN2 Mask */
AnnaBridge 171:3a7713b1edbc 358 #define MXC_F_GPIO_RST_MODE_PIN3_POS 12 /**< PIN3 Position */
AnnaBridge 171:3a7713b1edbc 359 #define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS)) /**< PIN3 Mask */
AnnaBridge 171:3a7713b1edbc 360 #define MXC_F_GPIO_RST_MODE_PIN4_POS 16 /**< PIN4 Position */
AnnaBridge 171:3a7713b1edbc 361 #define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS)) /**< PIN4 Mask */
AnnaBridge 171:3a7713b1edbc 362 #define MXC_F_GPIO_RST_MODE_PIN5_POS 20 /**< PIN5 Position */
AnnaBridge 171:3a7713b1edbc 363 #define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS)) /**< PIN5 Mask */
AnnaBridge 171:3a7713b1edbc 364 #define MXC_F_GPIO_RST_MODE_PIN6_POS 24 /**< PIN6 Position */
AnnaBridge 171:3a7713b1edbc 365 #define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS)) /**< PIN6 Mask */
AnnaBridge 171:3a7713b1edbc 366 #define MXC_F_GPIO_RST_MODE_PIN7_POS 28 /**< PIN7 Position */
AnnaBridge 171:3a7713b1edbc 367 #define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS)) /**< PIN7 Mask */
AnnaBridge 171:3a7713b1edbc 368 /**@} end of group GPIO_FREE */
AnnaBridge 171:3a7713b1edbc 369 /**
AnnaBridge 171:3a7713b1edbc 370 * @ingroup gpio_registers
AnnaBridge 171:3a7713b1edbc 371 * @defgroup GPIO_FREE_Register GPIO_FREE
AnnaBridge 171:3a7713b1edbc 372 * @brief Field Positions and Bit Masks for the GPIO_FREE register.
AnnaBridge 171:3a7713b1edbc 373 * @{
AnnaBridge 171:3a7713b1edbc 374 */
AnnaBridge 171:3a7713b1edbc 375 #define MXC_F_GPIO_FREE_PIN0_POS 0 /**< PIN0 Position */
AnnaBridge 171:3a7713b1edbc 376 #define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) /**< PIN0 Mask */
AnnaBridge 171:3a7713b1edbc 377 #define MXC_F_GPIO_FREE_PIN1_POS 1 /**< PIN1 Position */
AnnaBridge 171:3a7713b1edbc 378 #define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) /**< PIN1 Mask */
AnnaBridge 171:3a7713b1edbc 379 #define MXC_F_GPIO_FREE_PIN2_POS 2 /**< PIN2 Position */
AnnaBridge 171:3a7713b1edbc 380 #define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) /**< PIN2 Mask */
AnnaBridge 171:3a7713b1edbc 381 #define MXC_F_GPIO_FREE_PIN3_POS 3 /**< PIN3 Position */
AnnaBridge 171:3a7713b1edbc 382 #define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) /**< PIN3 Mask */
AnnaBridge 171:3a7713b1edbc 383 #define MXC_F_GPIO_FREE_PIN4_POS 4 /**< PIN4 Position */
AnnaBridge 171:3a7713b1edbc 384 #define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) /**< PIN4 Mask */
AnnaBridge 171:3a7713b1edbc 385 #define MXC_F_GPIO_FREE_PIN5_POS 5 /**< PIN5 Position */
AnnaBridge 171:3a7713b1edbc 386 #define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) /**< PIN5 Mask */
AnnaBridge 171:3a7713b1edbc 387 #define MXC_F_GPIO_FREE_PIN6_POS 6 /**< PIN6 Position */
AnnaBridge 171:3a7713b1edbc 388 #define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) /**< PIN6 Mask */
AnnaBridge 171:3a7713b1edbc 389 #define MXC_F_GPIO_FREE_PIN7_POS 7 /**< PIN7 Position */
AnnaBridge 171:3a7713b1edbc 390 #define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) /**< PIN7 Mask */
AnnaBridge 171:3a7713b1edbc 391 /**@} end of group GPIO_FREE */
AnnaBridge 171:3a7713b1edbc 392 /**
AnnaBridge 171:3a7713b1edbc 393 * @ingroup gpio_registers
AnnaBridge 171:3a7713b1edbc 394 * @defgroup GPIO_OUT_MODE_Register GPIO_OUT_MODE
AnnaBridge 171:3a7713b1edbc 395 * @brief Field Positions and Bit Masks for the GPIO_OUT_MODE register.
AnnaBridge 171:3a7713b1edbc 396 * @{
AnnaBridge 171:3a7713b1edbc 397 */
AnnaBridge 171:3a7713b1edbc 398 #define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 /**< PIN0 Position */
AnnaBridge 171:3a7713b1edbc 399 #define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) /**< PIN0 Mask */
AnnaBridge 171:3a7713b1edbc 400 #define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 /**< PIN1 Position */
AnnaBridge 171:3a7713b1edbc 401 #define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) /**< PIN1 Mask */
AnnaBridge 171:3a7713b1edbc 402 #define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 /**< PIN2 Position */
AnnaBridge 171:3a7713b1edbc 403 #define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) /**< PIN2 Mask */
AnnaBridge 171:3a7713b1edbc 404 #define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 /**< PIN3 Position */
AnnaBridge 171:3a7713b1edbc 405 #define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) /**< PIN3 Mask */
AnnaBridge 171:3a7713b1edbc 406 #define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 /**< PIN4 Position */
AnnaBridge 171:3a7713b1edbc 407 #define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) /**< PIN4 Mask */
AnnaBridge 171:3a7713b1edbc 408 #define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 /**< PIN5 Position */
AnnaBridge 171:3a7713b1edbc 409 #define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) /**< PIN5 Mask */
AnnaBridge 171:3a7713b1edbc 410 #define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 /**< PIN6 Position */
AnnaBridge 171:3a7713b1edbc 411 #define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) /**< PIN6 Mask */
AnnaBridge 171:3a7713b1edbc 412 #define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 /**< PIN7 Position */
AnnaBridge 171:3a7713b1edbc 413 #define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) /**< PIN7 Mask */
AnnaBridge 171:3a7713b1edbc 414 /**@} end of group GPIO_OUT_MODE */
AnnaBridge 171:3a7713b1edbc 415 /**
AnnaBridge 171:3a7713b1edbc 416 * @ingroup gpio_registers
AnnaBridge 171:3a7713b1edbc 417 * @defgroup GPIO_OUT_VAL_Register GPIO_OUT_VAL
AnnaBridge 171:3a7713b1edbc 418 * @brief Field Positions and Bit Masks for the GPIO_OUT_VAL register.
AnnaBridge 171:3a7713b1edbc 419 * @{
AnnaBridge 171:3a7713b1edbc 420 */
AnnaBridge 171:3a7713b1edbc 421 #define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 /**< PIN0 Position */
AnnaBridge 171:3a7713b1edbc 422 #define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) /**< PIN0 Mask */
AnnaBridge 171:3a7713b1edbc 423 #define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 /**< PIN1 Position */
AnnaBridge 171:3a7713b1edbc 424 #define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) /**< PIN1 Mask */
AnnaBridge 171:3a7713b1edbc 425 #define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 /**< PIN2 Position */
AnnaBridge 171:3a7713b1edbc 426 #define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) /**< PIN2 Mask */
AnnaBridge 171:3a7713b1edbc 427 #define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 /**< PIN3 Position */
AnnaBridge 171:3a7713b1edbc 428 #define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) /**< PIN3 Mask */
AnnaBridge 171:3a7713b1edbc 429 #define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 /**< PIN4 Position */
AnnaBridge 171:3a7713b1edbc 430 #define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) /**< PIN4 Mask */
AnnaBridge 171:3a7713b1edbc 431 #define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 /**< PIN5 Position */
AnnaBridge 171:3a7713b1edbc 432 #define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) /**< PIN5 Mask */
AnnaBridge 171:3a7713b1edbc 433 #define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 /**< PIN6 Position */
AnnaBridge 171:3a7713b1edbc 434 #define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) /**< PIN6 Mask */
AnnaBridge 171:3a7713b1edbc 435 #define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 /**< PIN7 Position */
AnnaBridge 171:3a7713b1edbc 436 #define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) /**< PIN7 Mask */
AnnaBridge 171:3a7713b1edbc 437 /**@} end of group GPIO_OUT_VAL */
AnnaBridge 171:3a7713b1edbc 438 /**
AnnaBridge 171:3a7713b1edbc 439 * @ingroup gpio_registers
AnnaBridge 171:3a7713b1edbc 440 * @defgroup GPIO_FUNC_SEL_Register GPIO_FUNC_SEL
AnnaBridge 171:3a7713b1edbc 441 * @brief Field Positions and Bit Masks for the GPIO_FUNC_SEL register.
AnnaBridge 171:3a7713b1edbc 442 * @{
AnnaBridge 171:3a7713b1edbc 443 */
AnnaBridge 171:3a7713b1edbc 444 #define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0 /**< PIN0 Position */
AnnaBridge 171:3a7713b1edbc 445 #define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS)) /**< PIN0 Mask */
AnnaBridge 171:3a7713b1edbc 446 #define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4 /**< PIN1 Position */
AnnaBridge 171:3a7713b1edbc 447 #define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS)) /**< PIN1 Mask */
AnnaBridge 171:3a7713b1edbc 448 #define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8 /**< PIN2 Position */
AnnaBridge 171:3a7713b1edbc 449 #define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS)) /**< PIN2 Mask */
AnnaBridge 171:3a7713b1edbc 450 #define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12 /**< PIN3 Position */
AnnaBridge 171:3a7713b1edbc 451 #define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS)) /**< PIN3 Mask */
AnnaBridge 171:3a7713b1edbc 452 #define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16 /**< PIN4 Position */
AnnaBridge 171:3a7713b1edbc 453 #define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS)) /**< PIN4 Mask */
AnnaBridge 171:3a7713b1edbc 454 #define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20 /**< PIN5 Position */
AnnaBridge 171:3a7713b1edbc 455 #define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS)) /**< PIN5 Mask */
AnnaBridge 171:3a7713b1edbc 456 #define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24 /**< PIN6 Position */
AnnaBridge 171:3a7713b1edbc 457 #define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS)) /**< PIN6 Mask */
AnnaBridge 171:3a7713b1edbc 458 #define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28 /**< PIN7 Position */
AnnaBridge 171:3a7713b1edbc 459 #define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS)) /**< PIN7 Mask */
AnnaBridge 171:3a7713b1edbc 460 /**@} end of group GPIO_FUNC_SEL */
AnnaBridge 171:3a7713b1edbc 461 /**
AnnaBridge 171:3a7713b1edbc 462 * @ingroup gpio_registers
AnnaBridge 171:3a7713b1edbc 463 * @defgroup GPIO_IN_MODE_Register GPIO_IN_MODE
AnnaBridge 171:3a7713b1edbc 464 * @brief Field Positions and Bit Masks for the GPIO_IN_MODE register.
AnnaBridge 171:3a7713b1edbc 465 * @{
AnnaBridge 171:3a7713b1edbc 466 */
AnnaBridge 171:3a7713b1edbc 467 #define MXC_F_GPIO_IN_MODE_PIN0_POS 0 /**< PIN0 Position */
AnnaBridge 171:3a7713b1edbc 468 #define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) /**< PIN0 Mask */
AnnaBridge 171:3a7713b1edbc 469 #define MXC_F_GPIO_IN_MODE_PIN1_POS 4 /**< PIN1 Position */
AnnaBridge 171:3a7713b1edbc 470 #define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) /**< PIN1 Mask */
AnnaBridge 171:3a7713b1edbc 471 #define MXC_F_GPIO_IN_MODE_PIN2_POS 8 /**< PIN2 Position */
AnnaBridge 171:3a7713b1edbc 472 #define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) /**< PIN2 Mask */
AnnaBridge 171:3a7713b1edbc 473 #define MXC_F_GPIO_IN_MODE_PIN3_POS 12 /**< PIN3 Position */
AnnaBridge 171:3a7713b1edbc 474 #define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) /**< PIN3 Mask */
AnnaBridge 171:3a7713b1edbc 475 #define MXC_F_GPIO_IN_MODE_PIN4_POS 16 /**< PIN4 Position */
AnnaBridge 171:3a7713b1edbc 476 #define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) /**< PIN4 Mask */
AnnaBridge 171:3a7713b1edbc 477 #define MXC_F_GPIO_IN_MODE_PIN5_POS 20 /**< PIN5 Position */
AnnaBridge 171:3a7713b1edbc 478 #define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) /**< PIN5 Mask */
AnnaBridge 171:3a7713b1edbc 479 #define MXC_F_GPIO_IN_MODE_PIN6_POS 24 /**< PIN6 Position */
AnnaBridge 171:3a7713b1edbc 480 #define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) /**< PIN6 Mask */
AnnaBridge 171:3a7713b1edbc 481 #define MXC_F_GPIO_IN_MODE_PIN7_POS 28 /**< PIN7 Position */
AnnaBridge 171:3a7713b1edbc 482 #define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) /**< PIN7 Mask */
AnnaBridge 171:3a7713b1edbc 483 /**@} end of group GPIO_IN_MODE */
AnnaBridge 171:3a7713b1edbc 484 /**
AnnaBridge 171:3a7713b1edbc 485 * @ingroup gpio_registers
AnnaBridge 171:3a7713b1edbc 486 * @defgroup GPIO_IN_VAL_Register GPIO_IN_VAL
AnnaBridge 171:3a7713b1edbc 487 * @brief Field Positions and Bit Masks for the GPIO_IN_VAL register.
AnnaBridge 171:3a7713b1edbc 488 * @{
AnnaBridge 171:3a7713b1edbc 489 */
AnnaBridge 171:3a7713b1edbc 490 #define MXC_F_GPIO_IN_VAL_PIN0_POS 0 /**< PIN0 Position */
AnnaBridge 171:3a7713b1edbc 491 #define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) /**< PIN0 Mask */
AnnaBridge 171:3a7713b1edbc 492 #define MXC_F_GPIO_IN_VAL_PIN1_POS 1 /**< PIN1 Position */
AnnaBridge 171:3a7713b1edbc 493 #define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) /**< PIN1 Mask */
AnnaBridge 171:3a7713b1edbc 494 #define MXC_F_GPIO_IN_VAL_PIN2_POS 2 /**< PIN2 Position */
AnnaBridge 171:3a7713b1edbc 495 #define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) /**< PIN2 Mask */
AnnaBridge 171:3a7713b1edbc 496 #define MXC_F_GPIO_IN_VAL_PIN3_POS 3 /**< PIN3 Position */
AnnaBridge 171:3a7713b1edbc 497 #define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) /**< PIN3 Mask */
AnnaBridge 171:3a7713b1edbc 498 #define MXC_F_GPIO_IN_VAL_PIN4_POS 4 /**< PIN4 Position */
AnnaBridge 171:3a7713b1edbc 499 #define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) /**< PIN4 Mask */
AnnaBridge 171:3a7713b1edbc 500 #define MXC_F_GPIO_IN_VAL_PIN5_POS 5 /**< PIN5 Position */
AnnaBridge 171:3a7713b1edbc 501 #define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) /**< PIN5 Mask */
AnnaBridge 171:3a7713b1edbc 502 #define MXC_F_GPIO_IN_VAL_PIN6_POS 6 /**< PIN6 Position */
AnnaBridge 171:3a7713b1edbc 503 #define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) /**< PIN6 Mask */
AnnaBridge 171:3a7713b1edbc 504 #define MXC_F_GPIO_IN_VAL_PIN7_POS 7 /**< PIN7 Position */
AnnaBridge 171:3a7713b1edbc 505 #define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) /**< PIN7 Mask */
AnnaBridge 171:3a7713b1edbc 506 /**@} end of group GPIO_IN_VAL */
AnnaBridge 171:3a7713b1edbc 507 /**
AnnaBridge 171:3a7713b1edbc 508 * @ingroup gpio_registers
AnnaBridge 171:3a7713b1edbc 509 * @defgroup GPIO_INT_MODE_Register GPIO_INT_MODE
AnnaBridge 171:3a7713b1edbc 510 * @brief Field Positions and Bit Masks for the GPIO_INT_MODE register.
AnnaBridge 171:3a7713b1edbc 511 * @{
AnnaBridge 171:3a7713b1edbc 512 */
AnnaBridge 171:3a7713b1edbc 513 #define MXC_F_GPIO_INT_MODE_PIN0_POS 0 /**< PIN0 Position */
AnnaBridge 171:3a7713b1edbc 514 #define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) /**< PIN0 Mask */
AnnaBridge 171:3a7713b1edbc 515 #define MXC_F_GPIO_INT_MODE_PIN1_POS 4 /**< PIN1 Position */
AnnaBridge 171:3a7713b1edbc 516 #define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) /**< PIN1 Mask */
AnnaBridge 171:3a7713b1edbc 517 #define MXC_F_GPIO_INT_MODE_PIN2_POS 8 /**< PIN2 Position */
AnnaBridge 171:3a7713b1edbc 518 #define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) /**< PIN2 Mask */
AnnaBridge 171:3a7713b1edbc 519 #define MXC_F_GPIO_INT_MODE_PIN3_POS 12 /**< PIN3 Position */
AnnaBridge 171:3a7713b1edbc 520 #define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) /**< PIN3 Mask */
AnnaBridge 171:3a7713b1edbc 521 #define MXC_F_GPIO_INT_MODE_PIN4_POS 16 /**< PIN4 Position */
AnnaBridge 171:3a7713b1edbc 522 #define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) /**< PIN4 Mask */
AnnaBridge 171:3a7713b1edbc 523 #define MXC_F_GPIO_INT_MODE_PIN5_POS 20 /**< PIN5 Position */
AnnaBridge 171:3a7713b1edbc 524 #define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) /**< PIN5 Mask */
AnnaBridge 171:3a7713b1edbc 525 #define MXC_F_GPIO_INT_MODE_PIN6_POS 24 /**< PIN6 Position */
AnnaBridge 171:3a7713b1edbc 526 #define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) /**< PIN6 Mask */
AnnaBridge 171:3a7713b1edbc 527 #define MXC_F_GPIO_INT_MODE_PIN7_POS 28 /**< PIN7 Position */
AnnaBridge 171:3a7713b1edbc 528 #define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) /**< PIN7 Mask */
AnnaBridge 171:3a7713b1edbc 529 /**@} end of group GPIO_INT_MODE */
AnnaBridge 171:3a7713b1edbc 530 /**
AnnaBridge 171:3a7713b1edbc 531 * @ingroup gpio_registers
AnnaBridge 171:3a7713b1edbc 532 * @defgroup GPIO_INTFL_Register GPIO_INTFL
AnnaBridge 171:3a7713b1edbc 533 * @brief Field Positions and Bit Masks for the GPIO_INTFL register.
AnnaBridge 171:3a7713b1edbc 534 * @{
AnnaBridge 171:3a7713b1edbc 535 */
AnnaBridge 171:3a7713b1edbc 536 #define MXC_F_GPIO_INTFL_PIN0_POS 0 /**< PIN0 Position */
AnnaBridge 171:3a7713b1edbc 537 #define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) /**< PIN0 Mask */
AnnaBridge 171:3a7713b1edbc 538 #define MXC_F_GPIO_INTFL_PIN1_POS 1 /**< PIN1 Position */
AnnaBridge 171:3a7713b1edbc 539 #define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) /**< PIN1 Mask */
AnnaBridge 171:3a7713b1edbc 540 #define MXC_F_GPIO_INTFL_PIN2_POS 2 /**< PIN2 Position */
AnnaBridge 171:3a7713b1edbc 541 #define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) /**< PIN2 Mask */
AnnaBridge 171:3a7713b1edbc 542 #define MXC_F_GPIO_INTFL_PIN3_POS 3 /**< PIN3 Position */
AnnaBridge 171:3a7713b1edbc 543 #define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) /**< PIN3 Mask */
AnnaBridge 171:3a7713b1edbc 544 #define MXC_F_GPIO_INTFL_PIN4_POS 4 /**< PIN4 Position */
AnnaBridge 171:3a7713b1edbc 545 #define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) /**< PIN4 Mask */
AnnaBridge 171:3a7713b1edbc 546 #define MXC_F_GPIO_INTFL_PIN5_POS 5 /**< PIN5 Position */
AnnaBridge 171:3a7713b1edbc 547 #define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) /**< PIN5 Mask */
AnnaBridge 171:3a7713b1edbc 548 #define MXC_F_GPIO_INTFL_PIN6_POS 6 /**< PIN6 Position */
AnnaBridge 171:3a7713b1edbc 549 #define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) /**< PIN6 Mask */
AnnaBridge 171:3a7713b1edbc 550 #define MXC_F_GPIO_INTFL_PIN7_POS 7 /**< PIN7 Position */
AnnaBridge 171:3a7713b1edbc 551 #define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) /**< PIN7 Mask */
AnnaBridge 171:3a7713b1edbc 552 /**@} end of group GPIO_INTFL */
AnnaBridge 171:3a7713b1edbc 553 /**
AnnaBridge 171:3a7713b1edbc 554 * @ingroup gpio_registers
AnnaBridge 171:3a7713b1edbc 555 * @defgroup GPIO_INTEN_Register GPIO_INTEN
AnnaBridge 171:3a7713b1edbc 556 * @brief Field Positions and Bit Masks for the GPIO_INTEN register.
AnnaBridge 171:3a7713b1edbc 557 * @{
AnnaBridge 171:3a7713b1edbc 558 */
AnnaBridge 171:3a7713b1edbc 559 #define MXC_F_GPIO_INTEN_PIN0_POS 0 /**< PIN0 Position */
AnnaBridge 171:3a7713b1edbc 560 #define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) /**< PIN0 Mask */
AnnaBridge 171:3a7713b1edbc 561 #define MXC_F_GPIO_INTEN_PIN1_POS 1 /**< PIN1 Position */
AnnaBridge 171:3a7713b1edbc 562 #define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) /**< PIN1 Mask */
AnnaBridge 171:3a7713b1edbc 563 #define MXC_F_GPIO_INTEN_PIN2_POS 2 /**< PIN2 Position */
AnnaBridge 171:3a7713b1edbc 564 #define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) /**< PIN2 Mask */
AnnaBridge 171:3a7713b1edbc 565 #define MXC_F_GPIO_INTEN_PIN3_POS 3 /**< PIN3 Position */
AnnaBridge 171:3a7713b1edbc 566 #define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) /**< PIN3 Mask */
AnnaBridge 171:3a7713b1edbc 567 #define MXC_F_GPIO_INTEN_PIN4_POS 4 /**< PIN4 Position */
AnnaBridge 171:3a7713b1edbc 568 #define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) /**< PIN4 Mask */
AnnaBridge 171:3a7713b1edbc 569 #define MXC_F_GPIO_INTEN_PIN5_POS 5 /**< PIN5 Position */
AnnaBridge 171:3a7713b1edbc 570 #define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) /**< PIN5 Mask */
AnnaBridge 171:3a7713b1edbc 571 #define MXC_F_GPIO_INTEN_PIN6_POS 6 /**< PIN6 Position */
AnnaBridge 171:3a7713b1edbc 572 #define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) /**< PIN6 Mask */
AnnaBridge 171:3a7713b1edbc 573 #define MXC_F_GPIO_INTEN_PIN7_POS 7 /**< PIN7 Position */
AnnaBridge 171:3a7713b1edbc 574 #define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) /**< PIN7 Mask */
AnnaBridge 171:3a7713b1edbc 575 /**@} end group GPIO_INTEN_Register */
AnnaBridge 171:3a7713b1edbc 576
AnnaBridge 171:3a7713b1edbc 577
AnnaBridge 171:3a7713b1edbc 578 /*
AnnaBridge 171:3a7713b1edbc 579 Field values and shifted values for module GPIO.
AnnaBridge 171:3a7713b1edbc 580 */
AnnaBridge 171:3a7713b1edbc 581 /**
AnnaBridge 171:3a7713b1edbc 582 * @ingroup GPIO_RST_MODE_Register
AnnaBridge 171:3a7713b1edbc 583 * @defgroup GPIO_RST_MODE_Values Reset Mode Values
AnnaBridge 171:3a7713b1edbc 584 * @brief Mode Values for setting the GPIO_RST_MODE Field for different pad modes
AnnaBridge 171:3a7713b1edbc 585 * @{
AnnaBridge 171:3a7713b1edbc 586 */
AnnaBridge 171:3a7713b1edbc 587 #define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL)) /**< DRIVE_0 */
AnnaBridge 171:3a7713b1edbc 588 #define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL)) /**< WEAK_PULLDOWN */
AnnaBridge 171:3a7713b1edbc 589 #define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< WEAK_PULLUP */
AnnaBridge 171:3a7713b1edbc 590 #define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL)) /**< DRIVE_1 */
AnnaBridge 171:3a7713b1edbc 591 #define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL)) /**< HIGH_Z */
AnnaBridge 171:3a7713b1edbc 592 /**@}*/
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 /**
AnnaBridge 171:3a7713b1edbc 595 * @ingroup GPIO_FREE_Register
AnnaBridge 171:3a7713b1edbc 596 * @defgroup GPIO_FREE_Values Reset Mode Values
AnnaBridge 171:3a7713b1edbc 597 * @brief Mode Values for setting the GPIO_FREE to Available or Unavailable
AnnaBridge 171:3a7713b1edbc 598 * @{
AnnaBridge 171:3a7713b1edbc 599 */
AnnaBridge 171:3a7713b1edbc 600 #define MXC_V_GPIO_FREE_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) /**< GPIO Pin is Unavailable */
AnnaBridge 171:3a7713b1edbc 601 #define MXC_V_GPIO_FREE_AVAILABLE ((uint32_t)(0x00000001UL)) /**< GPIO Pin is Available */
AnnaBridge 171:3a7713b1edbc 602 /**@}*/
AnnaBridge 171:3a7713b1edbc 603
AnnaBridge 171:3a7713b1edbc 604 /**
AnnaBridge 171:3a7713b1edbc 605 * @ingroup GPIO_FREE_Register
AnnaBridge 171:3a7713b1edbc 606 * @defgroup GPIO_OUT_MODE_Values Output Mode Values
AnnaBridge 171:3a7713b1edbc 607 * @brief GPIO_OUT_MODE values for setting the different port pin output modes
AnnaBridge 171:3a7713b1edbc 608 * @{
AnnaBridge 171:3a7713b1edbc 609 */
AnnaBridge 171:3a7713b1edbc 610 #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLUP */
AnnaBridge 171:3a7713b1edbc 611 #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN */
AnnaBridge 171:3a7713b1edbc 612 #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN_WEAK_PULLUP */
AnnaBridge 171:3a7713b1edbc 613 #define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) /**< See \MXIM_Device User Guide for details: NORMAL_HIGH_Z */
AnnaBridge 171:3a7713b1edbc 614 #define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL)) /**< See \MXIM_Device User Guide for details: NORMAL */
AnnaBridge 171:3a7713b1edbc 615 #define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) /**< See \MXIM_Device User Guide for details: SLOW_HIGH_Z */
AnnaBridge 171:3a7713b1edbc 616 #define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) /**< See \MXIM_Device User Guide for details: SLOW_DRIVE */
AnnaBridge 171:3a7713b1edbc 617 #define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) /**< See \MXIM_Device User Guide for details: FAST_HIGH_Z */
AnnaBridge 171:3a7713b1edbc 618 #define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) /**< See \MXIM_Device User Guide for details: FAST_DRIVE */
AnnaBridge 171:3a7713b1edbc 619 #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLDOWN */
AnnaBridge 171:3a7713b1edbc 620 #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE */
AnnaBridge 171:3a7713b1edbc 621 #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE_WEAK_PULLDOWN */
AnnaBridge 171:3a7713b1edbc 622 #define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_INPUT_DISABLED */
AnnaBridge 171:3a7713b1edbc 623 /**@}*/
AnnaBridge 171:3a7713b1edbc 624
AnnaBridge 171:3a7713b1edbc 625 /**
AnnaBridge 171:3a7713b1edbc 626 * @ingroup GPIO_FUNC_SEL_Register
AnnaBridge 171:3a7713b1edbc 627 * @defgroup GPIO_FUNC_SEL_Values Function type selection values
AnnaBridge 171:3a7713b1edbc 628 * @brief Function selection values for the GPIO_FUNC_SEL Register.
AnnaBridge 171:3a7713b1edbc 629 * @{
AnnaBridge 171:3a7713b1edbc 630 */
AnnaBridge 171:3a7713b1edbc 631 #define MXC_V_GPIO_FUNC_SEL_MODE_GPIO ((uint32_t)(0x00000000UL)) /**< Standard GPIO Mode */
AnnaBridge 171:3a7713b1edbc 632 #define MXC_V_GPIO_FUNC_SEL_MODE_PT ((uint32_t)(0x00000001UL)) /**< Pulse Train Mode */
AnnaBridge 171:3a7713b1edbc 633 #define MXC_V_GPIO_FUNC_SEL_MODE_TMR ((uint32_t)(0x00000002UL)) /**< Timer Mode */
AnnaBridge 171:3a7713b1edbc 634 /**@}*/
AnnaBridge 171:3a7713b1edbc 635
AnnaBridge 171:3a7713b1edbc 636 /**
AnnaBridge 171:3a7713b1edbc 637 * @ingroup GPIO_IN_MODE_Register
AnnaBridge 171:3a7713b1edbc 638 * @defgroup GPIO_IN_MODE_Values Input mode selection values
AnnaBridge 171:3a7713b1edbc 639 * @brief Input mode values for selecting the GPIO input mode.
AnnaBridge 171:3a7713b1edbc 640 * @{
AnnaBridge 171:3a7713b1edbc 641 */
AnnaBridge 171:3a7713b1edbc 642 #define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL)) /**< Normal Input Mode */
AnnaBridge 171:3a7713b1edbc 643 #define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL)) /**< Inverted Input Mode */
AnnaBridge 171:3a7713b1edbc 644 #define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) /**< Always reads 0 */
AnnaBridge 171:3a7713b1edbc 645 #define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL)) /**< Always reads 1 */
AnnaBridge 171:3a7713b1edbc 646 /**@}*/
AnnaBridge 171:3a7713b1edbc 647
AnnaBridge 171:3a7713b1edbc 648 /**
AnnaBridge 171:3a7713b1edbc 649 * @ingroup GPIO_INT_MODE_Register
AnnaBridge 171:3a7713b1edbc 650 * @defgroup GPIO_INT_MODE_Values Interrupt mode selection values
AnnaBridge 171:3a7713b1edbc 651 * @brief Values for setting the interrupt mode of a GPIO input pin.
AnnaBridge 171:3a7713b1edbc 652 * @{
AnnaBridge 171:3a7713b1edbc 653 */
AnnaBridge 171:3a7713b1edbc 654 #define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL)) /**< Disable Interrupt for a given port pin */
AnnaBridge 171:3a7713b1edbc 655 #define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) /**< Interrupt on falling edge */
AnnaBridge 171:3a7713b1edbc 656 #define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) /**< Interrupt on rising edge */
AnnaBridge 171:3a7713b1edbc 657 #define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL)) /**< Interrupt on rising or falling edge */
AnnaBridge 171:3a7713b1edbc 658 #define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL)) /**< Interrupt on Low Level */
AnnaBridge 171:3a7713b1edbc 659 #define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL)) /**< Interrupt on High Level */
AnnaBridge 171:3a7713b1edbc 660 /**@}*/
AnnaBridge 171:3a7713b1edbc 661
AnnaBridge 171:3a7713b1edbc 662 /**@}*/
AnnaBridge 171:3a7713b1edbc 663 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 664 }
AnnaBridge 171:3a7713b1edbc 665 #endif
AnnaBridge 171:3a7713b1edbc 666
AnnaBridge 171:3a7713b1edbc 667 #endif /* _MXC_GPIO_REGS_H_ */
AnnaBridge 171:3a7713b1edbc 668