The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_MAX32625PICO_NO_BOOT/TARGET_Maxim/TARGET_MAX32625/device/max32625.h@169:a7c7b631e539
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 169:a7c7b631e539 1 /*******************************************************************************
Anna Bridge 169:a7c7b631e539 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
Anna Bridge 169:a7c7b631e539 3 *
Anna Bridge 169:a7c7b631e539 4 * Permission is hereby granted, free of charge, to any person obtaining a
Anna Bridge 169:a7c7b631e539 5 * copy of this software and associated documentation files (the "Software"),
Anna Bridge 169:a7c7b631e539 6 * to deal in the Software without restriction, including without limitation
Anna Bridge 169:a7c7b631e539 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Anna Bridge 169:a7c7b631e539 8 * and/or sell copies of the Software, and to permit persons to whom the
Anna Bridge 169:a7c7b631e539 9 * Software is furnished to do so, subject to the following conditions:
Anna Bridge 169:a7c7b631e539 10 *
Anna Bridge 169:a7c7b631e539 11 * The above copyright notice and this permission notice shall be included
Anna Bridge 169:a7c7b631e539 12 * in all copies or substantial portions of the Software.
Anna Bridge 169:a7c7b631e539 13 *
Anna Bridge 169:a7c7b631e539 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Anna Bridge 169:a7c7b631e539 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Anna Bridge 169:a7c7b631e539 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Anna Bridge 169:a7c7b631e539 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Anna Bridge 169:a7c7b631e539 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Anna Bridge 169:a7c7b631e539 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Anna Bridge 169:a7c7b631e539 20 * OTHER DEALINGS IN THE SOFTWARE.
Anna Bridge 169:a7c7b631e539 21 *
Anna Bridge 169:a7c7b631e539 22 * Except as contained in this notice, the name of Maxim Integrated
Anna Bridge 169:a7c7b631e539 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Anna Bridge 169:a7c7b631e539 24 * Products, Inc. Branding Policy.
Anna Bridge 169:a7c7b631e539 25 *
Anna Bridge 169:a7c7b631e539 26 * The mere transfer of this software does not imply any licenses
Anna Bridge 169:a7c7b631e539 27 * of trade secrets, proprietary technology, copyrights, patents,
Anna Bridge 169:a7c7b631e539 28 * trademarks, maskwork rights, or any other form of intellectual
Anna Bridge 169:a7c7b631e539 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Anna Bridge 169:a7c7b631e539 30 * ownership rights.
Anna Bridge 169:a7c7b631e539 31 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 32
Anna Bridge 169:a7c7b631e539 33 #ifndef _MAX32625_H_
Anna Bridge 169:a7c7b631e539 34 #define _MAX32625_H_
Anna Bridge 169:a7c7b631e539 35
Anna Bridge 169:a7c7b631e539 36 #include <stdint.h>
Anna Bridge 169:a7c7b631e539 37
Anna Bridge 169:a7c7b631e539 38 #ifndef FALSE
Anna Bridge 169:a7c7b631e539 39 #define FALSE (0)
Anna Bridge 169:a7c7b631e539 40 #endif
Anna Bridge 169:a7c7b631e539 41
Anna Bridge 169:a7c7b631e539 42 #ifndef TRUE
Anna Bridge 169:a7c7b631e539 43 #define TRUE (1)
Anna Bridge 169:a7c7b631e539 44 #endif
Anna Bridge 169:a7c7b631e539 45
Anna Bridge 169:a7c7b631e539 46 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
Anna Bridge 169:a7c7b631e539 47 #if defined ( __GNUC__ )
Anna Bridge 169:a7c7b631e539 48 #define __weak __attribute__((weak))
Anna Bridge 169:a7c7b631e539 49
Anna Bridge 169:a7c7b631e539 50 #elif defined ( __CC_ARM)
Anna Bridge 169:a7c7b631e539 51
Anna Bridge 169:a7c7b631e539 52 #define inline __inline
Anna Bridge 169:a7c7b631e539 53 #pragma anon_unions
Anna Bridge 169:a7c7b631e539 54
Anna Bridge 169:a7c7b631e539 55 #endif
Anna Bridge 169:a7c7b631e539 56
Anna Bridge 169:a7c7b631e539 57 typedef enum {
Anna Bridge 169:a7c7b631e539 58 NonMaskableInt_IRQn = -14,
Anna Bridge 169:a7c7b631e539 59 HardFault_IRQn = -13,
Anna Bridge 169:a7c7b631e539 60 MemoryManagement_IRQn = -12,
Anna Bridge 169:a7c7b631e539 61 BusFault_IRQn = -11,
Anna Bridge 169:a7c7b631e539 62 UsageFault_IRQn = -10,
Anna Bridge 169:a7c7b631e539 63 SVCall_IRQn = -5,
Anna Bridge 169:a7c7b631e539 64 DebugMonitor_IRQn = -4,
Anna Bridge 169:a7c7b631e539 65 PendSV_IRQn = -2,
Anna Bridge 169:a7c7b631e539 66 SysTick_IRQn = -1,
Anna Bridge 169:a7c7b631e539 67
Anna Bridge 169:a7c7b631e539 68 /* Device-specific interrupt sources (external to ARM core) */
Anna Bridge 169:a7c7b631e539 69 /* table entry number */
Anna Bridge 169:a7c7b631e539 70 /* |||| */
Anna Bridge 169:a7c7b631e539 71 /* |||| table offset address */
Anna Bridge 169:a7c7b631e539 72 /* vvvv vvvvvv */
Anna Bridge 169:a7c7b631e539 73
Anna Bridge 169:a7c7b631e539 74 CLKMAN_IRQn = 0, /* 0x10 0x0040,CLKMAN */
Anna Bridge 169:a7c7b631e539 75 PWRMAN_IRQn = 1, /* 0x11 0x0044 PWRMAN */
Anna Bridge 169:a7c7b631e539 76 FLC_IRQn = 2, /* 0x12 0x0048 Flash Controller */
Anna Bridge 169:a7c7b631e539 77 RTC0_IRQn = 3, /* 0x13 0x004C RTC Counter match with Compare 0 */
Anna Bridge 169:a7c7b631e539 78 RTC1_IRQn = 4, /* 0x14 0x0050 RTC Counter match with Compare 1 */
Anna Bridge 169:a7c7b631e539 79 RTC2_IRQn = 5, /* 0x15 0x0054 RTC Prescaler interval compare match */
Anna Bridge 169:a7c7b631e539 80 RTC3_IRQn = 6, /* 0x16 0x0058 RTC Overflow */
Anna Bridge 169:a7c7b631e539 81 PMU_IRQn = 7, /* 0x17 0x005C Peripheral Management Unit (PMU/DMA) */
Anna Bridge 169:a7c7b631e539 82 USB_IRQn = 8, /* 0x18 0x0060 USB */
Anna Bridge 169:a7c7b631e539 83 AES_IRQn = 9, /* 0x19 0x0064 AES */
Anna Bridge 169:a7c7b631e539 84 MAA_IRQn = 10, /* 0x1A 0x0068 MAA */
Anna Bridge 169:a7c7b631e539 85 WDT0_IRQn = 11, /* 0x1B 0x006C Watchdog 0 timeout */
Anna Bridge 169:a7c7b631e539 86 WDT0_P_IRQn = 12, /* 0x1C 0x0070 Watchdog 0 pre-window (fed too early) */
Anna Bridge 169:a7c7b631e539 87 WDT1_IRQn = 13, /* 0x1D 0x0074 Watchdog 1 timeout */
Anna Bridge 169:a7c7b631e539 88 WDT1_P_IRQn = 14, /* 0x1E 0x0078 Watchdog 1 pre-window (fed too early) */
Anna Bridge 169:a7c7b631e539 89 GPIO_P0_IRQn = 15, /* 0x1F 0x007C GPIO Port 0 */
Anna Bridge 169:a7c7b631e539 90 GPIO_P1_IRQn = 16, /* 0x20 0x0080 GPIO Port 1 */
Anna Bridge 169:a7c7b631e539 91 GPIO_P2_IRQn = 17, /* 0x21 0x0084 GPIO Port 2 */
Anna Bridge 169:a7c7b631e539 92 GPIO_P3_IRQn = 18, /* 0x22 0x0088 GPIO Port 3 */
Anna Bridge 169:a7c7b631e539 93 GPIO_P4_IRQn = 19, /* 0x23 0x008C GPIO Port 4 */
Anna Bridge 169:a7c7b631e539 94 GPIO_P5_IRQn = 20, /* 0x24 0x0090 GPIO Port 5 (Unused) */
Anna Bridge 169:a7c7b631e539 95 GPIO_P6_IRQn = 21, /* 0x25 0x0094 GPIO Port 6 (Unused) */
Anna Bridge 169:a7c7b631e539 96 TMR0_0_IRQn = 22, /* 0x26 0x0098 Timer 0 (32-bit, 16-bit #0) */
Anna Bridge 169:a7c7b631e539 97 TMR0_1_IRQn = 23, /* 0x27 0x009C Timer 0 (16-bit #1) */
Anna Bridge 169:a7c7b631e539 98 TMR1_0_IRQn = 24, /* 0x28 0x00A0 Timer 1 (32-bit, 16-bit #0) */
Anna Bridge 169:a7c7b631e539 99 TMR1_1_IRQn = 25, /* 0x29 0x00A4 Timer 1 (16-bit #1) */
Anna Bridge 169:a7c7b631e539 100 TMR2_0_IRQn = 26, /* 0x2A 0x00A8 Timer 2 (32-bit, 16-bit #0) */
Anna Bridge 169:a7c7b631e539 101 TMR2_1_IRQn = 27, /* 0x2B 0x00AC Timer 2 (16-bit #1) */
Anna Bridge 169:a7c7b631e539 102 TMR3_0_IRQn = 28, /* 0x2C 0x00B0 Timer 3 (32-bit, 16-bit #0) */
Anna Bridge 169:a7c7b631e539 103 TMR3_1_IRQn = 29, /* 0x2D 0x00B4 Timer 3 (16-bit #1) */
Anna Bridge 169:a7c7b631e539 104 TMR4_0_IRQn = 30, /* 0x2E 0x00B8 Timer 4 (32-bit, 16-bit #0) */
Anna Bridge 169:a7c7b631e539 105 TMR4_1_IRQn = 31, /* 0x2F 0x00BC Timer 4 (16-bit #1) */
Anna Bridge 169:a7c7b631e539 106 TMR5_0_IRQn = 32, /* 0x30 0x00C0 Timer 5 (32-bit, 16-bit #0) */
Anna Bridge 169:a7c7b631e539 107 TMR5_1_IRQn = 33, /* 0x31 0x00C4 Timer 5 (16-bit #1) */
Anna Bridge 169:a7c7b631e539 108 UART0_IRQn = 34, /* 0x32 0x00C8 UART 0 */
Anna Bridge 169:a7c7b631e539 109 UART1_IRQn = 35, /* 0x33 0x00CC UART 1 */
Anna Bridge 169:a7c7b631e539 110 UART2_IRQn = 36, /* 0x34 0x00D0 UART 2 */
Anna Bridge 169:a7c7b631e539 111 UART3_IRQn = 37, /* 0x35 0x00D4 UART 3 (Unused) */
Anna Bridge 169:a7c7b631e539 112 PT_IRQn = 38, /* 0x36 0x00D8 Pulse Trains */
Anna Bridge 169:a7c7b631e539 113 I2CM0_IRQn = 39, /* 0x37 0x00DC I2C Master 0 */
Anna Bridge 169:a7c7b631e539 114 I2CM1_IRQn = 40, /* 0x38 0x00E0 I2C Master 1 */
Anna Bridge 169:a7c7b631e539 115 I2CM2_IRQn = 41, /* 0x39 0x00E4 I2C Master 2 (Unused) */
Anna Bridge 169:a7c7b631e539 116 I2CS_IRQn = 42, /* 0x3A 0x00E8 I2C Slave */
Anna Bridge 169:a7c7b631e539 117 SPIM0_IRQn = 43, /* 0x3B 0x00EC SPI Master 0 */
Anna Bridge 169:a7c7b631e539 118 SPIM1_IRQn = 44, /* 0x3C 0x00F0 SPI Master 1 */
Anna Bridge 169:a7c7b631e539 119 SPIM2_IRQn = 45, /* 0x3D 0x00F4 SPI Master 2 */
Anna Bridge 169:a7c7b631e539 120 SPIB_IRQn = 46, /* 0x3E 0x00F8 SPI Bridge (Unused) */
Anna Bridge 169:a7c7b631e539 121 OWM_IRQn = 47, /* 0x3F 0x00FC 1-Wire Master */
Anna Bridge 169:a7c7b631e539 122 AFE_IRQn = 48, /* 0x40 0x0100 Analog Front End, ADC */
Anna Bridge 169:a7c7b631e539 123 SPIS_IRQn = 49, /* 0x41 0x0104 SPI Slave */
Anna Bridge 169:a7c7b631e539 124 MXC_IRQ_EXT_COUNT,
Anna Bridge 169:a7c7b631e539 125 } IRQn_Type;
Anna Bridge 169:a7c7b631e539 126
Anna Bridge 169:a7c7b631e539 127 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
Anna Bridge 169:a7c7b631e539 128
Anna Bridge 169:a7c7b631e539 129
Anna Bridge 169:a7c7b631e539 130 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 131 /* ================ Processor and Core Peripheral Section ================ */
Anna Bridge 169:a7c7b631e539 132 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 133
Anna Bridge 169:a7c7b631e539 134 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
Anna Bridge 169:a7c7b631e539 135 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
Anna Bridge 169:a7c7b631e539 136 #define __MPU_PRESENT 0 /*!< MPU present or not */
Anna Bridge 169:a7c7b631e539 137 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
Anna Bridge 169:a7c7b631e539 138 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Anna Bridge 169:a7c7b631e539 139 #define __FPU_PRESENT 1 /*!< FPU present or not */
Anna Bridge 169:a7c7b631e539 140
Anna Bridge 169:a7c7b631e539 141 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
Anna Bridge 169:a7c7b631e539 142 #include "system_max32625.h" /*!< System Header */
Anna Bridge 169:a7c7b631e539 143
Anna Bridge 169:a7c7b631e539 144
Anna Bridge 169:a7c7b631e539 145 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 146 /* ================== Device Specific Memory Section ================== */
Anna Bridge 169:a7c7b631e539 147 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 148
Anna Bridge 169:a7c7b631e539 149 #define MXC_FLASH_MEM_BASE 0x00000000UL
Anna Bridge 169:a7c7b631e539 150 #define MXC_FLASH_PAGE_SIZE 0x00002000UL
Anna Bridge 169:a7c7b631e539 151 #define MXC_FLASH_FULL_MEM_SIZE 0x00080000UL
Anna Bridge 169:a7c7b631e539 152 #define MXC_SYS_MEM_BASE 0x20000000UL
Anna Bridge 169:a7c7b631e539 153 #define MXC_SRAM_FULL_MEM_SIZE 0x00028000UL
Anna Bridge 169:a7c7b631e539 154 #define MXC_EXT_FLASH_MEM_BASE 0x10000000UL
Anna Bridge 169:a7c7b631e539 155
Anna Bridge 169:a7c7b631e539 156 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 157 /* ================ Device Specific Peripheral Section ================ */
Anna Bridge 169:a7c7b631e539 158 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 159
Anna Bridge 169:a7c7b631e539 160
Anna Bridge 169:a7c7b631e539 161 /*
Anna Bridge 169:a7c7b631e539 162 Base addresses and configuration settings for all MAX32625 peripheral modules.
Anna Bridge 169:a7c7b631e539 163 */
Anna Bridge 169:a7c7b631e539 164
Anna Bridge 169:a7c7b631e539 165
Anna Bridge 169:a7c7b631e539 166 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 167 /* System Manager Settings */
Anna Bridge 169:a7c7b631e539 168
Anna Bridge 169:a7c7b631e539 169 #define MXC_BASE_SYSMAN ((uint32_t)0x40000000UL)
Anna Bridge 169:a7c7b631e539 170 #define MXC_SYSMAN ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN)
Anna Bridge 169:a7c7b631e539 171
Anna Bridge 169:a7c7b631e539 172
Anna Bridge 169:a7c7b631e539 173
Anna Bridge 169:a7c7b631e539 174 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 175 /* System Clock Manager */
Anna Bridge 169:a7c7b631e539 176
Anna Bridge 169:a7c7b631e539 177 #define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL)
Anna Bridge 169:a7c7b631e539 178 #define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
Anna Bridge 169:a7c7b631e539 179
Anna Bridge 169:a7c7b631e539 180
Anna Bridge 169:a7c7b631e539 181
Anna Bridge 169:a7c7b631e539 182 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 183 /* System Power Manager */
Anna Bridge 169:a7c7b631e539 184
Anna Bridge 169:a7c7b631e539 185 #define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL)
Anna Bridge 169:a7c7b631e539 186 #define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
Anna Bridge 169:a7c7b631e539 187
Anna Bridge 169:a7c7b631e539 188
Anna Bridge 169:a7c7b631e539 189
Anna Bridge 169:a7c7b631e539 190 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 191 /* Real Time Clock */
Anna Bridge 169:a7c7b631e539 192
Anna Bridge 169:a7c7b631e539 193 #define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL)
Anna Bridge 169:a7c7b631e539 194 #define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
Anna Bridge 169:a7c7b631e539 195 #define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL)
Anna Bridge 169:a7c7b631e539 196 #define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
Anna Bridge 169:a7c7b631e539 197
Anna Bridge 169:a7c7b631e539 198 #define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? RTC0_IRQn : \
Anna Bridge 169:a7c7b631e539 199 (i) == 1 ? RTC1_IRQn : \
Anna Bridge 169:a7c7b631e539 200 (i) == 2 ? RTC2_IRQn : \
Anna Bridge 169:a7c7b631e539 201 (i) == 3 ? RTC3_IRQn : 0)
Anna Bridge 169:a7c7b631e539 202
Anna Bridge 169:a7c7b631e539 203
Anna Bridge 169:a7c7b631e539 204
Anna Bridge 169:a7c7b631e539 205 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 206 /* Power Sequencer */
Anna Bridge 169:a7c7b631e539 207
Anna Bridge 169:a7c7b631e539 208 #define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL)
Anna Bridge 169:a7c7b631e539 209 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
Anna Bridge 169:a7c7b631e539 210
Anna Bridge 169:a7c7b631e539 211
Anna Bridge 169:a7c7b631e539 212
Anna Bridge 169:a7c7b631e539 213 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 214 /* System I/O Manager */
Anna Bridge 169:a7c7b631e539 215
Anna Bridge 169:a7c7b631e539 216 #define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL)
Anna Bridge 169:a7c7b631e539 217 #define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
Anna Bridge 169:a7c7b631e539 218
Anna Bridge 169:a7c7b631e539 219
Anna Bridge 169:a7c7b631e539 220
Anna Bridge 169:a7c7b631e539 221 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 222 /* Shadow Trim Registers */
Anna Bridge 169:a7c7b631e539 223
Anna Bridge 169:a7c7b631e539 224 #define MXC_BASE_TRIM ((uint32_t)0x40001000UL)
Anna Bridge 169:a7c7b631e539 225 #define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM)
Anna Bridge 169:a7c7b631e539 226
Anna Bridge 169:a7c7b631e539 227
Anna Bridge 169:a7c7b631e539 228
Anna Bridge 169:a7c7b631e539 229 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 230 /* Flash Controller */
Anna Bridge 169:a7c7b631e539 231
Anna Bridge 169:a7c7b631e539 232 #define MXC_BASE_FLC ((uint32_t)0x40002000UL)
Anna Bridge 169:a7c7b631e539 233 #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
Anna Bridge 169:a7c7b631e539 234
Anna Bridge 169:a7c7b631e539 235 #define MXC_FLC_PAGE_SIZE_SHIFT (13)
Anna Bridge 169:a7c7b631e539 236 #define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
Anna Bridge 169:a7c7b631e539 237 #define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
Anna Bridge 169:a7c7b631e539 238
Anna Bridge 169:a7c7b631e539 239
Anna Bridge 169:a7c7b631e539 240
Anna Bridge 169:a7c7b631e539 241 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 242 /* Instruction Cache */
Anna Bridge 169:a7c7b631e539 243
Anna Bridge 169:a7c7b631e539 244 #define MXC_BASE_ICC ((uint32_t)0x40003000UL)
Anna Bridge 169:a7c7b631e539 245 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
Anna Bridge 169:a7c7b631e539 246
Anna Bridge 169:a7c7b631e539 247
Anna Bridge 169:a7c7b631e539 248
Anna Bridge 169:a7c7b631e539 249 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 250 /* SPI XIP Interface */
Anna Bridge 169:a7c7b631e539 251
Anna Bridge 169:a7c7b631e539 252 #define MXC_BASE_SPIX ((uint32_t)0x40004000UL)
Anna Bridge 169:a7c7b631e539 253 #define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX)
Anna Bridge 169:a7c7b631e539 254
Anna Bridge 169:a7c7b631e539 255
Anna Bridge 169:a7c7b631e539 256
Anna Bridge 169:a7c7b631e539 257 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 258 /* Peripheral Management Unit */
Anna Bridge 169:a7c7b631e539 259
Anna Bridge 169:a7c7b631e539 260 #define MXC_CFG_PMU_CHANNELS (6)
Anna Bridge 169:a7c7b631e539 261
Anna Bridge 169:a7c7b631e539 262 #define MXC_BASE_PMU0 ((uint32_t)0x40005000UL)
Anna Bridge 169:a7c7b631e539 263 #define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
Anna Bridge 169:a7c7b631e539 264 #define MXC_BASE_PMU1 ((uint32_t)0x40005020UL)
Anna Bridge 169:a7c7b631e539 265 #define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
Anna Bridge 169:a7c7b631e539 266 #define MXC_BASE_PMU2 ((uint32_t)0x40005040UL)
Anna Bridge 169:a7c7b631e539 267 #define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
Anna Bridge 169:a7c7b631e539 268 #define MXC_BASE_PMU3 ((uint32_t)0x40005060UL)
Anna Bridge 169:a7c7b631e539 269 #define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
Anna Bridge 169:a7c7b631e539 270 #define MXC_BASE_PMU4 ((uint32_t)0x40005080UL)
Anna Bridge 169:a7c7b631e539 271 #define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
Anna Bridge 169:a7c7b631e539 272 #define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL)
Anna Bridge 169:a7c7b631e539 273 #define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
Anna Bridge 169:a7c7b631e539 274
Anna Bridge 169:a7c7b631e539 275 #define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \
Anna Bridge 169:a7c7b631e539 276 (i) == 1 ? MXC_BASE_PMU1 : \
Anna Bridge 169:a7c7b631e539 277 (i) == 2 ? MXC_BASE_PMU2 : \
Anna Bridge 169:a7c7b631e539 278 (i) == 3 ? MXC_BASE_PMU3 : \
Anna Bridge 169:a7c7b631e539 279 (i) == 4 ? MXC_BASE_PMU4 : \
Anna Bridge 169:a7c7b631e539 280 (i) == 5 ? MXC_BASE_PMU5 : 0)
Anna Bridge 169:a7c7b631e539 281
Anna Bridge 169:a7c7b631e539 282 #define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \
Anna Bridge 169:a7c7b631e539 283 (i) == 1 ? MXC_PMU1 : \
Anna Bridge 169:a7c7b631e539 284 (i) == 2 ? MXC_PMU2 : \
Anna Bridge 169:a7c7b631e539 285 (i) == 3 ? MXC_PMU3 : \
Anna Bridge 169:a7c7b631e539 286 (i) == 4 ? MXC_PMU4 : \
Anna Bridge 169:a7c7b631e539 287 (i) == 5 ? MXC_PMU5 : 0)
Anna Bridge 169:a7c7b631e539 288
Anna Bridge 169:a7c7b631e539 289 #define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \
Anna Bridge 169:a7c7b631e539 290 (p) == MXC_PMU1 ? 1 : \
Anna Bridge 169:a7c7b631e539 291 (p) == MXC_PMU2 ? 2 : \
Anna Bridge 169:a7c7b631e539 292 (p) == MXC_PMU3 ? 3 : \
Anna Bridge 169:a7c7b631e539 293 (p) == MXC_PMU4 ? 4 : \
Anna Bridge 169:a7c7b631e539 294 (p) == MXC_PMU5 ? 5 : -1)
Anna Bridge 169:a7c7b631e539 295
Anna Bridge 169:a7c7b631e539 296
Anna Bridge 169:a7c7b631e539 297 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 298 /* USB Device Controller */
Anna Bridge 169:a7c7b631e539 299
Anna Bridge 169:a7c7b631e539 300 #define MXC_BASE_USB ((uint32_t)0x40100000UL)
Anna Bridge 169:a7c7b631e539 301 #define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
Anna Bridge 169:a7c7b631e539 302
Anna Bridge 169:a7c7b631e539 303 #define MXC_USB_MAX_PACKET (64)
Anna Bridge 169:a7c7b631e539 304 #define MXC_USB_NUM_EP (8)
Anna Bridge 169:a7c7b631e539 305
Anna Bridge 169:a7c7b631e539 306
Anna Bridge 169:a7c7b631e539 307
Anna Bridge 169:a7c7b631e539 308 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 309 /* CRC-16/CRC-32 Engine */
Anna Bridge 169:a7c7b631e539 310
Anna Bridge 169:a7c7b631e539 311 #define MXC_BASE_CRC ((uint32_t)0x40006000UL)
Anna Bridge 169:a7c7b631e539 312 #define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
Anna Bridge 169:a7c7b631e539 313 #define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL)
Anna Bridge 169:a7c7b631e539 314 #define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
Anna Bridge 169:a7c7b631e539 315
Anna Bridge 169:a7c7b631e539 316
Anna Bridge 169:a7c7b631e539 317
Anna Bridge 169:a7c7b631e539 318 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 319 /* Pseudo-random number generator (PRNG) */
Anna Bridge 169:a7c7b631e539 320
Anna Bridge 169:a7c7b631e539 321 #define MXC_BASE_PRNG ((uint32_t)0x40007000UL)
Anna Bridge 169:a7c7b631e539 322 #define MXC_PRNG ((mxc_prng_regs_t *)MXC_BASE_PRNG)
Anna Bridge 169:a7c7b631e539 323
Anna Bridge 169:a7c7b631e539 324 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 325 /* AES Cryptographic Engine */
Anna Bridge 169:a7c7b631e539 326
Anna Bridge 169:a7c7b631e539 327 #define MXC_BASE_AES ((uint32_t)0x40007400UL)
Anna Bridge 169:a7c7b631e539 328 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
Anna Bridge 169:a7c7b631e539 329 #define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL)
Anna Bridge 169:a7c7b631e539 330 #define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
Anna Bridge 169:a7c7b631e539 331
Anna Bridge 169:a7c7b631e539 332
Anna Bridge 169:a7c7b631e539 333
Anna Bridge 169:a7c7b631e539 334 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 335 /* MAA Cryptographic Engine */
Anna Bridge 169:a7c7b631e539 336
Anna Bridge 169:a7c7b631e539 337 #define MXC_BASE_MAA ((uint32_t)0x40007800UL)
Anna Bridge 169:a7c7b631e539 338 #define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
Anna Bridge 169:a7c7b631e539 339 #define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL)
Anna Bridge 169:a7c7b631e539 340 #define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
Anna Bridge 169:a7c7b631e539 341
Anna Bridge 169:a7c7b631e539 342 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 343 /* Trust Protection Unit (TPU) */
Anna Bridge 169:a7c7b631e539 344
Anna Bridge 169:a7c7b631e539 345 #define MXC_BASE_TPU ((uint32_t)0x40007000UL)
Anna Bridge 169:a7c7b631e539 346 #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
Anna Bridge 169:a7c7b631e539 347 #define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL)
Anna Bridge 169:a7c7b631e539 348 #define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
Anna Bridge 169:a7c7b631e539 349
Anna Bridge 169:a7c7b631e539 350 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 351 /* Watchdog Timers */
Anna Bridge 169:a7c7b631e539 352
Anna Bridge 169:a7c7b631e539 353 #define MXC_CFG_WDT_INSTANCES (2)
Anna Bridge 169:a7c7b631e539 354
Anna Bridge 169:a7c7b631e539 355 #define MXC_BASE_WDT0 ((uint32_t)0x40008000UL)
Anna Bridge 169:a7c7b631e539 356 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
Anna Bridge 169:a7c7b631e539 357 #define MXC_BASE_WDT1 ((uint32_t)0x40009000UL)
Anna Bridge 169:a7c7b631e539 358 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
Anna Bridge 169:a7c7b631e539 359
Anna Bridge 169:a7c7b631e539 360 #define MXC_WDT_GET_IRQ(i) (IRQn_Type)((i) == 0 ? WDT0_IRQn : \
Anna Bridge 169:a7c7b631e539 361 (i) == 1 ? WDT1_IRQn : 0)
Anna Bridge 169:a7c7b631e539 362
Anna Bridge 169:a7c7b631e539 363 #define MXC_WDT_GET_IRQ_P(i) (IRQn_Type)((i) == 0 ? WDT0_P_IRQn : \
Anna Bridge 169:a7c7b631e539 364 (i) == 1 ? WDT1_P_IRQn : 0)
Anna Bridge 169:a7c7b631e539 365
Anna Bridge 169:a7c7b631e539 366 #define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
Anna Bridge 169:a7c7b631e539 367 (i) == 1 ? MXC_BASE_WDT1 : 0)
Anna Bridge 169:a7c7b631e539 368
Anna Bridge 169:a7c7b631e539 369 #define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
Anna Bridge 169:a7c7b631e539 370 (i) == 1 ? MXC_WDT1 : 0)
Anna Bridge 169:a7c7b631e539 371
Anna Bridge 169:a7c7b631e539 372 #define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: \
Anna Bridge 169:a7c7b631e539 373 (i) == MXC_WDT1 ? 1: -1)
Anna Bridge 169:a7c7b631e539 374
Anna Bridge 169:a7c7b631e539 375
Anna Bridge 169:a7c7b631e539 376 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 377 /* Low-Level Watchdog Timer */
Anna Bridge 169:a7c7b631e539 378
Anna Bridge 169:a7c7b631e539 379 #define MXC_BASE_WDT2 ((uint32_t)0x40007C60UL)
Anna Bridge 169:a7c7b631e539 380 #define MXC_WDT2 ((mxc_wdt2_regs_t *)MXC_BASE_WDT2)
Anna Bridge 169:a7c7b631e539 381
Anna Bridge 169:a7c7b631e539 382
Anna Bridge 169:a7c7b631e539 383
Anna Bridge 169:a7c7b631e539 384 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 385 /* General Purpose I/O Ports (GPIO) */
Anna Bridge 169:a7c7b631e539 386
Anna Bridge 169:a7c7b631e539 387 #define MXC_GPIO_NUM_PORTS (5)
Anna Bridge 169:a7c7b631e539 388 #define MXC_GPIO_MAX_PINS_PER_PORT (8)
Anna Bridge 169:a7c7b631e539 389
Anna Bridge 169:a7c7b631e539 390 #define MXC_BASE_GPIO ((uint32_t)0x4000A000UL)
Anna Bridge 169:a7c7b631e539 391 #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
Anna Bridge 169:a7c7b631e539 392
Anna Bridge 169:a7c7b631e539 393 #define MXC_GPIO_GET_IRQ(i) (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn : \
Anna Bridge 169:a7c7b631e539 394 (i) == 1 ? GPIO_P1_IRQn : \
Anna Bridge 169:a7c7b631e539 395 (i) == 2 ? GPIO_P2_IRQn : \
Anna Bridge 169:a7c7b631e539 396 (i) == 3 ? GPIO_P3_IRQn : \
Anna Bridge 169:a7c7b631e539 397 (i) == 4 ? GPIO_P4_IRQn : 0)
Anna Bridge 169:a7c7b631e539 398
Anna Bridge 169:a7c7b631e539 399
Anna Bridge 169:a7c7b631e539 400
Anna Bridge 169:a7c7b631e539 401 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 402 /* 16/32 bit Timer/Counters */
Anna Bridge 169:a7c7b631e539 403
Anna Bridge 169:a7c7b631e539 404 #define MXC_CFG_TMR_INSTANCES (6)
Anna Bridge 169:a7c7b631e539 405
Anna Bridge 169:a7c7b631e539 406 #define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL)
Anna Bridge 169:a7c7b631e539 407 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
Anna Bridge 169:a7c7b631e539 408 #define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL)
Anna Bridge 169:a7c7b631e539 409 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
Anna Bridge 169:a7c7b631e539 410 #define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL)
Anna Bridge 169:a7c7b631e539 411 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
Anna Bridge 169:a7c7b631e539 412 #define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL)
Anna Bridge 169:a7c7b631e539 413 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
Anna Bridge 169:a7c7b631e539 414 #define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL)
Anna Bridge 169:a7c7b631e539 415 #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
Anna Bridge 169:a7c7b631e539 416 #define MXC_BASE_TMR5 ((uint32_t)0x40010000UL)
Anna Bridge 169:a7c7b631e539 417 #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
Anna Bridge 169:a7c7b631e539 418
Anna Bridge 169:a7c7b631e539 419 #define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
Anna Bridge 169:a7c7b631e539 420 (i) == 1 ? TMR1_0_IRQn : \
Anna Bridge 169:a7c7b631e539 421 (i) == 2 ? TMR2_0_IRQn : \
Anna Bridge 169:a7c7b631e539 422 (i) == 3 ? TMR3_0_IRQn : \
Anna Bridge 169:a7c7b631e539 423 (i) == 4 ? TMR4_0_IRQn : \
Anna Bridge 169:a7c7b631e539 424 (i) == 5 ? TMR5_0_IRQn : 0)
Anna Bridge 169:a7c7b631e539 425
Anna Bridge 169:a7c7b631e539 426 #define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
Anna Bridge 169:a7c7b631e539 427 (i) == 1 ? TMR1_0_IRQn : \
Anna Bridge 169:a7c7b631e539 428 (i) == 2 ? TMR2_0_IRQn : \
Anna Bridge 169:a7c7b631e539 429 (i) == 3 ? TMR3_0_IRQn : \
Anna Bridge 169:a7c7b631e539 430 (i) == 4 ? TMR4_0_IRQn : \
Anna Bridge 169:a7c7b631e539 431 (i) == 5 ? TMR5_0_IRQn : \
Anna Bridge 169:a7c7b631e539 432 (i) == 6 ? TMR0_1_IRQn : \
Anna Bridge 169:a7c7b631e539 433 (i) == 7 ? TMR1_1_IRQn : \
Anna Bridge 169:a7c7b631e539 434 (i) == 8 ? TMR2_1_IRQn : \
Anna Bridge 169:a7c7b631e539 435 (i) == 9 ? TMR3_1_IRQn : \
Anna Bridge 169:a7c7b631e539 436 (i) == 10 ? TMR4_1_IRQn : \
Anna Bridge 169:a7c7b631e539 437 (i) == 11 ? TMR5_1_IRQn : 0)
Anna Bridge 169:a7c7b631e539 438
Anna Bridge 169:a7c7b631e539 439 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
Anna Bridge 169:a7c7b631e539 440 (i) == 1 ? MXC_BASE_TMR1 : \
Anna Bridge 169:a7c7b631e539 441 (i) == 2 ? MXC_BASE_TMR2 : \
Anna Bridge 169:a7c7b631e539 442 (i) == 3 ? MXC_BASE_TMR3 : \
Anna Bridge 169:a7c7b631e539 443 (i) == 4 ? MXC_BASE_TMR4 : \
Anna Bridge 169:a7c7b631e539 444 (i) == 5 ? MXC_BASE_TMR5 : 0)
Anna Bridge 169:a7c7b631e539 445
Anna Bridge 169:a7c7b631e539 446 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
Anna Bridge 169:a7c7b631e539 447 (i) == 1 ? MXC_TMR1 : \
Anna Bridge 169:a7c7b631e539 448 (i) == 2 ? MXC_TMR2 : \
Anna Bridge 169:a7c7b631e539 449 (i) == 3 ? MXC_TMR3 : \
Anna Bridge 169:a7c7b631e539 450 (i) == 4 ? MXC_TMR4 : \
Anna Bridge 169:a7c7b631e539 451 (i) == 5 ? MXC_TMR5 : 0)
Anna Bridge 169:a7c7b631e539 452
Anna Bridge 169:a7c7b631e539 453 #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
Anna Bridge 169:a7c7b631e539 454 (p) == MXC_TMR1 ? 1 : \
Anna Bridge 169:a7c7b631e539 455 (p) == MXC_TMR2 ? 2 : \
Anna Bridge 169:a7c7b631e539 456 (p) == MXC_TMR3 ? 3 : \
Anna Bridge 169:a7c7b631e539 457 (p) == MXC_TMR4 ? 4 : \
Anna Bridge 169:a7c7b631e539 458 (p) == MXC_TMR5 ? 5 : -1)
Anna Bridge 169:a7c7b631e539 459
Anna Bridge 169:a7c7b631e539 460
Anna Bridge 169:a7c7b631e539 461
Anna Bridge 169:a7c7b631e539 462
Anna Bridge 169:a7c7b631e539 463 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 464 /* Pulse Train Generation */
Anna Bridge 169:a7c7b631e539 465
Anna Bridge 169:a7c7b631e539 466 #define MXC_CFG_PT_INSTANCES (16)
Anna Bridge 169:a7c7b631e539 467
Anna Bridge 169:a7c7b631e539 468 #define MXC_BASE_PTG ((uint32_t)0x40011000UL)
Anna Bridge 169:a7c7b631e539 469 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
Anna Bridge 169:a7c7b631e539 470 #define MXC_BASE_PT0 ((uint32_t)0x40011020UL)
Anna Bridge 169:a7c7b631e539 471 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
Anna Bridge 169:a7c7b631e539 472 #define MXC_BASE_PT1 ((uint32_t)0x40011040UL)
Anna Bridge 169:a7c7b631e539 473 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
Anna Bridge 169:a7c7b631e539 474 #define MXC_BASE_PT2 ((uint32_t)0x40011060UL)
Anna Bridge 169:a7c7b631e539 475 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
Anna Bridge 169:a7c7b631e539 476 #define MXC_BASE_PT3 ((uint32_t)0x40011080UL)
Anna Bridge 169:a7c7b631e539 477 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
Anna Bridge 169:a7c7b631e539 478 #define MXC_BASE_PT4 ((uint32_t)0x400110A0UL)
Anna Bridge 169:a7c7b631e539 479 #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
Anna Bridge 169:a7c7b631e539 480 #define MXC_BASE_PT5 ((uint32_t)0x400110C0UL)
Anna Bridge 169:a7c7b631e539 481 #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
Anna Bridge 169:a7c7b631e539 482 #define MXC_BASE_PT6 ((uint32_t)0x400110E0UL)
Anna Bridge 169:a7c7b631e539 483 #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
Anna Bridge 169:a7c7b631e539 484 #define MXC_BASE_PT7 ((uint32_t)0x40011100UL)
Anna Bridge 169:a7c7b631e539 485 #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
Anna Bridge 169:a7c7b631e539 486 #define MXC_BASE_PT8 ((uint32_t)0x40011120UL)
Anna Bridge 169:a7c7b631e539 487 #define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
Anna Bridge 169:a7c7b631e539 488 #define MXC_BASE_PT9 ((uint32_t)0x40011140UL)
Anna Bridge 169:a7c7b631e539 489 #define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
Anna Bridge 169:a7c7b631e539 490 #define MXC_BASE_PT10 ((uint32_t)0x40011160UL)
Anna Bridge 169:a7c7b631e539 491 #define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
Anna Bridge 169:a7c7b631e539 492 #define MXC_BASE_PT11 ((uint32_t)0x40011180UL)
Anna Bridge 169:a7c7b631e539 493 #define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
Anna Bridge 169:a7c7b631e539 494 #define MXC_BASE_PT12 ((uint32_t)0x400111A0UL)
Anna Bridge 169:a7c7b631e539 495 #define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12)
Anna Bridge 169:a7c7b631e539 496 #define MXC_BASE_PT13 ((uint32_t)0x400111C0UL)
Anna Bridge 169:a7c7b631e539 497 #define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13)
Anna Bridge 169:a7c7b631e539 498 #define MXC_BASE_PT14 ((uint32_t)0x400111E0UL)
Anna Bridge 169:a7c7b631e539 499 #define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14)
Anna Bridge 169:a7c7b631e539 500 #define MXC_BASE_PT15 ((uint32_t)0x40011200UL)
Anna Bridge 169:a7c7b631e539 501 #define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15)
Anna Bridge 169:a7c7b631e539 502
Anna Bridge 169:a7c7b631e539 503 #define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \
Anna Bridge 169:a7c7b631e539 504 (i) == 1 ? MXC_BASE_PT1 : \
Anna Bridge 169:a7c7b631e539 505 (i) == 2 ? MXC_BASE_PT2 : \
Anna Bridge 169:a7c7b631e539 506 (i) == 3 ? MXC_BASE_PT3 : \
Anna Bridge 169:a7c7b631e539 507 (i) == 4 ? MXC_BASE_PT4 : \
Anna Bridge 169:a7c7b631e539 508 (i) == 5 ? MXC_BASE_PT5 : \
Anna Bridge 169:a7c7b631e539 509 (i) == 6 ? MXC_BASE_PT6 : \
Anna Bridge 169:a7c7b631e539 510 (i) == 7 ? MXC_BASE_PT7 : \
Anna Bridge 169:a7c7b631e539 511 (i) == 8 ? MXC_BASE_PT8 : \
Anna Bridge 169:a7c7b631e539 512 (i) == 9 ? MXC_BASE_PT9 : \
Anna Bridge 169:a7c7b631e539 513 (i) == 10 ? MXC_BASE_PT10 : \
Anna Bridge 169:a7c7b631e539 514 (i) == 11 ? MXC_BASE_PT11 : \
Anna Bridge 169:a7c7b631e539 515 (i) == 12 ? MXC_BASE_PT12 : \
Anna Bridge 169:a7c7b631e539 516 (i) == 13 ? MXC_BASE_PT13 : \
Anna Bridge 169:a7c7b631e539 517 (i) == 14 ? MXC_BASE_PT14 : \
Anna Bridge 169:a7c7b631e539 518 (i) == 15 ? MXC_BASE_PT15 : 0)
Anna Bridge 169:a7c7b631e539 519
Anna Bridge 169:a7c7b631e539 520 #define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \
Anna Bridge 169:a7c7b631e539 521 (i) == 1 ? MXC_PT1 : \
Anna Bridge 169:a7c7b631e539 522 (i) == 2 ? MXC_PT2 : \
Anna Bridge 169:a7c7b631e539 523 (i) == 3 ? MXC_PT3 : \
Anna Bridge 169:a7c7b631e539 524 (i) == 4 ? MXC_PT4 : \
Anna Bridge 169:a7c7b631e539 525 (i) == 5 ? MXC_PT5 : \
Anna Bridge 169:a7c7b631e539 526 (i) == 6 ? MXC_PT6 : \
Anna Bridge 169:a7c7b631e539 527 (i) == 7 ? MXC_PT7 : \
Anna Bridge 169:a7c7b631e539 528 (i) == 8 ? MXC_PT8 : \
Anna Bridge 169:a7c7b631e539 529 (i) == 9 ? MXC_PT9 : \
Anna Bridge 169:a7c7b631e539 530 (i) == 10 ? MXC_PT10 : \
Anna Bridge 169:a7c7b631e539 531 (i) == 11 ? MXC_PT11 : \
Anna Bridge 169:a7c7b631e539 532 (i) == 12 ? MXC_PT12 : \
Anna Bridge 169:a7c7b631e539 533 (i) == 13 ? MXC_PT13 : \
Anna Bridge 169:a7c7b631e539 534 (i) == 14 ? MXC_PT14 : \
Anna Bridge 169:a7c7b631e539 535 (i) == 15 ? MXC_PT15 : 0)
Anna Bridge 169:a7c7b631e539 536
Anna Bridge 169:a7c7b631e539 537 #define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \
Anna Bridge 169:a7c7b631e539 538 (p) == MXC_PT1 ? 1 : \
Anna Bridge 169:a7c7b631e539 539 (p) == MXC_PT2 ? 2 : \
Anna Bridge 169:a7c7b631e539 540 (p) == MXC_PT3 ? 3 : \
Anna Bridge 169:a7c7b631e539 541 (p) == MXC_PT4 ? 4 : \
Anna Bridge 169:a7c7b631e539 542 (p) == MXC_PT5 ? 5 : \
Anna Bridge 169:a7c7b631e539 543 (p) == MXC_PT6 ? 6 : \
Anna Bridge 169:a7c7b631e539 544 (p) == MXC_PT7 ? 7 : \
Anna Bridge 169:a7c7b631e539 545 (p) == MXC_PT8 ? 8 : \
Anna Bridge 169:a7c7b631e539 546 (p) == MXC_PT9 ? 9 : \
Anna Bridge 169:a7c7b631e539 547 (p) == MXC_PT10 ? 10 : \
Anna Bridge 169:a7c7b631e539 548 (p) == MXC_PT11 ? 11 : \
Anna Bridge 169:a7c7b631e539 549 (p) == MXC_PT12 ? 12 : \
Anna Bridge 169:a7c7b631e539 550 (p) == MXC_PT13 ? 13 : \
Anna Bridge 169:a7c7b631e539 551 (p) == MXC_PT14 ? 14 : \
Anna Bridge 169:a7c7b631e539 552 (p) == MXC_PT15 ? 15 : -1)
Anna Bridge 169:a7c7b631e539 553
Anna Bridge 169:a7c7b631e539 554
Anna Bridge 169:a7c7b631e539 555
Anna Bridge 169:a7c7b631e539 556 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 557 /* UART / Serial Port Interface */
Anna Bridge 169:a7c7b631e539 558
Anna Bridge 169:a7c7b631e539 559 #define MXC_CFG_UART_INSTANCES (3)
Anna Bridge 169:a7c7b631e539 560 #define MXC_UART_FIFO_DEPTH (32)
Anna Bridge 169:a7c7b631e539 561
Anna Bridge 169:a7c7b631e539 562 #define MXC_BASE_UART0 ((uint32_t)0x40012000UL)
Anna Bridge 169:a7c7b631e539 563 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
Anna Bridge 169:a7c7b631e539 564 #define MXC_BASE_UART1 ((uint32_t)0x40013000UL)
Anna Bridge 169:a7c7b631e539 565 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
Anna Bridge 169:a7c7b631e539 566 #define MXC_BASE_UART2 ((uint32_t)0x40014000UL)
Anna Bridge 169:a7c7b631e539 567 #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
Anna Bridge 169:a7c7b631e539 568 #define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL)
Anna Bridge 169:a7c7b631e539 569 #define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO)
Anna Bridge 169:a7c7b631e539 570 #define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL)
Anna Bridge 169:a7c7b631e539 571 #define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO)
Anna Bridge 169:a7c7b631e539 572 #define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL)
Anna Bridge 169:a7c7b631e539 573 #define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO)
Anna Bridge 169:a7c7b631e539 574
Anna Bridge 169:a7c7b631e539 575 #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
Anna Bridge 169:a7c7b631e539 576 (i) == 1 ? UART1_IRQn : \
Anna Bridge 169:a7c7b631e539 577 (i) == 2 ? UART2_IRQn : 0)
Anna Bridge 169:a7c7b631e539 578
Anna Bridge 169:a7c7b631e539 579 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
Anna Bridge 169:a7c7b631e539 580 (i) == 1 ? MXC_BASE_UART1 : \
Anna Bridge 169:a7c7b631e539 581 (i) == 2 ? MXC_BASE_UART2 : 0)
Anna Bridge 169:a7c7b631e539 582
Anna Bridge 169:a7c7b631e539 583 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
Anna Bridge 169:a7c7b631e539 584 (i) == 1 ? MXC_UART1 : \
Anna Bridge 169:a7c7b631e539 585 (i) == 2 ? MXC_UART2 : 0)
Anna Bridge 169:a7c7b631e539 586
Anna Bridge 169:a7c7b631e539 587 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
Anna Bridge 169:a7c7b631e539 588 (p) == MXC_UART1 ? 1 : \
Anna Bridge 169:a7c7b631e539 589 (p) == MXC_UART2 ? 2 : -1)
Anna Bridge 169:a7c7b631e539 590
Anna Bridge 169:a7c7b631e539 591 #define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \
Anna Bridge 169:a7c7b631e539 592 (i) == 1 ? MXC_BASE_UART1_FIFO : \
Anna Bridge 169:a7c7b631e539 593 (i) == 2 ? MXC_BASE_UART2_FIFO : 0)
Anna Bridge 169:a7c7b631e539 594
Anna Bridge 169:a7c7b631e539 595 #define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \
Anna Bridge 169:a7c7b631e539 596 (i) == 1 ? MXC_UART1_FIFO : \
Anna Bridge 169:a7c7b631e539 597 (i) == 2 ? MXC_UART2_FIFO : 0)
Anna Bridge 169:a7c7b631e539 598
Anna Bridge 169:a7c7b631e539 599
Anna Bridge 169:a7c7b631e539 600
Anna Bridge 169:a7c7b631e539 601 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 602 /* I2C Master Interface */
Anna Bridge 169:a7c7b631e539 603
Anna Bridge 169:a7c7b631e539 604 #define MXC_CFG_I2CM_INSTANCES (2)
Anna Bridge 169:a7c7b631e539 605 #define MXC_I2CM_FIFO_DEPTH (8)
Anna Bridge 169:a7c7b631e539 606
Anna Bridge 169:a7c7b631e539 607 #define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL)
Anna Bridge 169:a7c7b631e539 608 #define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
Anna Bridge 169:a7c7b631e539 609 #define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL)
Anna Bridge 169:a7c7b631e539 610 #define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
Anna Bridge 169:a7c7b631e539 611 #define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL)
Anna Bridge 169:a7c7b631e539 612 #define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO)
Anna Bridge 169:a7c7b631e539 613 #define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL)
Anna Bridge 169:a7c7b631e539 614 #define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO)
Anna Bridge 169:a7c7b631e539 615
Anna Bridge 169:a7c7b631e539 616 #define MXC_I2CM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CM0_IRQn : \
Anna Bridge 169:a7c7b631e539 617 (i) == 1 ? I2CM1_IRQn : 0)
Anna Bridge 169:a7c7b631e539 618
Anna Bridge 169:a7c7b631e539 619 #define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
Anna Bridge 169:a7c7b631e539 620 (i) == 1 ? MXC_BASE_I2CM1 : 0)
Anna Bridge 169:a7c7b631e539 621
Anna Bridge 169:a7c7b631e539 622 #define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
Anna Bridge 169:a7c7b631e539 623 (i) == 1 ? MXC_I2CM1 : 0)
Anna Bridge 169:a7c7b631e539 624
Anna Bridge 169:a7c7b631e539 625 #define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \
Anna Bridge 169:a7c7b631e539 626 (p) == MXC_I2CM1 ? 1 : -1)
Anna Bridge 169:a7c7b631e539 627
Anna Bridge 169:a7c7b631e539 628 #define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \
Anna Bridge 169:a7c7b631e539 629 (i) == 1 ? MXC_BASE_I2CM1_FIFO : 0)
Anna Bridge 169:a7c7b631e539 630
Anna Bridge 169:a7c7b631e539 631 #define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \
Anna Bridge 169:a7c7b631e539 632 (i) == 1 ? MXC_I2CM1_FIFO : 0)
Anna Bridge 169:a7c7b631e539 633
Anna Bridge 169:a7c7b631e539 634
Anna Bridge 169:a7c7b631e539 635
Anna Bridge 169:a7c7b631e539 636 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 637 /* I2C Slave Interface (Mailbox type) */
Anna Bridge 169:a7c7b631e539 638
Anna Bridge 169:a7c7b631e539 639 #define MXC_CFG_I2CS_INSTANCES (1)
Anna Bridge 169:a7c7b631e539 640 #define MXC_CFG_I2CS_BUFFER_SIZE (32)
Anna Bridge 169:a7c7b631e539 641
Anna Bridge 169:a7c7b631e539 642 #define MXC_BASE_I2CS ((uint32_t)0x40019000UL)
Anna Bridge 169:a7c7b631e539 643 #define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS)
Anna Bridge 169:a7c7b631e539 644
Anna Bridge 169:a7c7b631e539 645 #define MXC_I2CS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0)
Anna Bridge 169:a7c7b631e539 646
Anna Bridge 169:a7c7b631e539 647 #define MXC_I2CS_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CS : 0)
Anna Bridge 169:a7c7b631e539 648
Anna Bridge 169:a7c7b631e539 649 #define MXC_I2CS_GET_I2CS(i) ((i) == 0 ? MXC_I2CS : 0)
Anna Bridge 169:a7c7b631e539 650
Anna Bridge 169:a7c7b631e539 651 #define MXC_I2CS_GET_IDX(p) ((p) == MXC_I2CS ? 0 : -1)
Anna Bridge 169:a7c7b631e539 652
Anna Bridge 169:a7c7b631e539 653 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 654 /* SPI Master Interface */
Anna Bridge 169:a7c7b631e539 655
Anna Bridge 169:a7c7b631e539 656 #define MXC_CFG_SPIM_INSTANCES (3)
Anna Bridge 169:a7c7b631e539 657 #define MXC_CFG_SPIM_FIFO_DEPTH (16)
Anna Bridge 169:a7c7b631e539 658
Anna Bridge 169:a7c7b631e539 659 #define MXC_BASE_SPIM0 ((uint32_t)0x4001A000UL)
Anna Bridge 169:a7c7b631e539 660 #define MXC_SPIM0 ((mxc_spim_regs_t *)MXC_BASE_SPIM0)
Anna Bridge 169:a7c7b631e539 661 #define MXC_BASE_SPIM1 ((uint32_t)0x4001B000UL)
Anna Bridge 169:a7c7b631e539 662 #define MXC_SPIM1 ((mxc_spim_regs_t *)MXC_BASE_SPIM1)
Anna Bridge 169:a7c7b631e539 663 #define MXC_BASE_SPIM2 ((uint32_t)0x4001C000UL)
Anna Bridge 169:a7c7b631e539 664 #define MXC_SPIM2 ((mxc_spim_regs_t *)MXC_BASE_SPIM2)
Anna Bridge 169:a7c7b631e539 665 #define MXC_BASE_SPIM0_FIFO ((uint32_t)0x4010A000UL)
Anna Bridge 169:a7c7b631e539 666 #define MXC_SPIM0_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO)
Anna Bridge 169:a7c7b631e539 667 #define MXC_BASE_SPIM1_FIFO ((uint32_t)0x4010B000UL)
Anna Bridge 169:a7c7b631e539 668 #define MXC_SPIM1_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO)
Anna Bridge 169:a7c7b631e539 669 #define MXC_BASE_SPIM2_FIFO ((uint32_t)0x4010C000UL)
Anna Bridge 169:a7c7b631e539 670 #define MXC_SPIM2_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO)
Anna Bridge 169:a7c7b631e539 671
Anna Bridge 169:a7c7b631e539 672 #define MXC_SPIM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIM0_IRQn : \
Anna Bridge 169:a7c7b631e539 673 (i) == 1 ? SPIM1_IRQn : \
Anna Bridge 169:a7c7b631e539 674 (i) == 2 ? SPIM2_IRQn : 0)
Anna Bridge 169:a7c7b631e539 675
Anna Bridge 169:a7c7b631e539 676 #define MXC_SPIM_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIM0 : \
Anna Bridge 169:a7c7b631e539 677 (i) == 1 ? MXC_BASE_SPIM1 : \
Anna Bridge 169:a7c7b631e539 678 (i) == 2 ? MXC_BASE_SPIM2 : 0)
Anna Bridge 169:a7c7b631e539 679
Anna Bridge 169:a7c7b631e539 680 #define MXC_SPIM_GET_SPIM(i) ((i) == 0 ? MXC_SPIM0 : \
Anna Bridge 169:a7c7b631e539 681 (i) == 1 ? MXC_SPIM1 : \
Anna Bridge 169:a7c7b631e539 682 (i) == 2 ? MXC_SPIM2 : 0)
Anna Bridge 169:a7c7b631e539 683
Anna Bridge 169:a7c7b631e539 684 #define MXC_SPIM_GET_IDX(p) ((p) == MXC_SPIM0 ? 0 : \
Anna Bridge 169:a7c7b631e539 685 (p) == MXC_SPIM1 ? 1 : \
Anna Bridge 169:a7c7b631e539 686 (p) == MXC_SPIM2 ? 2 : -1)
Anna Bridge 169:a7c7b631e539 687
Anna Bridge 169:a7c7b631e539 688 #define MXC_SPIM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIM0_FIFO : \
Anna Bridge 169:a7c7b631e539 689 (i) == 1 ? MXC_BASE_SPIM1_FIFO : \
Anna Bridge 169:a7c7b631e539 690 (i) == 2 ? MXC_BASE_SPIM2_FIFO : 0)
Anna Bridge 169:a7c7b631e539 691
Anna Bridge 169:a7c7b631e539 692 #define MXC_SPIM_GET_SPIM_FIFO(i) ((i) == 0 ? MXC_SPIM0_FIFO : \
Anna Bridge 169:a7c7b631e539 693 (i) == 1 ? MXC_SPIM1_FIFO : \
Anna Bridge 169:a7c7b631e539 694 (i) == 2 ? MXC_SPIM2_FIFO : 0)
Anna Bridge 169:a7c7b631e539 695
Anna Bridge 169:a7c7b631e539 696
Anna Bridge 169:a7c7b631e539 697
Anna Bridge 169:a7c7b631e539 698 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 699 /* 1-Wire Master Interface */
Anna Bridge 169:a7c7b631e539 700
Anna Bridge 169:a7c7b631e539 701 #define MXC_CFG_OWM_INSTANCES (1)
Anna Bridge 169:a7c7b631e539 702
Anna Bridge 169:a7c7b631e539 703 #define MXC_BASE_OWM ((uint32_t)0x4001E000UL)
Anna Bridge 169:a7c7b631e539 704 #define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
Anna Bridge 169:a7c7b631e539 705
Anna Bridge 169:a7c7b631e539 706 #define MXC_OWM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? OWM_IRQn : 0)
Anna Bridge 169:a7c7b631e539 707
Anna Bridge 169:a7c7b631e539 708 #define MXC_OWM_GET_BASE(i) ((i) == 0 ? MXC_BASE_OWM : 0)
Anna Bridge 169:a7c7b631e539 709
Anna Bridge 169:a7c7b631e539 710 #define MXC_OWM_GET_OWM(i) ((i) == 0 ? MXC_OWM : 0)
Anna Bridge 169:a7c7b631e539 711
Anna Bridge 169:a7c7b631e539 712 #define MXC_OWM_GET_IDX(p) ((p) == MXC_OWM ? 0 : -1)
Anna Bridge 169:a7c7b631e539 713
Anna Bridge 169:a7c7b631e539 714 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 715 /* ADC / AFE */
Anna Bridge 169:a7c7b631e539 716
Anna Bridge 169:a7c7b631e539 717 #define MXC_CFG_ADC_FIFO_DEPTH (32)
Anna Bridge 169:a7c7b631e539 718
Anna Bridge 169:a7c7b631e539 719 #define MXC_BASE_ADC ((uint32_t)0x4001F000UL)
Anna Bridge 169:a7c7b631e539 720 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
Anna Bridge 169:a7c7b631e539 721
Anna Bridge 169:a7c7b631e539 722
Anna Bridge 169:a7c7b631e539 723
Anna Bridge 169:a7c7b631e539 724 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 725 /* SPI Slave Interface */
Anna Bridge 169:a7c7b631e539 726 #define MXC_CFG_SPIS_INSTANCES (1)
Anna Bridge 169:a7c7b631e539 727 #define MXC_CFG_SPIS_FIFO_DEPTH (32)
Anna Bridge 169:a7c7b631e539 728
Anna Bridge 169:a7c7b631e539 729 #define MXC_BASE_SPIS ((uint32_t)0x40020000UL)
Anna Bridge 169:a7c7b631e539 730 #define MXC_SPIS ((mxc_spis_regs_t *)MXC_BASE_SPIS)
Anna Bridge 169:a7c7b631e539 731 #define MXC_BASE_SPIS_FIFO ((uint32_t)0x4010E000UL)
Anna Bridge 169:a7c7b631e539 732 #define MXC_SPIS_FIFO ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO)
Anna Bridge 169:a7c7b631e539 733
Anna Bridge 169:a7c7b631e539 734 #define MXC_SPIS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIS_IRQn : 0)
Anna Bridge 169:a7c7b631e539 735
Anna Bridge 169:a7c7b631e539 736 #define MXC_SPIS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIS : 0)
Anna Bridge 169:a7c7b631e539 737
Anna Bridge 169:a7c7b631e539 738 #define MXC_SPIS_GET_SPIS(i) ((i) == 0 ? MXC_SPIS : 0)
Anna Bridge 169:a7c7b631e539 739
Anna Bridge 169:a7c7b631e539 740 #define MXC_SPIS_GET_IDX(p) ((p) == MXC_SPIS ? 0 : -1)
Anna Bridge 169:a7c7b631e539 741
Anna Bridge 169:a7c7b631e539 742 #define MXC_SPIS_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIS_FIFO : 0)
Anna Bridge 169:a7c7b631e539 743
Anna Bridge 169:a7c7b631e539 744 #define MXC_SPIS_GET_SPIS_FIFO(i) ((i) == 0 ? MXC_SPIS_FIFO :0)
Anna Bridge 169:a7c7b631e539 745
Anna Bridge 169:a7c7b631e539 746 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 747 /* Bit Shifting */
Anna Bridge 169:a7c7b631e539 748
Anna Bridge 169:a7c7b631e539 749 #define MXC_F_BIT_0 (1 << 0)
Anna Bridge 169:a7c7b631e539 750 #define MXC_F_BIT_1 (1 << 1)
Anna Bridge 169:a7c7b631e539 751 #define MXC_F_BIT_2 (1 << 2)
Anna Bridge 169:a7c7b631e539 752 #define MXC_F_BIT_3 (1 << 3)
Anna Bridge 169:a7c7b631e539 753 #define MXC_F_BIT_4 (1 << 4)
Anna Bridge 169:a7c7b631e539 754 #define MXC_F_BIT_5 (1 << 5)
Anna Bridge 169:a7c7b631e539 755 #define MXC_F_BIT_6 (1 << 6)
Anna Bridge 169:a7c7b631e539 756 #define MXC_F_BIT_7 (1 << 7)
Anna Bridge 169:a7c7b631e539 757 #define MXC_F_BIT_8 (1 << 8)
Anna Bridge 169:a7c7b631e539 758 #define MXC_F_BIT_9 (1 << 9)
Anna Bridge 169:a7c7b631e539 759 #define MXC_F_BIT_10 (1 << 10)
Anna Bridge 169:a7c7b631e539 760 #define MXC_F_BIT_11 (1 << 11)
Anna Bridge 169:a7c7b631e539 761 #define MXC_F_BIT_12 (1 << 12)
Anna Bridge 169:a7c7b631e539 762 #define MXC_F_BIT_13 (1 << 13)
Anna Bridge 169:a7c7b631e539 763 #define MXC_F_BIT_14 (1 << 14)
Anna Bridge 169:a7c7b631e539 764 #define MXC_F_BIT_15 (1 << 15)
Anna Bridge 169:a7c7b631e539 765 #define MXC_F_BIT_16 (1 << 16)
Anna Bridge 169:a7c7b631e539 766 #define MXC_F_BIT_17 (1 << 17)
Anna Bridge 169:a7c7b631e539 767 #define MXC_F_BIT_18 (1 << 18)
Anna Bridge 169:a7c7b631e539 768 #define MXC_F_BIT_19 (1 << 19)
Anna Bridge 169:a7c7b631e539 769 #define MXC_F_BIT_20 (1 << 20)
Anna Bridge 169:a7c7b631e539 770 #define MXC_F_BIT_21 (1 << 21)
Anna Bridge 169:a7c7b631e539 771 #define MXC_F_BIT_22 (1 << 22)
Anna Bridge 169:a7c7b631e539 772 #define MXC_F_BIT_23 (1 << 23)
Anna Bridge 169:a7c7b631e539 773 #define MXC_F_BIT_24 (1 << 24)
Anna Bridge 169:a7c7b631e539 774 #define MXC_F_BIT_25 (1 << 25)
Anna Bridge 169:a7c7b631e539 775 #define MXC_F_BIT_26 (1 << 26)
Anna Bridge 169:a7c7b631e539 776 #define MXC_F_BIT_27 (1 << 27)
Anna Bridge 169:a7c7b631e539 777 #define MXC_F_BIT_28 (1 << 28)
Anna Bridge 169:a7c7b631e539 778 #define MXC_F_BIT_29 (1 << 29)
Anna Bridge 169:a7c7b631e539 779 #define MXC_F_BIT_30 (1 << 30)
Anna Bridge 169:a7c7b631e539 780 #define MXC_F_BIT_31 (1 << 31)
Anna Bridge 169:a7c7b631e539 781
Anna Bridge 169:a7c7b631e539 782
Anna Bridge 169:a7c7b631e539 783 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 784
Anna Bridge 169:a7c7b631e539 785 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
Anna Bridge 169:a7c7b631e539 786 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
Anna Bridge 169:a7c7b631e539 787 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
Anna Bridge 169:a7c7b631e539 788 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
Anna Bridge 169:a7c7b631e539 789 #define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
Anna Bridge 169:a7c7b631e539 790
Anna Bridge 169:a7c7b631e539 791
Anna Bridge 169:a7c7b631e539 792 /*******************************************************************************/
Anna Bridge 169:a7c7b631e539 793
Anna Bridge 169:a7c7b631e539 794 /* SCB CPACR Register Definitions */
Anna Bridge 169:a7c7b631e539 795 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
Anna Bridge 169:a7c7b631e539 796 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
Anna Bridge 169:a7c7b631e539 797 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
Anna Bridge 169:a7c7b631e539 798 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
Anna Bridge 169:a7c7b631e539 799 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
Anna Bridge 169:a7c7b631e539 800
Anna Bridge 169:a7c7b631e539 801 #endif /* _MAX32625_H_ */
Anna Bridge 169:a7c7b631e539 802