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TARGET_MAX32620FTHR/TOOLCHAIN_IAR/gpio_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_MAX32620FTHR/TARGET_Maxim/TARGET_MAX32620C/device/gpio_regs.h@167:84c0a372a020
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 167:84c0a372a020 | 1 | /******************************************************************************* |
| AnnaBridge | 167:84c0a372a020 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| AnnaBridge | 167:84c0a372a020 | 3 | * |
| AnnaBridge | 167:84c0a372a020 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| AnnaBridge | 167:84c0a372a020 | 5 | * copy of this software and associated documentation files (the "Software"), |
| AnnaBridge | 167:84c0a372a020 | 6 | * to deal in the Software without restriction, including without limitation |
| AnnaBridge | 167:84c0a372a020 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| AnnaBridge | 167:84c0a372a020 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| AnnaBridge | 167:84c0a372a020 | 9 | * Software is furnished to do so, subject to the following conditions: |
| AnnaBridge | 167:84c0a372a020 | 10 | * |
| AnnaBridge | 167:84c0a372a020 | 11 | * The above copyright notice and this permission notice shall be included |
| AnnaBridge | 167:84c0a372a020 | 12 | * in all copies or substantial portions of the Software. |
| AnnaBridge | 167:84c0a372a020 | 13 | * |
| AnnaBridge | 167:84c0a372a020 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| AnnaBridge | 167:84c0a372a020 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| AnnaBridge | 167:84c0a372a020 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| AnnaBridge | 167:84c0a372a020 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| AnnaBridge | 167:84c0a372a020 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| AnnaBridge | 167:84c0a372a020 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| AnnaBridge | 167:84c0a372a020 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| AnnaBridge | 167:84c0a372a020 | 21 | * |
| AnnaBridge | 167:84c0a372a020 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| AnnaBridge | 167:84c0a372a020 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| AnnaBridge | 167:84c0a372a020 | 24 | * Products, Inc. Branding Policy. |
| AnnaBridge | 167:84c0a372a020 | 25 | * |
| AnnaBridge | 167:84c0a372a020 | 26 | * The mere transfer of this software does not imply any licenses |
| AnnaBridge | 167:84c0a372a020 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| AnnaBridge | 167:84c0a372a020 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| AnnaBridge | 167:84c0a372a020 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| AnnaBridge | 167:84c0a372a020 | 30 | * ownership rights. |
| AnnaBridge | 167:84c0a372a020 | 31 | * |
| AnnaBridge | 167:84c0a372a020 | 32 | * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $ |
| AnnaBridge | 167:84c0a372a020 | 33 | * $Revision: 21839 $ |
| AnnaBridge | 167:84c0a372a020 | 34 | * |
| AnnaBridge | 167:84c0a372a020 | 35 | ******************************************************************************/ |
| AnnaBridge | 167:84c0a372a020 | 36 | |
| AnnaBridge | 167:84c0a372a020 | 37 | #ifndef _MXC_GPIO_REGS_H_ |
| AnnaBridge | 167:84c0a372a020 | 38 | #define _MXC_GPIO_REGS_H_ |
| AnnaBridge | 167:84c0a372a020 | 39 | |
| AnnaBridge | 167:84c0a372a020 | 40 | #ifdef __cplusplus |
| AnnaBridge | 167:84c0a372a020 | 41 | extern "C" { |
| AnnaBridge | 167:84c0a372a020 | 42 | #endif |
| AnnaBridge | 167:84c0a372a020 | 43 | |
| AnnaBridge | 167:84c0a372a020 | 44 | #include <stdint.h> |
| AnnaBridge | 167:84c0a372a020 | 45 | |
| AnnaBridge | 167:84c0a372a020 | 46 | /* |
| AnnaBridge | 167:84c0a372a020 | 47 | If types are not defined elsewhere (CMSIS) define them here |
| AnnaBridge | 167:84c0a372a020 | 48 | */ |
| AnnaBridge | 167:84c0a372a020 | 49 | #ifndef __IO |
| AnnaBridge | 167:84c0a372a020 | 50 | #define __IO volatile |
| AnnaBridge | 167:84c0a372a020 | 51 | #endif |
| AnnaBridge | 167:84c0a372a020 | 52 | #ifndef __I |
| AnnaBridge | 167:84c0a372a020 | 53 | #define __I volatile const |
| AnnaBridge | 167:84c0a372a020 | 54 | #endif |
| AnnaBridge | 167:84c0a372a020 | 55 | #ifndef __O |
| AnnaBridge | 167:84c0a372a020 | 56 | #define __O volatile |
| AnnaBridge | 167:84c0a372a020 | 57 | #endif |
| AnnaBridge | 167:84c0a372a020 | 58 | #ifndef __RO |
| AnnaBridge | 167:84c0a372a020 | 59 | #define __RO volatile const |
| AnnaBridge | 167:84c0a372a020 | 60 | #endif |
| AnnaBridge | 167:84c0a372a020 | 61 | |
| AnnaBridge | 167:84c0a372a020 | 62 | |
| AnnaBridge | 167:84c0a372a020 | 63 | /* |
| AnnaBridge | 167:84c0a372a020 | 64 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| AnnaBridge | 167:84c0a372a020 | 65 | access to each register in module. |
| AnnaBridge | 167:84c0a372a020 | 66 | */ |
| AnnaBridge | 167:84c0a372a020 | 67 | |
| AnnaBridge | 167:84c0a372a020 | 68 | /* Offset Register Description |
| AnnaBridge | 167:84c0a372a020 | 69 | ============= ============================================================================ */ |
| AnnaBridge | 167:84c0a372a020 | 70 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 71 | __IO uint32_t rst_mode[16]; /* 0x0000-0x003C Port P[0..15] Default (Power-On Reset) Output Drive Mode */ |
| AnnaBridge | 167:84c0a372a020 | 72 | __IO uint32_t free[16]; /* 0x0040-0x007C Port P[0..15] Free for GPIO Operation Flags */ |
| AnnaBridge | 167:84c0a372a020 | 73 | __IO uint32_t out_mode[16]; /* 0x0080-0x00BC Port P[0..15] Output Drive Mode */ |
| AnnaBridge | 167:84c0a372a020 | 74 | __IO uint32_t out_val[16]; /* 0x00C0-0x00FC Port P[0..15] GPIO Output Value */ |
| AnnaBridge | 167:84c0a372a020 | 75 | __IO uint32_t func_sel[16]; /* 0x0100-0x013C Port P[0..15] GPIO Function Select */ |
| AnnaBridge | 167:84c0a372a020 | 76 | __IO uint32_t in_mode[16]; /* 0x0140-0x017C Port P[0..15] GPIO Input Monitoring Mode */ |
| AnnaBridge | 167:84c0a372a020 | 77 | __IO uint32_t in_val[16]; /* 0x0180-0x01BC Port P[0..15] GPIO Input Value */ |
| AnnaBridge | 167:84c0a372a020 | 78 | __IO uint32_t int_mode[16]; /* 0x01C0-0x01FC Port P[0..15] Interrupt Detection Mode */ |
| AnnaBridge | 167:84c0a372a020 | 79 | __IO uint32_t intfl[16]; /* 0x0200-0x023C Port P[0..15] Interrupt Flags */ |
| AnnaBridge | 167:84c0a372a020 | 80 | __IO uint32_t inten[16]; /* 0x0240-0x027C Port P[0..15] Interrupt Enables */ |
| AnnaBridge | 167:84c0a372a020 | 81 | } mxc_gpio_regs_t; |
| AnnaBridge | 167:84c0a372a020 | 82 | |
| AnnaBridge | 167:84c0a372a020 | 83 | |
| AnnaBridge | 167:84c0a372a020 | 84 | /* |
| AnnaBridge | 167:84c0a372a020 | 85 | Register offsets for module GPIO. |
| AnnaBridge | 167:84c0a372a020 | 86 | */ |
| AnnaBridge | 167:84c0a372a020 | 87 | |
| AnnaBridge | 167:84c0a372a020 | 88 | #define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL) |
| AnnaBridge | 167:84c0a372a020 | 89 | #define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL) |
| AnnaBridge | 167:84c0a372a020 | 90 | #define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL) |
| AnnaBridge | 167:84c0a372a020 | 91 | #define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL) |
| AnnaBridge | 167:84c0a372a020 | 92 | #define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL) |
| AnnaBridge | 167:84c0a372a020 | 93 | #define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL) |
| AnnaBridge | 167:84c0a372a020 | 94 | #define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL) |
| AnnaBridge | 167:84c0a372a020 | 95 | #define MXC_R_GPIO_OFFS_RST_MODE_P7 ((uint32_t)0x0000001CUL) |
| AnnaBridge | 167:84c0a372a020 | 96 | #define MXC_R_GPIO_OFFS_RST_MODE_P8 ((uint32_t)0x00000020UL) |
| AnnaBridge | 167:84c0a372a020 | 97 | #define MXC_R_GPIO_OFFS_RST_MODE_P9 ((uint32_t)0x00000024UL) |
| AnnaBridge | 167:84c0a372a020 | 98 | #define MXC_R_GPIO_OFFS_RST_MODE_P10 ((uint32_t)0x00000028UL) |
| AnnaBridge | 167:84c0a372a020 | 99 | #define MXC_R_GPIO_OFFS_RST_MODE_P11 ((uint32_t)0x0000002CUL) |
| AnnaBridge | 167:84c0a372a020 | 100 | #define MXC_R_GPIO_OFFS_RST_MODE_P12 ((uint32_t)0x00000030UL) |
| AnnaBridge | 167:84c0a372a020 | 101 | #define MXC_R_GPIO_OFFS_RST_MODE_P13 ((uint32_t)0x00000034UL) |
| AnnaBridge | 167:84c0a372a020 | 102 | #define MXC_R_GPIO_OFFS_RST_MODE_P14 ((uint32_t)0x00000038UL) |
| AnnaBridge | 167:84c0a372a020 | 103 | #define MXC_R_GPIO_OFFS_RST_MODE_P15 ((uint32_t)0x0000003CUL) |
| AnnaBridge | 167:84c0a372a020 | 104 | #define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) |
| AnnaBridge | 167:84c0a372a020 | 105 | #define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) |
| AnnaBridge | 167:84c0a372a020 | 106 | #define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) |
| AnnaBridge | 167:84c0a372a020 | 107 | #define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) |
| AnnaBridge | 167:84c0a372a020 | 108 | #define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) |
| AnnaBridge | 167:84c0a372a020 | 109 | #define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) |
| AnnaBridge | 167:84c0a372a020 | 110 | #define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) |
| AnnaBridge | 167:84c0a372a020 | 111 | #define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL) |
| AnnaBridge | 167:84c0a372a020 | 112 | #define MXC_R_GPIO_OFFS_FREE_P8 ((uint32_t)0x00000060UL) |
| AnnaBridge | 167:84c0a372a020 | 113 | #define MXC_R_GPIO_OFFS_FREE_P9 ((uint32_t)0x00000064UL) |
| AnnaBridge | 167:84c0a372a020 | 114 | #define MXC_R_GPIO_OFFS_FREE_P10 ((uint32_t)0x00000068UL) |
| AnnaBridge | 167:84c0a372a020 | 115 | #define MXC_R_GPIO_OFFS_FREE_P11 ((uint32_t)0x0000006CUL) |
| AnnaBridge | 167:84c0a372a020 | 116 | #define MXC_R_GPIO_OFFS_FREE_P12 ((uint32_t)0x00000070UL) |
| AnnaBridge | 167:84c0a372a020 | 117 | #define MXC_R_GPIO_OFFS_FREE_P13 ((uint32_t)0x00000074UL) |
| AnnaBridge | 167:84c0a372a020 | 118 | #define MXC_R_GPIO_OFFS_FREE_P14 ((uint32_t)0x00000078UL) |
| AnnaBridge | 167:84c0a372a020 | 119 | #define MXC_R_GPIO_OFFS_FREE_P15 ((uint32_t)0x0000007CUL) |
| AnnaBridge | 167:84c0a372a020 | 120 | #define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) |
| AnnaBridge | 167:84c0a372a020 | 121 | #define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) |
| AnnaBridge | 167:84c0a372a020 | 122 | #define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) |
| AnnaBridge | 167:84c0a372a020 | 123 | #define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) |
| AnnaBridge | 167:84c0a372a020 | 124 | #define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) |
| AnnaBridge | 167:84c0a372a020 | 125 | #define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) |
| AnnaBridge | 167:84c0a372a020 | 126 | #define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) |
| AnnaBridge | 167:84c0a372a020 | 127 | #define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL) |
| AnnaBridge | 167:84c0a372a020 | 128 | #define MXC_R_GPIO_OFFS_OUT_MODE_P8 ((uint32_t)0x000000A0UL) |
| AnnaBridge | 167:84c0a372a020 | 129 | #define MXC_R_GPIO_OFFS_OUT_MODE_P9 ((uint32_t)0x000000A4UL) |
| AnnaBridge | 167:84c0a372a020 | 130 | #define MXC_R_GPIO_OFFS_OUT_MODE_P10 ((uint32_t)0x000000A8UL) |
| AnnaBridge | 167:84c0a372a020 | 131 | #define MXC_R_GPIO_OFFS_OUT_MODE_P11 ((uint32_t)0x000000ACUL) |
| AnnaBridge | 167:84c0a372a020 | 132 | #define MXC_R_GPIO_OFFS_OUT_MODE_P12 ((uint32_t)0x000000B0UL) |
| AnnaBridge | 167:84c0a372a020 | 133 | #define MXC_R_GPIO_OFFS_OUT_MODE_P13 ((uint32_t)0x000000B4UL) |
| AnnaBridge | 167:84c0a372a020 | 134 | #define MXC_R_GPIO_OFFS_OUT_MODE_P14 ((uint32_t)0x000000B8UL) |
| AnnaBridge | 167:84c0a372a020 | 135 | #define MXC_R_GPIO_OFFS_OUT_MODE_P15 ((uint32_t)0x000000BCUL) |
| AnnaBridge | 167:84c0a372a020 | 136 | #define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) |
| AnnaBridge | 167:84c0a372a020 | 137 | #define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) |
| AnnaBridge | 167:84c0a372a020 | 138 | #define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) |
| AnnaBridge | 167:84c0a372a020 | 139 | #define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) |
| AnnaBridge | 167:84c0a372a020 | 140 | #define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) |
| AnnaBridge | 167:84c0a372a020 | 141 | #define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) |
| AnnaBridge | 167:84c0a372a020 | 142 | #define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) |
| AnnaBridge | 167:84c0a372a020 | 143 | #define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL) |
| AnnaBridge | 167:84c0a372a020 | 144 | #define MXC_R_GPIO_OFFS_OUT_VAL_P8 ((uint32_t)0x000000E0UL) |
| AnnaBridge | 167:84c0a372a020 | 145 | #define MXC_R_GPIO_OFFS_OUT_VAL_P9 ((uint32_t)0x000000E4UL) |
| AnnaBridge | 167:84c0a372a020 | 146 | #define MXC_R_GPIO_OFFS_OUT_VAL_P10 ((uint32_t)0x000000E8UL) |
| AnnaBridge | 167:84c0a372a020 | 147 | #define MXC_R_GPIO_OFFS_OUT_VAL_P11 ((uint32_t)0x000000ECUL) |
| AnnaBridge | 167:84c0a372a020 | 148 | #define MXC_R_GPIO_OFFS_OUT_VAL_P12 ((uint32_t)0x000000F0UL) |
| AnnaBridge | 167:84c0a372a020 | 149 | #define MXC_R_GPIO_OFFS_OUT_VAL_P13 ((uint32_t)0x000000F4UL) |
| AnnaBridge | 167:84c0a372a020 | 150 | #define MXC_R_GPIO_OFFS_OUT_VAL_P14 ((uint32_t)0x000000F8UL) |
| AnnaBridge | 167:84c0a372a020 | 151 | #define MXC_R_GPIO_OFFS_OUT_VAL_P15 ((uint32_t)0x000000FCUL) |
| AnnaBridge | 167:84c0a372a020 | 152 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) |
| AnnaBridge | 167:84c0a372a020 | 153 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) |
| AnnaBridge | 167:84c0a372a020 | 154 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) |
| AnnaBridge | 167:84c0a372a020 | 155 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL) |
| AnnaBridge | 167:84c0a372a020 | 156 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL) |
| AnnaBridge | 167:84c0a372a020 | 157 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL) |
| AnnaBridge | 167:84c0a372a020 | 158 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) |
| AnnaBridge | 167:84c0a372a020 | 159 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL) |
| AnnaBridge | 167:84c0a372a020 | 160 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P8 ((uint32_t)0x00000120UL) |
| AnnaBridge | 167:84c0a372a020 | 161 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P9 ((uint32_t)0x00000124UL) |
| AnnaBridge | 167:84c0a372a020 | 162 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P10 ((uint32_t)0x00000128UL) |
| AnnaBridge | 167:84c0a372a020 | 163 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P11 ((uint32_t)0x0000012CUL) |
| AnnaBridge | 167:84c0a372a020 | 164 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P12 ((uint32_t)0x00000130UL) |
| AnnaBridge | 167:84c0a372a020 | 165 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P13 ((uint32_t)0x00000134UL) |
| AnnaBridge | 167:84c0a372a020 | 166 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P14 ((uint32_t)0x00000138UL) |
| AnnaBridge | 167:84c0a372a020 | 167 | #define MXC_R_GPIO_OFFS_FUNC_SEL_P15 ((uint32_t)0x0000013CUL) |
| AnnaBridge | 167:84c0a372a020 | 168 | #define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) |
| AnnaBridge | 167:84c0a372a020 | 169 | #define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) |
| AnnaBridge | 167:84c0a372a020 | 170 | #define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) |
| AnnaBridge | 167:84c0a372a020 | 171 | #define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) |
| AnnaBridge | 167:84c0a372a020 | 172 | #define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) |
| AnnaBridge | 167:84c0a372a020 | 173 | #define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) |
| AnnaBridge | 167:84c0a372a020 | 174 | #define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) |
| AnnaBridge | 167:84c0a372a020 | 175 | #define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL) |
| AnnaBridge | 167:84c0a372a020 | 176 | #define MXC_R_GPIO_OFFS_IN_MODE_P8 ((uint32_t)0x00000160UL) |
| AnnaBridge | 167:84c0a372a020 | 177 | #define MXC_R_GPIO_OFFS_IN_MODE_P9 ((uint32_t)0x00000164UL) |
| AnnaBridge | 167:84c0a372a020 | 178 | #define MXC_R_GPIO_OFFS_IN_MODE_P10 ((uint32_t)0x00000168UL) |
| AnnaBridge | 167:84c0a372a020 | 179 | #define MXC_R_GPIO_OFFS_IN_MODE_P11 ((uint32_t)0x0000016CUL) |
| AnnaBridge | 167:84c0a372a020 | 180 | #define MXC_R_GPIO_OFFS_IN_MODE_P12 ((uint32_t)0x00000170UL) |
| AnnaBridge | 167:84c0a372a020 | 181 | #define MXC_R_GPIO_OFFS_IN_MODE_P13 ((uint32_t)0x00000174UL) |
| AnnaBridge | 167:84c0a372a020 | 182 | #define MXC_R_GPIO_OFFS_IN_MODE_P14 ((uint32_t)0x00000178UL) |
| AnnaBridge | 167:84c0a372a020 | 183 | #define MXC_R_GPIO_OFFS_IN_MODE_P15 ((uint32_t)0x0000017CUL) |
| AnnaBridge | 167:84c0a372a020 | 184 | #define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) |
| AnnaBridge | 167:84c0a372a020 | 185 | #define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) |
| AnnaBridge | 167:84c0a372a020 | 186 | #define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) |
| AnnaBridge | 167:84c0a372a020 | 187 | #define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) |
| AnnaBridge | 167:84c0a372a020 | 188 | #define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) |
| AnnaBridge | 167:84c0a372a020 | 189 | #define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) |
| AnnaBridge | 167:84c0a372a020 | 190 | #define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) |
| AnnaBridge | 167:84c0a372a020 | 191 | #define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL) |
| AnnaBridge | 167:84c0a372a020 | 192 | #define MXC_R_GPIO_OFFS_IN_VAL_P8 ((uint32_t)0x000001A0UL) |
| AnnaBridge | 167:84c0a372a020 | 193 | #define MXC_R_GPIO_OFFS_IN_VAL_P9 ((uint32_t)0x000001A4UL) |
| AnnaBridge | 167:84c0a372a020 | 194 | #define MXC_R_GPIO_OFFS_IN_VAL_P10 ((uint32_t)0x000001A8UL) |
| AnnaBridge | 167:84c0a372a020 | 195 | #define MXC_R_GPIO_OFFS_IN_VAL_P11 ((uint32_t)0x000001ACUL) |
| AnnaBridge | 167:84c0a372a020 | 196 | #define MXC_R_GPIO_OFFS_IN_VAL_P12 ((uint32_t)0x000001B0UL) |
| AnnaBridge | 167:84c0a372a020 | 197 | #define MXC_R_GPIO_OFFS_IN_VAL_P13 ((uint32_t)0x000001B4UL) |
| AnnaBridge | 167:84c0a372a020 | 198 | #define MXC_R_GPIO_OFFS_IN_VAL_P14 ((uint32_t)0x000001B8UL) |
| AnnaBridge | 167:84c0a372a020 | 199 | #define MXC_R_GPIO_OFFS_IN_VAL_P15 ((uint32_t)0x000001BCUL) |
| AnnaBridge | 167:84c0a372a020 | 200 | #define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) |
| AnnaBridge | 167:84c0a372a020 | 201 | #define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) |
| AnnaBridge | 167:84c0a372a020 | 202 | #define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) |
| AnnaBridge | 167:84c0a372a020 | 203 | #define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) |
| AnnaBridge | 167:84c0a372a020 | 204 | #define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) |
| AnnaBridge | 167:84c0a372a020 | 205 | #define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) |
| AnnaBridge | 167:84c0a372a020 | 206 | #define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) |
| AnnaBridge | 167:84c0a372a020 | 207 | #define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL) |
| AnnaBridge | 167:84c0a372a020 | 208 | #define MXC_R_GPIO_OFFS_INT_MODE_P8 ((uint32_t)0x000001E0UL) |
| AnnaBridge | 167:84c0a372a020 | 209 | #define MXC_R_GPIO_OFFS_INT_MODE_P9 ((uint32_t)0x000001E4UL) |
| AnnaBridge | 167:84c0a372a020 | 210 | #define MXC_R_GPIO_OFFS_INT_MODE_P10 ((uint32_t)0x000001E8UL) |
| AnnaBridge | 167:84c0a372a020 | 211 | #define MXC_R_GPIO_OFFS_INT_MODE_P11 ((uint32_t)0x000001ECUL) |
| AnnaBridge | 167:84c0a372a020 | 212 | #define MXC_R_GPIO_OFFS_INT_MODE_P12 ((uint32_t)0x000001F0UL) |
| AnnaBridge | 167:84c0a372a020 | 213 | #define MXC_R_GPIO_OFFS_INT_MODE_P13 ((uint32_t)0x000001F4UL) |
| AnnaBridge | 167:84c0a372a020 | 214 | #define MXC_R_GPIO_OFFS_INT_MODE_P14 ((uint32_t)0x000001F8UL) |
| AnnaBridge | 167:84c0a372a020 | 215 | #define MXC_R_GPIO_OFFS_INT_MODE_P15 ((uint32_t)0x000001FCUL) |
| AnnaBridge | 167:84c0a372a020 | 216 | #define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) |
| AnnaBridge | 167:84c0a372a020 | 217 | #define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) |
| AnnaBridge | 167:84c0a372a020 | 218 | #define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) |
| AnnaBridge | 167:84c0a372a020 | 219 | #define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) |
| AnnaBridge | 167:84c0a372a020 | 220 | #define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) |
| AnnaBridge | 167:84c0a372a020 | 221 | #define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) |
| AnnaBridge | 167:84c0a372a020 | 222 | #define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) |
| AnnaBridge | 167:84c0a372a020 | 223 | #define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL) |
| AnnaBridge | 167:84c0a372a020 | 224 | #define MXC_R_GPIO_OFFS_INTFL_P8 ((uint32_t)0x00000220UL) |
| AnnaBridge | 167:84c0a372a020 | 225 | #define MXC_R_GPIO_OFFS_INTFL_P9 ((uint32_t)0x00000224UL) |
| AnnaBridge | 167:84c0a372a020 | 226 | #define MXC_R_GPIO_OFFS_INTFL_P10 ((uint32_t)0x00000228UL) |
| AnnaBridge | 167:84c0a372a020 | 227 | #define MXC_R_GPIO_OFFS_INTFL_P11 ((uint32_t)0x0000022CUL) |
| AnnaBridge | 167:84c0a372a020 | 228 | #define MXC_R_GPIO_OFFS_INTFL_P12 ((uint32_t)0x00000230UL) |
| AnnaBridge | 167:84c0a372a020 | 229 | #define MXC_R_GPIO_OFFS_INTFL_P13 ((uint32_t)0x00000234UL) |
| AnnaBridge | 167:84c0a372a020 | 230 | #define MXC_R_GPIO_OFFS_INTFL_P14 ((uint32_t)0x00000238UL) |
| AnnaBridge | 167:84c0a372a020 | 231 | #define MXC_R_GPIO_OFFS_INTFL_P15 ((uint32_t)0x0000023CUL) |
| AnnaBridge | 167:84c0a372a020 | 232 | #define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) |
| AnnaBridge | 167:84c0a372a020 | 233 | #define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) |
| AnnaBridge | 167:84c0a372a020 | 234 | #define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) |
| AnnaBridge | 167:84c0a372a020 | 235 | #define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) |
| AnnaBridge | 167:84c0a372a020 | 236 | #define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) |
| AnnaBridge | 167:84c0a372a020 | 237 | #define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) |
| AnnaBridge | 167:84c0a372a020 | 238 | #define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) |
| AnnaBridge | 167:84c0a372a020 | 239 | #define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL) |
| AnnaBridge | 167:84c0a372a020 | 240 | #define MXC_R_GPIO_OFFS_INTEN_P8 ((uint32_t)0x00000260UL) |
| AnnaBridge | 167:84c0a372a020 | 241 | #define MXC_R_GPIO_OFFS_INTEN_P9 ((uint32_t)0x00000264UL) |
| AnnaBridge | 167:84c0a372a020 | 242 | #define MXC_R_GPIO_OFFS_INTEN_P10 ((uint32_t)0x00000268UL) |
| AnnaBridge | 167:84c0a372a020 | 243 | #define MXC_R_GPIO_OFFS_INTEN_P11 ((uint32_t)0x0000026CUL) |
| AnnaBridge | 167:84c0a372a020 | 244 | #define MXC_R_GPIO_OFFS_INTEN_P12 ((uint32_t)0x00000270UL) |
| AnnaBridge | 167:84c0a372a020 | 245 | #define MXC_R_GPIO_OFFS_INTEN_P13 ((uint32_t)0x00000274UL) |
| AnnaBridge | 167:84c0a372a020 | 246 | #define MXC_R_GPIO_OFFS_INTEN_P14 ((uint32_t)0x00000278UL) |
| AnnaBridge | 167:84c0a372a020 | 247 | #define MXC_R_GPIO_OFFS_INTEN_P15 ((uint32_t)0x0000027CUL) |
| AnnaBridge | 167:84c0a372a020 | 248 | |
| AnnaBridge | 167:84c0a372a020 | 249 | |
| AnnaBridge | 167:84c0a372a020 | 250 | /* |
| AnnaBridge | 167:84c0a372a020 | 251 | Field positions and masks for module GPIO. |
| AnnaBridge | 167:84c0a372a020 | 252 | */ |
| AnnaBridge | 167:84c0a372a020 | 253 | |
| AnnaBridge | 167:84c0a372a020 | 254 | #define MXC_F_GPIO_RST_MODE_PIN0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 255 | #define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 256 | #define MXC_F_GPIO_RST_MODE_PIN1_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 257 | #define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 258 | #define MXC_F_GPIO_RST_MODE_PIN2_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 259 | #define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 260 | #define MXC_F_GPIO_RST_MODE_PIN3_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 261 | #define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 262 | #define MXC_F_GPIO_RST_MODE_PIN4_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 263 | #define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 264 | #define MXC_F_GPIO_RST_MODE_PIN5_POS 20 |
| AnnaBridge | 167:84c0a372a020 | 265 | #define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 266 | #define MXC_F_GPIO_RST_MODE_PIN6_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 267 | #define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 268 | #define MXC_F_GPIO_RST_MODE_PIN7_POS 28 |
| AnnaBridge | 167:84c0a372a020 | 269 | #define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 270 | |
| AnnaBridge | 167:84c0a372a020 | 271 | #define MXC_F_GPIO_FREE_PIN0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 272 | #define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 273 | #define MXC_F_GPIO_FREE_PIN1_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 274 | #define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 275 | #define MXC_F_GPIO_FREE_PIN2_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 276 | #define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 277 | #define MXC_F_GPIO_FREE_PIN3_POS 3 |
| AnnaBridge | 167:84c0a372a020 | 278 | #define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 279 | #define MXC_F_GPIO_FREE_PIN4_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 280 | #define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 281 | #define MXC_F_GPIO_FREE_PIN5_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 282 | #define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 283 | #define MXC_F_GPIO_FREE_PIN6_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 284 | #define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 285 | #define MXC_F_GPIO_FREE_PIN7_POS 7 |
| AnnaBridge | 167:84c0a372a020 | 286 | #define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 287 | |
| AnnaBridge | 167:84c0a372a020 | 288 | #define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 289 | #define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 290 | #define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 291 | #define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 292 | #define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 293 | #define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 294 | #define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 295 | #define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 296 | #define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 297 | #define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 298 | #define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 |
| AnnaBridge | 167:84c0a372a020 | 299 | #define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 300 | #define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 301 | #define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 302 | #define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 |
| AnnaBridge | 167:84c0a372a020 | 303 | #define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 304 | |
| AnnaBridge | 167:84c0a372a020 | 305 | #define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 306 | #define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 307 | #define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 308 | #define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 309 | #define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 310 | #define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 311 | #define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 |
| AnnaBridge | 167:84c0a372a020 | 312 | #define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 313 | #define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 314 | #define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 315 | #define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 316 | #define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 317 | #define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 318 | #define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 319 | #define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 |
| AnnaBridge | 167:84c0a372a020 | 320 | #define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 321 | |
| AnnaBridge | 167:84c0a372a020 | 322 | #define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 323 | #define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 324 | #define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 325 | #define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 326 | #define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 327 | #define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 328 | #define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 329 | #define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 330 | #define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 331 | #define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 332 | #define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20 |
| AnnaBridge | 167:84c0a372a020 | 333 | #define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 334 | #define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 335 | #define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 336 | #define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28 |
| AnnaBridge | 167:84c0a372a020 | 337 | #define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 338 | |
| AnnaBridge | 167:84c0a372a020 | 339 | #define MXC_F_GPIO_IN_MODE_PIN0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 340 | #define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 341 | #define MXC_F_GPIO_IN_MODE_PIN1_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 342 | #define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 343 | #define MXC_F_GPIO_IN_MODE_PIN2_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 344 | #define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 345 | #define MXC_F_GPIO_IN_MODE_PIN3_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 346 | #define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 347 | #define MXC_F_GPIO_IN_MODE_PIN4_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 348 | #define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 349 | #define MXC_F_GPIO_IN_MODE_PIN5_POS 20 |
| AnnaBridge | 167:84c0a372a020 | 350 | #define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 351 | #define MXC_F_GPIO_IN_MODE_PIN6_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 352 | #define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 353 | #define MXC_F_GPIO_IN_MODE_PIN7_POS 28 |
| AnnaBridge | 167:84c0a372a020 | 354 | #define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 355 | |
| AnnaBridge | 167:84c0a372a020 | 356 | #define MXC_F_GPIO_IN_VAL_PIN0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 357 | #define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 358 | #define MXC_F_GPIO_IN_VAL_PIN1_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 359 | #define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 360 | #define MXC_F_GPIO_IN_VAL_PIN2_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 361 | #define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 362 | #define MXC_F_GPIO_IN_VAL_PIN3_POS 3 |
| AnnaBridge | 167:84c0a372a020 | 363 | #define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 364 | #define MXC_F_GPIO_IN_VAL_PIN4_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 365 | #define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 366 | #define MXC_F_GPIO_IN_VAL_PIN5_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 367 | #define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 368 | #define MXC_F_GPIO_IN_VAL_PIN6_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 369 | #define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 370 | #define MXC_F_GPIO_IN_VAL_PIN7_POS 7 |
| AnnaBridge | 167:84c0a372a020 | 371 | #define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 372 | |
| AnnaBridge | 167:84c0a372a020 | 373 | #define MXC_F_GPIO_INT_MODE_PIN0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 374 | #define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 375 | #define MXC_F_GPIO_INT_MODE_PIN1_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 376 | #define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 377 | #define MXC_F_GPIO_INT_MODE_PIN2_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 378 | #define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 379 | #define MXC_F_GPIO_INT_MODE_PIN3_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 380 | #define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 381 | #define MXC_F_GPIO_INT_MODE_PIN4_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 382 | #define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 383 | #define MXC_F_GPIO_INT_MODE_PIN5_POS 20 |
| AnnaBridge | 167:84c0a372a020 | 384 | #define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 385 | #define MXC_F_GPIO_INT_MODE_PIN6_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 386 | #define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 387 | #define MXC_F_GPIO_INT_MODE_PIN7_POS 28 |
| AnnaBridge | 167:84c0a372a020 | 388 | #define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 389 | |
| AnnaBridge | 167:84c0a372a020 | 390 | #define MXC_F_GPIO_INTFL_PIN0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 391 | #define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 392 | #define MXC_F_GPIO_INTFL_PIN1_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 393 | #define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 394 | #define MXC_F_GPIO_INTFL_PIN2_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 395 | #define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 396 | #define MXC_F_GPIO_INTFL_PIN3_POS 3 |
| AnnaBridge | 167:84c0a372a020 | 397 | #define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 398 | #define MXC_F_GPIO_INTFL_PIN4_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 399 | #define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 400 | #define MXC_F_GPIO_INTFL_PIN5_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 401 | #define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 402 | #define MXC_F_GPIO_INTFL_PIN6_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 403 | #define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 404 | #define MXC_F_GPIO_INTFL_PIN7_POS 7 |
| AnnaBridge | 167:84c0a372a020 | 405 | #define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 406 | |
| AnnaBridge | 167:84c0a372a020 | 407 | #define MXC_F_GPIO_INTEN_PIN0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 408 | #define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 409 | #define MXC_F_GPIO_INTEN_PIN1_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 410 | #define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 411 | #define MXC_F_GPIO_INTEN_PIN2_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 412 | #define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 413 | #define MXC_F_GPIO_INTEN_PIN3_POS 3 |
| AnnaBridge | 167:84c0a372a020 | 414 | #define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 415 | #define MXC_F_GPIO_INTEN_PIN4_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 416 | #define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 417 | #define MXC_F_GPIO_INTEN_PIN5_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 418 | #define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 419 | #define MXC_F_GPIO_INTEN_PIN6_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 420 | #define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 421 | #define MXC_F_GPIO_INTEN_PIN7_POS 7 |
| AnnaBridge | 167:84c0a372a020 | 422 | #define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 423 | |
| AnnaBridge | 167:84c0a372a020 | 424 | |
| AnnaBridge | 167:84c0a372a020 | 425 | |
| AnnaBridge | 167:84c0a372a020 | 426 | /* |
| AnnaBridge | 167:84c0a372a020 | 427 | Field values and shifted values for module GPIO. |
| AnnaBridge | 167:84c0a372a020 | 428 | */ |
| AnnaBridge | 167:84c0a372a020 | 429 | |
| AnnaBridge | 167:84c0a372a020 | 430 | #define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 167:84c0a372a020 | 431 | #define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 167:84c0a372a020 | 432 | #define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 167:84c0a372a020 | 433 | #define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 167:84c0a372a020 | 434 | #define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 167:84c0a372a020 | 435 | |
| AnnaBridge | 167:84c0a372a020 | 436 | #define MXC_V_GPIO_FREE_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 167:84c0a372a020 | 437 | #define MXC_V_GPIO_FREE_AVAILABLE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 167:84c0a372a020 | 438 | |
| AnnaBridge | 167:84c0a372a020 | 439 | #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 167:84c0a372a020 | 440 | #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 167:84c0a372a020 | 441 | #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 167:84c0a372a020 | 442 | #define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 167:84c0a372a020 | 443 | #define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 167:84c0a372a020 | 444 | #define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) |
| AnnaBridge | 167:84c0a372a020 | 445 | #define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) |
| AnnaBridge | 167:84c0a372a020 | 446 | #define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) |
| AnnaBridge | 167:84c0a372a020 | 447 | #define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) |
| AnnaBridge | 167:84c0a372a020 | 448 | #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL)) |
| AnnaBridge | 167:84c0a372a020 | 449 | #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL)) |
| AnnaBridge | 167:84c0a372a020 | 450 | #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL)) |
| AnnaBridge | 167:84c0a372a020 | 451 | #define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL)) |
| AnnaBridge | 167:84c0a372a020 | 452 | |
| AnnaBridge | 167:84c0a372a020 | 453 | #define MXC_V_GPIO_FUNC_SEL_MODE_GPIO ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 167:84c0a372a020 | 454 | #define MXC_V_GPIO_FUNC_SEL_MODE_PT ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 167:84c0a372a020 | 455 | #define MXC_V_GPIO_FUNC_SEL_MODE_TMR ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 167:84c0a372a020 | 456 | |
| AnnaBridge | 167:84c0a372a020 | 457 | #define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 167:84c0a372a020 | 458 | #define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 167:84c0a372a020 | 459 | #define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 167:84c0a372a020 | 460 | #define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 167:84c0a372a020 | 461 | |
| AnnaBridge | 167:84c0a372a020 | 462 | #define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL)) |
| AnnaBridge | 167:84c0a372a020 | 463 | #define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) |
| AnnaBridge | 167:84c0a372a020 | 464 | #define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) |
| AnnaBridge | 167:84c0a372a020 | 465 | #define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL)) |
| AnnaBridge | 167:84c0a372a020 | 466 | #define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL)) |
| AnnaBridge | 167:84c0a372a020 | 467 | #define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL)) |
| AnnaBridge | 167:84c0a372a020 | 468 | |
| AnnaBridge | 167:84c0a372a020 | 469 | |
| AnnaBridge | 167:84c0a372a020 | 470 | |
| AnnaBridge | 167:84c0a372a020 | 471 | #ifdef __cplusplus |
| AnnaBridge | 167:84c0a372a020 | 472 | } |
| AnnaBridge | 167:84c0a372a020 | 473 | #endif |
| AnnaBridge | 167:84c0a372a020 | 474 | |
| AnnaBridge | 167:84c0a372a020 | 475 | #endif /* _MXC_GPIO_REGS_H_ */ |
