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TARGET_MAX32620FTHR/TOOLCHAIN_GCC_ARM/spix.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_MAX32620FTHR/TARGET_Maxim/TARGET_MAX32620C/mxc/spix.h@167:84c0a372a020 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /**
AnnaBridge 167:84c0a372a020 2 * @file
AnnaBridge 167:84c0a372a020 3 * @brief This is the high level API for the SPI Execute in Place (SPIX)
AnnaBridge 167:84c0a372a020 4 * module.
AnnaBridge 167:84c0a372a020 5 * @note If using this SPIX with IAR Embedded Workbench for ARM, it is
AnnaBridge 167:84c0a372a020 6 * required to define <tt>IAR_SPIX_PRAGMA=1</tt>. This should be
AnnaBridge 167:84c0a372a020 7 * done under Project->Options-> C/C++ Compiler->Preprocessor in the
AnnaBridge 167:84c0a372a020 8 * Defined Symbols input box. See the IAR documentation for
AnnaBridge 167:84c0a372a020 9 * additional information on how to set a preprocessor define in a
AnnaBridge 167:84c0a372a020 10 * project.
AnnaBridge 167:84c0a372a020 11 */
AnnaBridge 167:84c0a372a020 12 /*******************************************************************************
AnnaBridge 167:84c0a372a020 13 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 14 *
AnnaBridge 167:84c0a372a020 15 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 16 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 17 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 18 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 19 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 20 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 23 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 24 *
AnnaBridge 167:84c0a372a020 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 26 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 28 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 29 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 31 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 32 *
AnnaBridge 167:84c0a372a020 33 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 34 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 35 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 36 *
AnnaBridge 167:84c0a372a020 37 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 38 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 39 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 40 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 41 * ownership rights.
AnnaBridge 167:84c0a372a020 42 *
AnnaBridge 167:84c0a372a020 43 * $Date: 2017-02-16 12:03:11 -0600 (Thu, 16 Feb 2017) $
AnnaBridge 167:84c0a372a020 44 * $Revision: 26463 $
AnnaBridge 167:84c0a372a020 45 *
AnnaBridge 167:84c0a372a020 46 **************************************************************************** */
AnnaBridge 167:84c0a372a020 47
AnnaBridge 167:84c0a372a020 48
AnnaBridge 167:84c0a372a020 49
AnnaBridge 167:84c0a372a020 50 #include "mxc_sys.h"
AnnaBridge 167:84c0a372a020 51 #include "spix_regs.h"
AnnaBridge 167:84c0a372a020 52
AnnaBridge 167:84c0a372a020 53 /* Define to prevent redundant inclusion */
AnnaBridge 167:84c0a372a020 54 #ifndef _SPIX_H_
AnnaBridge 167:84c0a372a020 55 #define _SPIX_H_
AnnaBridge 167:84c0a372a020 56
AnnaBridge 167:84c0a372a020 57 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 58 extern "C" {
AnnaBridge 167:84c0a372a020 59 #endif
AnnaBridge 167:84c0a372a020 60
AnnaBridge 167:84c0a372a020 61 /**
AnnaBridge 167:84c0a372a020 62 * @ingroup periphlibs
AnnaBridge 167:84c0a372a020 63 * @defgroup spix SPIX
AnnaBridge 167:84c0a372a020 64 * @brief SPI Execute In Place.
AnnaBridge 167:84c0a372a020 65 * @{
AnnaBridge 167:84c0a372a020 66 */
AnnaBridge 167:84c0a372a020 67
AnnaBridge 167:84c0a372a020 68 /* **** Definitions **** */
AnnaBridge 167:84c0a372a020 69 /**
AnnaBridge 167:84c0a372a020 70 * Enumeration type for the number of I/O pins to use during each fetch stage for SPIX
AnnaBridge 167:84c0a372a020 71 */
AnnaBridge 167:84c0a372a020 72 typedef enum {
AnnaBridge 167:84c0a372a020 73 SPIX_SINGLE_IO = MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE, /**< 1 I/O pin for SPIX Fetch Cmd Data line */
AnnaBridge 167:84c0a372a020 74 SPIX_DUAL_IO = MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO, /**< 2 I/O pins for SPIX Fetch Cmd Data line */
AnnaBridge 167:84c0a372a020 75 SPIX_QUAD_IO = MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO /**< 4 I/O pins for SPIX Fetch Cmd Data line */
AnnaBridge 167:84c0a372a020 76 } spix_width_t;
AnnaBridge 167:84c0a372a020 77
AnnaBridge 167:84c0a372a020 78 /**
AnnaBridge 167:84c0a372a020 79 * Enumeration type for the number of address bytes to use during an SPIX fetch
AnnaBridge 167:84c0a372a020 80 */
AnnaBridge 167:84c0a372a020 81 typedef enum {
AnnaBridge 167:84c0a372a020 82 SPIX_3BYTE_FETCH_ADDR = 0, ///< Fetch Address of 3 Bytes
AnnaBridge 167:84c0a372a020 83 SPIX_4BYTE_FETCH_ADDR = 1 ///< Fetch Address of 4 Bytes
AnnaBridge 167:84c0a372a020 84 } spix_addr_size_t;
AnnaBridge 167:84c0a372a020 85
AnnaBridge 167:84c0a372a020 86 /**
AnnaBridge 167:84c0a372a020 87 * Structure type for SPIX fetch configuration
AnnaBridge 167:84c0a372a020 88 */
AnnaBridge 167:84c0a372a020 89 typedef struct {
AnnaBridge 167:84c0a372a020 90 spix_width_t cmd_width; ///< Number of I/O lines used for command SPI transaction.
AnnaBridge 167:84c0a372a020 91 spix_width_t addr_width; ///< Number of I/O lines used for address SPI transaction.
AnnaBridge 167:84c0a372a020 92 spix_width_t data_width; ///< Number of I/O lines used for data SPI transaction.
AnnaBridge 167:84c0a372a020 93 spix_addr_size_t addr_size; ///< Use 3 or 4 byte addresses for fetches.
AnnaBridge 167:84c0a372a020 94 uint8_t cmd; ///< Command value to initiate fetch.
AnnaBridge 167:84c0a372a020 95 uint8_t mode_clocks; ///< Number of SPI clocks required during mode phase of fetch.
AnnaBridge 167:84c0a372a020 96 uint8_t no_cmd_mode; ///< Read command sent only once.
AnnaBridge 167:84c0a372a020 97 uint16_t mode_data; ///< Data sent with mode clocks.
AnnaBridge 167:84c0a372a020 98 } spix_fetch_t;
AnnaBridge 167:84c0a372a020 99
AnnaBridge 167:84c0a372a020 100 /* **** Globals **** */
AnnaBridge 167:84c0a372a020 101
AnnaBridge 167:84c0a372a020 102 /* **** Function Prototypes **** */
AnnaBridge 167:84c0a372a020 103
AnnaBridge 167:84c0a372a020 104 /**
AnnaBridge 167:84c0a372a020 105 * @brief Configure SPI execute in place clocking.
AnnaBridge 167:84c0a372a020 106 * @param sys_cfg Pointer to system level configuration structure.
AnnaBridge 167:84c0a372a020 107 * @param baud Frequency in hertz to set the clock to. May not be able
AnnaBridge 167:84c0a372a020 108 * to achieve with the given clock divider.
AnnaBridge 167:84c0a372a020 109 * @param sample Number of SPIX clocks to delay the sampling of the SDIO
AnnaBridge 167:84c0a372a020 110 * lines. Will use feedback mode if set to 0.
AnnaBridge 167:84c0a372a020 111 * @return #E_NO_ERROR if everything is successful
AnnaBridge 167:84c0a372a020 112 */
AnnaBridge 167:84c0a372a020 113 int SPIX_ConfigClock(const sys_cfg_spix_t *sys_cfg, uint32_t baud, uint8_t sample);
AnnaBridge 167:84c0a372a020 114
AnnaBridge 167:84c0a372a020 115 /**
AnnaBridge 167:84c0a372a020 116 * @brief Configure SPI execute in place slave select.
AnnaBridge 167:84c0a372a020 117 * @param ssel Index of which slave select line to use.
AnnaBridge 167:84c0a372a020 118 * @param pol Polarity of slave select (0 for active low, 1 for
AnnaBridge 167:84c0a372a020 119 * active high).
AnnaBridge 167:84c0a372a020 120 * @param act_delay SPIX clocks between slave select assert and active
AnnaBridge 167:84c0a372a020 121 * SPI clock.
AnnaBridge 167:84c0a372a020 122 * @param inact_delay SPIX clocks between active SPI clock and slave
AnnaBridge 167:84c0a372a020 123 * select deassert.
AnnaBridge 167:84c0a372a020 124 */
AnnaBridge 167:84c0a372a020 125 void SPIX_ConfigSlave(uint8_t ssel, uint8_t pol, uint8_t act_delay, uint8_t inact_delay);
AnnaBridge 167:84c0a372a020 126
AnnaBridge 167:84c0a372a020 127 /**
AnnaBridge 167:84c0a372a020 128 * @brief Configure how the SPIX fetches data.
AnnaBridge 167:84c0a372a020 129 * @param fetch Pointer to configuration struct that describes how to
AnnaBridge 167:84c0a372a020 130 * fetch data.
AnnaBridge 167:84c0a372a020 131 */
AnnaBridge 167:84c0a372a020 132 void SPIX_ConfigFetch(const spix_fetch_t *fetch);
AnnaBridge 167:84c0a372a020 133
AnnaBridge 167:84c0a372a020 134 /**
AnnaBridge 167:84c0a372a020 135 * @brief Shutdown SPIX module.
AnnaBridge 167:84c0a372a020 136 * @param spix Pointer to SPIX regs.
AnnaBridge 167:84c0a372a020 137 * @return #E_NO_ERROR if everything is successful
AnnaBridge 167:84c0a372a020 138 */
AnnaBridge 167:84c0a372a020 139 int SPIX_Shutdown(mxc_spix_regs_t *spix);
AnnaBridge 167:84c0a372a020 140
AnnaBridge 167:84c0a372a020 141 /**@} end of group spix */
AnnaBridge 167:84c0a372a020 142 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 143 }
AnnaBridge 167:84c0a372a020 144 #endif
AnnaBridge 167:84c0a372a020 145
AnnaBridge 167:84c0a372a020 146 #endif /* _SPIX_H */