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TARGET_MAX32620FTHR/TOOLCHAIN_ARM_STD/trim_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_MAX32620FTHR/TARGET_Maxim/TARGET_MAX32620C/device/trim_regs.h@167:84c0a372a020 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-05-02 16:15:59 -0500 (Mon, 02 May 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 22594 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_TRIM_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_TRIM_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 /*
AnnaBridge 167:84c0a372a020 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 65 access to each register in module.
AnnaBridge 167:84c0a372a020 66 */
AnnaBridge 167:84c0a372a020 67
AnnaBridge 167:84c0a372a020 68 /* Offset Register Description
AnnaBridge 167:84c0a372a020 69 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 70 typedef struct {
AnnaBridge 167:84c0a372a020 71 __RO uint32_t rsv000[10]; /* 0x0000-0x0024 */
AnnaBridge 167:84c0a372a020 72 __IO uint32_t reg10_mem_size; /* 0x0028 Shadow Trim for Flash and SRAM Memory Size */
AnnaBridge 167:84c0a372a020 73 __IO uint32_t reg11_adc_trim0; /* 0x002C Shadow Trim for ADC R0 */
AnnaBridge 167:84c0a372a020 74 __IO uint32_t reg12_adc_trim1; /* 0x0030 Shadow Trim for ADC R1 */
AnnaBridge 167:84c0a372a020 75 __IO uint32_t for_pwr_reg5; /* 0x0034 Shadow Trim for PWRSEQ Register REG5 */
AnnaBridge 167:84c0a372a020 76 __IO uint32_t for_pwr_reg6; /* 0x0038 Shadow Trim for PWRSEQ Register REG6 */
AnnaBridge 167:84c0a372a020 77 __IO uint32_t for_pwr_reg7; /* 0x003C Shadow Trim for PWRSEQ Register REG7 */
AnnaBridge 167:84c0a372a020 78 } mxc_trim_regs_t;
AnnaBridge 167:84c0a372a020 79
AnnaBridge 167:84c0a372a020 80
AnnaBridge 167:84c0a372a020 81 /*
AnnaBridge 167:84c0a372a020 82 Register offsets for module TRIM.
AnnaBridge 167:84c0a372a020 83 */
AnnaBridge 167:84c0a372a020 84
AnnaBridge 167:84c0a372a020 85 #define MXC_R_TRIM_OFFS_REG10_MEM_SIZE ((uint32_t)0x00000028UL)
AnnaBridge 167:84c0a372a020 86 #define MXC_R_TRIM_OFFS_REG11_ADC_TRIM0 ((uint32_t)0x0000002CUL)
AnnaBridge 167:84c0a372a020 87 #define MXC_R_TRIM_OFFS_REG12_ADC_TRIM1 ((uint32_t)0x00000030UL)
AnnaBridge 167:84c0a372a020 88 #define MXC_R_TRIM_OFFS_FOR_PWR_REG5 ((uint32_t)0x00000034UL)
AnnaBridge 167:84c0a372a020 89 #define MXC_R_TRIM_OFFS_FOR_PWR_REG6 ((uint32_t)0x00000038UL)
AnnaBridge 167:84c0a372a020 90 #define MXC_R_TRIM_OFFS_FOR_PWR_REG7 ((uint32_t)0x0000003CUL)
AnnaBridge 167:84c0a372a020 91
AnnaBridge 167:84c0a372a020 92
AnnaBridge 167:84c0a372a020 93 /*
AnnaBridge 167:84c0a372a020 94 Field positions and masks for module TRIM.
AnnaBridge 167:84c0a372a020 95 */
AnnaBridge 167:84c0a372a020 96
AnnaBridge 167:84c0a372a020 97 #define MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS 0
AnnaBridge 167:84c0a372a020 98 #define MXC_F_TRIM_REG10_MEM_SIZE_SRAM ((uint32_t)(0x00000003UL << MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS))
AnnaBridge 167:84c0a372a020 99 #define MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS 2
AnnaBridge 167:84c0a372a020 100 #define MXC_F_TRIM_REG10_MEM_SIZE_FLASH ((uint32_t)(0x00000007UL << MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS))
AnnaBridge 167:84c0a372a020 101
AnnaBridge 167:84c0a372a020 102 #define MXC_V_TRIM_REG10_MEM_SRAM_FULL_SIZE ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 103 #define MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 104 #define MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 105
AnnaBridge 167:84c0a372a020 106 #define MXC_V_TRIM_REG10_MEM_FLASH_FULL_SIZE ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 107 #define MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 108 #define MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 109 #define MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 110 #define MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE ((uint32_t)(0x00000004UL))
AnnaBridge 167:84c0a372a020 111
AnnaBridge 167:84c0a372a020 112 #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS 0
AnnaBridge 167:84c0a372a020 113 #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS))
AnnaBridge 167:84c0a372a020 114 #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS 16
AnnaBridge 167:84c0a372a020 115 #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS))
AnnaBridge 167:84c0a372a020 116
AnnaBridge 167:84c0a372a020 117 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS 0
AnnaBridge 167:84c0a372a020 118 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS))
AnnaBridge 167:84c0a372a020 119 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS 16
AnnaBridge 167:84c0a372a020 120 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS))
AnnaBridge 167:84c0a372a020 121 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS 28
AnnaBridge 167:84c0a372a020 122 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC ((uint32_t)(0x0000000FUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS))
AnnaBridge 167:84c0a372a020 123
AnnaBridge 167:84c0a372a020 124
AnnaBridge 167:84c0a372a020 125
AnnaBridge 167:84c0a372a020 126 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 127 }
AnnaBridge 167:84c0a372a020 128 #endif
AnnaBridge 167:84c0a372a020 129
AnnaBridge 167:84c0a372a020 130 #endif /* _MXC_TRIM_REGS_H_ */
AnnaBridge 167:84c0a372a020 131