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TARGET_MAX32620FTHR/TOOLCHAIN_ARM_STD/i2cs_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_MAX32620FTHR/TARGET_Maxim/TARGET_MAX32620C/device/i2cs_regs.h@167:84c0a372a020 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 21839 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_I2CS_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_I2CS_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 /*
AnnaBridge 167:84c0a372a020 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 65 access to each register in module.
AnnaBridge 167:84c0a372a020 66 */
AnnaBridge 167:84c0a372a020 67
AnnaBridge 167:84c0a372a020 68 /* Offset Register Description
AnnaBridge 167:84c0a372a020 69 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 70 typedef struct {
AnnaBridge 167:84c0a372a020 71 __IO uint32_t clk_div; /* 0x0000 I2C Slave Clock Divisor Control */
AnnaBridge 167:84c0a372a020 72 __IO uint32_t dev_id; /* 0x0004 I2C Slave Device ID Register */
AnnaBridge 167:84c0a372a020 73 __IO uint32_t intfl; /* 0x0008 I2CS Interrupt Flags */
AnnaBridge 167:84c0a372a020 74 __IO uint32_t inten; /* 0x000C I2CS Interrupt Enable/Disable Controls */
AnnaBridge 167:84c0a372a020 75 __IO uint32_t data_byte[32]; /* 0x0010-0x008C I2CS Data Byte */
AnnaBridge 167:84c0a372a020 76 } mxc_i2cs_regs_t;
AnnaBridge 167:84c0a372a020 77
AnnaBridge 167:84c0a372a020 78
AnnaBridge 167:84c0a372a020 79 /*
AnnaBridge 167:84c0a372a020 80 Register offsets for module I2CS.
AnnaBridge 167:84c0a372a020 81 */
AnnaBridge 167:84c0a372a020 82
AnnaBridge 167:84c0a372a020 83 #define MXC_R_I2CS_OFFS_CLK_DIV ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 84 #define MXC_R_I2CS_OFFS_DEV_ID ((uint32_t)0x00000004UL)
AnnaBridge 167:84c0a372a020 85 #define MXC_R_I2CS_OFFS_INTFL ((uint32_t)0x00000008UL)
AnnaBridge 167:84c0a372a020 86 #define MXC_R_I2CS_OFFS_INTEN ((uint32_t)0x0000000CUL)
AnnaBridge 167:84c0a372a020 87 #define MXC_R_I2CS_OFFS_DATA_BYTE ((uint32_t)0x00000010UL)
AnnaBridge 167:84c0a372a020 88
AnnaBridge 167:84c0a372a020 89
AnnaBridge 167:84c0a372a020 90 /*
AnnaBridge 167:84c0a372a020 91 Field positions and masks for module I2CS.
AnnaBridge 167:84c0a372a020 92 */
AnnaBridge 167:84c0a372a020 93
AnnaBridge 167:84c0a372a020 94 #define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS 0
AnnaBridge 167:84c0a372a020 95 #define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS))
AnnaBridge 167:84c0a372a020 96
AnnaBridge 167:84c0a372a020 97 #define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS 0
AnnaBridge 167:84c0a372a020 98 #define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID ((uint32_t)(0x000003FFUL << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS))
AnnaBridge 167:84c0a372a020 99 #define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS 12
AnnaBridge 167:84c0a372a020 100 #define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS))
AnnaBridge 167:84c0a372a020 101 #define MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS 14
AnnaBridge 167:84c0a372a020 102 #define MXC_F_I2CS_DEV_ID_SLAVE_RESET ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS))
AnnaBridge 167:84c0a372a020 103
AnnaBridge 167:84c0a372a020 104 #define MXC_F_I2CS_INTFL_BYTE0_POS 0
AnnaBridge 167:84c0a372a020 105 #define MXC_F_I2CS_INTFL_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE0_POS))
AnnaBridge 167:84c0a372a020 106 #define MXC_F_I2CS_INTFL_BYTE1_POS 1
AnnaBridge 167:84c0a372a020 107 #define MXC_F_I2CS_INTFL_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE1_POS))
AnnaBridge 167:84c0a372a020 108 #define MXC_F_I2CS_INTFL_BYTE2_POS 2
AnnaBridge 167:84c0a372a020 109 #define MXC_F_I2CS_INTFL_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE2_POS))
AnnaBridge 167:84c0a372a020 110 #define MXC_F_I2CS_INTFL_BYTE3_POS 3
AnnaBridge 167:84c0a372a020 111 #define MXC_F_I2CS_INTFL_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE3_POS))
AnnaBridge 167:84c0a372a020 112 #define MXC_F_I2CS_INTFL_BYTE4_POS 4
AnnaBridge 167:84c0a372a020 113 #define MXC_F_I2CS_INTFL_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE4_POS))
AnnaBridge 167:84c0a372a020 114 #define MXC_F_I2CS_INTFL_BYTE5_POS 5
AnnaBridge 167:84c0a372a020 115 #define MXC_F_I2CS_INTFL_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE5_POS))
AnnaBridge 167:84c0a372a020 116 #define MXC_F_I2CS_INTFL_BYTE6_POS 6
AnnaBridge 167:84c0a372a020 117 #define MXC_F_I2CS_INTFL_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE6_POS))
AnnaBridge 167:84c0a372a020 118 #define MXC_F_I2CS_INTFL_BYTE7_POS 7
AnnaBridge 167:84c0a372a020 119 #define MXC_F_I2CS_INTFL_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE7_POS))
AnnaBridge 167:84c0a372a020 120 #define MXC_F_I2CS_INTFL_BYTE8_POS 8
AnnaBridge 167:84c0a372a020 121 #define MXC_F_I2CS_INTFL_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE8_POS))
AnnaBridge 167:84c0a372a020 122 #define MXC_F_I2CS_INTFL_BYTE9_POS 9
AnnaBridge 167:84c0a372a020 123 #define MXC_F_I2CS_INTFL_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE9_POS))
AnnaBridge 167:84c0a372a020 124 #define MXC_F_I2CS_INTFL_BYTE10_POS 10
AnnaBridge 167:84c0a372a020 125 #define MXC_F_I2CS_INTFL_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE10_POS))
AnnaBridge 167:84c0a372a020 126 #define MXC_F_I2CS_INTFL_BYTE11_POS 11
AnnaBridge 167:84c0a372a020 127 #define MXC_F_I2CS_INTFL_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE11_POS))
AnnaBridge 167:84c0a372a020 128 #define MXC_F_I2CS_INTFL_BYTE12_POS 12
AnnaBridge 167:84c0a372a020 129 #define MXC_F_I2CS_INTFL_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE12_POS))
AnnaBridge 167:84c0a372a020 130 #define MXC_F_I2CS_INTFL_BYTE13_POS 13
AnnaBridge 167:84c0a372a020 131 #define MXC_F_I2CS_INTFL_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE13_POS))
AnnaBridge 167:84c0a372a020 132 #define MXC_F_I2CS_INTFL_BYTE14_POS 14
AnnaBridge 167:84c0a372a020 133 #define MXC_F_I2CS_INTFL_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE14_POS))
AnnaBridge 167:84c0a372a020 134 #define MXC_F_I2CS_INTFL_BYTE15_POS 15
AnnaBridge 167:84c0a372a020 135 #define MXC_F_I2CS_INTFL_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE15_POS))
AnnaBridge 167:84c0a372a020 136 #define MXC_F_I2CS_INTFL_BYTE16_POS 16
AnnaBridge 167:84c0a372a020 137 #define MXC_F_I2CS_INTFL_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE16_POS))
AnnaBridge 167:84c0a372a020 138 #define MXC_F_I2CS_INTFL_BYTE17_POS 17
AnnaBridge 167:84c0a372a020 139 #define MXC_F_I2CS_INTFL_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE17_POS))
AnnaBridge 167:84c0a372a020 140 #define MXC_F_I2CS_INTFL_BYTE18_POS 18
AnnaBridge 167:84c0a372a020 141 #define MXC_F_I2CS_INTFL_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE18_POS))
AnnaBridge 167:84c0a372a020 142 #define MXC_F_I2CS_INTFL_BYTE19_POS 19
AnnaBridge 167:84c0a372a020 143 #define MXC_F_I2CS_INTFL_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE19_POS))
AnnaBridge 167:84c0a372a020 144 #define MXC_F_I2CS_INTFL_BYTE20_POS 20
AnnaBridge 167:84c0a372a020 145 #define MXC_F_I2CS_INTFL_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE20_POS))
AnnaBridge 167:84c0a372a020 146 #define MXC_F_I2CS_INTFL_BYTE21_POS 21
AnnaBridge 167:84c0a372a020 147 #define MXC_F_I2CS_INTFL_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE21_POS))
AnnaBridge 167:84c0a372a020 148 #define MXC_F_I2CS_INTFL_BYTE22_POS 22
AnnaBridge 167:84c0a372a020 149 #define MXC_F_I2CS_INTFL_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE22_POS))
AnnaBridge 167:84c0a372a020 150 #define MXC_F_I2CS_INTFL_BYTE23_POS 23
AnnaBridge 167:84c0a372a020 151 #define MXC_F_I2CS_INTFL_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE23_POS))
AnnaBridge 167:84c0a372a020 152 #define MXC_F_I2CS_INTFL_BYTE24_POS 24
AnnaBridge 167:84c0a372a020 153 #define MXC_F_I2CS_INTFL_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE24_POS))
AnnaBridge 167:84c0a372a020 154 #define MXC_F_I2CS_INTFL_BYTE25_POS 25
AnnaBridge 167:84c0a372a020 155 #define MXC_F_I2CS_INTFL_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE25_POS))
AnnaBridge 167:84c0a372a020 156 #define MXC_F_I2CS_INTFL_BYTE26_POS 26
AnnaBridge 167:84c0a372a020 157 #define MXC_F_I2CS_INTFL_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE26_POS))
AnnaBridge 167:84c0a372a020 158 #define MXC_F_I2CS_INTFL_BYTE27_POS 27
AnnaBridge 167:84c0a372a020 159 #define MXC_F_I2CS_INTFL_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE27_POS))
AnnaBridge 167:84c0a372a020 160 #define MXC_F_I2CS_INTFL_BYTE28_POS 28
AnnaBridge 167:84c0a372a020 161 #define MXC_F_I2CS_INTFL_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE28_POS))
AnnaBridge 167:84c0a372a020 162 #define MXC_F_I2CS_INTFL_BYTE29_POS 29
AnnaBridge 167:84c0a372a020 163 #define MXC_F_I2CS_INTFL_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE29_POS))
AnnaBridge 167:84c0a372a020 164 #define MXC_F_I2CS_INTFL_BYTE30_POS 30
AnnaBridge 167:84c0a372a020 165 #define MXC_F_I2CS_INTFL_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE30_POS))
AnnaBridge 167:84c0a372a020 166 #define MXC_F_I2CS_INTFL_BYTE31_POS 31
AnnaBridge 167:84c0a372a020 167 #define MXC_F_I2CS_INTFL_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE31_POS))
AnnaBridge 167:84c0a372a020 168
AnnaBridge 167:84c0a372a020 169 #define MXC_F_I2CS_INTEN_BYTE0_POS 0
AnnaBridge 167:84c0a372a020 170 #define MXC_F_I2CS_INTEN_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE0_POS))
AnnaBridge 167:84c0a372a020 171 #define MXC_F_I2CS_INTEN_BYTE1_POS 1
AnnaBridge 167:84c0a372a020 172 #define MXC_F_I2CS_INTEN_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE1_POS))
AnnaBridge 167:84c0a372a020 173 #define MXC_F_I2CS_INTEN_BYTE2_POS 2
AnnaBridge 167:84c0a372a020 174 #define MXC_F_I2CS_INTEN_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE2_POS))
AnnaBridge 167:84c0a372a020 175 #define MXC_F_I2CS_INTEN_BYTE3_POS 3
AnnaBridge 167:84c0a372a020 176 #define MXC_F_I2CS_INTEN_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE3_POS))
AnnaBridge 167:84c0a372a020 177 #define MXC_F_I2CS_INTEN_BYTE4_POS 4
AnnaBridge 167:84c0a372a020 178 #define MXC_F_I2CS_INTEN_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE4_POS))
AnnaBridge 167:84c0a372a020 179 #define MXC_F_I2CS_INTEN_BYTE5_POS 5
AnnaBridge 167:84c0a372a020 180 #define MXC_F_I2CS_INTEN_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE5_POS))
AnnaBridge 167:84c0a372a020 181 #define MXC_F_I2CS_INTEN_BYTE6_POS 6
AnnaBridge 167:84c0a372a020 182 #define MXC_F_I2CS_INTEN_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE6_POS))
AnnaBridge 167:84c0a372a020 183 #define MXC_F_I2CS_INTEN_BYTE7_POS 7
AnnaBridge 167:84c0a372a020 184 #define MXC_F_I2CS_INTEN_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE7_POS))
AnnaBridge 167:84c0a372a020 185 #define MXC_F_I2CS_INTEN_BYTE8_POS 8
AnnaBridge 167:84c0a372a020 186 #define MXC_F_I2CS_INTEN_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE8_POS))
AnnaBridge 167:84c0a372a020 187 #define MXC_F_I2CS_INTEN_BYTE9_POS 9
AnnaBridge 167:84c0a372a020 188 #define MXC_F_I2CS_INTEN_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE9_POS))
AnnaBridge 167:84c0a372a020 189 #define MXC_F_I2CS_INTEN_BYTE10_POS 10
AnnaBridge 167:84c0a372a020 190 #define MXC_F_I2CS_INTEN_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE10_POS))
AnnaBridge 167:84c0a372a020 191 #define MXC_F_I2CS_INTEN_BYTE11_POS 11
AnnaBridge 167:84c0a372a020 192 #define MXC_F_I2CS_INTEN_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE11_POS))
AnnaBridge 167:84c0a372a020 193 #define MXC_F_I2CS_INTEN_BYTE12_POS 12
AnnaBridge 167:84c0a372a020 194 #define MXC_F_I2CS_INTEN_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE12_POS))
AnnaBridge 167:84c0a372a020 195 #define MXC_F_I2CS_INTEN_BYTE13_POS 13
AnnaBridge 167:84c0a372a020 196 #define MXC_F_I2CS_INTEN_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE13_POS))
AnnaBridge 167:84c0a372a020 197 #define MXC_F_I2CS_INTEN_BYTE14_POS 14
AnnaBridge 167:84c0a372a020 198 #define MXC_F_I2CS_INTEN_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE14_POS))
AnnaBridge 167:84c0a372a020 199 #define MXC_F_I2CS_INTEN_BYTE15_POS 15
AnnaBridge 167:84c0a372a020 200 #define MXC_F_I2CS_INTEN_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE15_POS))
AnnaBridge 167:84c0a372a020 201 #define MXC_F_I2CS_INTEN_BYTE16_POS 16
AnnaBridge 167:84c0a372a020 202 #define MXC_F_I2CS_INTEN_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE16_POS))
AnnaBridge 167:84c0a372a020 203 #define MXC_F_I2CS_INTEN_BYTE17_POS 17
AnnaBridge 167:84c0a372a020 204 #define MXC_F_I2CS_INTEN_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE17_POS))
AnnaBridge 167:84c0a372a020 205 #define MXC_F_I2CS_INTEN_BYTE18_POS 18
AnnaBridge 167:84c0a372a020 206 #define MXC_F_I2CS_INTEN_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE18_POS))
AnnaBridge 167:84c0a372a020 207 #define MXC_F_I2CS_INTEN_BYTE19_POS 19
AnnaBridge 167:84c0a372a020 208 #define MXC_F_I2CS_INTEN_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE19_POS))
AnnaBridge 167:84c0a372a020 209 #define MXC_F_I2CS_INTEN_BYTE20_POS 20
AnnaBridge 167:84c0a372a020 210 #define MXC_F_I2CS_INTEN_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE20_POS))
AnnaBridge 167:84c0a372a020 211 #define MXC_F_I2CS_INTEN_BYTE21_POS 21
AnnaBridge 167:84c0a372a020 212 #define MXC_F_I2CS_INTEN_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE21_POS))
AnnaBridge 167:84c0a372a020 213 #define MXC_F_I2CS_INTEN_BYTE22_POS 22
AnnaBridge 167:84c0a372a020 214 #define MXC_F_I2CS_INTEN_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE22_POS))
AnnaBridge 167:84c0a372a020 215 #define MXC_F_I2CS_INTEN_BYTE23_POS 23
AnnaBridge 167:84c0a372a020 216 #define MXC_F_I2CS_INTEN_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE23_POS))
AnnaBridge 167:84c0a372a020 217 #define MXC_F_I2CS_INTEN_BYTE24_POS 24
AnnaBridge 167:84c0a372a020 218 #define MXC_F_I2CS_INTEN_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE24_POS))
AnnaBridge 167:84c0a372a020 219 #define MXC_F_I2CS_INTEN_BYTE25_POS 25
AnnaBridge 167:84c0a372a020 220 #define MXC_F_I2CS_INTEN_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE25_POS))
AnnaBridge 167:84c0a372a020 221 #define MXC_F_I2CS_INTEN_BYTE26_POS 26
AnnaBridge 167:84c0a372a020 222 #define MXC_F_I2CS_INTEN_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE26_POS))
AnnaBridge 167:84c0a372a020 223 #define MXC_F_I2CS_INTEN_BYTE27_POS 27
AnnaBridge 167:84c0a372a020 224 #define MXC_F_I2CS_INTEN_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE27_POS))
AnnaBridge 167:84c0a372a020 225 #define MXC_F_I2CS_INTEN_BYTE28_POS 28
AnnaBridge 167:84c0a372a020 226 #define MXC_F_I2CS_INTEN_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE28_POS))
AnnaBridge 167:84c0a372a020 227 #define MXC_F_I2CS_INTEN_BYTE29_POS 29
AnnaBridge 167:84c0a372a020 228 #define MXC_F_I2CS_INTEN_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE29_POS))
AnnaBridge 167:84c0a372a020 229 #define MXC_F_I2CS_INTEN_BYTE30_POS 30
AnnaBridge 167:84c0a372a020 230 #define MXC_F_I2CS_INTEN_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE30_POS))
AnnaBridge 167:84c0a372a020 231 #define MXC_F_I2CS_INTEN_BYTE31_POS 31
AnnaBridge 167:84c0a372a020 232 #define MXC_F_I2CS_INTEN_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE31_POS))
AnnaBridge 167:84c0a372a020 233
AnnaBridge 167:84c0a372a020 234 #define MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS 0
AnnaBridge 167:84c0a372a020 235 #define MXC_F_I2CS_DATA_BYTE_DATA_FIELD ((uint32_t)(0x000000FFUL << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS))
AnnaBridge 167:84c0a372a020 236 #define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS 8
AnnaBridge 167:84c0a372a020 237 #define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS))
AnnaBridge 167:84c0a372a020 238 #define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS 9
AnnaBridge 167:84c0a372a020 239 #define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS))
AnnaBridge 167:84c0a372a020 240
AnnaBridge 167:84c0a372a020 241
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AnnaBridge 167:84c0a372a020 243 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 244 }
AnnaBridge 167:84c0a372a020 245 #endif
AnnaBridge 167:84c0a372a020 246
AnnaBridge 167:84c0a372a020 247 #endif /* _MXC_I2CS_REGS_H_ */
AnnaBridge 167:84c0a372a020 248