mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32600MBED/TOOLCHAIN_IAR/pwrseq_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_PWRSEQ_REGS_H
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_PWRSEQ_REGS_H
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file pwrseq_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup pwrseq PWRSEQ
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 50 ====== ================================================= */
AnnaBridge 171:3a7713b1edbc 51 typedef struct {
AnnaBridge 171:3a7713b1edbc 52 __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
AnnaBridge 171:3a7713b1edbc 53 __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
AnnaBridge 171:3a7713b1edbc 54 __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
AnnaBridge 171:3a7713b1edbc 55 __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
AnnaBridge 171:3a7713b1edbc 56 __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 */
AnnaBridge 171:3a7713b1edbc 57 __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
AnnaBridge 171:3a7713b1edbc 58 __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
AnnaBridge 171:3a7713b1edbc 59 __I uint32_t rsv001C; /* 0x001C */
AnnaBridge 171:3a7713b1edbc 60 __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
AnnaBridge 171:3a7713b1edbc 61 __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
AnnaBridge 171:3a7713b1edbc 62 } mxc_pwrseq_regs_t;
AnnaBridge 171:3a7713b1edbc 63
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /*
AnnaBridge 171:3a7713b1edbc 66 Register offsets for module PWRSEQ.
AnnaBridge 171:3a7713b1edbc 67 */
AnnaBridge 171:3a7713b1edbc 68 #define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 69 #define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 70 #define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 71 #define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 72 #define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
AnnaBridge 171:3a7713b1edbc 73 #define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
AnnaBridge 171:3a7713b1edbc 74 #define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
AnnaBridge 171:3a7713b1edbc 75 #define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
AnnaBridge 171:3a7713b1edbc 76 #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 /*
AnnaBridge 171:3a7713b1edbc 80 Field positions and masks for module PWRSEQ.
AnnaBridge 171:3a7713b1edbc 81 */
AnnaBridge 171:3a7713b1edbc 82 #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
AnnaBridge 171:3a7713b1edbc 83 #define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
AnnaBridge 171:3a7713b1edbc 84 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
AnnaBridge 171:3a7713b1edbc 85 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
AnnaBridge 171:3a7713b1edbc 86 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
AnnaBridge 171:3a7713b1edbc 87 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
AnnaBridge 171:3a7713b1edbc 88 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS 3
AnnaBridge 171:3a7713b1edbc 89 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 90 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS 4
AnnaBridge 171:3a7713b1edbc 91 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 92 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS 5
AnnaBridge 171:3a7713b1edbc 93 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 94 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS 6
AnnaBridge 171:3a7713b1edbc 95 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 96 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
AnnaBridge 171:3a7713b1edbc 97 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 98 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
AnnaBridge 171:3a7713b1edbc 99 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 100 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
AnnaBridge 171:3a7713b1edbc 101 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 102 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
AnnaBridge 171:3a7713b1edbc 103 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 104 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
AnnaBridge 171:3a7713b1edbc 105 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 106 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
AnnaBridge 171:3a7713b1edbc 107 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 108 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS 13
AnnaBridge 171:3a7713b1edbc 109 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 110 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS 14
AnnaBridge 171:3a7713b1edbc 111 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 112 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS 15
AnnaBridge 171:3a7713b1edbc 113 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 114 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS 16
AnnaBridge 171:3a7713b1edbc 115 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 116 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
AnnaBridge 171:3a7713b1edbc 117 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 118 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS 18
AnnaBridge 171:3a7713b1edbc 119 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 120 #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS 19
AnnaBridge 171:3a7713b1edbc 121 #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS))
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS 0
AnnaBridge 171:3a7713b1edbc 124 #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS))
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS 8
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS))
AnnaBridge 171:3a7713b1edbc 127 #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS 9
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS))
AnnaBridge 171:3a7713b1edbc 129 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS 10
AnnaBridge 171:3a7713b1edbc 130 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS))
AnnaBridge 171:3a7713b1edbc 131 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS 11
AnnaBridge 171:3a7713b1edbc 132 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS))
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS 12
AnnaBridge 171:3a7713b1edbc 134 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS))
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS 13
AnnaBridge 171:3a7713b1edbc 136 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS))
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS 14
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS))
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_PWRSEQ_REG2_PWR_RST3_POS 0
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_PWRSEQ_REG2_PWR_RST3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS))
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_PWRSEQ_REG2_PWR_W3_POS 5
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_PWRSEQ_REG2_PWR_W3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS))
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_PWRSEQ_REG2_PWR_W1_POS 10
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_PWRSEQ_REG2_PWR_W1 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS))
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS 15
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS))
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS 20
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_PWRSEQ_REG2_PWR_WRTC ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS))
AnnaBridge 171:3a7713b1edbc 150 #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS 25
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS))
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS 3
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS))
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS 5
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS))
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS 8
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS))
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS 10
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS))
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 13
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 15
AnnaBridge 171:3a7713b1edbc 166 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS 16
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS))
AnnaBridge 171:3a7713b1edbc 169 #define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS 17
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_PWRSEQ_REG3_PWR_BO_TC ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS))
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
AnnaBridge 171:3a7713b1edbc 175 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
AnnaBridge 171:3a7713b1edbc 176 #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS 2
AnnaBridge 171:3a7713b1edbc 177 #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS))
AnnaBridge 171:3a7713b1edbc 178 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
AnnaBridge 171:3a7713b1edbc 179 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
AnnaBridge 171:3a7713b1edbc 180 #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS 4
AnnaBridge 171:3a7713b1edbc 181 #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS))
AnnaBridge 171:3a7713b1edbc 182 #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS 5
AnnaBridge 171:3a7713b1edbc 183 #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS))
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS 6
AnnaBridge 171:3a7713b1edbc 185 #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS))
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
AnnaBridge 171:3a7713b1edbc 188 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
AnnaBridge 171:3a7713b1edbc 189 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS 6
AnnaBridge 171:3a7713b1edbc 190 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8 ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS))
AnnaBridge 171:3a7713b1edbc 191 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS 10
AnnaBridge 171:3a7713b1edbc 192 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS))
AnnaBridge 171:3a7713b1edbc 193 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS 15
AnnaBridge 171:3a7713b1edbc 194 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS))
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
AnnaBridge 171:3a7713b1edbc 197 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
AnnaBridge 171:3a7713b1edbc 198 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
AnnaBridge 171:3a7713b1edbc 199 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
AnnaBridge 171:3a7713b1edbc 200 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
AnnaBridge 171:3a7713b1edbc 201 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
AnnaBridge 171:3a7713b1edbc 204 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
AnnaBridge 171:3a7713b1edbc 205 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
AnnaBridge 171:3a7713b1edbc 206 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
AnnaBridge 171:3a7713b1edbc 207 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS 2
AnnaBridge 171:3a7713b1edbc 208 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 209 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
AnnaBridge 171:3a7713b1edbc 210 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 211 #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS 4
AnnaBridge 171:3a7713b1edbc 212 #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 213 #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS 5
AnnaBridge 171:3a7713b1edbc 214 #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 215 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS 6
AnnaBridge 171:3a7713b1edbc 216 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS))
AnnaBridge 171:3a7713b1edbc 217 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS 7
AnnaBridge 171:3a7713b1edbc 218 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS))
AnnaBridge 171:3a7713b1edbc 219 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS 8
AnnaBridge 171:3a7713b1edbc 220 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS))
AnnaBridge 171:3a7713b1edbc 221 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS 9
AnnaBridge 171:3a7713b1edbc 222 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS))
AnnaBridge 171:3a7713b1edbc 223 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS 10
AnnaBridge 171:3a7713b1edbc 224 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS))
AnnaBridge 171:3a7713b1edbc 225 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS 11
AnnaBridge 171:3a7713b1edbc 226 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS))
AnnaBridge 171:3a7713b1edbc 227 #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS 12
AnnaBridge 171:3a7713b1edbc 228 #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 229 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 13
AnnaBridge 171:3a7713b1edbc 230 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
AnnaBridge 171:3a7713b1edbc 231 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 14
AnnaBridge 171:3a7713b1edbc 232 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
AnnaBridge 171:3a7713b1edbc 233 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 15
AnnaBridge 171:3a7713b1edbc 234 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
AnnaBridge 171:3a7713b1edbc 235 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 16
AnnaBridge 171:3a7713b1edbc 236 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
AnnaBridge 171:3a7713b1edbc 237 #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS 17
AnnaBridge 171:3a7713b1edbc 238 #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS))
AnnaBridge 171:3a7713b1edbc 239 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
AnnaBridge 171:3a7713b1edbc 240 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 241 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
AnnaBridge 171:3a7713b1edbc 242 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 243 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS 20
AnnaBridge 171:3a7713b1edbc 244 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS))
AnnaBridge 171:3a7713b1edbc 245 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS 21
AnnaBridge 171:3a7713b1edbc 246 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS))
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
AnnaBridge 171:3a7713b1edbc 249 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
AnnaBridge 171:3a7713b1edbc 250 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS 2
AnnaBridge 171:3a7713b1edbc 251 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 252 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
AnnaBridge 171:3a7713b1edbc 253 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 254 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS 4
AnnaBridge 171:3a7713b1edbc 255 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 256 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS 5
AnnaBridge 171:3a7713b1edbc 257 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 258 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS 6
AnnaBridge 171:3a7713b1edbc 259 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS))
AnnaBridge 171:3a7713b1edbc 260 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS 7
AnnaBridge 171:3a7713b1edbc 261 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS))
AnnaBridge 171:3a7713b1edbc 262 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS 8
AnnaBridge 171:3a7713b1edbc 263 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS))
AnnaBridge 171:3a7713b1edbc 264 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS 9
AnnaBridge 171:3a7713b1edbc 265 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS))
AnnaBridge 171:3a7713b1edbc 266 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS 10
AnnaBridge 171:3a7713b1edbc 267 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS))
AnnaBridge 171:3a7713b1edbc 268 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS 11
AnnaBridge 171:3a7713b1edbc 269 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS))
AnnaBridge 171:3a7713b1edbc 270 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS 12
AnnaBridge 171:3a7713b1edbc 271 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 272 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 13
AnnaBridge 171:3a7713b1edbc 273 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
AnnaBridge 171:3a7713b1edbc 274 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 14
AnnaBridge 171:3a7713b1edbc 275 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
AnnaBridge 171:3a7713b1edbc 276 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 15
AnnaBridge 171:3a7713b1edbc 277 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
AnnaBridge 171:3a7713b1edbc 278 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 16
AnnaBridge 171:3a7713b1edbc 279 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
AnnaBridge 171:3a7713b1edbc 280 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS 17
AnnaBridge 171:3a7713b1edbc 281 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS))
AnnaBridge 171:3a7713b1edbc 282 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
AnnaBridge 171:3a7713b1edbc 283 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 284 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
AnnaBridge 171:3a7713b1edbc 285 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 286 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS 20
AnnaBridge 171:3a7713b1edbc 287 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS))
AnnaBridge 171:3a7713b1edbc 288 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS 21
AnnaBridge 171:3a7713b1edbc 289 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS))
AnnaBridge 171:3a7713b1edbc 290
AnnaBridge 171:3a7713b1edbc 291 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 292 }
AnnaBridge 171:3a7713b1edbc 293 #endif
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 /**
AnnaBridge 171:3a7713b1edbc 296 * @}
AnnaBridge 171:3a7713b1edbc 297 */
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 #endif /* _MXC_PWRSEQ_REGS_H */