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TARGET_MAX32600MBED/TOOLCHAIN_IAR/pwrman_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /******************************************************************************* |
| AnnaBridge | 171:3a7713b1edbc | 2 | * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. |
| AnnaBridge | 171:3a7713b1edbc | 3 | * |
| AnnaBridge | 171:3a7713b1edbc | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| AnnaBridge | 171:3a7713b1edbc | 5 | * copy of this software and associated documentation files (the "Software"), |
| AnnaBridge | 171:3a7713b1edbc | 6 | * to deal in the Software without restriction, including without limitation |
| AnnaBridge | 171:3a7713b1edbc | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| AnnaBridge | 171:3a7713b1edbc | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| AnnaBridge | 171:3a7713b1edbc | 9 | * Software is furnished to do so, subject to the following conditions: |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * The above copyright notice and this permission notice shall be included |
| AnnaBridge | 171:3a7713b1edbc | 12 | * in all copies or substantial portions of the Software. |
| AnnaBridge | 171:3a7713b1edbc | 13 | * |
| AnnaBridge | 171:3a7713b1edbc | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| AnnaBridge | 171:3a7713b1edbc | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| AnnaBridge | 171:3a7713b1edbc | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| AnnaBridge | 171:3a7713b1edbc | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| AnnaBridge | 171:3a7713b1edbc | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| AnnaBridge | 171:3a7713b1edbc | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| AnnaBridge | 171:3a7713b1edbc | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| AnnaBridge | 171:3a7713b1edbc | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| AnnaBridge | 171:3a7713b1edbc | 24 | * Products, Inc. Branding Policy. |
| AnnaBridge | 171:3a7713b1edbc | 25 | * |
| AnnaBridge | 171:3a7713b1edbc | 26 | * The mere transfer of this software does not imply any licenses |
| AnnaBridge | 171:3a7713b1edbc | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| AnnaBridge | 171:3a7713b1edbc | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| AnnaBridge | 171:3a7713b1edbc | 30 | * ownership rights. |
| AnnaBridge | 171:3a7713b1edbc | 31 | ******************************************************************************* |
| AnnaBridge | 171:3a7713b1edbc | 32 | */ |
| AnnaBridge | 171:3a7713b1edbc | 33 | |
| AnnaBridge | 171:3a7713b1edbc | 34 | #ifndef _MXC_PWRMAN_REGS_H_ |
| AnnaBridge | 171:3a7713b1edbc | 35 | #define _MXC_PWRMAN_REGS_H_ |
| AnnaBridge | 171:3a7713b1edbc | 36 | |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 38 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 39 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 40 | |
| AnnaBridge | 171:3a7713b1edbc | 41 | #include <stdint.h> |
| AnnaBridge | 171:3a7713b1edbc | 42 | |
| AnnaBridge | 171:3a7713b1edbc | 43 | /** |
| AnnaBridge | 171:3a7713b1edbc | 44 | * @file pwrman_regs.h |
| AnnaBridge | 171:3a7713b1edbc | 45 | * @addtogroup pwrman PWRMAN |
| AnnaBridge | 171:3a7713b1edbc | 46 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 47 | */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | |
| AnnaBridge | 171:3a7713b1edbc | 49 | /** |
| AnnaBridge | 171:3a7713b1edbc | 50 | * @brief Defines PAD Modes for Wake Up Detection. |
| AnnaBridge | 171:3a7713b1edbc | 51 | */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | typedef enum { |
| AnnaBridge | 171:3a7713b1edbc | 53 | /** WUD Mode for Selected PAD = Clear/Activate */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | MXC_E_PWRMAN_PAD_MODE_CLEAR_SET, |
| AnnaBridge | 171:3a7713b1edbc | 55 | /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO, |
| AnnaBridge | 171:3a7713b1edbc | 57 | /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */ |
| AnnaBridge | 171:3a7713b1edbc | 58 | MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO, |
| AnnaBridge | 171:3a7713b1edbc | 59 | /** WUD Mode for Selected PAD = No pad state change */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | MXC_E_PWRMAN_PAD_MODE_NONE |
| AnnaBridge | 171:3a7713b1edbc | 61 | } mxc_pwrman_pad_mode_t; |
| AnnaBridge | 171:3a7713b1edbc | 62 | |
| AnnaBridge | 171:3a7713b1edbc | 63 | /* Offset Register Description |
| AnnaBridge | 171:3a7713b1edbc | 64 | ====== =========================================== */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 66 | __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | __IO uint32_t intfl; /* 0x0004 Interrupt Flags */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */ |
| AnnaBridge | 171:3a7713b1edbc | 70 | __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | __I uint32_t rsv001C[5]; /* 0x001C */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | |
| AnnaBridge | 171:3a7713b1edbc | 75 | __IO uint32_t wud_seen0; /* 0x0030 Wake-up Detect Status for P0/P1/P2/P3 */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | __IO uint32_t wud_seen1; /* 0x0034 Wake-up Detect Status for P4/P5/P6/P7 */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | __IO uint32_t die_type; /* 0x0038 Die ID Register (Device Type) */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | __IO uint32_t base_part_num; /* 0x003C Base Part Number */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | } mxc_pwrman_regs_t; |
| AnnaBridge | 171:3a7713b1edbc | 83 | |
| AnnaBridge | 171:3a7713b1edbc | 84 | /* |
| AnnaBridge | 171:3a7713b1edbc | 85 | Register offsets for module PWRMAN. |
| AnnaBridge | 171:3a7713b1edbc | 86 | */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | #define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL) |
| AnnaBridge | 171:3a7713b1edbc | 88 | #define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL) |
| AnnaBridge | 171:3a7713b1edbc | 89 | #define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL) |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL) |
| AnnaBridge | 171:3a7713b1edbc | 91 | #define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL) |
| AnnaBridge | 171:3a7713b1edbc | 92 | #define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL) |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL) |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x00000030UL) |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000034UL) |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL) |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL) |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL) |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL) |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL) |
| AnnaBridge | 171:3a7713b1edbc | 101 | |
| AnnaBridge | 171:3a7713b1edbc | 102 | /* |
| AnnaBridge | 171:3a7713b1edbc | 103 | Field positions and masks for module PWRMAN. |
| AnnaBridge | 171:3a7713b1edbc | 104 | */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 110 | #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 111 | #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 17 |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 18 |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 19 |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21 |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22 |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31 |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 139 | |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define MXC_F_PWRMAN_INTFL_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define MXC_F_PWRMAN_INTFL_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 150 | |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define MXC_F_PWRMAN_INTEN_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define MXC_F_PWRMAN_INTEN_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 161 | |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 172 | |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 179 | |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7 |
| AnnaBridge | 171:3a7713b1edbc | 195 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11 |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13 |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14 |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15 |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17 |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18 |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19 |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21 |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22 |
| AnnaBridge | 171:3a7713b1edbc | 225 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23 |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25 |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26 |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27 |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28 |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29 |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30 |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31 |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 244 | |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7 |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11 |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13 |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14 |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15 |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17 |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18 |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19 |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21 |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22 |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23 |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25 |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26 |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27 |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 301 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28 |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29 |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30 |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31 |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 309 | |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS 28 |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 314 | |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 319 | |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31 |
| AnnaBridge | 171:3a7713b1edbc | 323 | #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 324 | |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 330 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 331 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 7 |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 342 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS 11 |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS 13 |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS 14 |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 15 |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS 17 |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS 18 |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS 19 |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 21 |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22 |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 23 |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 373 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 374 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 25 |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 377 | |
| AnnaBridge | 171:3a7713b1edbc | 378 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 379 | } |
| AnnaBridge | 171:3a7713b1edbc | 380 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 381 | |
| AnnaBridge | 171:3a7713b1edbc | 382 | /** |
| AnnaBridge | 171:3a7713b1edbc | 383 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 384 | */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | |
| AnnaBridge | 171:3a7713b1edbc | 386 | #endif /* _MXC_PWRMAN_REGS_H_ */ |
