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TARGET_MAX32600MBED/TOOLCHAIN_IAR/clkman_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_CLKMAN_REGS_H_
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_CLKMAN_REGS_H_
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file clkman_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup clkman CLKMAN
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /**
AnnaBridge 171:3a7713b1edbc 50 * @brief Defines clock input selections for the phase locked loop.
AnnaBridge 171:3a7713b1edbc 51 */
AnnaBridge 171:3a7713b1edbc 52 typedef enum {
AnnaBridge 171:3a7713b1edbc 53 /** Input select for high frequency crystal oscillator */
AnnaBridge 171:3a7713b1edbc 54 MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0,
AnnaBridge 171:3a7713b1edbc 55 /** Input select for 24MHz ring oscillator */
AnnaBridge 171:3a7713b1edbc 56 MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO,
AnnaBridge 171:3a7713b1edbc 57 } mxc_clkman_pll_input_select_t;
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /**
AnnaBridge 171:3a7713b1edbc 60 * @brief Defines clock input frequency for the phase locked loop.
AnnaBridge 171:3a7713b1edbc 61 */
AnnaBridge 171:3a7713b1edbc 62 typedef enum {
AnnaBridge 171:3a7713b1edbc 63 /** Input frequency of 24MHz */
AnnaBridge 171:3a7713b1edbc 64 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0,
AnnaBridge 171:3a7713b1edbc 65 /** Input frequency of 12MHz */
AnnaBridge 171:3a7713b1edbc 66 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ,
AnnaBridge 171:3a7713b1edbc 67 /** Input frequency of 8MHz */
AnnaBridge 171:3a7713b1edbc 68 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ,
AnnaBridge 171:3a7713b1edbc 69 } mxc_clkman_pll_divisor_select_t;
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /**
AnnaBridge 171:3a7713b1edbc 72 * @brief Defines terminal count for PLL stable.
AnnaBridge 171:3a7713b1edbc 73 */
AnnaBridge 171:3a7713b1edbc 74 typedef enum {
AnnaBridge 171:3a7713b1edbc 75 /** Clock stable after 2^8 = 256 clock cycles */
AnnaBridge 171:3a7713b1edbc 76 MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0,
AnnaBridge 171:3a7713b1edbc 77 /** Clock stable after 2^9 = 512 clock cycles */
AnnaBridge 171:3a7713b1edbc 78 MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS,
AnnaBridge 171:3a7713b1edbc 79 /** Clock stable after 2^10 = 1024 clock cycles */
AnnaBridge 171:3a7713b1edbc 80 MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS,
AnnaBridge 171:3a7713b1edbc 81 /** Clock stable after 2^11 = 2048 clock cycles */
AnnaBridge 171:3a7713b1edbc 82 MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS,
AnnaBridge 171:3a7713b1edbc 83 /** Clock stable after 2^12 = 4096 clock cycles */
AnnaBridge 171:3a7713b1edbc 84 MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS,
AnnaBridge 171:3a7713b1edbc 85 /** Clock stable after 2^13 = 8192 clock cycles */
AnnaBridge 171:3a7713b1edbc 86 MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS,
AnnaBridge 171:3a7713b1edbc 87 /** Clock stable after 2^14 = 16384 clock cycles */
AnnaBridge 171:3a7713b1edbc 88 MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS,
AnnaBridge 171:3a7713b1edbc 89 /** Clock stable after 2^15 = 32768 clock cycles */
AnnaBridge 171:3a7713b1edbc 90 MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS,
AnnaBridge 171:3a7713b1edbc 91 /** Clock stable after 2^16 = 65536 clock cycles */
AnnaBridge 171:3a7713b1edbc 92 MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS,
AnnaBridge 171:3a7713b1edbc 93 /** Clock stable after 2^17 = 131072 clock cycles */
AnnaBridge 171:3a7713b1edbc 94 MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS,
AnnaBridge 171:3a7713b1edbc 95 /** Clock stable after 2^18 = 262144 clock cycles */
AnnaBridge 171:3a7713b1edbc 96 MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS,
AnnaBridge 171:3a7713b1edbc 97 /** Clock stable after 2^19 = 524288 clock cycles */
AnnaBridge 171:3a7713b1edbc 98 MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS,
AnnaBridge 171:3a7713b1edbc 99 /** Clock stable after 2^20 = 1048576 clock cycles */
AnnaBridge 171:3a7713b1edbc 100 MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS,
AnnaBridge 171:3a7713b1edbc 101 /** Clock stable after 2^21 = 2097152 clock cycles */
AnnaBridge 171:3a7713b1edbc 102 MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS,
AnnaBridge 171:3a7713b1edbc 103 /** Clock stable after 2^22 = 4194304 clock cycles */
AnnaBridge 171:3a7713b1edbc 104 MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS,
AnnaBridge 171:3a7713b1edbc 105 /** Clock stable after 2^23 = 8388608 clock cycles */
AnnaBridge 171:3a7713b1edbc 106 MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS
AnnaBridge 171:3a7713b1edbc 107 } mxc_clkman_stability_count_t;
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109 /**
AnnaBridge 171:3a7713b1edbc 110 * @brief Defines clock source selections for system clock.
AnnaBridge 171:3a7713b1edbc 111 */
AnnaBridge 171:3a7713b1edbc 112 typedef enum {
AnnaBridge 171:3a7713b1edbc 113 /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */
AnnaBridge 171:3a7713b1edbc 114 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0,
AnnaBridge 171:3a7713b1edbc 115 /** Clock select for 24MHz ring oscillator */
AnnaBridge 171:3a7713b1edbc 116 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO,
AnnaBridge 171:3a7713b1edbc 117 /** Clock select for high frequency crystal oscillator */
AnnaBridge 171:3a7713b1edbc 118 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX,
AnnaBridge 171:3a7713b1edbc 119 /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */
AnnaBridge 171:3a7713b1edbc 120 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2
AnnaBridge 171:3a7713b1edbc 121 } mxc_clkman_system_source_select_t;
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 /**
AnnaBridge 171:3a7713b1edbc 124 * @brief Defines clock source selections for analog to digital converter clock.
AnnaBridge 171:3a7713b1edbc 125 */
AnnaBridge 171:3a7713b1edbc 126 typedef enum {
AnnaBridge 171:3a7713b1edbc 127 /** Clock select for system clock frequency */
AnnaBridge 171:3a7713b1edbc 128 MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0,
AnnaBridge 171:3a7713b1edbc 129 /** Clock select for 8MHz phase locked loop output */
AnnaBridge 171:3a7713b1edbc 130 MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ,
AnnaBridge 171:3a7713b1edbc 131 /** Clock select for high frequency crystal oscillator */
AnnaBridge 171:3a7713b1edbc 132 MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX,
AnnaBridge 171:3a7713b1edbc 133 /** Clock select for 24MHz ring oscillator */
AnnaBridge 171:3a7713b1edbc 134 MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO,
AnnaBridge 171:3a7713b1edbc 135 } mxc_clkman_adc_source_select_t;
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 /**
AnnaBridge 171:3a7713b1edbc 138 * @brief Defines clock source selections for watchdog timer clock.
AnnaBridge 171:3a7713b1edbc 139 */
AnnaBridge 171:3a7713b1edbc 140 typedef enum {
AnnaBridge 171:3a7713b1edbc 141 /** Clock select for system clock frequency */
AnnaBridge 171:3a7713b1edbc 142 MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0,
AnnaBridge 171:3a7713b1edbc 143 /** Clock select for 8MHz phase locked loop output */
AnnaBridge 171:3a7713b1edbc 144 MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC,
AnnaBridge 171:3a7713b1edbc 145 /** Clock select for high frequency crystal oscillator */
AnnaBridge 171:3a7713b1edbc 146 MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO,
AnnaBridge 171:3a7713b1edbc 147 /** Clock select for 24MHz ring oscillator */
AnnaBridge 171:3a7713b1edbc 148 MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO,
AnnaBridge 171:3a7713b1edbc 149 } mxc_clkman_wdt_source_select_t;
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 /**
AnnaBridge 171:3a7713b1edbc 152 * @brief Defines clock scales for various clocks.
AnnaBridge 171:3a7713b1edbc 153 */
AnnaBridge 171:3a7713b1edbc 154 typedef enum {
AnnaBridge 171:3a7713b1edbc 155 /** Clock disabled */
AnnaBridge 171:3a7713b1edbc 156 MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0,
AnnaBridge 171:3a7713b1edbc 157 /** Clock enabled */
AnnaBridge 171:3a7713b1edbc 158 MXC_E_CLKMAN_CLK_SCALE_ENABLED,
AnnaBridge 171:3a7713b1edbc 159 /** Clock scale for dividing by 2 */
AnnaBridge 171:3a7713b1edbc 160 MXC_E_CLKMAN_CLK_SCALE_DIV_2,
AnnaBridge 171:3a7713b1edbc 161 /** Clock scale for dividing by 4 */
AnnaBridge 171:3a7713b1edbc 162 MXC_E_CLKMAN_CLK_SCALE_DIV_4,
AnnaBridge 171:3a7713b1edbc 163 /** Clock scale for dividing by 8 */
AnnaBridge 171:3a7713b1edbc 164 MXC_E_CLKMAN_CLK_SCALE_DIV_8,
AnnaBridge 171:3a7713b1edbc 165 /** Clock scale for dividing by 16 */
AnnaBridge 171:3a7713b1edbc 166 MXC_E_CLKMAN_CLK_SCALE_DIV_16,
AnnaBridge 171:3a7713b1edbc 167 /** Clock scale for dividing by 32 */
AnnaBridge 171:3a7713b1edbc 168 MXC_E_CLKMAN_CLK_SCALE_DIV_32,
AnnaBridge 171:3a7713b1edbc 169 /** Clock scale for dividing by 64 */
AnnaBridge 171:3a7713b1edbc 170 MXC_E_CLKMAN_CLK_SCALE_DIV_64,
AnnaBridge 171:3a7713b1edbc 171 /** Clock scale for dividing by 128 */
AnnaBridge 171:3a7713b1edbc 172 MXC_E_CLKMAN_CLK_SCALE_DIV_128,
AnnaBridge 171:3a7713b1edbc 173 /** Clock scale for dividing by 256 */
AnnaBridge 171:3a7713b1edbc 174 MXC_E_CLKMAN_CLK_SCALE_DIV_256
AnnaBridge 171:3a7713b1edbc 175 } mxc_clkman_clk_scale_t;
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 /**
AnnaBridge 171:3a7713b1edbc 178 * @brief Defines Setting of the Clock Gates .
AnnaBridge 171:3a7713b1edbc 179 */
AnnaBridge 171:3a7713b1edbc 180 typedef enum {
AnnaBridge 171:3a7713b1edbc 181 /** Clock Gater is Off */
AnnaBridge 171:3a7713b1edbc 182 MXC_E_CLKMAN_CLK_GATE_OFF = 0,
AnnaBridge 171:3a7713b1edbc 183 /** Clock Gater is Dynamic */
AnnaBridge 171:3a7713b1edbc 184 MXC_E_CLKMAN_CLK_GATE_DYNAMIC,
AnnaBridge 171:3a7713b1edbc 185 /** Clock Gater is On */
AnnaBridge 171:3a7713b1edbc 186 MXC_E_CLKMAN_CLK_GATE_ON
AnnaBridge 171:3a7713b1edbc 187 } mxc_clkman_clk_gate_t;
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 190 ====== ===================================================================== */
AnnaBridge 171:3a7713b1edbc 191 typedef struct {
AnnaBridge 171:3a7713b1edbc 192 __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */
AnnaBridge 171:3a7713b1edbc 193 __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */
AnnaBridge 171:3a7713b1edbc 194 __IO uint32_t intfl; /* 0x0008 Interrupt Flags */
AnnaBridge 171:3a7713b1edbc 195 __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */
AnnaBridge 171:3a7713b1edbc 196 __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */
AnnaBridge 171:3a7713b1edbc 197 __I uint32_t rsv0014[4]; /* 0x0014 */
AnnaBridge 171:3a7713b1edbc 198 __IO uint32_t i2c_timer_ctrl; /* 0x0024 I2C Timer Control */
AnnaBridge 171:3a7713b1edbc 199 __I uint32_t rsv0028[6]; /* 0x0028 */
AnnaBridge 171:3a7713b1edbc 200 __IO uint32_t clk_ctrl_0_system; /* 0x0040 Control Settings for CLK0 - System Clock */
AnnaBridge 171:3a7713b1edbc 201 __IO uint32_t clk_ctrl_1_gpio; /* 0x0044 Control Settings for CLK1 - GPIO Module Clock */
AnnaBridge 171:3a7713b1edbc 202 __IO uint32_t clk_ctrl_2_pt; /* 0x0048 Control Settings for CLK2 - Pulse Train Module Clock */
AnnaBridge 171:3a7713b1edbc 203 __IO uint32_t clk_ctrl_3_spi0; /* 0x004C Control Settings for CLK3 - SPI0 Master Clock */
AnnaBridge 171:3a7713b1edbc 204 __IO uint32_t clk_ctrl_4_spi1; /* 0x0050 Control Settings for CLK4 - SPI1 Master Clock */
AnnaBridge 171:3a7713b1edbc 205 __IO uint32_t clk_ctrl_5_spi2; /* 0x0054 Control Settings for CLK5 - SPI2 Master Clock */
AnnaBridge 171:3a7713b1edbc 206 __IO uint32_t clk_ctrl_6_i2cm; /* 0x0058 Control Settings for CLK6 - Clock for all I2C Masters */
AnnaBridge 171:3a7713b1edbc 207 __IO uint32_t clk_ctrl_7_i2cs; /* 0x005C Control Settings for CLK7 - I2C Slave Clock */
AnnaBridge 171:3a7713b1edbc 208 __IO uint32_t clk_ctrl_8_lcd_chpump; /* 0x0060 Control Settings for CLK8 - LCD Charge Pump Clock */
AnnaBridge 171:3a7713b1edbc 209 __IO uint32_t clk_ctrl_9_puf; /* 0x0064 Control Settings for CLK9 - PUF Clock */
AnnaBridge 171:3a7713b1edbc 210 __IO uint32_t clk_ctrl_10_prng; /* 0x0068 Control Settings for CLK10 - PRNG Clock */
AnnaBridge 171:3a7713b1edbc 211 __IO uint32_t clk_ctrl_11_wdt0; /* 0x006C Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk */
AnnaBridge 171:3a7713b1edbc 212 __IO uint32_t clk_ctrl_12_wdt1; /* 0x0070 Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk */
AnnaBridge 171:3a7713b1edbc 213 __IO uint32_t clk_ctrl_13_rtc_int_sync; /* 0x0074 Control Settings for CLK13 - RTC Interrupt Sync Clock */
AnnaBridge 171:3a7713b1edbc 214 __IO uint32_t clk_ctrl_14_dac0; /* 0x0078 Control Settings for CLK14 - 12-bit DAC 0 Clock */
AnnaBridge 171:3a7713b1edbc 215 __IO uint32_t clk_ctrl_15_dac1; /* 0x007C Control Settings for CLK15 - 12-bit DAC 1 Clock */
AnnaBridge 171:3a7713b1edbc 216 __IO uint32_t clk_ctrl_16_dac2; /* 0x0080 Control Settings for CLK16 - 8-bit DAC 0 Clock */
AnnaBridge 171:3a7713b1edbc 217 __IO uint32_t clk_ctrl_17_dac3; /* 0x0084 Control Settings for CLK17 - 8-bit DAC 1 Clock */
AnnaBridge 171:3a7713b1edbc 218 __I uint32_t rsv0088[30]; /* 0x0088 */
AnnaBridge 171:3a7713b1edbc 219 __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */
AnnaBridge 171:3a7713b1edbc 220 __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */
AnnaBridge 171:3a7713b1edbc 221 __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */
AnnaBridge 171:3a7713b1edbc 222 __I uint32_t rsv010C[13]; /* 0x010C */
AnnaBridge 171:3a7713b1edbc 223 __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */
AnnaBridge 171:3a7713b1edbc 224 __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */
AnnaBridge 171:3a7713b1edbc 225 __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */
AnnaBridge 171:3a7713b1edbc 226 } mxc_clkman_regs_t;
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 /*
AnnaBridge 171:3a7713b1edbc 229 Register offsets for module CLKMAN.
AnnaBridge 171:3a7713b1edbc 230 */
AnnaBridge 171:3a7713b1edbc 231 #define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 232 #define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 233 #define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 234 #define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 235 #define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL)
AnnaBridge 171:3a7713b1edbc 236 #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000024UL)
AnnaBridge 171:3a7713b1edbc 237 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM ((uint32_t)0x00000040UL)
AnnaBridge 171:3a7713b1edbc 238 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO ((uint32_t)0x00000044UL)
AnnaBridge 171:3a7713b1edbc 239 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT ((uint32_t)0x00000048UL)
AnnaBridge 171:3a7713b1edbc 240 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0 ((uint32_t)0x0000004CUL)
AnnaBridge 171:3a7713b1edbc 241 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1 ((uint32_t)0x00000050UL)
AnnaBridge 171:3a7713b1edbc 242 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2 ((uint32_t)0x00000054UL)
AnnaBridge 171:3a7713b1edbc 243 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM ((uint32_t)0x00000058UL)
AnnaBridge 171:3a7713b1edbc 244 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS ((uint32_t)0x0000005CUL)
AnnaBridge 171:3a7713b1edbc 245 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP ((uint32_t)0x00000060UL)
AnnaBridge 171:3a7713b1edbc 246 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF ((uint32_t)0x00000064UL)
AnnaBridge 171:3a7713b1edbc 247 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG ((uint32_t)0x00000068UL)
AnnaBridge 171:3a7713b1edbc 248 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0 ((uint32_t)0x0000006CUL)
AnnaBridge 171:3a7713b1edbc 249 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1 ((uint32_t)0x00000070UL)
AnnaBridge 171:3a7713b1edbc 250 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC ((uint32_t)0x00000074UL)
AnnaBridge 171:3a7713b1edbc 251 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0 ((uint32_t)0x00000078UL)
AnnaBridge 171:3a7713b1edbc 252 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1 ((uint32_t)0x0000007CUL)
AnnaBridge 171:3a7713b1edbc 253 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2 ((uint32_t)0x00000080UL)
AnnaBridge 171:3a7713b1edbc 254 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3 ((uint32_t)0x00000084UL)
AnnaBridge 171:3a7713b1edbc 255 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL)
AnnaBridge 171:3a7713b1edbc 256 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL)
AnnaBridge 171:3a7713b1edbc 257 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL)
AnnaBridge 171:3a7713b1edbc 258 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL)
AnnaBridge 171:3a7713b1edbc 259 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL)
AnnaBridge 171:3a7713b1edbc 260 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL)
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 /*
AnnaBridge 171:3a7713b1edbc 263 Field positions and masks for module CLKMAN.
AnnaBridge 171:3a7713b1edbc 264 */
AnnaBridge 171:3a7713b1edbc 265 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS 0
AnnaBridge 171:3a7713b1edbc 266 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS))
AnnaBridge 171:3a7713b1edbc 267 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS 1
AnnaBridge 171:3a7713b1edbc 268 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS))
AnnaBridge 171:3a7713b1edbc 269 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS 2
AnnaBridge 171:3a7713b1edbc 270 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS))
AnnaBridge 171:3a7713b1edbc 271 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS 4
AnnaBridge 171:3a7713b1edbc 272 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS))
AnnaBridge 171:3a7713b1edbc 273 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS 9
AnnaBridge 171:3a7713b1edbc 274 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS))
AnnaBridge 171:3a7713b1edbc 275 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS 12
AnnaBridge 171:3a7713b1edbc 276 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS))
AnnaBridge 171:3a7713b1edbc 277 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS 13
AnnaBridge 171:3a7713b1edbc 278 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS))
AnnaBridge 171:3a7713b1edbc 279 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS 14
AnnaBridge 171:3a7713b1edbc 280 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS))
AnnaBridge 171:3a7713b1edbc 281 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS 16
AnnaBridge 171:3a7713b1edbc 282 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS))
AnnaBridge 171:3a7713b1edbc 283 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS 18
AnnaBridge 171:3a7713b1edbc 284 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS))
AnnaBridge 171:3a7713b1edbc 285 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS 19
AnnaBridge 171:3a7713b1edbc 286 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS))
AnnaBridge 171:3a7713b1edbc 287 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS 20
AnnaBridge 171:3a7713b1edbc 288 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS))
AnnaBridge 171:3a7713b1edbc 289 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 24
AnnaBridge 171:3a7713b1edbc 290 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
AnnaBridge 171:3a7713b1edbc 291 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS 25
AnnaBridge 171:3a7713b1edbc 292 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS))
AnnaBridge 171:3a7713b1edbc 293 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 28
AnnaBridge 171:3a7713b1edbc 294 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 1
AnnaBridge 171:3a7713b1edbc 297 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
AnnaBridge 171:3a7713b1edbc 298 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS 3
AnnaBridge 171:3a7713b1edbc 299 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS))
AnnaBridge 171:3a7713b1edbc 300 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS 4
AnnaBridge 171:3a7713b1edbc 301 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS))
AnnaBridge 171:3a7713b1edbc 302 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS 8
AnnaBridge 171:3a7713b1edbc 303 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS))
AnnaBridge 171:3a7713b1edbc 304 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS 9
AnnaBridge 171:3a7713b1edbc 305 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))
AnnaBridge 171:3a7713b1edbc 306 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS 12
AnnaBridge 171:3a7713b1edbc 307 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS))
AnnaBridge 171:3a7713b1edbc 308 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS 16
AnnaBridge 171:3a7713b1edbc 309 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS))
AnnaBridge 171:3a7713b1edbc 310 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS 17
AnnaBridge 171:3a7713b1edbc 311 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS))
AnnaBridge 171:3a7713b1edbc 312 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS 20
AnnaBridge 171:3a7713b1edbc 313 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS))
AnnaBridge 171:3a7713b1edbc 314 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS 21
AnnaBridge 171:3a7713b1edbc 315 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS))
AnnaBridge 171:3a7713b1edbc 316 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 24
AnnaBridge 171:3a7713b1edbc 317 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 #define MXC_F_CLKMAN_INTFL_RING_STABLE_POS 0
AnnaBridge 171:3a7713b1edbc 320 #define MXC_F_CLKMAN_INTFL_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS))
AnnaBridge 171:3a7713b1edbc 321 #define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS 1
AnnaBridge 171:3a7713b1edbc 322 #define MXC_F_CLKMAN_INTFL_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS))
AnnaBridge 171:3a7713b1edbc 323 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 2
AnnaBridge 171:3a7713b1edbc 324 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
AnnaBridge 171:3a7713b1edbc 325
AnnaBridge 171:3a7713b1edbc 326 #define MXC_F_CLKMAN_INTEN_RING_STABLE_POS 0
AnnaBridge 171:3a7713b1edbc 327 #define MXC_F_CLKMAN_INTEN_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS))
AnnaBridge 171:3a7713b1edbc 328 #define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS 1
AnnaBridge 171:3a7713b1edbc 329 #define MXC_F_CLKMAN_INTEN_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS))
AnnaBridge 171:3a7713b1edbc 330 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 2
AnnaBridge 171:3a7713b1edbc 331 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
AnnaBridge 171:3a7713b1edbc 332
AnnaBridge 171:3a7713b1edbc 333 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0
AnnaBridge 171:3a7713b1edbc 334 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
AnnaBridge 171:3a7713b1edbc 335 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1
AnnaBridge 171:3a7713b1edbc 336 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
AnnaBridge 171:3a7713b1edbc 337 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2
AnnaBridge 171:3a7713b1edbc 338 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
AnnaBridge 171:3a7713b1edbc 339 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3
AnnaBridge 171:3a7713b1edbc 340 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
AnnaBridge 171:3a7713b1edbc 341 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16
AnnaBridge 171:3a7713b1edbc 342 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
AnnaBridge 171:3a7713b1edbc 343
AnnaBridge 171:3a7713b1edbc 344 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0
AnnaBridge 171:3a7713b1edbc 345 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
AnnaBridge 171:3a7713b1edbc 346
AnnaBridge 171:3a7713b1edbc 347 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 348 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 349
AnnaBridge 171:3a7713b1edbc 350 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 351 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 352
AnnaBridge 171:3a7713b1edbc 353 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 354 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 355
AnnaBridge 171:3a7713b1edbc 356 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 357 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 360 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 363 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 366 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 369 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 372 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 373
AnnaBridge 171:3a7713b1edbc 374 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 375 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 378 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 379
AnnaBridge 171:3a7713b1edbc 380 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 381 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 382
AnnaBridge 171:3a7713b1edbc 383 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 384 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 385
AnnaBridge 171:3a7713b1edbc 386 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 387 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 390 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 391
AnnaBridge 171:3a7713b1edbc 392 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 393 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 394
AnnaBridge 171:3a7713b1edbc 395 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 396 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 399 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 400
AnnaBridge 171:3a7713b1edbc 401 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 402 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 403
AnnaBridge 171:3a7713b1edbc 404 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 405 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0
AnnaBridge 171:3a7713b1edbc 408 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
AnnaBridge 171:3a7713b1edbc 409
AnnaBridge 171:3a7713b1edbc 410 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS 0
AnnaBridge 171:3a7713b1edbc 411 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 412 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS 2
AnnaBridge 171:3a7713b1edbc 413 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 414 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4
AnnaBridge 171:3a7713b1edbc 415 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 416 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6
AnnaBridge 171:3a7713b1edbc 417 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 418 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8
AnnaBridge 171:3a7713b1edbc 419 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 420 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10
AnnaBridge 171:3a7713b1edbc 421 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 422 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12
AnnaBridge 171:3a7713b1edbc 423 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 424 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS 14
AnnaBridge 171:3a7713b1edbc 425 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 426 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS 16
AnnaBridge 171:3a7713b1edbc 427 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 428 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS 18
AnnaBridge 171:3a7713b1edbc 429 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 430 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS 20
AnnaBridge 171:3a7713b1edbc 431 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 432 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS 22
AnnaBridge 171:3a7713b1edbc 433 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 434 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS 24
AnnaBridge 171:3a7713b1edbc 435 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 436 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 26
AnnaBridge 171:3a7713b1edbc 437 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 438 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS 28
AnnaBridge 171:3a7713b1edbc 439 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 440 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 30
AnnaBridge 171:3a7713b1edbc 441 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 442
AnnaBridge 171:3a7713b1edbc 443 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS 0
AnnaBridge 171:3a7713b1edbc 444 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 445 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS 2
AnnaBridge 171:3a7713b1edbc 446 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 447 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS 4
AnnaBridge 171:3a7713b1edbc 448 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 449 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS 6
AnnaBridge 171:3a7713b1edbc 450 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 451 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS 8
AnnaBridge 171:3a7713b1edbc 452 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 453 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS 10
AnnaBridge 171:3a7713b1edbc 454 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 455 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS 12
AnnaBridge 171:3a7713b1edbc 456 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 457 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS 14
AnnaBridge 171:3a7713b1edbc 458 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 459 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 16
AnnaBridge 171:3a7713b1edbc 460 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 461 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 18
AnnaBridge 171:3a7713b1edbc 462 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 463 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS 20
AnnaBridge 171:3a7713b1edbc 464 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 465 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS 22
AnnaBridge 171:3a7713b1edbc 466 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 467 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS 24
AnnaBridge 171:3a7713b1edbc 468 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 469 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26
AnnaBridge 171:3a7713b1edbc 470 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 471 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28
AnnaBridge 171:3a7713b1edbc 472 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 473 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS 30
AnnaBridge 171:3a7713b1edbc 474 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 475
AnnaBridge 171:3a7713b1edbc 476 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS 0
AnnaBridge 171:3a7713b1edbc 477 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 478 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS 2
AnnaBridge 171:3a7713b1edbc 479 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 480 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS 4
AnnaBridge 171:3a7713b1edbc 481 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 482 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS 6
AnnaBridge 171:3a7713b1edbc 483 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS))
AnnaBridge 171:3a7713b1edbc 484
AnnaBridge 171:3a7713b1edbc 485 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 486 }
AnnaBridge 171:3a7713b1edbc 487 #endif
AnnaBridge 171:3a7713b1edbc 488
AnnaBridge 171:3a7713b1edbc 489 /**
AnnaBridge 171:3a7713b1edbc 490 * @}
AnnaBridge 171:3a7713b1edbc 491 */
AnnaBridge 171:3a7713b1edbc 492
AnnaBridge 171:3a7713b1edbc 493 #endif /* _MXC_CLKMAN_REGS_H_ */