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TARGET_MAX32600MBED/TOOLCHAIN_ARM_STD/rtc_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_RTC_REGS_H
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_RTC_REGS_H
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file rtc_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup rtc RTCTMR
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /**
AnnaBridge 171:3a7713b1edbc 50 * @brief Defines clock divider for 4096Hz input clock.
AnnaBridge 171:3a7713b1edbc 51 */
AnnaBridge 171:3a7713b1edbc 52 typedef enum {
AnnaBridge 171:3a7713b1edbc 53 /** (4kHz) divide input clock by 2^0 = 1 */
AnnaBridge 171:3a7713b1edbc 54 MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
AnnaBridge 171:3a7713b1edbc 55 /** (2kHz) divide input clock by 2^1 = 2 */
AnnaBridge 171:3a7713b1edbc 56 MXC_E_RTC_PRESCALE_DIV_2_1,
AnnaBridge 171:3a7713b1edbc 57 /** (1kHz) divide input clock by 2^2 = 4 */
AnnaBridge 171:3a7713b1edbc 58 MXC_E_RTC_PRESCALE_DIV_2_2,
AnnaBridge 171:3a7713b1edbc 59 /** (512Hz) divide input clock by 2^3 = 8 */
AnnaBridge 171:3a7713b1edbc 60 MXC_E_RTC_PRESCALE_DIV_2_3,
AnnaBridge 171:3a7713b1edbc 61 /** (256Hz) divide input clock by 2^4 = 16 */
AnnaBridge 171:3a7713b1edbc 62 MXC_E_RTC_PRESCALE_DIV_2_4,
AnnaBridge 171:3a7713b1edbc 63 /** (128Hz) divide input clock by 2^5 = 32 */
AnnaBridge 171:3a7713b1edbc 64 MXC_E_RTC_PRESCALE_DIV_2_5,
AnnaBridge 171:3a7713b1edbc 65 /** (64Hz) divide input clock by 2^6 = 64 */
AnnaBridge 171:3a7713b1edbc 66 MXC_E_RTC_PRESCALE_DIV_2_6,
AnnaBridge 171:3a7713b1edbc 67 /** (32Hz) divide input clock by 2^7 = 128 */
AnnaBridge 171:3a7713b1edbc 68 MXC_E_RTC_PRESCALE_DIV_2_7,
AnnaBridge 171:3a7713b1edbc 69 /** (16Hz) divide input clock by 2^8 = 256 */
AnnaBridge 171:3a7713b1edbc 70 MXC_E_RTC_PRESCALE_DIV_2_8,
AnnaBridge 171:3a7713b1edbc 71 /** (8Hz) divide input clock by 2^9 = 512 */
AnnaBridge 171:3a7713b1edbc 72 MXC_E_RTC_PRESCALE_DIV_2_9,
AnnaBridge 171:3a7713b1edbc 73 /** (4Hz) divide input clock by 2^10 = 1024 */
AnnaBridge 171:3a7713b1edbc 74 MXC_E_RTC_PRESCALE_DIV_2_10,
AnnaBridge 171:3a7713b1edbc 75 /** (2Hz) divide input clock by 2^11 = 2048 */
AnnaBridge 171:3a7713b1edbc 76 MXC_E_RTC_PRESCALE_DIV_2_11,
AnnaBridge 171:3a7713b1edbc 77 /** (1Hz) divide input clock by 2^12 = 4096 */
AnnaBridge 171:3a7713b1edbc 78 MXC_E_RTC_PRESCALE_DIV_2_12,
AnnaBridge 171:3a7713b1edbc 79 } mxc_rtc_prescale_t;
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 82 ====== ========================================= */
AnnaBridge 171:3a7713b1edbc 83 typedef struct {
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t comp[2]; /* 0x0008 RTC Alarm (0..1) Compare Registers */
AnnaBridge 171:3a7713b1edbc 87 __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */
AnnaBridge 171:3a7713b1edbc 88 __I uint32_t rsv0014; /* 0x0014 */
AnnaBridge 171:3a7713b1edbc 89 __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */
AnnaBridge 171:3a7713b1edbc 90 __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */
AnnaBridge 171:3a7713b1edbc 91 __I uint32_t rsv0020; /* 0x0020 */
AnnaBridge 171:3a7713b1edbc 92 __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */
AnnaBridge 171:3a7713b1edbc 93 __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */
AnnaBridge 171:3a7713b1edbc 94 __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */
AnnaBridge 171:3a7713b1edbc 95 } mxc_rtctmr_regs_t;
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 /*
AnnaBridge 171:3a7713b1edbc 98 Register offsets for module RTCTMR.
AnnaBridge 171:3a7713b1edbc 99 */
AnnaBridge 171:3a7713b1edbc 100 #define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 101 #define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 102 #define MXC_R_RTCTMR_OFFS_COMP_0 ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 103 #define MXC_R_RTCTMR_OFFS_COMP_1 ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 104 #define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL)
AnnaBridge 171:3a7713b1edbc 105 #define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL)
AnnaBridge 171:3a7713b1edbc 106 #define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL)
AnnaBridge 171:3a7713b1edbc 107 #define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL)
AnnaBridge 171:3a7713b1edbc 108 #define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL)
AnnaBridge 171:3a7713b1edbc 109 #define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL)
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /*
AnnaBridge 171:3a7713b1edbc 112 Field positions and masks for module RTCTMR.
AnnaBridge 171:3a7713b1edbc 113 */
AnnaBridge 171:3a7713b1edbc 114 #define MXC_F_RTC_CTRL_ENABLE_POS 0
AnnaBridge 171:3a7713b1edbc 115 #define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS))
AnnaBridge 171:3a7713b1edbc 116 #define MXC_F_RTC_CTRL_CLEAR_POS 1
AnnaBridge 171:3a7713b1edbc 117 #define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS))
AnnaBridge 171:3a7713b1edbc 118 #define MXC_F_RTC_CTRL_PENDING_POS 2
AnnaBridge 171:3a7713b1edbc 119 #define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS))
AnnaBridge 171:3a7713b1edbc 120 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3
AnnaBridge 171:3a7713b1edbc 121 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS))
AnnaBridge 171:3a7713b1edbc 122 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4
AnnaBridge 171:3a7713b1edbc 123 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS))
AnnaBridge 171:3a7713b1edbc 124 #define MXC_F_RTC_CTRL_EN_ACTIVE_POS 16
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_RTC_CTRL_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS))
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17
AnnaBridge 171:3a7713b1edbc 127 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS))
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18
AnnaBridge 171:3a7713b1edbc 129 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS))
AnnaBridge 171:3a7713b1edbc 130 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19
AnnaBridge 171:3a7713b1edbc 131 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS))
AnnaBridge 171:3a7713b1edbc 132 #define MXC_F_RTC_CTRL_SET_ACTIVE_POS 20
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_RTC_CTRL_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS))
AnnaBridge 171:3a7713b1edbc 134 #define MXC_F_RTC_CTRL_CLR_ACTIVE_POS 21
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_RTC_CTRL_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS))
AnnaBridge 171:3a7713b1edbc 136 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS))
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS))
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS))
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS))
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS))
AnnaBridge 171:3a7713b1edbc 146
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_RTC_FLAGS_COMP0_POS 0
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS))
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_RTC_FLAGS_COMP1_POS 1
AnnaBridge 171:3a7713b1edbc 150 #define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS))
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS))
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_RTC_FLAGS_OVERFLOW_POS 3
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS))
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_RTC_FLAGS_TRIM_POS 4
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS))
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS))
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS))
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS))
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS))
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12
AnnaBridge 171:3a7713b1edbc 166 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS))
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS))
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_RTC_INTEN_COMP0_POS 0
AnnaBridge 171:3a7713b1edbc 171 #define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS))
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_RTC_INTEN_COMP1_POS 1
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS))
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2
AnnaBridge 171:3a7713b1edbc 175 #define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS))
AnnaBridge 171:3a7713b1edbc 176 #define MXC_F_RTC_INTEN_OVERFLOW_POS 3
AnnaBridge 171:3a7713b1edbc 177 #define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS))
AnnaBridge 171:3a7713b1edbc 178 #define MXC_F_RTC_INTEN_TRIM_POS 4
AnnaBridge 171:3a7713b1edbc 179 #define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS))
AnnaBridge 171:3a7713b1edbc 180
AnnaBridge 171:3a7713b1edbc 181 #define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS 0
AnnaBridge 171:3a7713b1edbc 182 #define MXC_F_RTC_PRESCALE_WIDTH_SELECTION ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS))
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS 0
AnnaBridge 171:3a7713b1edbc 185 #define MXC_F_RTC_PRESCALE_MASK_COMP_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS))
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0
AnnaBridge 171:3a7713b1edbc 188 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS))
AnnaBridge 171:3a7713b1edbc 189 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1
AnnaBridge 171:3a7713b1edbc 190 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS))
AnnaBridge 171:3a7713b1edbc 191 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2
AnnaBridge 171:3a7713b1edbc 192 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS))
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0
AnnaBridge 171:3a7713b1edbc 195 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS))
AnnaBridge 171:3a7713b1edbc 196 #define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS 18
AnnaBridge 171:3a7713b1edbc 197 #define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS))
AnnaBridge 171:3a7713b1edbc 198
AnnaBridge 171:3a7713b1edbc 199 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0
AnnaBridge 171:3a7713b1edbc 200 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS))
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 #define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0
AnnaBridge 171:3a7713b1edbc 203 #define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS))
AnnaBridge 171:3a7713b1edbc 204 #define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1
AnnaBridge 171:3a7713b1edbc 205 #define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS))
AnnaBridge 171:3a7713b1edbc 206 #define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2
AnnaBridge 171:3a7713b1edbc 207 #define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS))
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 #define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS 0
AnnaBridge 171:3a7713b1edbc 210 #define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS))
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0
AnnaBridge 171:3a7713b1edbc 213 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS))
AnnaBridge 171:3a7713b1edbc 214 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1
AnnaBridge 171:3a7713b1edbc 215 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS))
AnnaBridge 171:3a7713b1edbc 216 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2
AnnaBridge 171:3a7713b1edbc 217 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS))
AnnaBridge 171:3a7713b1edbc 218 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3
AnnaBridge 171:3a7713b1edbc 219 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS))
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 222 ====== ===================================================================== */
AnnaBridge 171:3a7713b1edbc 223 typedef struct {
AnnaBridge 171:3a7713b1edbc 224 __IO uint32_t nano_counter; /* 0x0000 Nanoring Counter Read Register */
AnnaBridge 171:3a7713b1edbc 225 __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */
AnnaBridge 171:3a7713b1edbc 226 __IO uint32_t dsen_ctrl; /* 0x0008 Dynamic Tamper Sensor Control */
AnnaBridge 171:3a7713b1edbc 227 __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */
AnnaBridge 171:3a7713b1edbc 228 } mxc_rtccfg_regs_t;
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 /*
AnnaBridge 171:3a7713b1edbc 231 Register offsets for module RTCCFG.
AnnaBridge 171:3a7713b1edbc 232 */
AnnaBridge 171:3a7713b1edbc 233 #define MXC_R_RTCCFG_OFFS_NANO_COUNTER ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 234 #define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 235 #define MXC_R_RTCCFG_OFFS_DSEN_CTRL ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 236 #define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 237
AnnaBridge 171:3a7713b1edbc 238 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 239 }
AnnaBridge 171:3a7713b1edbc 240 #endif
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 /**
AnnaBridge 171:3a7713b1edbc 243 * @}
AnnaBridge 171:3a7713b1edbc 244 */
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 #endif /* _MXC_RTC_REGS_H */