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TARGET_LPC546XX/TOOLCHAIN_ARM_STD/fsl_spifi.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Child:
172:65be27845400
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * The Clear BSD License
AnnaBridge 171:3a7713b1edbc 3 * Copyright (c) 2016, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 4 * Copyright 2016-2017 NXP
AnnaBridge 171:3a7713b1edbc 5 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 6 *
AnnaBridge 171:3a7713b1edbc 7 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 8 * are permitted (subject to the limitations in the disclaimer below) provided
AnnaBridge 171:3a7713b1edbc 9 * that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 12 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 15 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 16 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 171:3a7713b1edbc 19 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 20 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
AnnaBridge 171:3a7713b1edbc 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 33 */
AnnaBridge 171:3a7713b1edbc 34 #ifndef _FSL_SPIFI_H_
AnnaBridge 171:3a7713b1edbc 35 #define _FSL_SPIFI_H_
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 38
AnnaBridge 171:3a7713b1edbc 39 /*!
AnnaBridge 171:3a7713b1edbc 40 * @addtogroup spifi
AnnaBridge 171:3a7713b1edbc 41 * @{
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 45 * Definitions
AnnaBridge 171:3a7713b1edbc 46 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 49 /*@{*/
AnnaBridge 171:3a7713b1edbc 50 /*! @brief SPIFI driver version 2.0.0. */
AnnaBridge 171:3a7713b1edbc 51 #define FSL_SPIFI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
AnnaBridge 171:3a7713b1edbc 52 /*@}*/
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54 /*! @brief Status structure of SPIFI.*/
AnnaBridge 171:3a7713b1edbc 55 enum _status_t
AnnaBridge 171:3a7713b1edbc 56 {
AnnaBridge 171:3a7713b1edbc 57 kStatus_SPIFI_Idle = MAKE_STATUS(kStatusGroup_SPIFI, 0), /*!< SPIFI is in idle state */
AnnaBridge 171:3a7713b1edbc 58 kStatus_SPIFI_Busy = MAKE_STATUS(kStatusGroup_SPIFI, 1), /*!< SPIFI is busy */
AnnaBridge 171:3a7713b1edbc 59 kStatus_SPIFI_Error = MAKE_STATUS(kStatusGroup_SPIFI, 2), /*!< Error occurred during SPIFI transfer */
AnnaBridge 171:3a7713b1edbc 60 };
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 /*! @brief SPIFI interrupt source */
AnnaBridge 171:3a7713b1edbc 63 typedef enum _spifi_interrupt_enable
AnnaBridge 171:3a7713b1edbc 64 {
AnnaBridge 171:3a7713b1edbc 65 kSPIFI_CommandFinishInterruptEnable = SPIFI_CTRL_INTEN_MASK, /*!< Interrupt while command finished */
AnnaBridge 171:3a7713b1edbc 66 } spifi_interrupt_enable_t;
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 /*! @brief SPIFI SPI mode select */
AnnaBridge 171:3a7713b1edbc 69 typedef enum _spifi_spi_mode
AnnaBridge 171:3a7713b1edbc 70 {
AnnaBridge 171:3a7713b1edbc 71 kSPIFI_SPISckLow = 0x0U, /*!< SCK low after last bit of command, keeps low while CS high */
AnnaBridge 171:3a7713b1edbc 72 kSPIFI_SPISckHigh = 0x1U /*!< SCK high after last bit of command and while CS high */
AnnaBridge 171:3a7713b1edbc 73 } spifi_spi_mode_t;
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 /*! @brief SPIFI dual mode select */
AnnaBridge 171:3a7713b1edbc 76 typedef enum _spifi_dual_mode
AnnaBridge 171:3a7713b1edbc 77 {
AnnaBridge 171:3a7713b1edbc 78 kSPIFI_QuadMode = 0x0U, /*!< SPIFI uses IO3:0 */
AnnaBridge 171:3a7713b1edbc 79 kSPIFI_DualMode = 0x1U /*!< SPIFI uses IO1:0 */
AnnaBridge 171:3a7713b1edbc 80 } spifi_dual_mode_t;
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 /*! @brief SPIFI data direction */
AnnaBridge 171:3a7713b1edbc 83 typedef enum _spifi_data_direction
AnnaBridge 171:3a7713b1edbc 84 {
AnnaBridge 171:3a7713b1edbc 85 kSPIFI_DataInput = 0x0U, /*!< Data input from serial flash. */
AnnaBridge 171:3a7713b1edbc 86 kSPIFI_DataOutput = 0x1U /*!< Data output to serial flash. */
AnnaBridge 171:3a7713b1edbc 87 } spifi_data_direction_t;
AnnaBridge 171:3a7713b1edbc 88
AnnaBridge 171:3a7713b1edbc 89 /*! @brief SPIFI command opcode format */
AnnaBridge 171:3a7713b1edbc 90 typedef enum _spifi_command_format
AnnaBridge 171:3a7713b1edbc 91 {
AnnaBridge 171:3a7713b1edbc 92 kSPIFI_CommandAllSerial = 0x0, /*!< All fields of command are serial. */
AnnaBridge 171:3a7713b1edbc 93 kSPIFI_CommandDataQuad = 0x1U, /*!< Only data field is dual/quad, others are serial. */
AnnaBridge 171:3a7713b1edbc 94 kSPIFI_CommandOpcodeSerial = 0x2U, /*!< Only opcode field is serial, others are quad/dual. */
AnnaBridge 171:3a7713b1edbc 95 kSPIFI_CommandAllQuad = 0x3U /*!< All fields of command are dual/quad mode. */
AnnaBridge 171:3a7713b1edbc 96 } spifi_command_format_t;
AnnaBridge 171:3a7713b1edbc 97
AnnaBridge 171:3a7713b1edbc 98 /*! @brief SPIFI command type */
AnnaBridge 171:3a7713b1edbc 99 typedef enum _spifi_command_type
AnnaBridge 171:3a7713b1edbc 100 {
AnnaBridge 171:3a7713b1edbc 101 kSPIFI_CommandOpcodeOnly = 0x1U, /*!< Command only have opcode, no address field */
AnnaBridge 171:3a7713b1edbc 102 kSPIFI_CommandOpcodeAddrOneByte = 0x2U, /*!< Command have opcode and also one byte address field */
AnnaBridge 171:3a7713b1edbc 103 kSPIFI_CommandOpcodeAddrTwoBytes = 0x3U, /*!< Command have opcode and also two bytes address field */
AnnaBridge 171:3a7713b1edbc 104 kSPIFI_CommandOpcodeAddrThreeBytes = 0x4U, /*!< Command have opcode and also three bytes address field. */
AnnaBridge 171:3a7713b1edbc 105 kSPIFI_CommandOpcodeAddrFourBytes = 0x5U, /*!< Command have opcode and also four bytes address field */
AnnaBridge 171:3a7713b1edbc 106 kSPIFI_CommandNoOpcodeAddrThreeBytes = 0x6U, /*!< Command have no opcode and three bytes address field */
AnnaBridge 171:3a7713b1edbc 107 kSPIFI_CommandNoOpcodeAddrFourBytes = 0x7U /*!< Command have no opcode and four bytes address field */
AnnaBridge 171:3a7713b1edbc 108 } spifi_command_type_t;
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 /*! @brief SPIFI status flags */
AnnaBridge 171:3a7713b1edbc 111 enum _spifi_status_flags
AnnaBridge 171:3a7713b1edbc 112 {
AnnaBridge 171:3a7713b1edbc 113 kSPIFI_MemoryCommandWriteFinished = SPIFI_STAT_MCINIT_MASK, /*!< Memory command write finished */
AnnaBridge 171:3a7713b1edbc 114 kSPIFI_CommandWriteFinished = SPIFI_STAT_CMD_MASK, /*!< Command write finished */
AnnaBridge 171:3a7713b1edbc 115 kSPIFI_InterruptRequest = SPIFI_STAT_INTRQ_MASK /*!< CMD flag from 1 to 0, means command execute finished */
AnnaBridge 171:3a7713b1edbc 116 };
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 /*! @brief SPIFI command structure */
AnnaBridge 171:3a7713b1edbc 119 typedef struct _spifi_command
AnnaBridge 171:3a7713b1edbc 120 {
AnnaBridge 171:3a7713b1edbc 121 uint16_t dataLen; /*!< How many data bytes are needed in this command. */
AnnaBridge 171:3a7713b1edbc 122 bool isPollMode; /*!< For command need to read data from serial flash */
AnnaBridge 171:3a7713b1edbc 123 spifi_data_direction_t direction; /*!< Data direction of this command. */
AnnaBridge 171:3a7713b1edbc 124 uint8_t intermediateBytes; /*!< How many intermediate bytes needed */
AnnaBridge 171:3a7713b1edbc 125 spifi_command_format_t format; /*!< Command format */
AnnaBridge 171:3a7713b1edbc 126 spifi_command_type_t type; /*!< Command type */
AnnaBridge 171:3a7713b1edbc 127 uint8_t opcode; /*!< Command opcode value */
AnnaBridge 171:3a7713b1edbc 128 } spifi_command_t;
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /*!
AnnaBridge 171:3a7713b1edbc 131 * @brief SPIFI region configuration structure.
AnnaBridge 171:3a7713b1edbc 132 */
AnnaBridge 171:3a7713b1edbc 133 typedef struct _spifi_config
AnnaBridge 171:3a7713b1edbc 134 {
AnnaBridge 171:3a7713b1edbc 135 uint16_t timeout; /*!< SPI transfer timeout, the unit is SCK cycles */
AnnaBridge 171:3a7713b1edbc 136 uint8_t csHighTime; /*!< CS high time cycles */
AnnaBridge 171:3a7713b1edbc 137 bool disablePrefetch; /*!< True means SPIFI will not attempt a speculative prefetch. */
AnnaBridge 171:3a7713b1edbc 138 bool disableCachePrefech; /*!< Disable prefetch of cache line */
AnnaBridge 171:3a7713b1edbc 139 bool isFeedbackClock; /*!< Is data sample uses feedback clock. */
AnnaBridge 171:3a7713b1edbc 140 spifi_spi_mode_t spiMode; /*!< SPIFI spi mode select */
AnnaBridge 171:3a7713b1edbc 141 bool isReadFullClockCycle; /*!< If enable read full clock cycle. */
AnnaBridge 171:3a7713b1edbc 142 spifi_dual_mode_t dualMode; /*!< SPIFI dual mode, dual or quad. */
AnnaBridge 171:3a7713b1edbc 143 } spifi_config_t;
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 /*! @brief Transfer structure for SPIFI */
AnnaBridge 171:3a7713b1edbc 146 typedef struct _spifi_transfer
AnnaBridge 171:3a7713b1edbc 147 {
AnnaBridge 171:3a7713b1edbc 148 uint8_t *data; /*!< Pointer to data to transmit */
AnnaBridge 171:3a7713b1edbc 149 size_t dataSize; /*!< Bytes to be transmit */
AnnaBridge 171:3a7713b1edbc 150 } spifi_transfer_t;
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 153 * API
AnnaBridge 171:3a7713b1edbc 154 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 157 extern "C" {
AnnaBridge 171:3a7713b1edbc 158 #endif /* _cplusplus */
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /*!
AnnaBridge 171:3a7713b1edbc 161 * @name Initialization and deinitialization
AnnaBridge 171:3a7713b1edbc 162 * @{
AnnaBridge 171:3a7713b1edbc 163 */
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165 /*!
AnnaBridge 171:3a7713b1edbc 166 * @brief Initializes the SPIFI with the user configuration structure.
AnnaBridge 171:3a7713b1edbc 167 *
AnnaBridge 171:3a7713b1edbc 168 * This function configures the SPIFI module with the user-defined configuration.
AnnaBridge 171:3a7713b1edbc 169 *
AnnaBridge 171:3a7713b1edbc 170 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 171 * @param config The pointer to the configuration structure.
AnnaBridge 171:3a7713b1edbc 172 */
AnnaBridge 171:3a7713b1edbc 173 void SPIFI_Init(SPIFI_Type *base, const spifi_config_t *config);
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 /*!
AnnaBridge 171:3a7713b1edbc 176 * @brief Get SPIFI default configure settings.
AnnaBridge 171:3a7713b1edbc 177 *
AnnaBridge 171:3a7713b1edbc 178 * @param config SPIFI config structure pointer.
AnnaBridge 171:3a7713b1edbc 179 */
AnnaBridge 171:3a7713b1edbc 180 void SPIFI_GetDefaultConfig(spifi_config_t *config);
AnnaBridge 171:3a7713b1edbc 181
AnnaBridge 171:3a7713b1edbc 182 /*!
AnnaBridge 171:3a7713b1edbc 183 * @brief Deinitializes the SPIFI regions.
AnnaBridge 171:3a7713b1edbc 184 *
AnnaBridge 171:3a7713b1edbc 185 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 186 */
AnnaBridge 171:3a7713b1edbc 187 void SPIFI_Deinit(SPIFI_Type *base);
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /* @}*/
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 /*!
AnnaBridge 171:3a7713b1edbc 192 * @name Basic Control Operations
AnnaBridge 171:3a7713b1edbc 193 * @{
AnnaBridge 171:3a7713b1edbc 194 */
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 /*!
AnnaBridge 171:3a7713b1edbc 197 * @brief Set SPIFI flash command.
AnnaBridge 171:3a7713b1edbc 198 *
AnnaBridge 171:3a7713b1edbc 199 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 200 * @param cmd SPIFI command structure pointer.
AnnaBridge 171:3a7713b1edbc 201 */
AnnaBridge 171:3a7713b1edbc 202 void SPIFI_SetCommand(SPIFI_Type *base, spifi_command_t *cmd);
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204 /*!
AnnaBridge 171:3a7713b1edbc 205 * @brief Set SPIFI command address.
AnnaBridge 171:3a7713b1edbc 206 *
AnnaBridge 171:3a7713b1edbc 207 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 208 * @param addr Address value for the command.
AnnaBridge 171:3a7713b1edbc 209 */
AnnaBridge 171:3a7713b1edbc 210 static inline void SPIFI_SetCommandAddress(SPIFI_Type *base, uint32_t addr)
AnnaBridge 171:3a7713b1edbc 211 {
AnnaBridge 171:3a7713b1edbc 212 base->ADDR = addr;
AnnaBridge 171:3a7713b1edbc 213 }
AnnaBridge 171:3a7713b1edbc 214
AnnaBridge 171:3a7713b1edbc 215 /*!
AnnaBridge 171:3a7713b1edbc 216 * @brief Set SPIFI intermediate data.
AnnaBridge 171:3a7713b1edbc 217 *
AnnaBridge 171:3a7713b1edbc 218 * Before writing a command wihch needs specific intermediate value, users shall call this function to write it.
AnnaBridge 171:3a7713b1edbc 219 * The main use of this function for current serial flash is to select no-opcode mode and cancelling this mode. As
AnnaBridge 171:3a7713b1edbc 220 * dummy cycle do not care about the value, no need to call this function.
AnnaBridge 171:3a7713b1edbc 221 *
AnnaBridge 171:3a7713b1edbc 222 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 223 * @param val Intermediate data.
AnnaBridge 171:3a7713b1edbc 224 */
AnnaBridge 171:3a7713b1edbc 225 static inline void SPIFI_SetIntermediateData(SPIFI_Type *base, uint32_t val)
AnnaBridge 171:3a7713b1edbc 226 {
AnnaBridge 171:3a7713b1edbc 227 base->IDATA = val;
AnnaBridge 171:3a7713b1edbc 228 }
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 /*!
AnnaBridge 171:3a7713b1edbc 231 * @brief Set SPIFI Cache limit value.
AnnaBridge 171:3a7713b1edbc 232 *
AnnaBridge 171:3a7713b1edbc 233 * SPIFI includes caching of prevously-accessed data to improve performance. Software can write an address to this
AnnaBridge 171:3a7713b1edbc 234 * function, to prevent such caching at and above the address.
AnnaBridge 171:3a7713b1edbc 235 *
AnnaBridge 171:3a7713b1edbc 236 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 237 * @param val Zero-based upper limit of cacheable memory.
AnnaBridge 171:3a7713b1edbc 238 */
AnnaBridge 171:3a7713b1edbc 239 static inline void SPIFI_SetCacheLimit(SPIFI_Type *base, uint32_t val)
AnnaBridge 171:3a7713b1edbc 240 {
AnnaBridge 171:3a7713b1edbc 241 base->CLIMIT = val;
AnnaBridge 171:3a7713b1edbc 242 }
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 /*!
AnnaBridge 171:3a7713b1edbc 245 * @brief Reset the command field of SPIFI.
AnnaBridge 171:3a7713b1edbc 246 *
AnnaBridge 171:3a7713b1edbc 247 * This function is used to abort the current command or memory mode.
AnnaBridge 171:3a7713b1edbc 248 *
AnnaBridge 171:3a7713b1edbc 249 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 250 */
AnnaBridge 171:3a7713b1edbc 251 static inline void SPIFI_ResetCommand(SPIFI_Type *base)
AnnaBridge 171:3a7713b1edbc 252 {
AnnaBridge 171:3a7713b1edbc 253 base->STAT = SPIFI_STAT_RESET_MASK;
AnnaBridge 171:3a7713b1edbc 254 /* Wait for the RESET flag cleared by HW */
AnnaBridge 171:3a7713b1edbc 255 while (base->STAT & SPIFI_STAT_RESET_MASK)
AnnaBridge 171:3a7713b1edbc 256 {
AnnaBridge 171:3a7713b1edbc 257 }
AnnaBridge 171:3a7713b1edbc 258 }
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 /*!
AnnaBridge 171:3a7713b1edbc 261 * @brief Set SPIFI flash AHB read command.
AnnaBridge 171:3a7713b1edbc 262 *
AnnaBridge 171:3a7713b1edbc 263 * Call this function means SPIFI enters to memory mode, while users need to use command, a SPIFI_ResetCommand shall
AnnaBridge 171:3a7713b1edbc 264 * be called.
AnnaBridge 171:3a7713b1edbc 265 *
AnnaBridge 171:3a7713b1edbc 266 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 267 * @param cmd SPIFI command structure pointer.
AnnaBridge 171:3a7713b1edbc 268 */
AnnaBridge 171:3a7713b1edbc 269 void SPIFI_SetMemoryCommand(SPIFI_Type *base, spifi_command_t *cmd);
AnnaBridge 171:3a7713b1edbc 270
AnnaBridge 171:3a7713b1edbc 271 /*!
AnnaBridge 171:3a7713b1edbc 272 * @brief Enable SPIFI interrupt.
AnnaBridge 171:3a7713b1edbc 273 *
AnnaBridge 171:3a7713b1edbc 274 * The interrupt is triggered only in command mode, and it means the command now is finished.
AnnaBridge 171:3a7713b1edbc 275 *
AnnaBridge 171:3a7713b1edbc 276 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 277 * @param mask SPIFI interrupt enable mask. It is a logic OR of members the
AnnaBridge 171:3a7713b1edbc 278 * enumeration :: spifi_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 279 */
AnnaBridge 171:3a7713b1edbc 280 static inline void SPIFI_EnableInterrupt(SPIFI_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 281 {
AnnaBridge 171:3a7713b1edbc 282 base->CTRL |= mask;
AnnaBridge 171:3a7713b1edbc 283 }
AnnaBridge 171:3a7713b1edbc 284
AnnaBridge 171:3a7713b1edbc 285 /*!
AnnaBridge 171:3a7713b1edbc 286 * @brief Disable SPIFI interrupt.
AnnaBridge 171:3a7713b1edbc 287 *
AnnaBridge 171:3a7713b1edbc 288 * The interrupt is triggered only in command mode, and it means the command now is finished.
AnnaBridge 171:3a7713b1edbc 289 *
AnnaBridge 171:3a7713b1edbc 290 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 291 * @param mask SPIFI interrupt enable mask. It is a logic OR of members the
AnnaBridge 171:3a7713b1edbc 292 * enumeration :: spifi_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 293 */
AnnaBridge 171:3a7713b1edbc 294 static inline void SPIFI_DisableInterrupt(SPIFI_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 295 {
AnnaBridge 171:3a7713b1edbc 296 base->CTRL &= ~mask;
AnnaBridge 171:3a7713b1edbc 297 }
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 /*!
AnnaBridge 171:3a7713b1edbc 300 * @name Status
AnnaBridge 171:3a7713b1edbc 301 * @{
AnnaBridge 171:3a7713b1edbc 302 */
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304 /*!
AnnaBridge 171:3a7713b1edbc 305 * @brief Get the status of all interrupt flags for SPIFI.
AnnaBridge 171:3a7713b1edbc 306 *
AnnaBridge 171:3a7713b1edbc 307 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 308 * @return SPIFI flag status
AnnaBridge 171:3a7713b1edbc 309 */
AnnaBridge 171:3a7713b1edbc 310 static inline uint32_t SPIFI_GetStatusFlag(SPIFI_Type *base)
AnnaBridge 171:3a7713b1edbc 311 {
AnnaBridge 171:3a7713b1edbc 312 return base->STAT;
AnnaBridge 171:3a7713b1edbc 313 }
AnnaBridge 171:3a7713b1edbc 314
AnnaBridge 171:3a7713b1edbc 315 /* @}*/
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 /*!
AnnaBridge 171:3a7713b1edbc 318 * @brief Enable or disable DMA request for SPIFI.
AnnaBridge 171:3a7713b1edbc 319 *
AnnaBridge 171:3a7713b1edbc 320 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 321 * @param enable True means enable DMA and false means disable DMA.
AnnaBridge 171:3a7713b1edbc 322 */
AnnaBridge 171:3a7713b1edbc 323 static inline void SPIFI_EnableDMA(SPIFI_Type *base, bool enable)
AnnaBridge 171:3a7713b1edbc 324 {
AnnaBridge 171:3a7713b1edbc 325 if (enable)
AnnaBridge 171:3a7713b1edbc 326 {
AnnaBridge 171:3a7713b1edbc 327 base->CTRL |= SPIFI_CTRL_DMAEN_MASK;
AnnaBridge 171:3a7713b1edbc 328 }
AnnaBridge 171:3a7713b1edbc 329 else
AnnaBridge 171:3a7713b1edbc 330 {
AnnaBridge 171:3a7713b1edbc 331 base->CTRL &= ~SPIFI_CTRL_DMAEN_MASK;
AnnaBridge 171:3a7713b1edbc 332 }
AnnaBridge 171:3a7713b1edbc 333 }
AnnaBridge 171:3a7713b1edbc 334
AnnaBridge 171:3a7713b1edbc 335 /*!
AnnaBridge 171:3a7713b1edbc 336 * @brief Gets the SPIFI data register address.
AnnaBridge 171:3a7713b1edbc 337 *
AnnaBridge 171:3a7713b1edbc 338 * This API is used to provide a transfer address for the SPIFI DMA transfer configuration.
AnnaBridge 171:3a7713b1edbc 339 *
AnnaBridge 171:3a7713b1edbc 340 * @param base SPIFI base pointer
AnnaBridge 171:3a7713b1edbc 341 * @return data register address
AnnaBridge 171:3a7713b1edbc 342 */
AnnaBridge 171:3a7713b1edbc 343 static inline uint32_t SPIFI_GetDataRegisterAddress(SPIFI_Type *base)
AnnaBridge 171:3a7713b1edbc 344 {
AnnaBridge 171:3a7713b1edbc 345 return (uint32_t)(&(base->DATA));
AnnaBridge 171:3a7713b1edbc 346 }
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 /*!
AnnaBridge 171:3a7713b1edbc 349 * @brief Write a word data in address of SPIFI.
AnnaBridge 171:3a7713b1edbc 350 *
AnnaBridge 171:3a7713b1edbc 351 * Users can write a page or at least a word data into SPIFI address.
AnnaBridge 171:3a7713b1edbc 352 *
AnnaBridge 171:3a7713b1edbc 353 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 354 * @param data Data need be write.
AnnaBridge 171:3a7713b1edbc 355 */
AnnaBridge 171:3a7713b1edbc 356 static inline void SPIFI_WriteData(SPIFI_Type *base, uint32_t data)
AnnaBridge 171:3a7713b1edbc 357 {
AnnaBridge 171:3a7713b1edbc 358 base->DATA = data;
AnnaBridge 171:3a7713b1edbc 359 }
AnnaBridge 171:3a7713b1edbc 360
AnnaBridge 171:3a7713b1edbc 361 /*!
AnnaBridge 171:3a7713b1edbc 362 * @brief Read data from serial flash.
AnnaBridge 171:3a7713b1edbc 363 *
AnnaBridge 171:3a7713b1edbc 364 * Users should notice before call this function, the data length field in command register shall larger
AnnaBridge 171:3a7713b1edbc 365 * than 4, otherwise a hardfault will happen.
AnnaBridge 171:3a7713b1edbc 366 *
AnnaBridge 171:3a7713b1edbc 367 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 368 * @return Data input from flash.
AnnaBridge 171:3a7713b1edbc 369 */
AnnaBridge 171:3a7713b1edbc 370 static inline uint32_t SPIFI_ReadData(SPIFI_Type *base)
AnnaBridge 171:3a7713b1edbc 371 {
AnnaBridge 171:3a7713b1edbc 372 return base->DATA;
AnnaBridge 171:3a7713b1edbc 373 }
AnnaBridge 171:3a7713b1edbc 374
AnnaBridge 171:3a7713b1edbc 375 /* @} */
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 378 }
AnnaBridge 171:3a7713b1edbc 379 #endif
AnnaBridge 171:3a7713b1edbc 380
AnnaBridge 171:3a7713b1edbc 381 /*! @}*/
AnnaBridge 171:3a7713b1edbc 382
AnnaBridge 171:3a7713b1edbc 383 #endif /* _FSL_SPIFI_H_ */