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TARGET_LPC546XX/TOOLCHAIN_ARM_STD/fsl_spi.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * The Clear BSD License
AnnaBridge 171:3a7713b1edbc 3 * Copyright (c) 2016, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 4 * Copyright 2016-2017 NXP
AnnaBridge 171:3a7713b1edbc 5 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 6 *
AnnaBridge 171:3a7713b1edbc 7 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 8 * are permitted (subject to the limitations in the disclaimer below) provided
AnnaBridge 171:3a7713b1edbc 9 * that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 12 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 15 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 16 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 171:3a7713b1edbc 19 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 20 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
AnnaBridge 171:3a7713b1edbc 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 33 */
AnnaBridge 171:3a7713b1edbc 34 #ifndef _FSL_SPI_H_
AnnaBridge 171:3a7713b1edbc 35 #define _FSL_SPI_H_
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 38 #include "fsl_flexcomm.h"
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /*!
AnnaBridge 171:3a7713b1edbc 41 * @addtogroup spi_driver
AnnaBridge 171:3a7713b1edbc 42 * @{
AnnaBridge 171:3a7713b1edbc 43 */
AnnaBridge 171:3a7713b1edbc 44
AnnaBridge 171:3a7713b1edbc 45 /*! @file */
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 48 * Definitions
AnnaBridge 171:3a7713b1edbc 49 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 52 /*@{*/
AnnaBridge 171:3a7713b1edbc 53 /*! @brief SPI driver version 2.0.1. */
AnnaBridge 171:3a7713b1edbc 54 #define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
AnnaBridge 171:3a7713b1edbc 55 /*@}*/
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 #ifndef SPI_DUMMYDATA
AnnaBridge 171:3a7713b1edbc 58 /*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */
AnnaBridge 171:3a7713b1edbc 59 #define SPI_DUMMYDATA (0xFFU)
AnnaBridge 171:3a7713b1edbc 60 #endif
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 #define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF)
AnnaBridge 171:3a7713b1edbc 63 #define SPI_CTRLMASK (0xFFFF0000)
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 #define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000)
AnnaBridge 171:3a7713b1edbc 66 #define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16))
AnnaBridge 171:3a7713b1edbc 67 #define SPI_DEASSERT_ALL (0xF0000)
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 #define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK))
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 #define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT)
AnnaBridge 171:3a7713b1edbc 72 #define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT)
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 /*! @brief SPI transfer option.*/
AnnaBridge 171:3a7713b1edbc 75 typedef enum _spi_xfer_option
AnnaBridge 171:3a7713b1edbc 76 {
AnnaBridge 171:3a7713b1edbc 77 kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< Delay chip select */
AnnaBridge 171:3a7713b1edbc 78 kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< When transfer ends, assert chip select */
AnnaBridge 171:3a7713b1edbc 79 } spi_xfer_option_t;
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 /*! @brief SPI data shifter direction options.*/
AnnaBridge 171:3a7713b1edbc 82 typedef enum _spi_shift_direction
AnnaBridge 171:3a7713b1edbc 83 {
AnnaBridge 171:3a7713b1edbc 84 kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */
AnnaBridge 171:3a7713b1edbc 85 kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */
AnnaBridge 171:3a7713b1edbc 86 } spi_shift_direction_t;
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 /*! @brief SPI clock polarity configuration.*/
AnnaBridge 171:3a7713b1edbc 89 typedef enum _spi_clock_polarity
AnnaBridge 171:3a7713b1edbc 90 {
AnnaBridge 171:3a7713b1edbc 91 kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
AnnaBridge 171:3a7713b1edbc 92 kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */
AnnaBridge 171:3a7713b1edbc 93 } spi_clock_polarity_t;
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 /*! @brief SPI clock phase configuration.*/
AnnaBridge 171:3a7713b1edbc 96 typedef enum _spi_clock_phase
AnnaBridge 171:3a7713b1edbc 97 {
AnnaBridge 171:3a7713b1edbc 98 kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first
AnnaBridge 171:3a7713b1edbc 99 * cycle of a data transfer. */
AnnaBridge 171:3a7713b1edbc 100 kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the
AnnaBridge 171:3a7713b1edbc 101 * first cycle of a data transfer. */
AnnaBridge 171:3a7713b1edbc 102 } spi_clock_phase_t;
AnnaBridge 171:3a7713b1edbc 103
AnnaBridge 171:3a7713b1edbc 104 /*! @brief txFIFO watermark values */
AnnaBridge 171:3a7713b1edbc 105 typedef enum _spi_txfifo_watermark
AnnaBridge 171:3a7713b1edbc 106 {
AnnaBridge 171:3a7713b1edbc 107 kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */
AnnaBridge 171:3a7713b1edbc 108 kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */
AnnaBridge 171:3a7713b1edbc 109 kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */
AnnaBridge 171:3a7713b1edbc 110 kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */
AnnaBridge 171:3a7713b1edbc 111 kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */
AnnaBridge 171:3a7713b1edbc 112 kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */
AnnaBridge 171:3a7713b1edbc 113 kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */
AnnaBridge 171:3a7713b1edbc 114 kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */
AnnaBridge 171:3a7713b1edbc 115 } spi_txfifo_watermark_t;
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117 /*! @brief rxFIFO watermark values */
AnnaBridge 171:3a7713b1edbc 118 typedef enum _spi_rxfifo_watermark
AnnaBridge 171:3a7713b1edbc 119 {
AnnaBridge 171:3a7713b1edbc 120 kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */
AnnaBridge 171:3a7713b1edbc 121 kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */
AnnaBridge 171:3a7713b1edbc 122 kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */
AnnaBridge 171:3a7713b1edbc 123 kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */
AnnaBridge 171:3a7713b1edbc 124 kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */
AnnaBridge 171:3a7713b1edbc 125 kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */
AnnaBridge 171:3a7713b1edbc 126 kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */
AnnaBridge 171:3a7713b1edbc 127 kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */
AnnaBridge 171:3a7713b1edbc 128 } spi_rxfifo_watermark_t;
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /*! @brief Transfer data width */
AnnaBridge 171:3a7713b1edbc 131 typedef enum _spi_data_width
AnnaBridge 171:3a7713b1edbc 132 {
AnnaBridge 171:3a7713b1edbc 133 kSPI_Data4Bits = 3, /*!< 4 bits data width */
AnnaBridge 171:3a7713b1edbc 134 kSPI_Data5Bits = 4, /*!< 5 bits data width */
AnnaBridge 171:3a7713b1edbc 135 kSPI_Data6Bits = 5, /*!< 6 bits data width */
AnnaBridge 171:3a7713b1edbc 136 kSPI_Data7Bits = 6, /*!< 7 bits data width */
AnnaBridge 171:3a7713b1edbc 137 kSPI_Data8Bits = 7, /*!< 8 bits data width */
AnnaBridge 171:3a7713b1edbc 138 kSPI_Data9Bits = 8, /*!< 9 bits data width */
AnnaBridge 171:3a7713b1edbc 139 kSPI_Data10Bits = 9, /*!< 10 bits data width */
AnnaBridge 171:3a7713b1edbc 140 kSPI_Data11Bits = 10, /*!< 11 bits data width */
AnnaBridge 171:3a7713b1edbc 141 kSPI_Data12Bits = 11, /*!< 12 bits data width */
AnnaBridge 171:3a7713b1edbc 142 kSPI_Data13Bits = 12, /*!< 13 bits data width */
AnnaBridge 171:3a7713b1edbc 143 kSPI_Data14Bits = 13, /*!< 14 bits data width */
AnnaBridge 171:3a7713b1edbc 144 kSPI_Data15Bits = 14, /*!< 15 bits data width */
AnnaBridge 171:3a7713b1edbc 145 kSPI_Data16Bits = 15, /*!< 16 bits data width */
AnnaBridge 171:3a7713b1edbc 146 } spi_data_width_t;
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /*! @brief Slave select */
AnnaBridge 171:3a7713b1edbc 149 typedef enum _spi_ssel
AnnaBridge 171:3a7713b1edbc 150 {
AnnaBridge 171:3a7713b1edbc 151 kSPI_Ssel0 = 0, /*!< Slave select 0 */
AnnaBridge 171:3a7713b1edbc 152 kSPI_Ssel1 = 1, /*!< Slave select 1 */
AnnaBridge 171:3a7713b1edbc 153 kSPI_Ssel2 = 2, /*!< Slave select 2 */
AnnaBridge 171:3a7713b1edbc 154 kSPI_Ssel3 = 3, /*!< Slave select 3 */
AnnaBridge 171:3a7713b1edbc 155 } spi_ssel_t;
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 /*! @brief ssel polarity */
AnnaBridge 171:3a7713b1edbc 158 typedef enum _spi_spol
AnnaBridge 171:3a7713b1edbc 159 {
AnnaBridge 171:3a7713b1edbc 160 kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1),
AnnaBridge 171:3a7713b1edbc 161 kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1),
AnnaBridge 171:3a7713b1edbc 162 kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1),
AnnaBridge 171:3a7713b1edbc 163 kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1),
AnnaBridge 171:3a7713b1edbc 164 kSPI_SpolActiveAllHigh =
AnnaBridge 171:3a7713b1edbc 165 (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh),
AnnaBridge 171:3a7713b1edbc 166 kSPI_SpolActiveAllLow = 0,
AnnaBridge 171:3a7713b1edbc 167 } spi_spol_t;
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 /*!
AnnaBridge 171:3a7713b1edbc 170 * @brief SPI delay time configure structure.
AnnaBridge 171:3a7713b1edbc 171 * Note:
AnnaBridge 171:3a7713b1edbc 172 * The DLY register controls several programmable delays related to SPI signalling,
AnnaBridge 171:3a7713b1edbc 173 * it stands for how many SPI clock time will be inserted.
AnnaBridge 171:3a7713b1edbc 174 * The maxinun value of these delay time is 15.
AnnaBridge 171:3a7713b1edbc 175 */
AnnaBridge 171:3a7713b1edbc 176 typedef struct _spi_delay_config
AnnaBridge 171:3a7713b1edbc 177 {
AnnaBridge 171:3a7713b1edbc 178 uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */
AnnaBridge 171:3a7713b1edbc 179 uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */
AnnaBridge 171:3a7713b1edbc 180 uint8_t frameDelay; /*!< Delay between frame to frame. */
AnnaBridge 171:3a7713b1edbc 181 uint8_t transferDelay; /*!< Delay between transfer to transfer. */
AnnaBridge 171:3a7713b1edbc 182 } spi_delay_config_t;
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 /*! @brief SPI master user configure structure.*/
AnnaBridge 171:3a7713b1edbc 185 typedef struct _spi_master_config
AnnaBridge 171:3a7713b1edbc 186 {
AnnaBridge 171:3a7713b1edbc 187 bool enableLoopback; /*!< Enable loopback for test purpose */
AnnaBridge 171:3a7713b1edbc 188 bool enableMaster; /*!< Enable SPI at initialization time */
AnnaBridge 171:3a7713b1edbc 189 spi_clock_polarity_t polarity; /*!< Clock polarity */
AnnaBridge 171:3a7713b1edbc 190 spi_clock_phase_t phase; /*!< Clock phase */
AnnaBridge 171:3a7713b1edbc 191 spi_shift_direction_t direction; /*!< MSB or LSB */
AnnaBridge 171:3a7713b1edbc 192 uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */
AnnaBridge 171:3a7713b1edbc 193 spi_data_width_t dataWidth; /*!< Width of the data */
AnnaBridge 171:3a7713b1edbc 194 spi_ssel_t sselNum; /*!< Slave select number */
AnnaBridge 171:3a7713b1edbc 195 spi_spol_t sselPol; /*!< Configure active CS polarity */
AnnaBridge 171:3a7713b1edbc 196 spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
AnnaBridge 171:3a7713b1edbc 197 spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
AnnaBridge 171:3a7713b1edbc 198 spi_delay_config_t delayConfig; /*!< Delay configuration. */
AnnaBridge 171:3a7713b1edbc 199 } spi_master_config_t;
AnnaBridge 171:3a7713b1edbc 200
AnnaBridge 171:3a7713b1edbc 201 /*! @brief SPI slave user configure structure.*/
AnnaBridge 171:3a7713b1edbc 202 typedef struct _spi_slave_config
AnnaBridge 171:3a7713b1edbc 203 {
AnnaBridge 171:3a7713b1edbc 204 bool enableSlave; /*!< Enable SPI at initialization time */
AnnaBridge 171:3a7713b1edbc 205 spi_clock_polarity_t polarity; /*!< Clock polarity */
AnnaBridge 171:3a7713b1edbc 206 spi_clock_phase_t phase; /*!< Clock phase */
AnnaBridge 171:3a7713b1edbc 207 spi_shift_direction_t direction; /*!< MSB or LSB */
AnnaBridge 171:3a7713b1edbc 208 spi_data_width_t dataWidth; /*!< Width of the data */
AnnaBridge 171:3a7713b1edbc 209 spi_spol_t sselPol; /*!< Configure active CS polarity */
AnnaBridge 171:3a7713b1edbc 210 spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
AnnaBridge 171:3a7713b1edbc 211 spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
AnnaBridge 171:3a7713b1edbc 212 } spi_slave_config_t;
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 /*! @brief SPI transfer status.*/
AnnaBridge 171:3a7713b1edbc 215 enum _spi_status
AnnaBridge 171:3a7713b1edbc 216 {
AnnaBridge 171:3a7713b1edbc 217 kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */
AnnaBridge 171:3a7713b1edbc 218 kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */
AnnaBridge 171:3a7713b1edbc 219 kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */
AnnaBridge 171:3a7713b1edbc 220 kStatus_SPI_BaudrateNotSupport =
AnnaBridge 171:3a7713b1edbc 221 MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */
AnnaBridge 171:3a7713b1edbc 222 };
AnnaBridge 171:3a7713b1edbc 223
AnnaBridge 171:3a7713b1edbc 224 /*! @brief SPI interrupt sources.*/
AnnaBridge 171:3a7713b1edbc 225 enum _spi_interrupt_enable
AnnaBridge 171:3a7713b1edbc 226 {
AnnaBridge 171:3a7713b1edbc 227 kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */
AnnaBridge 171:3a7713b1edbc 228 kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */
AnnaBridge 171:3a7713b1edbc 229 };
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /*! @brief SPI status flags.*/
AnnaBridge 171:3a7713b1edbc 232 enum _spi_statusflags
AnnaBridge 171:3a7713b1edbc 233 {
AnnaBridge 171:3a7713b1edbc 234 kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */
AnnaBridge 171:3a7713b1edbc 235 kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */
AnnaBridge 171:3a7713b1edbc 236 kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */
AnnaBridge 171:3a7713b1edbc 237 kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */
AnnaBridge 171:3a7713b1edbc 238 };
AnnaBridge 171:3a7713b1edbc 239
AnnaBridge 171:3a7713b1edbc 240 /*! @brief SPI transfer structure */
AnnaBridge 171:3a7713b1edbc 241 typedef struct _spi_transfer
AnnaBridge 171:3a7713b1edbc 242 {
AnnaBridge 171:3a7713b1edbc 243 uint8_t *txData; /*!< Send buffer */
AnnaBridge 171:3a7713b1edbc 244 uint8_t *rxData; /*!< Receive buffer */
AnnaBridge 171:3a7713b1edbc 245 uint32_t configFlags; /*!< Additional option to control transfer */
AnnaBridge 171:3a7713b1edbc 246 size_t dataSize; /*!< Transfer bytes */
AnnaBridge 171:3a7713b1edbc 247 } spi_transfer_t;
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249 /*! @brief SPI half-duplex(master only) transfer structure */
AnnaBridge 171:3a7713b1edbc 250 typedef struct _spi_half_duplex_transfer
AnnaBridge 171:3a7713b1edbc 251 {
AnnaBridge 171:3a7713b1edbc 252 uint8_t *txData; /*!< Send buffer */
AnnaBridge 171:3a7713b1edbc 253 uint8_t *rxData; /*!< Receive buffer */
AnnaBridge 171:3a7713b1edbc 254 size_t txDataSize; /*!< Transfer bytes for transmit */
AnnaBridge 171:3a7713b1edbc 255 size_t rxDataSize; /*!< Transfer bytes */
AnnaBridge 171:3a7713b1edbc 256 uint32_t configFlags; /*!< Transfer configuration flags. */
AnnaBridge 171:3a7713b1edbc 257 bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for
AnnaBridge 171:3a7713b1edbc 258 deassert. */
AnnaBridge 171:3a7713b1edbc 259 bool isTransmitFirst; /*!< True for transmit first and false for receive first. */
AnnaBridge 171:3a7713b1edbc 260 } spi_half_duplex_transfer_t;
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 /*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */
AnnaBridge 171:3a7713b1edbc 263 typedef struct _spi_config
AnnaBridge 171:3a7713b1edbc 264 {
AnnaBridge 171:3a7713b1edbc 265 spi_data_width_t dataWidth;
AnnaBridge 171:3a7713b1edbc 266 spi_ssel_t sselNum;
AnnaBridge 171:3a7713b1edbc 267 } spi_config_t;
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 /*! @brief Master handle type */
AnnaBridge 171:3a7713b1edbc 270 typedef struct _spi_master_handle spi_master_handle_t;
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 /*! @brief Slave handle type */
AnnaBridge 171:3a7713b1edbc 273 typedef spi_master_handle_t spi_slave_handle_t;
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 /*! @brief SPI master callback for finished transmit */
AnnaBridge 171:3a7713b1edbc 276 typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 /*! @brief SPI slave callback for finished transmit */
AnnaBridge 171:3a7713b1edbc 279 typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
AnnaBridge 171:3a7713b1edbc 280
AnnaBridge 171:3a7713b1edbc 281 /*! @brief SPI transfer handle structure */
AnnaBridge 171:3a7713b1edbc 282 struct _spi_master_handle
AnnaBridge 171:3a7713b1edbc 283 {
AnnaBridge 171:3a7713b1edbc 284 uint8_t *volatile txData; /*!< Transfer buffer */
AnnaBridge 171:3a7713b1edbc 285 uint8_t *volatile rxData; /*!< Receive buffer */
AnnaBridge 171:3a7713b1edbc 286 volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */
AnnaBridge 171:3a7713b1edbc 287 volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */
AnnaBridge 171:3a7713b1edbc 288 volatile size_t toReceiveCount; /*!< Receive data remaining in bytes */
AnnaBridge 171:3a7713b1edbc 289 size_t totalByteCount; /*!< A number of transfer bytes */
AnnaBridge 171:3a7713b1edbc 290 volatile uint32_t state; /*!< SPI internal state */
AnnaBridge 171:3a7713b1edbc 291 spi_master_callback_t callback; /*!< SPI callback */
AnnaBridge 171:3a7713b1edbc 292 void *userData; /*!< Callback parameter */
AnnaBridge 171:3a7713b1edbc 293 uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */
AnnaBridge 171:3a7713b1edbc 294 uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */
AnnaBridge 171:3a7713b1edbc 295 uint32_t configFlags; /*!< Additional option to control transfer */
AnnaBridge 171:3a7713b1edbc 296 spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
AnnaBridge 171:3a7713b1edbc 297 spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
AnnaBridge 171:3a7713b1edbc 298 };
AnnaBridge 171:3a7713b1edbc 299
AnnaBridge 171:3a7713b1edbc 300 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 301 extern "C" {
AnnaBridge 171:3a7713b1edbc 302 #endif
AnnaBridge 171:3a7713b1edbc 303 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 304 * API
AnnaBridge 171:3a7713b1edbc 305 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 306
AnnaBridge 171:3a7713b1edbc 307 /*! @brief Returns instance number for SPI peripheral base address. */
AnnaBridge 171:3a7713b1edbc 308 uint32_t SPI_GetInstance(SPI_Type *base);
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 /*!
AnnaBridge 171:3a7713b1edbc 311 * @name Initialization and deinitialization
AnnaBridge 171:3a7713b1edbc 312 * @{
AnnaBridge 171:3a7713b1edbc 313 */
AnnaBridge 171:3a7713b1edbc 314
AnnaBridge 171:3a7713b1edbc 315 /*!
AnnaBridge 171:3a7713b1edbc 316 * @brief Sets the SPI master configuration structure to default values.
AnnaBridge 171:3a7713b1edbc 317 *
AnnaBridge 171:3a7713b1edbc 318 * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
AnnaBridge 171:3a7713b1edbc 319 * User may use the initialized structure unchanged in SPI_MasterInit(), or modify
AnnaBridge 171:3a7713b1edbc 320 * some fields of the structure before calling SPI_MasterInit(). After calling this API,
AnnaBridge 171:3a7713b1edbc 321 * the master is ready to transfer.
AnnaBridge 171:3a7713b1edbc 322 * Example:
AnnaBridge 171:3a7713b1edbc 323 @code
AnnaBridge 171:3a7713b1edbc 324 spi_master_config_t config;
AnnaBridge 171:3a7713b1edbc 325 SPI_MasterGetDefaultConfig(&config);
AnnaBridge 171:3a7713b1edbc 326 @endcode
AnnaBridge 171:3a7713b1edbc 327 *
AnnaBridge 171:3a7713b1edbc 328 * @param config pointer to master config structure
AnnaBridge 171:3a7713b1edbc 329 */
AnnaBridge 171:3a7713b1edbc 330 void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 /*!
AnnaBridge 171:3a7713b1edbc 333 * @brief Initializes the SPI with master configuration.
AnnaBridge 171:3a7713b1edbc 334 *
AnnaBridge 171:3a7713b1edbc 335 * The configuration structure can be filled by user from scratch, or be set with default
AnnaBridge 171:3a7713b1edbc 336 * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
AnnaBridge 171:3a7713b1edbc 337 * Example
AnnaBridge 171:3a7713b1edbc 338 @code
AnnaBridge 171:3a7713b1edbc 339 spi_master_config_t config = {
AnnaBridge 171:3a7713b1edbc 340 .baudRate_Bps = 400000,
AnnaBridge 171:3a7713b1edbc 341 ...
AnnaBridge 171:3a7713b1edbc 342 };
AnnaBridge 171:3a7713b1edbc 343 SPI_MasterInit(SPI0, &config);
AnnaBridge 171:3a7713b1edbc 344 @endcode
AnnaBridge 171:3a7713b1edbc 345 *
AnnaBridge 171:3a7713b1edbc 346 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 347 * @param config pointer to master configuration structure
AnnaBridge 171:3a7713b1edbc 348 * @param srcClock_Hz Source clock frequency.
AnnaBridge 171:3a7713b1edbc 349 */
AnnaBridge 171:3a7713b1edbc 350 status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
AnnaBridge 171:3a7713b1edbc 351
AnnaBridge 171:3a7713b1edbc 352 /*!
AnnaBridge 171:3a7713b1edbc 353 * @brief Sets the SPI slave configuration structure to default values.
AnnaBridge 171:3a7713b1edbc 354 *
AnnaBridge 171:3a7713b1edbc 355 * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
AnnaBridge 171:3a7713b1edbc 356 * Modify some fields of the structure before calling SPI_SlaveInit().
AnnaBridge 171:3a7713b1edbc 357 * Example:
AnnaBridge 171:3a7713b1edbc 358 @code
AnnaBridge 171:3a7713b1edbc 359 spi_slave_config_t config;
AnnaBridge 171:3a7713b1edbc 360 SPI_SlaveGetDefaultConfig(&config);
AnnaBridge 171:3a7713b1edbc 361 @endcode
AnnaBridge 171:3a7713b1edbc 362 *
AnnaBridge 171:3a7713b1edbc 363 * @param config pointer to slave configuration structure
AnnaBridge 171:3a7713b1edbc 364 */
AnnaBridge 171:3a7713b1edbc 365 void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
AnnaBridge 171:3a7713b1edbc 366
AnnaBridge 171:3a7713b1edbc 367 /*!
AnnaBridge 171:3a7713b1edbc 368 * @brief Initializes the SPI with slave configuration.
AnnaBridge 171:3a7713b1edbc 369 *
AnnaBridge 171:3a7713b1edbc 370 * The configuration structure can be filled by user from scratch or be set with
AnnaBridge 171:3a7713b1edbc 371 * default values by SPI_SlaveGetDefaultConfig().
AnnaBridge 171:3a7713b1edbc 372 * After calling this API, the slave is ready to transfer.
AnnaBridge 171:3a7713b1edbc 373 * Example
AnnaBridge 171:3a7713b1edbc 374 @code
AnnaBridge 171:3a7713b1edbc 375 spi_slave_config_t config = {
AnnaBridge 171:3a7713b1edbc 376 .polarity = flexSPIClockPolarity_ActiveHigh;
AnnaBridge 171:3a7713b1edbc 377 .phase = flexSPIClockPhase_FirstEdge;
AnnaBridge 171:3a7713b1edbc 378 .direction = flexSPIMsbFirst;
AnnaBridge 171:3a7713b1edbc 379 ...
AnnaBridge 171:3a7713b1edbc 380 };
AnnaBridge 171:3a7713b1edbc 381 SPI_SlaveInit(SPI0, &config);
AnnaBridge 171:3a7713b1edbc 382 @endcode
AnnaBridge 171:3a7713b1edbc 383 *
AnnaBridge 171:3a7713b1edbc 384 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 385 * @param config pointer to slave configuration structure
AnnaBridge 171:3a7713b1edbc 386 */
AnnaBridge 171:3a7713b1edbc 387 status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 /*!
AnnaBridge 171:3a7713b1edbc 390 * @brief De-initializes the SPI.
AnnaBridge 171:3a7713b1edbc 391 *
AnnaBridge 171:3a7713b1edbc 392 * Calling this API resets the SPI module, gates the SPI clock.
AnnaBridge 171:3a7713b1edbc 393 * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
AnnaBridge 171:3a7713b1edbc 394 *
AnnaBridge 171:3a7713b1edbc 395 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 396 */
AnnaBridge 171:3a7713b1edbc 397 void SPI_Deinit(SPI_Type *base);
AnnaBridge 171:3a7713b1edbc 398
AnnaBridge 171:3a7713b1edbc 399 /*!
AnnaBridge 171:3a7713b1edbc 400 * @brief Enable or disable the SPI Master or Slave
AnnaBridge 171:3a7713b1edbc 401 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 402 * @param enable or disable ( true = enable, false = disable)
AnnaBridge 171:3a7713b1edbc 403 */
AnnaBridge 171:3a7713b1edbc 404 static inline void SPI_Enable(SPI_Type *base, bool enable)
AnnaBridge 171:3a7713b1edbc 405 {
AnnaBridge 171:3a7713b1edbc 406 if (enable)
AnnaBridge 171:3a7713b1edbc 407 {
AnnaBridge 171:3a7713b1edbc 408 base->CFG |= SPI_CFG_ENABLE_MASK;
AnnaBridge 171:3a7713b1edbc 409 }
AnnaBridge 171:3a7713b1edbc 410 else
AnnaBridge 171:3a7713b1edbc 411 {
AnnaBridge 171:3a7713b1edbc 412 base->CFG &= ~SPI_CFG_ENABLE_MASK;
AnnaBridge 171:3a7713b1edbc 413 }
AnnaBridge 171:3a7713b1edbc 414 }
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 /*! @} */
AnnaBridge 171:3a7713b1edbc 417
AnnaBridge 171:3a7713b1edbc 418 /*!
AnnaBridge 171:3a7713b1edbc 419 * @name Status
AnnaBridge 171:3a7713b1edbc 420 * @{
AnnaBridge 171:3a7713b1edbc 421 */
AnnaBridge 171:3a7713b1edbc 422
AnnaBridge 171:3a7713b1edbc 423 /*!
AnnaBridge 171:3a7713b1edbc 424 * @brief Gets the status flag.
AnnaBridge 171:3a7713b1edbc 425 *
AnnaBridge 171:3a7713b1edbc 426 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 427 * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status.
AnnaBridge 171:3a7713b1edbc 428 */
AnnaBridge 171:3a7713b1edbc 429 static inline uint32_t SPI_GetStatusFlags(SPI_Type *base)
AnnaBridge 171:3a7713b1edbc 430 {
AnnaBridge 171:3a7713b1edbc 431 assert(NULL != base);
AnnaBridge 171:3a7713b1edbc 432 return base->FIFOSTAT;
AnnaBridge 171:3a7713b1edbc 433 }
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 /*! @} */
AnnaBridge 171:3a7713b1edbc 436
AnnaBridge 171:3a7713b1edbc 437 /*!
AnnaBridge 171:3a7713b1edbc 438 * @name Interrupts
AnnaBridge 171:3a7713b1edbc 439 * @{
AnnaBridge 171:3a7713b1edbc 440 */
AnnaBridge 171:3a7713b1edbc 441
AnnaBridge 171:3a7713b1edbc 442 /*!
AnnaBridge 171:3a7713b1edbc 443 * @brief Enables the interrupt for the SPI.
AnnaBridge 171:3a7713b1edbc 444 *
AnnaBridge 171:3a7713b1edbc 445 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 446 * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 447 * @arg kSPI_RxLvlIrq
AnnaBridge 171:3a7713b1edbc 448 * @arg kSPI_TxLvlIrq
AnnaBridge 171:3a7713b1edbc 449 */
AnnaBridge 171:3a7713b1edbc 450 static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs)
AnnaBridge 171:3a7713b1edbc 451 {
AnnaBridge 171:3a7713b1edbc 452 assert(NULL != base);
AnnaBridge 171:3a7713b1edbc 453 base->FIFOINTENSET = irqs;
AnnaBridge 171:3a7713b1edbc 454 }
AnnaBridge 171:3a7713b1edbc 455
AnnaBridge 171:3a7713b1edbc 456 /*!
AnnaBridge 171:3a7713b1edbc 457 * @brief Disables the interrupt for the SPI.
AnnaBridge 171:3a7713b1edbc 458 *
AnnaBridge 171:3a7713b1edbc 459 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 460 * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 461 * @arg kSPI_RxLvlIrq
AnnaBridge 171:3a7713b1edbc 462 * @arg kSPI_TxLvlIrq
AnnaBridge 171:3a7713b1edbc 463 */
AnnaBridge 171:3a7713b1edbc 464 static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs)
AnnaBridge 171:3a7713b1edbc 465 {
AnnaBridge 171:3a7713b1edbc 466 assert(NULL != base);
AnnaBridge 171:3a7713b1edbc 467 base->FIFOINTENCLR = irqs;
AnnaBridge 171:3a7713b1edbc 468 }
AnnaBridge 171:3a7713b1edbc 469
AnnaBridge 171:3a7713b1edbc 470 /*! @} */
AnnaBridge 171:3a7713b1edbc 471
AnnaBridge 171:3a7713b1edbc 472 /*!
AnnaBridge 171:3a7713b1edbc 473 * @name DMA Control
AnnaBridge 171:3a7713b1edbc 474 * @{
AnnaBridge 171:3a7713b1edbc 475 */
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 /*!
AnnaBridge 171:3a7713b1edbc 478 * @brief Enables the DMA request from SPI txFIFO.
AnnaBridge 171:3a7713b1edbc 479 *
AnnaBridge 171:3a7713b1edbc 480 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 481 * @param enable True means enable DMA, false means disable DMA
AnnaBridge 171:3a7713b1edbc 482 */
AnnaBridge 171:3a7713b1edbc 483 void SPI_EnableTxDMA(SPI_Type *base, bool enable);
AnnaBridge 171:3a7713b1edbc 484
AnnaBridge 171:3a7713b1edbc 485 /*!
AnnaBridge 171:3a7713b1edbc 486 * @brief Enables the DMA request from SPI rxFIFO.
AnnaBridge 171:3a7713b1edbc 487 *
AnnaBridge 171:3a7713b1edbc 488 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 489 * @param enable True means enable DMA, false means disable DMA
AnnaBridge 171:3a7713b1edbc 490 */
AnnaBridge 171:3a7713b1edbc 491 void SPI_EnableRxDMA(SPI_Type *base, bool enable);
AnnaBridge 171:3a7713b1edbc 492
AnnaBridge 171:3a7713b1edbc 493 /*! @} */
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 /*!
AnnaBridge 171:3a7713b1edbc 496 * @name Bus Operations
AnnaBridge 171:3a7713b1edbc 497 * @{
AnnaBridge 171:3a7713b1edbc 498 */
AnnaBridge 171:3a7713b1edbc 499
AnnaBridge 171:3a7713b1edbc 500 /*!
AnnaBridge 171:3a7713b1edbc 501 * @brief Sets the baud rate for SPI transfer. This is only used in master.
AnnaBridge 171:3a7713b1edbc 502 *
AnnaBridge 171:3a7713b1edbc 503 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 504 * @param baudrate_Bps baud rate needed in Hz.
AnnaBridge 171:3a7713b1edbc 505 * @param srcClock_Hz SPI source clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 506 */
AnnaBridge 171:3a7713b1edbc 507 status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
AnnaBridge 171:3a7713b1edbc 508
AnnaBridge 171:3a7713b1edbc 509 /*!
AnnaBridge 171:3a7713b1edbc 510 * @brief Writes a data into the SPI data register.
AnnaBridge 171:3a7713b1edbc 511 *
AnnaBridge 171:3a7713b1edbc 512 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 513 * @param data needs to be write.
AnnaBridge 171:3a7713b1edbc 514 * @param configFlags transfer configuration options @ref spi_xfer_option_t
AnnaBridge 171:3a7713b1edbc 515 */
AnnaBridge 171:3a7713b1edbc 516 void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags);
AnnaBridge 171:3a7713b1edbc 517
AnnaBridge 171:3a7713b1edbc 518 /*!
AnnaBridge 171:3a7713b1edbc 519 * @brief Gets a data from the SPI data register.
AnnaBridge 171:3a7713b1edbc 520 *
AnnaBridge 171:3a7713b1edbc 521 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 522 * @return Data in the register.
AnnaBridge 171:3a7713b1edbc 523 */
AnnaBridge 171:3a7713b1edbc 524 static inline uint32_t SPI_ReadData(SPI_Type *base)
AnnaBridge 171:3a7713b1edbc 525 {
AnnaBridge 171:3a7713b1edbc 526 assert(NULL != base);
AnnaBridge 171:3a7713b1edbc 527 return base->FIFORD;
AnnaBridge 171:3a7713b1edbc 528 }
AnnaBridge 171:3a7713b1edbc 529
AnnaBridge 171:3a7713b1edbc 530 /*!
AnnaBridge 171:3a7713b1edbc 531 * @brief Set delay time for transfer.
AnnaBridge 171:3a7713b1edbc 532 * the delay uint is SPI clock time, maximum value is 0xF.
AnnaBridge 171:3a7713b1edbc 533 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 534 * @param config configuration for delay option @ref spi_delay_config_t.
AnnaBridge 171:3a7713b1edbc 535 */
AnnaBridge 171:3a7713b1edbc 536 static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config)
AnnaBridge 171:3a7713b1edbc 537 {
AnnaBridge 171:3a7713b1edbc 538 assert(NULL != base);
AnnaBridge 171:3a7713b1edbc 539 assert(NULL != config);
AnnaBridge 171:3a7713b1edbc 540 base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) |
AnnaBridge 171:3a7713b1edbc 541 SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay));
AnnaBridge 171:3a7713b1edbc 542 }
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 /*!
AnnaBridge 171:3a7713b1edbc 545 * @brief Set up the dummy data.
AnnaBridge 171:3a7713b1edbc 546 *
AnnaBridge 171:3a7713b1edbc 547 * @param base SPI peripheral address.
AnnaBridge 171:3a7713b1edbc 548 * @param dummyData Data to be transferred when tx buffer is NULL.
AnnaBridge 171:3a7713b1edbc 549 */
AnnaBridge 171:3a7713b1edbc 550 void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData);
AnnaBridge 171:3a7713b1edbc 551
AnnaBridge 171:3a7713b1edbc 552 /*! @} */
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 /*!
AnnaBridge 171:3a7713b1edbc 555 * @name Transactional
AnnaBridge 171:3a7713b1edbc 556 * @{
AnnaBridge 171:3a7713b1edbc 557 */
AnnaBridge 171:3a7713b1edbc 558
AnnaBridge 171:3a7713b1edbc 559 /*!
AnnaBridge 171:3a7713b1edbc 560 * @brief Initializes the SPI master handle.
AnnaBridge 171:3a7713b1edbc 561 *
AnnaBridge 171:3a7713b1edbc 562 * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
AnnaBridge 171:3a7713b1edbc 563 * for a specified SPI instance, call this API once to get the initialized handle.
AnnaBridge 171:3a7713b1edbc 564 *
AnnaBridge 171:3a7713b1edbc 565 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 566 * @param handle SPI handle pointer.
AnnaBridge 171:3a7713b1edbc 567 * @param callback Callback function.
AnnaBridge 171:3a7713b1edbc 568 * @param userData User data.
AnnaBridge 171:3a7713b1edbc 569 */
AnnaBridge 171:3a7713b1edbc 570 status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
AnnaBridge 171:3a7713b1edbc 571 spi_master_handle_t *handle,
AnnaBridge 171:3a7713b1edbc 572 spi_master_callback_t callback,
AnnaBridge 171:3a7713b1edbc 573 void *userData);
AnnaBridge 171:3a7713b1edbc 574
AnnaBridge 171:3a7713b1edbc 575 /*!
AnnaBridge 171:3a7713b1edbc 576 * @brief Transfers a block of data using a polling method.
AnnaBridge 171:3a7713b1edbc 577 *
AnnaBridge 171:3a7713b1edbc 578 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 579 * @param xfer pointer to spi_xfer_config_t structure
AnnaBridge 171:3a7713b1edbc 580 * @retval kStatus_Success Successfully start a transfer.
AnnaBridge 171:3a7713b1edbc 581 * @retval kStatus_InvalidArgument Input argument is invalid.
AnnaBridge 171:3a7713b1edbc 582 */
AnnaBridge 171:3a7713b1edbc 583 status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 /*!
AnnaBridge 171:3a7713b1edbc 586 * @brief Performs a non-blocking SPI interrupt transfer.
AnnaBridge 171:3a7713b1edbc 587 *
AnnaBridge 171:3a7713b1edbc 588 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 589 * @param handle pointer to spi_master_handle_t structure which stores the transfer state
AnnaBridge 171:3a7713b1edbc 590 * @param xfer pointer to spi_xfer_config_t structure
AnnaBridge 171:3a7713b1edbc 591 * @retval kStatus_Success Successfully start a transfer.
AnnaBridge 171:3a7713b1edbc 592 * @retval kStatus_InvalidArgument Input argument is invalid.
AnnaBridge 171:3a7713b1edbc 593 * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
AnnaBridge 171:3a7713b1edbc 594 */
AnnaBridge 171:3a7713b1edbc 595 status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 /*!
AnnaBridge 171:3a7713b1edbc 598 * @brief Transfers a block of data using a polling method.
AnnaBridge 171:3a7713b1edbc 599 *
AnnaBridge 171:3a7713b1edbc 600 * This function will do a half-duplex transfer for SPI master, This is a blocking function,
AnnaBridge 171:3a7713b1edbc 601 * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex,
AnnaBridge 171:3a7713b1edbc 602 * users can set transmit first or receive first.
AnnaBridge 171:3a7713b1edbc 603 *
AnnaBridge 171:3a7713b1edbc 604 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 605 * @param xfer pointer to spi_half_duplex_transfer_t structure
AnnaBridge 171:3a7713b1edbc 606 * @return status of status_t.
AnnaBridge 171:3a7713b1edbc 607 */
AnnaBridge 171:3a7713b1edbc 608 status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer);
AnnaBridge 171:3a7713b1edbc 609
AnnaBridge 171:3a7713b1edbc 610 /*!
AnnaBridge 171:3a7713b1edbc 611 * @brief Performs a non-blocking SPI interrupt transfer.
AnnaBridge 171:3a7713b1edbc 612 *
AnnaBridge 171:3a7713b1edbc 613 * This function using polling way to do the first half transimission and using interrupts to
AnnaBridge 171:3a7713b1edbc 614 * do the second half transimission, the transfer mechanism is half-duplex.
AnnaBridge 171:3a7713b1edbc 615 * When do the second half transimission, code will return right away. When all data is transferred,
AnnaBridge 171:3a7713b1edbc 616 * the callback function is called.
AnnaBridge 171:3a7713b1edbc 617 *
AnnaBridge 171:3a7713b1edbc 618 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 619 * @param handle pointer to spi_master_handle_t structure which stores the transfer state
AnnaBridge 171:3a7713b1edbc 620 * @param xfer pointer to spi_half_duplex_transfer_t structure
AnnaBridge 171:3a7713b1edbc 621 * @return status of status_t.
AnnaBridge 171:3a7713b1edbc 622 */
AnnaBridge 171:3a7713b1edbc 623 status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base,
AnnaBridge 171:3a7713b1edbc 624 spi_master_handle_t *handle,
AnnaBridge 171:3a7713b1edbc 625 spi_half_duplex_transfer_t *xfer);
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 /*!
AnnaBridge 171:3a7713b1edbc 628 * @brief Gets the master transfer count.
AnnaBridge 171:3a7713b1edbc 629 *
AnnaBridge 171:3a7713b1edbc 630 * This function gets the master transfer count.
AnnaBridge 171:3a7713b1edbc 631 *
AnnaBridge 171:3a7713b1edbc 632 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 633 * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
AnnaBridge 171:3a7713b1edbc 634 * @param count The number of bytes transferred by using the non-blocking transaction.
AnnaBridge 171:3a7713b1edbc 635 * @return status of status_t.
AnnaBridge 171:3a7713b1edbc 636 */
AnnaBridge 171:3a7713b1edbc 637 status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
AnnaBridge 171:3a7713b1edbc 638
AnnaBridge 171:3a7713b1edbc 639 /*!
AnnaBridge 171:3a7713b1edbc 640 * @brief SPI master aborts a transfer using an interrupt.
AnnaBridge 171:3a7713b1edbc 641 *
AnnaBridge 171:3a7713b1edbc 642 * This function aborts a transfer using an interrupt.
AnnaBridge 171:3a7713b1edbc 643 *
AnnaBridge 171:3a7713b1edbc 644 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 645 * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
AnnaBridge 171:3a7713b1edbc 646 */
AnnaBridge 171:3a7713b1edbc 647 void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 /*!
AnnaBridge 171:3a7713b1edbc 650 * @brief Interrupts the handler for the SPI.
AnnaBridge 171:3a7713b1edbc 651 *
AnnaBridge 171:3a7713b1edbc 652 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 653 * @param handle pointer to spi_master_handle_t structure which stores the transfer state.
AnnaBridge 171:3a7713b1edbc 654 */
AnnaBridge 171:3a7713b1edbc 655 void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
AnnaBridge 171:3a7713b1edbc 656
AnnaBridge 171:3a7713b1edbc 657 /*!
AnnaBridge 171:3a7713b1edbc 658 * @brief Initializes the SPI slave handle.
AnnaBridge 171:3a7713b1edbc 659 *
AnnaBridge 171:3a7713b1edbc 660 * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
AnnaBridge 171:3a7713b1edbc 661 * for a specified SPI instance, call this API once to get the initialized handle.
AnnaBridge 171:3a7713b1edbc 662 *
AnnaBridge 171:3a7713b1edbc 663 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 664 * @param handle SPI handle pointer.
AnnaBridge 171:3a7713b1edbc 665 * @param callback Callback function.
AnnaBridge 171:3a7713b1edbc 666 * @param userData User data.
AnnaBridge 171:3a7713b1edbc 667 */
AnnaBridge 171:3a7713b1edbc 668 static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base,
AnnaBridge 171:3a7713b1edbc 669 spi_slave_handle_t *handle,
AnnaBridge 171:3a7713b1edbc 670 spi_slave_callback_t callback,
AnnaBridge 171:3a7713b1edbc 671 void *userData)
AnnaBridge 171:3a7713b1edbc 672 {
AnnaBridge 171:3a7713b1edbc 673 return SPI_MasterTransferCreateHandle(base, handle, callback, userData);
AnnaBridge 171:3a7713b1edbc 674 }
AnnaBridge 171:3a7713b1edbc 675
AnnaBridge 171:3a7713b1edbc 676 /*!
AnnaBridge 171:3a7713b1edbc 677 * @brief Performs a non-blocking SPI slave interrupt transfer.
AnnaBridge 171:3a7713b1edbc 678 *
AnnaBridge 171:3a7713b1edbc 679 * @note The API returns immediately after the transfer initialization is finished.
AnnaBridge 171:3a7713b1edbc 680 *
AnnaBridge 171:3a7713b1edbc 681 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 682 * @param handle pointer to spi_master_handle_t structure which stores the transfer state
AnnaBridge 171:3a7713b1edbc 683 * @param xfer pointer to spi_xfer_config_t structure
AnnaBridge 171:3a7713b1edbc 684 * @retval kStatus_Success Successfully start a transfer.
AnnaBridge 171:3a7713b1edbc 685 * @retval kStatus_InvalidArgument Input argument is invalid.
AnnaBridge 171:3a7713b1edbc 686 * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
AnnaBridge 171:3a7713b1edbc 687 */
AnnaBridge 171:3a7713b1edbc 688 static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
AnnaBridge 171:3a7713b1edbc 689 {
AnnaBridge 171:3a7713b1edbc 690 return SPI_MasterTransferNonBlocking(base, handle, xfer);
AnnaBridge 171:3a7713b1edbc 691 }
AnnaBridge 171:3a7713b1edbc 692
AnnaBridge 171:3a7713b1edbc 693 /*!
AnnaBridge 171:3a7713b1edbc 694 * @brief Gets the slave transfer count.
AnnaBridge 171:3a7713b1edbc 695 *
AnnaBridge 171:3a7713b1edbc 696 * This function gets the slave transfer count.
AnnaBridge 171:3a7713b1edbc 697 *
AnnaBridge 171:3a7713b1edbc 698 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 699 * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
AnnaBridge 171:3a7713b1edbc 700 * @param count The number of bytes transferred by using the non-blocking transaction.
AnnaBridge 171:3a7713b1edbc 701 * @return status of status_t.
AnnaBridge 171:3a7713b1edbc 702 */
AnnaBridge 171:3a7713b1edbc 703 static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
AnnaBridge 171:3a7713b1edbc 704 {
AnnaBridge 171:3a7713b1edbc 705 return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count);
AnnaBridge 171:3a7713b1edbc 706 }
AnnaBridge 171:3a7713b1edbc 707
AnnaBridge 171:3a7713b1edbc 708 /*!
AnnaBridge 171:3a7713b1edbc 709 * @brief SPI slave aborts a transfer using an interrupt.
AnnaBridge 171:3a7713b1edbc 710 *
AnnaBridge 171:3a7713b1edbc 711 * This function aborts a transfer using an interrupt.
AnnaBridge 171:3a7713b1edbc 712 *
AnnaBridge 171:3a7713b1edbc 713 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 714 * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state.
AnnaBridge 171:3a7713b1edbc 715 */
AnnaBridge 171:3a7713b1edbc 716 static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
AnnaBridge 171:3a7713b1edbc 717 {
AnnaBridge 171:3a7713b1edbc 718 SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle);
AnnaBridge 171:3a7713b1edbc 719 }
AnnaBridge 171:3a7713b1edbc 720
AnnaBridge 171:3a7713b1edbc 721 /*!
AnnaBridge 171:3a7713b1edbc 722 * @brief Interrupts a handler for the SPI slave.
AnnaBridge 171:3a7713b1edbc 723 *
AnnaBridge 171:3a7713b1edbc 724 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 725 * @param handle pointer to spi_slave_handle_t structure which stores the transfer state
AnnaBridge 171:3a7713b1edbc 726 */
AnnaBridge 171:3a7713b1edbc 727 static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle)
AnnaBridge 171:3a7713b1edbc 728 {
AnnaBridge 171:3a7713b1edbc 729 SPI_MasterTransferHandleIRQ(base, handle);
AnnaBridge 171:3a7713b1edbc 730 }
AnnaBridge 171:3a7713b1edbc 731
AnnaBridge 171:3a7713b1edbc 732 /*! @} */
AnnaBridge 171:3a7713b1edbc 733
AnnaBridge 171:3a7713b1edbc 734 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 735 }
AnnaBridge 171:3a7713b1edbc 736 #endif
AnnaBridge 171:3a7713b1edbc 737
AnnaBridge 171:3a7713b1edbc 738 /*! @} */
AnnaBridge 171:3a7713b1edbc 739
AnnaBridge 171:3a7713b1edbc 740 #endif /* _FSL_SPI_H_*/