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TARGET_LPC546XX/TOOLCHAIN_ARM_STD/LPC54628_features.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_FF_LPC546XX/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54628_features.h@163:e59c8e839560
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 163:e59c8e839560 | 1 | /* |
| AnnaBridge | 163:e59c8e839560 | 2 | ** ################################################################### |
| AnnaBridge | 163:e59c8e839560 | 3 | ** Version: rev. 1.2, 2017-06-08 |
| AnnaBridge | 163:e59c8e839560 | 4 | ** Build: b170609 |
| AnnaBridge | 163:e59c8e839560 | 5 | ** |
| AnnaBridge | 163:e59c8e839560 | 6 | ** Abstract: |
| AnnaBridge | 163:e59c8e839560 | 7 | ** Chip specific module features. |
| AnnaBridge | 163:e59c8e839560 | 8 | ** |
| AnnaBridge | 163:e59c8e839560 | 9 | ** Copyright 2016 Freescale Semiconductor, Inc. |
| AnnaBridge | 163:e59c8e839560 | 10 | ** Copyright 2016-2017 NXP |
| AnnaBridge | 163:e59c8e839560 | 11 | ** Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 163:e59c8e839560 | 12 | ** are permitted provided that the following conditions are met: |
| AnnaBridge | 163:e59c8e839560 | 13 | ** |
| AnnaBridge | 163:e59c8e839560 | 14 | ** 1. Redistributions of source code must retain the above copyright notice, this list |
| AnnaBridge | 163:e59c8e839560 | 15 | ** of conditions and the following disclaimer. |
| AnnaBridge | 163:e59c8e839560 | 16 | ** |
| AnnaBridge | 163:e59c8e839560 | 17 | ** 2. Redistributions in binary form must reproduce the above copyright notice, this |
| AnnaBridge | 163:e59c8e839560 | 18 | ** list of conditions and the following disclaimer in the documentation and/or |
| AnnaBridge | 163:e59c8e839560 | 19 | ** other materials provided with the distribution. |
| AnnaBridge | 163:e59c8e839560 | 20 | ** |
| AnnaBridge | 163:e59c8e839560 | 21 | ** 3. Neither the name of the copyright holder nor the names of its |
| AnnaBridge | 163:e59c8e839560 | 22 | ** contributors may be used to endorse or promote products derived from this |
| AnnaBridge | 163:e59c8e839560 | 23 | ** software without specific prior written permission. |
| AnnaBridge | 163:e59c8e839560 | 24 | ** |
| AnnaBridge | 163:e59c8e839560 | 25 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| AnnaBridge | 163:e59c8e839560 | 26 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| AnnaBridge | 163:e59c8e839560 | 27 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 163:e59c8e839560 | 28 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| AnnaBridge | 163:e59c8e839560 | 29 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| AnnaBridge | 163:e59c8e839560 | 30 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| AnnaBridge | 163:e59c8e839560 | 31 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| AnnaBridge | 163:e59c8e839560 | 32 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| AnnaBridge | 163:e59c8e839560 | 33 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| AnnaBridge | 163:e59c8e839560 | 34 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 163:e59c8e839560 | 35 | ** |
| AnnaBridge | 163:e59c8e839560 | 36 | ** http: www.nxp.com |
| AnnaBridge | 163:e59c8e839560 | 37 | ** mail: support@nxp.com |
| AnnaBridge | 163:e59c8e839560 | 38 | ** |
| AnnaBridge | 163:e59c8e839560 | 39 | ** Revisions: |
| AnnaBridge | 163:e59c8e839560 | 40 | ** - rev. 1.0 (2016-08-12) |
| AnnaBridge | 163:e59c8e839560 | 41 | ** Initial version. |
| AnnaBridge | 163:e59c8e839560 | 42 | ** - rev. 1.1 (2016-11-25) |
| AnnaBridge | 163:e59c8e839560 | 43 | ** Update CANFD and Classic CAN register. |
| AnnaBridge | 163:e59c8e839560 | 44 | ** Add MAC TIMERSTAMP registers. |
| AnnaBridge | 163:e59c8e839560 | 45 | ** - rev. 1.2 (2017-06-08) |
| AnnaBridge | 163:e59c8e839560 | 46 | ** Remove RTC_CTRL_RTC_OSC_BYPASS. |
| AnnaBridge | 163:e59c8e839560 | 47 | ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. |
| AnnaBridge | 163:e59c8e839560 | 48 | ** Remove RESET and HALT from SYSCON_AHBCLKDIV. |
| AnnaBridge | 163:e59c8e839560 | 49 | ** |
| AnnaBridge | 163:e59c8e839560 | 50 | ** ################################################################### |
| AnnaBridge | 163:e59c8e839560 | 51 | */ |
| AnnaBridge | 163:e59c8e839560 | 52 | |
| AnnaBridge | 163:e59c8e839560 | 53 | #ifndef _LPC54628_FEATURES_H_ |
| AnnaBridge | 163:e59c8e839560 | 54 | #define _LPC54628_FEATURES_H_ |
| AnnaBridge | 163:e59c8e839560 | 55 | |
| AnnaBridge | 163:e59c8e839560 | 56 | /* SOC module features */ |
| AnnaBridge | 163:e59c8e839560 | 57 | |
| AnnaBridge | 163:e59c8e839560 | 58 | /* @brief ACMP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 59 | #define FSL_FEATURE_SOC_ACMP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 60 | /* @brief ADC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 61 | #define FSL_FEATURE_SOC_ADC_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 62 | /* @brief ADC12 availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 63 | #define FSL_FEATURE_SOC_ADC12_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 64 | /* @brief ADC16 availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 65 | #define FSL_FEATURE_SOC_ADC16_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 66 | /* @brief ADC_5HC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 67 | #define FSL_FEATURE_SOC_ADC_5HC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 68 | /* @brief AES availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 69 | #define FSL_FEATURE_SOC_AES_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 70 | /* @brief AFE availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 71 | #define FSL_FEATURE_SOC_AFE_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 72 | /* @brief AGC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 73 | #define FSL_FEATURE_SOC_AGC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 74 | /* @brief AIPS availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 75 | #define FSL_FEATURE_SOC_AIPS_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 76 | /* @brief AIPSTZ availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 77 | #define FSL_FEATURE_SOC_AIPSTZ_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 78 | /* @brief ANATOP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 79 | #define FSL_FEATURE_SOC_ANATOP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 80 | /* @brief AOI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 81 | #define FSL_FEATURE_SOC_AOI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 82 | /* @brief APBH availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 83 | #define FSL_FEATURE_SOC_APBH_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 84 | /* @brief ASMC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 85 | #define FSL_FEATURE_SOC_ASMC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 86 | /* @brief ASRC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 87 | #define FSL_FEATURE_SOC_ASRC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 88 | /* @brief ASYNC_SYSCON availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 89 | #define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 90 | /* @brief ATX availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 91 | #define FSL_FEATURE_SOC_ATX_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 92 | /* @brief AXBS availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 93 | #define FSL_FEATURE_SOC_AXBS_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 94 | /* @brief BCH availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 95 | #define FSL_FEATURE_SOC_BCH_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 96 | /* @brief BLEDP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 97 | #define FSL_FEATURE_SOC_BLEDP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 98 | /* @brief BOD availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 99 | #define FSL_FEATURE_SOC_BOD_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 100 | /* @brief CAAM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 101 | #define FSL_FEATURE_SOC_CAAM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 102 | /* @brief CADC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 103 | #define FSL_FEATURE_SOC_CADC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 104 | /* @brief CALIB availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 105 | #define FSL_FEATURE_SOC_CALIB_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 106 | /* @brief CAN availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 107 | #define FSL_FEATURE_SOC_LPC_CAN_COUNT (2) |
| AnnaBridge | 163:e59c8e839560 | 108 | /* @brief CAU availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 109 | #define FSL_FEATURE_SOC_CAU_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 110 | /* @brief CAU3 availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 111 | #define FSL_FEATURE_SOC_CAU3_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 112 | /* @brief CCM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 113 | #define FSL_FEATURE_SOC_CCM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 114 | /* @brief CCM_ANALOG availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 115 | #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 116 | /* @brief CHRG availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 117 | #define FSL_FEATURE_SOC_CHRG_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 118 | /* @brief CMP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 119 | #define FSL_FEATURE_SOC_CMP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 120 | /* @brief CMT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 121 | #define FSL_FEATURE_SOC_CMT_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 122 | /* @brief CNC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 123 | #define FSL_FEATURE_SOC_CNC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 124 | /* @brief COP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 125 | #define FSL_FEATURE_SOC_COP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 126 | /* @brief CRC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 127 | #define FSL_FEATURE_SOC_CRC_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 128 | /* @brief CS availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 129 | #define FSL_FEATURE_SOC_CS_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 130 | /* @brief CSI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 131 | #define FSL_FEATURE_SOC_CSI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 132 | /* @brief CT32B availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 133 | #define FSL_FEATURE_SOC_CT32B_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 134 | /* @brief CTI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 135 | #define FSL_FEATURE_SOC_CTI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 136 | /* @brief CTIMER availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 137 | #define FSL_FEATURE_SOC_CTIMER_COUNT (5) |
| AnnaBridge | 163:e59c8e839560 | 138 | /* @brief DAC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 139 | #define FSL_FEATURE_SOC_DAC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 140 | /* @brief DAC32 availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 141 | #define FSL_FEATURE_SOC_DAC32_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 142 | /* @brief DCDC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 143 | #define FSL_FEATURE_SOC_DCDC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 144 | /* @brief DCP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 145 | #define FSL_FEATURE_SOC_DCP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 146 | /* @brief DDR availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 147 | #define FSL_FEATURE_SOC_DDR_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 148 | /* @brief DDRC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 149 | #define FSL_FEATURE_SOC_DDRC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 150 | /* @brief DDRC_MP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 151 | #define FSL_FEATURE_SOC_DDRC_MP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 152 | /* @brief DDR_PHY availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 153 | #define FSL_FEATURE_SOC_DDR_PHY_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 154 | /* @brief DMA availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 155 | #define FSL_FEATURE_SOC_DMA_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 156 | /* @brief DMAMUX availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 157 | #define FSL_FEATURE_SOC_DMAMUX_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 158 | /* @brief DMIC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 159 | #define FSL_FEATURE_SOC_DMIC_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 160 | /* @brief DRY availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 161 | #define FSL_FEATURE_SOC_DRY_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 162 | /* @brief DSPI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 163 | #define FSL_FEATURE_SOC_DSPI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 164 | /* @brief ECSPI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 165 | #define FSL_FEATURE_SOC_ECSPI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 166 | /* @brief EDMA availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 167 | #define FSL_FEATURE_SOC_EDMA_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 168 | /* @brief EEPROM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 169 | #define FSL_FEATURE_SOC_EEPROM_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 170 | /* @brief EIM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 171 | #define FSL_FEATURE_SOC_EIM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 172 | /* @brief EMC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 173 | #define FSL_FEATURE_SOC_EMC_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 174 | /* @brief EMVSIM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 175 | #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 176 | /* @brief ENC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 177 | #define FSL_FEATURE_SOC_ENC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 178 | /* @brief ENET availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 179 | #define FSL_FEATURE_SOC_LPC_ENET_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 180 | /* @brief EPDC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 181 | #define FSL_FEATURE_SOC_EPDC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 182 | /* @brief EPIT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 183 | #define FSL_FEATURE_SOC_EPIT_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 184 | /* @brief ESAI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 185 | #define FSL_FEATURE_SOC_ESAI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 186 | /* @brief EWM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 187 | #define FSL_FEATURE_SOC_EWM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 188 | /* @brief FB availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 189 | #define FSL_FEATURE_SOC_FB_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 190 | /* @brief FGPIO availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 191 | #define FSL_FEATURE_SOC_FGPIO_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 192 | /* @brief FLASH availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 193 | #define FSL_FEATURE_SOC_FLASH_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 194 | /* @brief FLEXCAN availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 195 | #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 196 | /* @brief FLEXCOMM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 197 | #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10) |
| AnnaBridge | 163:e59c8e839560 | 198 | /* @brief FLEXIO availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 199 | #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 200 | /* @brief FLEXRAM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 201 | #define FSL_FEATURE_SOC_FLEXRAM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 202 | /* @brief FLEXSPI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 203 | #define FSL_FEATURE_SOC_FLEXSPI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 204 | /* @brief FMC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 205 | #define FSL_FEATURE_SOC_FMC_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 206 | /* @brief FSKDT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 207 | #define FSL_FEATURE_SOC_FSKDT_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 208 | /* @brief FSP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 209 | #define FSL_FEATURE_SOC_FSP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 210 | /* @brief FTFA availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 211 | #define FSL_FEATURE_SOC_FTFA_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 212 | /* @brief FTFE availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 213 | #define FSL_FEATURE_SOC_FTFE_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 214 | /* @brief FTFL availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 215 | #define FSL_FEATURE_SOC_FTFL_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 216 | /* @brief FTM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 217 | #define FSL_FEATURE_SOC_FTM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 218 | /* @brief FTMRA availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 219 | #define FSL_FEATURE_SOC_FTMRA_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 220 | /* @brief FTMRE availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 221 | #define FSL_FEATURE_SOC_FTMRE_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 222 | /* @brief FTMRH availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 223 | #define FSL_FEATURE_SOC_FTMRH_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 224 | /* @brief GINT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 225 | #define FSL_FEATURE_SOC_GINT_COUNT (2) |
| AnnaBridge | 163:e59c8e839560 | 226 | /* @brief GPC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 227 | #define FSL_FEATURE_SOC_GPC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 228 | /* @brief GPC_PGC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 229 | #define FSL_FEATURE_SOC_GPC_PGC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 230 | /* @brief GPIO availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 231 | #define FSL_FEATURE_SOC_GPIO_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 232 | /* @brief GPMI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 233 | #define FSL_FEATURE_SOC_GPMI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 234 | /* @brief GPT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 235 | #define FSL_FEATURE_SOC_GPT_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 236 | /* @brief HSADC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 237 | #define FSL_FEATURE_SOC_HSADC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 238 | /* @brief I2C availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 239 | #define FSL_FEATURE_SOC_I2C_COUNT (10) |
| AnnaBridge | 163:e59c8e839560 | 240 | /* @brief I2S availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 241 | #define FSL_FEATURE_SOC_I2S_COUNT (2) |
| AnnaBridge | 163:e59c8e839560 | 242 | /* @brief ICS availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 243 | #define FSL_FEATURE_SOC_ICS_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 244 | /* @brief IEE availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 245 | #define FSL_FEATURE_SOC_IEE_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 246 | /* @brief IEER availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 247 | #define FSL_FEATURE_SOC_IEER_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 248 | /* @brief IGPIO availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 249 | #define FSL_FEATURE_SOC_IGPIO_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 250 | /* @brief II2C availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 251 | #define FSL_FEATURE_SOC_II2C_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 252 | /* @brief INPUTMUX availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 253 | #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 254 | /* @brief INTMUX availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 255 | #define FSL_FEATURE_SOC_INTMUX_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 256 | /* @brief IOCON availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 257 | #define FSL_FEATURE_SOC_IOCON_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 258 | /* @brief IOMUXC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 259 | #define FSL_FEATURE_SOC_IOMUXC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 260 | /* @brief IOMUXC_GPR availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 261 | #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 262 | /* @brief IOMUXC_LPSR availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 263 | #define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 264 | /* @brief IOMUXC_LPSR_GPR availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 265 | #define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 266 | /* @brief IOMUXC_SNVS availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 267 | #define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 268 | /* @brief IPWM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 269 | #define FSL_FEATURE_SOC_IPWM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 270 | /* @brief IRQ availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 271 | #define FSL_FEATURE_SOC_IRQ_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 272 | /* @brief IUART availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 273 | #define FSL_FEATURE_SOC_IUART_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 274 | /* @brief KBI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 275 | #define FSL_FEATURE_SOC_KBI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 276 | /* @brief KPP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 277 | #define FSL_FEATURE_SOC_KPP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 278 | /* @brief L2CACHEC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 279 | #define FSL_FEATURE_SOC_L2CACHEC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 280 | /* @brief LCD availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 281 | #define FSL_FEATURE_SOC_LCD_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 282 | /* @brief LCDC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 283 | #define FSL_FEATURE_SOC_LCDC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 284 | /* @brief LCDIF availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 285 | #define FSL_FEATURE_SOC_LCDIF_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 286 | /* @brief LDO availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 287 | #define FSL_FEATURE_SOC_LDO_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 288 | /* @brief LLWU availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 289 | #define FSL_FEATURE_SOC_LLWU_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 290 | /* @brief LMEM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 291 | #define FSL_FEATURE_SOC_LMEM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 292 | /* @brief LPADC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 293 | #define FSL_FEATURE_SOC_LPADC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 294 | /* @brief LPCMP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 295 | #define FSL_FEATURE_SOC_LPCMP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 296 | /* @brief LPDAC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 297 | #define FSL_FEATURE_SOC_LPDAC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 298 | /* @brief LPI2C availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 299 | #define FSL_FEATURE_SOC_LPI2C_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 300 | /* @brief LPIT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 301 | #define FSL_FEATURE_SOC_LPIT_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 302 | /* @brief LPSCI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 303 | #define FSL_FEATURE_SOC_LPSCI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 304 | /* @brief LPSPI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 305 | #define FSL_FEATURE_SOC_LPSPI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 306 | /* @brief LPTMR availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 307 | #define FSL_FEATURE_SOC_LPTMR_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 308 | /* @brief LPTPM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 309 | #define FSL_FEATURE_SOC_LPTPM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 310 | /* @brief LPUART availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 311 | #define FSL_FEATURE_SOC_LPUART_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 312 | /* @brief LTC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 313 | #define FSL_FEATURE_SOC_LTC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 314 | /* @brief MAILBOX availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 315 | #define FSL_FEATURE_SOC_MAILBOX_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 316 | /* @brief MC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 317 | #define FSL_FEATURE_SOC_MC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 318 | /* @brief MCG availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 319 | #define FSL_FEATURE_SOC_MCG_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 320 | /* @brief MCGLITE availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 321 | #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 322 | /* @brief MCM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 323 | #define FSL_FEATURE_SOC_MCM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 324 | /* @brief MIPI_CSI2 availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 325 | #define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 326 | /* @brief MIPI_DSI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 327 | #define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 328 | /* @brief MIPI_DSI_HOST availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 329 | #define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 330 | /* @brief MMAU availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 331 | #define FSL_FEATURE_SOC_MMAU_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 332 | /* @brief MMCAU availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 333 | #define FSL_FEATURE_SOC_MMCAU_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 334 | /* @brief MMDC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 335 | #define FSL_FEATURE_SOC_MMDC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 336 | /* @brief MMDVSQ availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 337 | #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 338 | /* @brief MPU availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 339 | #define FSL_FEATURE_SOC_MPU_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 340 | /* @brief MRT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 341 | #define FSL_FEATURE_SOC_MRT_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 342 | /* @brief MSCAN availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 343 | #define FSL_FEATURE_SOC_MSCAN_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 344 | /* @brief MSCM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 345 | #define FSL_FEATURE_SOC_MSCM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 346 | /* @brief MTB availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 347 | #define FSL_FEATURE_SOC_MTB_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 348 | /* @brief MTBDWT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 349 | #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 350 | /* @brief MU availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 351 | #define FSL_FEATURE_SOC_MU_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 352 | /* @brief NFC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 353 | #define FSL_FEATURE_SOC_NFC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 354 | /* @brief OCOTP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 355 | #define FSL_FEATURE_SOC_OCOTP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 356 | /* @brief OPAMP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 357 | #define FSL_FEATURE_SOC_OPAMP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 358 | /* @brief OSC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 359 | #define FSL_FEATURE_SOC_OSC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 360 | /* @brief OSC32 availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 361 | #define FSL_FEATURE_SOC_OSC32_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 362 | /* @brief OTFAD availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 363 | #define FSL_FEATURE_SOC_OTFAD_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 364 | /* @brief PCC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 365 | #define FSL_FEATURE_SOC_PCC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 366 | /* @brief PCIE_PHY_CMN availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 367 | #define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 368 | /* @brief PCIE_PHY_TRSV availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 369 | #define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 370 | /* @brief PDB availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 371 | #define FSL_FEATURE_SOC_PDB_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 372 | /* @brief PGA availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 373 | #define FSL_FEATURE_SOC_PGA_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 374 | /* @brief PINT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 375 | #define FSL_FEATURE_SOC_PINT_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 376 | /* @brief PIT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 377 | #define FSL_FEATURE_SOC_PIT_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 378 | /* @brief PMC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 379 | #define FSL_FEATURE_SOC_PMC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 380 | /* @brief PMU availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 381 | #define FSL_FEATURE_SOC_PMU_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 382 | /* @brief PORT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 383 | #define FSL_FEATURE_SOC_PORT_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 384 | /* @brief PROP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 385 | #define FSL_FEATURE_SOC_PROP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 386 | /* @brief PWM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 387 | #define FSL_FEATURE_SOC_PWM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 388 | /* @brief PWT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 389 | #define FSL_FEATURE_SOC_PWT_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 390 | /* @brief PXP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 391 | #define FSL_FEATURE_SOC_PXP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 392 | /* @brief QDEC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 393 | #define FSL_FEATURE_SOC_QDEC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 394 | /* @brief QuadSPI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 395 | #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 396 | /* @brief RCM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 397 | #define FSL_FEATURE_SOC_RCM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 398 | /* @brief RDC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 399 | #define FSL_FEATURE_SOC_RDC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 400 | /* @brief RDC_SEMAPHORE availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 401 | #define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 402 | /* @brief RFSYS availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 403 | #define FSL_FEATURE_SOC_RFSYS_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 404 | /* @brief RFVBAT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 405 | #define FSL_FEATURE_SOC_RFVBAT_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 406 | /* @brief RIT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 407 | #define FSL_FEATURE_SOC_RIT_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 408 | /* @brief RNG availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 409 | #define FSL_FEATURE_SOC_LPC_RNG_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 410 | /* @brief RNGB availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 411 | #define FSL_FEATURE_SOC_RNGB_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 412 | /* @brief ROM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 413 | #define FSL_FEATURE_SOC_ROM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 414 | /* @brief ROMC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 415 | #define FSL_FEATURE_SOC_ROMC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 416 | /* @brief RSIM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 417 | #define FSL_FEATURE_SOC_RSIM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 418 | /* @brief RTC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 419 | #define FSL_FEATURE_SOC_RTC_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 420 | /* @brief SCG availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 421 | #define FSL_FEATURE_SOC_SCG_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 422 | /* @brief SCI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 423 | #define FSL_FEATURE_SOC_SCI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 424 | /* @brief SCT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 425 | #define FSL_FEATURE_SOC_SCT_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 426 | /* @brief SDHC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 427 | #define FSL_FEATURE_SOC_SDHC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 428 | /* @brief SDIF availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 429 | #define FSL_FEATURE_SOC_SDIF_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 430 | /* @brief SDIO availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 431 | #define FSL_FEATURE_SOC_SDIO_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 432 | /* @brief SDMA availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 433 | #define FSL_FEATURE_SOC_SDMA_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 434 | /* @brief SDMAARM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 435 | #define FSL_FEATURE_SOC_SDMAARM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 436 | /* @brief SDMABP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 437 | #define FSL_FEATURE_SOC_SDMABP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 438 | /* @brief SDMACORE availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 439 | #define FSL_FEATURE_SOC_SDMACORE_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 440 | /* @brief SDMCORE availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 441 | #define FSL_FEATURE_SOC_SDMCORE_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 442 | /* @brief SDRAM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 443 | #define FSL_FEATURE_SOC_SDRAM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 444 | /* @brief SEMA4 availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 445 | #define FSL_FEATURE_SOC_SEMA4_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 446 | /* @brief SEMA42 availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 447 | #define FSL_FEATURE_SOC_SEMA42_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 448 | /* @brief SHA availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 449 | #define FSL_FEATURE_SOC_SHA_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 450 | /* @brief SIM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 451 | #define FSL_FEATURE_SOC_SIM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 452 | /* @brief SJC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 453 | #define FSL_FEATURE_SOC_SJC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 454 | /* @brief SLCD availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 455 | #define FSL_FEATURE_SOC_SLCD_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 456 | /* @brief SMARTCARD availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 457 | #define FSL_FEATURE_SOC_SMARTCARD_COUNT (2) |
| AnnaBridge | 163:e59c8e839560 | 458 | /* @brief SMC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 459 | #define FSL_FEATURE_SOC_SMC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 460 | /* @brief SNVS availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 461 | #define FSL_FEATURE_SOC_SNVS_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 462 | /* @brief SPBA availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 463 | #define FSL_FEATURE_SOC_SPBA_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 464 | /* @brief SPDIF availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 465 | #define FSL_FEATURE_SOC_SPDIF_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 466 | /* @brief SPI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 467 | #define FSL_FEATURE_SOC_SPI_COUNT (10) |
| AnnaBridge | 163:e59c8e839560 | 468 | /* @brief SPIFI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 469 | #define FSL_FEATURE_SOC_SPIFI_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 470 | /* @brief SPM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 471 | #define FSL_FEATURE_SOC_SPM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 472 | /* @brief SRC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 473 | #define FSL_FEATURE_SOC_SRC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 474 | /* @brief SYSCON availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 475 | #define FSL_FEATURE_SOC_SYSCON_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 476 | /* @brief TEMPMON availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 477 | #define FSL_FEATURE_SOC_TEMPMON_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 478 | /* @brief TMR availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 479 | #define FSL_FEATURE_SOC_TMR_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 480 | /* @brief TPM availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 481 | #define FSL_FEATURE_SOC_TPM_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 482 | /* @brief TRGMUX availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 483 | #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 484 | /* @brief TRIAMP availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 485 | #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 486 | /* @brief TRNG availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 487 | #define FSL_FEATURE_SOC_TRNG_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 488 | /* @brief TSC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 489 | #define FSL_FEATURE_SOC_TSC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 490 | /* @brief TSI availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 491 | #define FSL_FEATURE_SOC_TSI_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 492 | /* @brief TSTMR availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 493 | #define FSL_FEATURE_SOC_TSTMR_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 494 | /* @brief UART availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 495 | #define FSL_FEATURE_SOC_UART_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 496 | /* @brief USART availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 497 | #define FSL_FEATURE_SOC_USART_COUNT (10) |
| AnnaBridge | 163:e59c8e839560 | 498 | /* @brief USB availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 499 | #define FSL_FEATURE_SOC_USB_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 500 | /* @brief USBHS availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 501 | #define FSL_FEATURE_SOC_USBHS_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 502 | /* @brief USBDCD availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 503 | #define FSL_FEATURE_SOC_USBDCD_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 504 | /* @brief USBFSH availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 505 | #define FSL_FEATURE_SOC_USBFSH_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 506 | /* @brief USBHSD availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 507 | #define FSL_FEATURE_SOC_USBHSD_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 508 | /* @brief USBHSDCD availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 509 | #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 510 | /* @brief USBHSH availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 511 | #define FSL_FEATURE_SOC_USBHSH_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 512 | /* @brief USBNC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 513 | #define FSL_FEATURE_SOC_USBNC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 514 | /* @brief USBPHY availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 515 | #define FSL_FEATURE_SOC_USBPHY_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 516 | /* @brief USB_HSIC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 517 | #define FSL_FEATURE_SOC_USB_HSIC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 518 | /* @brief USB_OTG availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 519 | #define FSL_FEATURE_SOC_USB_OTG_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 520 | /* @brief USBVREG availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 521 | #define FSL_FEATURE_SOC_USBVREG_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 522 | /* @brief USDHC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 523 | #define FSL_FEATURE_SOC_USDHC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 524 | /* @brief UTICK availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 525 | #define FSL_FEATURE_SOC_UTICK_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 526 | /* @brief VIU availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 527 | #define FSL_FEATURE_SOC_VIU_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 528 | /* @brief VREF availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 529 | #define FSL_FEATURE_SOC_VREF_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 530 | /* @brief VFIFO availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 531 | #define FSL_FEATURE_SOC_VFIFO_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 532 | /* @brief WDOG availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 533 | #define FSL_FEATURE_SOC_WDOG_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 534 | /* @brief WKPU availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 535 | #define FSL_FEATURE_SOC_WKPU_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 536 | /* @brief WWDT availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 537 | #define FSL_FEATURE_SOC_WWDT_COUNT (1) |
| AnnaBridge | 163:e59c8e839560 | 538 | /* @brief XBAR availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 539 | #define FSL_FEATURE_SOC_XBAR_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 540 | /* @brief XBARA availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 541 | #define FSL_FEATURE_SOC_XBARA_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 542 | /* @brief XBARB availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 543 | #define FSL_FEATURE_SOC_XBARB_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 544 | /* @brief XCVR availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 545 | #define FSL_FEATURE_SOC_XCVR_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 546 | /* @brief XRDC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 547 | #define FSL_FEATURE_SOC_XRDC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 548 | /* @brief XTALOSC availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 549 | #define FSL_FEATURE_SOC_XTALOSC_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 550 | /* @brief XTALOSC24M availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 551 | #define FSL_FEATURE_SOC_XTALOSC24M_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 552 | /* @brief ZLL availability on the SoC. */ |
| AnnaBridge | 163:e59c8e839560 | 553 | #define FSL_FEATURE_SOC_ZLL_COUNT (0) |
| AnnaBridge | 163:e59c8e839560 | 554 | |
| AnnaBridge | 163:e59c8e839560 | 555 | /* CAN module features */ |
| AnnaBridge | 163:e59c8e839560 | 556 | |
| AnnaBridge | 163:e59c8e839560 | 557 | /* @brief Support CANFD or not */ |
| AnnaBridge | 163:e59c8e839560 | 558 | #define FSL_FEATURE_CAN_SUPPORT_CANFD (1) |
| AnnaBridge | 163:e59c8e839560 | 559 | |
| AnnaBridge | 163:e59c8e839560 | 560 | /* DMA module features */ |
| AnnaBridge | 163:e59c8e839560 | 561 | |
| AnnaBridge | 163:e59c8e839560 | 562 | /* @brief Number of channels */ |
| AnnaBridge | 163:e59c8e839560 | 563 | #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) |
| AnnaBridge | 163:e59c8e839560 | 564 | |
| AnnaBridge | 163:e59c8e839560 | 565 | /* EEPROM module features */ |
| AnnaBridge | 163:e59c8e839560 | 566 | |
| AnnaBridge | 163:e59c8e839560 | 567 | /* @brief Size of the EEPROM */ |
| AnnaBridge | 163:e59c8e839560 | 568 | #define FSL_FEATURE_EEPROM_SIZE (0x00004000) |
| AnnaBridge | 163:e59c8e839560 | 569 | /* @brief Base address of the EEPROM */ |
| AnnaBridge | 163:e59c8e839560 | 570 | #define FSL_FEATURE_EEPROM_BASE_ADDRESS (0x40108000) |
| AnnaBridge | 163:e59c8e839560 | 571 | /* @brief Page count of the EEPROM */ |
| AnnaBridge | 163:e59c8e839560 | 572 | #define FSL_FEATURE_EEPROM_PAGE_COUNT (128) |
| AnnaBridge | 163:e59c8e839560 | 573 | /* @brief Command number for eeprom program */ |
| AnnaBridge | 163:e59c8e839560 | 574 | #define FSL_FEATURE_EEPROM_PROGRAM_CMD (6) |
| AnnaBridge | 163:e59c8e839560 | 575 | /* @brief EEPROM internal clock freqency */ |
| AnnaBridge | 163:e59c8e839560 | 576 | #define FSL_FEATURE_EEPROM_INTERNAL_FREQ (1500000) |
| AnnaBridge | 163:e59c8e839560 | 577 | |
| AnnaBridge | 163:e59c8e839560 | 578 | /* IOCON module features */ |
| AnnaBridge | 163:e59c8e839560 | 579 | |
| AnnaBridge | 163:e59c8e839560 | 580 | /* @brief Func bit field width */ |
| AnnaBridge | 163:e59c8e839560 | 581 | #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) |
| AnnaBridge | 163:e59c8e839560 | 582 | |
| AnnaBridge | 163:e59c8e839560 | 583 | /* PINT module features */ |
| AnnaBridge | 163:e59c8e839560 | 584 | |
| AnnaBridge | 163:e59c8e839560 | 585 | /* @brief Number of connected outputs */ |
| AnnaBridge | 163:e59c8e839560 | 586 | #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) |
| AnnaBridge | 163:e59c8e839560 | 587 | |
| AnnaBridge | 163:e59c8e839560 | 588 | /* SCT module features */ |
| AnnaBridge | 163:e59c8e839560 | 589 | |
| AnnaBridge | 163:e59c8e839560 | 590 | /* @brief Number of events */ |
| AnnaBridge | 163:e59c8e839560 | 591 | #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10) |
| AnnaBridge | 163:e59c8e839560 | 592 | /* @brief Number of states */ |
| AnnaBridge | 163:e59c8e839560 | 593 | #define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) |
| AnnaBridge | 163:e59c8e839560 | 594 | /* @brief Number of match capture */ |
| AnnaBridge | 163:e59c8e839560 | 595 | #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) |
| AnnaBridge | 163:e59c8e839560 | 596 | |
| AnnaBridge | 163:e59c8e839560 | 597 | /* SDIF module features */ |
| AnnaBridge | 163:e59c8e839560 | 598 | |
| AnnaBridge | 163:e59c8e839560 | 599 | /* @brief FIFO depth, every location is a WORD */ |
| AnnaBridge | 163:e59c8e839560 | 600 | #define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) |
| AnnaBridge | 163:e59c8e839560 | 601 | /* @brief Max DMA buffer size */ |
| AnnaBridge | 163:e59c8e839560 | 602 | #define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) |
| AnnaBridge | 163:e59c8e839560 | 603 | /* @brief Max source clock in HZ */ |
| AnnaBridge | 163:e59c8e839560 | 604 | #define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) |
| AnnaBridge | 163:e59c8e839560 | 605 | |
| AnnaBridge | 163:e59c8e839560 | 606 | /* SPIFI module features */ |
| AnnaBridge | 163:e59c8e839560 | 607 | |
| AnnaBridge | 163:e59c8e839560 | 608 | /* @brief SPIFI start address */ |
| AnnaBridge | 163:e59c8e839560 | 609 | #define FSL_FEATURE_SPIFI_START_ADDR (0x10000000) |
| AnnaBridge | 163:e59c8e839560 | 610 | /* @brief SPIFI end address */ |
| AnnaBridge | 163:e59c8e839560 | 611 | #define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF) |
| AnnaBridge | 163:e59c8e839560 | 612 | |
| AnnaBridge | 163:e59c8e839560 | 613 | /* SYSCON module features */ |
| AnnaBridge | 163:e59c8e839560 | 614 | |
| AnnaBridge | 163:e59c8e839560 | 615 | /* @brief Pointer to ROM IAP entry functions */ |
| AnnaBridge | 163:e59c8e839560 | 616 | #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) |
| AnnaBridge | 163:e59c8e839560 | 617 | /* @brief Flash page size in bytes */ |
| AnnaBridge | 163:e59c8e839560 | 618 | #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) |
| AnnaBridge | 163:e59c8e839560 | 619 | /* @brief Flash sector size in bytes */ |
| AnnaBridge | 163:e59c8e839560 | 620 | #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) |
| AnnaBridge | 163:e59c8e839560 | 621 | /* @brief Flash size in bytes */ |
| AnnaBridge | 163:e59c8e839560 | 622 | #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288) |
| AnnaBridge | 163:e59c8e839560 | 623 | |
| AnnaBridge | 163:e59c8e839560 | 624 | /* USB module features */ |
| AnnaBridge | 163:e59c8e839560 | 625 | |
| AnnaBridge | 163:e59c8e839560 | 626 | /* @brief Size of the USB dedicated RAM */ |
| AnnaBridge | 163:e59c8e839560 | 627 | #define FSL_FEATURE_USB_USB_RAM (0x00002000) |
| AnnaBridge | 163:e59c8e839560 | 628 | /* @brief Base address of the USB dedicated RAM */ |
| AnnaBridge | 163:e59c8e839560 | 629 | #define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) |
| AnnaBridge | 163:e59c8e839560 | 630 | |
| AnnaBridge | 163:e59c8e839560 | 631 | /* USBFSH module features */ |
| AnnaBridge | 163:e59c8e839560 | 632 | |
| AnnaBridge | 163:e59c8e839560 | 633 | /* @brief Size of the USB dedicated RAM */ |
| AnnaBridge | 163:e59c8e839560 | 634 | #define FSL_FEATURE_USBFSH_USB_RAM (0x00002000) |
| AnnaBridge | 163:e59c8e839560 | 635 | /* @brief Base address of the USB dedicated RAM */ |
| AnnaBridge | 163:e59c8e839560 | 636 | #define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) |
| AnnaBridge | 163:e59c8e839560 | 637 | |
| AnnaBridge | 163:e59c8e839560 | 638 | /* USBHSD module features */ |
| AnnaBridge | 163:e59c8e839560 | 639 | |
| AnnaBridge | 163:e59c8e839560 | 640 | /* @brief Size of the USB dedicated RAM */ |
| AnnaBridge | 163:e59c8e839560 | 641 | #define FSL_FEATURE_USBHSD_USB_RAM (0x00002000) |
| AnnaBridge | 163:e59c8e839560 | 642 | /* @brief Base address of the USB dedicated RAM */ |
| AnnaBridge | 163:e59c8e839560 | 643 | #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) |
| AnnaBridge | 163:e59c8e839560 | 644 | |
| AnnaBridge | 163:e59c8e839560 | 645 | /* USBHSH module features */ |
| AnnaBridge | 163:e59c8e839560 | 646 | |
| AnnaBridge | 163:e59c8e839560 | 647 | /* @brief Size of the USB dedicated RAM */ |
| AnnaBridge | 163:e59c8e839560 | 648 | #define FSL_FEATURE_USBHSH_USB_RAM (0x00002000) |
| AnnaBridge | 163:e59c8e839560 | 649 | /* @brief Base address of the USB dedicated RAM */ |
| AnnaBridge | 163:e59c8e839560 | 650 | #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) |
| AnnaBridge | 163:e59c8e839560 | 651 | |
| AnnaBridge | 163:e59c8e839560 | 652 | #endif /* _LPC54628_FEATURES_H_ */ |
| AnnaBridge | 163:e59c8e839560 | 653 |
