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TARGET_LPC1549/TOOLCHAIN_ARM_MICRO/LPC15xx.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1
AnnaBridge	171:3a7713b1edbc	2	/**************************************************************************************************//
AnnaBridge	171:3a7713b1edbc	3	* @file LPC15xx.h
AnnaBridge	171:3a7713b1edbc	4	*
AnnaBridge	171:3a7713b1edbc	5	* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
AnnaBridge	171:3a7713b1edbc	6	* LPC15xx from .
AnnaBridge	171:3a7713b1edbc	7	*
AnnaBridge	171:3a7713b1edbc	8	* @version V0.3
AnnaBridge	171:3a7713b1edbc	9	* @date 17. July 2013
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* @note Generated with SVDConv V2.80
AnnaBridge	171:3a7713b1edbc	12	* from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
AnnaBridge	171:3a7713b1edbc	13	*
AnnaBridge	171:3a7713b1edbc	14	* modified by Keil
AnnaBridge	171:3a7713b1edbc	15	* modified by ytsuboi
AnnaBridge	171:3a7713b1edbc	16	*******************************************************************************************************/
AnnaBridge	171:3a7713b1edbc	17
AnnaBridge	171:3a7713b1edbc	18
AnnaBridge	171:3a7713b1edbc	19
AnnaBridge	171:3a7713b1edbc	20	/** @addtogroup (null)
AnnaBridge	171:3a7713b1edbc	21	* @{
AnnaBridge	171:3a7713b1edbc	22	*/
AnnaBridge	171:3a7713b1edbc	23
AnnaBridge	171:3a7713b1edbc	24	/** @addtogroup LPC15xx
AnnaBridge	171:3a7713b1edbc	25	* @{
AnnaBridge	171:3a7713b1edbc	26	*/
AnnaBridge	171:3a7713b1edbc	27
AnnaBridge	171:3a7713b1edbc	28	#ifndef LPC15XX_H
AnnaBridge	171:3a7713b1edbc	29	#define LPC15XX_H
AnnaBridge	171:3a7713b1edbc	30
AnnaBridge	171:3a7713b1edbc	31	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	32	extern "C" {
AnnaBridge	171:3a7713b1edbc	33	#endif
AnnaBridge	171:3a7713b1edbc	34
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* ------------------------- Interrupt Number Definition ------------------------ */
AnnaBridge	171:3a7713b1edbc	37
AnnaBridge	171:3a7713b1edbc	38	typedef enum {
AnnaBridge	171:3a7713b1edbc	39	/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
AnnaBridge	171:3a7713b1edbc	40	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
AnnaBridge	171:3a7713b1edbc	41	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
AnnaBridge	171:3a7713b1edbc	42	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
AnnaBridge	171:3a7713b1edbc	43	MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
AnnaBridge	171:3a7713b1edbc	44	and No Match */
AnnaBridge	171:3a7713b1edbc	45	BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
AnnaBridge	171:3a7713b1edbc	46	related Fault */
AnnaBridge	171:3a7713b1edbc	47	UsageFault_IRQn = -10, /!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
AnnaBridge	171:3a7713b1edbc	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
AnnaBridge	171:3a7713b1edbc	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
AnnaBridge	171:3a7713b1edbc	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
AnnaBridge	171:3a7713b1edbc	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
AnnaBridge	171:3a7713b1edbc	52	/* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
AnnaBridge	171:3a7713b1edbc	53	WDT_IRQn = 0, /!< 0 WDT /
AnnaBridge	171:3a7713b1edbc	54	BOD_IRQn = 1, /!< 1 BOD /
AnnaBridge	171:3a7713b1edbc	55	FLASH_IRQn = 2, /!< 2 FLASH /
AnnaBridge	171:3a7713b1edbc	56	EE_IRQn = 3, /!< 3 EE /
AnnaBridge	171:3a7713b1edbc	57	DMA_IRQn = 4, /!< 4 DMA /
AnnaBridge	171:3a7713b1edbc	58	GINT0_IRQn = 5, /!< 5 GINT0 /
AnnaBridge	171:3a7713b1edbc	59	GINT1_IRQn = 6, /!< 6 GINT1 /
AnnaBridge	171:3a7713b1edbc	60	PIN_INT0_IRQn = 7, /!< 7 PIN_INT0 /
AnnaBridge	171:3a7713b1edbc	61	PIN_INT1_IRQn = 8, /!< 8 PIN_INT1 /
AnnaBridge	171:3a7713b1edbc	62	PIN_INT2_IRQn = 9, /!< 9 PIN_INT2 /
AnnaBridge	171:3a7713b1edbc	63	PIN_INT3_IRQn = 10, /!< 10 PIN_INT3 /
AnnaBridge	171:3a7713b1edbc	64	PIN_INT4_IRQn = 11, /!< 11 PIN_INT4 /
AnnaBridge	171:3a7713b1edbc	65	PIN_INT5_IRQn = 12, /!< 12 PIN_INT5 /
AnnaBridge	171:3a7713b1edbc	66	PIN_INT6_IRQn = 13, /!< 13 PIN_INT6 /
AnnaBridge	171:3a7713b1edbc	67	PIN_INT7_IRQn = 14, /!< 14 PIN_INT7 /
AnnaBridge	171:3a7713b1edbc	68	RIT_IRQn = 15, /!< 15 RIT /
AnnaBridge	171:3a7713b1edbc	69	SCT0_IRQn = 16, /!< 16 SCT0 /
AnnaBridge	171:3a7713b1edbc	70	SCT1_IRQn = 17, /!< 17 SCT1 /
AnnaBridge	171:3a7713b1edbc	71	SCT2_IRQn = 18, /!< 18 SCT2 /
AnnaBridge	171:3a7713b1edbc	72	SCT3_IRQn = 19, /!< 19 SCT3 /
AnnaBridge	171:3a7713b1edbc	73	MRT_IRQn = 20, /!< 20 MRT /
AnnaBridge	171:3a7713b1edbc	74	UART0_IRQn = 21, /!< 21 UART0 /
AnnaBridge	171:3a7713b1edbc	75	UART1_IRQn = 22, /!< 22 UART1 /
AnnaBridge	171:3a7713b1edbc	76	UART2_IRQn = 23, /!< 23 UART2 /
AnnaBridge	171:3a7713b1edbc	77	I2C0_IRQn = 24, /!< 24 I2C0 /
AnnaBridge	171:3a7713b1edbc	78	SPI0_IRQn = 25, /!< 25 SPI0 /
AnnaBridge	171:3a7713b1edbc	79	SPI1_IRQn = 26, /!< 26 SPI1 /
AnnaBridge	171:3a7713b1edbc	80	C_CAN0_IRQn = 27, /!< 27 C_CAN0 /
AnnaBridge	171:3a7713b1edbc	81	USB_IRQ_IRQn = 28, /!< 28 USB_IRQ /
AnnaBridge	171:3a7713b1edbc	82	USB_FIQ_IRQn = 29, /!< 29 USB_FIQ /
AnnaBridge	171:3a7713b1edbc	83	USBWAKEUP_IRQn = 30, /!< 30 USBWAKEUP /
AnnaBridge	171:3a7713b1edbc	84	ADC0_SEQA_IRQn = 31, /!< 31 ADC0_SEQA /
AnnaBridge	171:3a7713b1edbc	85	ADC0_SEQB_IRQn = 32, /!< 32 ADC0_SEQB /
AnnaBridge	171:3a7713b1edbc	86	ADC0_THCMP_IRQn = 33, /!< 33 ADC0_THCMP /
AnnaBridge	171:3a7713b1edbc	87	ADC0_OVR_IRQn = 34, /!< 34 ADC0_OVR /
AnnaBridge	171:3a7713b1edbc	88	ADC1_SEQA_IRQn = 35, /!< 35 ADC1_SEQA /
AnnaBridge	171:3a7713b1edbc	89	ADC1_SEQB_IRQn = 36, /!< 36 ADC1_SEQB /
AnnaBridge	171:3a7713b1edbc	90	ADC1_THCMP_IRQn = 37, /!< 37 ADC1_THCMP /
AnnaBridge	171:3a7713b1edbc	91	ADC1_OVR_IRQn = 38, /!< 38 ADC1_OVR /
AnnaBridge	171:3a7713b1edbc	92	DAC_IRQn = 39, /!< 39 DAC /
AnnaBridge	171:3a7713b1edbc	93	CMP0_IRQn = 40, /!< 40 CMP0 /
AnnaBridge	171:3a7713b1edbc	94	CMP1_IRQn = 41, /!< 41 CMP1 /
AnnaBridge	171:3a7713b1edbc	95	CMP2_IRQn = 42, /!< 42 CMP2 /
AnnaBridge	171:3a7713b1edbc	96	CMP3_IRQn = 43, /!< 43 CMP3 /
AnnaBridge	171:3a7713b1edbc	97	QEI_IRQn = 44, /!< 44 QEI /
AnnaBridge	171:3a7713b1edbc	98	RTC_ALARM_IRQn = 45, /!< 45 RTC_ALARM /
AnnaBridge	171:3a7713b1edbc	99	RTC_WAKE_IRQn = 46 /!< 46 RTC_WAKE /
AnnaBridge	171:3a7713b1edbc	100	} IRQn_Type;
AnnaBridge	171:3a7713b1edbc	101
AnnaBridge	171:3a7713b1edbc	102
AnnaBridge	171:3a7713b1edbc	103	/** @addtogroup Configuration_of_CMSIS
AnnaBridge	171:3a7713b1edbc	104	* @{
AnnaBridge	171:3a7713b1edbc	105	*/
AnnaBridge	171:3a7713b1edbc	106
AnnaBridge	171:3a7713b1edbc	107
AnnaBridge	171:3a7713b1edbc	108	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	109	/* ================ Processor and Core Peripheral Section ================ */
AnnaBridge	171:3a7713b1edbc	110	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	111
AnnaBridge	171:3a7713b1edbc	112	/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
AnnaBridge	171:3a7713b1edbc	113	#define __CM3_REV 0x0201 /!< Cortex-M3 Core Revision /
AnnaBridge	171:3a7713b1edbc	114	#define __MPU_PRESENT 0 /!< MPU present or not /
AnnaBridge	171:3a7713b1edbc	115	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
AnnaBridge	171:3a7713b1edbc	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
AnnaBridge	171:3a7713b1edbc	117	/** @} / / End of group Configuration_of_CMSIS */
AnnaBridge	171:3a7713b1edbc	118
AnnaBridge	171:3a7713b1edbc	119	#include "core_cm3.h" /!< Cortex-M3 processor and core peripherals /
AnnaBridge	171:3a7713b1edbc	120	#include "system_LPC15xx.h" /!< LPC15xx System /
AnnaBridge	171:3a7713b1edbc	121
AnnaBridge	171:3a7713b1edbc	122
AnnaBridge	171:3a7713b1edbc	123	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	124	/* ================ Device Specific Peripheral Section ================ */
AnnaBridge	171:3a7713b1edbc	125	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	126
AnnaBridge	171:3a7713b1edbc	127
AnnaBridge	171:3a7713b1edbc	128	/** @addtogroup Device_Peripheral_Registers
AnnaBridge	171:3a7713b1edbc	129	* @{
AnnaBridge	171:3a7713b1edbc	130	*/
AnnaBridge	171:3a7713b1edbc	131
AnnaBridge	171:3a7713b1edbc	132
AnnaBridge	171:3a7713b1edbc	133	/* ------------------- Start of section using anonymous unions ------------------ */
AnnaBridge	171:3a7713b1edbc	134	#if defined(__CC_ARM)
AnnaBridge	171:3a7713b1edbc	135	#pragma push
AnnaBridge	171:3a7713b1edbc	136	#pragma anon_unions
AnnaBridge	171:3a7713b1edbc	137	#elif defined(__ICCARM__)
AnnaBridge	171:3a7713b1edbc	138	#pragma language=extended
AnnaBridge	171:3a7713b1edbc	139	#elif defined(__GNUC__)
AnnaBridge	171:3a7713b1edbc	140	/* anonymous unions are enabled by default */
AnnaBridge	171:3a7713b1edbc	141	#elif defined(__TMS470__)
AnnaBridge	171:3a7713b1edbc	142	/* anonymous unions are enabled by default */
AnnaBridge	171:3a7713b1edbc	143	#elif defined(__TASKING__)
AnnaBridge	171:3a7713b1edbc	144	#pragma warning 586
AnnaBridge	171:3a7713b1edbc	145	#else
AnnaBridge	171:3a7713b1edbc	146	#warning Not supported compiler type
AnnaBridge	171:3a7713b1edbc	147	#endif
AnnaBridge	171:3a7713b1edbc	148
AnnaBridge	171:3a7713b1edbc	149
AnnaBridge	171:3a7713b1edbc	150
AnnaBridge	171:3a7713b1edbc	151	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	152	/* ================ GPIO_PORT ================ */
AnnaBridge	171:3a7713b1edbc	153	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	154
AnnaBridge	171:3a7713b1edbc	155
AnnaBridge	171:3a7713b1edbc	156	/**
AnnaBridge	171:3a7713b1edbc	157	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
AnnaBridge	171:3a7713b1edbc	158	*/
AnnaBridge	171:3a7713b1edbc	159
AnnaBridge	171:3a7713b1edbc	160	typedef struct { /!< GPIO_PORT Structure /
AnnaBridge	171:3a7713b1edbc	161	__IO uint8_t B[76]; /!< Byte pin registers /
AnnaBridge	171:3a7713b1edbc	162	__I uint32_t RESERVED0[1005];
AnnaBridge	171:3a7713b1edbc	163	__IO uint32_t W[76]; /!< Word pin registers /
AnnaBridge	171:3a7713b1edbc	164	__I uint32_t RESERVED1[948];
AnnaBridge	171:3a7713b1edbc	165	__IO uint32_t DIR[3]; /!< Port Direction registers /
AnnaBridge	171:3a7713b1edbc	166	__I uint32_t RESERVED2[29];
AnnaBridge	171:3a7713b1edbc	167	__IO uint32_t MASK[3]; /!< Port Mask register /
AnnaBridge	171:3a7713b1edbc	168	__I uint32_t RESERVED3[29];
AnnaBridge	171:3a7713b1edbc	169	__IO uint32_t PIN[3]; /!< Port pin register /
AnnaBridge	171:3a7713b1edbc	170	__I uint32_t RESERVED4[29];
AnnaBridge	171:3a7713b1edbc	171	__IO uint32_t MPIN[3]; /!< Masked port register /
AnnaBridge	171:3a7713b1edbc	172	__I uint32_t RESERVED5[29];
AnnaBridge	171:3a7713b1edbc	173	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
AnnaBridge	171:3a7713b1edbc	174	__I uint32_t RESERVED6[29];
AnnaBridge	171:3a7713b1edbc	175	__O uint32_t CLR[3]; /!< Clear port /
AnnaBridge	171:3a7713b1edbc	176	__I uint32_t RESERVED7[29];
AnnaBridge	171:3a7713b1edbc	177	__O uint32_t NOT[3]; /!< Toggle port /
AnnaBridge	171:3a7713b1edbc	178	} LPC_GPIO_PORT_Type;
AnnaBridge	171:3a7713b1edbc	179
AnnaBridge	171:3a7713b1edbc	180
AnnaBridge	171:3a7713b1edbc	181	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	182	/* ================ DMA ================ */
AnnaBridge	171:3a7713b1edbc	183	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	184
AnnaBridge	171:3a7713b1edbc	185
AnnaBridge	171:3a7713b1edbc	186	/**
AnnaBridge	171:3a7713b1edbc	187	* @brief DMA controller (DMA)
AnnaBridge	171:3a7713b1edbc	188	*/
AnnaBridge	171:3a7713b1edbc	189
AnnaBridge	171:3a7713b1edbc	190	typedef struct { /!< DMA Structure /
AnnaBridge	171:3a7713b1edbc	191	__IO uint32_t CTRL; /!< DMA control. /
AnnaBridge	171:3a7713b1edbc	192	__I uint32_t INTSTAT; /!< Interrupt status. /
AnnaBridge	171:3a7713b1edbc	193	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
AnnaBridge	171:3a7713b1edbc	194	__I uint32_t RESERVED0[5];
AnnaBridge	171:3a7713b1edbc	195	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	196	__I uint32_t RESERVED1;
AnnaBridge	171:3a7713b1edbc	197	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	198	__I uint32_t RESERVED2;
AnnaBridge	171:3a7713b1edbc	199	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	200	__I uint32_t RESERVED3;
AnnaBridge	171:3a7713b1edbc	201	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	202	__I uint32_t RESERVED4;
AnnaBridge	171:3a7713b1edbc	203	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	204	__I uint32_t RESERVED5;
AnnaBridge	171:3a7713b1edbc	205	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	206	__I uint32_t RESERVED6;
AnnaBridge	171:3a7713b1edbc	207	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	208	__I uint32_t RESERVED7;
AnnaBridge	171:3a7713b1edbc	209	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	210	__I uint32_t RESERVED8;
AnnaBridge	171:3a7713b1edbc	211	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	212	__I uint32_t RESERVED9;
AnnaBridge	171:3a7713b1edbc	213	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	214	__I uint32_t RESERVED10;
AnnaBridge	171:3a7713b1edbc	215	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	216	__I uint32_t RESERVED11;
AnnaBridge	171:3a7713b1edbc	217	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
AnnaBridge	171:3a7713b1edbc	218	__I uint32_t RESERVED12[225];
AnnaBridge	171:3a7713b1edbc	219	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	220	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	221	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	222	__I uint32_t RESERVED13;
AnnaBridge	171:3a7713b1edbc	223	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	224	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	225	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	226	__I uint32_t RESERVED14;
AnnaBridge	171:3a7713b1edbc	227	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	228	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	229	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	230	__I uint32_t RESERVED15;
AnnaBridge	171:3a7713b1edbc	231	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	232	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	233	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	234	__I uint32_t RESERVED16;
AnnaBridge	171:3a7713b1edbc	235	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	236	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	237	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	238	__I uint32_t RESERVED17;
AnnaBridge	171:3a7713b1edbc	239	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	240	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	241	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	242	__I uint32_t RESERVED18;
AnnaBridge	171:3a7713b1edbc	243	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	244	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	245	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	246	__I uint32_t RESERVED19;
AnnaBridge	171:3a7713b1edbc	247	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	248	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	249	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	250	__I uint32_t RESERVED20;
AnnaBridge	171:3a7713b1edbc	251	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	252	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	253	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	254	__I uint32_t RESERVED21;
AnnaBridge	171:3a7713b1edbc	255	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	256	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	257	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	258	__I uint32_t RESERVED22;
AnnaBridge	171:3a7713b1edbc	259	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	260	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	261	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	262	__I uint32_t RESERVED23;
AnnaBridge	171:3a7713b1edbc	263	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	264	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	265	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	266	__I uint32_t RESERVED24;
AnnaBridge	171:3a7713b1edbc	267	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	268	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	269	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	270	__I uint32_t RESERVED25;
AnnaBridge	171:3a7713b1edbc	271	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	272	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	273	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	274	__I uint32_t RESERVED26;
AnnaBridge	171:3a7713b1edbc	275	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	276	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	277	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	278	__I uint32_t RESERVED27;
AnnaBridge	171:3a7713b1edbc	279	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	280	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	281	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	282	__I uint32_t RESERVED28;
AnnaBridge	171:3a7713b1edbc	283	__IO uint32_t CFG16; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	284	__I uint32_t CTLSTAT16; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	285	__IO uint32_t XFERCFG16; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	286	__I uint32_t RESERVED29;
AnnaBridge	171:3a7713b1edbc	287	__IO uint32_t CFG17; /!< Configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	288	__I uint32_t CTLSTAT17; /!< Control and status register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	289	__IO uint32_t XFERCFG17; /!< Transfer configuration register for DMA channel 0. /
AnnaBridge	171:3a7713b1edbc	290	} LPC_DMA_Type;
AnnaBridge	171:3a7713b1edbc	291
AnnaBridge	171:3a7713b1edbc	292
AnnaBridge	171:3a7713b1edbc	293	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	294	/* ================ USB ================ */
AnnaBridge	171:3a7713b1edbc	295	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	296
AnnaBridge	171:3a7713b1edbc	297
AnnaBridge	171:3a7713b1edbc	298	/**
AnnaBridge	171:3a7713b1edbc	299	* @brief USB device controller (USB)
AnnaBridge	171:3a7713b1edbc	300	*/
AnnaBridge	171:3a7713b1edbc	301
AnnaBridge	171:3a7713b1edbc	302	typedef struct { /!< USB Structure /
AnnaBridge	171:3a7713b1edbc	303	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
AnnaBridge	171:3a7713b1edbc	304	__IO uint32_t INFO; /!< USB Info register /
AnnaBridge	171:3a7713b1edbc	305	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
AnnaBridge	171:3a7713b1edbc	306	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
AnnaBridge	171:3a7713b1edbc	307	__IO uint32_t LPM; /!< Link Power Management register /
AnnaBridge	171:3a7713b1edbc	308	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
AnnaBridge	171:3a7713b1edbc	309	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
AnnaBridge	171:3a7713b1edbc	310	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
AnnaBridge	171:3a7713b1edbc	311	__IO uint32_t INTSTAT; /!< USB interrupt status register /
AnnaBridge	171:3a7713b1edbc	312	__IO uint32_t INTEN; /!< USB interrupt enable register /
AnnaBridge	171:3a7713b1edbc	313	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
AnnaBridge	171:3a7713b1edbc	314	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
AnnaBridge	171:3a7713b1edbc	315	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	316	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
AnnaBridge	171:3a7713b1edbc	317	} LPC_USB_Type;
AnnaBridge	171:3a7713b1edbc	318
AnnaBridge	171:3a7713b1edbc	319
AnnaBridge	171:3a7713b1edbc	320	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	321	/* ================ CRC ================ */
AnnaBridge	171:3a7713b1edbc	322	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	323
AnnaBridge	171:3a7713b1edbc	324
AnnaBridge	171:3a7713b1edbc	325	/**
AnnaBridge	171:3a7713b1edbc	326	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
AnnaBridge	171:3a7713b1edbc	327	*/
AnnaBridge	171:3a7713b1edbc	328
AnnaBridge	171:3a7713b1edbc	329	typedef struct { /!< CRC Structure /
AnnaBridge	171:3a7713b1edbc	330	__IO uint32_t MODE; /!< CRC mode register /
AnnaBridge	171:3a7713b1edbc	331	__IO uint32_t SEED; /!< CRC seed register /
AnnaBridge	171:3a7713b1edbc	332
AnnaBridge	171:3a7713b1edbc	333	union {
AnnaBridge	171:3a7713b1edbc	334	__O uint32_t WR_DATA; /!< CRC data register /
AnnaBridge	171:3a7713b1edbc	335	__I uint32_t SUM; /!< CRC checksum register /
AnnaBridge	171:3a7713b1edbc	336	};
AnnaBridge	171:3a7713b1edbc	337	} LPC_CRC_Type;
AnnaBridge	171:3a7713b1edbc	338
AnnaBridge	171:3a7713b1edbc	339
AnnaBridge	171:3a7713b1edbc	340	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	341	/* ================ SCT0 ================ */
AnnaBridge	171:3a7713b1edbc	342	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	343
AnnaBridge	171:3a7713b1edbc	344
AnnaBridge	171:3a7713b1edbc	345	/**
AnnaBridge	171:3a7713b1edbc	346	* @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
AnnaBridge	171:3a7713b1edbc	347	*/
AnnaBridge	171:3a7713b1edbc	348
AnnaBridge	171:3a7713b1edbc	349	typedef struct { /!< SCT0 Structure /
AnnaBridge	171:3a7713b1edbc	350	__IO uint32_t CONFIG; /!< SCT configuration register /
AnnaBridge	171:3a7713b1edbc	351	__IO uint32_t CTRL; /!< SCT control register /
AnnaBridge	171:3a7713b1edbc	352	__IO uint32_t LIMIT; /!< SCT limit register /
AnnaBridge	171:3a7713b1edbc	353	__IO uint32_t HALT; /!< SCT halt condition register /
AnnaBridge	171:3a7713b1edbc	354	__IO uint32_t STOP; /!< SCT stop condition register /
AnnaBridge	171:3a7713b1edbc	355	__IO uint32_t START; /!< SCT start condition register /
AnnaBridge	171:3a7713b1edbc	356	__IO uint32_t DITHER; /!< SCT dither condition register /
AnnaBridge	171:3a7713b1edbc	357	__I uint32_t RESERVED0[9];
AnnaBridge	171:3a7713b1edbc	358	__IO uint32_t COUNT; /!< SCT counter register /
AnnaBridge	171:3a7713b1edbc	359	__IO uint32_t STATE; /!< SCT state register /
AnnaBridge	171:3a7713b1edbc	360	__I uint32_t INPUT; /!< SCT input register /
AnnaBridge	171:3a7713b1edbc	361	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
AnnaBridge	171:3a7713b1edbc	362	__IO uint32_t OUTPUT; /!< SCT output register /
AnnaBridge	171:3a7713b1edbc	363	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
AnnaBridge	171:3a7713b1edbc	364	__IO uint32_t RES; /!< SCT conflict resolution register /
AnnaBridge	171:3a7713b1edbc	365	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
AnnaBridge	171:3a7713b1edbc	366	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
AnnaBridge	171:3a7713b1edbc	367	__I uint32_t RESERVED1[35];
AnnaBridge	171:3a7713b1edbc	368	__IO uint32_t EVEN; /!< SCT event enable register /
AnnaBridge	171:3a7713b1edbc	369	__IO uint32_t EVFLAG; /!< SCT event flag register /
AnnaBridge	171:3a7713b1edbc	370	__IO uint32_t CONEN; /!< SCT conflict enable register /
AnnaBridge	171:3a7713b1edbc	371	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
AnnaBridge	171:3a7713b1edbc	372
AnnaBridge	171:3a7713b1edbc	373	union {
AnnaBridge	171:3a7713b1edbc	374	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	375	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	376	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	377	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	378	};
AnnaBridge	171:3a7713b1edbc	379
AnnaBridge	171:3a7713b1edbc	380	union {
AnnaBridge	171:3a7713b1edbc	381	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	382	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	383	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	384	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	385	};
AnnaBridge	171:3a7713b1edbc	386
AnnaBridge	171:3a7713b1edbc	387	union {
AnnaBridge	171:3a7713b1edbc	388	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	389	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	390	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	391	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	392	};
AnnaBridge	171:3a7713b1edbc	393
AnnaBridge	171:3a7713b1edbc	394	union {
AnnaBridge	171:3a7713b1edbc	395	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	396	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	397	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	398	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	399	};
AnnaBridge	171:3a7713b1edbc	400
AnnaBridge	171:3a7713b1edbc	401	union {
AnnaBridge	171:3a7713b1edbc	402	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	403	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	404	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	405	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	406	};
AnnaBridge	171:3a7713b1edbc	407
AnnaBridge	171:3a7713b1edbc	408	union {
AnnaBridge	171:3a7713b1edbc	409	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	410	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	411	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	412	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	413	};
AnnaBridge	171:3a7713b1edbc	414
AnnaBridge	171:3a7713b1edbc	415	union {
AnnaBridge	171:3a7713b1edbc	416	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	417	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	418	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	419	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	420	};
AnnaBridge	171:3a7713b1edbc	421
AnnaBridge	171:3a7713b1edbc	422	union {
AnnaBridge	171:3a7713b1edbc	423	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	424	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	425	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	426	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	427	};
AnnaBridge	171:3a7713b1edbc	428
AnnaBridge	171:3a7713b1edbc	429	union {
AnnaBridge	171:3a7713b1edbc	430	__I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	431	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	432	__IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	433	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	434	};
AnnaBridge	171:3a7713b1edbc	435
AnnaBridge	171:3a7713b1edbc	436	union {
AnnaBridge	171:3a7713b1edbc	437	__IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	438	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	439	__I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	440	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	441	};
AnnaBridge	171:3a7713b1edbc	442
AnnaBridge	171:3a7713b1edbc	443	union {
AnnaBridge	171:3a7713b1edbc	444	__IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	445	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	446	__I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	447	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	448	};
AnnaBridge	171:3a7713b1edbc	449
AnnaBridge	171:3a7713b1edbc	450	union {
AnnaBridge	171:3a7713b1edbc	451	__IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	452	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	453	__I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	454	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	455	};
AnnaBridge	171:3a7713b1edbc	456
AnnaBridge	171:3a7713b1edbc	457	union {
AnnaBridge	171:3a7713b1edbc	458	__IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	459	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	460	__I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	461	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	462	};
AnnaBridge	171:3a7713b1edbc	463
AnnaBridge	171:3a7713b1edbc	464	union {
AnnaBridge	171:3a7713b1edbc	465	__IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	466	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	467	__I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	468	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	469	};
AnnaBridge	171:3a7713b1edbc	470
AnnaBridge	171:3a7713b1edbc	471	union {
AnnaBridge	171:3a7713b1edbc	472	__I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	473	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	474	__IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	475	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	476	};
AnnaBridge	171:3a7713b1edbc	477
AnnaBridge	171:3a7713b1edbc	478	union {
AnnaBridge	171:3a7713b1edbc	479	__IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
AnnaBridge	171:3a7713b1edbc	480	to REGMODE15 = 0 */
AnnaBridge	171:3a7713b1edbc	481	__I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	482	REGMODE15 = 1 */
AnnaBridge	171:3a7713b1edbc	483	};
AnnaBridge	171:3a7713b1edbc	484	__IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
AnnaBridge	171:3a7713b1edbc	485	0 to 5. */
AnnaBridge	171:3a7713b1edbc	486	__IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
AnnaBridge	171:3a7713b1edbc	487	0 to 5. */
AnnaBridge	171:3a7713b1edbc	488	__IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
AnnaBridge	171:3a7713b1edbc	489	0 to 5. */
AnnaBridge	171:3a7713b1edbc	490	__IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
AnnaBridge	171:3a7713b1edbc	491	0 to 5. */
AnnaBridge	171:3a7713b1edbc	492	__IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
AnnaBridge	171:3a7713b1edbc	493	0 to 5. */
AnnaBridge	171:3a7713b1edbc	494	__IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
AnnaBridge	171:3a7713b1edbc	495	0 to 5. */
AnnaBridge	171:3a7713b1edbc	496	__I uint32_t RESERVED2[42];
AnnaBridge	171:3a7713b1edbc	497
AnnaBridge	171:3a7713b1edbc	498	union {
AnnaBridge	171:3a7713b1edbc	499	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	500	= 1 */
AnnaBridge	171:3a7713b1edbc	501	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	502	= 0 */
AnnaBridge	171:3a7713b1edbc	503	};
AnnaBridge	171:3a7713b1edbc	504
AnnaBridge	171:3a7713b1edbc	505	union {
AnnaBridge	171:3a7713b1edbc	506	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	507	= 0 */
AnnaBridge	171:3a7713b1edbc	508	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	509	= 1 */
AnnaBridge	171:3a7713b1edbc	510	};
AnnaBridge	171:3a7713b1edbc	511
AnnaBridge	171:3a7713b1edbc	512	union {
AnnaBridge	171:3a7713b1edbc	513	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	514	= 0 */
AnnaBridge	171:3a7713b1edbc	515	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	516	= 1 */
AnnaBridge	171:3a7713b1edbc	517	};
AnnaBridge	171:3a7713b1edbc	518
AnnaBridge	171:3a7713b1edbc	519	union {
AnnaBridge	171:3a7713b1edbc	520	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	521	= 1 */
AnnaBridge	171:3a7713b1edbc	522	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	523	= 0 */
AnnaBridge	171:3a7713b1edbc	524	};
AnnaBridge	171:3a7713b1edbc	525
AnnaBridge	171:3a7713b1edbc	526	union {
AnnaBridge	171:3a7713b1edbc	527	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	528	= 1 */
AnnaBridge	171:3a7713b1edbc	529	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	530	= 0 */
AnnaBridge	171:3a7713b1edbc	531	};
AnnaBridge	171:3a7713b1edbc	532
AnnaBridge	171:3a7713b1edbc	533	union {
AnnaBridge	171:3a7713b1edbc	534	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	535	= 1 */
AnnaBridge	171:3a7713b1edbc	536	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	537	= 0 */
AnnaBridge	171:3a7713b1edbc	538	};
AnnaBridge	171:3a7713b1edbc	539
AnnaBridge	171:3a7713b1edbc	540	union {
AnnaBridge	171:3a7713b1edbc	541	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	542	= 0 */
AnnaBridge	171:3a7713b1edbc	543	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	544	= 1 */
AnnaBridge	171:3a7713b1edbc	545	};
AnnaBridge	171:3a7713b1edbc	546
AnnaBridge	171:3a7713b1edbc	547	union {
AnnaBridge	171:3a7713b1edbc	548	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	549	= 0 */
AnnaBridge	171:3a7713b1edbc	550	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	551	= 1 */
AnnaBridge	171:3a7713b1edbc	552	};
AnnaBridge	171:3a7713b1edbc	553
AnnaBridge	171:3a7713b1edbc	554	union {
AnnaBridge	171:3a7713b1edbc	555	__IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	556	= 1 */
AnnaBridge	171:3a7713b1edbc	557	__IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	558	= 0 */
AnnaBridge	171:3a7713b1edbc	559	};
AnnaBridge	171:3a7713b1edbc	560
AnnaBridge	171:3a7713b1edbc	561	union {
AnnaBridge	171:3a7713b1edbc	562	__IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	563	= 1 */
AnnaBridge	171:3a7713b1edbc	564	__IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	565	= 0 */
AnnaBridge	171:3a7713b1edbc	566	};
AnnaBridge	171:3a7713b1edbc	567
AnnaBridge	171:3a7713b1edbc	568	union {
AnnaBridge	171:3a7713b1edbc	569	__IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	570	= 1 */
AnnaBridge	171:3a7713b1edbc	571	__IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	572	= 0 */
AnnaBridge	171:3a7713b1edbc	573	};
AnnaBridge	171:3a7713b1edbc	574
AnnaBridge	171:3a7713b1edbc	575	union {
AnnaBridge	171:3a7713b1edbc	576	__IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	577	= 1 */
AnnaBridge	171:3a7713b1edbc	578	__IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	579	= 0 */
AnnaBridge	171:3a7713b1edbc	580	};
AnnaBridge	171:3a7713b1edbc	581
AnnaBridge	171:3a7713b1edbc	582	union {
AnnaBridge	171:3a7713b1edbc	583	__IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	584	= 0 */
AnnaBridge	171:3a7713b1edbc	585	__IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	586	= 1 */
AnnaBridge	171:3a7713b1edbc	587	};
AnnaBridge	171:3a7713b1edbc	588
AnnaBridge	171:3a7713b1edbc	589	union {
AnnaBridge	171:3a7713b1edbc	590	__IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	591	= 0 */
AnnaBridge	171:3a7713b1edbc	592	__IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	593	= 1 */
AnnaBridge	171:3a7713b1edbc	594	};
AnnaBridge	171:3a7713b1edbc	595
AnnaBridge	171:3a7713b1edbc	596	union {
AnnaBridge	171:3a7713b1edbc	597	__IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	598	= 1 */
AnnaBridge	171:3a7713b1edbc	599	__IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	600	= 0 */
AnnaBridge	171:3a7713b1edbc	601	};
AnnaBridge	171:3a7713b1edbc	602
AnnaBridge	171:3a7713b1edbc	603	union {
AnnaBridge	171:3a7713b1edbc	604	__IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
AnnaBridge	171:3a7713b1edbc	605	= 1 */
AnnaBridge	171:3a7713b1edbc	606	__IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
AnnaBridge	171:3a7713b1edbc	607	= 0 */
AnnaBridge	171:3a7713b1edbc	608	};
AnnaBridge	171:3a7713b1edbc	609	__IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
AnnaBridge	171:3a7713b1edbc	610	registers 0 to 5. */
AnnaBridge	171:3a7713b1edbc	611	__IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
AnnaBridge	171:3a7713b1edbc	612	registers 0 to 5. */
AnnaBridge	171:3a7713b1edbc	613	__IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
AnnaBridge	171:3a7713b1edbc	614	registers 0 to 5. */
AnnaBridge	171:3a7713b1edbc	615	__IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
AnnaBridge	171:3a7713b1edbc	616	registers 0 to 5. */
AnnaBridge	171:3a7713b1edbc	617	__IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
AnnaBridge	171:3a7713b1edbc	618	registers 0 to 5. */
AnnaBridge	171:3a7713b1edbc	619	__IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
AnnaBridge	171:3a7713b1edbc	620	registers 0 to 5. */
AnnaBridge	171:3a7713b1edbc	621	__I uint32_t RESERVED3[42];
AnnaBridge	171:3a7713b1edbc	622	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	623	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	624	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	625	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	626	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	627	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	628	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	629	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	630	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	631	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	632	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	633	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	634	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	635	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	636	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	637	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	638	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	639	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	640	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	641	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	642	__IO uint32_t EV10_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	643	__IO uint32_t EV10_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	644	__IO uint32_t EV11_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	645	__IO uint32_t EV11_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	646	__IO uint32_t EV12_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	647	__IO uint32_t EV12_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	648	__IO uint32_t EV13_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	649	__IO uint32_t EV13_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	650	__IO uint32_t EV14_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	651	__IO uint32_t EV14_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	652	__IO uint32_t EV15_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	653	__IO uint32_t EV15_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	654	__I uint32_t RESERVED4[96];
AnnaBridge	171:3a7713b1edbc	655	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	656	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	657	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	658	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	659	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	660	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	661	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	662	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	663	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	664	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	665	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	666	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	667	__IO uint32_t OUT6_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	668	__IO uint32_t OUT6_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	669	__IO uint32_t OUT7_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	670	__IO uint32_t OUT7_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	671	__IO uint32_t OUT8_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	672	__IO uint32_t OUT8_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	673	__IO uint32_t OUT9_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	674	__IO uint32_t OUT9_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	675	} LPC_SCT0_Type;
AnnaBridge	171:3a7713b1edbc	676
AnnaBridge	171:3a7713b1edbc	677
AnnaBridge	171:3a7713b1edbc	678	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	679	/* ================ SCT2 ================ */
AnnaBridge	171:3a7713b1edbc	680	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	681
AnnaBridge	171:3a7713b1edbc	682
AnnaBridge	171:3a7713b1edbc	683	/**
AnnaBridge	171:3a7713b1edbc	684	* @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
AnnaBridge	171:3a7713b1edbc	685	*/
AnnaBridge	171:3a7713b1edbc	686
AnnaBridge	171:3a7713b1edbc	687	typedef struct { /!< SCT2 Structure /
AnnaBridge	171:3a7713b1edbc	688	__IO uint32_t CONFIG; /!< SCT configuration register /
AnnaBridge	171:3a7713b1edbc	689	__IO uint32_t CTRL; /!< SCT control register /
AnnaBridge	171:3a7713b1edbc	690	__IO uint32_t LIMIT; /!< SCT limit register /
AnnaBridge	171:3a7713b1edbc	691	__IO uint32_t HALT; /!< SCT halt condition register /
AnnaBridge	171:3a7713b1edbc	692	__IO uint32_t STOP; /!< SCT stop condition register /
AnnaBridge	171:3a7713b1edbc	693	__IO uint32_t START; /!< SCT start condition register /
AnnaBridge	171:3a7713b1edbc	694	__I uint32_t RESERVED0[10];
AnnaBridge	171:3a7713b1edbc	695	__IO uint32_t COUNT; /!< SCT counter register /
AnnaBridge	171:3a7713b1edbc	696	__IO uint32_t STATE; /!< SCT state register /
AnnaBridge	171:3a7713b1edbc	697	__I uint32_t INPUT; /!< SCT input register /
AnnaBridge	171:3a7713b1edbc	698	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
AnnaBridge	171:3a7713b1edbc	699	__IO uint32_t OUTPUT; /!< SCT output register /
AnnaBridge	171:3a7713b1edbc	700	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
AnnaBridge	171:3a7713b1edbc	701	__IO uint32_t RES; /!< SCT conflict resolution register /
AnnaBridge	171:3a7713b1edbc	702	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
AnnaBridge	171:3a7713b1edbc	703	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
AnnaBridge	171:3a7713b1edbc	704	__I uint32_t RESERVED1[35];
AnnaBridge	171:3a7713b1edbc	705	__IO uint32_t EVEN; /!< SCT event enable register /
AnnaBridge	171:3a7713b1edbc	706	__IO uint32_t EVFLAG; /!< SCT event flag register /
AnnaBridge	171:3a7713b1edbc	707	__IO uint32_t CONEN; /!< SCT conflict enable register /
AnnaBridge	171:3a7713b1edbc	708	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
AnnaBridge	171:3a7713b1edbc	709
AnnaBridge	171:3a7713b1edbc	710	union {
AnnaBridge	171:3a7713b1edbc	711	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	712	= 1 */
AnnaBridge	171:3a7713b1edbc	713	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	714	REGMODE7 = 0 */
AnnaBridge	171:3a7713b1edbc	715	};
AnnaBridge	171:3a7713b1edbc	716
AnnaBridge	171:3a7713b1edbc	717	union {
AnnaBridge	171:3a7713b1edbc	718	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	719	= 1 */
AnnaBridge	171:3a7713b1edbc	720	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	721	REGMODE7 = 0 */
AnnaBridge	171:3a7713b1edbc	722	};
AnnaBridge	171:3a7713b1edbc	723
AnnaBridge	171:3a7713b1edbc	724	union {
AnnaBridge	171:3a7713b1edbc	725	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	726	= 1 */
AnnaBridge	171:3a7713b1edbc	727	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	728	REGMODE7 = 0 */
AnnaBridge	171:3a7713b1edbc	729	};
AnnaBridge	171:3a7713b1edbc	730
AnnaBridge	171:3a7713b1edbc	731	union {
AnnaBridge	171:3a7713b1edbc	732	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	733	REGMODE7 = 0 */
AnnaBridge	171:3a7713b1edbc	734	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	735	= 1 */
AnnaBridge	171:3a7713b1edbc	736	};
AnnaBridge	171:3a7713b1edbc	737
AnnaBridge	171:3a7713b1edbc	738	union {
AnnaBridge	171:3a7713b1edbc	739	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	740	= 1 */
AnnaBridge	171:3a7713b1edbc	741	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	742	REGMODE7 = 0 */
AnnaBridge	171:3a7713b1edbc	743	};
AnnaBridge	171:3a7713b1edbc	744
AnnaBridge	171:3a7713b1edbc	745	union {
AnnaBridge	171:3a7713b1edbc	746	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	747	REGMODE7 = 0 */
AnnaBridge	171:3a7713b1edbc	748	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	749	= 1 */
AnnaBridge	171:3a7713b1edbc	750	};
AnnaBridge	171:3a7713b1edbc	751
AnnaBridge	171:3a7713b1edbc	752	union {
AnnaBridge	171:3a7713b1edbc	753	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	754	= 1 */
AnnaBridge	171:3a7713b1edbc	755	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	756	REGMODE7 = 0 */
AnnaBridge	171:3a7713b1edbc	757	};
AnnaBridge	171:3a7713b1edbc	758
AnnaBridge	171:3a7713b1edbc	759	union {
AnnaBridge	171:3a7713b1edbc	760	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	761	= 1 */
AnnaBridge	171:3a7713b1edbc	762	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
AnnaBridge	171:3a7713b1edbc	763	REGMODE7 = 0 */
AnnaBridge	171:3a7713b1edbc	764	};
AnnaBridge	171:3a7713b1edbc	765	__I uint32_t RESERVED2[56];
AnnaBridge	171:3a7713b1edbc	766
AnnaBridge	171:3a7713b1edbc	767	union {
AnnaBridge	171:3a7713b1edbc	768	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
AnnaBridge	171:3a7713b1edbc	769	= 1 */
AnnaBridge	171:3a7713b1edbc	770	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	771	= 0 */
AnnaBridge	171:3a7713b1edbc	772	};
AnnaBridge	171:3a7713b1edbc	773
AnnaBridge	171:3a7713b1edbc	774	union {
AnnaBridge	171:3a7713b1edbc	775	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
AnnaBridge	171:3a7713b1edbc	776	= 1 */
AnnaBridge	171:3a7713b1edbc	777	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	778	= 0 */
AnnaBridge	171:3a7713b1edbc	779	};
AnnaBridge	171:3a7713b1edbc	780
AnnaBridge	171:3a7713b1edbc	781	union {
AnnaBridge	171:3a7713b1edbc	782	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
AnnaBridge	171:3a7713b1edbc	783	= 1 */
AnnaBridge	171:3a7713b1edbc	784	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	785	= 0 */
AnnaBridge	171:3a7713b1edbc	786	};
AnnaBridge	171:3a7713b1edbc	787
AnnaBridge	171:3a7713b1edbc	788	union {
AnnaBridge	171:3a7713b1edbc	789	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	790	= 0 */
AnnaBridge	171:3a7713b1edbc	791	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
AnnaBridge	171:3a7713b1edbc	792	= 1 */
AnnaBridge	171:3a7713b1edbc	793	};
AnnaBridge	171:3a7713b1edbc	794
AnnaBridge	171:3a7713b1edbc	795	union {
AnnaBridge	171:3a7713b1edbc	796	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
AnnaBridge	171:3a7713b1edbc	797	= 1 */
AnnaBridge	171:3a7713b1edbc	798	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	799	= 0 */
AnnaBridge	171:3a7713b1edbc	800	};
AnnaBridge	171:3a7713b1edbc	801
AnnaBridge	171:3a7713b1edbc	802	union {
AnnaBridge	171:3a7713b1edbc	803	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	804	= 0 */
AnnaBridge	171:3a7713b1edbc	805	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
AnnaBridge	171:3a7713b1edbc	806	= 1 */
AnnaBridge	171:3a7713b1edbc	807	};
AnnaBridge	171:3a7713b1edbc	808
AnnaBridge	171:3a7713b1edbc	809	union {
AnnaBridge	171:3a7713b1edbc	810	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
AnnaBridge	171:3a7713b1edbc	811	= 1 */
AnnaBridge	171:3a7713b1edbc	812	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	813	= 0 */
AnnaBridge	171:3a7713b1edbc	814	};
AnnaBridge	171:3a7713b1edbc	815
AnnaBridge	171:3a7713b1edbc	816	union {
AnnaBridge	171:3a7713b1edbc	817	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
AnnaBridge	171:3a7713b1edbc	818	= 1 */
AnnaBridge	171:3a7713b1edbc	819	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
AnnaBridge	171:3a7713b1edbc	820	= 0 */
AnnaBridge	171:3a7713b1edbc	821	};
AnnaBridge	171:3a7713b1edbc	822	__I uint32_t RESERVED3[56];
AnnaBridge	171:3a7713b1edbc	823	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	824	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	825	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	826	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	827	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	828	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	829	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	830	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	831	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	832	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	833	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	834	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	835	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	836	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	837	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	838	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	839	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	840	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	841	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
AnnaBridge	171:3a7713b1edbc	842	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
AnnaBridge	171:3a7713b1edbc	843	__I uint32_t RESERVED4[108];
AnnaBridge	171:3a7713b1edbc	844	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	845	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	846	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	847	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	848	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	849	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	850	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	851	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	852	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	853	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	854	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
AnnaBridge	171:3a7713b1edbc	855	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
AnnaBridge	171:3a7713b1edbc	856	} LPC_SCT2_Type;
AnnaBridge	171:3a7713b1edbc	857
AnnaBridge	171:3a7713b1edbc	858
AnnaBridge	171:3a7713b1edbc	859	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	860	/* ================ ADC0 ================ */
AnnaBridge	171:3a7713b1edbc	861	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	862
AnnaBridge	171:3a7713b1edbc	863
AnnaBridge	171:3a7713b1edbc	864	/**
AnnaBridge	171:3a7713b1edbc	865	* @brief 12-bit ADC controller ADC0/1 (ADC0)
AnnaBridge	171:3a7713b1edbc	866	*/
AnnaBridge	171:3a7713b1edbc	867
AnnaBridge	171:3a7713b1edbc	868	typedef struct { /!< ADC0 Structure /
AnnaBridge	171:3a7713b1edbc	869	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
AnnaBridge	171:3a7713b1edbc	870	bits for each sequence and the A/D power-down bit. */
AnnaBridge	171:3a7713b1edbc	871	__IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
AnnaBridge	171:3a7713b1edbc	872	internal source for various channels */
AnnaBridge	171:3a7713b1edbc	873	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
AnnaBridge	171:3a7713b1edbc	874	and channel selection for conversion sequence-A. Also specifies
AnnaBridge	171:3a7713b1edbc	875	interrupt mode for sequence-A. */
AnnaBridge	171:3a7713b1edbc	876	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
AnnaBridge	171:3a7713b1edbc	877	and channel selection for conversion sequence-B. Also specifies
AnnaBridge	171:3a7713b1edbc	878	interrupt mode for sequence-B. */
AnnaBridge	171:3a7713b1edbc	879	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
AnnaBridge	171:3a7713b1edbc	880	the result of the most recent A/D conversion performed under
AnnaBridge	171:3a7713b1edbc	881	sequence-A */
AnnaBridge	171:3a7713b1edbc	882	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
AnnaBridge	171:3a7713b1edbc	883	the result of the most recent A/D conversion performed under
AnnaBridge	171:3a7713b1edbc	884	sequence-B */
AnnaBridge	171:3a7713b1edbc	885	__I uint32_t RESERVED0[2];
AnnaBridge	171:3a7713b1edbc	886	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
AnnaBridge	171:3a7713b1edbc	887	of the most recent conversion completed on channel 0. */
AnnaBridge	171:3a7713b1edbc	888	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
AnnaBridge	171:3a7713b1edbc	889	level for automatic threshold comparison for any channels linked
AnnaBridge	171:3a7713b1edbc	890	to threshold pair 0. */
AnnaBridge	171:3a7713b1edbc	891	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
AnnaBridge	171:3a7713b1edbc	892	level for automatic threshold comparison for any channels linked
AnnaBridge	171:3a7713b1edbc	893	to threshold pair 1. */
AnnaBridge	171:3a7713b1edbc	894	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
AnnaBridge	171:3a7713b1edbc	895	level for automatic threshold comparison for any channels linked
AnnaBridge	171:3a7713b1edbc	896	to threshold pair 0. */
AnnaBridge	171:3a7713b1edbc	897	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
AnnaBridge	171:3a7713b1edbc	898	level for automatic threshold comparison for any channels linked
AnnaBridge	171:3a7713b1edbc	899	to threshold pair 1. */
AnnaBridge	171:3a7713b1edbc	900	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
AnnaBridge	171:3a7713b1edbc	901	threshold compare registers are to be used for each channel */
AnnaBridge	171:3a7713b1edbc	902	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
AnnaBridge	171:3a7713b1edbc	903	bits that enable the sequence-A, sequence-B, threshold compare
AnnaBridge	171:3a7713b1edbc	904	and data overrun interrupts to be generated. */
AnnaBridge	171:3a7713b1edbc	905	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
AnnaBridge	171:3a7713b1edbc	906	and the individual component overrun and threshold-compare flags.
AnnaBridge	171:3a7713b1edbc	907	(The overrun bits replicate information stored in the result
AnnaBridge	171:3a7713b1edbc	908	registers). */
AnnaBridge	171:3a7713b1edbc	909	__IO uint32_t TRM; /!< ADC trim register. /
AnnaBridge	171:3a7713b1edbc	910	} LPC_ADC0_Type;
AnnaBridge	171:3a7713b1edbc	911
AnnaBridge	171:3a7713b1edbc	912
AnnaBridge	171:3a7713b1edbc	913	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	914	/* ================ DAC ================ */
AnnaBridge	171:3a7713b1edbc	915	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	916
AnnaBridge	171:3a7713b1edbc	917
AnnaBridge	171:3a7713b1edbc	918	/**
AnnaBridge	171:3a7713b1edbc	919	* @brief 12-bit DAC Modification (DAC)
AnnaBridge	171:3a7713b1edbc	920	*/
AnnaBridge	171:3a7713b1edbc	921
AnnaBridge	171:3a7713b1edbc	922	typedef struct { /!< DAC Structure /
AnnaBridge	171:3a7713b1edbc	923	__IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
AnnaBridge	171:3a7713b1edbc	924	value to be converted to analog. */
AnnaBridge	171:3a7713b1edbc	925	__IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
AnnaBridge	171:3a7713b1edbc	926	DAC operation and the interrupt/dma request flag. */
AnnaBridge	171:3a7713b1edbc	927	__IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
AnnaBridge	171:3a7713b1edbc	928	value for the internal DAC DMA/Interrupt timer. */
AnnaBridge	171:3a7713b1edbc	929	} LPC_DAC_Type;
AnnaBridge	171:3a7713b1edbc	930
AnnaBridge	171:3a7713b1edbc	931
AnnaBridge	171:3a7713b1edbc	932	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	933	/* ================ ACMP ================ */
AnnaBridge	171:3a7713b1edbc	934	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	935
AnnaBridge	171:3a7713b1edbc	936
AnnaBridge	171:3a7713b1edbc	937	/**
AnnaBridge	171:3a7713b1edbc	938	* @brief Analog comparators ACMP0/1/2/3 (ACMP)
AnnaBridge	171:3a7713b1edbc	939	*/
AnnaBridge	171:3a7713b1edbc	940
AnnaBridge	171:3a7713b1edbc	941	typedef struct { /!< ACMP Structure /
AnnaBridge	171:3a7713b1edbc	942	__IO uint32_t CTRL; /!< Comparator block control register /
AnnaBridge	171:3a7713b1edbc	943	__IO uint32_t CMP0; /!< Comparator 0 source control /
AnnaBridge	171:3a7713b1edbc	944	__IO uint32_t CMPFILTR0; /!< Comparator 0 pin filter set-up /
AnnaBridge	171:3a7713b1edbc	945	__IO uint32_t CMP1; /!< Comparator 1 source control /
AnnaBridge	171:3a7713b1edbc	946	__IO uint32_t CMPFILTR1; /!< Comparator 0 pin filter set-up /
AnnaBridge	171:3a7713b1edbc	947	__IO uint32_t CMP2; /!< Comparator 2 source control /
AnnaBridge	171:3a7713b1edbc	948	__IO uint32_t CMPFILTR2; /!< Comparator 0 pin filter set-up /
AnnaBridge	171:3a7713b1edbc	949	__IO uint32_t CMP3; /!< Comparator 3 source control /
AnnaBridge	171:3a7713b1edbc	950	__IO uint32_t CMPFILTR3; /!< Comparator 0 pin filter set-up /
AnnaBridge	171:3a7713b1edbc	951	} LPC_ACMP_Type;
AnnaBridge	171:3a7713b1edbc	952
AnnaBridge	171:3a7713b1edbc	953
AnnaBridge	171:3a7713b1edbc	954	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	955	/* ================ INMUX ================ */
AnnaBridge	171:3a7713b1edbc	956	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	957
AnnaBridge	171:3a7713b1edbc	958
AnnaBridge	171:3a7713b1edbc	959	/**
AnnaBridge	171:3a7713b1edbc	960	* @brief Input multiplexing (INMUX) (INMUX)
AnnaBridge	171:3a7713b1edbc	961	*/
AnnaBridge	171:3a7713b1edbc	962
AnnaBridge	171:3a7713b1edbc	963	typedef struct { /!< INMUX Structure /
AnnaBridge	171:3a7713b1edbc	964	__IO uint32_t SCT0_INMUX[7]; /!< Pinmux register for SCT0 input 0 /
AnnaBridge	171:3a7713b1edbc	965	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	966	__IO uint32_t SCT1_INMUX[7]; /!< Pinmux register for SCT1 input 0 /
AnnaBridge	171:3a7713b1edbc	967	__I uint32_t RESERVED1;
AnnaBridge	171:3a7713b1edbc	968	__IO uint32_t SCT2_INMUX[3]; /!< Pinmux register for SCT2 input 0 /
AnnaBridge	171:3a7713b1edbc	969	__I uint32_t RESERVED2[5];
AnnaBridge	171:3a7713b1edbc	970	__IO uint32_t SCT3_INMUX[3]; /!< Pinmux register for SCT3 input 0 /
AnnaBridge	171:3a7713b1edbc	971	__I uint32_t RESERVED3[21];
AnnaBridge	171:3a7713b1edbc	972	__IO uint32_t PINTSEL[8]; /!< Pin interrupt select register 0 /
AnnaBridge	171:3a7713b1edbc	973	__IO uint32_t DMA_ITRIG_INMUX[18]; /!< Trigger input for DMA channel 0 select register. /
AnnaBridge	171:3a7713b1edbc	974	__I uint32_t RESERVED4[14];
AnnaBridge	171:3a7713b1edbc	975	__IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
AnnaBridge	171:3a7713b1edbc	976	clock */
AnnaBridge	171:3a7713b1edbc	977	__IO uint32_t FREQMEAS_TARGET; /!< Clock selection for frequency measurement function target clock /
AnnaBridge	171:3a7713b1edbc	978	} LPC_INMUX_Type;
AnnaBridge	171:3a7713b1edbc	979
AnnaBridge	171:3a7713b1edbc	980
AnnaBridge	171:3a7713b1edbc	981	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	982	/* ================ RTC ================ */
AnnaBridge	171:3a7713b1edbc	983	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	984
AnnaBridge	171:3a7713b1edbc	985
AnnaBridge	171:3a7713b1edbc	986	/**
AnnaBridge	171:3a7713b1edbc	987	* @brief Real-Time Clock (RTC) (RTC)
AnnaBridge	171:3a7713b1edbc	988	*/
AnnaBridge	171:3a7713b1edbc	989
AnnaBridge	171:3a7713b1edbc	990	typedef struct { /!< RTC Structure /
AnnaBridge	171:3a7713b1edbc	991	__IO uint32_t CTRL; /!< RTC control register /
AnnaBridge	171:3a7713b1edbc	992	__IO uint32_t MATCH; /!< RTC match register /
AnnaBridge	171:3a7713b1edbc	993	__IO uint32_t COUNT; /!< RTC counter register /
AnnaBridge	171:3a7713b1edbc	994	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
AnnaBridge	171:3a7713b1edbc	995	} LPC_RTC_Type;
AnnaBridge	171:3a7713b1edbc	996
AnnaBridge	171:3a7713b1edbc	997
AnnaBridge	171:3a7713b1edbc	998	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	999	/* ================ WWDT ================ */
AnnaBridge	171:3a7713b1edbc	1000	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1001
AnnaBridge	171:3a7713b1edbc	1002
AnnaBridge	171:3a7713b1edbc	1003	/**
AnnaBridge	171:3a7713b1edbc	1004	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
AnnaBridge	171:3a7713b1edbc	1005	*/
AnnaBridge	171:3a7713b1edbc	1006
AnnaBridge	171:3a7713b1edbc	1007	typedef struct { /!< WWDT Structure /
AnnaBridge	171:3a7713b1edbc	1008	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
AnnaBridge	171:3a7713b1edbc	1009	and status of the Watchdog Timer. */
AnnaBridge	171:3a7713b1edbc	1010	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
AnnaBridge	171:3a7713b1edbc	1011	the time-out value. */
AnnaBridge	171:3a7713b1edbc	1012	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
AnnaBridge	171:3a7713b1edbc	1013	to this register reloads the Watchdog timer with the value contained
AnnaBridge	171:3a7713b1edbc	1014	in WDTC. */
AnnaBridge	171:3a7713b1edbc	1015	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
AnnaBridge	171:3a7713b1edbc	1016	the current value of the Watchdog timer. */
AnnaBridge	171:3a7713b1edbc	1017	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	1018	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
AnnaBridge	171:3a7713b1edbc	1019	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
AnnaBridge	171:3a7713b1edbc	1020	} LPC_WWDT_Type;
AnnaBridge	171:3a7713b1edbc	1021
AnnaBridge	171:3a7713b1edbc	1022
AnnaBridge	171:3a7713b1edbc	1023	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1024	/* ================ SWM ================ */
AnnaBridge	171:3a7713b1edbc	1025	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1026
AnnaBridge	171:3a7713b1edbc	1027
AnnaBridge	171:3a7713b1edbc	1028	/**
AnnaBridge	171:3a7713b1edbc	1029	* @brief Switch Matrix (SWM) (SWM)
AnnaBridge	171:3a7713b1edbc	1030	*/
AnnaBridge	171:3a7713b1edbc	1031
AnnaBridge	171:3a7713b1edbc	1032	typedef struct { /!< SWM Structure /
AnnaBridge	171:3a7713b1edbc	1033	union {
AnnaBridge	171:3a7713b1edbc	1034	__IO uint32_t PINASSIGN[16];
AnnaBridge	171:3a7713b1edbc	1035	struct {
AnnaBridge	171:3a7713b1edbc	1036	__IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
AnnaBridge	171:3a7713b1edbc	1037	U0_RTS, U0_CTS. */
AnnaBridge	171:3a7713b1edbc	1038	__IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
AnnaBridge	171:3a7713b1edbc	1039	U1_RXD, U1_RTS. */
AnnaBridge	171:3a7713b1edbc	1040	__IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
AnnaBridge	171:3a7713b1edbc	1041	U2_TXD, U2_RXD. */
AnnaBridge	171:3a7713b1edbc	1042	__IO uint32_t PINASSIGN3; /!< Pin assign register 3. Assign movable function . /
AnnaBridge	171:3a7713b1edbc	1043	__IO uint32_t PINASSIGN4; /!< Pin assign register 4. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1044	__IO uint32_t PINASSIGN5; /!< Pin assign register 5. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1045	__IO uint32_t PINASSIGN6; /!< Pin assign register 6. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1046	__IO uint32_t PINASSIGN7; /!< Pin assign register 7. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1047	__IO uint32_t PINASSIGN8; /!< Pin assign register 8. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1048	__IO uint32_t PINASSIGN9; /!< Pin assign register 9. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1049	__IO uint32_t PINASSIGN10; /!< Pin assign register 10. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1050	__IO uint32_t PINASSIGN11; /!< Pin assign register 11. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1051	__IO uint32_t PINASSIGN12; /!< Pin assign register 12. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1052	__IO uint32_t PINASSIGN13; /!< Pin assign register 13. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1053	__IO uint32_t PINASSIGN14; /!< Pin assign register 14. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1054	__IO uint32_t PINASSIGN15; /!< Pin assign register 15. Assign movable functions /
AnnaBridge	171:3a7713b1edbc	1055	};
AnnaBridge	171:3a7713b1edbc	1056	};
AnnaBridge	171:3a7713b1edbc	1057	__I uint32_t RESERVED0[96];
AnnaBridge	171:3a7713b1edbc	1058	__IO uint32_t PINENABLE0; /!< Pin enable register 0. Enables fixed-pin functions /
AnnaBridge	171:3a7713b1edbc	1059	__IO uint32_t PINENABLE1; /!< Pin enable register 0. Enables fixed-pin functions /
AnnaBridge	171:3a7713b1edbc	1060	} LPC_SWM_Type;
AnnaBridge	171:3a7713b1edbc	1061
AnnaBridge	171:3a7713b1edbc	1062
AnnaBridge	171:3a7713b1edbc	1063	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1064	/* ================ PMU ================ */
AnnaBridge	171:3a7713b1edbc	1065	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1066
AnnaBridge	171:3a7713b1edbc	1067
AnnaBridge	171:3a7713b1edbc	1068	/**
AnnaBridge	171:3a7713b1edbc	1069	* @brief Power Management Unit (PMU) (PMU)
AnnaBridge	171:3a7713b1edbc	1070	*/
AnnaBridge	171:3a7713b1edbc	1071
AnnaBridge	171:3a7713b1edbc	1072	typedef struct { /!< PMU Structure /
AnnaBridge	171:3a7713b1edbc	1073	__IO uint32_t PCON; /!< Power control register /
AnnaBridge	171:3a7713b1edbc	1074	__IO uint32_t GPREG0; /!< General purpose register 0 /
AnnaBridge	171:3a7713b1edbc	1075	__IO uint32_t GPREG1; /!< General purpose register 0 /
AnnaBridge	171:3a7713b1edbc	1076	__IO uint32_t GPREG2; /!< General purpose register 0 /
AnnaBridge	171:3a7713b1edbc	1077	__IO uint32_t GPREG3; /!< General purpose register 0 /
AnnaBridge	171:3a7713b1edbc	1078	__IO uint32_t DPDCTRL; /!< Deep power-down control register /
AnnaBridge	171:3a7713b1edbc	1079	} LPC_PMU_Type;
AnnaBridge	171:3a7713b1edbc	1080
AnnaBridge	171:3a7713b1edbc	1081
AnnaBridge	171:3a7713b1edbc	1082	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1083	/* ================ USART0 ================ */
AnnaBridge	171:3a7713b1edbc	1084	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1085
AnnaBridge	171:3a7713b1edbc	1086
AnnaBridge	171:3a7713b1edbc	1087	/**
AnnaBridge	171:3a7713b1edbc	1088	* @brief USART0 (USART0)
AnnaBridge	171:3a7713b1edbc	1089	*/
AnnaBridge	171:3a7713b1edbc	1090
AnnaBridge	171:3a7713b1edbc	1091	typedef struct { /!< USART0 Structure /
AnnaBridge	171:3a7713b1edbc	1092	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
AnnaBridge	171:3a7713b1edbc	1093	that typically are not changed during operation. */
AnnaBridge	171:3a7713b1edbc	1094	__IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
AnnaBridge	171:3a7713b1edbc	1095	likely to change during operation. */
AnnaBridge	171:3a7713b1edbc	1096	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
AnnaBridge	171:3a7713b1edbc	1097	here. Writing ones clears some bits in the register. Some bits
AnnaBridge	171:3a7713b1edbc	1098	can be cleared by writing a 1 to them. */
AnnaBridge	171:3a7713b1edbc	1099	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
AnnaBridge	171:3a7713b1edbc	1100	interrupt enable bit for each potential USART interrupt. A complete
AnnaBridge	171:3a7713b1edbc	1101	value may be read from this register. Writing a 1 to any implemented
AnnaBridge	171:3a7713b1edbc	1102	bit position causes that bit to be set. */
AnnaBridge	171:3a7713b1edbc	1103	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
AnnaBridge	171:3a7713b1edbc	1104	of bits in the INTENSET register. Writing a 1 to any implemented
AnnaBridge	171:3a7713b1edbc	1105	bit position causes the corresponding bit to be cleared. */
AnnaBridge	171:3a7713b1edbc	1106	__I uint32_t RXDATA; /!< Receiver Data register. Contains the last character received. /
AnnaBridge	171:3a7713b1edbc	1107	__I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
AnnaBridge	171:3a7713b1edbc	1108	received with the current USART receive status. Allows DMA or
AnnaBridge	171:3a7713b1edbc	1109	software to recover incoming data and status together. */
AnnaBridge	171:3a7713b1edbc	1110	__IO uint32_t TXDATA; /!< Transmit Data register. Data to be transmitted is written here. /
AnnaBridge	171:3a7713b1edbc	1111	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
AnnaBridge	171:3a7713b1edbc	1112	value. */
AnnaBridge	171:3a7713b1edbc	1113	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
AnnaBridge	171:3a7713b1edbc	1114	enabled. */
AnnaBridge	171:3a7713b1edbc	1115	} LPC_USART0_Type;
AnnaBridge	171:3a7713b1edbc	1116
AnnaBridge	171:3a7713b1edbc	1117
AnnaBridge	171:3a7713b1edbc	1118	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1119	/* ================ SPI0 ================ */
AnnaBridge	171:3a7713b1edbc	1120	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1121
AnnaBridge	171:3a7713b1edbc	1122
AnnaBridge	171:3a7713b1edbc	1123	/**
AnnaBridge	171:3a7713b1edbc	1124	* @brief SPI0 (SPI0)
AnnaBridge	171:3a7713b1edbc	1125	*/
AnnaBridge	171:3a7713b1edbc	1126
AnnaBridge	171:3a7713b1edbc	1127	typedef struct { /!< SPI0 Structure /
AnnaBridge	171:3a7713b1edbc	1128	__IO uint32_t CFG; /!< SPI Configuration register /
AnnaBridge	171:3a7713b1edbc	1129	__IO uint32_t DLY; /!< SPI Delay register /
AnnaBridge	171:3a7713b1edbc	1130	__IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
AnnaBridge	171:3a7713b1edbc	1131	to that bit position */
AnnaBridge	171:3a7713b1edbc	1132	__IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
AnnaBridge	171:3a7713b1edbc	1133	from this register. Writing a 1 to any implemented bit position
AnnaBridge	171:3a7713b1edbc	1134	causes that bit to be set. */
AnnaBridge	171:3a7713b1edbc	1135	__O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
AnnaBridge	171:3a7713b1edbc	1136	position causes the corresponding bit in INTENSET to be cleared. */
AnnaBridge	171:3a7713b1edbc	1137	__I uint32_t RXDAT; /!< SPI Receive Data /
AnnaBridge	171:3a7713b1edbc	1138	__IO uint32_t TXDATCTL; /!< SPI Transmit Data with Control /
AnnaBridge	171:3a7713b1edbc	1139	__IO uint32_t TXDAT; /!< SPI Transmit Data with Control /
AnnaBridge	171:3a7713b1edbc	1140	__IO uint32_t TXCTL; /!< SPI Transmit Control /
AnnaBridge	171:3a7713b1edbc	1141	__IO uint32_t DIV; /!< SPI clock Divider /
AnnaBridge	171:3a7713b1edbc	1142	__I uint32_t INTSTAT; /!< SPI Interrupt Status /
AnnaBridge	171:3a7713b1edbc	1143	} LPC_SPI0_Type;
AnnaBridge	171:3a7713b1edbc	1144
AnnaBridge	171:3a7713b1edbc	1145
AnnaBridge	171:3a7713b1edbc	1146	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1147	/* ================ I2C0 ================ */
AnnaBridge	171:3a7713b1edbc	1148	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1149
AnnaBridge	171:3a7713b1edbc	1150
AnnaBridge	171:3a7713b1edbc	1151	/**
AnnaBridge	171:3a7713b1edbc	1152	* @brief I2C-bus interface (I2C0)
AnnaBridge	171:3a7713b1edbc	1153	*/
AnnaBridge	171:3a7713b1edbc	1154
AnnaBridge	171:3a7713b1edbc	1155	typedef struct { /!< I2C0 Structure /
AnnaBridge	171:3a7713b1edbc	1156	__IO uint32_t CFG; /!< Configuration for shared functions. /
AnnaBridge	171:3a7713b1edbc	1157	__IO uint32_t STAT; /!< Status register for Master, Slave, and Monitor functions. /
AnnaBridge	171:3a7713b1edbc	1158	__IO uint32_t INTENSET; /!< Interrupt Enable Set and read register. /
AnnaBridge	171:3a7713b1edbc	1159	__O uint32_t INTENCLR; /!< Interrupt Enable Clear register. /
AnnaBridge	171:3a7713b1edbc	1160	__IO uint32_t TIMEOUT; /!< Time-out value register. /
AnnaBridge	171:3a7713b1edbc	1161	__IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
AnnaBridge	171:3a7713b1edbc	1162	what time increments are used for the MSTTIME and SLVTIME registers. */
AnnaBridge	171:3a7713b1edbc	1163	__I uint32_t INTSTAT; /!< Interrupt Status register for Master, Slave, and Monitor functions. /
AnnaBridge	171:3a7713b1edbc	1164	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	1165	__IO uint32_t MSTCTL; /!< Master control register. /
AnnaBridge	171:3a7713b1edbc	1166	__IO uint32_t MSTTIME; /!< Master timing configuration. /
AnnaBridge	171:3a7713b1edbc	1167	__IO uint32_t MSTDAT; /!< Combined Master receiver and transmitter data register. /
AnnaBridge	171:3a7713b1edbc	1168	__I uint32_t RESERVED1[5];
AnnaBridge	171:3a7713b1edbc	1169	__IO uint32_t SLVCTL; /!< Slave control register. /
AnnaBridge	171:3a7713b1edbc	1170	__IO uint32_t SLVDAT; /!< Combined Slave receiver and transmitter data register. /
AnnaBridge	171:3a7713b1edbc	1171	__IO uint32_t SLVADR0; /!< Slave address 0. /
AnnaBridge	171:3a7713b1edbc	1172	__IO uint32_t SLVADR1; /!< Slave address 0. /
AnnaBridge	171:3a7713b1edbc	1173	__IO uint32_t SLVADR2; /!< Slave address 0. /
AnnaBridge	171:3a7713b1edbc	1174	__IO uint32_t SLVADR3; /!< Slave address 0. /
AnnaBridge	171:3a7713b1edbc	1175	__IO uint32_t SLVQUAL0; /!< Slave Qualification for address 0. /
AnnaBridge	171:3a7713b1edbc	1176	__I uint32_t RESERVED2[9];
AnnaBridge	171:3a7713b1edbc	1177	__I uint32_t MONRXDAT; /!< Monitor receiver data register. /
AnnaBridge	171:3a7713b1edbc	1178	} LPC_I2C0_Type;
AnnaBridge	171:3a7713b1edbc	1179
AnnaBridge	171:3a7713b1edbc	1180
AnnaBridge	171:3a7713b1edbc	1181	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1182	/* ================ QEI ================ */
AnnaBridge	171:3a7713b1edbc	1183	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1184
AnnaBridge	171:3a7713b1edbc	1185
AnnaBridge	171:3a7713b1edbc	1186	/**
AnnaBridge	171:3a7713b1edbc	1187	* @brief Quadrature Encoder Interface (QEI) (QEI)
AnnaBridge	171:3a7713b1edbc	1188	*/
AnnaBridge	171:3a7713b1edbc	1189
AnnaBridge	171:3a7713b1edbc	1190	typedef struct { /!< QEI Structure /
AnnaBridge	171:3a7713b1edbc	1191	__O uint32_t CON; /!< Control register /
AnnaBridge	171:3a7713b1edbc	1192	__I uint32_t STAT; /!< Encoder status register /
AnnaBridge	171:3a7713b1edbc	1193	__IO uint32_t CONF; /!< Configuration register /
AnnaBridge	171:3a7713b1edbc	1194	__I uint32_t POS; /!< Position register /
AnnaBridge	171:3a7713b1edbc	1195	__IO uint32_t MAXPOS; /!< Maximum position register /
AnnaBridge	171:3a7713b1edbc	1196	__IO uint32_t CMPOS0; /!< position compare register 0 /
AnnaBridge	171:3a7713b1edbc	1197	__IO uint32_t CMPOS1; /!< position compare register 1 /
AnnaBridge	171:3a7713b1edbc	1198	__IO uint32_t CMPOS2; /!< position compare register 2 /
AnnaBridge	171:3a7713b1edbc	1199	__I uint32_t INXCNT; /!< Index count register /
AnnaBridge	171:3a7713b1edbc	1200	__IO uint32_t INXCMP0; /!< Index compare register 0 /
AnnaBridge	171:3a7713b1edbc	1201	__IO uint32_t LOAD; /!< Velocity timer reload register /
AnnaBridge	171:3a7713b1edbc	1202	__I uint32_t TIME; /!< Velocity timer register /
AnnaBridge	171:3a7713b1edbc	1203	__I uint32_t VEL; /!< Velocity counter register /
AnnaBridge	171:3a7713b1edbc	1204	__I uint32_t CAP; /!< Velocity capture register /
AnnaBridge	171:3a7713b1edbc	1205	__IO uint32_t VELCOMP; /!< Velocity compare register /
AnnaBridge	171:3a7713b1edbc	1206	__IO uint32_t FILTERPHA; /!< Digital filter register on input phase A (QEI_A) /
AnnaBridge	171:3a7713b1edbc	1207	__IO uint32_t FILTERPHB; /!< Digital filter register on input phase B (QEI_B) /
AnnaBridge	171:3a7713b1edbc	1208	__IO uint32_t FILTERINX; /!< Digital filter register on input index (QEI_IDX) /
AnnaBridge	171:3a7713b1edbc	1209	__IO uint32_t WINDOW; /!< Index acceptance window register /
AnnaBridge	171:3a7713b1edbc	1210	__IO uint32_t INXCMP1; /!< Index compare register 1 /
AnnaBridge	171:3a7713b1edbc	1211	__IO uint32_t INXCMP2; /!< Index compare register 2 /
AnnaBridge	171:3a7713b1edbc	1212	__I uint32_t RESERVED0[993];
AnnaBridge	171:3a7713b1edbc	1213	__O uint32_t IEC; /!< Interrupt enable clear register /
AnnaBridge	171:3a7713b1edbc	1214	__O uint32_t IES; /!< Interrupt enable set register /
AnnaBridge	171:3a7713b1edbc	1215	__I uint32_t INTSTAT; /!< Interrupt status register /
AnnaBridge	171:3a7713b1edbc	1216	__O uint32_t IE; /!< Interrupt enable clear register /
AnnaBridge	171:3a7713b1edbc	1217	__O uint32_t CLR; /!< Interrupt status clear register /
AnnaBridge	171:3a7713b1edbc	1218	__O uint32_t SET; /!< Interrupt status set register /
AnnaBridge	171:3a7713b1edbc	1219	} LPC_QEI_Type;
AnnaBridge	171:3a7713b1edbc	1220
AnnaBridge	171:3a7713b1edbc	1221
AnnaBridge	171:3a7713b1edbc	1222	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1223	/* ================ SYSCON ================ */
AnnaBridge	171:3a7713b1edbc	1224	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1225
AnnaBridge	171:3a7713b1edbc	1226
AnnaBridge	171:3a7713b1edbc	1227	/**
AnnaBridge	171:3a7713b1edbc	1228	* @brief System configuration (SYSCON) (SYSCON)
AnnaBridge	171:3a7713b1edbc	1229	*/
AnnaBridge	171:3a7713b1edbc	1230
AnnaBridge	171:3a7713b1edbc	1231	typedef struct { /!< SYSCON Structure /
AnnaBridge	171:3a7713b1edbc	1232	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
AnnaBridge	171:3a7713b1edbc	1233	__I uint32_t RESERVED0[4];
AnnaBridge	171:3a7713b1edbc	1234	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
AnnaBridge	171:3a7713b1edbc	1235	__I uint32_t RESERVED1;
AnnaBridge	171:3a7713b1edbc	1236	__IO uint32_t NMISRC; /!< NMI Source Control /
AnnaBridge	171:3a7713b1edbc	1237	__I uint32_t RESERVED2[8];
AnnaBridge	171:3a7713b1edbc	1238	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
AnnaBridge	171:3a7713b1edbc	1239	__IO uint32_t PRESETCTRL0; /!< Peripheral reset control 0 /
AnnaBridge	171:3a7713b1edbc	1240	__IO uint32_t PRESETCTRL1; /!< Peripheral reset control 1 /
AnnaBridge	171:3a7713b1edbc	1241	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
AnnaBridge	171:3a7713b1edbc	1242	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
AnnaBridge	171:3a7713b1edbc	1243	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 2 /
AnnaBridge	171:3a7713b1edbc	1244	__I uint32_t RESERVED3[10];
AnnaBridge	171:3a7713b1edbc	1245	__IO uint32_t MAINCLKSELA; /!< Main clock source select A /
AnnaBridge	171:3a7713b1edbc	1246	__IO uint32_t MAINCLKSELB; /!< Main clock source select B /
AnnaBridge	171:3a7713b1edbc	1247	__IO uint32_t USBCLKSEL; /!< USB clock source select /
AnnaBridge	171:3a7713b1edbc	1248	__IO uint32_t ADCASYNCCLKSEL; /!< ADC asynchronous clock source select /
AnnaBridge	171:3a7713b1edbc	1249	__I uint32_t RESERVED4;
AnnaBridge	171:3a7713b1edbc	1250	__IO uint32_t CLKOUTSELA; /!< CLKOUT clock source select A /
AnnaBridge	171:3a7713b1edbc	1251	__IO uint32_t CLKOUTSELB; /!< CLKOUT clock source select B /
AnnaBridge	171:3a7713b1edbc	1252	__I uint32_t RESERVED5;
AnnaBridge	171:3a7713b1edbc	1253	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
AnnaBridge	171:3a7713b1edbc	1254	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
AnnaBridge	171:3a7713b1edbc	1255	__IO uint32_t SCTPLLCLKSEL; /!< SCT PLL clock source select /
AnnaBridge	171:3a7713b1edbc	1256	__I uint32_t RESERVED6[5];
AnnaBridge	171:3a7713b1edbc	1257	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
AnnaBridge	171:3a7713b1edbc	1258	__IO uint32_t SYSAHBCLKCTRL0; /!< System clock control 0 /
AnnaBridge	171:3a7713b1edbc	1259	__IO uint32_t SYSAHBCLKCTRL1; /!< System clock control 1 /
AnnaBridge	171:3a7713b1edbc	1260	__IO uint32_t SYSTICKCLKDIV; /!< SYSTICK clock divider /
AnnaBridge	171:3a7713b1edbc	1261	__IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
AnnaBridge	171:3a7713b1edbc	1262	baud rate generator. */
AnnaBridge	171:3a7713b1edbc	1263	__IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
AnnaBridge	171:3a7713b1edbc	1264	filter */
AnnaBridge	171:3a7713b1edbc	1265	__IO uint32_t TRACECLKDIV; /!< ARM trace clock divider /
AnnaBridge	171:3a7713b1edbc	1266	__I uint32_t RESERVED7[4];
AnnaBridge	171:3a7713b1edbc	1267	__IO uint32_t USBCLKDIV; /!< USB clock divider /
AnnaBridge	171:3a7713b1edbc	1268	__IO uint32_t ADCASYNCCLKDIV; /!< Asynchronous ADC clock divider /
AnnaBridge	171:3a7713b1edbc	1269	__I uint32_t RESERVED8;
AnnaBridge	171:3a7713b1edbc	1270	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
AnnaBridge	171:3a7713b1edbc	1271	__I uint32_t RESERVED9[11];
AnnaBridge	171:3a7713b1edbc	1272	__IO uint32_t FRGCTRL; /!< USART fractional baud rate generator control /
AnnaBridge	171:3a7713b1edbc	1273	__IO uint32_t USBCLKCTRL; /!< USB clock control /
AnnaBridge	171:3a7713b1edbc	1274	__IO uint32_t USBCLKST; /!< USB clock status /
AnnaBridge	171:3a7713b1edbc	1275	__I uint32_t RESERVED10[19];
AnnaBridge	171:3a7713b1edbc	1276	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
AnnaBridge	171:3a7713b1edbc	1277	__I uint32_t RESERVED11;
AnnaBridge	171:3a7713b1edbc	1278	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
AnnaBridge	171:3a7713b1edbc	1279	__I uint32_t RESERVED12;
AnnaBridge	171:3a7713b1edbc	1280	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator control /
AnnaBridge	171:3a7713b1edbc	1281	__I uint32_t RESERVED13;
AnnaBridge	171:3a7713b1edbc	1282	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
AnnaBridge	171:3a7713b1edbc	1283	__I uint32_t SYSPLLSTAT; /!< System PLL status /
AnnaBridge	171:3a7713b1edbc	1284	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
AnnaBridge	171:3a7713b1edbc	1285	__I uint32_t USBPLLSTAT; /!< USB PLL status /
AnnaBridge	171:3a7713b1edbc	1286	__IO uint32_t SCTPLLCTRL; /!< SCT PLL control /
AnnaBridge	171:3a7713b1edbc	1287	__I uint32_t SCTPLLSTAT; /!< SCT PLL status /
AnnaBridge	171:3a7713b1edbc	1288	__I uint32_t RESERVED14[21];
AnnaBridge	171:3a7713b1edbc	1289	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
AnnaBridge	171:3a7713b1edbc	1290	__IO uint32_t PDRUNCFG; /!< Power configuration register /
AnnaBridge	171:3a7713b1edbc	1291	__I uint32_t RESERVED15[3];
AnnaBridge	171:3a7713b1edbc	1292	__IO uint32_t STARTERP0; /!< Start logic 0 wake-up enable register /
AnnaBridge	171:3a7713b1edbc	1293	__IO uint32_t STARTERP1; /!< Start logic 1 wake-up enable register /
AnnaBridge	171:3a7713b1edbc	1294	} LPC_SYSCON_Type;
AnnaBridge	171:3a7713b1edbc	1295
AnnaBridge	171:3a7713b1edbc	1296
AnnaBridge	171:3a7713b1edbc	1297	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1298	/* ================ MRT ================ */
AnnaBridge	171:3a7713b1edbc	1299	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1300
AnnaBridge	171:3a7713b1edbc	1301
AnnaBridge	171:3a7713b1edbc	1302	/**
AnnaBridge	171:3a7713b1edbc	1303	* @brief Multi-Rate Timer (MRT) (MRT)
AnnaBridge	171:3a7713b1edbc	1304	*/
AnnaBridge	171:3a7713b1edbc	1305
AnnaBridge	171:3a7713b1edbc	1306	typedef struct { /!< MRT Structure /
AnnaBridge	171:3a7713b1edbc	1307	__IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
AnnaBridge	171:3a7713b1edbc	1308	the TIMER0 register. */
AnnaBridge	171:3a7713b1edbc	1309	__I uint32_t TIMER0; /!< MRT0 Timer register. This register reads the value of the down-counter. /
AnnaBridge	171:3a7713b1edbc	1310	__IO uint32_t CTRL0; /!< MRT0 Control register. This register controls the MRT0 modes. /
AnnaBridge	171:3a7713b1edbc	1311	__IO uint32_t STAT0; /!< MRT0 Status register. /
AnnaBridge	171:3a7713b1edbc	1312	__IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
AnnaBridge	171:3a7713b1edbc	1313	the TIMER0 register. */
AnnaBridge	171:3a7713b1edbc	1314	__I uint32_t TIMER1; /!< MRT0 Timer register. This register reads the value of the down-counter. /
AnnaBridge	171:3a7713b1edbc	1315	__IO uint32_t CTRL1; /!< MRT0 Control register. This register controls the MRT0 modes. /
AnnaBridge	171:3a7713b1edbc	1316	__IO uint32_t STAT1; /!< MRT0 Status register. /
AnnaBridge	171:3a7713b1edbc	1317	__IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
AnnaBridge	171:3a7713b1edbc	1318	the TIMER0 register. */
AnnaBridge	171:3a7713b1edbc	1319	__I uint32_t TIMER2; /!< MRT0 Timer register. This register reads the value of the down-counter. /
AnnaBridge	171:3a7713b1edbc	1320	__IO uint32_t CTRL2; /!< MRT0 Control register. This register controls the MRT0 modes. /
AnnaBridge	171:3a7713b1edbc	1321	__IO uint32_t STAT2; /!< MRT0 Status register. /
AnnaBridge	171:3a7713b1edbc	1322	__IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
AnnaBridge	171:3a7713b1edbc	1323	the TIMER0 register. */
AnnaBridge	171:3a7713b1edbc	1324	__I uint32_t TIMER3; /!< MRT0 Timer register. This register reads the value of the down-counter. /
AnnaBridge	171:3a7713b1edbc	1325	__IO uint32_t CTRL3; /!< MRT0 Control register. This register controls the MRT0 modes. /
AnnaBridge	171:3a7713b1edbc	1326	__IO uint32_t STAT3; /!< MRT0 Status register. /
AnnaBridge	171:3a7713b1edbc	1327	__I uint32_t RESERVED0[45];
AnnaBridge	171:3a7713b1edbc	1328	__I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
AnnaBridge	171:3a7713b1edbc	1329	first idle channel. */
AnnaBridge	171:3a7713b1edbc	1330	__IO uint32_t IRQ_FLAG; /!< Global interrupt flag register /
AnnaBridge	171:3a7713b1edbc	1331	} LPC_MRT_Type;
AnnaBridge	171:3a7713b1edbc	1332
AnnaBridge	171:3a7713b1edbc	1333
AnnaBridge	171:3a7713b1edbc	1334	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1335	/* ================ PINT ================ */
AnnaBridge	171:3a7713b1edbc	1336	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1337
AnnaBridge	171:3a7713b1edbc	1338
AnnaBridge	171:3a7713b1edbc	1339	/**
AnnaBridge	171:3a7713b1edbc	1340	* @brief Pin interruptand pattern match (PINT) (PINT)
AnnaBridge	171:3a7713b1edbc	1341	*/
AnnaBridge	171:3a7713b1edbc	1342
AnnaBridge	171:3a7713b1edbc	1343	typedef struct { /!< PINT Structure /
AnnaBridge	171:3a7713b1edbc	1344	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
AnnaBridge	171:3a7713b1edbc	1345	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
AnnaBridge	171:3a7713b1edbc	1346	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
AnnaBridge	171:3a7713b1edbc	1347	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
AnnaBridge	171:3a7713b1edbc	1348	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
AnnaBridge	171:3a7713b1edbc	1349	register */
AnnaBridge	171:3a7713b1edbc	1350	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
AnnaBridge	171:3a7713b1edbc	1351	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
AnnaBridge	171:3a7713b1edbc	1352	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
AnnaBridge	171:3a7713b1edbc	1353	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
AnnaBridge	171:3a7713b1edbc	1354	__IO uint32_t IST; /!< Pin interrupt status register /
AnnaBridge	171:3a7713b1edbc	1355	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
AnnaBridge	171:3a7713b1edbc	1356	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
AnnaBridge	171:3a7713b1edbc	1357	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
AnnaBridge	171:3a7713b1edbc	1358	} LPC_PINT_Type;
AnnaBridge	171:3a7713b1edbc	1359
AnnaBridge	171:3a7713b1edbc	1360
AnnaBridge	171:3a7713b1edbc	1361	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1362	/* ================ GINT0 ================ */
AnnaBridge	171:3a7713b1edbc	1363	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1364
AnnaBridge	171:3a7713b1edbc	1365
AnnaBridge	171:3a7713b1edbc	1366	/**
AnnaBridge	171:3a7713b1edbc	1367	* @brief Group interrupt 0/1 (GINT0/1) (GINT0)
AnnaBridge	171:3a7713b1edbc	1368	*/
AnnaBridge	171:3a7713b1edbc	1369
AnnaBridge	171:3a7713b1edbc	1370	typedef struct { /!< GINT0 Structure /
AnnaBridge	171:3a7713b1edbc	1371	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
AnnaBridge	171:3a7713b1edbc	1372	__I uint32_t RESERVED0[7];
AnnaBridge	171:3a7713b1edbc	1373	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
AnnaBridge	171:3a7713b1edbc	1374	__I uint32_t RESERVED1[5];
AnnaBridge	171:3a7713b1edbc	1375	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port 0 enable register /
AnnaBridge	171:3a7713b1edbc	1376	} LPC_GINT0_Type;
AnnaBridge	171:3a7713b1edbc	1377
AnnaBridge	171:3a7713b1edbc	1378
AnnaBridge	171:3a7713b1edbc	1379	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1380	/* ================ RIT ================ */
AnnaBridge	171:3a7713b1edbc	1381	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1382
AnnaBridge	171:3a7713b1edbc	1383
AnnaBridge	171:3a7713b1edbc	1384	/**
AnnaBridge	171:3a7713b1edbc	1385	* @brief Repetitive Interrupt Timer (RIT) (RIT)
AnnaBridge	171:3a7713b1edbc	1386	*/
AnnaBridge	171:3a7713b1edbc	1387
AnnaBridge	171:3a7713b1edbc	1388	typedef struct { /!< RIT Structure /
AnnaBridge	171:3a7713b1edbc	1389	__IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
AnnaBridge	171:3a7713b1edbc	1390	value. */
AnnaBridge	171:3a7713b1edbc	1391	__IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
AnnaBridge	171:3a7713b1edbc	1392	value. A 1 written to any bit will force a compare on the corresponding
AnnaBridge	171:3a7713b1edbc	1393	bit of the counter and compare register. */
AnnaBridge	171:3a7713b1edbc	1394	__IO uint32_t CTRL; /!< Control register. /
AnnaBridge	171:3a7713b1edbc	1395	__IO uint32_t COUNTER; /!< Counter LSB register. 32 LSBs of the counter. /
AnnaBridge	171:3a7713b1edbc	1396	__IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
AnnaBridge	171:3a7713b1edbc	1397	value. */
AnnaBridge	171:3a7713b1edbc	1398	__IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
AnnaBridge	171:3a7713b1edbc	1399	value. A 1 written to any bit will force a compare on the corresponding
AnnaBridge	171:3a7713b1edbc	1400	bit of the counter and compare register. */
AnnaBridge	171:3a7713b1edbc	1401	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	1402	__IO uint32_t COUNTER_H; /!< Counter MSB register. 16 MSBs of the counter. /
AnnaBridge	171:3a7713b1edbc	1403	} LPC_RIT_Type;
AnnaBridge	171:3a7713b1edbc	1404
AnnaBridge	171:3a7713b1edbc	1405
AnnaBridge	171:3a7713b1edbc	1406	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1407	/* ================ SCTIPU ================ */
AnnaBridge	171:3a7713b1edbc	1408	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1409
AnnaBridge	171:3a7713b1edbc	1410
AnnaBridge	171:3a7713b1edbc	1411	/**
AnnaBridge	171:3a7713b1edbc	1412	* @brief SCT Input Processing Unit (IPU) (SCTIPU)
AnnaBridge	171:3a7713b1edbc	1413	*/
AnnaBridge	171:3a7713b1edbc	1414
AnnaBridge	171:3a7713b1edbc	1415	typedef struct { /!< SCTIPU Structure /
AnnaBridge	171:3a7713b1edbc	1416	__IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
AnnaBridge	171:3a7713b1edbc	1417	latch/sample-enable mux selects, and sample overrride bits for
AnnaBridge	171:3a7713b1edbc	1418	the SAMPLE module. */
AnnaBridge	171:3a7713b1edbc	1419	__I uint32_t RESERVED0[7];
AnnaBridge	171:3a7713b1edbc	1420	__IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
AnnaBridge	171:3a7713b1edbc	1421	to ORed Abort Output 0. */
AnnaBridge	171:3a7713b1edbc	1422	__IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
AnnaBridge	171:3a7713b1edbc	1423	input source caused abort output 0. */
AnnaBridge	171:3a7713b1edbc	1424	__I uint32_t RESERVED1[6];
AnnaBridge	171:3a7713b1edbc	1425	__IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
AnnaBridge	171:3a7713b1edbc	1426	to ORed Abort Output 0. */
AnnaBridge	171:3a7713b1edbc	1427	__IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
AnnaBridge	171:3a7713b1edbc	1428	input source caused abort output 0. */
AnnaBridge	171:3a7713b1edbc	1429	__I uint32_t RESERVED2[6];
AnnaBridge	171:3a7713b1edbc	1430	__IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
AnnaBridge	171:3a7713b1edbc	1431	to ORed Abort Output 0. */
AnnaBridge	171:3a7713b1edbc	1432	__IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
AnnaBridge	171:3a7713b1edbc	1433	input source caused abort output 0. */
AnnaBridge	171:3a7713b1edbc	1434	__I uint32_t RESERVED3[6];
AnnaBridge	171:3a7713b1edbc	1435	__IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
AnnaBridge	171:3a7713b1edbc	1436	to ORed Abort Output 0. */
AnnaBridge	171:3a7713b1edbc	1437	__IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
AnnaBridge	171:3a7713b1edbc	1438	input source caused abort output 0. */
AnnaBridge	171:3a7713b1edbc	1439	} LPC_SCTIPU_Type;
AnnaBridge	171:3a7713b1edbc	1440
AnnaBridge	171:3a7713b1edbc	1441
AnnaBridge	171:3a7713b1edbc	1442	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1443	/* ================ FLASHCTRL ================ */
AnnaBridge	171:3a7713b1edbc	1444	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1445
AnnaBridge	171:3a7713b1edbc	1446
AnnaBridge	171:3a7713b1edbc	1447	/**
AnnaBridge	171:3a7713b1edbc	1448	* @brief Flash controller (FLASHCTRL)
AnnaBridge	171:3a7713b1edbc	1449	*/
AnnaBridge	171:3a7713b1edbc	1450
AnnaBridge	171:3a7713b1edbc	1451	typedef struct { /!< FLASHCTRL Structure /
AnnaBridge	171:3a7713b1edbc	1452	__I uint32_t RESERVED0[8];
AnnaBridge	171:3a7713b1edbc	1453	__IO uint32_t FMSSTART; /!< Signature start address register /
AnnaBridge	171:3a7713b1edbc	1454	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
AnnaBridge	171:3a7713b1edbc	1455	__I uint32_t RESERVED1;
AnnaBridge	171:3a7713b1edbc	1456	__I uint32_t FMSW0; /!< Signature word /
AnnaBridge	171:3a7713b1edbc	1457	} LPC_FLASHCTRL_Type;
AnnaBridge	171:3a7713b1edbc	1458
AnnaBridge	171:3a7713b1edbc	1459
AnnaBridge	171:3a7713b1edbc	1460	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1461	/* ================ C_CAN0 ================ */
AnnaBridge	171:3a7713b1edbc	1462	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1463
AnnaBridge	171:3a7713b1edbc	1464
AnnaBridge	171:3a7713b1edbc	1465	/**
AnnaBridge	171:3a7713b1edbc	1466	* @brief Controller Area Network C_CAN0 (C_CAN0)
AnnaBridge	171:3a7713b1edbc	1467	*/
AnnaBridge	171:3a7713b1edbc	1468
AnnaBridge	171:3a7713b1edbc	1469	typedef struct { /!< C_CAN0 Structure /
AnnaBridge	171:3a7713b1edbc	1470	__IO uint32_t CANCNTL; /!< CAN control /
AnnaBridge	171:3a7713b1edbc	1471	__IO uint32_t CANSTAT; /!< Status register /
AnnaBridge	171:3a7713b1edbc	1472	__I uint32_t CANEC; /!< Error counter /
AnnaBridge	171:3a7713b1edbc	1473	__IO uint32_t CANBT; /!< Bit timing register /
AnnaBridge	171:3a7713b1edbc	1474	__I uint32_t CANINT; /!< Interrupt register /
AnnaBridge	171:3a7713b1edbc	1475	__IO uint32_t CANTEST; /!< Test register /
AnnaBridge	171:3a7713b1edbc	1476	__IO uint32_t CANBRPE; /!< Baud rate prescaler extension register /
AnnaBridge	171:3a7713b1edbc	1477	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	1478	__IO uint32_t CANIF1_CMDREQ; /!< Message interface 1 command request /
AnnaBridge	171:3a7713b1edbc	1479
AnnaBridge	171:3a7713b1edbc	1480	union {
AnnaBridge	171:3a7713b1edbc	1481	__IO uint32_t CANIF1_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
AnnaBridge	171:3a7713b1edbc	1482	__IO uint32_t CANIF1_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
AnnaBridge	171:3a7713b1edbc	1483	};
AnnaBridge	171:3a7713b1edbc	1484	__IO uint32_t CANIF1_MSK1; /!< Message interface 1 mask 1 /
AnnaBridge	171:3a7713b1edbc	1485	__IO uint32_t CANIF1_MSK2; /!< Message interface 1 mask 2 /
AnnaBridge	171:3a7713b1edbc	1486	__IO uint32_t CANIF1_ARB1; /!< Message interface 1 arbitration 1 /
AnnaBridge	171:3a7713b1edbc	1487	__IO uint32_t CANIF1_ARB2; /!< Message interface 1 arbitration 2 /
AnnaBridge	171:3a7713b1edbc	1488	__IO uint32_t CANIF1_MCTRL; /!< Message interface 1 message control /
AnnaBridge	171:3a7713b1edbc	1489	__IO uint32_t CANIF1_DA1; /!< Message interface 1 data A1 /
AnnaBridge	171:3a7713b1edbc	1490	__IO uint32_t CANIF1_DA2; /!< Message interface 1 data A2 /
AnnaBridge	171:3a7713b1edbc	1491	__IO uint32_t CANIF1_DB1; /!< Message interface 1 data B1 /
AnnaBridge	171:3a7713b1edbc	1492	__IO uint32_t CANIF1_DB2; /!< Message interface 1 data B2 /
AnnaBridge	171:3a7713b1edbc	1493	__I uint32_t RESERVED1[13];
AnnaBridge	171:3a7713b1edbc	1494	__IO uint32_t CANIF2_CMDREQ; /!< Message interface 1 command request /
AnnaBridge	171:3a7713b1edbc	1495
AnnaBridge	171:3a7713b1edbc	1496	union {
AnnaBridge	171:3a7713b1edbc	1497	__IO uint32_t CANIF2_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
AnnaBridge	171:3a7713b1edbc	1498	__IO uint32_t CANIF2_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
AnnaBridge	171:3a7713b1edbc	1499	};
AnnaBridge	171:3a7713b1edbc	1500	__IO uint32_t CANIF2_MSK1; /!< Message interface 1 mask 1 /
AnnaBridge	171:3a7713b1edbc	1501	__IO uint32_t CANIF2_MSK2; /!< Message interface 1 mask 2 /
AnnaBridge	171:3a7713b1edbc	1502	__IO uint32_t CANIF2_ARB1; /!< Message interface 1 arbitration 1 /
AnnaBridge	171:3a7713b1edbc	1503	__IO uint32_t CANIF2_ARB2; /!< Message interface 1 arbitration 2 /
AnnaBridge	171:3a7713b1edbc	1504	__IO uint32_t CANIF2_MCTRL; /!< Message interface 1 message control /
AnnaBridge	171:3a7713b1edbc	1505	__IO uint32_t CANIF2_DA1; /!< Message interface 2 data A1 /
AnnaBridge	171:3a7713b1edbc	1506	__IO uint32_t CANIF2_DA2; /!< Message interface 2 data A2 /
AnnaBridge	171:3a7713b1edbc	1507	__IO uint32_t CANIF2_DB1; /!< Message interface 2 data B1 /
AnnaBridge	171:3a7713b1edbc	1508	__IO uint32_t CANIF2_DB2; /!< Message interface 2 data B2 /
AnnaBridge	171:3a7713b1edbc	1509	__I uint32_t RESERVED2[21];
AnnaBridge	171:3a7713b1edbc	1510	__I uint32_t CANTXREQ1; /!< Transmission request 1 /
AnnaBridge	171:3a7713b1edbc	1511	__I uint32_t CANTXREQ2; /!< Transmission request 2 /
AnnaBridge	171:3a7713b1edbc	1512	__I uint32_t RESERVED3[6];
AnnaBridge	171:3a7713b1edbc	1513	__I uint32_t CANND1; /!< New data 1 /
AnnaBridge	171:3a7713b1edbc	1514	__I uint32_t CANND2; /!< New data 2 /
AnnaBridge	171:3a7713b1edbc	1515	__I uint32_t RESERVED4[6];
AnnaBridge	171:3a7713b1edbc	1516	__I uint32_t CANIR1; /!< Interrupt pending 1 /
AnnaBridge	171:3a7713b1edbc	1517	__I uint32_t CANIR2; /!< Interrupt pending 2 /
AnnaBridge	171:3a7713b1edbc	1518	__I uint32_t RESERVED5[6];
AnnaBridge	171:3a7713b1edbc	1519	__I uint32_t CANMSGV1; /!< Message valid 1 /
AnnaBridge	171:3a7713b1edbc	1520	__I uint32_t CANMSGV2; /!< Message valid 2 /
AnnaBridge	171:3a7713b1edbc	1521	__I uint32_t RESERVED6[6];
AnnaBridge	171:3a7713b1edbc	1522	__IO uint32_t CANCLKDIV; /!< Can clock divider register /
AnnaBridge	171:3a7713b1edbc	1523	} LPC_C_CAN0_Type;
AnnaBridge	171:3a7713b1edbc	1524
AnnaBridge	171:3a7713b1edbc	1525
AnnaBridge	171:3a7713b1edbc	1526	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1527	/* ================ IOCON ================ */
AnnaBridge	171:3a7713b1edbc	1528	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1529
AnnaBridge	171:3a7713b1edbc	1530
AnnaBridge	171:3a7713b1edbc	1531	/**
AnnaBridge	171:3a7713b1edbc	1532	* @brief I/O pin configuration (IOCON) (IOCON)
AnnaBridge	171:3a7713b1edbc	1533	*/
AnnaBridge	171:3a7713b1edbc	1534
AnnaBridge	171:3a7713b1edbc	1535	typedef struct { /!< IOCON Structure /
AnnaBridge	171:3a7713b1edbc	1536	__IO uint32_t PIO0_0; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1537	__IO uint32_t PIO0_1; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1538	__IO uint32_t PIO0_2; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1539	__IO uint32_t PIO0_3; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1540	__IO uint32_t PIO0_4; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1541	__IO uint32_t PIO0_5; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1542	__IO uint32_t PIO0_6; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1543	__IO uint32_t PIO0_7; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1544	__IO uint32_t PIO0_8; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1545	__IO uint32_t PIO0_9; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1546	__IO uint32_t PIO0_10; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1547	__IO uint32_t PIO0_11; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1548	__IO uint32_t PIO0_12; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1549	__IO uint32_t PIO0_13; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1550	__IO uint32_t PIO0_14; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1551	__IO uint32_t PIO0_15; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1552	__IO uint32_t PIO0_16; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1553	__IO uint32_t PIO0_17; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1554	__IO uint32_t PIO0_18; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1555	__IO uint32_t PIO0_19; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1556	__IO uint32_t PIO0_20; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1557	__IO uint32_t PIO0_21; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
AnnaBridge	171:3a7713b1edbc	1558	__IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
AnnaBridge	171:3a7713b1edbc	1559	the I2C-bus SCL function. */
AnnaBridge	171:3a7713b1edbc	1560	__IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
AnnaBridge	171:3a7713b1edbc	1561	the I2C-bus SCL function. */
AnnaBridge	171:3a7713b1edbc	1562	__IO uint32_t PIO0_24; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
AnnaBridge	171:3a7713b1edbc	1563	__IO uint32_t PIO0_25; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
AnnaBridge	171:3a7713b1edbc	1564	__IO uint32_t PIO0_26; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
AnnaBridge	171:3a7713b1edbc	1565	__IO uint32_t PIO0_27; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
AnnaBridge	171:3a7713b1edbc	1566	__IO uint32_t PIO0_28; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
AnnaBridge	171:3a7713b1edbc	1567	__IO uint32_t PIO0_29; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
AnnaBridge	171:3a7713b1edbc	1568	__IO uint32_t PIO0_30; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
AnnaBridge	171:3a7713b1edbc	1569	__IO uint32_t PIO0_31; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
AnnaBridge	171:3a7713b1edbc	1570	__IO uint32_t PIO1_0; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1571	__IO uint32_t PIO1_1; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1572	__IO uint32_t PIO1_2; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1573	__IO uint32_t PIO1_3; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1574	__IO uint32_t PIO1_4; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1575	__IO uint32_t PIO1_5; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1576	__IO uint32_t PIO1_6; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1577	__IO uint32_t PIO1_7; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1578	__IO uint32_t PIO1_8; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1579	__IO uint32_t PIO1_9; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1580	__IO uint32_t PIO1_10; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1581	__IO uint32_t PIO1_11; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1582	__IO uint32_t PIO1_12; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1583	__IO uint32_t PIO1_13; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1584	__IO uint32_t PIO1_14; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1585	__IO uint32_t PIO1_15; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1586	__IO uint32_t PIO1_16; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1587	__IO uint32_t PIO1_17; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1588	__IO uint32_t PIO1_18; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1589	__IO uint32_t PIO1_19; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1590	__IO uint32_t PIO1_20; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1591	__IO uint32_t PIO1_21; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1592	__IO uint32_t PIO1_22; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1593	__IO uint32_t PIO1_23; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1594	__IO uint32_t PIO1_24; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1595	__IO uint32_t PIO1_25; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1596	__IO uint32_t PIO1_26; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1597	__IO uint32_t PIO1_27; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1598	__IO uint32_t PIO1_28; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1599	__IO uint32_t PIO1_29; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1600	__IO uint32_t PIO1_30; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1601	__IO uint32_t PIO1_31; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
AnnaBridge	171:3a7713b1edbc	1602	__IO uint32_t PIO2_0; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1603	__IO uint32_t PIO2_1; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1604	__IO uint32_t PIO2_2; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1605	__IO uint32_t PIO2_3; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1606	__IO uint32_t PIO2_4; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1607	__IO uint32_t PIO2_5; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1608	__IO uint32_t PIO2_6; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1609	__IO uint32_t PIO2_7; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1610	__IO uint32_t PIO2_8; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1611	__IO uint32_t PIO2_9; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1612	__IO uint32_t PIO2_10; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1613	__IO uint32_t PIO2_11; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
AnnaBridge	171:3a7713b1edbc	1614	} LPC_IOCON_Type;
AnnaBridge	171:3a7713b1edbc	1615
AnnaBridge	171:3a7713b1edbc	1616
AnnaBridge	171:3a7713b1edbc	1617	/* -------------------- End of section using anonymous unions ------------------- */
AnnaBridge	171:3a7713b1edbc	1618	#if defined(__CC_ARM)
AnnaBridge	171:3a7713b1edbc	1619	#pragma pop
AnnaBridge	171:3a7713b1edbc	1620	#elif defined(__ICCARM__)
AnnaBridge	171:3a7713b1edbc	1621	/* leave anonymous unions enabled */
AnnaBridge	171:3a7713b1edbc	1622	#elif defined(__GNUC__)
AnnaBridge	171:3a7713b1edbc	1623	/* anonymous unions are enabled by default */
AnnaBridge	171:3a7713b1edbc	1624	#elif defined(__TMS470__)
AnnaBridge	171:3a7713b1edbc	1625	/* anonymous unions are enabled by default */
AnnaBridge	171:3a7713b1edbc	1626	#elif defined(__TASKING__)
AnnaBridge	171:3a7713b1edbc	1627	#pragma warning restore
AnnaBridge	171:3a7713b1edbc	1628	#else
AnnaBridge	171:3a7713b1edbc	1629	#warning Not supported compiler type
AnnaBridge	171:3a7713b1edbc	1630	#endif
AnnaBridge	171:3a7713b1edbc	1631
AnnaBridge	171:3a7713b1edbc	1632
AnnaBridge	171:3a7713b1edbc	1633
AnnaBridge	171:3a7713b1edbc	1634
AnnaBridge	171:3a7713b1edbc	1635	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1636	/* ================ Peripheral memory map ================ */
AnnaBridge	171:3a7713b1edbc	1637	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1638
AnnaBridge	171:3a7713b1edbc	1639	#define LPC_GPIO_PORT_BASE 0x1C000000UL
AnnaBridge	171:3a7713b1edbc	1640	#define LPC_DMA_BASE 0x1C004000UL
AnnaBridge	171:3a7713b1edbc	1641	#define LPC_USB_BASE 0x1C00C000UL
AnnaBridge	171:3a7713b1edbc	1642	#define LPC_CRC_BASE 0x1C010000UL
AnnaBridge	171:3a7713b1edbc	1643	#define LPC_SCT0_BASE 0x1C018000UL
AnnaBridge	171:3a7713b1edbc	1644	#define LPC_SCT1_BASE 0x1C01C000UL
AnnaBridge	171:3a7713b1edbc	1645	#define LPC_SCT2_BASE 0x1C020000UL
AnnaBridge	171:3a7713b1edbc	1646	#define LPC_SCT3_BASE 0x1C024000UL
AnnaBridge	171:3a7713b1edbc	1647	#define LPC_ADC0_BASE 0x40000000UL
AnnaBridge	171:3a7713b1edbc	1648	#define LPC_DAC_BASE 0x40004000UL
AnnaBridge	171:3a7713b1edbc	1649	#define LPC_ACMP_BASE 0x40008000UL
AnnaBridge	171:3a7713b1edbc	1650	#define LPC_INMUX_BASE 0x40014000UL
AnnaBridge	171:3a7713b1edbc	1651	#define LPC_RTC_BASE 0x40028000UL
AnnaBridge	171:3a7713b1edbc	1652	#define LPC_WWDT_BASE 0x4002C000UL
AnnaBridge	171:3a7713b1edbc	1653	#define LPC_SWM_BASE 0x40038000UL
AnnaBridge	171:3a7713b1edbc	1654	#define LPC_PMU_BASE 0x4003C000UL
AnnaBridge	171:3a7713b1edbc	1655	#define LPC_USART0_BASE 0x40040000UL
AnnaBridge	171:3a7713b1edbc	1656	#define LPC_USART1_BASE 0x40044000UL
AnnaBridge	171:3a7713b1edbc	1657	#define LPC_SPI0_BASE 0x40048000UL
AnnaBridge	171:3a7713b1edbc	1658	#define LPC_SPI1_BASE 0x4004C000UL
AnnaBridge	171:3a7713b1edbc	1659	#define LPC_I2C0_BASE 0x40050000UL
AnnaBridge	171:3a7713b1edbc	1660	#define LPC_QEI_BASE 0x40058000UL
AnnaBridge	171:3a7713b1edbc	1661	#define LPC_SYSCON_BASE 0x40074000UL
AnnaBridge	171:3a7713b1edbc	1662	#define LPC_ADC1_BASE 0x40080000UL
AnnaBridge	171:3a7713b1edbc	1663	#define LPC_MRT_BASE 0x400A0000UL
AnnaBridge	171:3a7713b1edbc	1664	#define LPC_PINT_BASE 0x400A4000UL
AnnaBridge	171:3a7713b1edbc	1665	#define LPC_GINT0_BASE 0x400A8000UL
AnnaBridge	171:3a7713b1edbc	1666	#define LPC_GINT1_BASE 0x400AC000UL
AnnaBridge	171:3a7713b1edbc	1667	#define LPC_RIT_BASE 0x400B4000UL
AnnaBridge	171:3a7713b1edbc	1668	#define LPC_SCTIPU_BASE 0x400B8000UL
AnnaBridge	171:3a7713b1edbc	1669	#define LPC_FLASHCTRL_BASE 0x400BC000UL
AnnaBridge	171:3a7713b1edbc	1670	#define LPC_USART2_BASE 0x400C0000UL
AnnaBridge	171:3a7713b1edbc	1671	#define LPC_C_CAN0_BASE 0x400F0000UL
AnnaBridge	171:3a7713b1edbc	1672	#define LPC_IOCON_BASE 0x400F8000UL
AnnaBridge	171:3a7713b1edbc	1673
AnnaBridge	171:3a7713b1edbc	1674
AnnaBridge	171:3a7713b1edbc	1675	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1676	/* ================ Peripheral declaration ================ */
AnnaBridge	171:3a7713b1edbc	1677	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	1678
AnnaBridge	171:3a7713b1edbc	1679	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
AnnaBridge	171:3a7713b1edbc	1680	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
AnnaBridge	171:3a7713b1edbc	1681	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
AnnaBridge	171:3a7713b1edbc	1682	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
AnnaBridge	171:3a7713b1edbc	1683	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
AnnaBridge	171:3a7713b1edbc	1684	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
AnnaBridge	171:3a7713b1edbc	1685	#define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
AnnaBridge	171:3a7713b1edbc	1686	#define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
AnnaBridge	171:3a7713b1edbc	1687	#define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
AnnaBridge	171:3a7713b1edbc	1688	#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
AnnaBridge	171:3a7713b1edbc	1689	#define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
AnnaBridge	171:3a7713b1edbc	1690	#define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
AnnaBridge	171:3a7713b1edbc	1691	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
AnnaBridge	171:3a7713b1edbc	1692	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
AnnaBridge	171:3a7713b1edbc	1693	#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
AnnaBridge	171:3a7713b1edbc	1694	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
AnnaBridge	171:3a7713b1edbc	1695	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
AnnaBridge	171:3a7713b1edbc	1696	#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
AnnaBridge	171:3a7713b1edbc	1697	#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
AnnaBridge	171:3a7713b1edbc	1698	#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
AnnaBridge	171:3a7713b1edbc	1699	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
AnnaBridge	171:3a7713b1edbc	1700	#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
AnnaBridge	171:3a7713b1edbc	1701	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
AnnaBridge	171:3a7713b1edbc	1702	#define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
AnnaBridge	171:3a7713b1edbc	1703	#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
AnnaBridge	171:3a7713b1edbc	1704	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
AnnaBridge	171:3a7713b1edbc	1705	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
AnnaBridge	171:3a7713b1edbc	1706	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
AnnaBridge	171:3a7713b1edbc	1707	#define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
AnnaBridge	171:3a7713b1edbc	1708	#define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
AnnaBridge	171:3a7713b1edbc	1709	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
AnnaBridge	171:3a7713b1edbc	1710	#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
AnnaBridge	171:3a7713b1edbc	1711	#define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
AnnaBridge	171:3a7713b1edbc	1712	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
AnnaBridge	171:3a7713b1edbc	1713
AnnaBridge	171:3a7713b1edbc	1714
AnnaBridge	171:3a7713b1edbc	1715	/** @} / / End of group Device_Peripheral_Registers */
AnnaBridge	171:3a7713b1edbc	1716	/** @} / / End of group LPC15xx */
AnnaBridge	171:3a7713b1edbc	1717	/** @} / / End of group (null) */
AnnaBridge	171:3a7713b1edbc	1718
AnnaBridge	171:3a7713b1edbc	1719	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1720	}
AnnaBridge	171:3a7713b1edbc	1721	#endif
AnnaBridge	171:3a7713b1edbc	1722
AnnaBridge	171:3a7713b1edbc	1723
AnnaBridge	171:3a7713b1edbc	1724	#endif /* LPC15XX_H */
AnnaBridge	171:3a7713b1edbc	1725