The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_KW41Z/TOOLCHAIN_IAR/MKW41Z4_features.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /* |
AnnaBridge | 171:3a7713b1edbc | 2 | ** ################################################################### |
AnnaBridge | 171:3a7713b1edbc | 3 | ** Version: rev. 1.0, 2015-09-23 |
AnnaBridge | 171:3a7713b1edbc | 4 | ** Build: b160720 |
AnnaBridge | 171:3a7713b1edbc | 5 | ** |
AnnaBridge | 171:3a7713b1edbc | 6 | ** Abstract: |
AnnaBridge | 171:3a7713b1edbc | 7 | ** Chip specific module features. |
AnnaBridge | 171:3a7713b1edbc | 8 | ** |
AnnaBridge | 171:3a7713b1edbc | 9 | ** Copyright (c) 2016 Freescale Semiconductor, Inc. |
AnnaBridge | 171:3a7713b1edbc | 10 | ** All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 11 | ** |
AnnaBridge | 171:3a7713b1edbc | 12 | ** Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 13 | ** are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | ** |
AnnaBridge | 171:3a7713b1edbc | 15 | ** o Redistributions of source code must retain the above copyright notice, this list |
AnnaBridge | 171:3a7713b1edbc | 16 | ** of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | ** |
AnnaBridge | 171:3a7713b1edbc | 18 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
AnnaBridge | 171:3a7713b1edbc | 19 | ** list of conditions and the following disclaimer in the documentation and/or |
AnnaBridge | 171:3a7713b1edbc | 20 | ** other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | ** |
AnnaBridge | 171:3a7713b1edbc | 22 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
AnnaBridge | 171:3a7713b1edbc | 23 | ** contributors may be used to endorse or promote products derived from this |
AnnaBridge | 171:3a7713b1edbc | 24 | ** software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 25 | ** |
AnnaBridge | 171:3a7713b1edbc | 26 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
AnnaBridge | 171:3a7713b1edbc | 27 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 28 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 29 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 30 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
AnnaBridge | 171:3a7713b1edbc | 31 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
AnnaBridge | 171:3a7713b1edbc | 32 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
AnnaBridge | 171:3a7713b1edbc | 33 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
AnnaBridge | 171:3a7713b1edbc | 34 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
AnnaBridge | 171:3a7713b1edbc | 35 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 36 | ** |
AnnaBridge | 171:3a7713b1edbc | 37 | ** http: www.freescale.com |
AnnaBridge | 171:3a7713b1edbc | 38 | ** mail: support@freescale.com |
AnnaBridge | 171:3a7713b1edbc | 39 | ** |
AnnaBridge | 171:3a7713b1edbc | 40 | ** Revisions: |
AnnaBridge | 171:3a7713b1edbc | 41 | ** - rev. 1.0 (2015-09-23) |
AnnaBridge | 171:3a7713b1edbc | 42 | ** Initial version. |
AnnaBridge | 171:3a7713b1edbc | 43 | ** |
AnnaBridge | 171:3a7713b1edbc | 44 | ** ################################################################### |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _MKW41Z4_FEATURES_H_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _MKW41Z4_FEATURES_H_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* SOC module features */ |
AnnaBridge | 171:3a7713b1edbc | 51 | |
AnnaBridge | 171:3a7713b1edbc | 52 | /* @brief ACMP availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 53 | #define FSL_FEATURE_SOC_ACMP_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 54 | /* @brief ADC16 availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 55 | #define FSL_FEATURE_SOC_ADC16_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 56 | /* @brief ADC12 availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #define FSL_FEATURE_SOC_ADC12_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 58 | /* @brief AFE availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 59 | #define FSL_FEATURE_SOC_AFE_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 60 | /* @brief AIPS availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 61 | #define FSL_FEATURE_SOC_AIPS_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 62 | /* @brief AOI availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 63 | #define FSL_FEATURE_SOC_AOI_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 64 | /* @brief AXBS availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 65 | #define FSL_FEATURE_SOC_AXBS_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 66 | /* @brief ASMC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 67 | #define FSL_FEATURE_SOC_ASMC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 68 | /* @brief CADC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define FSL_FEATURE_SOC_CADC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 70 | /* @brief FLEXCAN availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 72 | /* @brief MMCAU availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define FSL_FEATURE_SOC_MMCAU_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 74 | /* @brief CMP availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #define FSL_FEATURE_SOC_CMP_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 76 | /* @brief CMT availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 77 | #define FSL_FEATURE_SOC_CMT_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 78 | /* @brief CNC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define FSL_FEATURE_SOC_CNC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 80 | /* @brief CRC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #define FSL_FEATURE_SOC_CRC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 82 | /* @brief DAC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define FSL_FEATURE_SOC_DAC_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 84 | /* @brief DAC32 availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define FSL_FEATURE_SOC_DAC32_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 86 | /* @brief DCDC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 87 | #define FSL_FEATURE_SOC_DCDC_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 88 | /* @brief DDR availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define FSL_FEATURE_SOC_DDR_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 90 | /* @brief DMA availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define FSL_FEATURE_SOC_DMA_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 92 | /* @brief EDMA availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 93 | #define FSL_FEATURE_SOC_EDMA_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 94 | /* @brief DMAMUX availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 95 | #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 96 | /* @brief DRY availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #define FSL_FEATURE_SOC_DRY_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 98 | /* @brief DSPI availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 99 | #define FSL_FEATURE_SOC_DSPI_COUNT (2) |
AnnaBridge | 171:3a7713b1edbc | 100 | /* @brief EMVSIM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 101 | #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 102 | /* @brief ENC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 103 | #define FSL_FEATURE_SOC_ENC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 104 | /* @brief ENET availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 105 | #define FSL_FEATURE_SOC_ENET_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 106 | /* @brief EWM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 107 | #define FSL_FEATURE_SOC_EWM_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 108 | /* @brief FB availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 109 | #define FSL_FEATURE_SOC_FB_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 110 | /* @brief FGPIO availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #define FSL_FEATURE_SOC_FGPIO_COUNT (3) |
AnnaBridge | 171:3a7713b1edbc | 112 | /* @brief FLEXIO availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 113 | #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 114 | /* @brief FMC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 115 | #define FSL_FEATURE_SOC_FMC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 116 | /* @brief FSKDT availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 117 | #define FSL_FEATURE_SOC_FSKDT_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 118 | /* @brief FTFA availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 119 | #define FSL_FEATURE_SOC_FTFA_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 120 | /* @brief FTFE availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 121 | #define FSL_FEATURE_SOC_FTFE_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 122 | /* @brief FTFL availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 123 | #define FSL_FEATURE_SOC_FTFL_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 124 | /* @brief FTM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 125 | #define FSL_FEATURE_SOC_FTM_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 126 | /* @brief FTMRA availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 127 | #define FSL_FEATURE_SOC_FTMRA_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 128 | /* @brief FTMRE availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 129 | #define FSL_FEATURE_SOC_FTMRE_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 130 | /* @brief FTMRH availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #define FSL_FEATURE_SOC_FTMRH_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 132 | /* @brief GPIO availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #define FSL_FEATURE_SOC_GPIO_COUNT (3) |
AnnaBridge | 171:3a7713b1edbc | 134 | /* @brief HSADC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 135 | #define FSL_FEATURE_SOC_HSADC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 136 | /* @brief I2C availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 137 | #define FSL_FEATURE_SOC_I2C_COUNT (2) |
AnnaBridge | 171:3a7713b1edbc | 138 | /* @brief I2S availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define FSL_FEATURE_SOC_I2S_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 140 | /* @brief ICS availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define FSL_FEATURE_SOC_ICS_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 142 | /* @brief INTMUX availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #define FSL_FEATURE_SOC_INTMUX_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 144 | /* @brief IRQ availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define FSL_FEATURE_SOC_IRQ_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 146 | /* @brief KBI availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 147 | #define FSL_FEATURE_SOC_KBI_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 148 | /* @brief SLCD availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 149 | #define FSL_FEATURE_SOC_SLCD_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 150 | /* @brief LCDC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 151 | #define FSL_FEATURE_SOC_LCDC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 152 | /* @brief LDO availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #define FSL_FEATURE_SOC_LDO_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 154 | /* @brief LLWU availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define FSL_FEATURE_SOC_LLWU_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 156 | /* @brief LMEM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 157 | #define FSL_FEATURE_SOC_LMEM_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 158 | /* @brief LPI2C availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 159 | #define FSL_FEATURE_SOC_LPI2C_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 160 | /* @brief LPIT availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #define FSL_FEATURE_SOC_LPIT_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 162 | /* @brief LPSCI availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 163 | #define FSL_FEATURE_SOC_LPSCI_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 164 | /* @brief LPSPI availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 165 | #define FSL_FEATURE_SOC_LPSPI_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 166 | /* @brief LPTMR availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 167 | #define FSL_FEATURE_SOC_LPTMR_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 168 | /* @brief LPTPM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 169 | #define FSL_FEATURE_SOC_LPTPM_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 170 | /* @brief LPUART availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 171 | #define FSL_FEATURE_SOC_LPUART_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 172 | /* @brief LTC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 173 | #define FSL_FEATURE_SOC_LTC_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 174 | /* @brief MC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 175 | #define FSL_FEATURE_SOC_MC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 176 | /* @brief MCG availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 177 | #define FSL_FEATURE_SOC_MCG_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 178 | /* @brief MCGLITE availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 179 | #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 180 | /* @brief MCM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 181 | #define FSL_FEATURE_SOC_MCM_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 182 | /* @brief MMAU availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 183 | #define FSL_FEATURE_SOC_MMAU_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 184 | /* @brief MMDVSQ availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 185 | #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 186 | /* @brief MPU availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 187 | #define FSL_FEATURE_SOC_MPU_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 188 | /* @brief MSCAN availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 189 | #define FSL_FEATURE_SOC_MSCAN_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 190 | /* @brief MSCM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 191 | #define FSL_FEATURE_SOC_MSCM_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 192 | /* @brief MTB availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #define FSL_FEATURE_SOC_MTB_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 194 | /* @brief MTBDWT availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 196 | /* @brief MU availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 197 | #define FSL_FEATURE_SOC_MU_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 198 | /* @brief NFC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define FSL_FEATURE_SOC_NFC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 200 | /* @brief OPAMP availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 201 | #define FSL_FEATURE_SOC_OPAMP_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 202 | /* @brief OSC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #define FSL_FEATURE_SOC_OSC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 204 | /* @brief OSC32 availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define FSL_FEATURE_SOC_OSC32_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 206 | /* @brief OTFAD availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define FSL_FEATURE_SOC_OTFAD_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 208 | /* @brief PDB availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 209 | #define FSL_FEATURE_SOC_PDB_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 210 | /* @brief PCC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 211 | #define FSL_FEATURE_SOC_PCC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 212 | /* @brief PGA availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #define FSL_FEATURE_SOC_PGA_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 214 | /* @brief PIT availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 215 | #define FSL_FEATURE_SOC_PIT_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 216 | /* @brief PMC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 217 | #define FSL_FEATURE_SOC_PMC_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 218 | /* @brief PORT availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 219 | #define FSL_FEATURE_SOC_PORT_COUNT (3) |
AnnaBridge | 171:3a7713b1edbc | 220 | /* @brief PWM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 221 | #define FSL_FEATURE_SOC_PWM_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 222 | /* @brief PWT availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 223 | #define FSL_FEATURE_SOC_PWT_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 224 | /* @brief QuadSPI availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 225 | #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 226 | /* @brief RCM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 227 | #define FSL_FEATURE_SOC_RCM_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 228 | /* @brief RFSYS availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 229 | #define FSL_FEATURE_SOC_RFSYS_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 230 | /* @brief RFVBAT availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define FSL_FEATURE_SOC_RFVBAT_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 232 | /* @brief RNG availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 233 | #define FSL_FEATURE_SOC_RNG_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 234 | /* @brief RNGB availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define FSL_FEATURE_SOC_RNGB_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 236 | /* @brief ROM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 237 | #define FSL_FEATURE_SOC_ROM_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 238 | /* @brief RSIM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 239 | #define FSL_FEATURE_SOC_RSIM_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 240 | /* @brief RTC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 241 | #define FSL_FEATURE_SOC_RTC_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 242 | /* @brief SCG availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 243 | #define FSL_FEATURE_SOC_SCG_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 244 | /* @brief SCI availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 245 | #define FSL_FEATURE_SOC_SCI_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 246 | /* @brief SDHC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define FSL_FEATURE_SOC_SDHC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 248 | /* @brief SDRAM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #define FSL_FEATURE_SOC_SDRAM_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 250 | /* @brief SEMA42 availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #define FSL_FEATURE_SOC_SEMA42_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 252 | /* @brief SIM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #define FSL_FEATURE_SOC_SIM_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 254 | /* @brief SMC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 255 | #define FSL_FEATURE_SOC_SMC_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 256 | /* @brief SPI availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 257 | #define FSL_FEATURE_SOC_SPI_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 258 | /* @brief TMR availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 259 | #define FSL_FEATURE_SOC_TMR_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 260 | /* @brief TPM availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 261 | #define FSL_FEATURE_SOC_TPM_COUNT (3) |
AnnaBridge | 171:3a7713b1edbc | 262 | /* @brief TRGMUX availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 263 | #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 264 | /* @brief TRIAMP availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 265 | #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 266 | /* @brief TRNG availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define FSL_FEATURE_SOC_TRNG_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 268 | /* @brief TSI availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 269 | #define FSL_FEATURE_SOC_TSI_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 270 | /* @brief TSTMR availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #define FSL_FEATURE_SOC_TSTMR_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 272 | /* @brief UART availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 273 | #define FSL_FEATURE_SOC_UART_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 274 | /* @brief USB availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 275 | #define FSL_FEATURE_SOC_USB_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 276 | /* @brief USBDCD availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #define FSL_FEATURE_SOC_USBDCD_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 278 | /* @brief USBHSDCD availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 279 | #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 280 | /* @brief USBPHY availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 281 | #define FSL_FEATURE_SOC_USBPHY_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 282 | /* @brief VREF availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #define FSL_FEATURE_SOC_VREF_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 284 | /* @brief WDOG availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define FSL_FEATURE_SOC_WDOG_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 286 | /* @brief XBAR availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 287 | #define FSL_FEATURE_SOC_XBAR_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 288 | /* @brief XBARA availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 289 | #define FSL_FEATURE_SOC_XBARA_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 290 | /* @brief XBARB availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 291 | #define FSL_FEATURE_SOC_XBARB_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 292 | /* @brief XCVR availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 293 | #define FSL_FEATURE_SOC_XCVR_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 294 | /* @brief XRDC availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 295 | #define FSL_FEATURE_SOC_XRDC_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 296 | /* @brief ZLL availability on the SoC. */ |
AnnaBridge | 171:3a7713b1edbc | 297 | #define FSL_FEATURE_SOC_ZLL_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 298 | |
AnnaBridge | 171:3a7713b1edbc | 299 | /* ADC16 module features */ |
AnnaBridge | 171:3a7713b1edbc | 300 | |
AnnaBridge | 171:3a7713b1edbc | 301 | /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ |
AnnaBridge | 171:3a7713b1edbc | 302 | #define FSL_FEATURE_ADC16_HAS_PGA (0) |
AnnaBridge | 171:3a7713b1edbc | 303 | /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ |
AnnaBridge | 171:3a7713b1edbc | 304 | #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) |
AnnaBridge | 171:3a7713b1edbc | 305 | /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ |
AnnaBridge | 171:3a7713b1edbc | 306 | #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 307 | /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ |
AnnaBridge | 171:3a7713b1edbc | 308 | #define FSL_FEATURE_ADC16_HAS_DMA (1) |
AnnaBridge | 171:3a7713b1edbc | 309 | /* @brief Has differential mode (bitfield SC1x[DIFF]). */ |
AnnaBridge | 171:3a7713b1edbc | 310 | #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) |
AnnaBridge | 171:3a7713b1edbc | 311 | /* @brief Has FIFO (bit SC4[AFDEP]). */ |
AnnaBridge | 171:3a7713b1edbc | 312 | #define FSL_FEATURE_ADC16_HAS_FIFO (0) |
AnnaBridge | 171:3a7713b1edbc | 313 | /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ |
AnnaBridge | 171:3a7713b1edbc | 314 | #define FSL_FEATURE_ADC16_FIFO_SIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 315 | /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 316 | #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) |
AnnaBridge | 171:3a7713b1edbc | 317 | /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ |
AnnaBridge | 171:3a7713b1edbc | 318 | #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) |
AnnaBridge | 171:3a7713b1edbc | 319 | /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ |
AnnaBridge | 171:3a7713b1edbc | 320 | #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) |
AnnaBridge | 171:3a7713b1edbc | 321 | /* @brief Has HW averaging (bit SC3[AVGE]). */ |
AnnaBridge | 171:3a7713b1edbc | 322 | #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) |
AnnaBridge | 171:3a7713b1edbc | 323 | /* @brief Has offset correction (register OFS). */ |
AnnaBridge | 171:3a7713b1edbc | 324 | #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) |
AnnaBridge | 171:3a7713b1edbc | 325 | /* @brief Maximum ADC resolution. */ |
AnnaBridge | 171:3a7713b1edbc | 326 | #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) |
AnnaBridge | 171:3a7713b1edbc | 327 | /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ |
AnnaBridge | 171:3a7713b1edbc | 328 | #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) |
AnnaBridge | 171:3a7713b1edbc | 329 | |
AnnaBridge | 171:3a7713b1edbc | 330 | /* CMP module features */ |
AnnaBridge | 171:3a7713b1edbc | 331 | |
AnnaBridge | 171:3a7713b1edbc | 332 | /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ |
AnnaBridge | 171:3a7713b1edbc | 333 | #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) |
AnnaBridge | 171:3a7713b1edbc | 334 | /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ |
AnnaBridge | 171:3a7713b1edbc | 335 | #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) |
AnnaBridge | 171:3a7713b1edbc | 336 | /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ |
AnnaBridge | 171:3a7713b1edbc | 337 | #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) |
AnnaBridge | 171:3a7713b1edbc | 338 | /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ |
AnnaBridge | 171:3a7713b1edbc | 339 | #define FSL_FEATURE_CMP_HAS_DMA (1) |
AnnaBridge | 171:3a7713b1edbc | 340 | /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ |
AnnaBridge | 171:3a7713b1edbc | 341 | #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) |
AnnaBridge | 171:3a7713b1edbc | 342 | /* @brief Has DAC Test function in CMP (register DACTEST). */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) |
AnnaBridge | 171:3a7713b1edbc | 344 | |
AnnaBridge | 171:3a7713b1edbc | 345 | /* COP module features */ |
AnnaBridge | 171:3a7713b1edbc | 346 | |
AnnaBridge | 171:3a7713b1edbc | 347 | /* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ |
AnnaBridge | 171:3a7713b1edbc | 348 | #define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) |
AnnaBridge | 171:3a7713b1edbc | 349 | /* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ |
AnnaBridge | 171:3a7713b1edbc | 350 | #define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) |
AnnaBridge | 171:3a7713b1edbc | 351 | /* @brief Has more clock sources like MCGIRC */ |
AnnaBridge | 171:3a7713b1edbc | 352 | #define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) |
AnnaBridge | 171:3a7713b1edbc | 353 | /* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ |
AnnaBridge | 171:3a7713b1edbc | 354 | #define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) |
AnnaBridge | 171:3a7713b1edbc | 355 | |
AnnaBridge | 171:3a7713b1edbc | 356 | /* DAC module features */ |
AnnaBridge | 171:3a7713b1edbc | 357 | |
AnnaBridge | 171:3a7713b1edbc | 358 | /* @brief Define the size of hardware buffer */ |
AnnaBridge | 171:3a7713b1edbc | 359 | #define FSL_FEATURE_DAC_BUFFER_SIZE (2) |
AnnaBridge | 171:3a7713b1edbc | 360 | /* @brief Define whether the buffer supports watermark event detection or not. */ |
AnnaBridge | 171:3a7713b1edbc | 361 | #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) |
AnnaBridge | 171:3a7713b1edbc | 362 | /* @brief Define whether the buffer supports watermark selection detection or not. */ |
AnnaBridge | 171:3a7713b1edbc | 363 | #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) |
AnnaBridge | 171:3a7713b1edbc | 364 | /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ |
AnnaBridge | 171:3a7713b1edbc | 365 | #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) |
AnnaBridge | 171:3a7713b1edbc | 366 | /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ |
AnnaBridge | 171:3a7713b1edbc | 367 | #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) |
AnnaBridge | 171:3a7713b1edbc | 368 | /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ |
AnnaBridge | 171:3a7713b1edbc | 369 | #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) |
AnnaBridge | 171:3a7713b1edbc | 370 | /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ |
AnnaBridge | 171:3a7713b1edbc | 371 | #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) |
AnnaBridge | 171:3a7713b1edbc | 372 | /* @brief Define whether FIFO buffer mode is available or not. */ |
AnnaBridge | 171:3a7713b1edbc | 373 | #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) |
AnnaBridge | 171:3a7713b1edbc | 374 | /* @brief Define whether swing buffer mode is available or not.. */ |
AnnaBridge | 171:3a7713b1edbc | 375 | #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) |
AnnaBridge | 171:3a7713b1edbc | 376 | |
AnnaBridge | 171:3a7713b1edbc | 377 | /* DCDC module features */ |
AnnaBridge | 171:3a7713b1edbc | 378 | |
AnnaBridge | 171:3a7713b1edbc | 379 | /* @brief Has VDD1P5 bits in DCDC REG3. */ |
AnnaBridge | 171:3a7713b1edbc | 380 | #define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) |
AnnaBridge | 171:3a7713b1edbc | 381 | /* @brief Has VDD1P45 bits in DCDC REG3. */ |
AnnaBridge | 171:3a7713b1edbc | 382 | #define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) |
AnnaBridge | 171:3a7713b1edbc | 383 | |
AnnaBridge | 171:3a7713b1edbc | 384 | /* EDMA module features */ |
AnnaBridge | 171:3a7713b1edbc | 385 | |
AnnaBridge | 171:3a7713b1edbc | 386 | /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ |
AnnaBridge | 171:3a7713b1edbc | 387 | #define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) |
AnnaBridge | 171:3a7713b1edbc | 388 | /* @brief Total number of DMA channels on all modules. */ |
AnnaBridge | 171:3a7713b1edbc | 389 | #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) |
AnnaBridge | 171:3a7713b1edbc | 390 | /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ |
AnnaBridge | 171:3a7713b1edbc | 391 | #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 392 | /* @brief Has DMA_Error interrupt vector. */ |
AnnaBridge | 171:3a7713b1edbc | 393 | #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) |
AnnaBridge | 171:3a7713b1edbc | 394 | /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ |
AnnaBridge | 171:3a7713b1edbc | 395 | #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) |
AnnaBridge | 171:3a7713b1edbc | 396 | |
AnnaBridge | 171:3a7713b1edbc | 397 | /* DMAMUX module features */ |
AnnaBridge | 171:3a7713b1edbc | 398 | |
AnnaBridge | 171:3a7713b1edbc | 399 | /* @brief Number of DMA channels (related to number of register CHCFGn). */ |
AnnaBridge | 171:3a7713b1edbc | 400 | #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) |
AnnaBridge | 171:3a7713b1edbc | 401 | /* @brief Total number of DMA channels on all modules. */ |
AnnaBridge | 171:3a7713b1edbc | 402 | #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) |
AnnaBridge | 171:3a7713b1edbc | 403 | /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ |
AnnaBridge | 171:3a7713b1edbc | 404 | #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) |
AnnaBridge | 171:3a7713b1edbc | 405 | |
AnnaBridge | 171:3a7713b1edbc | 406 | /* FLASH module features */ |
AnnaBridge | 171:3a7713b1edbc | 407 | |
AnnaBridge | 171:3a7713b1edbc | 408 | #if defined(CPU_MKW41Z256VHT4) |
AnnaBridge | 171:3a7713b1edbc | 409 | /* @brief Is of type FTFA. */ |
AnnaBridge | 171:3a7713b1edbc | 410 | #define FSL_FEATURE_FLASH_IS_FTFA (1) |
AnnaBridge | 171:3a7713b1edbc | 411 | /* @brief Is of type FTFE. */ |
AnnaBridge | 171:3a7713b1edbc | 412 | #define FSL_FEATURE_FLASH_IS_FTFE (0) |
AnnaBridge | 171:3a7713b1edbc | 413 | /* @brief Is of type FTFL. */ |
AnnaBridge | 171:3a7713b1edbc | 414 | #define FSL_FEATURE_FLASH_IS_FTFL (0) |
AnnaBridge | 171:3a7713b1edbc | 415 | /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ |
AnnaBridge | 171:3a7713b1edbc | 416 | #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) |
AnnaBridge | 171:3a7713b1edbc | 417 | /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ |
AnnaBridge | 171:3a7713b1edbc | 418 | #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) |
AnnaBridge | 171:3a7713b1edbc | 419 | /* @brief Has EEPROM region protection (register FEPROT). */ |
AnnaBridge | 171:3a7713b1edbc | 420 | #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) |
AnnaBridge | 171:3a7713b1edbc | 421 | /* @brief Has data flash region protection (register FDPROT). */ |
AnnaBridge | 171:3a7713b1edbc | 422 | #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) |
AnnaBridge | 171:3a7713b1edbc | 423 | /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ |
AnnaBridge | 171:3a7713b1edbc | 424 | #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) |
AnnaBridge | 171:3a7713b1edbc | 425 | /* @brief Has flash cache control in FMC module. */ |
AnnaBridge | 171:3a7713b1edbc | 426 | #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) |
AnnaBridge | 171:3a7713b1edbc | 427 | /* @brief Has flash cache control in MCM module. */ |
AnnaBridge | 171:3a7713b1edbc | 428 | #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) |
AnnaBridge | 171:3a7713b1edbc | 429 | /* @brief Has flash cache control in MSCM module. */ |
AnnaBridge | 171:3a7713b1edbc | 430 | #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) |
AnnaBridge | 171:3a7713b1edbc | 431 | /* @brief P-Flash start address. */ |
AnnaBridge | 171:3a7713b1edbc | 432 | #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) |
AnnaBridge | 171:3a7713b1edbc | 433 | /* @brief P-Flash block count. */ |
AnnaBridge | 171:3a7713b1edbc | 434 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) |
AnnaBridge | 171:3a7713b1edbc | 435 | /* @brief P-Flash block size. */ |
AnnaBridge | 171:3a7713b1edbc | 436 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) |
AnnaBridge | 171:3a7713b1edbc | 437 | /* @brief P-Flash sector size. */ |
AnnaBridge | 171:3a7713b1edbc | 438 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) |
AnnaBridge | 171:3a7713b1edbc | 439 | /* @brief P-Flash write unit size. */ |
AnnaBridge | 171:3a7713b1edbc | 440 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) |
AnnaBridge | 171:3a7713b1edbc | 441 | /* @brief P-Flash data path width. */ |
AnnaBridge | 171:3a7713b1edbc | 442 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) |
AnnaBridge | 171:3a7713b1edbc | 443 | /* @brief P-Flash block swap feature. */ |
AnnaBridge | 171:3a7713b1edbc | 444 | #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) |
AnnaBridge | 171:3a7713b1edbc | 445 | /* @brief P-Flash protection region count. */ |
AnnaBridge | 171:3a7713b1edbc | 446 | #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) |
AnnaBridge | 171:3a7713b1edbc | 447 | /* @brief Has FlexNVM memory. */ |
AnnaBridge | 171:3a7713b1edbc | 448 | #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) |
AnnaBridge | 171:3a7713b1edbc | 449 | /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ |
AnnaBridge | 171:3a7713b1edbc | 450 | #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) |
AnnaBridge | 171:3a7713b1edbc | 451 | /* @brief FlexNVM block count. */ |
AnnaBridge | 171:3a7713b1edbc | 452 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 453 | /* @brief FlexNVM block size. */ |
AnnaBridge | 171:3a7713b1edbc | 454 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 455 | /* @brief FlexNVM sector size. */ |
AnnaBridge | 171:3a7713b1edbc | 456 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 457 | /* @brief FlexNVM write unit size. */ |
AnnaBridge | 171:3a7713b1edbc | 458 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 459 | /* @brief FlexNVM data path width. */ |
AnnaBridge | 171:3a7713b1edbc | 460 | #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 461 | /* @brief Has FlexRAM memory. */ |
AnnaBridge | 171:3a7713b1edbc | 462 | #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) |
AnnaBridge | 171:3a7713b1edbc | 463 | /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ |
AnnaBridge | 171:3a7713b1edbc | 464 | #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) |
AnnaBridge | 171:3a7713b1edbc | 465 | /* @brief FlexRAM size. */ |
AnnaBridge | 171:3a7713b1edbc | 466 | #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 467 | /* @brief Has 0x00 Read 1s Block command. */ |
AnnaBridge | 171:3a7713b1edbc | 468 | #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 469 | /* @brief Has 0x01 Read 1s Section command. */ |
AnnaBridge | 171:3a7713b1edbc | 470 | #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 471 | /* @brief Has 0x02 Program Check command. */ |
AnnaBridge | 171:3a7713b1edbc | 472 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 473 | /* @brief Has 0x03 Read Resource command. */ |
AnnaBridge | 171:3a7713b1edbc | 474 | #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 475 | /* @brief Has 0x06 Program Longword command. */ |
AnnaBridge | 171:3a7713b1edbc | 476 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 477 | /* @brief Has 0x07 Program Phrase command. */ |
AnnaBridge | 171:3a7713b1edbc | 478 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) |
AnnaBridge | 171:3a7713b1edbc | 479 | /* @brief Has 0x08 Erase Flash Block command. */ |
AnnaBridge | 171:3a7713b1edbc | 480 | #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 481 | /* @brief Has 0x09 Erase Flash Sector command. */ |
AnnaBridge | 171:3a7713b1edbc | 482 | #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 483 | /* @brief Has 0x0B Program Section command. */ |
AnnaBridge | 171:3a7713b1edbc | 484 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) |
AnnaBridge | 171:3a7713b1edbc | 485 | /* @brief Has 0x40 Read 1s All Blocks command. */ |
AnnaBridge | 171:3a7713b1edbc | 486 | #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 487 | /* @brief Has 0x41 Read Once command. */ |
AnnaBridge | 171:3a7713b1edbc | 488 | #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 489 | /* @brief Has 0x43 Program Once command. */ |
AnnaBridge | 171:3a7713b1edbc | 490 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 491 | /* @brief Has 0x44 Erase All Blocks command. */ |
AnnaBridge | 171:3a7713b1edbc | 492 | #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 493 | /* @brief Has 0x45 Verify Backdoor Access Key command. */ |
AnnaBridge | 171:3a7713b1edbc | 494 | #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 495 | /* @brief Has 0x46 Swap Control command. */ |
AnnaBridge | 171:3a7713b1edbc | 496 | #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) |
AnnaBridge | 171:3a7713b1edbc | 497 | /* @brief Has 0x49 Erase All Blocks Unsecure command. */ |
AnnaBridge | 171:3a7713b1edbc | 498 | #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 499 | /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ |
AnnaBridge | 171:3a7713b1edbc | 500 | #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 501 | /* @brief Has 0x4B Erase All Execute-only Segments command. */ |
AnnaBridge | 171:3a7713b1edbc | 502 | #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 503 | /* @brief Has 0x80 Program Partition command. */ |
AnnaBridge | 171:3a7713b1edbc | 504 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) |
AnnaBridge | 171:3a7713b1edbc | 505 | /* @brief Has 0x81 Set FlexRAM Function command. */ |
AnnaBridge | 171:3a7713b1edbc | 506 | #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) |
AnnaBridge | 171:3a7713b1edbc | 507 | /* @brief P-Flash Erase/Read 1st all block command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 508 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) |
AnnaBridge | 171:3a7713b1edbc | 509 | /* @brief P-Flash Erase sector command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 510 | #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) |
AnnaBridge | 171:3a7713b1edbc | 511 | /* @brief P-Flash Rrogram/Verify section command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 512 | #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) |
AnnaBridge | 171:3a7713b1edbc | 513 | /* @brief P-Flash Read resource command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 514 | #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) |
AnnaBridge | 171:3a7713b1edbc | 515 | /* @brief P-Flash Program check command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 516 | #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) |
AnnaBridge | 171:3a7713b1edbc | 517 | /* @brief P-Flash Program check command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 518 | #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 519 | /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 520 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 521 | /* @brief FlexNVM Erase sector command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 522 | #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 523 | /* @brief FlexNVM Rrogram/Verify section command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 524 | #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 525 | /* @brief FlexNVM Read resource command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 526 | #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 527 | /* @brief FlexNVM Program check command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 528 | #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 529 | /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 530 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 531 | /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 532 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 533 | /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 534 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 535 | /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 536 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 537 | /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 538 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 539 | /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 540 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 541 | /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 542 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 543 | /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 544 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 545 | /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 546 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 547 | /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 548 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 549 | /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 550 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 551 | /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 552 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 553 | /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 554 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 555 | /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 556 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 557 | /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 558 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 559 | /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 560 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 561 | /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 562 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 563 | /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 564 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 565 | /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 566 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 567 | /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 568 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 569 | /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 570 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 571 | /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 572 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 573 | /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 574 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 575 | /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 576 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 577 | /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 578 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 579 | /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 580 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 581 | /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 582 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 583 | /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 584 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 585 | /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 586 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 587 | /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 588 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 589 | /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 590 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 591 | /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 592 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 593 | #elif defined(CPU_MKW41Z512VHT4) |
AnnaBridge | 171:3a7713b1edbc | 594 | /* @brief Is of type FTFA. */ |
AnnaBridge | 171:3a7713b1edbc | 595 | #define FSL_FEATURE_FLASH_IS_FTFA (1) |
AnnaBridge | 171:3a7713b1edbc | 596 | /* @brief Is of type FTFE. */ |
AnnaBridge | 171:3a7713b1edbc | 597 | #define FSL_FEATURE_FLASH_IS_FTFE (0) |
AnnaBridge | 171:3a7713b1edbc | 598 | /* @brief Is of type FTFL. */ |
AnnaBridge | 171:3a7713b1edbc | 599 | #define FSL_FEATURE_FLASH_IS_FTFL (0) |
AnnaBridge | 171:3a7713b1edbc | 600 | /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ |
AnnaBridge | 171:3a7713b1edbc | 601 | #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) |
AnnaBridge | 171:3a7713b1edbc | 602 | /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ |
AnnaBridge | 171:3a7713b1edbc | 603 | #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) |
AnnaBridge | 171:3a7713b1edbc | 604 | /* @brief Has EEPROM region protection (register FEPROT). */ |
AnnaBridge | 171:3a7713b1edbc | 605 | #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) |
AnnaBridge | 171:3a7713b1edbc | 606 | /* @brief Has data flash region protection (register FDPROT). */ |
AnnaBridge | 171:3a7713b1edbc | 607 | #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) |
AnnaBridge | 171:3a7713b1edbc | 608 | /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ |
AnnaBridge | 171:3a7713b1edbc | 609 | #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) |
AnnaBridge | 171:3a7713b1edbc | 610 | /* @brief Has flash cache control in FMC module. */ |
AnnaBridge | 171:3a7713b1edbc | 611 | #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) |
AnnaBridge | 171:3a7713b1edbc | 612 | /* @brief Has flash cache control in MCM module. */ |
AnnaBridge | 171:3a7713b1edbc | 613 | #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) |
AnnaBridge | 171:3a7713b1edbc | 614 | /* @brief Has flash cache control in MSCM module. */ |
AnnaBridge | 171:3a7713b1edbc | 615 | #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) |
AnnaBridge | 171:3a7713b1edbc | 616 | /* @brief P-Flash start address. */ |
AnnaBridge | 171:3a7713b1edbc | 617 | #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) |
AnnaBridge | 171:3a7713b1edbc | 618 | /* @brief P-Flash block count. */ |
AnnaBridge | 171:3a7713b1edbc | 619 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) |
AnnaBridge | 171:3a7713b1edbc | 620 | /* @brief P-Flash block size. */ |
AnnaBridge | 171:3a7713b1edbc | 621 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) |
AnnaBridge | 171:3a7713b1edbc | 622 | /* @brief P-Flash sector size. */ |
AnnaBridge | 171:3a7713b1edbc | 623 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) |
AnnaBridge | 171:3a7713b1edbc | 624 | /* @brief P-Flash write unit size. */ |
AnnaBridge | 171:3a7713b1edbc | 625 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) |
AnnaBridge | 171:3a7713b1edbc | 626 | /* @brief P-Flash data path width. */ |
AnnaBridge | 171:3a7713b1edbc | 627 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) |
AnnaBridge | 171:3a7713b1edbc | 628 | /* @brief P-Flash block swap feature. */ |
AnnaBridge | 171:3a7713b1edbc | 629 | #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) |
AnnaBridge | 171:3a7713b1edbc | 630 | /* @brief P-Flash protection region count. */ |
AnnaBridge | 171:3a7713b1edbc | 631 | #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) |
AnnaBridge | 171:3a7713b1edbc | 632 | /* @brief Has FlexNVM memory. */ |
AnnaBridge | 171:3a7713b1edbc | 633 | #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) |
AnnaBridge | 171:3a7713b1edbc | 634 | /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ |
AnnaBridge | 171:3a7713b1edbc | 635 | #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) |
AnnaBridge | 171:3a7713b1edbc | 636 | /* @brief FlexNVM block count. */ |
AnnaBridge | 171:3a7713b1edbc | 637 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 638 | /* @brief FlexNVM block size. */ |
AnnaBridge | 171:3a7713b1edbc | 639 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 640 | /* @brief FlexNVM sector size. */ |
AnnaBridge | 171:3a7713b1edbc | 641 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 642 | /* @brief FlexNVM write unit size. */ |
AnnaBridge | 171:3a7713b1edbc | 643 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 644 | /* @brief FlexNVM data path width. */ |
AnnaBridge | 171:3a7713b1edbc | 645 | #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 646 | /* @brief Has FlexRAM memory. */ |
AnnaBridge | 171:3a7713b1edbc | 647 | #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) |
AnnaBridge | 171:3a7713b1edbc | 648 | /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ |
AnnaBridge | 171:3a7713b1edbc | 649 | #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) |
AnnaBridge | 171:3a7713b1edbc | 650 | /* @brief FlexRAM size. */ |
AnnaBridge | 171:3a7713b1edbc | 651 | #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 652 | /* @brief Has 0x00 Read 1s Block command. */ |
AnnaBridge | 171:3a7713b1edbc | 653 | #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 654 | /* @brief Has 0x01 Read 1s Section command. */ |
AnnaBridge | 171:3a7713b1edbc | 655 | #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 656 | /* @brief Has 0x02 Program Check command. */ |
AnnaBridge | 171:3a7713b1edbc | 657 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 658 | /* @brief Has 0x03 Read Resource command. */ |
AnnaBridge | 171:3a7713b1edbc | 659 | #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 660 | /* @brief Has 0x06 Program Longword command. */ |
AnnaBridge | 171:3a7713b1edbc | 661 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 662 | /* @brief Has 0x07 Program Phrase command. */ |
AnnaBridge | 171:3a7713b1edbc | 663 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) |
AnnaBridge | 171:3a7713b1edbc | 664 | /* @brief Has 0x08 Erase Flash Block command. */ |
AnnaBridge | 171:3a7713b1edbc | 665 | #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 666 | /* @brief Has 0x09 Erase Flash Sector command. */ |
AnnaBridge | 171:3a7713b1edbc | 667 | #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 668 | /* @brief Has 0x0B Program Section command. */ |
AnnaBridge | 171:3a7713b1edbc | 669 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) |
AnnaBridge | 171:3a7713b1edbc | 670 | /* @brief Has 0x40 Read 1s All Blocks command. */ |
AnnaBridge | 171:3a7713b1edbc | 671 | #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 672 | /* @brief Has 0x41 Read Once command. */ |
AnnaBridge | 171:3a7713b1edbc | 673 | #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 674 | /* @brief Has 0x43 Program Once command. */ |
AnnaBridge | 171:3a7713b1edbc | 675 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 676 | /* @brief Has 0x44 Erase All Blocks command. */ |
AnnaBridge | 171:3a7713b1edbc | 677 | #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 678 | /* @brief Has 0x45 Verify Backdoor Access Key command. */ |
AnnaBridge | 171:3a7713b1edbc | 679 | #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 680 | /* @brief Has 0x46 Swap Control command. */ |
AnnaBridge | 171:3a7713b1edbc | 681 | #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) |
AnnaBridge | 171:3a7713b1edbc | 682 | /* @brief Has 0x49 Erase All Blocks Unsecure command. */ |
AnnaBridge | 171:3a7713b1edbc | 683 | #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 684 | /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ |
AnnaBridge | 171:3a7713b1edbc | 685 | #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 686 | /* @brief Has 0x4B Erase All Execute-only Segments command. */ |
AnnaBridge | 171:3a7713b1edbc | 687 | #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) |
AnnaBridge | 171:3a7713b1edbc | 688 | /* @brief Has 0x80 Program Partition command. */ |
AnnaBridge | 171:3a7713b1edbc | 689 | #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) |
AnnaBridge | 171:3a7713b1edbc | 690 | /* @brief Has 0x81 Set FlexRAM Function command. */ |
AnnaBridge | 171:3a7713b1edbc | 691 | #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) |
AnnaBridge | 171:3a7713b1edbc | 692 | /* @brief P-Flash Erase/Read 1st all block command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 693 | #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) |
AnnaBridge | 171:3a7713b1edbc | 694 | /* @brief P-Flash Erase sector command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 695 | #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) |
AnnaBridge | 171:3a7713b1edbc | 696 | /* @brief P-Flash Rrogram/Verify section command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 697 | #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) |
AnnaBridge | 171:3a7713b1edbc | 698 | /* @brief P-Flash Read resource command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 699 | #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) |
AnnaBridge | 171:3a7713b1edbc | 700 | /* @brief P-Flash Program check command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 701 | #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) |
AnnaBridge | 171:3a7713b1edbc | 702 | /* @brief P-Flash Program check command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 703 | #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 704 | /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 705 | #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 706 | /* @brief FlexNVM Erase sector command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 707 | #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 708 | /* @brief FlexNVM Rrogram/Verify section command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 709 | #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 710 | /* @brief FlexNVM Read resource command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 711 | #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 712 | /* @brief FlexNVM Program check command address alignment. */ |
AnnaBridge | 171:3a7713b1edbc | 713 | #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) |
AnnaBridge | 171:3a7713b1edbc | 714 | /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 715 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 716 | /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 717 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 718 | /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 719 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 720 | /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 721 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 722 | /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 723 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 724 | /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 725 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 726 | /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 727 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 728 | /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 729 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 730 | /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 731 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 732 | /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 733 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 734 | /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 735 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 736 | /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 737 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 738 | /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 739 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 740 | /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 741 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 742 | /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 743 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 744 | /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 745 | #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 746 | /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 747 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 748 | /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 749 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 750 | /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 751 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 752 | /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 753 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 754 | /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 755 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 756 | /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 757 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 758 | /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 759 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 760 | /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 761 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 762 | /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 763 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 764 | /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 765 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 766 | /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 767 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 768 | /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 769 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 770 | /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 771 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 772 | /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 773 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 774 | /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 775 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 776 | /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ |
AnnaBridge | 171:3a7713b1edbc | 777 | #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 778 | #endif /* defined(CPU_MKW41Z256VHT4) */ |
AnnaBridge | 171:3a7713b1edbc | 779 | |
AnnaBridge | 171:3a7713b1edbc | 780 | /* GPIO module features */ |
AnnaBridge | 171:3a7713b1edbc | 781 | |
AnnaBridge | 171:3a7713b1edbc | 782 | /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ |
AnnaBridge | 171:3a7713b1edbc | 783 | #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) |
AnnaBridge | 171:3a7713b1edbc | 784 | /* @brief Has port input disable register (PIDR). */ |
AnnaBridge | 171:3a7713b1edbc | 785 | #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) |
AnnaBridge | 171:3a7713b1edbc | 786 | /* @brief Has dedicated interrupt vector. */ |
AnnaBridge | 171:3a7713b1edbc | 787 | #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) |
AnnaBridge | 171:3a7713b1edbc | 788 | |
AnnaBridge | 171:3a7713b1edbc | 789 | /* I2C module features */ |
AnnaBridge | 171:3a7713b1edbc | 790 | |
AnnaBridge | 171:3a7713b1edbc | 791 | /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ |
AnnaBridge | 171:3a7713b1edbc | 792 | #define FSL_FEATURE_I2C_HAS_SMBUS (1) |
AnnaBridge | 171:3a7713b1edbc | 793 | /* @brief Maximum supported baud rate in kilobit per second. */ |
AnnaBridge | 171:3a7713b1edbc | 794 | #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) |
AnnaBridge | 171:3a7713b1edbc | 795 | /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ |
AnnaBridge | 171:3a7713b1edbc | 796 | #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) |
AnnaBridge | 171:3a7713b1edbc | 797 | /* @brief Has DMA support (register bit C1[DMAEN]). */ |
AnnaBridge | 171:3a7713b1edbc | 798 | #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) |
AnnaBridge | 171:3a7713b1edbc | 799 | /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ |
AnnaBridge | 171:3a7713b1edbc | 800 | #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) |
AnnaBridge | 171:3a7713b1edbc | 801 | /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ |
AnnaBridge | 171:3a7713b1edbc | 802 | #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) |
AnnaBridge | 171:3a7713b1edbc | 803 | /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ |
AnnaBridge | 171:3a7713b1edbc | 804 | #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) |
AnnaBridge | 171:3a7713b1edbc | 805 | /* @brief Maximum width of the glitch filter in number of bus clocks. */ |
AnnaBridge | 171:3a7713b1edbc | 806 | #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) |
AnnaBridge | 171:3a7713b1edbc | 807 | /* @brief Has control of the drive capability of the I2C pins. */ |
AnnaBridge | 171:3a7713b1edbc | 808 | #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) |
AnnaBridge | 171:3a7713b1edbc | 809 | /* @brief Has double buffering support (register S2). */ |
AnnaBridge | 171:3a7713b1edbc | 810 | #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) |
AnnaBridge | 171:3a7713b1edbc | 811 | /* @brief Has double buffer enable. */ |
AnnaBridge | 171:3a7713b1edbc | 812 | #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) |
AnnaBridge | 171:3a7713b1edbc | 813 | |
AnnaBridge | 171:3a7713b1edbc | 814 | /* LLWU module features */ |
AnnaBridge | 171:3a7713b1edbc | 815 | |
AnnaBridge | 171:3a7713b1edbc | 816 | /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 817 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) |
AnnaBridge | 171:3a7713b1edbc | 818 | /* @brief Has pins 8-15 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 819 | #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) |
AnnaBridge | 171:3a7713b1edbc | 820 | /* @brief Maximum number of internal modules connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 821 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) |
AnnaBridge | 171:3a7713b1edbc | 822 | /* @brief Number of digital filters. */ |
AnnaBridge | 171:3a7713b1edbc | 823 | #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) |
AnnaBridge | 171:3a7713b1edbc | 824 | /* @brief Has MF register. */ |
AnnaBridge | 171:3a7713b1edbc | 825 | #define FSL_FEATURE_LLWU_HAS_MF (0) |
AnnaBridge | 171:3a7713b1edbc | 826 | /* @brief Has PF register. */ |
AnnaBridge | 171:3a7713b1edbc | 827 | #define FSL_FEATURE_LLWU_HAS_PF (0) |
AnnaBridge | 171:3a7713b1edbc | 828 | /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ |
AnnaBridge | 171:3a7713b1edbc | 829 | #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) |
AnnaBridge | 171:3a7713b1edbc | 830 | /* @brief Has external pin 0 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 831 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) |
AnnaBridge | 171:3a7713b1edbc | 832 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 833 | #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) |
AnnaBridge | 171:3a7713b1edbc | 834 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 835 | #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) |
AnnaBridge | 171:3a7713b1edbc | 836 | /* @brief Has external pin 1 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 837 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) |
AnnaBridge | 171:3a7713b1edbc | 838 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 839 | #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) |
AnnaBridge | 171:3a7713b1edbc | 840 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 841 | #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) |
AnnaBridge | 171:3a7713b1edbc | 842 | /* @brief Has external pin 2 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 843 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) |
AnnaBridge | 171:3a7713b1edbc | 844 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 845 | #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) |
AnnaBridge | 171:3a7713b1edbc | 846 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 847 | #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) |
AnnaBridge | 171:3a7713b1edbc | 848 | /* @brief Has external pin 3 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 849 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) |
AnnaBridge | 171:3a7713b1edbc | 850 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 851 | #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) |
AnnaBridge | 171:3a7713b1edbc | 852 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 853 | #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) |
AnnaBridge | 171:3a7713b1edbc | 854 | /* @brief Has external pin 4 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 855 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) |
AnnaBridge | 171:3a7713b1edbc | 856 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 857 | #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) |
AnnaBridge | 171:3a7713b1edbc | 858 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 859 | #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) |
AnnaBridge | 171:3a7713b1edbc | 860 | /* @brief Has external pin 5 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 861 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) |
AnnaBridge | 171:3a7713b1edbc | 862 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 863 | #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) |
AnnaBridge | 171:3a7713b1edbc | 864 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 865 | #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) |
AnnaBridge | 171:3a7713b1edbc | 866 | /* @brief Has external pin 6 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 867 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) |
AnnaBridge | 171:3a7713b1edbc | 868 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 869 | #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) |
AnnaBridge | 171:3a7713b1edbc | 870 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 871 | #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) |
AnnaBridge | 171:3a7713b1edbc | 872 | /* @brief Has external pin 7 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 873 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) |
AnnaBridge | 171:3a7713b1edbc | 874 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 875 | #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) |
AnnaBridge | 171:3a7713b1edbc | 876 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 877 | #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) |
AnnaBridge | 171:3a7713b1edbc | 878 | /* @brief Has external pin 8 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 879 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) |
AnnaBridge | 171:3a7713b1edbc | 880 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 881 | #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) |
AnnaBridge | 171:3a7713b1edbc | 882 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 883 | #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 884 | /* @brief Has external pin 9 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 885 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) |
AnnaBridge | 171:3a7713b1edbc | 886 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 887 | #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 888 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 889 | #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 890 | /* @brief Has external pin 10 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 891 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) |
AnnaBridge | 171:3a7713b1edbc | 892 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 893 | #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) |
AnnaBridge | 171:3a7713b1edbc | 894 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 895 | #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) |
AnnaBridge | 171:3a7713b1edbc | 896 | /* @brief Has external pin 11 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 897 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) |
AnnaBridge | 171:3a7713b1edbc | 898 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 899 | #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) |
AnnaBridge | 171:3a7713b1edbc | 900 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 901 | #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) |
AnnaBridge | 171:3a7713b1edbc | 902 | /* @brief Has external pin 12 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 903 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) |
AnnaBridge | 171:3a7713b1edbc | 904 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 905 | #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) |
AnnaBridge | 171:3a7713b1edbc | 906 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 907 | #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) |
AnnaBridge | 171:3a7713b1edbc | 908 | /* @brief Has external pin 13 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 909 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) |
AnnaBridge | 171:3a7713b1edbc | 910 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 911 | #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) |
AnnaBridge | 171:3a7713b1edbc | 912 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 913 | #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) |
AnnaBridge | 171:3a7713b1edbc | 914 | /* @brief Has external pin 14 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 915 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) |
AnnaBridge | 171:3a7713b1edbc | 916 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 917 | #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) |
AnnaBridge | 171:3a7713b1edbc | 918 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 919 | #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) |
AnnaBridge | 171:3a7713b1edbc | 920 | /* @brief Has external pin 15 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 921 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) |
AnnaBridge | 171:3a7713b1edbc | 922 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 923 | #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) |
AnnaBridge | 171:3a7713b1edbc | 924 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 925 | #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) |
AnnaBridge | 171:3a7713b1edbc | 926 | /* @brief Has external pin 16 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 927 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) |
AnnaBridge | 171:3a7713b1edbc | 928 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 929 | #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 930 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 931 | #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 932 | /* @brief Has external pin 17 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 933 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) |
AnnaBridge | 171:3a7713b1edbc | 934 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 935 | #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 936 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 937 | #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 938 | /* @brief Has external pin 18 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 939 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) |
AnnaBridge | 171:3a7713b1edbc | 940 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 941 | #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 942 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 943 | #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 944 | /* @brief Has external pin 19 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 945 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) |
AnnaBridge | 171:3a7713b1edbc | 946 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 947 | #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 948 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 949 | #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 950 | /* @brief Has external pin 20 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 951 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) |
AnnaBridge | 171:3a7713b1edbc | 952 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 953 | #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 954 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 955 | #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 956 | /* @brief Has external pin 21 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 957 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) |
AnnaBridge | 171:3a7713b1edbc | 958 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 959 | #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 960 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 961 | #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 962 | /* @brief Has external pin 22 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 963 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) |
AnnaBridge | 171:3a7713b1edbc | 964 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 965 | #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 966 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 967 | #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 968 | /* @brief Has external pin 23 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 969 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) |
AnnaBridge | 171:3a7713b1edbc | 970 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 971 | #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 972 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 973 | #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 974 | /* @brief Has external pin 24 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 975 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) |
AnnaBridge | 171:3a7713b1edbc | 976 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 977 | #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 978 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 979 | #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 980 | /* @brief Has external pin 25 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 981 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) |
AnnaBridge | 171:3a7713b1edbc | 982 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 983 | #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 984 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 985 | #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 986 | /* @brief Has external pin 26 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 987 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) |
AnnaBridge | 171:3a7713b1edbc | 988 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 989 | #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 990 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 991 | #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 992 | /* @brief Has external pin 27 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 993 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) |
AnnaBridge | 171:3a7713b1edbc | 994 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 995 | #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 996 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 997 | #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 998 | /* @brief Has external pin 28 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 999 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) |
AnnaBridge | 171:3a7713b1edbc | 1000 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 1001 | #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 1002 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 1003 | #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 1004 | /* @brief Has external pin 29 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 1005 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) |
AnnaBridge | 171:3a7713b1edbc | 1006 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 1007 | #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 1008 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 1009 | #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 1010 | /* @brief Has external pin 30 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 1011 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) |
AnnaBridge | 171:3a7713b1edbc | 1012 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 1013 | #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 1014 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 1015 | #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 1016 | /* @brief Has external pin 31 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 1017 | #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) |
AnnaBridge | 171:3a7713b1edbc | 1018 | /* @brief Index of port of external pin. */ |
AnnaBridge | 171:3a7713b1edbc | 1019 | #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) |
AnnaBridge | 171:3a7713b1edbc | 1020 | /* @brief Number of external pin port on specified port. */ |
AnnaBridge | 171:3a7713b1edbc | 1021 | #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) |
AnnaBridge | 171:3a7713b1edbc | 1022 | /* @brief Has internal module 0 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 1023 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) |
AnnaBridge | 171:3a7713b1edbc | 1024 | /* @brief Has internal module 1 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 1025 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) |
AnnaBridge | 171:3a7713b1edbc | 1026 | /* @brief Has internal module 2 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 1027 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) |
AnnaBridge | 171:3a7713b1edbc | 1028 | /* @brief Has internal module 3 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 1029 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) |
AnnaBridge | 171:3a7713b1edbc | 1030 | /* @brief Has internal module 4 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 1031 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) |
AnnaBridge | 171:3a7713b1edbc | 1032 | /* @brief Has internal module 5 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 1033 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) |
AnnaBridge | 171:3a7713b1edbc | 1034 | /* @brief Has internal module 6 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 1035 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) |
AnnaBridge | 171:3a7713b1edbc | 1036 | /* @brief Has internal module 7 connected to LLWU device. */ |
AnnaBridge | 171:3a7713b1edbc | 1037 | #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) |
AnnaBridge | 171:3a7713b1edbc | 1038 | /* @brief Has Version ID Register (LLWU_VERID). */ |
AnnaBridge | 171:3a7713b1edbc | 1039 | #define FSL_FEATURE_LLWU_HAS_VERID (0) |
AnnaBridge | 171:3a7713b1edbc | 1040 | /* @brief Has Parameter Register (LLWU_PARAM). */ |
AnnaBridge | 171:3a7713b1edbc | 1041 | #define FSL_FEATURE_LLWU_HAS_PARAM (0) |
AnnaBridge | 171:3a7713b1edbc | 1042 | /* @brief Width of registers of the LLWU. */ |
AnnaBridge | 171:3a7713b1edbc | 1043 | #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) |
AnnaBridge | 171:3a7713b1edbc | 1044 | /* @brief Has DMA Enable register (LLWU_DE). */ |
AnnaBridge | 171:3a7713b1edbc | 1045 | #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) |
AnnaBridge | 171:3a7713b1edbc | 1046 | |
AnnaBridge | 171:3a7713b1edbc | 1047 | /* LPTMR module features */ |
AnnaBridge | 171:3a7713b1edbc | 1048 | |
AnnaBridge | 171:3a7713b1edbc | 1049 | /* @brief Has shared interrupt handler with another LPTMR module. */ |
AnnaBridge | 171:3a7713b1edbc | 1050 | #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) |
AnnaBridge | 171:3a7713b1edbc | 1051 | |
AnnaBridge | 171:3a7713b1edbc | 1052 | /* LPUART module features */ |
AnnaBridge | 171:3a7713b1edbc | 1053 | |
AnnaBridge | 171:3a7713b1edbc | 1054 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1055 | #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) |
AnnaBridge | 171:3a7713b1edbc | 1056 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ |
AnnaBridge | 171:3a7713b1edbc | 1057 | #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) |
AnnaBridge | 171:3a7713b1edbc | 1058 | /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ |
AnnaBridge | 171:3a7713b1edbc | 1059 | #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) |
AnnaBridge | 171:3a7713b1edbc | 1060 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
AnnaBridge | 171:3a7713b1edbc | 1061 | #define FSL_FEATURE_LPUART_HAS_FIFO (0) |
AnnaBridge | 171:3a7713b1edbc | 1062 | /* @brief Has 32-bit register MODIR */ |
AnnaBridge | 171:3a7713b1edbc | 1063 | #define FSL_FEATURE_LPUART_HAS_MODIR (1) |
AnnaBridge | 171:3a7713b1edbc | 1064 | /* @brief Hardware flow control (RTS, CTS) is supported. */ |
AnnaBridge | 171:3a7713b1edbc | 1065 | #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) |
AnnaBridge | 171:3a7713b1edbc | 1066 | /* @brief Infrared (modulation) is supported. */ |
AnnaBridge | 171:3a7713b1edbc | 1067 | #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) |
AnnaBridge | 171:3a7713b1edbc | 1068 | /* @brief 2 bits long stop bit is available. */ |
AnnaBridge | 171:3a7713b1edbc | 1069 | #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) |
AnnaBridge | 171:3a7713b1edbc | 1070 | /* @brief If 10-bit mode is supported. */ |
AnnaBridge | 171:3a7713b1edbc | 1071 | #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) |
AnnaBridge | 171:3a7713b1edbc | 1072 | /* @brief If 7-bit mode is supported. */ |
AnnaBridge | 171:3a7713b1edbc | 1073 | #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) |
AnnaBridge | 171:3a7713b1edbc | 1074 | /* @brief Baud rate fine adjustment is available. */ |
AnnaBridge | 171:3a7713b1edbc | 1075 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) |
AnnaBridge | 171:3a7713b1edbc | 1076 | /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ |
AnnaBridge | 171:3a7713b1edbc | 1077 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) |
AnnaBridge | 171:3a7713b1edbc | 1078 | /* @brief Baud rate oversampling is available. */ |
AnnaBridge | 171:3a7713b1edbc | 1079 | #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) |
AnnaBridge | 171:3a7713b1edbc | 1080 | /* @brief Baud rate oversampling is available. */ |
AnnaBridge | 171:3a7713b1edbc | 1081 | #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) |
AnnaBridge | 171:3a7713b1edbc | 1082 | /* @brief Peripheral type. */ |
AnnaBridge | 171:3a7713b1edbc | 1083 | #define FSL_FEATURE_LPUART_IS_SCI (1) |
AnnaBridge | 171:3a7713b1edbc | 1084 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
AnnaBridge | 171:3a7713b1edbc | 1085 | #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) |
AnnaBridge | 171:3a7713b1edbc | 1086 | /* @brief Maximal data width without parity bit. */ |
AnnaBridge | 171:3a7713b1edbc | 1087 | #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) |
AnnaBridge | 171:3a7713b1edbc | 1088 | /* @brief Maximal data width with parity bit. */ |
AnnaBridge | 171:3a7713b1edbc | 1089 | #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) |
AnnaBridge | 171:3a7713b1edbc | 1090 | /* @brief Supports two match addresses to filter incoming frames. */ |
AnnaBridge | 171:3a7713b1edbc | 1091 | #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) |
AnnaBridge | 171:3a7713b1edbc | 1092 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ |
AnnaBridge | 171:3a7713b1edbc | 1093 | #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) |
AnnaBridge | 171:3a7713b1edbc | 1094 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ |
AnnaBridge | 171:3a7713b1edbc | 1095 | #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) |
AnnaBridge | 171:3a7713b1edbc | 1096 | /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ |
AnnaBridge | 171:3a7713b1edbc | 1097 | #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) |
AnnaBridge | 171:3a7713b1edbc | 1098 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ |
AnnaBridge | 171:3a7713b1edbc | 1099 | #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) |
AnnaBridge | 171:3a7713b1edbc | 1100 | /* @brief Has improved smart card (ISO7816 protocol) support. */ |
AnnaBridge | 171:3a7713b1edbc | 1101 | #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) |
AnnaBridge | 171:3a7713b1edbc | 1102 | /* @brief Has local operation network (CEA709.1-B protocol) support. */ |
AnnaBridge | 171:3a7713b1edbc | 1103 | #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) |
AnnaBridge | 171:3a7713b1edbc | 1104 | /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ |
AnnaBridge | 171:3a7713b1edbc | 1105 | #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) |
AnnaBridge | 171:3a7713b1edbc | 1106 | /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1107 | #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) |
AnnaBridge | 171:3a7713b1edbc | 1108 | /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ |
AnnaBridge | 171:3a7713b1edbc | 1109 | #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) |
AnnaBridge | 171:3a7713b1edbc | 1110 | /* @brief Has separate DMA RX and TX requests. */ |
AnnaBridge | 171:3a7713b1edbc | 1111 | #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) |
AnnaBridge | 171:3a7713b1edbc | 1112 | /* @brief Has separate RX and TX interrupts. */ |
AnnaBridge | 171:3a7713b1edbc | 1113 | #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) |
AnnaBridge | 171:3a7713b1edbc | 1114 | /* @brief Has LPAURT_PARAM. */ |
AnnaBridge | 171:3a7713b1edbc | 1115 | #define FSL_FEATURE_LPUART_HAS_PARAM (0) |
AnnaBridge | 171:3a7713b1edbc | 1116 | /* @brief Has LPUART_VERID. */ |
AnnaBridge | 171:3a7713b1edbc | 1117 | #define FSL_FEATURE_LPUART_HAS_VERID (0) |
AnnaBridge | 171:3a7713b1edbc | 1118 | /* @brief Has LPUART_GLOBAL. */ |
AnnaBridge | 171:3a7713b1edbc | 1119 | #define FSL_FEATURE_LPUART_HAS_GLOBAL (0) |
AnnaBridge | 171:3a7713b1edbc | 1120 | /* @brief Has LPUART_PINCFG. */ |
AnnaBridge | 171:3a7713b1edbc | 1121 | #define FSL_FEATURE_LPUART_HAS_PINCFG (0) |
AnnaBridge | 171:3a7713b1edbc | 1122 | |
AnnaBridge | 171:3a7713b1edbc | 1123 | /* LTC module features */ |
AnnaBridge | 171:3a7713b1edbc | 1124 | |
AnnaBridge | 171:3a7713b1edbc | 1125 | /* @brief LTC module supports DES algorithm. */ |
AnnaBridge | 171:3a7713b1edbc | 1126 | #define FSL_FEATURE_LTC_HAS_DES (0) |
AnnaBridge | 171:3a7713b1edbc | 1127 | /* @brief LTC module supports PKHA algorithm. */ |
AnnaBridge | 171:3a7713b1edbc | 1128 | #define FSL_FEATURE_LTC_HAS_PKHA (0) |
AnnaBridge | 171:3a7713b1edbc | 1129 | /* @brief LTC module supports SHA algorithm. */ |
AnnaBridge | 171:3a7713b1edbc | 1130 | #define FSL_FEATURE_LTC_HAS_SHA (0) |
AnnaBridge | 171:3a7713b1edbc | 1131 | /* @brief LTC module supports AES GCM mode. */ |
AnnaBridge | 171:3a7713b1edbc | 1132 | #define FSL_FEATURE_LTC_HAS_GCM (0) |
AnnaBridge | 171:3a7713b1edbc | 1133 | /* @brief LTC module supports DPAMS registers. */ |
AnnaBridge | 171:3a7713b1edbc | 1134 | #define FSL_FEATURE_LTC_HAS_DPAMS (0) |
AnnaBridge | 171:3a7713b1edbc | 1135 | /* @brief LTC module supports AES with 24 bytes key. */ |
AnnaBridge | 171:3a7713b1edbc | 1136 | #define FSL_FEATURE_LTC_HAS_AES192 (0) |
AnnaBridge | 171:3a7713b1edbc | 1137 | /* @brief LTC module supports AES with 32 bytes key. */ |
AnnaBridge | 171:3a7713b1edbc | 1138 | #define FSL_FEATURE_LTC_HAS_AES256 (0) |
AnnaBridge | 171:3a7713b1edbc | 1139 | |
AnnaBridge | 171:3a7713b1edbc | 1140 | /* MCG module features */ |
AnnaBridge | 171:3a7713b1edbc | 1141 | |
AnnaBridge | 171:3a7713b1edbc | 1142 | /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ |
AnnaBridge | 171:3a7713b1edbc | 1143 | #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) |
AnnaBridge | 171:3a7713b1edbc | 1144 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ |
AnnaBridge | 171:3a7713b1edbc | 1145 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) |
AnnaBridge | 171:3a7713b1edbc | 1146 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
AnnaBridge | 171:3a7713b1edbc | 1147 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) |
AnnaBridge | 171:3a7713b1edbc | 1148 | /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ |
AnnaBridge | 171:3a7713b1edbc | 1149 | #define FSL_FEATURE_MCG_PLL_REF_MIN (0) |
AnnaBridge | 171:3a7713b1edbc | 1150 | /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ |
AnnaBridge | 171:3a7713b1edbc | 1151 | #define FSL_FEATURE_MCG_PLL_REF_MAX (0) |
AnnaBridge | 171:3a7713b1edbc | 1152 | /* @brief The PLL clock is divided by 2 before VCO divider. */ |
AnnaBridge | 171:3a7713b1edbc | 1153 | #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) |
AnnaBridge | 171:3a7713b1edbc | 1154 | /* @brief FRDIV supports 1280. */ |
AnnaBridge | 171:3a7713b1edbc | 1155 | #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) |
AnnaBridge | 171:3a7713b1edbc | 1156 | /* @brief FRDIV supports 1536. */ |
AnnaBridge | 171:3a7713b1edbc | 1157 | #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) |
AnnaBridge | 171:3a7713b1edbc | 1158 | /* @brief MCGFFCLK divider. */ |
AnnaBridge | 171:3a7713b1edbc | 1159 | #define FSL_FEATURE_MCG_FFCLK_DIV (1) |
AnnaBridge | 171:3a7713b1edbc | 1160 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
AnnaBridge | 171:3a7713b1edbc | 1161 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) |
AnnaBridge | 171:3a7713b1edbc | 1162 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ |
AnnaBridge | 171:3a7713b1edbc | 1163 | #define FSL_FEATURE_MCG_HAS_RTC_32K (1) |
AnnaBridge | 171:3a7713b1edbc | 1164 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
AnnaBridge | 171:3a7713b1edbc | 1165 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
AnnaBridge | 171:3a7713b1edbc | 1166 | /* @brief Has 48MHz internal oscillator. */ |
AnnaBridge | 171:3a7713b1edbc | 1167 | #define FSL_FEATURE_MCG_HAS_IRC_48M (0) |
AnnaBridge | 171:3a7713b1edbc | 1168 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
AnnaBridge | 171:3a7713b1edbc | 1169 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
AnnaBridge | 171:3a7713b1edbc | 1170 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
AnnaBridge | 171:3a7713b1edbc | 1171 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) |
AnnaBridge | 171:3a7713b1edbc | 1172 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1173 | #define FSL_FEATURE_MCG_HAS_LOLRE (0) |
AnnaBridge | 171:3a7713b1edbc | 1174 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1175 | #define FSL_FEATURE_MCG_USE_OSCSEL (1) |
AnnaBridge | 171:3a7713b1edbc | 1176 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
AnnaBridge | 171:3a7713b1edbc | 1177 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
AnnaBridge | 171:3a7713b1edbc | 1178 | /* @brief TBD */ |
AnnaBridge | 171:3a7713b1edbc | 1179 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
AnnaBridge | 171:3a7713b1edbc | 1180 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
AnnaBridge | 171:3a7713b1edbc | 1181 | #define FSL_FEATURE_MCG_HAS_PLL (0) |
AnnaBridge | 171:3a7713b1edbc | 1182 | /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ |
AnnaBridge | 171:3a7713b1edbc | 1183 | #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) |
AnnaBridge | 171:3a7713b1edbc | 1184 | /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ |
AnnaBridge | 171:3a7713b1edbc | 1185 | #define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) |
AnnaBridge | 171:3a7713b1edbc | 1186 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
AnnaBridge | 171:3a7713b1edbc | 1187 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) |
AnnaBridge | 171:3a7713b1edbc | 1188 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
AnnaBridge | 171:3a7713b1edbc | 1189 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
AnnaBridge | 171:3a7713b1edbc | 1190 | /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ |
AnnaBridge | 171:3a7713b1edbc | 1191 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) |
AnnaBridge | 171:3a7713b1edbc | 1192 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1193 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
AnnaBridge | 171:3a7713b1edbc | 1194 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
AnnaBridge | 171:3a7713b1edbc | 1195 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) |
AnnaBridge | 171:3a7713b1edbc | 1196 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
AnnaBridge | 171:3a7713b1edbc | 1197 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
AnnaBridge | 171:3a7713b1edbc | 1198 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
AnnaBridge | 171:3a7713b1edbc | 1199 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
AnnaBridge | 171:3a7713b1edbc | 1200 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
AnnaBridge | 171:3a7713b1edbc | 1201 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
AnnaBridge | 171:3a7713b1edbc | 1202 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
AnnaBridge | 171:3a7713b1edbc | 1203 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1204 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
AnnaBridge | 171:3a7713b1edbc | 1205 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1206 | /* @brief Has PEI mode or PBI mode. */ |
AnnaBridge | 171:3a7713b1edbc | 1207 | #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) |
AnnaBridge | 171:3a7713b1edbc | 1208 | /* @brief Reset clock mode is BLPI. */ |
AnnaBridge | 171:3a7713b1edbc | 1209 | #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) |
AnnaBridge | 171:3a7713b1edbc | 1210 | |
AnnaBridge | 171:3a7713b1edbc | 1211 | /* interrupt module features */ |
AnnaBridge | 171:3a7713b1edbc | 1212 | |
AnnaBridge | 171:3a7713b1edbc | 1213 | /* @brief Lowest interrupt request number. */ |
AnnaBridge | 171:3a7713b1edbc | 1214 | #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) |
AnnaBridge | 171:3a7713b1edbc | 1215 | /* @brief Highest interrupt request number. */ |
AnnaBridge | 171:3a7713b1edbc | 1216 | #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) |
AnnaBridge | 171:3a7713b1edbc | 1217 | |
AnnaBridge | 171:3a7713b1edbc | 1218 | /* PIT module features */ |
AnnaBridge | 171:3a7713b1edbc | 1219 | |
AnnaBridge | 171:3a7713b1edbc | 1220 | /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ |
AnnaBridge | 171:3a7713b1edbc | 1221 | #define FSL_FEATURE_PIT_TIMER_COUNT (2) |
AnnaBridge | 171:3a7713b1edbc | 1222 | /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ |
AnnaBridge | 171:3a7713b1edbc | 1223 | #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) |
AnnaBridge | 171:3a7713b1edbc | 1224 | /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ |
AnnaBridge | 171:3a7713b1edbc | 1225 | #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) |
AnnaBridge | 171:3a7713b1edbc | 1226 | /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ |
AnnaBridge | 171:3a7713b1edbc | 1227 | #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) |
AnnaBridge | 171:3a7713b1edbc | 1228 | |
AnnaBridge | 171:3a7713b1edbc | 1229 | /* PMC module features */ |
AnnaBridge | 171:3a7713b1edbc | 1230 | |
AnnaBridge | 171:3a7713b1edbc | 1231 | /* @brief Has Bandgap Enable In VLPx Operation support. */ |
AnnaBridge | 171:3a7713b1edbc | 1232 | #define FSL_FEATURE_PMC_HAS_BGEN (0) |
AnnaBridge | 171:3a7713b1edbc | 1233 | /* @brief Has Bandgap Buffer Enable. */ |
AnnaBridge | 171:3a7713b1edbc | 1234 | #define FSL_FEATURE_PMC_HAS_BGBE (1) |
AnnaBridge | 171:3a7713b1edbc | 1235 | /* @brief Has Bandgap Buffer Drive Select. */ |
AnnaBridge | 171:3a7713b1edbc | 1236 | #define FSL_FEATURE_PMC_HAS_BGBDS (0) |
AnnaBridge | 171:3a7713b1edbc | 1237 | /* @brief Has Low-Voltage Detect Voltage Select support. */ |
AnnaBridge | 171:3a7713b1edbc | 1238 | #define FSL_FEATURE_PMC_HAS_LVDV (1) |
AnnaBridge | 171:3a7713b1edbc | 1239 | /* @brief Has Low-Voltage Warning Voltage Select support. */ |
AnnaBridge | 171:3a7713b1edbc | 1240 | #define FSL_FEATURE_PMC_HAS_LVWV (1) |
AnnaBridge | 171:3a7713b1edbc | 1241 | /* @brief Has LPO. */ |
AnnaBridge | 171:3a7713b1edbc | 1242 | #define FSL_FEATURE_PMC_HAS_LPO (0) |
AnnaBridge | 171:3a7713b1edbc | 1243 | /* @brief Has VLPx option PMC_REGSC[VLPO]. */ |
AnnaBridge | 171:3a7713b1edbc | 1244 | #define FSL_FEATURE_PMC_HAS_VLPO (1) |
AnnaBridge | 171:3a7713b1edbc | 1245 | /* @brief Has acknowledge isolation support. */ |
AnnaBridge | 171:3a7713b1edbc | 1246 | #define FSL_FEATURE_PMC_HAS_ACKISO (1) |
AnnaBridge | 171:3a7713b1edbc | 1247 | /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ |
AnnaBridge | 171:3a7713b1edbc | 1248 | #define FSL_FEATURE_PMC_HAS_REGFPM (0) |
AnnaBridge | 171:3a7713b1edbc | 1249 | /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ |
AnnaBridge | 171:3a7713b1edbc | 1250 | #define FSL_FEATURE_PMC_HAS_REGONS (1) |
AnnaBridge | 171:3a7713b1edbc | 1251 | /* @brief Has PMC_HVDSC1. */ |
AnnaBridge | 171:3a7713b1edbc | 1252 | #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) |
AnnaBridge | 171:3a7713b1edbc | 1253 | /* @brief Has PMC_PARAM. */ |
AnnaBridge | 171:3a7713b1edbc | 1254 | #define FSL_FEATURE_PMC_HAS_PARAM (0) |
AnnaBridge | 171:3a7713b1edbc | 1255 | /* @brief Has PMC_VERID. */ |
AnnaBridge | 171:3a7713b1edbc | 1256 | #define FSL_FEATURE_PMC_HAS_VERID (0) |
AnnaBridge | 171:3a7713b1edbc | 1257 | |
AnnaBridge | 171:3a7713b1edbc | 1258 | /* PORT module features */ |
AnnaBridge | 171:3a7713b1edbc | 1259 | |
AnnaBridge | 171:3a7713b1edbc | 1260 | /* @brief Has control lock (register bit PCR[LK]). */ |
AnnaBridge | 171:3a7713b1edbc | 1261 | #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) |
AnnaBridge | 171:3a7713b1edbc | 1262 | /* @brief Has open drain control (register bit PCR[ODE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1263 | #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) |
AnnaBridge | 171:3a7713b1edbc | 1264 | /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ |
AnnaBridge | 171:3a7713b1edbc | 1265 | #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) |
AnnaBridge | 171:3a7713b1edbc | 1266 | /* @brief Has DMA request (register bit field PCR[IRQC] values). */ |
AnnaBridge | 171:3a7713b1edbc | 1267 | #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) |
AnnaBridge | 171:3a7713b1edbc | 1268 | /* @brief Has pull resistor selection available. */ |
AnnaBridge | 171:3a7713b1edbc | 1269 | #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) |
AnnaBridge | 171:3a7713b1edbc | 1270 | /* @brief Has pull resistor enable (register bit PCR[PE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1271 | #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) |
AnnaBridge | 171:3a7713b1edbc | 1272 | /* @brief Has slew rate control (register bit PCR[SRE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1273 | #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) |
AnnaBridge | 171:3a7713b1edbc | 1274 | /* @brief Has passive filter (register bit field PCR[PFE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1275 | #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) |
AnnaBridge | 171:3a7713b1edbc | 1276 | /* @brief Has drive strength control (register bit PCR[DSE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1277 | #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) |
AnnaBridge | 171:3a7713b1edbc | 1278 | /* @brief Has separate drive strength register (HDRVE). */ |
AnnaBridge | 171:3a7713b1edbc | 1279 | #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) |
AnnaBridge | 171:3a7713b1edbc | 1280 | /* @brief Has glitch filter (register IOFLT). */ |
AnnaBridge | 171:3a7713b1edbc | 1281 | #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) |
AnnaBridge | 171:3a7713b1edbc | 1282 | /* @brief Defines width of PCR[MUX] field. */ |
AnnaBridge | 171:3a7713b1edbc | 1283 | #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) |
AnnaBridge | 171:3a7713b1edbc | 1284 | /* @brief Has dedicated interrupt vector. */ |
AnnaBridge | 171:3a7713b1edbc | 1285 | #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) |
AnnaBridge | 171:3a7713b1edbc | 1286 | /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ |
AnnaBridge | 171:3a7713b1edbc | 1287 | #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) |
AnnaBridge | 171:3a7713b1edbc | 1288 | /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ |
AnnaBridge | 171:3a7713b1edbc | 1289 | #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) |
AnnaBridge | 171:3a7713b1edbc | 1290 | |
AnnaBridge | 171:3a7713b1edbc | 1291 | /* RADIO module features */ |
AnnaBridge | 171:3a7713b1edbc | 1292 | |
AnnaBridge | 171:3a7713b1edbc | 1293 | /* @brief Zigbee availability. */ |
AnnaBridge | 171:3a7713b1edbc | 1294 | #define FSL_FEATURE_RADIO_HAS_ZIGBEE (1) |
AnnaBridge | 171:3a7713b1edbc | 1295 | /* @brief Bluetooth availability. */ |
AnnaBridge | 171:3a7713b1edbc | 1296 | #define FSL_FEATURE_RADIO_HAS_BLE (1) |
AnnaBridge | 171:3a7713b1edbc | 1297 | /* @brief ANT availability */ |
AnnaBridge | 171:3a7713b1edbc | 1298 | #define FSL_FEATURE_RADIO_HAS_ANT (1) |
AnnaBridge | 171:3a7713b1edbc | 1299 | |
AnnaBridge | 171:3a7713b1edbc | 1300 | /* RCM module features */ |
AnnaBridge | 171:3a7713b1edbc | 1301 | |
AnnaBridge | 171:3a7713b1edbc | 1302 | /* @brief Has Loss-of-Lock Reset support. */ |
AnnaBridge | 171:3a7713b1edbc | 1303 | #define FSL_FEATURE_RCM_HAS_LOL (0) |
AnnaBridge | 171:3a7713b1edbc | 1304 | /* @brief Has Loss-of-Clock Reset support. */ |
AnnaBridge | 171:3a7713b1edbc | 1305 | #define FSL_FEATURE_RCM_HAS_LOC (1) |
AnnaBridge | 171:3a7713b1edbc | 1306 | /* @brief Has JTAG generated Reset support. */ |
AnnaBridge | 171:3a7713b1edbc | 1307 | #define FSL_FEATURE_RCM_HAS_JTAG (0) |
AnnaBridge | 171:3a7713b1edbc | 1308 | /* @brief Has EzPort generated Reset support. */ |
AnnaBridge | 171:3a7713b1edbc | 1309 | #define FSL_FEATURE_RCM_HAS_EZPORT (0) |
AnnaBridge | 171:3a7713b1edbc | 1310 | /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ |
AnnaBridge | 171:3a7713b1edbc | 1311 | #define FSL_FEATURE_RCM_HAS_EZPMS (0) |
AnnaBridge | 171:3a7713b1edbc | 1312 | /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ |
AnnaBridge | 171:3a7713b1edbc | 1313 | #define FSL_FEATURE_RCM_HAS_BOOTROM (0) |
AnnaBridge | 171:3a7713b1edbc | 1314 | /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ |
AnnaBridge | 171:3a7713b1edbc | 1315 | #define FSL_FEATURE_RCM_HAS_SSRS (0) |
AnnaBridge | 171:3a7713b1edbc | 1316 | /* @brief Has Version ID Register (RCM_VERID). */ |
AnnaBridge | 171:3a7713b1edbc | 1317 | #define FSL_FEATURE_RCM_HAS_VERID (0) |
AnnaBridge | 171:3a7713b1edbc | 1318 | /* @brief Has Parameter Register (RCM_PARAM). */ |
AnnaBridge | 171:3a7713b1edbc | 1319 | #define FSL_FEATURE_RCM_HAS_PARAM (0) |
AnnaBridge | 171:3a7713b1edbc | 1320 | /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ |
AnnaBridge | 171:3a7713b1edbc | 1321 | #define FSL_FEATURE_RCM_HAS_SRIE (0) |
AnnaBridge | 171:3a7713b1edbc | 1322 | /* @brief Width of registers of the RCM. */ |
AnnaBridge | 171:3a7713b1edbc | 1323 | #define FSL_FEATURE_RCM_REG_WIDTH (8) |
AnnaBridge | 171:3a7713b1edbc | 1324 | /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ |
AnnaBridge | 171:3a7713b1edbc | 1325 | #define FSL_FEATURE_RCM_HAS_CORE1 (0) |
AnnaBridge | 171:3a7713b1edbc | 1326 | /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ |
AnnaBridge | 171:3a7713b1edbc | 1327 | #define FSL_FEATURE_RCM_HAS_MDM_AP (1) |
AnnaBridge | 171:3a7713b1edbc | 1328 | /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ |
AnnaBridge | 171:3a7713b1edbc | 1329 | #define FSL_FEATURE_RCM_HAS_WAKEUP (1) |
AnnaBridge | 171:3a7713b1edbc | 1330 | |
AnnaBridge | 171:3a7713b1edbc | 1331 | /* RTC module features */ |
AnnaBridge | 171:3a7713b1edbc | 1332 | |
AnnaBridge | 171:3a7713b1edbc | 1333 | /* @brief Has wakeup pin. */ |
AnnaBridge | 171:3a7713b1edbc | 1334 | #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) |
AnnaBridge | 171:3a7713b1edbc | 1335 | /* @brief Has wakeup pin selection (bit field CR[WPS]). */ |
AnnaBridge | 171:3a7713b1edbc | 1336 | #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) |
AnnaBridge | 171:3a7713b1edbc | 1337 | /* @brief Has low power features (registers MER, MCLR and MCHR). */ |
AnnaBridge | 171:3a7713b1edbc | 1338 | #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) |
AnnaBridge | 171:3a7713b1edbc | 1339 | /* @brief Has read/write access control (registers WAR and RAR). */ |
AnnaBridge | 171:3a7713b1edbc | 1340 | #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) |
AnnaBridge | 171:3a7713b1edbc | 1341 | /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ |
AnnaBridge | 171:3a7713b1edbc | 1342 | #define FSL_FEATURE_RTC_HAS_SECURITY (0) |
AnnaBridge | 171:3a7713b1edbc | 1343 | /* @brief Has RTC_CLKIN available. */ |
AnnaBridge | 171:3a7713b1edbc | 1344 | #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) |
AnnaBridge | 171:3a7713b1edbc | 1345 | /* @brief Has prescaler adjust for LPO. */ |
AnnaBridge | 171:3a7713b1edbc | 1346 | #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) |
AnnaBridge | 171:3a7713b1edbc | 1347 | /* @brief Has Clock Pin Enable field. */ |
AnnaBridge | 171:3a7713b1edbc | 1348 | #define FSL_FEATURE_RTC_HAS_CPE (0) |
AnnaBridge | 171:3a7713b1edbc | 1349 | /* @brief Has Timer Seconds Interrupt Configuration field. */ |
AnnaBridge | 171:3a7713b1edbc | 1350 | #define FSL_FEATURE_RTC_HAS_TSIC (0) |
AnnaBridge | 171:3a7713b1edbc | 1351 | /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ |
AnnaBridge | 171:3a7713b1edbc | 1352 | #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) |
AnnaBridge | 171:3a7713b1edbc | 1353 | |
AnnaBridge | 171:3a7713b1edbc | 1354 | /* SIM module features */ |
AnnaBridge | 171:3a7713b1edbc | 1355 | |
AnnaBridge | 171:3a7713b1edbc | 1356 | /* @brief Has USB FS divider. */ |
AnnaBridge | 171:3a7713b1edbc | 1357 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
AnnaBridge | 171:3a7713b1edbc | 1358 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
AnnaBridge | 171:3a7713b1edbc | 1359 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
AnnaBridge | 171:3a7713b1edbc | 1360 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1361 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 1362 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
AnnaBridge | 171:3a7713b1edbc | 1363 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) |
AnnaBridge | 171:3a7713b1edbc | 1364 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1365 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
AnnaBridge | 171:3a7713b1edbc | 1366 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1367 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
AnnaBridge | 171:3a7713b1edbc | 1368 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1369 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) |
AnnaBridge | 171:3a7713b1edbc | 1370 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1371 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
AnnaBridge | 171:3a7713b1edbc | 1372 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
AnnaBridge | 171:3a7713b1edbc | 1373 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
AnnaBridge | 171:3a7713b1edbc | 1374 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
AnnaBridge | 171:3a7713b1edbc | 1375 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
AnnaBridge | 171:3a7713b1edbc | 1376 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1377 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
AnnaBridge | 171:3a7713b1edbc | 1378 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
AnnaBridge | 171:3a7713b1edbc | 1379 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
AnnaBridge | 171:3a7713b1edbc | 1380 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1381 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
AnnaBridge | 171:3a7713b1edbc | 1382 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
AnnaBridge | 171:3a7713b1edbc | 1383 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
AnnaBridge | 171:3a7713b1edbc | 1384 | /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ |
AnnaBridge | 171:3a7713b1edbc | 1385 | #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 1386 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
AnnaBridge | 171:3a7713b1edbc | 1387 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 1388 | /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1389 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) |
AnnaBridge | 171:3a7713b1edbc | 1390 | /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1391 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) |
AnnaBridge | 171:3a7713b1edbc | 1392 | /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1393 | #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) |
AnnaBridge | 171:3a7713b1edbc | 1394 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1395 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) |
AnnaBridge | 171:3a7713b1edbc | 1396 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1397 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
AnnaBridge | 171:3a7713b1edbc | 1398 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
AnnaBridge | 171:3a7713b1edbc | 1399 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
AnnaBridge | 171:3a7713b1edbc | 1400 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1401 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) |
AnnaBridge | 171:3a7713b1edbc | 1402 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1403 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) |
AnnaBridge | 171:3a7713b1edbc | 1404 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1405 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1406 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1407 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1408 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1409 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1410 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1411 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1412 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1413 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1414 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1415 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1416 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1417 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1418 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1419 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1420 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1421 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1422 | /* @brief Has FTM module(s) configuration. */ |
AnnaBridge | 171:3a7713b1edbc | 1423 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) |
AnnaBridge | 171:3a7713b1edbc | 1424 | /* @brief Number of FTM modules. */ |
AnnaBridge | 171:3a7713b1edbc | 1425 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 1426 | /* @brief Number of FTM triggers with selectable source. */ |
AnnaBridge | 171:3a7713b1edbc | 1427 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 1428 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
AnnaBridge | 171:3a7713b1edbc | 1429 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) |
AnnaBridge | 171:3a7713b1edbc | 1430 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
AnnaBridge | 171:3a7713b1edbc | 1431 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
AnnaBridge | 171:3a7713b1edbc | 1432 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1433 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) |
AnnaBridge | 171:3a7713b1edbc | 1434 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1435 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) |
AnnaBridge | 171:3a7713b1edbc | 1436 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1437 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
AnnaBridge | 171:3a7713b1edbc | 1438 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1439 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
AnnaBridge | 171:3a7713b1edbc | 1440 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
AnnaBridge | 171:3a7713b1edbc | 1441 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 1442 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
AnnaBridge | 171:3a7713b1edbc | 1443 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 1444 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
AnnaBridge | 171:3a7713b1edbc | 1445 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 1446 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
AnnaBridge | 171:3a7713b1edbc | 1447 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
AnnaBridge | 171:3a7713b1edbc | 1448 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
AnnaBridge | 171:3a7713b1edbc | 1449 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) |
AnnaBridge | 171:3a7713b1edbc | 1450 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
AnnaBridge | 171:3a7713b1edbc | 1451 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1452 | /* @brief Has TPM module(s) configuration. */ |
AnnaBridge | 171:3a7713b1edbc | 1453 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) |
AnnaBridge | 171:3a7713b1edbc | 1454 | /* @brief The highest TPM module index. */ |
AnnaBridge | 171:3a7713b1edbc | 1455 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) |
AnnaBridge | 171:3a7713b1edbc | 1456 | /* @brief Has TPM module with index 0. */ |
AnnaBridge | 171:3a7713b1edbc | 1457 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) |
AnnaBridge | 171:3a7713b1edbc | 1458 | /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1459 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) |
AnnaBridge | 171:3a7713b1edbc | 1460 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
AnnaBridge | 171:3a7713b1edbc | 1461 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) |
AnnaBridge | 171:3a7713b1edbc | 1462 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1463 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) |
AnnaBridge | 171:3a7713b1edbc | 1464 | /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1465 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) |
AnnaBridge | 171:3a7713b1edbc | 1466 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1467 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) |
AnnaBridge | 171:3a7713b1edbc | 1468 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1469 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) |
AnnaBridge | 171:3a7713b1edbc | 1470 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1471 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) |
AnnaBridge | 171:3a7713b1edbc | 1472 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1473 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) |
AnnaBridge | 171:3a7713b1edbc | 1474 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1475 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1476 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1477 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1478 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1479 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1480 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1481 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1482 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1483 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1484 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1485 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1486 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1487 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1488 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1489 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1490 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1491 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1492 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1493 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1494 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1495 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1496 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1497 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) |
AnnaBridge | 171:3a7713b1edbc | 1498 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1499 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1500 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1501 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1502 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1503 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
AnnaBridge | 171:3a7713b1edbc | 1504 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1505 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) |
AnnaBridge | 171:3a7713b1edbc | 1506 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1507 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) |
AnnaBridge | 171:3a7713b1edbc | 1508 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
AnnaBridge | 171:3a7713b1edbc | 1509 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) |
AnnaBridge | 171:3a7713b1edbc | 1510 | /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ |
AnnaBridge | 171:3a7713b1edbc | 1511 | #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) |
AnnaBridge | 171:3a7713b1edbc | 1512 | /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ |
AnnaBridge | 171:3a7713b1edbc | 1513 | #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1514 | /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ |
AnnaBridge | 171:3a7713b1edbc | 1515 | #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1516 | /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ |
AnnaBridge | 171:3a7713b1edbc | 1517 | #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1518 | /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ |
AnnaBridge | 171:3a7713b1edbc | 1519 | #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1520 | /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ |
AnnaBridge | 171:3a7713b1edbc | 1521 | #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1522 | /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ |
AnnaBridge | 171:3a7713b1edbc | 1523 | #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1524 | /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ |
AnnaBridge | 171:3a7713b1edbc | 1525 | #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1526 | /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ |
AnnaBridge | 171:3a7713b1edbc | 1527 | #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1528 | /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ |
AnnaBridge | 171:3a7713b1edbc | 1529 | #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) |
AnnaBridge | 171:3a7713b1edbc | 1530 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
AnnaBridge | 171:3a7713b1edbc | 1531 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) |
AnnaBridge | 171:3a7713b1edbc | 1532 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
AnnaBridge | 171:3a7713b1edbc | 1533 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
AnnaBridge | 171:3a7713b1edbc | 1534 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
AnnaBridge | 171:3a7713b1edbc | 1535 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
AnnaBridge | 171:3a7713b1edbc | 1536 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
AnnaBridge | 171:3a7713b1edbc | 1537 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) |
AnnaBridge | 171:3a7713b1edbc | 1538 | /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ |
AnnaBridge | 171:3a7713b1edbc | 1539 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) |
AnnaBridge | 171:3a7713b1edbc | 1540 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1541 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
AnnaBridge | 171:3a7713b1edbc | 1542 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1543 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
AnnaBridge | 171:3a7713b1edbc | 1544 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1545 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
AnnaBridge | 171:3a7713b1edbc | 1546 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1547 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
AnnaBridge | 171:3a7713b1edbc | 1548 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1549 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
AnnaBridge | 171:3a7713b1edbc | 1550 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1551 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
AnnaBridge | 171:3a7713b1edbc | 1552 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
AnnaBridge | 171:3a7713b1edbc | 1553 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
AnnaBridge | 171:3a7713b1edbc | 1554 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
AnnaBridge | 171:3a7713b1edbc | 1555 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) |
AnnaBridge | 171:3a7713b1edbc | 1556 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
AnnaBridge | 171:3a7713b1edbc | 1557 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
AnnaBridge | 171:3a7713b1edbc | 1558 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
AnnaBridge | 171:3a7713b1edbc | 1559 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
AnnaBridge | 171:3a7713b1edbc | 1560 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
AnnaBridge | 171:3a7713b1edbc | 1561 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
AnnaBridge | 171:3a7713b1edbc | 1562 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
AnnaBridge | 171:3a7713b1edbc | 1563 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
AnnaBridge | 171:3a7713b1edbc | 1564 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1565 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) |
AnnaBridge | 171:3a7713b1edbc | 1566 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1567 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
AnnaBridge | 171:3a7713b1edbc | 1568 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
AnnaBridge | 171:3a7713b1edbc | 1569 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
AnnaBridge | 171:3a7713b1edbc | 1570 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
AnnaBridge | 171:3a7713b1edbc | 1571 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
AnnaBridge | 171:3a7713b1edbc | 1572 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1573 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 1574 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
AnnaBridge | 171:3a7713b1edbc | 1575 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
AnnaBridge | 171:3a7713b1edbc | 1576 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
AnnaBridge | 171:3a7713b1edbc | 1577 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
AnnaBridge | 171:3a7713b1edbc | 1578 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
AnnaBridge | 171:3a7713b1edbc | 1579 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
AnnaBridge | 171:3a7713b1edbc | 1580 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
AnnaBridge | 171:3a7713b1edbc | 1581 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
AnnaBridge | 171:3a7713b1edbc | 1582 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
AnnaBridge | 171:3a7713b1edbc | 1583 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
AnnaBridge | 171:3a7713b1edbc | 1584 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
AnnaBridge | 171:3a7713b1edbc | 1585 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
AnnaBridge | 171:3a7713b1edbc | 1586 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
AnnaBridge | 171:3a7713b1edbc | 1587 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
AnnaBridge | 171:3a7713b1edbc | 1588 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
AnnaBridge | 171:3a7713b1edbc | 1589 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
AnnaBridge | 171:3a7713b1edbc | 1590 | /* @brief Has miscellanious control register (register MCR). */ |
AnnaBridge | 171:3a7713b1edbc | 1591 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
AnnaBridge | 171:3a7713b1edbc | 1592 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
AnnaBridge | 171:3a7713b1edbc | 1593 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) |
AnnaBridge | 171:3a7713b1edbc | 1594 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
AnnaBridge | 171:3a7713b1edbc | 1595 | #define FSL_FEATURE_SIM_HAS_COP_STOP (1) |
AnnaBridge | 171:3a7713b1edbc | 1596 | /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ |
AnnaBridge | 171:3a7713b1edbc | 1597 | #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) |
AnnaBridge | 171:3a7713b1edbc | 1598 | |
AnnaBridge | 171:3a7713b1edbc | 1599 | /* SMC module features */ |
AnnaBridge | 171:3a7713b1edbc | 1600 | |
AnnaBridge | 171:3a7713b1edbc | 1601 | /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ |
AnnaBridge | 171:3a7713b1edbc | 1602 | #define FSL_FEATURE_SMC_HAS_PSTOPO (1) |
AnnaBridge | 171:3a7713b1edbc | 1603 | /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ |
AnnaBridge | 171:3a7713b1edbc | 1604 | #define FSL_FEATURE_SMC_HAS_LPOPO (0) |
AnnaBridge | 171:3a7713b1edbc | 1605 | /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ |
AnnaBridge | 171:3a7713b1edbc | 1606 | #define FSL_FEATURE_SMC_HAS_PORPO (1) |
AnnaBridge | 171:3a7713b1edbc | 1607 | /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ |
AnnaBridge | 171:3a7713b1edbc | 1608 | #define FSL_FEATURE_SMC_HAS_LPWUI (0) |
AnnaBridge | 171:3a7713b1edbc | 1609 | /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ |
AnnaBridge | 171:3a7713b1edbc | 1610 | #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) |
AnnaBridge | 171:3a7713b1edbc | 1611 | /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ |
AnnaBridge | 171:3a7713b1edbc | 1612 | #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) |
AnnaBridge | 171:3a7713b1edbc | 1613 | /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ |
AnnaBridge | 171:3a7713b1edbc | 1614 | #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) |
AnnaBridge | 171:3a7713b1edbc | 1615 | /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ |
AnnaBridge | 171:3a7713b1edbc | 1616 | #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) |
AnnaBridge | 171:3a7713b1edbc | 1617 | /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ |
AnnaBridge | 171:3a7713b1edbc | 1618 | #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) |
AnnaBridge | 171:3a7713b1edbc | 1619 | /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ |
AnnaBridge | 171:3a7713b1edbc | 1620 | #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) |
AnnaBridge | 171:3a7713b1edbc | 1621 | /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ |
AnnaBridge | 171:3a7713b1edbc | 1622 | #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) |
AnnaBridge | 171:3a7713b1edbc | 1623 | /* @brief Has stop submode. */ |
AnnaBridge | 171:3a7713b1edbc | 1624 | #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) |
AnnaBridge | 171:3a7713b1edbc | 1625 | /* @brief Has stop submode 0(VLLS0). */ |
AnnaBridge | 171:3a7713b1edbc | 1626 | #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) |
AnnaBridge | 171:3a7713b1edbc | 1627 | /* @brief Has stop submode 2(VLLS2). */ |
AnnaBridge | 171:3a7713b1edbc | 1628 | #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) |
AnnaBridge | 171:3a7713b1edbc | 1629 | /* @brief Has SMC_PARAM. */ |
AnnaBridge | 171:3a7713b1edbc | 1630 | #define FSL_FEATURE_SMC_HAS_PARAM (0) |
AnnaBridge | 171:3a7713b1edbc | 1631 | /* @brief Has SMC_VERID. */ |
AnnaBridge | 171:3a7713b1edbc | 1632 | #define FSL_FEATURE_SMC_HAS_VERID (0) |
AnnaBridge | 171:3a7713b1edbc | 1633 | |
AnnaBridge | 171:3a7713b1edbc | 1634 | /* DSPI module features */ |
AnnaBridge | 171:3a7713b1edbc | 1635 | |
AnnaBridge | 171:3a7713b1edbc | 1636 | /* @brief Receive/transmit FIFO size in number of items. */ |
AnnaBridge | 171:3a7713b1edbc | 1637 | #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) |
AnnaBridge | 171:3a7713b1edbc | 1638 | /* @brief Maximum transfer data width in bits. */ |
AnnaBridge | 171:3a7713b1edbc | 1639 | #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) |
AnnaBridge | 171:3a7713b1edbc | 1640 | /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ |
AnnaBridge | 171:3a7713b1edbc | 1641 | #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) |
AnnaBridge | 171:3a7713b1edbc | 1642 | /* @brief Number of chip select pins. */ |
AnnaBridge | 171:3a7713b1edbc | 1643 | #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) |
AnnaBridge | 171:3a7713b1edbc | 1644 | /* @brief Has chip select strobe capability on the PCS5 pin. */ |
AnnaBridge | 171:3a7713b1edbc | 1645 | #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) |
AnnaBridge | 171:3a7713b1edbc | 1646 | /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ |
AnnaBridge | 171:3a7713b1edbc | 1647 | #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) |
AnnaBridge | 171:3a7713b1edbc | 1648 | /* @brief Has 16-bit data transfer support. */ |
AnnaBridge | 171:3a7713b1edbc | 1649 | #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) |
AnnaBridge | 171:3a7713b1edbc | 1650 | /* @brief Has separate DMA RX and TX requests. */ |
AnnaBridge | 171:3a7713b1edbc | 1651 | #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) |
AnnaBridge | 171:3a7713b1edbc | 1652 | |
AnnaBridge | 171:3a7713b1edbc | 1653 | /* SysTick module features */ |
AnnaBridge | 171:3a7713b1edbc | 1654 | |
AnnaBridge | 171:3a7713b1edbc | 1655 | /* @brief Systick has external reference clock. */ |
AnnaBridge | 171:3a7713b1edbc | 1656 | #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) |
AnnaBridge | 171:3a7713b1edbc | 1657 | /* @brief Systick external reference clock is core clock divided by this value. */ |
AnnaBridge | 171:3a7713b1edbc | 1658 | #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) |
AnnaBridge | 171:3a7713b1edbc | 1659 | |
AnnaBridge | 171:3a7713b1edbc | 1660 | /* TPM module features */ |
AnnaBridge | 171:3a7713b1edbc | 1661 | |
AnnaBridge | 171:3a7713b1edbc | 1662 | /* @brief Bus clock is the source clock for the module. */ |
AnnaBridge | 171:3a7713b1edbc | 1663 | #define FSL_FEATURE_TPM_BUS_CLOCK (0) |
AnnaBridge | 171:3a7713b1edbc | 1664 | /* @brief Number of channels. */ |
AnnaBridge | 171:3a7713b1edbc | 1665 | #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ |
AnnaBridge | 171:3a7713b1edbc | 1666 | ((x) == TPM0 ? (4) : \ |
AnnaBridge | 171:3a7713b1edbc | 1667 | ((x) == TPM1 ? (2) : \ |
AnnaBridge | 171:3a7713b1edbc | 1668 | ((x) == TPM2 ? (2) : (-1)))) |
AnnaBridge | 171:3a7713b1edbc | 1669 | /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ |
AnnaBridge | 171:3a7713b1edbc | 1670 | #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) |
AnnaBridge | 171:3a7713b1edbc | 1671 | /* @brief Has TPM_PARAM. */ |
AnnaBridge | 171:3a7713b1edbc | 1672 | #define FSL_FEATURE_TPM_HAS_PARAM (0) |
AnnaBridge | 171:3a7713b1edbc | 1673 | /* @brief Has TPM_VERID. */ |
AnnaBridge | 171:3a7713b1edbc | 1674 | #define FSL_FEATURE_TPM_HAS_VERID (0) |
AnnaBridge | 171:3a7713b1edbc | 1675 | /* @brief Has TPM_GLOBAL. */ |
AnnaBridge | 171:3a7713b1edbc | 1676 | #define FSL_FEATURE_TPM_HAS_GLOBAL (0) |
AnnaBridge | 171:3a7713b1edbc | 1677 | /* @brief Has TPM_TRIG. */ |
AnnaBridge | 171:3a7713b1edbc | 1678 | #define FSL_FEATURE_TPM_HAS_TRIG (0) |
AnnaBridge | 171:3a7713b1edbc | 1679 | /* @brief Has counter pause on trigger. */ |
AnnaBridge | 171:3a7713b1edbc | 1680 | #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) |
AnnaBridge | 171:3a7713b1edbc | 1681 | /* @brief Has external trigger selection. */ |
AnnaBridge | 171:3a7713b1edbc | 1682 | #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) |
AnnaBridge | 171:3a7713b1edbc | 1683 | /* @brief Has TPM_COMBINE register. */ |
AnnaBridge | 171:3a7713b1edbc | 1684 | #define FSL_FEATURE_TPM_HAS_COMBINE (1) |
AnnaBridge | 171:3a7713b1edbc | 1685 | /* @brief Whether COMBINE register has effect. */ |
AnnaBridge | 171:3a7713b1edbc | 1686 | #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ |
AnnaBridge | 171:3a7713b1edbc | 1687 | ((x) == TPM0 ? (0) : \ |
AnnaBridge | 171:3a7713b1edbc | 1688 | ((x) == TPM1 ? (1) : \ |
AnnaBridge | 171:3a7713b1edbc | 1689 | ((x) == TPM2 ? (1) : (-1)))) |
AnnaBridge | 171:3a7713b1edbc | 1690 | /* @brief Has TPM_POL. */ |
AnnaBridge | 171:3a7713b1edbc | 1691 | #define FSL_FEATURE_TPM_HAS_POL (1) |
AnnaBridge | 171:3a7713b1edbc | 1692 | /* @brief Has TPM_FILTER register. */ |
AnnaBridge | 171:3a7713b1edbc | 1693 | #define FSL_FEATURE_TPM_HAS_FILTER (1) |
AnnaBridge | 171:3a7713b1edbc | 1694 | /* @brief Whether FILTER register has effect. */ |
AnnaBridge | 171:3a7713b1edbc | 1695 | #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ |
AnnaBridge | 171:3a7713b1edbc | 1696 | ((x) == TPM0 ? (0) : \ |
AnnaBridge | 171:3a7713b1edbc | 1697 | ((x) == TPM1 ? (1) : \ |
AnnaBridge | 171:3a7713b1edbc | 1698 | ((x) == TPM2 ? (1) : (-1)))) |
AnnaBridge | 171:3a7713b1edbc | 1699 | /* @brief Has TPM_QDCTRL register. */ |
AnnaBridge | 171:3a7713b1edbc | 1700 | #define FSL_FEATURE_TPM_HAS_QDCTRL (1) |
AnnaBridge | 171:3a7713b1edbc | 1701 | /* @brief Whether QDCTRL register has effect. */ |
AnnaBridge | 171:3a7713b1edbc | 1702 | #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ |
AnnaBridge | 171:3a7713b1edbc | 1703 | ((x) == TPM0 ? (0) : \ |
AnnaBridge | 171:3a7713b1edbc | 1704 | ((x) == TPM1 ? (1) : \ |
AnnaBridge | 171:3a7713b1edbc | 1705 | ((x) == TPM2 ? (1) : (-1)))) |
AnnaBridge | 171:3a7713b1edbc | 1706 | |
AnnaBridge | 171:3a7713b1edbc | 1707 | /* TRNG0 module features */ |
AnnaBridge | 171:3a7713b1edbc | 1708 | |
AnnaBridge | 171:3a7713b1edbc | 1709 | /* No feature definitions */ |
AnnaBridge | 171:3a7713b1edbc | 1710 | |
AnnaBridge | 171:3a7713b1edbc | 1711 | /* TSI module features */ |
AnnaBridge | 171:3a7713b1edbc | 1712 | |
AnnaBridge | 171:3a7713b1edbc | 1713 | /* @brief TSI module version. */ |
AnnaBridge | 171:3a7713b1edbc | 1714 | #define FSL_FEATURE_TSI_VERSION (4) |
AnnaBridge | 171:3a7713b1edbc | 1715 | /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ |
AnnaBridge | 171:3a7713b1edbc | 1716 | #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) |
AnnaBridge | 171:3a7713b1edbc | 1717 | /* @brief Number of TSI channels. */ |
AnnaBridge | 171:3a7713b1edbc | 1718 | #define FSL_FEATURE_TSI_CHANNEL_COUNT (16) |
AnnaBridge | 171:3a7713b1edbc | 1719 | |
AnnaBridge | 171:3a7713b1edbc | 1720 | /* VREF module features */ |
AnnaBridge | 171:3a7713b1edbc | 1721 | |
AnnaBridge | 171:3a7713b1edbc | 1722 | /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ |
AnnaBridge | 171:3a7713b1edbc | 1723 | #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) |
AnnaBridge | 171:3a7713b1edbc | 1724 | /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ |
AnnaBridge | 171:3a7713b1edbc | 1725 | #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) |
AnnaBridge | 171:3a7713b1edbc | 1726 | /* @brief If high/low buffer mode supported */ |
AnnaBridge | 171:3a7713b1edbc | 1727 | #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) |
AnnaBridge | 171:3a7713b1edbc | 1728 | /* @brief Module has also low reference (registers VREFL/VREFH) */ |
AnnaBridge | 171:3a7713b1edbc | 1729 | #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) |
AnnaBridge | 171:3a7713b1edbc | 1730 | /* @brief Has VREF_TRM4. */ |
AnnaBridge | 171:3a7713b1edbc | 1731 | #define FSL_FEATURE_VREF_HAS_TRM4 (0) |
AnnaBridge | 171:3a7713b1edbc | 1732 | |
AnnaBridge | 171:3a7713b1edbc | 1733 | #endif /* _MKW41Z4_FEATURES_H_ */ |
AnnaBridge | 171:3a7713b1edbc | 1734 |