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TARGET_KL82Z/TOOLCHAIN_IAR/MKL82Z7_features.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_USENSE/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/MKL82Z7_features.h@167:84c0a372a020 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 145:64910690c574 1 /*
AnnaBridge 145:64910690c574 2 ** ###################################################################
AnnaBridge 145:64910690c574 3 ** Version: rev. 1.6, 2015-12-15
AnnaBridge 145:64910690c574 4 ** Build: b160415
AnnaBridge 145:64910690c574 5 **
AnnaBridge 145:64910690c574 6 ** Abstract:
AnnaBridge 145:64910690c574 7 ** Chip specific module features.
AnnaBridge 145:64910690c574 8 **
AnnaBridge 145:64910690c574 9 ** Copyright (c) 2016 Freescale Semiconductor, Inc.
AnnaBridge 145:64910690c574 10 ** All rights reserved.
AnnaBridge 145:64910690c574 11 **
AnnaBridge 145:64910690c574 12 ** Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 145:64910690c574 13 ** are permitted provided that the following conditions are met:
AnnaBridge 145:64910690c574 14 **
AnnaBridge 145:64910690c574 15 ** o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 145:64910690c574 16 ** of conditions and the following disclaimer.
AnnaBridge 145:64910690c574 17 **
AnnaBridge 145:64910690c574 18 ** o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 145:64910690c574 19 ** list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 145:64910690c574 20 ** other materials provided with the distribution.
AnnaBridge 145:64910690c574 21 **
AnnaBridge 145:64910690c574 22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 145:64910690c574 23 ** contributors may be used to endorse or promote products derived from this
AnnaBridge 145:64910690c574 24 ** software without specific prior written permission.
AnnaBridge 145:64910690c574 25 **
AnnaBridge 145:64910690c574 26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 145:64910690c574 27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 145:64910690c574 28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 145:64910690c574 29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 145:64910690c574 30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 145:64910690c574 31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 145:64910690c574 32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 145:64910690c574 33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 145:64910690c574 34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 145:64910690c574 35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 145:64910690c574 36 **
AnnaBridge 145:64910690c574 37 ** http: www.freescale.com
AnnaBridge 145:64910690c574 38 ** mail: support@freescale.com
AnnaBridge 145:64910690c574 39 **
AnnaBridge 145:64910690c574 40 ** Revisions:
AnnaBridge 145:64910690c574 41 ** - rev. 1.0 (2015-04-20)
AnnaBridge 145:64910690c574 42 ** Initial version.
AnnaBridge 145:64910690c574 43 ** - rev. 1.1 (2015-04-24)
AnnaBridge 145:64910690c574 44 ** Add feature for QSPI
AnnaBridge 145:64910690c574 45 ** - rev. 1.2 (2015-07-29)
AnnaBridge 145:64910690c574 46 ** Add features for LTC and USB KHCI
AnnaBridge 145:64910690c574 47 ** - rev. 1.3 (2015-08-10)
AnnaBridge 145:64910690c574 48 ** Add features for INTMUX and align with 1.3 REL stream
AnnaBridge 145:64910690c574 49 ** - rev. 1.4 (2015-08-13)
AnnaBridge 145:64910690c574 50 ** Add new SIM feature FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER for ADC
AnnaBridge 145:64910690c574 51 ** - rev. 1.5 (2015-08-20)
AnnaBridge 145:64910690c574 52 ** Update according to latest RM Rev.1 and RDP
AnnaBridge 145:64910690c574 53 ** - rev. 1.6 (2015-12-15)
AnnaBridge 145:64910690c574 54 ** Correct USB RAM
AnnaBridge 145:64910690c574 55 **
AnnaBridge 145:64910690c574 56 ** ###################################################################
AnnaBridge 145:64910690c574 57 */
AnnaBridge 145:64910690c574 58
AnnaBridge 145:64910690c574 59 #ifndef _MKL82Z7_FEATURES_H_
AnnaBridge 145:64910690c574 60 #define _MKL82Z7_FEATURES_H_
AnnaBridge 145:64910690c574 61
AnnaBridge 145:64910690c574 62 /* SOC module features */
AnnaBridge 145:64910690c574 63
AnnaBridge 145:64910690c574 64 /* @brief ACMP availability on the SoC. */
AnnaBridge 145:64910690c574 65 #define FSL_FEATURE_SOC_ACMP_COUNT (0)
AnnaBridge 145:64910690c574 66 /* @brief ADC16 availability on the SoC. */
AnnaBridge 145:64910690c574 67 #define FSL_FEATURE_SOC_ADC16_COUNT (1)
AnnaBridge 145:64910690c574 68 /* @brief ADC12 availability on the SoC. */
AnnaBridge 145:64910690c574 69 #define FSL_FEATURE_SOC_ADC12_COUNT (0)
AnnaBridge 145:64910690c574 70 /* @brief AFE availability on the SoC. */
AnnaBridge 145:64910690c574 71 #define FSL_FEATURE_SOC_AFE_COUNT (0)
AnnaBridge 145:64910690c574 72 /* @brief AIPS availability on the SoC. */
AnnaBridge 145:64910690c574 73 #define FSL_FEATURE_SOC_AIPS_COUNT (1)
AnnaBridge 145:64910690c574 74 /* @brief AOI availability on the SoC. */
AnnaBridge 145:64910690c574 75 #define FSL_FEATURE_SOC_AOI_COUNT (0)
AnnaBridge 145:64910690c574 76 /* @brief AXBS availability on the SoC. */
AnnaBridge 145:64910690c574 77 #define FSL_FEATURE_SOC_AXBS_COUNT (0)
AnnaBridge 145:64910690c574 78 /* @brief ASMC availability on the SoC. */
AnnaBridge 145:64910690c574 79 #define FSL_FEATURE_SOC_ASMC_COUNT (0)
AnnaBridge 145:64910690c574 80 /* @brief CADC availability on the SoC. */
AnnaBridge 145:64910690c574 81 #define FSL_FEATURE_SOC_CADC_COUNT (0)
AnnaBridge 145:64910690c574 82 /* @brief FLEXCAN availability on the SoC. */
AnnaBridge 145:64910690c574 83 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
AnnaBridge 145:64910690c574 84 /* @brief MMCAU availability on the SoC. */
AnnaBridge 145:64910690c574 85 #define FSL_FEATURE_SOC_MMCAU_COUNT (0)
AnnaBridge 145:64910690c574 86 /* @brief CMP availability on the SoC. */
AnnaBridge 145:64910690c574 87 #define FSL_FEATURE_SOC_CMP_COUNT (1)
AnnaBridge 145:64910690c574 88 /* @brief CMT availability on the SoC. */
AnnaBridge 145:64910690c574 89 #define FSL_FEATURE_SOC_CMT_COUNT (0)
AnnaBridge 145:64910690c574 90 /* @brief CNC availability on the SoC. */
AnnaBridge 145:64910690c574 91 #define FSL_FEATURE_SOC_CNC_COUNT (0)
AnnaBridge 145:64910690c574 92 /* @brief CRC availability on the SoC. */
AnnaBridge 145:64910690c574 93 #define FSL_FEATURE_SOC_CRC_COUNT (1)
AnnaBridge 145:64910690c574 94 /* @brief DAC availability on the SoC. */
AnnaBridge 145:64910690c574 95 #define FSL_FEATURE_SOC_DAC_COUNT (1)
AnnaBridge 145:64910690c574 96 /* @brief DAC32 availability on the SoC. */
AnnaBridge 145:64910690c574 97 #define FSL_FEATURE_SOC_DAC32_COUNT (0)
AnnaBridge 145:64910690c574 98 /* @brief DCDC availability on the SoC. */
AnnaBridge 145:64910690c574 99 #define FSL_FEATURE_SOC_DCDC_COUNT (0)
AnnaBridge 145:64910690c574 100 /* @brief DDR availability on the SoC. */
AnnaBridge 145:64910690c574 101 #define FSL_FEATURE_SOC_DDR_COUNT (0)
AnnaBridge 145:64910690c574 102 /* @brief DMA availability on the SoC. */
AnnaBridge 145:64910690c574 103 #define FSL_FEATURE_SOC_DMA_COUNT (0)
AnnaBridge 145:64910690c574 104 /* @brief EDMA availability on the SoC. */
AnnaBridge 145:64910690c574 105 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
AnnaBridge 145:64910690c574 106 /* @brief DMAMUX availability on the SoC. */
AnnaBridge 145:64910690c574 107 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
AnnaBridge 145:64910690c574 108 /* @brief DRY availability on the SoC. */
AnnaBridge 145:64910690c574 109 #define FSL_FEATURE_SOC_DRY_COUNT (0)
AnnaBridge 145:64910690c574 110 /* @brief DSPI availability on the SoC. */
AnnaBridge 145:64910690c574 111 #define FSL_FEATURE_SOC_DSPI_COUNT (2)
AnnaBridge 145:64910690c574 112 /* @brief EMVSIM availability on the SoC. */
AnnaBridge 145:64910690c574 113 #define FSL_FEATURE_SOC_EMVSIM_COUNT (2)
AnnaBridge 145:64910690c574 114 /* @brief ENC availability on the SoC. */
AnnaBridge 145:64910690c574 115 #define FSL_FEATURE_SOC_ENC_COUNT (0)
AnnaBridge 145:64910690c574 116 /* @brief ENET availability on the SoC. */
AnnaBridge 145:64910690c574 117 #define FSL_FEATURE_SOC_ENET_COUNT (0)
AnnaBridge 145:64910690c574 118 /* @brief EWM availability on the SoC. */
AnnaBridge 145:64910690c574 119 #define FSL_FEATURE_SOC_EWM_COUNT (1)
AnnaBridge 145:64910690c574 120 /* @brief FB availability on the SoC. */
AnnaBridge 145:64910690c574 121 #define FSL_FEATURE_SOC_FB_COUNT (0)
AnnaBridge 145:64910690c574 122 /* @brief FGPIO availability on the SoC. */
AnnaBridge 145:64910690c574 123 #define FSL_FEATURE_SOC_FGPIO_COUNT (5)
AnnaBridge 145:64910690c574 124 /* @brief FLEXIO availability on the SoC. */
AnnaBridge 145:64910690c574 125 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
AnnaBridge 145:64910690c574 126 /* @brief FMC availability on the SoC. */
AnnaBridge 145:64910690c574 127 #define FSL_FEATURE_SOC_FMC_COUNT (1)
AnnaBridge 145:64910690c574 128 /* @brief FSKDT availability on the SoC. */
AnnaBridge 145:64910690c574 129 #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
AnnaBridge 145:64910690c574 130 /* @brief FTFA availability on the SoC. */
AnnaBridge 145:64910690c574 131 #define FSL_FEATURE_SOC_FTFA_COUNT (1)
AnnaBridge 145:64910690c574 132 /* @brief FTFE availability on the SoC. */
AnnaBridge 145:64910690c574 133 #define FSL_FEATURE_SOC_FTFE_COUNT (0)
AnnaBridge 145:64910690c574 134 /* @brief FTFL availability on the SoC. */
AnnaBridge 145:64910690c574 135 #define FSL_FEATURE_SOC_FTFL_COUNT (0)
AnnaBridge 145:64910690c574 136 /* @brief FTM availability on the SoC. */
AnnaBridge 145:64910690c574 137 #define FSL_FEATURE_SOC_FTM_COUNT (0)
AnnaBridge 145:64910690c574 138 /* @brief FTMRA availability on the SoC. */
AnnaBridge 145:64910690c574 139 #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
AnnaBridge 145:64910690c574 140 /* @brief FTMRE availability on the SoC. */
AnnaBridge 145:64910690c574 141 #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
AnnaBridge 145:64910690c574 142 /* @brief FTMRH availability on the SoC. */
AnnaBridge 145:64910690c574 143 #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
AnnaBridge 145:64910690c574 144 /* @brief GPIO availability on the SoC. */
AnnaBridge 145:64910690c574 145 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
AnnaBridge 145:64910690c574 146 /* @brief HSADC availability on the SoC. */
AnnaBridge 145:64910690c574 147 #define FSL_FEATURE_SOC_HSADC_COUNT (0)
AnnaBridge 145:64910690c574 148 /* @brief I2C availability on the SoC. */
AnnaBridge 145:64910690c574 149 #define FSL_FEATURE_SOC_I2C_COUNT (2)
AnnaBridge 145:64910690c574 150 /* @brief I2S availability on the SoC. */
AnnaBridge 145:64910690c574 151 #define FSL_FEATURE_SOC_I2S_COUNT (0)
AnnaBridge 145:64910690c574 152 /* @brief ICS availability on the SoC. */
AnnaBridge 145:64910690c574 153 #define FSL_FEATURE_SOC_ICS_COUNT (0)
AnnaBridge 145:64910690c574 154 /* @brief INTMUX availability on the SoC. */
AnnaBridge 145:64910690c574 155 #define FSL_FEATURE_SOC_INTMUX_COUNT (1)
AnnaBridge 145:64910690c574 156 /* @brief IRQ availability on the SoC. */
AnnaBridge 145:64910690c574 157 #define FSL_FEATURE_SOC_IRQ_COUNT (0)
AnnaBridge 145:64910690c574 158 /* @brief KBI availability on the SoC. */
AnnaBridge 145:64910690c574 159 #define FSL_FEATURE_SOC_KBI_COUNT (0)
AnnaBridge 145:64910690c574 160 /* @brief SLCD availability on the SoC. */
AnnaBridge 145:64910690c574 161 #define FSL_FEATURE_SOC_SLCD_COUNT (0)
AnnaBridge 145:64910690c574 162 /* @brief LCDC availability on the SoC. */
AnnaBridge 145:64910690c574 163 #define FSL_FEATURE_SOC_LCDC_COUNT (0)
AnnaBridge 145:64910690c574 164 /* @brief LDO availability on the SoC. */
AnnaBridge 145:64910690c574 165 #define FSL_FEATURE_SOC_LDO_COUNT (0)
AnnaBridge 145:64910690c574 166 /* @brief LLWU availability on the SoC. */
AnnaBridge 145:64910690c574 167 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
AnnaBridge 145:64910690c574 168 /* @brief LMEM availability on the SoC. */
AnnaBridge 145:64910690c574 169 #define FSL_FEATURE_SOC_LMEM_COUNT (0)
AnnaBridge 145:64910690c574 170 /* @brief LPI2C availability on the SoC. */
AnnaBridge 145:64910690c574 171 #define FSL_FEATURE_SOC_LPI2C_COUNT (0)
AnnaBridge 145:64910690c574 172 /* @brief LPIT availability on the SoC. */
AnnaBridge 145:64910690c574 173 #define FSL_FEATURE_SOC_LPIT_COUNT (0)
AnnaBridge 145:64910690c574 174 /* @brief LPSCI availability on the SoC. */
AnnaBridge 145:64910690c574 175 #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
AnnaBridge 145:64910690c574 176 /* @brief LPSPI availability on the SoC. */
AnnaBridge 145:64910690c574 177 #define FSL_FEATURE_SOC_LPSPI_COUNT (0)
AnnaBridge 145:64910690c574 178 /* @brief LPTMR availability on the SoC. */
AnnaBridge 145:64910690c574 179 #define FSL_FEATURE_SOC_LPTMR_COUNT (2)
AnnaBridge 145:64910690c574 180 /* @brief LPTPM availability on the SoC. */
AnnaBridge 145:64910690c574 181 #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
AnnaBridge 145:64910690c574 182 /* @brief LPUART availability on the SoC. */
AnnaBridge 145:64910690c574 183 #define FSL_FEATURE_SOC_LPUART_COUNT (3)
AnnaBridge 145:64910690c574 184 /* @brief LTC availability on the SoC. */
AnnaBridge 145:64910690c574 185 #define FSL_FEATURE_SOC_LTC_COUNT (1)
AnnaBridge 145:64910690c574 186 /* @brief MC availability on the SoC. */
AnnaBridge 145:64910690c574 187 #define FSL_FEATURE_SOC_MC_COUNT (0)
AnnaBridge 145:64910690c574 188 /* @brief MCG availability on the SoC. */
AnnaBridge 145:64910690c574 189 #define FSL_FEATURE_SOC_MCG_COUNT (1)
AnnaBridge 145:64910690c574 190 /* @brief MCGLITE availability on the SoC. */
AnnaBridge 145:64910690c574 191 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
AnnaBridge 145:64910690c574 192 /* @brief MCM availability on the SoC. */
AnnaBridge 145:64910690c574 193 #define FSL_FEATURE_SOC_MCM_COUNT (1)
AnnaBridge 145:64910690c574 194 /* @brief MMAU availability on the SoC. */
AnnaBridge 145:64910690c574 195 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
AnnaBridge 145:64910690c574 196 /* @brief MMDVSQ availability on the SoC. */
AnnaBridge 145:64910690c574 197 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
AnnaBridge 145:64910690c574 198 /* @brief MPU availability on the SoC. */
AnnaBridge 145:64910690c574 199 #define FSL_FEATURE_SOC_MPU_COUNT (1)
AnnaBridge 145:64910690c574 200 /* @brief MSCAN availability on the SoC. */
AnnaBridge 145:64910690c574 201 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
AnnaBridge 145:64910690c574 202 /* @brief MSCM availability on the SoC. */
AnnaBridge 145:64910690c574 203 #define FSL_FEATURE_SOC_MSCM_COUNT (0)
AnnaBridge 145:64910690c574 204 /* @brief MTB availability on the SoC. */
AnnaBridge 145:64910690c574 205 #define FSL_FEATURE_SOC_MTB_COUNT (1)
AnnaBridge 145:64910690c574 206 /* @brief MTBDWT availability on the SoC. */
AnnaBridge 145:64910690c574 207 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
AnnaBridge 145:64910690c574 208 /* @brief MU availability on the SoC. */
AnnaBridge 145:64910690c574 209 #define FSL_FEATURE_SOC_MU_COUNT (0)
AnnaBridge 145:64910690c574 210 /* @brief NFC availability on the SoC. */
AnnaBridge 145:64910690c574 211 #define FSL_FEATURE_SOC_NFC_COUNT (0)
AnnaBridge 145:64910690c574 212 /* @brief OPAMP availability on the SoC. */
AnnaBridge 145:64910690c574 213 #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
AnnaBridge 145:64910690c574 214 /* @brief OSC availability on the SoC. */
AnnaBridge 145:64910690c574 215 #define FSL_FEATURE_SOC_OSC_COUNT (1)
AnnaBridge 145:64910690c574 216 /* @brief OSC32 availability on the SoC. */
AnnaBridge 145:64910690c574 217 #define FSL_FEATURE_SOC_OSC32_COUNT (0)
AnnaBridge 145:64910690c574 218 /* @brief OTFAD availability on the SoC. */
AnnaBridge 145:64910690c574 219 #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
AnnaBridge 145:64910690c574 220 /* @brief PDB availability on the SoC. */
AnnaBridge 145:64910690c574 221 #define FSL_FEATURE_SOC_PDB_COUNT (0)
AnnaBridge 145:64910690c574 222 /* @brief PCC availability on the SoC. */
AnnaBridge 145:64910690c574 223 #define FSL_FEATURE_SOC_PCC_COUNT (0)
AnnaBridge 145:64910690c574 224 /* @brief PGA availability on the SoC. */
AnnaBridge 145:64910690c574 225 #define FSL_FEATURE_SOC_PGA_COUNT (0)
AnnaBridge 145:64910690c574 226 /* @brief PIT availability on the SoC. */
AnnaBridge 145:64910690c574 227 #define FSL_FEATURE_SOC_PIT_COUNT (1)
AnnaBridge 145:64910690c574 228 /* @brief PMC availability on the SoC. */
AnnaBridge 145:64910690c574 229 #define FSL_FEATURE_SOC_PMC_COUNT (1)
AnnaBridge 145:64910690c574 230 /* @brief PORT availability on the SoC. */
AnnaBridge 145:64910690c574 231 #define FSL_FEATURE_SOC_PORT_COUNT (5)
AnnaBridge 145:64910690c574 232 /* @brief PWM availability on the SoC. */
AnnaBridge 145:64910690c574 233 #define FSL_FEATURE_SOC_PWM_COUNT (0)
AnnaBridge 145:64910690c574 234 /* @brief PWT availability on the SoC. */
AnnaBridge 145:64910690c574 235 #define FSL_FEATURE_SOC_PWT_COUNT (0)
AnnaBridge 145:64910690c574 236 /* @brief QuadSPI availability on the SoC. */
AnnaBridge 145:64910690c574 237 #define FSL_FEATURE_SOC_QuadSPI_COUNT (1)
AnnaBridge 145:64910690c574 238 /* @brief RCM availability on the SoC. */
AnnaBridge 145:64910690c574 239 #define FSL_FEATURE_SOC_RCM_COUNT (1)
AnnaBridge 145:64910690c574 240 /* @brief RFSYS availability on the SoC. */
AnnaBridge 145:64910690c574 241 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
AnnaBridge 145:64910690c574 242 /* @brief RFVBAT availability on the SoC. */
AnnaBridge 145:64910690c574 243 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
AnnaBridge 145:64910690c574 244 /* @brief RNG availability on the SoC. */
AnnaBridge 145:64910690c574 245 #define FSL_FEATURE_SOC_RNG_COUNT (0)
AnnaBridge 145:64910690c574 246 /* @brief RNGB availability on the SoC. */
AnnaBridge 145:64910690c574 247 #define FSL_FEATURE_SOC_RNGB_COUNT (0)
AnnaBridge 145:64910690c574 248 /* @brief ROM availability on the SoC. */
AnnaBridge 145:64910690c574 249 #define FSL_FEATURE_SOC_ROM_COUNT (1)
AnnaBridge 145:64910690c574 250 /* @brief RSIM availability on the SoC. */
AnnaBridge 145:64910690c574 251 #define FSL_FEATURE_SOC_RSIM_COUNT (0)
AnnaBridge 145:64910690c574 252 /* @brief RTC availability on the SoC. */
AnnaBridge 145:64910690c574 253 #define FSL_FEATURE_SOC_RTC_COUNT (1)
AnnaBridge 145:64910690c574 254 /* @brief SCG availability on the SoC. */
AnnaBridge 145:64910690c574 255 #define FSL_FEATURE_SOC_SCG_COUNT (0)
AnnaBridge 145:64910690c574 256 /* @brief SCI availability on the SoC. */
AnnaBridge 145:64910690c574 257 #define FSL_FEATURE_SOC_SCI_COUNT (0)
AnnaBridge 145:64910690c574 258 /* @brief SDHC availability on the SoC. */
AnnaBridge 145:64910690c574 259 #define FSL_FEATURE_SOC_SDHC_COUNT (0)
AnnaBridge 145:64910690c574 260 /* @brief SDRAM availability on the SoC. */
AnnaBridge 145:64910690c574 261 #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
AnnaBridge 145:64910690c574 262 /* @brief SEMA42 availability on the SoC. */
AnnaBridge 145:64910690c574 263 #define FSL_FEATURE_SOC_SEMA42_COUNT (0)
AnnaBridge 145:64910690c574 264 /* @brief SIM availability on the SoC. */
AnnaBridge 145:64910690c574 265 #define FSL_FEATURE_SOC_SIM_COUNT (1)
AnnaBridge 145:64910690c574 266 /* @brief SMC availability on the SoC. */
AnnaBridge 145:64910690c574 267 #define FSL_FEATURE_SOC_SMC_COUNT (1)
AnnaBridge 145:64910690c574 268 /* @brief SPI availability on the SoC. */
AnnaBridge 145:64910690c574 269 #define FSL_FEATURE_SOC_SPI_COUNT (0)
AnnaBridge 145:64910690c574 270 /* @brief TMR availability on the SoC. */
AnnaBridge 145:64910690c574 271 #define FSL_FEATURE_SOC_TMR_COUNT (0)
AnnaBridge 145:64910690c574 272 /* @brief TPM availability on the SoC. */
AnnaBridge 145:64910690c574 273 #define FSL_FEATURE_SOC_TPM_COUNT (3)
AnnaBridge 145:64910690c574 274 /* @brief TRGMUX availability on the SoC. */
AnnaBridge 145:64910690c574 275 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
AnnaBridge 145:64910690c574 276 /* @brief TRIAMP availability on the SoC. */
AnnaBridge 145:64910690c574 277 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
AnnaBridge 145:64910690c574 278 /* @brief TRNG availability on the SoC. */
AnnaBridge 145:64910690c574 279 #define FSL_FEATURE_SOC_TRNG_COUNT (1)
AnnaBridge 145:64910690c574 280 /* @brief TSI availability on the SoC. */
AnnaBridge 145:64910690c574 281 #define FSL_FEATURE_SOC_TSI_COUNT (1)
AnnaBridge 145:64910690c574 282 /* @brief TSTMR availability on the SoC. */
AnnaBridge 145:64910690c574 283 #define FSL_FEATURE_SOC_TSTMR_COUNT (0)
AnnaBridge 145:64910690c574 284 /* @brief UART availability on the SoC. */
AnnaBridge 145:64910690c574 285 #define FSL_FEATURE_SOC_UART_COUNT (0)
AnnaBridge 145:64910690c574 286 /* @brief USB availability on the SoC. */
AnnaBridge 145:64910690c574 287 #define FSL_FEATURE_SOC_USB_COUNT (1)
AnnaBridge 145:64910690c574 288 /* @brief USBDCD availability on the SoC. */
AnnaBridge 145:64910690c574 289 #define FSL_FEATURE_SOC_USBDCD_COUNT (0)
AnnaBridge 145:64910690c574 290 /* @brief USBHSDCD availability on the SoC. */
AnnaBridge 145:64910690c574 291 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
AnnaBridge 145:64910690c574 292 /* @brief USBPHY availability on the SoC. */
AnnaBridge 145:64910690c574 293 #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
AnnaBridge 145:64910690c574 294 /* @brief VREF availability on the SoC. */
AnnaBridge 145:64910690c574 295 #define FSL_FEATURE_SOC_VREF_COUNT (1)
AnnaBridge 145:64910690c574 296 /* @brief WDOG availability on the SoC. */
AnnaBridge 145:64910690c574 297 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
AnnaBridge 145:64910690c574 298 /* @brief XBAR availability on the SoC. */
AnnaBridge 145:64910690c574 299 #define FSL_FEATURE_SOC_XBAR_COUNT (0)
AnnaBridge 145:64910690c574 300 /* @brief XBARA availability on the SoC. */
AnnaBridge 145:64910690c574 301 #define FSL_FEATURE_SOC_XBARA_COUNT (0)
AnnaBridge 145:64910690c574 302 /* @brief XBARB availability on the SoC. */
AnnaBridge 145:64910690c574 303 #define FSL_FEATURE_SOC_XBARB_COUNT (0)
AnnaBridge 145:64910690c574 304 /* @brief XCVR availability on the SoC. */
AnnaBridge 145:64910690c574 305 #define FSL_FEATURE_SOC_XCVR_COUNT (0)
AnnaBridge 145:64910690c574 306 /* @brief XRDC availability on the SoC. */
AnnaBridge 145:64910690c574 307 #define FSL_FEATURE_SOC_XRDC_COUNT (0)
AnnaBridge 145:64910690c574 308 /* @brief ZLL availability on the SoC. */
AnnaBridge 145:64910690c574 309 #define FSL_FEATURE_SOC_ZLL_COUNT (0)
AnnaBridge 145:64910690c574 310
AnnaBridge 145:64910690c574 311 /* ADC16 module features */
AnnaBridge 145:64910690c574 312
AnnaBridge 145:64910690c574 313 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
AnnaBridge 145:64910690c574 314 #define FSL_FEATURE_ADC16_HAS_PGA (0)
AnnaBridge 145:64910690c574 315 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
AnnaBridge 145:64910690c574 316 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
AnnaBridge 145:64910690c574 317 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
AnnaBridge 145:64910690c574 318 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
AnnaBridge 145:64910690c574 319 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
AnnaBridge 145:64910690c574 320 #define FSL_FEATURE_ADC16_HAS_DMA (1)
AnnaBridge 145:64910690c574 321 /* @brief Has differential mode (bitfield SC1x[DIFF]). */
AnnaBridge 145:64910690c574 322 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
AnnaBridge 145:64910690c574 323 /* @brief Has FIFO (bit SC4[AFDEP]). */
AnnaBridge 145:64910690c574 324 #define FSL_FEATURE_ADC16_HAS_FIFO (0)
AnnaBridge 145:64910690c574 325 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
AnnaBridge 145:64910690c574 326 #define FSL_FEATURE_ADC16_FIFO_SIZE (0)
AnnaBridge 145:64910690c574 327 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
AnnaBridge 145:64910690c574 328 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
AnnaBridge 145:64910690c574 329 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
AnnaBridge 145:64910690c574 330 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
AnnaBridge 145:64910690c574 331 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
AnnaBridge 145:64910690c574 332 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
AnnaBridge 145:64910690c574 333 /* @brief Has HW averaging (bit SC3[AVGE]). */
AnnaBridge 145:64910690c574 334 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
AnnaBridge 145:64910690c574 335 /* @brief Has offset correction (register OFS). */
AnnaBridge 145:64910690c574 336 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
AnnaBridge 145:64910690c574 337 /* @brief Maximum ADC resolution. */
AnnaBridge 145:64910690c574 338 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
AnnaBridge 145:64910690c574 339 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
AnnaBridge 145:64910690c574 340 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
AnnaBridge 145:64910690c574 341
AnnaBridge 145:64910690c574 342 /* CMP module features */
AnnaBridge 145:64910690c574 343
AnnaBridge 145:64910690c574 344 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
AnnaBridge 145:64910690c574 345 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
AnnaBridge 145:64910690c574 346 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */
AnnaBridge 145:64910690c574 347 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
AnnaBridge 145:64910690c574 348 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
AnnaBridge 145:64910690c574 349 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
AnnaBridge 145:64910690c574 350 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
AnnaBridge 145:64910690c574 351 #define FSL_FEATURE_CMP_HAS_DMA (1)
AnnaBridge 145:64910690c574 352 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
AnnaBridge 145:64910690c574 353 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
AnnaBridge 145:64910690c574 354 /* @brief Has DAC Test function in CMP (register DACTEST). */
AnnaBridge 145:64910690c574 355 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
AnnaBridge 145:64910690c574 356
AnnaBridge 145:64910690c574 357 /* CRC module features */
AnnaBridge 145:64910690c574 358
AnnaBridge 145:64910690c574 359 /* @brief Has data register with name CRC */
AnnaBridge 145:64910690c574 360 #define FSL_FEATURE_CRC_HAS_CRC_REG (1)
AnnaBridge 145:64910690c574 361
AnnaBridge 145:64910690c574 362 /* DAC module features */
AnnaBridge 145:64910690c574 363
AnnaBridge 145:64910690c574 364 /* @brief Define the size of hardware buffer */
AnnaBridge 145:64910690c574 365 #define FSL_FEATURE_DAC_BUFFER_SIZE (16)
AnnaBridge 145:64910690c574 366 /* @brief Define whether the buffer supports watermark event detection or not. */
AnnaBridge 145:64910690c574 367 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
AnnaBridge 145:64910690c574 368 /* @brief Define whether the buffer supports watermark selection detection or not. */
AnnaBridge 145:64910690c574 369 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
AnnaBridge 145:64910690c574 370 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
AnnaBridge 145:64910690c574 371 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
AnnaBridge 145:64910690c574 372 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
AnnaBridge 145:64910690c574 373 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
AnnaBridge 145:64910690c574 374 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
AnnaBridge 145:64910690c574 375 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
AnnaBridge 145:64910690c574 376 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
AnnaBridge 145:64910690c574 377 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
AnnaBridge 145:64910690c574 378 /* @brief Define whether FIFO buffer mode is available or not. */
AnnaBridge 145:64910690c574 379 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1)
AnnaBridge 145:64910690c574 380 /* @brief Define whether swing buffer mode is available or not.. */
AnnaBridge 145:64910690c574 381 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
AnnaBridge 145:64910690c574 382
AnnaBridge 145:64910690c574 383 /* EDMA module features */
AnnaBridge 145:64910690c574 384
AnnaBridge 145:64910690c574 385 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
AnnaBridge 145:64910690c574 386 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (8)
AnnaBridge 145:64910690c574 387 /* @brief Total number of DMA channels on all modules. */
AnnaBridge 145:64910690c574 388 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 8)
AnnaBridge 145:64910690c574 389 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
AnnaBridge 145:64910690c574 390 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
AnnaBridge 145:64910690c574 391 /* @brief Has DMA_Error interrupt vector. */
AnnaBridge 145:64910690c574 392 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
AnnaBridge 145:64910690c574 393 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
AnnaBridge 145:64910690c574 394 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (8)
AnnaBridge 145:64910690c574 395
AnnaBridge 145:64910690c574 396 /* DMAMUX module features */
AnnaBridge 145:64910690c574 397
AnnaBridge 145:64910690c574 398 /* @brief Number of DMA channels (related to number of register CHCFGn). */
AnnaBridge 145:64910690c574 399 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (8)
AnnaBridge 145:64910690c574 400 /* @brief Total number of DMA channels on all modules. */
AnnaBridge 145:64910690c574 401 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 8)
AnnaBridge 145:64910690c574 402 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
AnnaBridge 145:64910690c574 403 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
AnnaBridge 145:64910690c574 404
AnnaBridge 145:64910690c574 405 /* EWM module features */
AnnaBridge 145:64910690c574 406
AnnaBridge 145:64910690c574 407 /* @brief Has clock select (register CLKCTRL). */
AnnaBridge 145:64910690c574 408 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
AnnaBridge 145:64910690c574 409 /* @brief Has clock prescaler (register CLKPRESCALER). */
AnnaBridge 145:64910690c574 410 #define FSL_FEATURE_EWM_HAS_PRESCALER (1)
AnnaBridge 145:64910690c574 411
AnnaBridge 145:64910690c574 412 /* FLEXIO module features */
AnnaBridge 145:64910690c574 413
AnnaBridge 145:64910690c574 414 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
AnnaBridge 145:64910690c574 415 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
AnnaBridge 145:64910690c574 416 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */
AnnaBridge 145:64910690c574 417 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
AnnaBridge 145:64910690c574 418 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
AnnaBridge 145:64910690c574 419 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
AnnaBridge 145:64910690c574 420 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
AnnaBridge 145:64910690c574 421 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
AnnaBridge 145:64910690c574 422 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
AnnaBridge 145:64910690c574 423 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
AnnaBridge 145:64910690c574 424 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
AnnaBridge 145:64910690c574 425 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
AnnaBridge 145:64910690c574 426 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
AnnaBridge 145:64910690c574 427 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
AnnaBridge 145:64910690c574 428 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
AnnaBridge 145:64910690c574 429 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
AnnaBridge 145:64910690c574 430 /* @brief Reset value of the FLEXIO_VERID register */
AnnaBridge 145:64910690c574 431 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
AnnaBridge 145:64910690c574 432 /* @brief Reset value of the FLEXIO_PARAM register */
AnnaBridge 145:64910690c574 433 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10200808)
AnnaBridge 145:64910690c574 434 /* @brief Flexio DMA request base channel */
AnnaBridge 145:64910690c574 435 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
AnnaBridge 145:64910690c574 436
AnnaBridge 145:64910690c574 437 /* FLASH module features */
AnnaBridge 145:64910690c574 438
AnnaBridge 145:64910690c574 439 /* @brief Is of type FTFA. */
AnnaBridge 145:64910690c574 440 #define FSL_FEATURE_FLASH_IS_FTFA (1)
AnnaBridge 145:64910690c574 441 /* @brief Is of type FTFE. */
AnnaBridge 145:64910690c574 442 #define FSL_FEATURE_FLASH_IS_FTFE (0)
AnnaBridge 145:64910690c574 443 /* @brief Is of type FTFL. */
AnnaBridge 145:64910690c574 444 #define FSL_FEATURE_FLASH_IS_FTFL (0)
AnnaBridge 145:64910690c574 445 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
AnnaBridge 145:64910690c574 446 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
AnnaBridge 145:64910690c574 447 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
AnnaBridge 145:64910690c574 448 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
AnnaBridge 145:64910690c574 449 /* @brief Has EEPROM region protection (register FEPROT). */
AnnaBridge 145:64910690c574 450 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
AnnaBridge 145:64910690c574 451 /* @brief Has data flash region protection (register FDPROT). */
AnnaBridge 145:64910690c574 452 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
AnnaBridge 145:64910690c574 453 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
AnnaBridge 145:64910690c574 454 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
AnnaBridge 145:64910690c574 455 /* @brief Has flash cache control in FMC module. */
AnnaBridge 145:64910690c574 456 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
AnnaBridge 145:64910690c574 457 /* @brief Has flash cache control in MCM module. */
AnnaBridge 145:64910690c574 458 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
AnnaBridge 145:64910690c574 459 /* @brief Has flash cache control in MSCM module. */
AnnaBridge 145:64910690c574 460 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
AnnaBridge 145:64910690c574 461 /* @brief P-Flash start address. */
AnnaBridge 145:64910690c574 462 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
AnnaBridge 145:64910690c574 463 /* @brief P-Flash block count. */
AnnaBridge 145:64910690c574 464 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
AnnaBridge 145:64910690c574 465 /* @brief P-Flash block size. */
AnnaBridge 145:64910690c574 466 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
AnnaBridge 145:64910690c574 467 /* @brief P-Flash sector size. */
AnnaBridge 145:64910690c574 468 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
AnnaBridge 145:64910690c574 469 /* @brief P-Flash write unit size. */
AnnaBridge 145:64910690c574 470 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
AnnaBridge 145:64910690c574 471 /* @brief P-Flash data path width. */
AnnaBridge 145:64910690c574 472 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
AnnaBridge 145:64910690c574 473 /* @brief P-Flash block swap feature. */
AnnaBridge 145:64910690c574 474 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
AnnaBridge 167:84c0a372a020 475 /* @brief P-Flash protection region count. */
AnnaBridge 167:84c0a372a020 476 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
AnnaBridge 145:64910690c574 477 /* @brief Has FlexNVM memory. */
AnnaBridge 145:64910690c574 478 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
AnnaBridge 145:64910690c574 479 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
AnnaBridge 145:64910690c574 480 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
AnnaBridge 145:64910690c574 481 /* @brief FlexNVM block count. */
AnnaBridge 145:64910690c574 482 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
AnnaBridge 145:64910690c574 483 /* @brief FlexNVM block size. */
AnnaBridge 145:64910690c574 484 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
AnnaBridge 145:64910690c574 485 /* @brief FlexNVM sector size. */
AnnaBridge 145:64910690c574 486 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
AnnaBridge 145:64910690c574 487 /* @brief FlexNVM write unit size. */
AnnaBridge 145:64910690c574 488 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
AnnaBridge 145:64910690c574 489 /* @brief FlexNVM data path width. */
AnnaBridge 145:64910690c574 490 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
AnnaBridge 145:64910690c574 491 /* @brief Has FlexRAM memory. */
AnnaBridge 145:64910690c574 492 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
AnnaBridge 145:64910690c574 493 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
AnnaBridge 145:64910690c574 494 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
AnnaBridge 145:64910690c574 495 /* @brief FlexRAM size. */
AnnaBridge 145:64910690c574 496 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
AnnaBridge 145:64910690c574 497 /* @brief Has 0x00 Read 1s Block command. */
AnnaBridge 145:64910690c574 498 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
AnnaBridge 145:64910690c574 499 /* @brief Has 0x01 Read 1s Section command. */
AnnaBridge 145:64910690c574 500 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
AnnaBridge 145:64910690c574 501 /* @brief Has 0x02 Program Check command. */
AnnaBridge 145:64910690c574 502 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
AnnaBridge 145:64910690c574 503 /* @brief Has 0x03 Read Resource command. */
AnnaBridge 145:64910690c574 504 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
AnnaBridge 145:64910690c574 505 /* @brief Has 0x06 Program Longword command. */
AnnaBridge 145:64910690c574 506 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
AnnaBridge 145:64910690c574 507 /* @brief Has 0x07 Program Phrase command. */
AnnaBridge 145:64910690c574 508 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
AnnaBridge 145:64910690c574 509 /* @brief Has 0x08 Erase Flash Block command. */
AnnaBridge 145:64910690c574 510 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
AnnaBridge 145:64910690c574 511 /* @brief Has 0x09 Erase Flash Sector command. */
AnnaBridge 145:64910690c574 512 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
AnnaBridge 145:64910690c574 513 /* @brief Has 0x0B Program Section command. */
AnnaBridge 145:64910690c574 514 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
AnnaBridge 145:64910690c574 515 /* @brief Has 0x40 Read 1s All Blocks command. */
AnnaBridge 145:64910690c574 516 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
AnnaBridge 145:64910690c574 517 /* @brief Has 0x41 Read Once command. */
AnnaBridge 145:64910690c574 518 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
AnnaBridge 145:64910690c574 519 /* @brief Has 0x43 Program Once command. */
AnnaBridge 145:64910690c574 520 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
AnnaBridge 145:64910690c574 521 /* @brief Has 0x44 Erase All Blocks command. */
AnnaBridge 145:64910690c574 522 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
AnnaBridge 145:64910690c574 523 /* @brief Has 0x45 Verify Backdoor Access Key command. */
AnnaBridge 145:64910690c574 524 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
AnnaBridge 145:64910690c574 525 /* @brief Has 0x46 Swap Control command. */
AnnaBridge 145:64910690c574 526 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
AnnaBridge 145:64910690c574 527 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
AnnaBridge 145:64910690c574 528 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
AnnaBridge 145:64910690c574 529 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
AnnaBridge 145:64910690c574 530 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
AnnaBridge 145:64910690c574 531 /* @brief Has 0x4B Erase All Execute-only Segments command. */
AnnaBridge 145:64910690c574 532 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
AnnaBridge 145:64910690c574 533 /* @brief Has 0x80 Program Partition command. */
AnnaBridge 145:64910690c574 534 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
AnnaBridge 145:64910690c574 535 /* @brief Has 0x81 Set FlexRAM Function command. */
AnnaBridge 145:64910690c574 536 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
AnnaBridge 145:64910690c574 537 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
AnnaBridge 145:64910690c574 538 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge 145:64910690c574 539 /* @brief P-Flash Erase sector command address alignment. */
AnnaBridge 145:64910690c574 540 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
AnnaBridge 145:64910690c574 541 /* @brief P-Flash Rrogram/Verify section command address alignment. */
AnnaBridge 145:64910690c574 542 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
AnnaBridge 145:64910690c574 543 /* @brief P-Flash Read resource command address alignment. */
AnnaBridge 145:64910690c574 544 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge 145:64910690c574 545 /* @brief P-Flash Program check command address alignment. */
AnnaBridge 145:64910690c574 546 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge 145:64910690c574 547 /* @brief P-Flash Program check command address alignment. */
AnnaBridge 145:64910690c574 548 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 145:64910690c574 549 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
AnnaBridge 145:64910690c574 550 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 145:64910690c574 551 /* @brief FlexNVM Erase sector command address alignment. */
AnnaBridge 145:64910690c574 552 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 145:64910690c574 553 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
AnnaBridge 145:64910690c574 554 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 145:64910690c574 555 /* @brief FlexNVM Read resource command address alignment. */
AnnaBridge 145:64910690c574 556 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 145:64910690c574 557 /* @brief FlexNVM Program check command address alignment. */
AnnaBridge 145:64910690c574 558 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 145:64910690c574 559 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 560 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 561 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 562 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 563 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 564 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 565 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 566 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 567 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 568 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 569 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 570 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 571 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 572 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 573 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 574 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 575 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 576 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 577 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 578 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 579 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 580 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 581 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 582 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 583 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 584 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 585 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 586 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 587 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 588 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 589 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 145:64910690c574 590 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
AnnaBridge 145:64910690c574 591 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 592 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
AnnaBridge 145:64910690c574 593 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 594 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
AnnaBridge 145:64910690c574 595 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 596 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
AnnaBridge 145:64910690c574 597 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 598 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
AnnaBridge 145:64910690c574 599 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 600 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
AnnaBridge 145:64910690c574 601 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 602 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
AnnaBridge 145:64910690c574 603 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 604 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
AnnaBridge 145:64910690c574 605 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 606 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
AnnaBridge 145:64910690c574 607 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 608 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
AnnaBridge 145:64910690c574 609 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 610 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
AnnaBridge 145:64910690c574 611 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 612 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
AnnaBridge 145:64910690c574 613 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 614 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
AnnaBridge 145:64910690c574 615 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 616 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
AnnaBridge 145:64910690c574 617 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 618 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
AnnaBridge 145:64910690c574 619 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 620 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
AnnaBridge 145:64910690c574 621 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 145:64910690c574 622 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
AnnaBridge 145:64910690c574 623
AnnaBridge 145:64910690c574 624 /* GPIO module features */
AnnaBridge 145:64910690c574 625
AnnaBridge 145:64910690c574 626 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
AnnaBridge 145:64910690c574 627 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
AnnaBridge 145:64910690c574 628 /* @brief Has port input disable register (PIDR). */
AnnaBridge 145:64910690c574 629 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
AnnaBridge 145:64910690c574 630 /* @brief Has dedicated interrupt vector. */
AnnaBridge 145:64910690c574 631 #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
AnnaBridge 145:64910690c574 632
AnnaBridge 145:64910690c574 633 /* I2C module features */
AnnaBridge 145:64910690c574 634
AnnaBridge 145:64910690c574 635 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
AnnaBridge 145:64910690c574 636 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
AnnaBridge 145:64910690c574 637 /* @brief Maximum supported baud rate in kilobit per second. */
AnnaBridge 145:64910690c574 638 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
AnnaBridge 145:64910690c574 639 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
AnnaBridge 145:64910690c574 640 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
AnnaBridge 145:64910690c574 641 /* @brief Has DMA support (register bit C1[DMAEN]). */
AnnaBridge 145:64910690c574 642 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
AnnaBridge 145:64910690c574 643 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
AnnaBridge 145:64910690c574 644 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
AnnaBridge 145:64910690c574 645 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
AnnaBridge 145:64910690c574 646 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
AnnaBridge 145:64910690c574 647 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
AnnaBridge 145:64910690c574 648 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
AnnaBridge 145:64910690c574 649 /* @brief Maximum width of the glitch filter in number of bus clocks. */
AnnaBridge 145:64910690c574 650 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
AnnaBridge 145:64910690c574 651 /* @brief Has control of the drive capability of the I2C pins. */
AnnaBridge 145:64910690c574 652 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
AnnaBridge 145:64910690c574 653 /* @brief Has double buffering support (register S2). */
AnnaBridge 145:64910690c574 654 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
AnnaBridge 145:64910690c574 655 /* @brief Has double buffer enable. */
AnnaBridge 145:64910690c574 656 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1)
AnnaBridge 145:64910690c574 657
AnnaBridge 145:64910690c574 658 /* INTMUX module features */
AnnaBridge 145:64910690c574 659
AnnaBridge 145:64910690c574 660 /* @brief Number of INTMUX channels (related to number of register CHn_CSR). */
AnnaBridge 145:64910690c574 661 #define FSL_FEATURE_INTMUX_CHANNEL_COUNT (4)
AnnaBridge 145:64910690c574 662 /* @brief Number of INTMUX IRQ source. */
AnnaBridge 145:64910690c574 663 #define FSL_FEATURE_INTMUX_IRQ_COUNT (32)
AnnaBridge 145:64910690c574 664 /* @brief The start IRQ index of first INTMUX source IRQ. */
AnnaBridge 145:64910690c574 665 #define FSL_FEATURE_INTMUX_IRQ_START_INDEX (32)
AnnaBridge 145:64910690c574 666
AnnaBridge 145:64910690c574 667 /* LLWU module features */
AnnaBridge 145:64910690c574 668
AnnaBridge 145:64910690c574 669 #if defined(CPU_MKL82Z128VLH7) || defined(CPU_MKL82Z128VLK7) || defined(CPU_MKL82Z128VMP7)
AnnaBridge 145:64910690c574 670 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
AnnaBridge 145:64910690c574 671 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
AnnaBridge 145:64910690c574 672 /* @brief Has pins 8-15 connected to LLWU device. */
AnnaBridge 145:64910690c574 673 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
AnnaBridge 145:64910690c574 674 /* @brief Maximum number of internal modules connected to LLWU device. */
AnnaBridge 145:64910690c574 675 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
AnnaBridge 145:64910690c574 676 /* @brief Number of digital filters. */
AnnaBridge 145:64910690c574 677 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
AnnaBridge 145:64910690c574 678 /* @brief Has MF register. */
AnnaBridge 145:64910690c574 679 #define FSL_FEATURE_LLWU_HAS_MF (1)
AnnaBridge 145:64910690c574 680 /* @brief Has PF register. */
AnnaBridge 145:64910690c574 681 #define FSL_FEATURE_LLWU_HAS_PF (1)
AnnaBridge 145:64910690c574 682 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
AnnaBridge 145:64910690c574 683 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
AnnaBridge 145:64910690c574 684 /* @brief Has external pin 0 connected to LLWU device. */
AnnaBridge 145:64910690c574 685 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
AnnaBridge 145:64910690c574 686 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 687 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 688 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 689 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
AnnaBridge 145:64910690c574 690 /* @brief Has external pin 1 connected to LLWU device. */
AnnaBridge 145:64910690c574 691 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
AnnaBridge 145:64910690c574 692 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 693 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 694 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 695 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
AnnaBridge 145:64910690c574 696 /* @brief Has external pin 2 connected to LLWU device. */
AnnaBridge 145:64910690c574 697 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
AnnaBridge 145:64910690c574 698 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 699 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 700 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 701 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
AnnaBridge 145:64910690c574 702 /* @brief Has external pin 3 connected to LLWU device. */
AnnaBridge 145:64910690c574 703 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
AnnaBridge 145:64910690c574 704 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 705 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
AnnaBridge 145:64910690c574 706 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 707 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
AnnaBridge 145:64910690c574 708 /* @brief Has external pin 4 connected to LLWU device. */
AnnaBridge 145:64910690c574 709 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0)
AnnaBridge 145:64910690c574 710 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 711 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0)
AnnaBridge 145:64910690c574 712 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 713 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0)
AnnaBridge 145:64910690c574 714 /* @brief Has external pin 5 connected to LLWU device. */
AnnaBridge 145:64910690c574 715 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
AnnaBridge 145:64910690c574 716 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 717 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
AnnaBridge 145:64910690c574 718 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 719 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
AnnaBridge 145:64910690c574 720 /* @brief Has external pin 6 connected to LLWU device. */
AnnaBridge 145:64910690c574 721 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
AnnaBridge 145:64910690c574 722 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 723 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 724 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 725 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
AnnaBridge 145:64910690c574 726 /* @brief Has external pin 7 connected to LLWU device. */
AnnaBridge 145:64910690c574 727 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
AnnaBridge 145:64910690c574 728 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 729 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 730 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 731 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
AnnaBridge 145:64910690c574 732 /* @brief Has external pin 8 connected to LLWU device. */
AnnaBridge 145:64910690c574 733 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
AnnaBridge 145:64910690c574 734 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 735 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 736 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 737 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
AnnaBridge 145:64910690c574 738 /* @brief Has external pin 9 connected to LLWU device. */
AnnaBridge 145:64910690c574 739 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
AnnaBridge 145:64910690c574 740 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 741 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 742 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 743 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
AnnaBridge 145:64910690c574 744 /* @brief Has external pin 10 connected to LLWU device. */
AnnaBridge 145:64910690c574 745 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
AnnaBridge 145:64910690c574 746 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 747 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 748 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 749 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
AnnaBridge 145:64910690c574 750 /* @brief Has external pin 11 connected to LLWU device. */
AnnaBridge 145:64910690c574 751 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
AnnaBridge 145:64910690c574 752 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 753 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 754 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 755 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
AnnaBridge 145:64910690c574 756 /* @brief Has external pin 12 connected to LLWU device. */
AnnaBridge 145:64910690c574 757 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
AnnaBridge 145:64910690c574 758 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 759 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 760 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 761 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
AnnaBridge 145:64910690c574 762 /* @brief Has external pin 13 connected to LLWU device. */
AnnaBridge 145:64910690c574 763 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
AnnaBridge 145:64910690c574 764 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 765 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 766 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 767 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
AnnaBridge 145:64910690c574 768 /* @brief Has external pin 14 connected to LLWU device. */
AnnaBridge 145:64910690c574 769 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
AnnaBridge 145:64910690c574 770 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 771 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 772 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 773 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
AnnaBridge 145:64910690c574 774 /* @brief Has external pin 15 connected to LLWU device. */
AnnaBridge 145:64910690c574 775 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
AnnaBridge 145:64910690c574 776 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 777 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 778 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 779 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
AnnaBridge 145:64910690c574 780 /* @brief Has external pin 16 connected to LLWU device. */
AnnaBridge 145:64910690c574 781 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
AnnaBridge 145:64910690c574 782 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 783 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
AnnaBridge 145:64910690c574 784 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 785 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
AnnaBridge 145:64910690c574 786 /* @brief Has external pin 17 connected to LLWU device. */
AnnaBridge 145:64910690c574 787 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
AnnaBridge 145:64910690c574 788 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 789 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
AnnaBridge 145:64910690c574 790 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 791 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
AnnaBridge 145:64910690c574 792 /* @brief Has external pin 18 connected to LLWU device. */
AnnaBridge 145:64910690c574 793 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
AnnaBridge 145:64910690c574 794 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 795 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
AnnaBridge 145:64910690c574 796 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 797 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
AnnaBridge 145:64910690c574 798 /* @brief Has external pin 19 connected to LLWU device. */
AnnaBridge 145:64910690c574 799 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
AnnaBridge 145:64910690c574 800 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 801 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
AnnaBridge 145:64910690c574 802 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 803 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
AnnaBridge 145:64910690c574 804 /* @brief Has external pin 20 connected to LLWU device. */
AnnaBridge 145:64910690c574 805 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
AnnaBridge 145:64910690c574 806 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 807 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
AnnaBridge 145:64910690c574 808 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 809 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
AnnaBridge 145:64910690c574 810 /* @brief Has external pin 21 connected to LLWU device. */
AnnaBridge 145:64910690c574 811 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
AnnaBridge 145:64910690c574 812 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 813 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
AnnaBridge 145:64910690c574 814 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 815 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
AnnaBridge 145:64910690c574 816 /* @brief Has external pin 22 connected to LLWU device. */
AnnaBridge 145:64910690c574 817 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
AnnaBridge 145:64910690c574 818 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 819 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
AnnaBridge 145:64910690c574 820 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 821 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
AnnaBridge 145:64910690c574 822 /* @brief Has external pin 23 connected to LLWU device. */
AnnaBridge 145:64910690c574 823 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
AnnaBridge 145:64910690c574 824 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 825 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
AnnaBridge 145:64910690c574 826 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 827 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
AnnaBridge 145:64910690c574 828 /* @brief Has external pin 24 connected to LLWU device. */
AnnaBridge 145:64910690c574 829 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
AnnaBridge 145:64910690c574 830 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 831 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
AnnaBridge 145:64910690c574 832 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 833 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
AnnaBridge 145:64910690c574 834 /* @brief Has external pin 25 connected to LLWU device. */
AnnaBridge 145:64910690c574 835 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
AnnaBridge 145:64910690c574 836 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 837 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
AnnaBridge 145:64910690c574 838 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 839 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
AnnaBridge 145:64910690c574 840 /* @brief Has external pin 26 connected to LLWU device. */
AnnaBridge 145:64910690c574 841 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
AnnaBridge 145:64910690c574 842 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 843 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
AnnaBridge 145:64910690c574 844 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 845 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
AnnaBridge 145:64910690c574 846 /* @brief Has external pin 27 connected to LLWU device. */
AnnaBridge 145:64910690c574 847 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
AnnaBridge 145:64910690c574 848 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 849 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
AnnaBridge 145:64910690c574 850 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 851 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
AnnaBridge 145:64910690c574 852 /* @brief Has external pin 28 connected to LLWU device. */
AnnaBridge 145:64910690c574 853 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
AnnaBridge 145:64910690c574 854 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 855 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
AnnaBridge 145:64910690c574 856 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 857 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
AnnaBridge 145:64910690c574 858 /* @brief Has external pin 29 connected to LLWU device. */
AnnaBridge 145:64910690c574 859 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
AnnaBridge 145:64910690c574 860 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 861 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
AnnaBridge 145:64910690c574 862 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 863 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
AnnaBridge 145:64910690c574 864 /* @brief Has external pin 30 connected to LLWU device. */
AnnaBridge 145:64910690c574 865 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
AnnaBridge 145:64910690c574 866 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 867 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
AnnaBridge 145:64910690c574 868 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 869 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
AnnaBridge 145:64910690c574 870 /* @brief Has external pin 31 connected to LLWU device. */
AnnaBridge 145:64910690c574 871 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
AnnaBridge 145:64910690c574 872 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 873 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
AnnaBridge 145:64910690c574 874 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 875 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
AnnaBridge 145:64910690c574 876 /* @brief Has internal module 0 connected to LLWU device. */
AnnaBridge 145:64910690c574 877 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
AnnaBridge 145:64910690c574 878 /* @brief Has internal module 1 connected to LLWU device. */
AnnaBridge 145:64910690c574 879 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
AnnaBridge 145:64910690c574 880 /* @brief Has internal module 2 connected to LLWU device. */
AnnaBridge 145:64910690c574 881 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
AnnaBridge 145:64910690c574 882 /* @brief Has internal module 3 connected to LLWU device. */
AnnaBridge 145:64910690c574 883 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
AnnaBridge 145:64910690c574 884 /* @brief Has internal module 4 connected to LLWU device. */
AnnaBridge 145:64910690c574 885 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
AnnaBridge 145:64910690c574 886 /* @brief Has internal module 5 connected to LLWU device. */
AnnaBridge 145:64910690c574 887 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
AnnaBridge 145:64910690c574 888 /* @brief Has internal module 6 connected to LLWU device. */
AnnaBridge 145:64910690c574 889 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
AnnaBridge 145:64910690c574 890 /* @brief Has internal module 7 connected to LLWU device. */
AnnaBridge 145:64910690c574 891 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
AnnaBridge 145:64910690c574 892 /* @brief Has Version ID Register (LLWU_VERID). */
AnnaBridge 145:64910690c574 893 #define FSL_FEATURE_LLWU_HAS_VERID (0)
AnnaBridge 145:64910690c574 894 /* @brief Has Parameter Register (LLWU_PARAM). */
AnnaBridge 145:64910690c574 895 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
AnnaBridge 145:64910690c574 896 /* @brief Width of registers of the LLWU. */
AnnaBridge 145:64910690c574 897 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
AnnaBridge 145:64910690c574 898 /* @brief Has DMA Enable register (LLWU_DE). */
AnnaBridge 145:64910690c574 899 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
AnnaBridge 145:64910690c574 900 #elif defined(CPU_MKL82Z128VLL7)
AnnaBridge 145:64910690c574 901 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
AnnaBridge 145:64910690c574 902 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (19)
AnnaBridge 145:64910690c574 903 /* @brief Has pins 8-15 connected to LLWU device. */
AnnaBridge 145:64910690c574 904 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
AnnaBridge 145:64910690c574 905 /* @brief Maximum number of internal modules connected to LLWU device. */
AnnaBridge 145:64910690c574 906 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
AnnaBridge 145:64910690c574 907 /* @brief Number of digital filters. */
AnnaBridge 145:64910690c574 908 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
AnnaBridge 145:64910690c574 909 /* @brief Has MF register. */
AnnaBridge 145:64910690c574 910 #define FSL_FEATURE_LLWU_HAS_MF (1)
AnnaBridge 145:64910690c574 911 /* @brief Has PF register. */
AnnaBridge 145:64910690c574 912 #define FSL_FEATURE_LLWU_HAS_PF (1)
AnnaBridge 145:64910690c574 913 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
AnnaBridge 145:64910690c574 914 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
AnnaBridge 145:64910690c574 915 /* @brief Has external pin 0 connected to LLWU device. */
AnnaBridge 145:64910690c574 916 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
AnnaBridge 145:64910690c574 917 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 918 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 919 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 920 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
AnnaBridge 145:64910690c574 921 /* @brief Has external pin 1 connected to LLWU device. */
AnnaBridge 145:64910690c574 922 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
AnnaBridge 145:64910690c574 923 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 924 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 925 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 926 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
AnnaBridge 145:64910690c574 927 /* @brief Has external pin 2 connected to LLWU device. */
AnnaBridge 145:64910690c574 928 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
AnnaBridge 145:64910690c574 929 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 930 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 931 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 932 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
AnnaBridge 145:64910690c574 933 /* @brief Has external pin 3 connected to LLWU device. */
AnnaBridge 145:64910690c574 934 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
AnnaBridge 145:64910690c574 935 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 936 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
AnnaBridge 145:64910690c574 937 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 938 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
AnnaBridge 145:64910690c574 939 /* @brief Has external pin 4 connected to LLWU device. */
AnnaBridge 145:64910690c574 940 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
AnnaBridge 145:64910690c574 941 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 942 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
AnnaBridge 145:64910690c574 943 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 944 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
AnnaBridge 145:64910690c574 945 /* @brief Has external pin 5 connected to LLWU device. */
AnnaBridge 145:64910690c574 946 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
AnnaBridge 145:64910690c574 947 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 948 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
AnnaBridge 145:64910690c574 949 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 950 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
AnnaBridge 145:64910690c574 951 /* @brief Has external pin 6 connected to LLWU device. */
AnnaBridge 145:64910690c574 952 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
AnnaBridge 145:64910690c574 953 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 954 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 955 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 956 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
AnnaBridge 145:64910690c574 957 /* @brief Has external pin 7 connected to LLWU device. */
AnnaBridge 145:64910690c574 958 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
AnnaBridge 145:64910690c574 959 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 960 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 961 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 962 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
AnnaBridge 145:64910690c574 963 /* @brief Has external pin 8 connected to LLWU device. */
AnnaBridge 145:64910690c574 964 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
AnnaBridge 145:64910690c574 965 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 966 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 967 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 968 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
AnnaBridge 145:64910690c574 969 /* @brief Has external pin 9 connected to LLWU device. */
AnnaBridge 145:64910690c574 970 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
AnnaBridge 145:64910690c574 971 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 972 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 973 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 974 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
AnnaBridge 145:64910690c574 975 /* @brief Has external pin 10 connected to LLWU device. */
AnnaBridge 145:64910690c574 976 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
AnnaBridge 145:64910690c574 977 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 978 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 979 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 980 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
AnnaBridge 145:64910690c574 981 /* @brief Has external pin 11 connected to LLWU device. */
AnnaBridge 145:64910690c574 982 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
AnnaBridge 145:64910690c574 983 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 984 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 985 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 986 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
AnnaBridge 145:64910690c574 987 /* @brief Has external pin 12 connected to LLWU device. */
AnnaBridge 145:64910690c574 988 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
AnnaBridge 145:64910690c574 989 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 990 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 991 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 992 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
AnnaBridge 145:64910690c574 993 /* @brief Has external pin 13 connected to LLWU device. */
AnnaBridge 145:64910690c574 994 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
AnnaBridge 145:64910690c574 995 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 996 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 997 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 998 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
AnnaBridge 145:64910690c574 999 /* @brief Has external pin 14 connected to LLWU device. */
AnnaBridge 145:64910690c574 1000 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
AnnaBridge 145:64910690c574 1001 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1002 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 1003 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1004 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
AnnaBridge 145:64910690c574 1005 /* @brief Has external pin 15 connected to LLWU device. */
AnnaBridge 145:64910690c574 1006 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
AnnaBridge 145:64910690c574 1007 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1008 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 1009 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1010 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
AnnaBridge 145:64910690c574 1011 /* @brief Has external pin 16 connected to LLWU device. */
AnnaBridge 145:64910690c574 1012 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
AnnaBridge 145:64910690c574 1013 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1014 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 1015 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1016 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6)
AnnaBridge 145:64910690c574 1017 /* @brief Has external pin 17 connected to LLWU device. */
AnnaBridge 145:64910690c574 1018 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
AnnaBridge 145:64910690c574 1019 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1020 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 1021 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1022 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9)
AnnaBridge 145:64910690c574 1023 /* @brief Has external pin 18 connected to LLWU device. */
AnnaBridge 145:64910690c574 1024 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
AnnaBridge 145:64910690c574 1025 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1026 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 1027 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1028 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10)
AnnaBridge 145:64910690c574 1029 /* @brief Has external pin 19 connected to LLWU device. */
AnnaBridge 145:64910690c574 1030 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
AnnaBridge 145:64910690c574 1031 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1032 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1033 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1034 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1035 /* @brief Has external pin 20 connected to LLWU device. */
AnnaBridge 145:64910690c574 1036 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
AnnaBridge 145:64910690c574 1037 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1038 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1039 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1040 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1041 /* @brief Has external pin 21 connected to LLWU device. */
AnnaBridge 145:64910690c574 1042 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
AnnaBridge 145:64910690c574 1043 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1044 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1045 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1046 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1047 /* @brief Has external pin 22 connected to LLWU device. */
AnnaBridge 145:64910690c574 1048 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
AnnaBridge 145:64910690c574 1049 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1050 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1051 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1052 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1053 /* @brief Has external pin 23 connected to LLWU device. */
AnnaBridge 145:64910690c574 1054 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
AnnaBridge 145:64910690c574 1055 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1056 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1057 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1058 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1059 /* @brief Has external pin 24 connected to LLWU device. */
AnnaBridge 145:64910690c574 1060 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
AnnaBridge 145:64910690c574 1061 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1062 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1063 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1064 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1065 /* @brief Has external pin 25 connected to LLWU device. */
AnnaBridge 145:64910690c574 1066 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
AnnaBridge 145:64910690c574 1067 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1068 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1069 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1070 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1071 /* @brief Has external pin 26 connected to LLWU device. */
AnnaBridge 145:64910690c574 1072 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
AnnaBridge 145:64910690c574 1073 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1074 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1075 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1076 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1077 /* @brief Has external pin 27 connected to LLWU device. */
AnnaBridge 145:64910690c574 1078 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
AnnaBridge 145:64910690c574 1079 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1080 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1081 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1082 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1083 /* @brief Has external pin 28 connected to LLWU device. */
AnnaBridge 145:64910690c574 1084 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
AnnaBridge 145:64910690c574 1085 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1086 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1087 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1088 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1089 /* @brief Has external pin 29 connected to LLWU device. */
AnnaBridge 145:64910690c574 1090 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
AnnaBridge 145:64910690c574 1091 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1092 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1093 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1094 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1095 /* @brief Has external pin 30 connected to LLWU device. */
AnnaBridge 145:64910690c574 1096 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
AnnaBridge 145:64910690c574 1097 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1098 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1099 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1100 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1101 /* @brief Has external pin 31 connected to LLWU device. */
AnnaBridge 145:64910690c574 1102 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
AnnaBridge 145:64910690c574 1103 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1104 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1105 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1106 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1107 /* @brief Has internal module 0 connected to LLWU device. */
AnnaBridge 145:64910690c574 1108 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
AnnaBridge 145:64910690c574 1109 /* @brief Has internal module 1 connected to LLWU device. */
AnnaBridge 145:64910690c574 1110 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
AnnaBridge 145:64910690c574 1111 /* @brief Has internal module 2 connected to LLWU device. */
AnnaBridge 145:64910690c574 1112 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
AnnaBridge 145:64910690c574 1113 /* @brief Has internal module 3 connected to LLWU device. */
AnnaBridge 145:64910690c574 1114 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
AnnaBridge 145:64910690c574 1115 /* @brief Has internal module 4 connected to LLWU device. */
AnnaBridge 145:64910690c574 1116 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
AnnaBridge 145:64910690c574 1117 /* @brief Has internal module 5 connected to LLWU device. */
AnnaBridge 145:64910690c574 1118 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
AnnaBridge 145:64910690c574 1119 /* @brief Has internal module 6 connected to LLWU device. */
AnnaBridge 145:64910690c574 1120 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
AnnaBridge 145:64910690c574 1121 /* @brief Has internal module 7 connected to LLWU device. */
AnnaBridge 145:64910690c574 1122 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
AnnaBridge 145:64910690c574 1123 /* @brief Has Version ID Register (LLWU_VERID). */
AnnaBridge 145:64910690c574 1124 #define FSL_FEATURE_LLWU_HAS_VERID (0)
AnnaBridge 145:64910690c574 1125 /* @brief Has Parameter Register (LLWU_PARAM). */
AnnaBridge 145:64910690c574 1126 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
AnnaBridge 145:64910690c574 1127 /* @brief Width of registers of the LLWU. */
AnnaBridge 145:64910690c574 1128 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
AnnaBridge 145:64910690c574 1129 /* @brief Has DMA Enable register (LLWU_DE). */
AnnaBridge 145:64910690c574 1130 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
AnnaBridge 145:64910690c574 1131 #elif defined(CPU_MKL82Z128VMC7)
AnnaBridge 145:64910690c574 1132 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
AnnaBridge 145:64910690c574 1133 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (26)
AnnaBridge 145:64910690c574 1134 /* @brief Has pins 8-15 connected to LLWU device. */
AnnaBridge 145:64910690c574 1135 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
AnnaBridge 145:64910690c574 1136 /* @brief Maximum number of internal modules connected to LLWU device. */
AnnaBridge 145:64910690c574 1137 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
AnnaBridge 145:64910690c574 1138 /* @brief Number of digital filters. */
AnnaBridge 145:64910690c574 1139 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
AnnaBridge 145:64910690c574 1140 /* @brief Has MF register. */
AnnaBridge 145:64910690c574 1141 #define FSL_FEATURE_LLWU_HAS_MF (1)
AnnaBridge 145:64910690c574 1142 /* @brief Has PF register. */
AnnaBridge 145:64910690c574 1143 #define FSL_FEATURE_LLWU_HAS_PF (1)
AnnaBridge 145:64910690c574 1144 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
AnnaBridge 145:64910690c574 1145 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
AnnaBridge 145:64910690c574 1146 /* @brief Has external pin 0 connected to LLWU device. */
AnnaBridge 145:64910690c574 1147 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
AnnaBridge 145:64910690c574 1148 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1149 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 1150 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1151 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
AnnaBridge 145:64910690c574 1152 /* @brief Has external pin 1 connected to LLWU device. */
AnnaBridge 145:64910690c574 1153 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
AnnaBridge 145:64910690c574 1154 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1155 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 1156 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1157 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
AnnaBridge 145:64910690c574 1158 /* @brief Has external pin 2 connected to LLWU device. */
AnnaBridge 145:64910690c574 1159 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
AnnaBridge 145:64910690c574 1160 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1161 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 1162 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1163 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
AnnaBridge 145:64910690c574 1164 /* @brief Has external pin 3 connected to LLWU device. */
AnnaBridge 145:64910690c574 1165 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
AnnaBridge 145:64910690c574 1166 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1167 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
AnnaBridge 145:64910690c574 1168 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1169 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
AnnaBridge 145:64910690c574 1170 /* @brief Has external pin 4 connected to LLWU device. */
AnnaBridge 145:64910690c574 1171 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
AnnaBridge 145:64910690c574 1172 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1173 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
AnnaBridge 145:64910690c574 1174 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1175 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
AnnaBridge 145:64910690c574 1176 /* @brief Has external pin 5 connected to LLWU device. */
AnnaBridge 145:64910690c574 1177 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
AnnaBridge 145:64910690c574 1178 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1179 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
AnnaBridge 145:64910690c574 1180 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1181 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1182 /* @brief Has external pin 6 connected to LLWU device. */
AnnaBridge 145:64910690c574 1183 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
AnnaBridge 145:64910690c574 1184 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1185 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 1186 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1187 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
AnnaBridge 145:64910690c574 1188 /* @brief Has external pin 7 connected to LLWU device. */
AnnaBridge 145:64910690c574 1189 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
AnnaBridge 145:64910690c574 1190 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1191 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 1192 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1193 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
AnnaBridge 145:64910690c574 1194 /* @brief Has external pin 8 connected to LLWU device. */
AnnaBridge 145:64910690c574 1195 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
AnnaBridge 145:64910690c574 1196 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1197 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 1198 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1199 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
AnnaBridge 145:64910690c574 1200 /* @brief Has external pin 9 connected to LLWU device. */
AnnaBridge 145:64910690c574 1201 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
AnnaBridge 145:64910690c574 1202 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1203 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 1204 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1205 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
AnnaBridge 145:64910690c574 1206 /* @brief Has external pin 10 connected to LLWU device. */
AnnaBridge 145:64910690c574 1207 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
AnnaBridge 145:64910690c574 1208 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1209 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 1210 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1211 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
AnnaBridge 145:64910690c574 1212 /* @brief Has external pin 11 connected to LLWU device. */
AnnaBridge 145:64910690c574 1213 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
AnnaBridge 145:64910690c574 1214 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1215 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
AnnaBridge 145:64910690c574 1216 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1217 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
AnnaBridge 145:64910690c574 1218 /* @brief Has external pin 12 connected to LLWU device. */
AnnaBridge 145:64910690c574 1219 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
AnnaBridge 145:64910690c574 1220 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1221 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 1222 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1223 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1224 /* @brief Has external pin 13 connected to LLWU device. */
AnnaBridge 145:64910690c574 1225 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
AnnaBridge 145:64910690c574 1226 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1227 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 1228 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1229 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
AnnaBridge 145:64910690c574 1230 /* @brief Has external pin 14 connected to LLWU device. */
AnnaBridge 145:64910690c574 1231 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
AnnaBridge 145:64910690c574 1232 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1233 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 1234 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1235 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
AnnaBridge 145:64910690c574 1236 /* @brief Has external pin 15 connected to LLWU device. */
AnnaBridge 145:64910690c574 1237 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
AnnaBridge 145:64910690c574 1238 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1239 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 1240 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1241 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
AnnaBridge 145:64910690c574 1242 /* @brief Has external pin 16 connected to LLWU device. */
AnnaBridge 145:64910690c574 1243 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
AnnaBridge 145:64910690c574 1244 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1245 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 1246 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1247 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6)
AnnaBridge 145:64910690c574 1248 /* @brief Has external pin 17 connected to LLWU device. */
AnnaBridge 145:64910690c574 1249 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
AnnaBridge 145:64910690c574 1250 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1251 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 1252 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1253 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9)
AnnaBridge 145:64910690c574 1254 /* @brief Has external pin 18 connected to LLWU device. */
AnnaBridge 145:64910690c574 1255 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
AnnaBridge 145:64910690c574 1256 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1257 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX)
AnnaBridge 145:64910690c574 1258 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1259 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10)
AnnaBridge 145:64910690c574 1260 /* @brief Has external pin 19 connected to LLWU device. */
AnnaBridge 145:64910690c574 1261 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
AnnaBridge 145:64910690c574 1262 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1263 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1264 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1265 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1266 /* @brief Has external pin 20 connected to LLWU device. */
AnnaBridge 145:64910690c574 1267 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
AnnaBridge 145:64910690c574 1268 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1269 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1270 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1271 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1272 /* @brief Has external pin 21 connected to LLWU device. */
AnnaBridge 145:64910690c574 1273 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
AnnaBridge 145:64910690c574 1274 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1275 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1276 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1277 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1278 /* @brief Has external pin 22 connected to LLWU device. */
AnnaBridge 145:64910690c574 1279 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
AnnaBridge 145:64910690c574 1280 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1281 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX)
AnnaBridge 145:64910690c574 1282 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1283 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10)
AnnaBridge 145:64910690c574 1284 /* @brief Has external pin 23 connected to LLWU device. */
AnnaBridge 145:64910690c574 1285 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
AnnaBridge 145:64910690c574 1286 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1287 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX)
AnnaBridge 145:64910690c574 1288 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1289 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11)
AnnaBridge 145:64910690c574 1290 /* @brief Has external pin 24 connected to LLWU device. */
AnnaBridge 145:64910690c574 1291 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
AnnaBridge 145:64910690c574 1292 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1293 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 1294 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1295 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8)
AnnaBridge 145:64910690c574 1296 /* @brief Has external pin 25 connected to LLWU device. */
AnnaBridge 145:64910690c574 1297 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
AnnaBridge 145:64910690c574 1298 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1299 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX)
AnnaBridge 145:64910690c574 1300 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1301 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11)
AnnaBridge 145:64910690c574 1302 /* @brief Has external pin 26 connected to LLWU device. */
AnnaBridge 145:64910690c574 1303 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
AnnaBridge 145:64910690c574 1304 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1305 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1306 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1307 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1308 /* @brief Has external pin 27 connected to LLWU device. */
AnnaBridge 145:64910690c574 1309 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
AnnaBridge 145:64910690c574 1310 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1311 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1312 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1313 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1314 /* @brief Has external pin 28 connected to LLWU device. */
AnnaBridge 145:64910690c574 1315 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
AnnaBridge 145:64910690c574 1316 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1317 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1318 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1319 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1320 /* @brief Has external pin 29 connected to LLWU device. */
AnnaBridge 145:64910690c574 1321 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
AnnaBridge 145:64910690c574 1322 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1323 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1324 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1325 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1326 /* @brief Has external pin 30 connected to LLWU device. */
AnnaBridge 145:64910690c574 1327 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
AnnaBridge 145:64910690c574 1328 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1329 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1330 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1331 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1332 /* @brief Has external pin 31 connected to LLWU device. */
AnnaBridge 145:64910690c574 1333 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
AnnaBridge 145:64910690c574 1334 /* @brief Index of port of external pin. */
AnnaBridge 145:64910690c574 1335 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
AnnaBridge 145:64910690c574 1336 /* @brief Number of external pin port on specified port. */
AnnaBridge 145:64910690c574 1337 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
AnnaBridge 145:64910690c574 1338 /* @brief Has internal module 0 connected to LLWU device. */
AnnaBridge 145:64910690c574 1339 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
AnnaBridge 145:64910690c574 1340 /* @brief Has internal module 1 connected to LLWU device. */
AnnaBridge 145:64910690c574 1341 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
AnnaBridge 145:64910690c574 1342 /* @brief Has internal module 2 connected to LLWU device. */
AnnaBridge 145:64910690c574 1343 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
AnnaBridge 145:64910690c574 1344 /* @brief Has internal module 3 connected to LLWU device. */
AnnaBridge 145:64910690c574 1345 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
AnnaBridge 145:64910690c574 1346 /* @brief Has internal module 4 connected to LLWU device. */
AnnaBridge 145:64910690c574 1347 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
AnnaBridge 145:64910690c574 1348 /* @brief Has internal module 5 connected to LLWU device. */
AnnaBridge 145:64910690c574 1349 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
AnnaBridge 145:64910690c574 1350 /* @brief Has internal module 6 connected to LLWU device. */
AnnaBridge 145:64910690c574 1351 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
AnnaBridge 145:64910690c574 1352 /* @brief Has internal module 7 connected to LLWU device. */
AnnaBridge 145:64910690c574 1353 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
AnnaBridge 145:64910690c574 1354 /* @brief Has Version ID Register (LLWU_VERID). */
AnnaBridge 145:64910690c574 1355 #define FSL_FEATURE_LLWU_HAS_VERID (0)
AnnaBridge 145:64910690c574 1356 /* @brief Has Parameter Register (LLWU_PARAM). */
AnnaBridge 145:64910690c574 1357 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
AnnaBridge 145:64910690c574 1358 /* @brief Width of registers of the LLWU. */
AnnaBridge 145:64910690c574 1359 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
AnnaBridge 145:64910690c574 1360 /* @brief Has DMA Enable register (LLWU_DE). */
AnnaBridge 145:64910690c574 1361 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
AnnaBridge 145:64910690c574 1362 #endif /* defined(CPU_MKL82Z128VLH7) || defined(CPU_MKL82Z128VLK7) || defined(CPU_MKL82Z128VMP7) */
AnnaBridge 145:64910690c574 1363
AnnaBridge 145:64910690c574 1364 /* LPTMR module features */
AnnaBridge 145:64910690c574 1365
AnnaBridge 145:64910690c574 1366 /* @brief Has shared interrupt handler with another LPTMR module. */
AnnaBridge 145:64910690c574 1367 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
AnnaBridge 145:64910690c574 1368
AnnaBridge 145:64910690c574 1369 /* LPUART module features */
AnnaBridge 145:64910690c574 1370
AnnaBridge 145:64910690c574 1371 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
AnnaBridge 145:64910690c574 1372 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
AnnaBridge 145:64910690c574 1373 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
AnnaBridge 145:64910690c574 1374 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
AnnaBridge 145:64910690c574 1375 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
AnnaBridge 145:64910690c574 1376 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
AnnaBridge 145:64910690c574 1377 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge 145:64910690c574 1378 #define FSL_FEATURE_LPUART_HAS_FIFO (1)
AnnaBridge 145:64910690c574 1379 /* @brief Has 32-bit register MODIR */
AnnaBridge 145:64910690c574 1380 #define FSL_FEATURE_LPUART_HAS_MODIR (1)
AnnaBridge 145:64910690c574 1381 /* @brief Hardware flow control (RTS, CTS) is supported. */
AnnaBridge 145:64910690c574 1382 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
AnnaBridge 145:64910690c574 1383 /* @brief Infrared (modulation) is supported. */
AnnaBridge 145:64910690c574 1384 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
AnnaBridge 145:64910690c574 1385 /* @brief 2 bits long stop bit is available. */
AnnaBridge 145:64910690c574 1386 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
AnnaBridge 145:64910690c574 1387 /* @brief If 10-bit mode is supported. */
AnnaBridge 145:64910690c574 1388 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
AnnaBridge 145:64910690c574 1389 /* @brief If 7-bit mode is supported. */
AnnaBridge 145:64910690c574 1390 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
AnnaBridge 145:64910690c574 1391 /* @brief Baud rate fine adjustment is available. */
AnnaBridge 145:64910690c574 1392 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
AnnaBridge 145:64910690c574 1393 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
AnnaBridge 145:64910690c574 1394 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
AnnaBridge 145:64910690c574 1395 /* @brief Baud rate oversampling is available. */
AnnaBridge 145:64910690c574 1396 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
AnnaBridge 145:64910690c574 1397 /* @brief Baud rate oversampling is available. */
AnnaBridge 145:64910690c574 1398 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
AnnaBridge 145:64910690c574 1399 /* @brief Peripheral type. */
AnnaBridge 145:64910690c574 1400 #define FSL_FEATURE_LPUART_IS_SCI (1)
AnnaBridge 145:64910690c574 1401 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge 145:64910690c574 1402 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \
AnnaBridge 145:64910690c574 1403 ((x) == LPUART0 ? (8) : \
AnnaBridge 145:64910690c574 1404 ((x) == LPUART1 ? (8) : \
AnnaBridge 145:64910690c574 1405 ((x) == LPUART2 ? (1) : (-1))))
AnnaBridge 145:64910690c574 1406 /* @brief Maximal data width without parity bit. */
AnnaBridge 145:64910690c574 1407 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
AnnaBridge 145:64910690c574 1408 /* @brief Maximal data width with parity bit. */
AnnaBridge 145:64910690c574 1409 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
AnnaBridge 145:64910690c574 1410 /* @brief Supports two match addresses to filter incoming frames. */
AnnaBridge 145:64910690c574 1411 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
AnnaBridge 145:64910690c574 1412 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
AnnaBridge 145:64910690c574 1413 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
AnnaBridge 145:64910690c574 1414 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
AnnaBridge 145:64910690c574 1415 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
AnnaBridge 145:64910690c574 1416 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
AnnaBridge 145:64910690c574 1417 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
AnnaBridge 145:64910690c574 1418 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
AnnaBridge 145:64910690c574 1419 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
AnnaBridge 145:64910690c574 1420 /* @brief Has improved smart card (ISO7816 protocol) support. */
AnnaBridge 145:64910690c574 1421 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
AnnaBridge 145:64910690c574 1422 /* @brief Has local operation network (CEA709.1-B protocol) support. */
AnnaBridge 145:64910690c574 1423 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
AnnaBridge 145:64910690c574 1424 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
AnnaBridge 145:64910690c574 1425 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
AnnaBridge 145:64910690c574 1426 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
AnnaBridge 145:64910690c574 1427 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
AnnaBridge 145:64910690c574 1428 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
AnnaBridge 145:64910690c574 1429 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
AnnaBridge 145:64910690c574 1430 /* @brief Has separate DMA RX and TX requests. */
AnnaBridge 145:64910690c574 1431 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
AnnaBridge 145:64910690c574 1432 /* @brief Has separate RX and TX interrupts. */
AnnaBridge 145:64910690c574 1433 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
AnnaBridge 145:64910690c574 1434 /* @brief Has LPAURT_PARAM. */
AnnaBridge 145:64910690c574 1435 #define FSL_FEATURE_LPUART_HAS_PARAM (0)
AnnaBridge 145:64910690c574 1436 /* @brief Has LPUART_VERID. */
AnnaBridge 145:64910690c574 1437 #define FSL_FEATURE_LPUART_HAS_VERID (0)
AnnaBridge 145:64910690c574 1438 /* @brief Has LPUART_GLOBAL. */
AnnaBridge 145:64910690c574 1439 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
AnnaBridge 145:64910690c574 1440 /* @brief Has LPUART_PINCFG. */
AnnaBridge 145:64910690c574 1441 #define FSL_FEATURE_LPUART_HAS_PINCFG (0)
AnnaBridge 145:64910690c574 1442
AnnaBridge 145:64910690c574 1443 /* LTC module features */
AnnaBridge 145:64910690c574 1444
AnnaBridge 145:64910690c574 1445 /* @brief LTC module supports DES algorithm. */
AnnaBridge 145:64910690c574 1446 #define FSL_FEATURE_LTC_HAS_DES (1)
AnnaBridge 145:64910690c574 1447 /* @brief LTC module supports PKHA algorithm. */
AnnaBridge 145:64910690c574 1448 #define FSL_FEATURE_LTC_HAS_PKHA (1)
AnnaBridge 145:64910690c574 1449 /* @brief LTC module supports SHA algorithm. */
AnnaBridge 145:64910690c574 1450 #define FSL_FEATURE_LTC_HAS_SHA (1)
AnnaBridge 145:64910690c574 1451 /* @brief LTC module supports AES GCM mode. */
AnnaBridge 145:64910690c574 1452 #define FSL_FEATURE_LTC_HAS_GCM (1)
AnnaBridge 145:64910690c574 1453 /* @brief LTC module supports DPAMS registers. */
AnnaBridge 145:64910690c574 1454 #define FSL_FEATURE_LTC_HAS_DPAMS (1)
AnnaBridge 145:64910690c574 1455 /* @brief LTC module supports AES with 24 bytes key. */
AnnaBridge 145:64910690c574 1456 #define FSL_FEATURE_LTC_HAS_AES192 (1)
AnnaBridge 145:64910690c574 1457 /* @brief LTC module supports AES with 32 bytes key. */
AnnaBridge 145:64910690c574 1458 #define FSL_FEATURE_LTC_HAS_AES256 (1)
AnnaBridge 145:64910690c574 1459
AnnaBridge 145:64910690c574 1460 /* MCG module features */
AnnaBridge 145:64910690c574 1461
AnnaBridge 145:64910690c574 1462 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
AnnaBridge 145:64910690c574 1463 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
AnnaBridge 145:64910690c574 1464 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
AnnaBridge 145:64910690c574 1465 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (7)
AnnaBridge 145:64910690c574 1466 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
AnnaBridge 145:64910690c574 1467 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16)
AnnaBridge 145:64910690c574 1468 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */
AnnaBridge 145:64910690c574 1469 #define FSL_FEATURE_MCG_PLL_REF_MIN (8000000)
AnnaBridge 145:64910690c574 1470 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */
AnnaBridge 145:64910690c574 1471 #define FSL_FEATURE_MCG_PLL_REF_MAX (16000000)
AnnaBridge 145:64910690c574 1472 /* @brief The PLL clock is divided by 2 before VCO divider. */
AnnaBridge 145:64910690c574 1473 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (1)
AnnaBridge 145:64910690c574 1474 /* @brief FRDIV supports 1280. */
AnnaBridge 145:64910690c574 1475 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
AnnaBridge 145:64910690c574 1476 /* @brief FRDIV supports 1536. */
AnnaBridge 145:64910690c574 1477 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
AnnaBridge 145:64910690c574 1478 /* @brief MCGFFCLK divider. */
AnnaBridge 145:64910690c574 1479 #define FSL_FEATURE_MCG_FFCLK_DIV (1)
AnnaBridge 145:64910690c574 1480 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
AnnaBridge 145:64910690c574 1481 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
AnnaBridge 145:64910690c574 1482 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
AnnaBridge 145:64910690c574 1483 #define FSL_FEATURE_MCG_HAS_RTC_32K (1)
AnnaBridge 145:64910690c574 1484 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
AnnaBridge 145:64910690c574 1485 #define FSL_FEATURE_MCG_HAS_PLL1 (0)
AnnaBridge 145:64910690c574 1486 /* @brief Has 48MHz internal oscillator. */
AnnaBridge 145:64910690c574 1487 #define FSL_FEATURE_MCG_HAS_IRC_48M (1)
AnnaBridge 145:64910690c574 1488 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
AnnaBridge 145:64910690c574 1489 #define FSL_FEATURE_MCG_HAS_OSC1 (0)
AnnaBridge 145:64910690c574 1490 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
AnnaBridge 145:64910690c574 1491 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
AnnaBridge 145:64910690c574 1492 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
AnnaBridge 145:64910690c574 1493 #define FSL_FEATURE_MCG_HAS_LOLRE (1)
AnnaBridge 145:64910690c574 1494 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
AnnaBridge 145:64910690c574 1495 #define FSL_FEATURE_MCG_USE_OSCSEL (1)
AnnaBridge 145:64910690c574 1496 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
AnnaBridge 145:64910690c574 1497 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
AnnaBridge 145:64910690c574 1498 /* @brief TBD */
AnnaBridge 145:64910690c574 1499 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
AnnaBridge 145:64910690c574 1500 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
AnnaBridge 145:64910690c574 1501 #define FSL_FEATURE_MCG_HAS_PLL (1)
AnnaBridge 145:64910690c574 1502 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
AnnaBridge 145:64910690c574 1503 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
AnnaBridge 145:64910690c574 1504 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
AnnaBridge 145:64910690c574 1505 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
AnnaBridge 145:64910690c574 1506 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
AnnaBridge 145:64910690c574 1507 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
AnnaBridge 145:64910690c574 1508 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
AnnaBridge 145:64910690c574 1509 #define FSL_FEATURE_MCG_HAS_FLL (1)
AnnaBridge 145:64910690c574 1510 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
AnnaBridge 145:64910690c574 1511 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
AnnaBridge 145:64910690c574 1512 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
AnnaBridge 145:64910690c574 1513 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
AnnaBridge 145:64910690c574 1514 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
AnnaBridge 145:64910690c574 1515 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
AnnaBridge 145:64910690c574 1516 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
AnnaBridge 145:64910690c574 1517 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
AnnaBridge 145:64910690c574 1518 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
AnnaBridge 145:64910690c574 1519 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
AnnaBridge 145:64910690c574 1520 /* @brief Has external clock monitor (register bit C6[CME]). */
AnnaBridge 145:64910690c574 1521 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
AnnaBridge 145:64910690c574 1522 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
AnnaBridge 145:64910690c574 1523 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
AnnaBridge 145:64910690c574 1524 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
AnnaBridge 145:64910690c574 1525 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
AnnaBridge 145:64910690c574 1526 /* @brief Has PEI mode or PBI mode. */
AnnaBridge 145:64910690c574 1527 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
AnnaBridge 145:64910690c574 1528 /* @brief Reset clock mode is BLPI. */
AnnaBridge 145:64910690c574 1529 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
AnnaBridge 145:64910690c574 1530
AnnaBridge 145:64910690c574 1531 /* MPU module features */
AnnaBridge 145:64910690c574 1532
AnnaBridge 145:64910690c574 1533 /* @brief Specifies number of descriptors available. */
AnnaBridge 145:64910690c574 1534 #define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (8)
AnnaBridge 145:64910690c574 1535 /* @brief Has process identifier support. */
AnnaBridge 145:64910690c574 1536 #define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
AnnaBridge 145:64910690c574 1537 /* @brief Total number of MPU master. */
AnnaBridge 145:64910690c574 1538 #define FSL_FEATURE_MPU_MASTER_COUNT (8)
AnnaBridge 145:64910690c574 1539 /* @brief Total number of MPU master with privileged rights */
AnnaBridge 145:64910690c574 1540 #define FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT (4)
AnnaBridge 145:64910690c574 1541 /* @brief Max index of used MPU master. */
AnnaBridge 145:64910690c574 1542 #define FSL_FEATURE_MPU_MASTER_MAX_INDEX (4)
AnnaBridge 145:64910690c574 1543 /* @brief Max index of used MPU master with privileged rights */
AnnaBridge 145:64910690c574 1544 #define FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX (2)
AnnaBridge 145:64910690c574 1545 /* @brief Has master 0. */
AnnaBridge 145:64910690c574 1546 #define FSL_FEATURE_MPU_HAS_MASTER0 (1)
AnnaBridge 145:64910690c574 1547 /* @brief Has master 1. */
AnnaBridge 145:64910690c574 1548 #define FSL_FEATURE_MPU_HAS_MASTER1 (1)
AnnaBridge 145:64910690c574 1549 /* @brief Has master 2. */
AnnaBridge 145:64910690c574 1550 #define FSL_FEATURE_MPU_HAS_MASTER2 (1)
AnnaBridge 145:64910690c574 1551 /* @brief Has master 3. */
AnnaBridge 145:64910690c574 1552 #define FSL_FEATURE_MPU_HAS_MASTER3 (0)
AnnaBridge 145:64910690c574 1553 /* @brief Has master 4. */
AnnaBridge 145:64910690c574 1554 #define FSL_FEATURE_MPU_HAS_MASTER4 (1)
AnnaBridge 145:64910690c574 1555 /* @brief Has master 5. */
AnnaBridge 145:64910690c574 1556 #define FSL_FEATURE_MPU_HAS_MASTER5 (0)
AnnaBridge 145:64910690c574 1557 /* @brief Has master 6. */
AnnaBridge 145:64910690c574 1558 #define FSL_FEATURE_MPU_HAS_MASTER6 (0)
AnnaBridge 145:64910690c574 1559 /* @brief Has master 7. */
AnnaBridge 145:64910690c574 1560 #define FSL_FEATURE_MPU_HAS_MASTER7 (0)
AnnaBridge 145:64910690c574 1561
AnnaBridge 145:64910690c574 1562 /* interrupt module features */
AnnaBridge 145:64910690c574 1563
AnnaBridge 145:64910690c574 1564 /* @brief Lowest interrupt request number. */
AnnaBridge 145:64910690c574 1565 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
AnnaBridge 145:64910690c574 1566 /* @brief Highest interrupt request number. */
AnnaBridge 145:64910690c574 1567 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
AnnaBridge 145:64910690c574 1568
AnnaBridge 145:64910690c574 1569 /* OSC module features */
AnnaBridge 145:64910690c574 1570
AnnaBridge 145:64910690c574 1571 /* @brief Has OSC1 external oscillator. */
AnnaBridge 145:64910690c574 1572 #define FSL_FEATURE_OSC_HAS_OSC1 (0)
AnnaBridge 145:64910690c574 1573 /* @brief Has OSC0 external oscillator. */
AnnaBridge 145:64910690c574 1574 #define FSL_FEATURE_OSC_HAS_OSC0 (0)
AnnaBridge 145:64910690c574 1575 /* @brief Has OSC external oscillator (without index). */
AnnaBridge 145:64910690c574 1576 #define FSL_FEATURE_OSC_HAS_OSC (1)
AnnaBridge 145:64910690c574 1577 /* @brief Number of OSC external oscillators. */
AnnaBridge 145:64910690c574 1578 #define FSL_FEATURE_OSC_OSC_COUNT (1)
AnnaBridge 145:64910690c574 1579 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
AnnaBridge 145:64910690c574 1580 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1)
AnnaBridge 145:64910690c574 1581
AnnaBridge 145:64910690c574 1582 /* PIT module features */
AnnaBridge 145:64910690c574 1583
AnnaBridge 145:64910690c574 1584 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
AnnaBridge 145:64910690c574 1585 #define FSL_FEATURE_PIT_TIMER_COUNT (4)
AnnaBridge 145:64910690c574 1586 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
AnnaBridge 145:64910690c574 1587 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
AnnaBridge 145:64910690c574 1588 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
AnnaBridge 145:64910690c574 1589 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
AnnaBridge 145:64910690c574 1590 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
AnnaBridge 145:64910690c574 1591 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
AnnaBridge 145:64910690c574 1592
AnnaBridge 145:64910690c574 1593 /* PMC module features */
AnnaBridge 145:64910690c574 1594
AnnaBridge 145:64910690c574 1595 /* @brief Has Bandgap Enable In VLPx Operation support. */
AnnaBridge 145:64910690c574 1596 #define FSL_FEATURE_PMC_HAS_BGEN (1)
AnnaBridge 145:64910690c574 1597 /* @brief Has Bandgap Buffer Enable. */
AnnaBridge 145:64910690c574 1598 #define FSL_FEATURE_PMC_HAS_BGBE (1)
AnnaBridge 145:64910690c574 1599 /* @brief Has Bandgap Buffer Drive Select. */
AnnaBridge 145:64910690c574 1600 #define FSL_FEATURE_PMC_HAS_BGBDS (0)
AnnaBridge 145:64910690c574 1601 /* @brief Has Low-Voltage Detect Voltage Select support. */
AnnaBridge 145:64910690c574 1602 #define FSL_FEATURE_PMC_HAS_LVDV (1)
AnnaBridge 145:64910690c574 1603 /* @brief Has Low-Voltage Warning Voltage Select support. */
AnnaBridge 145:64910690c574 1604 #define FSL_FEATURE_PMC_HAS_LVWV (1)
AnnaBridge 145:64910690c574 1605 /* @brief Has LPO. */
AnnaBridge 145:64910690c574 1606 #define FSL_FEATURE_PMC_HAS_LPO (0)
AnnaBridge 145:64910690c574 1607 /* @brief Has VLPx option PMC_REGSC[VLPO]. */
AnnaBridge 145:64910690c574 1608 #define FSL_FEATURE_PMC_HAS_VLPO (1)
AnnaBridge 145:64910690c574 1609 /* @brief Has acknowledge isolation support. */
AnnaBridge 145:64910690c574 1610 #define FSL_FEATURE_PMC_HAS_ACKISO (1)
AnnaBridge 145:64910690c574 1611 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
AnnaBridge 145:64910690c574 1612 #define FSL_FEATURE_PMC_HAS_REGFPM (0)
AnnaBridge 145:64910690c574 1613 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
AnnaBridge 145:64910690c574 1614 #define FSL_FEATURE_PMC_HAS_REGONS (1)
AnnaBridge 145:64910690c574 1615 /* @brief Has PMC_HVDSC1. */
AnnaBridge 145:64910690c574 1616 #define FSL_FEATURE_PMC_HAS_HVDSC1 (1)
AnnaBridge 145:64910690c574 1617 /* @brief Has PMC_PARAM. */
AnnaBridge 145:64910690c574 1618 #define FSL_FEATURE_PMC_HAS_PARAM (0)
AnnaBridge 145:64910690c574 1619 /* @brief Has PMC_VERID. */
AnnaBridge 145:64910690c574 1620 #define FSL_FEATURE_PMC_HAS_VERID (0)
AnnaBridge 145:64910690c574 1621
AnnaBridge 145:64910690c574 1622 /* PORT module features */
AnnaBridge 145:64910690c574 1623
AnnaBridge 145:64910690c574 1624 /* @brief Has control lock (register bit PCR[LK]). */
AnnaBridge 145:64910690c574 1625 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
AnnaBridge 145:64910690c574 1626 /* @brief Has open drain control (register bit PCR[ODE]). */
AnnaBridge 145:64910690c574 1627 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
AnnaBridge 145:64910690c574 1628 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
AnnaBridge 145:64910690c574 1629 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
AnnaBridge 145:64910690c574 1630 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
AnnaBridge 145:64910690c574 1631 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
AnnaBridge 145:64910690c574 1632 /* @brief Has pull resistor selection available. */
AnnaBridge 145:64910690c574 1633 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
AnnaBridge 145:64910690c574 1634 /* @brief Has pull resistor enable (register bit PCR[PE]). */
AnnaBridge 145:64910690c574 1635 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
AnnaBridge 145:64910690c574 1636 /* @brief Has slew rate control (register bit PCR[SRE]). */
AnnaBridge 145:64910690c574 1637 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
AnnaBridge 145:64910690c574 1638 /* @brief Has passive filter (register bit field PCR[PFE]). */
AnnaBridge 145:64910690c574 1639 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
AnnaBridge 145:64910690c574 1640 /* @brief Has drive strength control (register bit PCR[DSE]). */
AnnaBridge 145:64910690c574 1641 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (0)
AnnaBridge 145:64910690c574 1642 /* @brief Has separate drive strength register (HDRVE). */
AnnaBridge 145:64910690c574 1643 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
AnnaBridge 145:64910690c574 1644 /* @brief Has glitch filter (register IOFLT). */
AnnaBridge 145:64910690c574 1645 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
AnnaBridge 145:64910690c574 1646 /* @brief Defines width of PCR[MUX] field. */
AnnaBridge 145:64910690c574 1647 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
AnnaBridge 145:64910690c574 1648 /* @brief Has dedicated interrupt vector. */
AnnaBridge 145:64910690c574 1649 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
AnnaBridge 145:64910690c574 1650 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
AnnaBridge 145:64910690c574 1651 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1)
AnnaBridge 145:64910690c574 1652 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
AnnaBridge 145:64910690c574 1653 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1)
AnnaBridge 145:64910690c574 1654
AnnaBridge 145:64910690c574 1655 /* QSPI module features */
AnnaBridge 145:64910690c574 1656
AnnaBridge 145:64910690c574 1657 /* @brief QSPI lookup table depth. */
AnnaBridge 145:64910690c574 1658 #define FSL_FEATURE_QSPI_LUT_DEPTH (64)
AnnaBridge 145:64910690c574 1659 /* @brief QSPI Tx FIFO depth. */
AnnaBridge 145:64910690c574 1660 #define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16)
AnnaBridge 145:64910690c574 1661 /* @brief QSPI Rx FIFO depth. */
AnnaBridge 145:64910690c574 1662 #define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16)
AnnaBridge 145:64910690c574 1663 /* @brief QSPI AHB buffer count. */
AnnaBridge 145:64910690c574 1664 #define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4)
AnnaBridge 145:64910690c574 1665 /* @brief QSPI AMBA base address. */
AnnaBridge 145:64910690c574 1666 #define FSL_FEATURE_QSPI_AMBA_BASE (0x68000000U)
AnnaBridge 145:64910690c574 1667 /* @brief QSPI AHB buffer ARDB base address. */
AnnaBridge 145:64910690c574 1668 #define FSL_FEATURE_QSPI_ARDB_BASE (0x67000000U)
AnnaBridge 145:64910690c574 1669
AnnaBridge 145:64910690c574 1670 /* RCM module features */
AnnaBridge 145:64910690c574 1671
AnnaBridge 145:64910690c574 1672 /* @brief Has Loss-of-Lock Reset support. */
AnnaBridge 145:64910690c574 1673 #define FSL_FEATURE_RCM_HAS_LOL (1)
AnnaBridge 145:64910690c574 1674 /* @brief Has Loss-of-Clock Reset support. */
AnnaBridge 145:64910690c574 1675 #define FSL_FEATURE_RCM_HAS_LOC (1)
AnnaBridge 145:64910690c574 1676 /* @brief Has JTAG generated Reset support. */
AnnaBridge 145:64910690c574 1677 #define FSL_FEATURE_RCM_HAS_JTAG (0)
AnnaBridge 145:64910690c574 1678 /* @brief Has EzPort generated Reset support. */
AnnaBridge 145:64910690c574 1679 #define FSL_FEATURE_RCM_HAS_EZPORT (0)
AnnaBridge 145:64910690c574 1680 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
AnnaBridge 145:64910690c574 1681 #define FSL_FEATURE_RCM_HAS_EZPMS (0)
AnnaBridge 145:64910690c574 1682 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
AnnaBridge 145:64910690c574 1683 #define FSL_FEATURE_RCM_HAS_BOOTROM (1)
AnnaBridge 145:64910690c574 1684 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
AnnaBridge 145:64910690c574 1685 #define FSL_FEATURE_RCM_HAS_SSRS (1)
AnnaBridge 145:64910690c574 1686 /* @brief Has Version ID Register (RCM_VERID). */
AnnaBridge 145:64910690c574 1687 #define FSL_FEATURE_RCM_HAS_VERID (0)
AnnaBridge 145:64910690c574 1688 /* @brief Has Parameter Register (RCM_PARAM). */
AnnaBridge 145:64910690c574 1689 #define FSL_FEATURE_RCM_HAS_PARAM (0)
AnnaBridge 145:64910690c574 1690 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
AnnaBridge 145:64910690c574 1691 #define FSL_FEATURE_RCM_HAS_SRIE (0)
AnnaBridge 145:64910690c574 1692 /* @brief Width of registers of the RCM. */
AnnaBridge 145:64910690c574 1693 #define FSL_FEATURE_RCM_REG_WIDTH (8)
AnnaBridge 145:64910690c574 1694 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
AnnaBridge 145:64910690c574 1695 #define FSL_FEATURE_RCM_HAS_CORE1 (0)
AnnaBridge 145:64910690c574 1696 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
AnnaBridge 145:64910690c574 1697 #define FSL_FEATURE_RCM_HAS_MDM_AP (1)
AnnaBridge 145:64910690c574 1698 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
AnnaBridge 145:64910690c574 1699 #define FSL_FEATURE_RCM_HAS_WAKEUP (1)
AnnaBridge 145:64910690c574 1700
AnnaBridge 145:64910690c574 1701 /* RTC module features */
AnnaBridge 145:64910690c574 1702
AnnaBridge 145:64910690c574 1703 /* @brief Has wakeup pin. */
AnnaBridge 145:64910690c574 1704 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
AnnaBridge 145:64910690c574 1705 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
AnnaBridge 145:64910690c574 1706 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
AnnaBridge 145:64910690c574 1707 /* @brief Has low power features (registers MER, MCLR and MCHR). */
AnnaBridge 145:64910690c574 1708 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
AnnaBridge 145:64910690c574 1709 /* @brief Has read/write access control (registers WAR and RAR). */
AnnaBridge 145:64910690c574 1710 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
AnnaBridge 145:64910690c574 1711 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
AnnaBridge 145:64910690c574 1712 #define FSL_FEATURE_RTC_HAS_SECURITY (1)
AnnaBridge 145:64910690c574 1713 /* @brief Has RTC_CLKIN available. */
AnnaBridge 145:64910690c574 1714 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
AnnaBridge 145:64910690c574 1715 /* @brief Has prescaler adjust for LPO. */
AnnaBridge 145:64910690c574 1716 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
AnnaBridge 145:64910690c574 1717 /* @brief Has Clock Pin Enable field. */
AnnaBridge 145:64910690c574 1718 #define FSL_FEATURE_RTC_HAS_CPE (0)
AnnaBridge 145:64910690c574 1719 /* @brief Has Timer Seconds Interrupt Configuration field. */
AnnaBridge 145:64910690c574 1720 #define FSL_FEATURE_RTC_HAS_TSIC (0)
AnnaBridge 145:64910690c574 1721 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
AnnaBridge 145:64910690c574 1722 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
AnnaBridge 145:64910690c574 1723
AnnaBridge 145:64910690c574 1724 /* SIM module features */
AnnaBridge 145:64910690c574 1725
AnnaBridge 145:64910690c574 1726 /* @brief Has USB FS divider. */
AnnaBridge 145:64910690c574 1727 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
AnnaBridge 145:64910690c574 1728 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
AnnaBridge 145:64910690c574 1729 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
AnnaBridge 145:64910690c574 1730 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
AnnaBridge 145:64910690c574 1731 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
AnnaBridge 145:64910690c574 1732 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
AnnaBridge 145:64910690c574 1733 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
AnnaBridge 145:64910690c574 1734 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
AnnaBridge 145:64910690c574 1735 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
AnnaBridge 145:64910690c574 1736 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
AnnaBridge 145:64910690c574 1737 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
AnnaBridge 145:64910690c574 1738 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
AnnaBridge 145:64910690c574 1739 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
AnnaBridge 145:64910690c574 1740 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
AnnaBridge 145:64910690c574 1741 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
AnnaBridge 145:64910690c574 1742 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
AnnaBridge 145:64910690c574 1743 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
AnnaBridge 145:64910690c574 1744 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
AnnaBridge 145:64910690c574 1745 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
AnnaBridge 145:64910690c574 1746 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
AnnaBridge 145:64910690c574 1747 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
AnnaBridge 145:64910690c574 1748 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
AnnaBridge 145:64910690c574 1749 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
AnnaBridge 145:64910690c574 1750 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
AnnaBridge 145:64910690c574 1751 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
AnnaBridge 145:64910690c574 1752 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
AnnaBridge 145:64910690c574 1753 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
AnnaBridge 145:64910690c574 1754 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
AnnaBridge 145:64910690c574 1755 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
AnnaBridge 145:64910690c574 1756 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
AnnaBridge 145:64910690c574 1757 #define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
AnnaBridge 145:64910690c574 1758 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
AnnaBridge 145:64910690c574 1759 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
AnnaBridge 145:64910690c574 1760 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
AnnaBridge 145:64910690c574 1761 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
AnnaBridge 145:64910690c574 1762 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
AnnaBridge 145:64910690c574 1763 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
AnnaBridge 145:64910690c574 1764 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
AnnaBridge 145:64910690c574 1765 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
AnnaBridge 145:64910690c574 1766 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
AnnaBridge 145:64910690c574 1767 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
AnnaBridge 145:64910690c574 1768 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
AnnaBridge 145:64910690c574 1769 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
AnnaBridge 145:64910690c574 1770 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
AnnaBridge 145:64910690c574 1771 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
AnnaBridge 145:64910690c574 1772 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
AnnaBridge 145:64910690c574 1773 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
AnnaBridge 145:64910690c574 1774 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
AnnaBridge 145:64910690c574 1775 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1)
AnnaBridge 145:64910690c574 1776 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
AnnaBridge 145:64910690c574 1777 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1)
AnnaBridge 145:64910690c574 1778 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
AnnaBridge 145:64910690c574 1779 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
AnnaBridge 145:64910690c574 1780 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
AnnaBridge 145:64910690c574 1781 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
AnnaBridge 145:64910690c574 1782 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
AnnaBridge 145:64910690c574 1783 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
AnnaBridge 145:64910690c574 1784 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
AnnaBridge 145:64910690c574 1785 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
AnnaBridge 145:64910690c574 1786 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
AnnaBridge 145:64910690c574 1787 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
AnnaBridge 145:64910690c574 1788 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
AnnaBridge 145:64910690c574 1789 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
AnnaBridge 145:64910690c574 1790 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
AnnaBridge 145:64910690c574 1791 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
AnnaBridge 145:64910690c574 1792 /* @brief Has FTM module(s) configuration. */
AnnaBridge 145:64910690c574 1793 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
AnnaBridge 145:64910690c574 1794 /* @brief Number of FTM modules. */
AnnaBridge 145:64910690c574 1795 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
AnnaBridge 145:64910690c574 1796 /* @brief Number of FTM triggers with selectable source. */
AnnaBridge 145:64910690c574 1797 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
AnnaBridge 145:64910690c574 1798 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
AnnaBridge 145:64910690c574 1799 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
AnnaBridge 145:64910690c574 1800 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
AnnaBridge 145:64910690c574 1801 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
AnnaBridge 145:64910690c574 1802 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
AnnaBridge 145:64910690c574 1803 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
AnnaBridge 145:64910690c574 1804 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
AnnaBridge 145:64910690c574 1805 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
AnnaBridge 145:64910690c574 1806 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
AnnaBridge 145:64910690c574 1807 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
AnnaBridge 145:64910690c574 1808 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
AnnaBridge 145:64910690c574 1809 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
AnnaBridge 145:64910690c574 1810 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
AnnaBridge 145:64910690c574 1811 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
AnnaBridge 145:64910690c574 1812 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
AnnaBridge 145:64910690c574 1813 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
AnnaBridge 145:64910690c574 1814 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
AnnaBridge 145:64910690c574 1815 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
AnnaBridge 145:64910690c574 1816 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
AnnaBridge 145:64910690c574 1817 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
AnnaBridge 145:64910690c574 1818 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
AnnaBridge 145:64910690c574 1819 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
AnnaBridge 145:64910690c574 1820 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
AnnaBridge 145:64910690c574 1821 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
AnnaBridge 145:64910690c574 1822 /* @brief Has TPM module(s) configuration. */
AnnaBridge 145:64910690c574 1823 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
AnnaBridge 145:64910690c574 1824 /* @brief The highest TPM module index. */
AnnaBridge 145:64910690c574 1825 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
AnnaBridge 145:64910690c574 1826 /* @brief Has TPM module with index 0. */
AnnaBridge 145:64910690c574 1827 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
AnnaBridge 145:64910690c574 1828 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
AnnaBridge 145:64910690c574 1829 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
AnnaBridge 145:64910690c574 1830 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
AnnaBridge 145:64910690c574 1831 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
AnnaBridge 145:64910690c574 1832 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
AnnaBridge 145:64910690c574 1833 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
AnnaBridge 145:64910690c574 1834 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
AnnaBridge 145:64910690c574 1835 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
AnnaBridge 145:64910690c574 1836 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
AnnaBridge 145:64910690c574 1837 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
AnnaBridge 145:64910690c574 1838 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
AnnaBridge 145:64910690c574 1839 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
AnnaBridge 145:64910690c574 1840 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
AnnaBridge 145:64910690c574 1841 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
AnnaBridge 145:64910690c574 1842 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
AnnaBridge 145:64910690c574 1843 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
AnnaBridge 145:64910690c574 1844 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
AnnaBridge 145:64910690c574 1845 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
AnnaBridge 145:64910690c574 1846 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
AnnaBridge 145:64910690c574 1847 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
AnnaBridge 145:64910690c574 1848 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
AnnaBridge 145:64910690c574 1849 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
AnnaBridge 145:64910690c574 1850 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
AnnaBridge 145:64910690c574 1851 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
AnnaBridge 145:64910690c574 1852 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
AnnaBridge 145:64910690c574 1853 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
AnnaBridge 145:64910690c574 1854 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
AnnaBridge 145:64910690c574 1855 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
AnnaBridge 145:64910690c574 1856 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
AnnaBridge 145:64910690c574 1857 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
AnnaBridge 145:64910690c574 1858 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
AnnaBridge 145:64910690c574 1859 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
AnnaBridge 145:64910690c574 1860 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
AnnaBridge 145:64910690c574 1861 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
AnnaBridge 145:64910690c574 1862 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
AnnaBridge 145:64910690c574 1863 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
AnnaBridge 145:64910690c574 1864 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
AnnaBridge 145:64910690c574 1865 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1)
AnnaBridge 145:64910690c574 1866 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
AnnaBridge 145:64910690c574 1867 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
AnnaBridge 145:64910690c574 1868 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
AnnaBridge 145:64910690c574 1869 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
AnnaBridge 145:64910690c574 1870 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
AnnaBridge 145:64910690c574 1871 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1)
AnnaBridge 145:64910690c574 1872 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
AnnaBridge 145:64910690c574 1873 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
AnnaBridge 145:64910690c574 1874 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
AnnaBridge 145:64910690c574 1875 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
AnnaBridge 145:64910690c574 1876 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
AnnaBridge 145:64910690c574 1877 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
AnnaBridge 145:64910690c574 1878 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
AnnaBridge 145:64910690c574 1879 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
AnnaBridge 145:64910690c574 1880 /* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */
AnnaBridge 145:64910690c574 1881 #define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0)
AnnaBridge 145:64910690c574 1882 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
AnnaBridge 145:64910690c574 1883 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0)
AnnaBridge 145:64910690c574 1884 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
AnnaBridge 145:64910690c574 1885 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
AnnaBridge 145:64910690c574 1886 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
AnnaBridge 145:64910690c574 1887 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
AnnaBridge 145:64910690c574 1888 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
AnnaBridge 145:64910690c574 1889 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
AnnaBridge 145:64910690c574 1890 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
AnnaBridge 145:64910690c574 1891 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
AnnaBridge 145:64910690c574 1892 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
AnnaBridge 145:64910690c574 1893 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
AnnaBridge 145:64910690c574 1894 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
AnnaBridge 145:64910690c574 1895 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
AnnaBridge 145:64910690c574 1896 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
AnnaBridge 145:64910690c574 1897 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
AnnaBridge 145:64910690c574 1898 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
AnnaBridge 145:64910690c574 1899 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
AnnaBridge 145:64910690c574 1900 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
AnnaBridge 145:64910690c574 1901 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
AnnaBridge 145:64910690c574 1902 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
AnnaBridge 145:64910690c574 1903 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
AnnaBridge 145:64910690c574 1904 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
AnnaBridge 145:64910690c574 1905 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
AnnaBridge 145:64910690c574 1906 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
AnnaBridge 145:64910690c574 1907 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
AnnaBridge 145:64910690c574 1908 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
AnnaBridge 145:64910690c574 1909 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
AnnaBridge 145:64910690c574 1910 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
AnnaBridge 145:64910690c574 1911 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (1)
AnnaBridge 145:64910690c574 1912 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
AnnaBridge 145:64910690c574 1913 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
AnnaBridge 145:64910690c574 1914 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
AnnaBridge 145:64910690c574 1915 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
AnnaBridge 145:64910690c574 1916 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
AnnaBridge 145:64910690c574 1917 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
AnnaBridge 145:64910690c574 1918 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
AnnaBridge 145:64910690c574 1919 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1)
AnnaBridge 145:64910690c574 1920 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
AnnaBridge 145:64910690c574 1921 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
AnnaBridge 145:64910690c574 1922 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
AnnaBridge 145:64910690c574 1923 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
AnnaBridge 145:64910690c574 1924 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
AnnaBridge 145:64910690c574 1925 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
AnnaBridge 145:64910690c574 1926 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
AnnaBridge 145:64910690c574 1927 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
AnnaBridge 145:64910690c574 1928 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
AnnaBridge 145:64910690c574 1929 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
AnnaBridge 145:64910690c574 1930 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
AnnaBridge 145:64910690c574 1931 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
AnnaBridge 145:64910690c574 1932 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
AnnaBridge 145:64910690c574 1933 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0)
AnnaBridge 145:64910690c574 1934 /* @brief Has device die ID (register bit field SDID[DIEID]). */
AnnaBridge 145:64910690c574 1935 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
AnnaBridge 145:64910690c574 1936 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
AnnaBridge 145:64910690c574 1937 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
AnnaBridge 145:64910690c574 1938 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
AnnaBridge 145:64910690c574 1939 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
AnnaBridge 145:64910690c574 1940 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
AnnaBridge 145:64910690c574 1941 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
AnnaBridge 145:64910690c574 1942 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
AnnaBridge 145:64910690c574 1943 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
AnnaBridge 145:64910690c574 1944 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
AnnaBridge 145:64910690c574 1945 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
AnnaBridge 145:64910690c574 1946 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
AnnaBridge 145:64910690c574 1947 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
AnnaBridge 145:64910690c574 1948 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
AnnaBridge 145:64910690c574 1949 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
AnnaBridge 145:64910690c574 1950 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
AnnaBridge 145:64910690c574 1951 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
AnnaBridge 145:64910690c574 1952 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
AnnaBridge 145:64910690c574 1953 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
AnnaBridge 145:64910690c574 1954 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
AnnaBridge 145:64910690c574 1955 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
AnnaBridge 145:64910690c574 1956 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
AnnaBridge 145:64910690c574 1957 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
AnnaBridge 145:64910690c574 1958 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
AnnaBridge 145:64910690c574 1959 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
AnnaBridge 145:64910690c574 1960 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
AnnaBridge 145:64910690c574 1961 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
AnnaBridge 145:64910690c574 1962 /* @brief Has miscellanious control register (register MCR). */
AnnaBridge 145:64910690c574 1963 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
AnnaBridge 145:64910690c574 1964 /* @brief Has COP watchdog (registers COPC and SRVCOP). */
AnnaBridge 145:64910690c574 1965 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
AnnaBridge 145:64910690c574 1966 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
AnnaBridge 145:64910690c574 1967 #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
AnnaBridge 145:64910690c574 1968 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
AnnaBridge 145:64910690c574 1969 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
AnnaBridge 145:64910690c574 1970 /* @brief Has MISCCTRL reg. */
AnnaBridge 145:64910690c574 1971 #define FSL_FEATURE_SIM_HAS_MISCCTRL (1)
AnnaBridge 145:64910690c574 1972 /* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */
AnnaBridge 145:64910690c574 1973 #define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (1)
AnnaBridge 145:64910690c574 1974 /* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */
AnnaBridge 145:64910690c574 1975 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (1)
AnnaBridge 145:64910690c574 1976 /* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */
AnnaBridge 145:64910690c574 1977 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (1)
AnnaBridge 145:64910690c574 1978 /* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */
AnnaBridge 145:64910690c574 1979 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (1)
AnnaBridge 145:64910690c574 1980 /* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */
AnnaBridge 145:64910690c574 1981 #define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (1)
AnnaBridge 145:64910690c574 1982 /* @brief Has SECKEY0 reg. */
AnnaBridge 145:64910690c574 1983 #define FSL_FEATURE_SIM_HAS_SECKEY0 (1)
AnnaBridge 145:64910690c574 1984 /* @brief Has SECKEY bit (e.g SIM_SECKEY0). */
AnnaBridge 145:64910690c574 1985 #define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (1)
AnnaBridge 145:64910690c574 1986 /* @brief Has SECKEY1 reg. */
AnnaBridge 145:64910690c574 1987 #define FSL_FEATURE_SIM_HAS_SECKEY1 (1)
AnnaBridge 145:64910690c574 1988 /* @brief Has SECKEY bit (e.g SIM_SECKEY1). */
AnnaBridge 145:64910690c574 1989 #define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (1)
AnnaBridge 145:64910690c574 1990 /* @brief Has SECKEY2 reg. */
AnnaBridge 145:64910690c574 1991 #define FSL_FEATURE_SIM_HAS_SECKEY2 (1)
AnnaBridge 145:64910690c574 1992 /* @brief Has SECKEY bit (e.g SIM_SECKEY2). */
AnnaBridge 145:64910690c574 1993 #define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (1)
AnnaBridge 145:64910690c574 1994 /* @brief Has SECKEY3 reg. */
AnnaBridge 145:64910690c574 1995 #define FSL_FEATURE_SIM_HAS_SECKEY3 (1)
AnnaBridge 145:64910690c574 1996 /* @brief Has SECKEY bit (e.g SIM_SECKEY3). */
AnnaBridge 145:64910690c574 1997 #define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (1)
AnnaBridge 145:64910690c574 1998
AnnaBridge 145:64910690c574 1999 /* SMC module features */
AnnaBridge 145:64910690c574 2000
AnnaBridge 145:64910690c574 2001 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
AnnaBridge 145:64910690c574 2002 #define FSL_FEATURE_SMC_HAS_PSTOPO (1)
AnnaBridge 145:64910690c574 2003 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
AnnaBridge 145:64910690c574 2004 #define FSL_FEATURE_SMC_HAS_LPOPO (1)
AnnaBridge 145:64910690c574 2005 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
AnnaBridge 145:64910690c574 2006 #define FSL_FEATURE_SMC_HAS_PORPO (1)
AnnaBridge 145:64910690c574 2007 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
AnnaBridge 145:64910690c574 2008 #define FSL_FEATURE_SMC_HAS_LPWUI (0)
AnnaBridge 145:64910690c574 2009 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
AnnaBridge 145:64910690c574 2010 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
AnnaBridge 145:64910690c574 2011 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
AnnaBridge 145:64910690c574 2012 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
AnnaBridge 145:64910690c574 2013 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
AnnaBridge 145:64910690c574 2014 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
AnnaBridge 145:64910690c574 2015 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
AnnaBridge 145:64910690c574 2016 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
AnnaBridge 145:64910690c574 2017 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
AnnaBridge 145:64910690c574 2018 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
AnnaBridge 145:64910690c574 2019 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
AnnaBridge 145:64910690c574 2020 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
AnnaBridge 145:64910690c574 2021 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
AnnaBridge 145:64910690c574 2022 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
AnnaBridge 145:64910690c574 2023 /* @brief Has stop submode. */
AnnaBridge 145:64910690c574 2024 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
AnnaBridge 145:64910690c574 2025 /* @brief Has stop submode 0(VLLS0). */
AnnaBridge 145:64910690c574 2026 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
AnnaBridge 145:64910690c574 2027 /* @brief Has stop submode 2(VLLS2). */
AnnaBridge 145:64910690c574 2028 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
AnnaBridge 145:64910690c574 2029 /* @brief Has SMC_PARAM. */
AnnaBridge 145:64910690c574 2030 #define FSL_FEATURE_SMC_HAS_PARAM (0)
AnnaBridge 145:64910690c574 2031 /* @brief Has SMC_VERID. */
AnnaBridge 145:64910690c574 2032 #define FSL_FEATURE_SMC_HAS_VERID (0)
AnnaBridge 145:64910690c574 2033
AnnaBridge 145:64910690c574 2034 /* DSPI module features */
AnnaBridge 145:64910690c574 2035
AnnaBridge 145:64910690c574 2036 #if defined(CPU_MKL82Z128VLH7) || defined(CPU_MKL82Z128VLK7) || defined(CPU_MKL82Z128VMP7)
AnnaBridge 145:64910690c574 2037 /* @brief Receive/transmit FIFO size in number of items. */
AnnaBridge 145:64910690c574 2038 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
AnnaBridge 145:64910690c574 2039 ((x) == DSPI0 ? (4) : \
AnnaBridge 145:64910690c574 2040 ((x) == DSPI1 ? (1) : (-1)))
AnnaBridge 145:64910690c574 2041 /* @brief Maximum transfer data width in bits. */
AnnaBridge 145:64910690c574 2042 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
AnnaBridge 145:64910690c574 2043 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
AnnaBridge 145:64910690c574 2044 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
AnnaBridge 145:64910690c574 2045 /* @brief Number of chip select pins. */
AnnaBridge 145:64910690c574 2046 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
AnnaBridge 145:64910690c574 2047 /* @brief Has chip select strobe capability on the PCS5 pin. */
AnnaBridge 145:64910690c574 2048 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
AnnaBridge 145:64910690c574 2049 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
AnnaBridge 145:64910690c574 2050 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
AnnaBridge 145:64910690c574 2051 /* @brief Has 16-bit data transfer support. */
AnnaBridge 145:64910690c574 2052 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
AnnaBridge 145:64910690c574 2053 /* @brief Has separate DMA RX and TX requests. */
AnnaBridge 145:64910690c574 2054 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
AnnaBridge 145:64910690c574 2055 #elif defined(CPU_MKL82Z128VLL7) || defined(CPU_MKL82Z128VMC7)
AnnaBridge 145:64910690c574 2056 /* @brief Receive/transmit FIFO size in number of items. */
AnnaBridge 145:64910690c574 2057 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
AnnaBridge 145:64910690c574 2058 ((x) == DSPI0 ? (4) : \
AnnaBridge 145:64910690c574 2059 ((x) == DSPI1 ? (1) : (-1)))
AnnaBridge 145:64910690c574 2060 /* @brief Maximum transfer data width in bits. */
AnnaBridge 145:64910690c574 2061 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
AnnaBridge 145:64910690c574 2062 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
AnnaBridge 145:64910690c574 2063 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
AnnaBridge 145:64910690c574 2064 /* @brief Number of chip select pins. */
AnnaBridge 145:64910690c574 2065 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
AnnaBridge 145:64910690c574 2066 /* @brief Has chip select strobe capability on the PCS5 pin. */
AnnaBridge 145:64910690c574 2067 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
AnnaBridge 145:64910690c574 2068 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
AnnaBridge 145:64910690c574 2069 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
AnnaBridge 145:64910690c574 2070 /* @brief Has 16-bit data transfer support. */
AnnaBridge 145:64910690c574 2071 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
AnnaBridge 145:64910690c574 2072 /* @brief Has separate DMA RX and TX requests. */
AnnaBridge 145:64910690c574 2073 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
AnnaBridge 145:64910690c574 2074 #endif /* defined(CPU_MKL82Z128VLH7) || defined(CPU_MKL82Z128VLK7) || defined(CPU_MKL82Z128VMP7) */
AnnaBridge 145:64910690c574 2075
AnnaBridge 145:64910690c574 2076 /* SysTick module features */
AnnaBridge 145:64910690c574 2077
AnnaBridge 145:64910690c574 2078 /* @brief Systick has external reference clock. */
AnnaBridge 145:64910690c574 2079 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
AnnaBridge 145:64910690c574 2080 /* @brief Systick external reference clock is core clock divided by this value. */
AnnaBridge 145:64910690c574 2081 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
AnnaBridge 145:64910690c574 2082
AnnaBridge 145:64910690c574 2083 /* TPM module features */
AnnaBridge 145:64910690c574 2084
AnnaBridge 145:64910690c574 2085 /* @brief Bus clock is the source clock for the module. */
AnnaBridge 145:64910690c574 2086 #define FSL_FEATURE_TPM_BUS_CLOCK (0)
AnnaBridge 145:64910690c574 2087 /* @brief Number of channels. */
AnnaBridge 145:64910690c574 2088 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
AnnaBridge 145:64910690c574 2089 ((x) == TPM0 ? (6) : \
AnnaBridge 145:64910690c574 2090 ((x) == TPM1 ? (2) : \
AnnaBridge 145:64910690c574 2091 ((x) == TPM2 ? (2) : (-1))))
AnnaBridge 145:64910690c574 2092 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
AnnaBridge 145:64910690c574 2093 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
AnnaBridge 145:64910690c574 2094 /* @brief Has TPM_PARAM. */
AnnaBridge 145:64910690c574 2095 #define FSL_FEATURE_TPM_HAS_PARAM (0)
AnnaBridge 145:64910690c574 2096 /* @brief Has TPM_VERID. */
AnnaBridge 145:64910690c574 2097 #define FSL_FEATURE_TPM_HAS_VERID (0)
AnnaBridge 145:64910690c574 2098 /* @brief Has TPM_GLOBAL. */
AnnaBridge 145:64910690c574 2099 #define FSL_FEATURE_TPM_HAS_GLOBAL (0)
AnnaBridge 145:64910690c574 2100 /* @brief Has TPM_TRIG. */
AnnaBridge 145:64910690c574 2101 #define FSL_FEATURE_TPM_HAS_TRIG (0)
AnnaBridge 145:64910690c574 2102 /* @brief Has counter pause on trigger. */
AnnaBridge 145:64910690c574 2103 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
AnnaBridge 145:64910690c574 2104 /* @brief Has external trigger selection. */
AnnaBridge 145:64910690c574 2105 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
AnnaBridge 145:64910690c574 2106 /* @brief Has TPM_COMBINE. */
AnnaBridge 145:64910690c574 2107 #define FSL_FEATURE_TPM_HAS_COMBINE (1)
AnnaBridge 145:64910690c574 2108 /* @brief Has TPM_POL. */
AnnaBridge 145:64910690c574 2109 #define FSL_FEATURE_TPM_HAS_POL (1)
AnnaBridge 145:64910690c574 2110 /* @brief Has TPM_FILTER. */
AnnaBridge 145:64910690c574 2111 #define FSL_FEATURE_TPM_HAS_FILTER (1)
AnnaBridge 145:64910690c574 2112 /* @brief Has TPM_QDCTRL. */
AnnaBridge 145:64910690c574 2113 #define FSL_FEATURE_TPM_HAS_QDCTRL (0)
AnnaBridge 145:64910690c574 2114
AnnaBridge 145:64910690c574 2115 /* TSI module features */
AnnaBridge 145:64910690c574 2116
AnnaBridge 145:64910690c574 2117 /* @brief TSI module version. */
AnnaBridge 145:64910690c574 2118 #define FSL_FEATURE_TSI_VERSION (4)
AnnaBridge 145:64910690c574 2119 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
AnnaBridge 145:64910690c574 2120 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (1)
AnnaBridge 145:64910690c574 2121 /* @brief Number of TSI channels. */
AnnaBridge 145:64910690c574 2122 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
AnnaBridge 145:64910690c574 2123
AnnaBridge 145:64910690c574 2124 /* USB module features */
AnnaBridge 145:64910690c574 2125
AnnaBridge 145:64910690c574 2126 /* @brief HOST mode enabled */
AnnaBridge 145:64910690c574 2127 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
AnnaBridge 145:64910690c574 2128 /* @brief OTG mode enabled */
AnnaBridge 145:64910690c574 2129 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
AnnaBridge 145:64910690c574 2130 /* @brief Size of the USB dedicated RAM */
AnnaBridge 145:64910690c574 2131 #define FSL_FEATURE_USB_KHCI_USB_RAM (2048)
AnnaBridge 145:64910690c574 2132 /* @brief Base address of the USB dedicated RAM */
AnnaBridge 145:64910690c574 2133 #define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074790400)
AnnaBridge 145:64910690c574 2134 /* @brief Has KEEP_ALIVE_CTRL register */
AnnaBridge 145:64910690c574 2135 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1)
AnnaBridge 145:64910690c574 2136 /* @brief Mode control of the USB Keep Alive */
AnnaBridge 145:64910690c574 2137 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
AnnaBridge 145:64910690c574 2138 /* @brief Has the Dynamic SOF threshold compare support */
AnnaBridge 145:64910690c574 2139 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1)
AnnaBridge 145:64910690c574 2140 /* @brief Has the VBUS detect support */
AnnaBridge 145:64910690c574 2141 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1)
AnnaBridge 145:64910690c574 2142 /* @brief Has the IRC48M module clock support */
AnnaBridge 145:64910690c574 2143 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
AnnaBridge 145:64910690c574 2144 /* @brief Number of endpoints supported */
AnnaBridge 145:64910690c574 2145 #define FSL_FEATURE_USB_ENDPT_COUNT (16)
AnnaBridge 145:64910690c574 2146
AnnaBridge 145:64910690c574 2147 /* VREF module features */
AnnaBridge 145:64910690c574 2148
AnnaBridge 145:64910690c574 2149 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */
AnnaBridge 145:64910690c574 2150 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
AnnaBridge 145:64910690c574 2151 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
AnnaBridge 145:64910690c574 2152 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
AnnaBridge 145:64910690c574 2153 /* @brief If high/low buffer mode supported */
AnnaBridge 145:64910690c574 2154 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
AnnaBridge 145:64910690c574 2155 /* @brief Module has also low reference (registers VREFL/VREFH) */
AnnaBridge 145:64910690c574 2156 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
AnnaBridge 145:64910690c574 2157 /* @brief Has VREF_TRM4. */
AnnaBridge 145:64910690c574 2158 #define FSL_FEATURE_VREF_HAS_TRM4 (0)
AnnaBridge 145:64910690c574 2159
AnnaBridge 145:64910690c574 2160 /* WDOG module features */
AnnaBridge 145:64910690c574 2161
AnnaBridge 145:64910690c574 2162 /* @brief Watchdog is available. */
AnnaBridge 145:64910690c574 2163 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
AnnaBridge 145:64910690c574 2164 /* @brief Has Wait mode support. */
AnnaBridge 145:64910690c574 2165 #define FSL_FEATURE_WDOG_HAS_WAITEN (1)
AnnaBridge 145:64910690c574 2166
AnnaBridge 145:64910690c574 2167 #endif /* _MKL82Z7_FEATURES_H_ */
AnnaBridge 145:64910690c574 2168