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TARGET_KL82Z/TOOLCHAIN_GCC_ARM/fsl_qspi.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * The Clear BSD License
AnnaBridge 171:3a7713b1edbc 3 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 4 * Copyright 2016-2017 NXP
AnnaBridge 171:3a7713b1edbc 5 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 6 *
AnnaBridge 171:3a7713b1edbc 7 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 8 * are permitted (subject to the limitations in the disclaimer below) provided
AnnaBridge 171:3a7713b1edbc 9 * that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 12 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 15 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 16 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 171:3a7713b1edbc 19 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 20 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
AnnaBridge 171:3a7713b1edbc 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 33 */
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 #ifndef _FSL_QSPI_H_
AnnaBridge 171:3a7713b1edbc 36 #define _FSL_QSPI_H_
AnnaBridge 171:3a7713b1edbc 37
AnnaBridge 171:3a7713b1edbc 38 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /*!
AnnaBridge 171:3a7713b1edbc 41 * @addtogroup qspi
AnnaBridge 171:3a7713b1edbc 42 * @{
AnnaBridge 171:3a7713b1edbc 43 */
AnnaBridge 171:3a7713b1edbc 44
AnnaBridge 171:3a7713b1edbc 45 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 46 * Definitions
AnnaBridge 171:3a7713b1edbc 47 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 50 /*@{*/
AnnaBridge 171:3a7713b1edbc 51 /*! @brief QSPI driver version 2.0.2. */
AnnaBridge 171:3a7713b1edbc 52 #define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
AnnaBridge 171:3a7713b1edbc 53 /*@}*/
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /*! @brief Macro functions for LUT table */
AnnaBridge 171:3a7713b1edbc 56 #define QSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
AnnaBridge 171:3a7713b1edbc 57 (QuadSPI_LUT_INSTR0(cmd0) | QuadSPI_LUT_PAD0(pad0) | QuadSPI_LUT_OPRND0(op0) | QuadSPI_LUT_INSTR1(cmd1) | \
AnnaBridge 171:3a7713b1edbc 58 QuadSPI_LUT_PAD1(pad1) | QuadSPI_LUT_OPRND1(op1))
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 /*! @brief Macro for QSPI LUT command */
AnnaBridge 171:3a7713b1edbc 61 #define QSPI_CMD (0x1U)
AnnaBridge 171:3a7713b1edbc 62 #define QSPI_ADDR (0x2U)
AnnaBridge 171:3a7713b1edbc 63 #define QSPI_DUMMY (0x3U)
AnnaBridge 171:3a7713b1edbc 64 #define QSPI_MODE (0x4U)
AnnaBridge 171:3a7713b1edbc 65 #define QSPI_MODE2 (0x5U)
AnnaBridge 171:3a7713b1edbc 66 #define QSPI_MODE4 (0x6U)
AnnaBridge 171:3a7713b1edbc 67 #define QSPI_READ (0x7U)
AnnaBridge 171:3a7713b1edbc 68 #define QSPI_WRITE (0x8U)
AnnaBridge 171:3a7713b1edbc 69 #define QSPI_JMP_ON_CS (0x9U)
AnnaBridge 171:3a7713b1edbc 70 #define QSPI_ADDR_DDR (0xAU)
AnnaBridge 171:3a7713b1edbc 71 #define QSPI_MODE_DDR (0xBU)
AnnaBridge 171:3a7713b1edbc 72 #define QSPI_MODE2_DDR (0xCU)
AnnaBridge 171:3a7713b1edbc 73 #define QSPI_MODE4_DDR (0xDU)
AnnaBridge 171:3a7713b1edbc 74 #define QSPI_READ_DDR (0xEU)
AnnaBridge 171:3a7713b1edbc 75 #define QSPI_WRITE_DDR (0xFU)
AnnaBridge 171:3a7713b1edbc 76 #define QSPI_DATA_LEARN (0x10U)
AnnaBridge 171:3a7713b1edbc 77 #define QSPI_CMD_DDR (0x11U)
AnnaBridge 171:3a7713b1edbc 78 #define QSPI_CADDR (0x12U)
AnnaBridge 171:3a7713b1edbc 79 #define QSPI_CADDR_DDR (0x13U)
AnnaBridge 171:3a7713b1edbc 80 #define QSPI_STOP (0x0U)
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 /*! @brief Macro for QSPI PAD */
AnnaBridge 171:3a7713b1edbc 83 #define QSPI_PAD_1 (0x0U)
AnnaBridge 171:3a7713b1edbc 84 #define QSPI_PAD_2 (0x1U)
AnnaBridge 171:3a7713b1edbc 85 #define QSPI_PAD_4 (0x2U)
AnnaBridge 171:3a7713b1edbc 86 #define QSPI_PAD_8 (0x3U)
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 /*! @brief Status structure of QSPI.*/
AnnaBridge 171:3a7713b1edbc 89 enum _status_t
AnnaBridge 171:3a7713b1edbc 90 {
AnnaBridge 171:3a7713b1edbc 91 kStatus_QSPI_Idle = MAKE_STATUS(kStatusGroup_QSPI, 0), /*!< QSPI is in idle state */
AnnaBridge 171:3a7713b1edbc 92 kStatus_QSPI_Busy = MAKE_STATUS(kStatusGroup_QSPI, 1), /*!< QSPI is busy */
AnnaBridge 171:3a7713b1edbc 93 kStatus_QSPI_Error = MAKE_STATUS(kStatusGroup_QSPI, 2), /*!< Error occurred during QSPI transfer */
AnnaBridge 171:3a7713b1edbc 94 };
AnnaBridge 171:3a7713b1edbc 95
AnnaBridge 171:3a7713b1edbc 96 /*! @brief QSPI read data area, from IP FIFO or AHB buffer.*/
AnnaBridge 171:3a7713b1edbc 97 typedef enum _qspi_read_area
AnnaBridge 171:3a7713b1edbc 98 {
AnnaBridge 171:3a7713b1edbc 99 kQSPI_ReadAHB = 0x0U, /*!< QSPI read from AHB buffer. */
AnnaBridge 171:3a7713b1edbc 100 kQSPI_ReadIP /*!< QSPI read from IP FIFO. */
AnnaBridge 171:3a7713b1edbc 101 } qspi_read_area_t;
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 /*! @brief QSPI command sequence type */
AnnaBridge 171:3a7713b1edbc 104 typedef enum _qspi_command_seq
AnnaBridge 171:3a7713b1edbc 105 {
AnnaBridge 171:3a7713b1edbc 106 kQSPI_IPSeq = QuadSPI_SPTRCLR_IPPTRC_MASK, /*!< IP command sequence */
AnnaBridge 171:3a7713b1edbc 107 kQSPI_BufferSeq = QuadSPI_SPTRCLR_BFPTRC_MASK, /*!< Buffer command sequence */
AnnaBridge 171:3a7713b1edbc 108 kQSPI_AllSeq = QuadSPI_SPTRCLR_IPPTRC_MASK | QuadSPI_SPTRCLR_BFPTRC_MASK /* All command sequence */
AnnaBridge 171:3a7713b1edbc 109 } qspi_command_seq_t;
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /*! @brief QSPI buffer type */
AnnaBridge 171:3a7713b1edbc 112 typedef enum _qspi_fifo
AnnaBridge 171:3a7713b1edbc 113 {
AnnaBridge 171:3a7713b1edbc 114 kQSPI_TxFifo = QuadSPI_MCR_CLR_TXF_MASK, /*!< QSPI Tx FIFO */
AnnaBridge 171:3a7713b1edbc 115 kQSPI_RxFifo = QuadSPI_MCR_CLR_RXF_MASK, /*!< QSPI Rx FIFO */
AnnaBridge 171:3a7713b1edbc 116 kQSPI_AllFifo = QuadSPI_MCR_CLR_TXF_MASK | QuadSPI_MCR_CLR_RXF_MASK /*!< QSPI all FIFO, including Tx and Rx */
AnnaBridge 171:3a7713b1edbc 117 } qspi_fifo_t;
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 /*! @brief QSPI transfer endianess*/
AnnaBridge 171:3a7713b1edbc 120 typedef enum _qspi_endianness
AnnaBridge 171:3a7713b1edbc 121 {
AnnaBridge 171:3a7713b1edbc 122 kQSPI_64BigEndian = 0x0U, /*!< 64 bits big endian */
AnnaBridge 171:3a7713b1edbc 123 kQSPI_32LittleEndian, /*!< 32 bit little endian */
AnnaBridge 171:3a7713b1edbc 124 kQSPI_32BigEndian, /*!< 32 bit big endian */
AnnaBridge 171:3a7713b1edbc 125 kQSPI_64LittleEndian /*!< 64 bit little endian */
AnnaBridge 171:3a7713b1edbc 126 } qspi_endianness_t;
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 /*! @brief QSPI error flags */
AnnaBridge 171:3a7713b1edbc 129 enum _qspi_error_flags
AnnaBridge 171:3a7713b1edbc 130 {
AnnaBridge 171:3a7713b1edbc 131 kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
AnnaBridge 171:3a7713b1edbc 132 kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */
AnnaBridge 171:3a7713b1edbc 133 kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */
AnnaBridge 171:3a7713b1edbc 134 kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */
AnnaBridge 171:3a7713b1edbc 135 kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */
AnnaBridge 171:3a7713b1edbc 136 kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */
AnnaBridge 171:3a7713b1edbc 137 kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */
AnnaBridge 171:3a7713b1edbc 138 #if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
AnnaBridge 171:3a7713b1edbc 139 kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */
AnnaBridge 171:3a7713b1edbc 140 #endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
AnnaBridge 171:3a7713b1edbc 141 #if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
AnnaBridge 171:3a7713b1edbc 142 kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */
AnnaBridge 171:3a7713b1edbc 143 #endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
AnnaBridge 171:3a7713b1edbc 144 kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */
AnnaBridge 171:3a7713b1edbc 145 #if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
AnnaBridge 171:3a7713b1edbc 146 kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK, /*!< IP command usage error flag */
AnnaBridge 171:3a7713b1edbc 147 #endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
AnnaBridge 171:3a7713b1edbc 148 kQSPI_IPCommandTriggerDuringAHBAccess = QuadSPI_FR_IPAEF_MASK, /*!< IP command trigger during AHB access error */
AnnaBridge 171:3a7713b1edbc 149 kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK, /*!< IP command trigger cannot be executed */
AnnaBridge 171:3a7713b1edbc 150 kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, /*!< IP command trigger during AHB grant error */
AnnaBridge 171:3a7713b1edbc 151 kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, /*!< IP command transaction finished flag */
AnnaBridge 171:3a7713b1edbc 152 kQSPI_FlagAll = (int)0x8C83F8D1U /*!< All error flag */
AnnaBridge 171:3a7713b1edbc 153 };
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 /*! @brief QSPI state bit */
AnnaBridge 171:3a7713b1edbc 156 enum _qspi_flags
AnnaBridge 171:3a7713b1edbc 157 {
AnnaBridge 171:3a7713b1edbc 158 kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
AnnaBridge 171:3a7713b1edbc 159 kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */
AnnaBridge 171:3a7713b1edbc 160 #if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
AnnaBridge 171:3a7713b1edbc 161 kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK, /*!< Tx DMA is requested or running */
AnnaBridge 171:3a7713b1edbc 162 kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK, /*!< Tx buffer watermark available */
AnnaBridge 171:3a7713b1edbc 163 #endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
AnnaBridge 171:3a7713b1edbc 164 kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, /*!< Tx buffer enough data available */
AnnaBridge 171:3a7713b1edbc 165 kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, /*!< Rx DMA is requesting or running */
AnnaBridge 171:3a7713b1edbc 166 kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */
AnnaBridge 171:3a7713b1edbc 167 kQSPI_RxWatermark = QuadSPI_SR_RXWE_MASK, /*!< Rx buffer watermark exceeded */
AnnaBridge 171:3a7713b1edbc 168 kQSPI_AHB3BufferFull = QuadSPI_SR_AHB3FUL_MASK, /*!< AHB buffer 3 full*/
AnnaBridge 171:3a7713b1edbc 169 kQSPI_AHB2BufferFull = QuadSPI_SR_AHB2FUL_MASK, /*!< AHB buffer 2 full */
AnnaBridge 171:3a7713b1edbc 170 kQSPI_AHB1BufferFull = QuadSPI_SR_AHB1FUL_MASK, /*!< AHB buffer 1 full */
AnnaBridge 171:3a7713b1edbc 171 kQSPI_AHB0BufferFull = QuadSPI_SR_AHB0FUL_MASK, /*!< AHB buffer 0 full */
AnnaBridge 171:3a7713b1edbc 172 kQSPI_AHB3BufferNotEmpty = QuadSPI_SR_AHB3NE_MASK, /*!< AHB buffer 3 not empty */
AnnaBridge 171:3a7713b1edbc 173 kQSPI_AHB2BufferNotEmpty = QuadSPI_SR_AHB2NE_MASK, /*!< AHB buffer 2 not empty */
AnnaBridge 171:3a7713b1edbc 174 kQSPI_AHB1BufferNotEmpty = QuadSPI_SR_AHB1NE_MASK, /*!< AHB buffer 1 not empty */
AnnaBridge 171:3a7713b1edbc 175 kQSPI_AHB0BufferNotEmpty = QuadSPI_SR_AHB0NE_MASK, /*!< AHB buffer 0 not empty */
AnnaBridge 171:3a7713b1edbc 176 kQSPI_AHBTransactionPending = QuadSPI_SR_AHBTRN_MASK, /*!< AHB access transaction pending */
AnnaBridge 171:3a7713b1edbc 177 kQSPI_AHBCommandPriorityGranted = QuadSPI_SR_AHBGNT_MASK, /*!< AHB command priority granted */
AnnaBridge 171:3a7713b1edbc 178 kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, /*!< AHB access */
AnnaBridge 171:3a7713b1edbc 179 kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, /*!< IP access */
AnnaBridge 171:3a7713b1edbc 180 kQSPI_Busy = QuadSPI_SR_BUSY_MASK, /*!< Module busy */
AnnaBridge 171:3a7713b1edbc 181 kQSPI_StateAll = (int)0xEF897FE7U /*!< All flags */
AnnaBridge 171:3a7713b1edbc 182 };
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 /*! @brief QSPI interrupt enable */
AnnaBridge 171:3a7713b1edbc 185 enum _qspi_interrupt_enable
AnnaBridge 171:3a7713b1edbc 186 {
AnnaBridge 171:3a7713b1edbc 187 kQSPI_DataLearningFailInterruptEnable =
AnnaBridge 171:3a7713b1edbc 188 (int)QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
AnnaBridge 171:3a7713b1edbc 189 kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */
AnnaBridge 171:3a7713b1edbc 190 kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */
AnnaBridge 171:3a7713b1edbc 191 kQSPI_IllegalInstructionInterruptEnable =
AnnaBridge 171:3a7713b1edbc 192 QuadSPI_RSER_ILLINIE_MASK, /*!< Illegal instruction error interrupt enable */
AnnaBridge 171:3a7713b1edbc 193 kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK, /*!< Rx buffer overflow interrupt enable */
AnnaBridge 171:3a7713b1edbc 194 kQSPI_RxBufferDrainInterruptEnable = QuadSPI_RSER_RBDIE_MASK, /*!< Rx buffer drain interrupt enable */
AnnaBridge 171:3a7713b1edbc 195 kQSPI_AHBSequenceErrorInterruptEnable = QuadSPI_RSER_ABSEIE_MASK, /*!< AHB sequence error interrupt enable */
AnnaBridge 171:3a7713b1edbc 196 #if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
AnnaBridge 171:3a7713b1edbc 197 kQSPI_AHBIllegalTransactionInterruptEnable =
AnnaBridge 171:3a7713b1edbc 198 QuadSPI_RSER_AITIE_MASK, /*!< AHB illegal transaction error interrupt enable */
AnnaBridge 171:3a7713b1edbc 199 #endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
AnnaBridge 171:3a7713b1edbc 200 #if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
AnnaBridge 171:3a7713b1edbc 201 kQSPI_AHBIllegalBurstSizeInterruptEnable =
AnnaBridge 171:3a7713b1edbc 202 QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */
AnnaBridge 171:3a7713b1edbc 203 #endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
AnnaBridge 171:3a7713b1edbc 204 kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */
AnnaBridge 171:3a7713b1edbc 205 #if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
AnnaBridge 171:3a7713b1edbc 206 kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, /*!< IP command usage error interrupt enable */
AnnaBridge 171:3a7713b1edbc 207 #endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
AnnaBridge 171:3a7713b1edbc 208 kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable =
AnnaBridge 171:3a7713b1edbc 209 QuadSPI_RSER_IPAEIE_MASK, /*!< IP command trigger during AHB access error */
AnnaBridge 171:3a7713b1edbc 210 kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable =
AnnaBridge 171:3a7713b1edbc 211 QuadSPI_RSER_IPIEIE_MASK, /*!< IP command trigger cannot be executed */
AnnaBridge 171:3a7713b1edbc 212 kQSPI_IPCommandTriggerDuringAHBGrantInterruptEnable =
AnnaBridge 171:3a7713b1edbc 213 QuadSPI_RSER_IPGEIE_MASK, /*!< IP command trigger during AHB grant error */
AnnaBridge 171:3a7713b1edbc 214 kQSPI_IPCommandTransactionFinishedInterruptEnable =
AnnaBridge 171:3a7713b1edbc 215 QuadSPI_RSER_TFIE_MASK, /*!< IP command transaction finished interrupt enable */
AnnaBridge 171:3a7713b1edbc 216 kQSPI_AllInterruptEnable = (int)0x8C83F8D1U /*!< All error interrupt enable */
AnnaBridge 171:3a7713b1edbc 217 };
AnnaBridge 171:3a7713b1edbc 218
AnnaBridge 171:3a7713b1edbc 219 /*! @brief QSPI DMA request flag */
AnnaBridge 171:3a7713b1edbc 220 enum _qspi_dma_enable
AnnaBridge 171:3a7713b1edbc 221 {
AnnaBridge 171:3a7713b1edbc 222 #if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
AnnaBridge 171:3a7713b1edbc 223 kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK, /*!< Tx buffer fill DMA */
AnnaBridge 171:3a7713b1edbc 224 #endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
AnnaBridge 171:3a7713b1edbc 225 kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK, /*!< Rx buffer drain DMA */
AnnaBridge 171:3a7713b1edbc 226 #if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
AnnaBridge 171:3a7713b1edbc 227 kQSPI_AllDDMAEnable = QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK /*!< All DMA source */
AnnaBridge 171:3a7713b1edbc 228 #else
AnnaBridge 171:3a7713b1edbc 229 kQSPI_AllDDMAEnable = QuadSPI_RSER_RBDDE_MASK /* All DMA source */
AnnaBridge 171:3a7713b1edbc 230 #endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
AnnaBridge 171:3a7713b1edbc 231 };
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 /*! @brief Phrase shift number for DQS mode. */
AnnaBridge 171:3a7713b1edbc 234 typedef enum _qspi_dqs_phrase_shift
AnnaBridge 171:3a7713b1edbc 235 {
AnnaBridge 171:3a7713b1edbc 236 kQSPI_DQSNoPhraseShift = 0x0U, /*!< No phase shift */
AnnaBridge 171:3a7713b1edbc 237 kQSPI_DQSPhraseShift45Degree, /*!< Select 45 degree phase shift*/
AnnaBridge 171:3a7713b1edbc 238 kQSPI_DQSPhraseShift90Degree, /*!< Select 90 degree phase shift */
AnnaBridge 171:3a7713b1edbc 239 kQSPI_DQSPhraseShift135Degree /*!< Select 135 degree phase shift */
AnnaBridge 171:3a7713b1edbc 240 } qspi_dqs_phrase_shift_t;
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 /*! @brief DQS configure features*/
AnnaBridge 171:3a7713b1edbc 243 typedef struct QspiDQSConfig
AnnaBridge 171:3a7713b1edbc 244 {
AnnaBridge 171:3a7713b1edbc 245 uint32_t portADelayTapNum; /*!< Delay chain tap number selection for QSPI port A DQS */
AnnaBridge 171:3a7713b1edbc 246 uint32_t portBDelayTapNum; /*!< Delay chain tap number selection for QSPI port B DQS*/
AnnaBridge 171:3a7713b1edbc 247 qspi_dqs_phrase_shift_t shift; /*!< Phase shift for internal DQS generation */
AnnaBridge 171:3a7713b1edbc 248 bool enableDQSClkInverse; /*!< Enable inverse clock for internal DQS generation */
AnnaBridge 171:3a7713b1edbc 249 bool enableDQSPadLoopback; /*!< Enable DQS loop back from DQS pad */
AnnaBridge 171:3a7713b1edbc 250 bool enableDQSLoopback; /*!< Enable DQS loop back */
AnnaBridge 171:3a7713b1edbc 251 } qspi_dqs_config_t;
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 /*! @brief Flash timing configuration. */
AnnaBridge 171:3a7713b1edbc 254 typedef struct QspiFlashTiming
AnnaBridge 171:3a7713b1edbc 255 {
AnnaBridge 171:3a7713b1edbc 256 uint32_t dataHoldTime; /*!< Serial flash data in hold time */
AnnaBridge 171:3a7713b1edbc 257 uint32_t CSHoldTime; /*!< Serial flash CS hold time in terms of serial flash clock cycles */
AnnaBridge 171:3a7713b1edbc 258 uint32_t CSSetupTime; /*!< Serial flash CS setup time in terms of serial flash clock cycles */
AnnaBridge 171:3a7713b1edbc 259 } qspi_flash_timing_t;
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 /*! @brief QSPI configuration structure*/
AnnaBridge 171:3a7713b1edbc 262 typedef struct QspiConfig
AnnaBridge 171:3a7713b1edbc 263 {
AnnaBridge 171:3a7713b1edbc 264 uint32_t clockSource; /*!< Clock source for QSPI module */
AnnaBridge 171:3a7713b1edbc 265 uint32_t baudRate; /*!< Serial flash clock baud rate */
AnnaBridge 171:3a7713b1edbc 266 uint8_t txWatermark; /*!< QSPI transmit watermark value */
AnnaBridge 171:3a7713b1edbc 267 uint8_t rxWatermark; /*!< QSPI receive watermark value. */
AnnaBridge 171:3a7713b1edbc 268 uint32_t AHBbufferSize[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */
AnnaBridge 171:3a7713b1edbc 269 uint8_t AHBbufferMaster[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer master. */
AnnaBridge 171:3a7713b1edbc 270 bool enableAHBbuffer3AllMaster; /*!< Is AHB buffer3 for all master.*/
AnnaBridge 171:3a7713b1edbc 271 qspi_read_area_t area; /*!< Which area Rx data readout */
AnnaBridge 171:3a7713b1edbc 272 bool enableQspi; /*!< Enable QSPI after initialization */
AnnaBridge 171:3a7713b1edbc 273 } qspi_config_t;
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 /*! @brief External flash configuration items*/
AnnaBridge 171:3a7713b1edbc 276 typedef struct _qspi_flash_config
AnnaBridge 171:3a7713b1edbc 277 {
AnnaBridge 171:3a7713b1edbc 278 uint32_t flashA1Size; /*!< Flash A1 size */
AnnaBridge 171:3a7713b1edbc 279 uint32_t flashA2Size; /*!< Flash A2 size */
AnnaBridge 171:3a7713b1edbc 280 #if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
AnnaBridge 171:3a7713b1edbc 281 uint32_t flashB1Size; /*!< Flash B1 size */
AnnaBridge 171:3a7713b1edbc 282 uint32_t flashB2Size; /*!< Flash B2 size */
AnnaBridge 171:3a7713b1edbc 283 #endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
AnnaBridge 171:3a7713b1edbc 284 uint32_t lookuptable[FSL_FEATURE_QSPI_LUT_DEPTH]; /*!< Flash command in LUT */
AnnaBridge 171:3a7713b1edbc 285 #if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
AnnaBridge 171:3a7713b1edbc 286 uint32_t dataHoldTime; /*!< Data line hold time. */
AnnaBridge 171:3a7713b1edbc 287 #endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
AnnaBridge 171:3a7713b1edbc 288 uint32_t CSHoldTime; /*!< CS line hold time */
AnnaBridge 171:3a7713b1edbc 289 uint32_t CSSetupTime; /*!< CS line setup time*/
AnnaBridge 171:3a7713b1edbc 290 uint32_t cloumnspace; /*!< Column space size */
AnnaBridge 171:3a7713b1edbc 291 uint32_t dataLearnValue; /*!< Data Learn value if enable data learn */
AnnaBridge 171:3a7713b1edbc 292 qspi_endianness_t endian; /*!< Flash data endianess. */
AnnaBridge 171:3a7713b1edbc 293 bool enableWordAddress; /*!< If enable word address.*/
AnnaBridge 171:3a7713b1edbc 294 } qspi_flash_config_t;
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 /*! @brief Transfer structure for QSPI */
AnnaBridge 171:3a7713b1edbc 297 typedef struct _qspi_transfer
AnnaBridge 171:3a7713b1edbc 298 {
AnnaBridge 171:3a7713b1edbc 299 uint32_t *data; /*!< Pointer to data to transmit */
AnnaBridge 171:3a7713b1edbc 300 size_t dataSize; /*!< Bytes to be transmit */
AnnaBridge 171:3a7713b1edbc 301 } qspi_transfer_t;
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 /******************************************************************************
AnnaBridge 171:3a7713b1edbc 304 * API
AnnaBridge 171:3a7713b1edbc 305 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 306 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 307 extern "C" {
AnnaBridge 171:3a7713b1edbc 308 #endif
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 /*!
AnnaBridge 171:3a7713b1edbc 311 * @name Initialization and deinitialization
AnnaBridge 171:3a7713b1edbc 312 * @{
AnnaBridge 171:3a7713b1edbc 313 */
AnnaBridge 171:3a7713b1edbc 314
AnnaBridge 171:3a7713b1edbc 315 /*!
AnnaBridge 171:3a7713b1edbc 316 * @brief Get the instance number for QSPI.
AnnaBridge 171:3a7713b1edbc 317 *
AnnaBridge 171:3a7713b1edbc 318 * @param base QSPI base pointer.
AnnaBridge 171:3a7713b1edbc 319 */
AnnaBridge 171:3a7713b1edbc 320 uint32_t QSPI_GetInstance(QuadSPI_Type *base);
AnnaBridge 171:3a7713b1edbc 321
AnnaBridge 171:3a7713b1edbc 322 /*!
AnnaBridge 171:3a7713b1edbc 323 * @brief Initializes the QSPI module and internal state.
AnnaBridge 171:3a7713b1edbc 324 *
AnnaBridge 171:3a7713b1edbc 325 * This function enables the clock for QSPI and also configures the QSPI with the
AnnaBridge 171:3a7713b1edbc 326 * input configure parameters. Users should call this function before any QSPI operations.
AnnaBridge 171:3a7713b1edbc 327 *
AnnaBridge 171:3a7713b1edbc 328 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 329 * @param config QSPI configure structure.
AnnaBridge 171:3a7713b1edbc 330 * @param srcClock_Hz QSPI source clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 331 */
AnnaBridge 171:3a7713b1edbc 332 void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz);
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 /*!
AnnaBridge 171:3a7713b1edbc 335 * @brief Gets default settings for QSPI.
AnnaBridge 171:3a7713b1edbc 336 *
AnnaBridge 171:3a7713b1edbc 337 * @param config QSPI configuration structure.
AnnaBridge 171:3a7713b1edbc 338 */
AnnaBridge 171:3a7713b1edbc 339 void QSPI_GetDefaultQspiConfig(qspi_config_t *config);
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341 /*!
AnnaBridge 171:3a7713b1edbc 342 * @brief Deinitializes the QSPI module.
AnnaBridge 171:3a7713b1edbc 343 *
AnnaBridge 171:3a7713b1edbc 344 * Clears the QSPI state and QSPI module registers.
AnnaBridge 171:3a7713b1edbc 345 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 346 */
AnnaBridge 171:3a7713b1edbc 347 void QSPI_Deinit(QuadSPI_Type *base);
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349 /*!
AnnaBridge 171:3a7713b1edbc 350 * @brief Configures the serial flash parameter.
AnnaBridge 171:3a7713b1edbc 351 *
AnnaBridge 171:3a7713b1edbc 352 * This function configures the serial flash relevant parameters, such as the size, command, and so on.
AnnaBridge 171:3a7713b1edbc 353 * The flash configuration value cannot have a default value. The user needs to configure it according to the
AnnaBridge 171:3a7713b1edbc 354 * QSPI features.
AnnaBridge 171:3a7713b1edbc 355 *
AnnaBridge 171:3a7713b1edbc 356 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 357 * @param config Flash configuration parameters.
AnnaBridge 171:3a7713b1edbc 358 */
AnnaBridge 171:3a7713b1edbc 359 void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config);
AnnaBridge 171:3a7713b1edbc 360
AnnaBridge 171:3a7713b1edbc 361 /*!
AnnaBridge 171:3a7713b1edbc 362 * @brief Software reset for the QSPI logic.
AnnaBridge 171:3a7713b1edbc 363 *
AnnaBridge 171:3a7713b1edbc 364 * This function sets the software reset flags for both AHB and buffer domain and
AnnaBridge 171:3a7713b1edbc 365 * resets both AHB buffer and also IP FIFOs.
AnnaBridge 171:3a7713b1edbc 366 *
AnnaBridge 171:3a7713b1edbc 367 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 368 */
AnnaBridge 171:3a7713b1edbc 369 void QSPI_SoftwareReset(QuadSPI_Type *base);
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 /*!
AnnaBridge 171:3a7713b1edbc 372 * @brief Enables or disables the QSPI module.
AnnaBridge 171:3a7713b1edbc 373 *
AnnaBridge 171:3a7713b1edbc 374 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 375 * @param enable True means enable QSPI, false means disable.
AnnaBridge 171:3a7713b1edbc 376 */
AnnaBridge 171:3a7713b1edbc 377 static inline void QSPI_Enable(QuadSPI_Type *base, bool enable)
AnnaBridge 171:3a7713b1edbc 378 {
AnnaBridge 171:3a7713b1edbc 379 if (enable)
AnnaBridge 171:3a7713b1edbc 380 {
AnnaBridge 171:3a7713b1edbc 381 base->MCR &= ~QuadSPI_MCR_MDIS_MASK;
AnnaBridge 171:3a7713b1edbc 382 }
AnnaBridge 171:3a7713b1edbc 383 else
AnnaBridge 171:3a7713b1edbc 384 {
AnnaBridge 171:3a7713b1edbc 385 base->MCR |= QuadSPI_MCR_MDIS_MASK;
AnnaBridge 171:3a7713b1edbc 386 }
AnnaBridge 171:3a7713b1edbc 387 }
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 /*! @} */
AnnaBridge 171:3a7713b1edbc 390
AnnaBridge 171:3a7713b1edbc 391 /*!
AnnaBridge 171:3a7713b1edbc 392 * @name Status
AnnaBridge 171:3a7713b1edbc 393 * @{
AnnaBridge 171:3a7713b1edbc 394 */
AnnaBridge 171:3a7713b1edbc 395
AnnaBridge 171:3a7713b1edbc 396 /*!
AnnaBridge 171:3a7713b1edbc 397 * @brief Gets the state value of QSPI.
AnnaBridge 171:3a7713b1edbc 398 *
AnnaBridge 171:3a7713b1edbc 399 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 400 * @return status flag, use status flag to AND #_qspi_flags could get the related status.
AnnaBridge 171:3a7713b1edbc 401 */
AnnaBridge 171:3a7713b1edbc 402 static inline uint32_t QSPI_GetStatusFlags(QuadSPI_Type *base)
AnnaBridge 171:3a7713b1edbc 403 {
AnnaBridge 171:3a7713b1edbc 404 return base->SR;
AnnaBridge 171:3a7713b1edbc 405 }
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /*!
AnnaBridge 171:3a7713b1edbc 408 * @brief Gets QSPI error status flags.
AnnaBridge 171:3a7713b1edbc 409 *
AnnaBridge 171:3a7713b1edbc 410 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 411 * @return status flag, use status flag to AND #_qspi_error_flags could get the related status.
AnnaBridge 171:3a7713b1edbc 412 */
AnnaBridge 171:3a7713b1edbc 413 static inline uint32_t QSPI_GetErrorStatusFlags(QuadSPI_Type *base)
AnnaBridge 171:3a7713b1edbc 414 {
AnnaBridge 171:3a7713b1edbc 415 return base->FR;
AnnaBridge 171:3a7713b1edbc 416 }
AnnaBridge 171:3a7713b1edbc 417
AnnaBridge 171:3a7713b1edbc 418 /*! @brief Clears the QSPI error flags.
AnnaBridge 171:3a7713b1edbc 419 *
AnnaBridge 171:3a7713b1edbc 420 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 421 * @param mask Which kind of QSPI flags to be cleared, a combination of _qspi_error_flags.
AnnaBridge 171:3a7713b1edbc 422 */
AnnaBridge 171:3a7713b1edbc 423 static inline void QSPI_ClearErrorFlag(QuadSPI_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 424 {
AnnaBridge 171:3a7713b1edbc 425 base->FR = mask;
AnnaBridge 171:3a7713b1edbc 426 }
AnnaBridge 171:3a7713b1edbc 427
AnnaBridge 171:3a7713b1edbc 428 /*! @} */
AnnaBridge 171:3a7713b1edbc 429
AnnaBridge 171:3a7713b1edbc 430 /*!
AnnaBridge 171:3a7713b1edbc 431 * @name Interrupts
AnnaBridge 171:3a7713b1edbc 432 * @{
AnnaBridge 171:3a7713b1edbc 433 */
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 /*!
AnnaBridge 171:3a7713b1edbc 436 * @brief Enables the QSPI interrupts.
AnnaBridge 171:3a7713b1edbc 437 *
AnnaBridge 171:3a7713b1edbc 438 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 439 * @param mask QSPI interrupt source.
AnnaBridge 171:3a7713b1edbc 440 */
AnnaBridge 171:3a7713b1edbc 441 static inline void QSPI_EnableInterrupts(QuadSPI_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 442 {
AnnaBridge 171:3a7713b1edbc 443 base->RSER |= mask;
AnnaBridge 171:3a7713b1edbc 444 }
AnnaBridge 171:3a7713b1edbc 445
AnnaBridge 171:3a7713b1edbc 446 /*!
AnnaBridge 171:3a7713b1edbc 447 * @brief Disables the QSPI interrupts.
AnnaBridge 171:3a7713b1edbc 448 *
AnnaBridge 171:3a7713b1edbc 449 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 450 * @param mask QSPI interrupt source.
AnnaBridge 171:3a7713b1edbc 451 */
AnnaBridge 171:3a7713b1edbc 452 static inline void QSPI_DisableInterrupts(QuadSPI_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 453 {
AnnaBridge 171:3a7713b1edbc 454 base->RSER &= ~mask;
AnnaBridge 171:3a7713b1edbc 455 }
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 /*! @} */
AnnaBridge 171:3a7713b1edbc 458
AnnaBridge 171:3a7713b1edbc 459 /*!
AnnaBridge 171:3a7713b1edbc 460 * @name DMA Control
AnnaBridge 171:3a7713b1edbc 461 * @{
AnnaBridge 171:3a7713b1edbc 462 */
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 /*!
AnnaBridge 171:3a7713b1edbc 465 * @brief Enables the QSPI DMA source.
AnnaBridge 171:3a7713b1edbc 466 *
AnnaBridge 171:3a7713b1edbc 467 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 468 * @param mask QSPI DMA source.
AnnaBridge 171:3a7713b1edbc 469 * @param enable True means enable DMA, false means disable.
AnnaBridge 171:3a7713b1edbc 470 */
AnnaBridge 171:3a7713b1edbc 471 static inline void QSPI_EnableDMA(QuadSPI_Type *base, uint32_t mask, bool enable)
AnnaBridge 171:3a7713b1edbc 472 {
AnnaBridge 171:3a7713b1edbc 473 if (enable)
AnnaBridge 171:3a7713b1edbc 474 {
AnnaBridge 171:3a7713b1edbc 475 base->RSER |= mask;
AnnaBridge 171:3a7713b1edbc 476 }
AnnaBridge 171:3a7713b1edbc 477 else
AnnaBridge 171:3a7713b1edbc 478 {
AnnaBridge 171:3a7713b1edbc 479 base->RSER &= ~mask;
AnnaBridge 171:3a7713b1edbc 480 }
AnnaBridge 171:3a7713b1edbc 481 }
AnnaBridge 171:3a7713b1edbc 482
AnnaBridge 171:3a7713b1edbc 483 /*!
AnnaBridge 171:3a7713b1edbc 484 * @brief Gets the Tx data register address. It is used for DMA operation.
AnnaBridge 171:3a7713b1edbc 485 *
AnnaBridge 171:3a7713b1edbc 486 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 487 * @return QSPI Tx data register address.
AnnaBridge 171:3a7713b1edbc 488 */
AnnaBridge 171:3a7713b1edbc 489 static inline uint32_t QSPI_GetTxDataRegisterAddress(QuadSPI_Type *base)
AnnaBridge 171:3a7713b1edbc 490 {
AnnaBridge 171:3a7713b1edbc 491 return (uint32_t)(&base->TBDR);
AnnaBridge 171:3a7713b1edbc 492 }
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 /*!
AnnaBridge 171:3a7713b1edbc 495 * @brief Gets the Rx data register address used for DMA operation.
AnnaBridge 171:3a7713b1edbc 496 *
AnnaBridge 171:3a7713b1edbc 497 * This function returns the Rx data register address or Rx buffer address
AnnaBridge 171:3a7713b1edbc 498 * according to the Rx read area settings.
AnnaBridge 171:3a7713b1edbc 499 *
AnnaBridge 171:3a7713b1edbc 500 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 501 * @return QSPI Rx data register address.
AnnaBridge 171:3a7713b1edbc 502 */
AnnaBridge 171:3a7713b1edbc 503 uint32_t QSPI_GetRxDataRegisterAddress(QuadSPI_Type *base);
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 /* @} */
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507 /*!
AnnaBridge 171:3a7713b1edbc 508 * @name Bus Operations
AnnaBridge 171:3a7713b1edbc 509 * @{
AnnaBridge 171:3a7713b1edbc 510 */
AnnaBridge 171:3a7713b1edbc 511
AnnaBridge 171:3a7713b1edbc 512 /*! @brief Sets the IP command address.
AnnaBridge 171:3a7713b1edbc 513 *
AnnaBridge 171:3a7713b1edbc 514 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 515 * @param addr IP command address.
AnnaBridge 171:3a7713b1edbc 516 */
AnnaBridge 171:3a7713b1edbc 517 static inline void QSPI_SetIPCommandAddress(QuadSPI_Type *base, uint32_t addr)
AnnaBridge 171:3a7713b1edbc 518 {
AnnaBridge 171:3a7713b1edbc 519 base->SFAR = addr;
AnnaBridge 171:3a7713b1edbc 520 }
AnnaBridge 171:3a7713b1edbc 521
AnnaBridge 171:3a7713b1edbc 522 /*! @brief Sets the IP command size.
AnnaBridge 171:3a7713b1edbc 523 *
AnnaBridge 171:3a7713b1edbc 524 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 525 * @param size IP command size.
AnnaBridge 171:3a7713b1edbc 526 */
AnnaBridge 171:3a7713b1edbc 527 static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint16_t size)
AnnaBridge 171:3a7713b1edbc 528 {
AnnaBridge 171:3a7713b1edbc 529 base->IPCR_ACCESSBIT.IDATZ = size;
AnnaBridge 171:3a7713b1edbc 530 }
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 /*! @brief Executes IP commands located in LUT table.
AnnaBridge 171:3a7713b1edbc 533 *
AnnaBridge 171:3a7713b1edbc 534 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 535 * @param index IP command located in which LUT table index.
AnnaBridge 171:3a7713b1edbc 536 */
AnnaBridge 171:3a7713b1edbc 537 void QSPI_ExecuteIPCommand(QuadSPI_Type *base, uint32_t index);
AnnaBridge 171:3a7713b1edbc 538
AnnaBridge 171:3a7713b1edbc 539 /*! @brief Executes AHB commands located in LUT table.
AnnaBridge 171:3a7713b1edbc 540 *
AnnaBridge 171:3a7713b1edbc 541 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 542 * @param index AHB command located in which LUT table index.
AnnaBridge 171:3a7713b1edbc 543 */
AnnaBridge 171:3a7713b1edbc 544 void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index);
AnnaBridge 171:3a7713b1edbc 545
AnnaBridge 171:3a7713b1edbc 546 #if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
AnnaBridge 171:3a7713b1edbc 547 /*! @brief Enables/disables the QSPI IP command parallel mode.
AnnaBridge 171:3a7713b1edbc 548 *
AnnaBridge 171:3a7713b1edbc 549 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 550 * @param enable True means enable parallel mode, false means disable parallel mode.
AnnaBridge 171:3a7713b1edbc 551 */
AnnaBridge 171:3a7713b1edbc 552 static inline void QSPI_EnableIPParallelMode(QuadSPI_Type *base, bool enable)
AnnaBridge 171:3a7713b1edbc 553 {
AnnaBridge 171:3a7713b1edbc 554 if (enable)
AnnaBridge 171:3a7713b1edbc 555 {
AnnaBridge 171:3a7713b1edbc 556 base->IPCR |= QuadSPI_IPCR_PAR_EN_MASK;
AnnaBridge 171:3a7713b1edbc 557 }
AnnaBridge 171:3a7713b1edbc 558 else
AnnaBridge 171:3a7713b1edbc 559 {
AnnaBridge 171:3a7713b1edbc 560 base->IPCR &= ~QuadSPI_IPCR_PAR_EN_MASK;
AnnaBridge 171:3a7713b1edbc 561 }
AnnaBridge 171:3a7713b1edbc 562 }
AnnaBridge 171:3a7713b1edbc 563
AnnaBridge 171:3a7713b1edbc 564 /*! @brief Enables/disables the QSPI AHB command parallel mode.
AnnaBridge 171:3a7713b1edbc 565 *
AnnaBridge 171:3a7713b1edbc 566 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 567 * @param enable True means enable parallel mode, false means disable parallel mode.
AnnaBridge 171:3a7713b1edbc 568 */
AnnaBridge 171:3a7713b1edbc 569 static inline void QSPI_EnableAHBParallelMode(QuadSPI_Type *base, bool enable)
AnnaBridge 171:3a7713b1edbc 570 {
AnnaBridge 171:3a7713b1edbc 571 if (enable)
AnnaBridge 171:3a7713b1edbc 572 {
AnnaBridge 171:3a7713b1edbc 573 base->BFGENCR |= QuadSPI_BFGENCR_PAR_EN_MASK;
AnnaBridge 171:3a7713b1edbc 574 }
AnnaBridge 171:3a7713b1edbc 575 else
AnnaBridge 171:3a7713b1edbc 576 {
AnnaBridge 171:3a7713b1edbc 577 base->BFGENCR &= ~QuadSPI_BFGENCR_PAR_EN_MASK;
AnnaBridge 171:3a7713b1edbc 578 }
AnnaBridge 171:3a7713b1edbc 579 }
AnnaBridge 171:3a7713b1edbc 580 #endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
AnnaBridge 171:3a7713b1edbc 581
AnnaBridge 171:3a7713b1edbc 582 /*! @brief Updates the LUT table.
AnnaBridge 171:3a7713b1edbc 583 *
AnnaBridge 171:3a7713b1edbc 584 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 585 * @param index Which LUT index needs to be located. It should be an integer divided by 4.
AnnaBridge 171:3a7713b1edbc 586 * @param cmd Command sequence array.
AnnaBridge 171:3a7713b1edbc 587 */
AnnaBridge 171:3a7713b1edbc 588 void QSPI_UpdateLUT(QuadSPI_Type *base, uint32_t index, uint32_t *cmd);
AnnaBridge 171:3a7713b1edbc 589
AnnaBridge 171:3a7713b1edbc 590 /*! @brief Clears the QSPI FIFO logic.
AnnaBridge 171:3a7713b1edbc 591 *
AnnaBridge 171:3a7713b1edbc 592 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 593 * @param mask Which kind of QSPI FIFO to be cleared.
AnnaBridge 171:3a7713b1edbc 594 */
AnnaBridge 171:3a7713b1edbc 595 static inline void QSPI_ClearFifo(QuadSPI_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 596 {
AnnaBridge 171:3a7713b1edbc 597 base->MCR |= mask;
AnnaBridge 171:3a7713b1edbc 598 }
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600 /*!@ brief Clears the command sequence for the IP/buffer command.
AnnaBridge 171:3a7713b1edbc 601 *
AnnaBridge 171:3a7713b1edbc 602 * This function can reset the command sequence.
AnnaBridge 171:3a7713b1edbc 603 * @param base QSPI base address.
AnnaBridge 171:3a7713b1edbc 604 * @param seq Which command sequence need to reset, IP command, buffer command or both.
AnnaBridge 171:3a7713b1edbc 605 */
AnnaBridge 171:3a7713b1edbc 606 static inline void QSPI_ClearCommandSequence(QuadSPI_Type *base, qspi_command_seq_t seq)
AnnaBridge 171:3a7713b1edbc 607 {
AnnaBridge 171:3a7713b1edbc 608 base->SPTRCLR = seq;
AnnaBridge 171:3a7713b1edbc 609 }
AnnaBridge 171:3a7713b1edbc 610
AnnaBridge 171:3a7713b1edbc 611 /*!
AnnaBridge 171:3a7713b1edbc 612 * @brief Enable or disable DDR mode.
AnnaBridge 171:3a7713b1edbc 613 *
AnnaBridge 171:3a7713b1edbc 614 * @param base QSPI base pointer
AnnaBridge 171:3a7713b1edbc 615 * @param eanble True means enable DDR mode, false means disable DDR mode.
AnnaBridge 171:3a7713b1edbc 616 */
AnnaBridge 171:3a7713b1edbc 617 static inline void QSPI_EnableDDRMode(QuadSPI_Type *base, bool enable)
AnnaBridge 171:3a7713b1edbc 618 {
AnnaBridge 171:3a7713b1edbc 619 if (enable)
AnnaBridge 171:3a7713b1edbc 620 {
AnnaBridge 171:3a7713b1edbc 621 base->MCR |= QuadSPI_MCR_DDR_EN_MASK;
AnnaBridge 171:3a7713b1edbc 622 }
AnnaBridge 171:3a7713b1edbc 623 else
AnnaBridge 171:3a7713b1edbc 624 {
AnnaBridge 171:3a7713b1edbc 625 base->MCR &= ~QuadSPI_MCR_DDR_EN_MASK;
AnnaBridge 171:3a7713b1edbc 626 }
AnnaBridge 171:3a7713b1edbc 627 }
AnnaBridge 171:3a7713b1edbc 628
AnnaBridge 171:3a7713b1edbc 629 /*!@ brief Set the RX buffer readout area.
AnnaBridge 171:3a7713b1edbc 630 *
AnnaBridge 171:3a7713b1edbc 631 * This function can set the RX buffer readout, from AHB bus or IP Bus.
AnnaBridge 171:3a7713b1edbc 632 * @param base QSPI base address.
AnnaBridge 171:3a7713b1edbc 633 * @param area QSPI Rx buffer readout area. AHB bus buffer or IP bus buffer.
AnnaBridge 171:3a7713b1edbc 634 */
AnnaBridge 171:3a7713b1edbc 635 void QSPI_SetReadDataArea(QuadSPI_Type *base, qspi_read_area_t area);
AnnaBridge 171:3a7713b1edbc 636
AnnaBridge 171:3a7713b1edbc 637 /*!
AnnaBridge 171:3a7713b1edbc 638 * @brief Sends a buffer of data bytes using a blocking method.
AnnaBridge 171:3a7713b1edbc 639 * @note This function blocks via polling until all bytes have been sent.
AnnaBridge 171:3a7713b1edbc 640 * @param base QSPI base pointer
AnnaBridge 171:3a7713b1edbc 641 * @param buffer The data bytes to send
AnnaBridge 171:3a7713b1edbc 642 * @param size The number of data bytes to send
AnnaBridge 171:3a7713b1edbc 643 */
AnnaBridge 171:3a7713b1edbc 644 void QSPI_WriteBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size);
AnnaBridge 171:3a7713b1edbc 645
AnnaBridge 171:3a7713b1edbc 646 /*!
AnnaBridge 171:3a7713b1edbc 647 * @brief Writes data into FIFO.
AnnaBridge 171:3a7713b1edbc 648 *
AnnaBridge 171:3a7713b1edbc 649 * @param base QSPI base pointer
AnnaBridge 171:3a7713b1edbc 650 * @param data The data bytes to send
AnnaBridge 171:3a7713b1edbc 651 */
AnnaBridge 171:3a7713b1edbc 652 static inline void QSPI_WriteData(QuadSPI_Type *base, uint32_t data)
AnnaBridge 171:3a7713b1edbc 653 {
AnnaBridge 171:3a7713b1edbc 654 base->TBDR = data;
AnnaBridge 171:3a7713b1edbc 655 }
AnnaBridge 171:3a7713b1edbc 656
AnnaBridge 171:3a7713b1edbc 657 /*!
AnnaBridge 171:3a7713b1edbc 658 * @brief Receives a buffer of data bytes using a blocking method.
AnnaBridge 171:3a7713b1edbc 659 * @note This function blocks via polling until all bytes have been sent. Users shall notice that
AnnaBridge 171:3a7713b1edbc 660 * this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
AnnaBridge 171:3a7713b1edbc 661 * For flash contents read, please use AHB bus read, this is much more efficiency.
AnnaBridge 171:3a7713b1edbc 662 *
AnnaBridge 171:3a7713b1edbc 663 * @param base QSPI base pointer
AnnaBridge 171:3a7713b1edbc 664 * @param buffer The data bytes to send
AnnaBridge 171:3a7713b1edbc 665 * @param size The number of data bytes to receive
AnnaBridge 171:3a7713b1edbc 666 */
AnnaBridge 171:3a7713b1edbc 667 void QSPI_ReadBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size);
AnnaBridge 171:3a7713b1edbc 668
AnnaBridge 171:3a7713b1edbc 669 /*!
AnnaBridge 171:3a7713b1edbc 670 * @brief Receives data from data FIFO.
AnnaBridge 171:3a7713b1edbc 671 *
AnnaBridge 171:3a7713b1edbc 672 * @param base QSPI base pointer
AnnaBridge 171:3a7713b1edbc 673 * @return The data in the FIFO.
AnnaBridge 171:3a7713b1edbc 674 */
AnnaBridge 171:3a7713b1edbc 675 uint32_t QSPI_ReadData(QuadSPI_Type *base);
AnnaBridge 171:3a7713b1edbc 676
AnnaBridge 171:3a7713b1edbc 677 /*! @} */
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679 /*!
AnnaBridge 171:3a7713b1edbc 680 * @name Transactional
AnnaBridge 171:3a7713b1edbc 681 * @{
AnnaBridge 171:3a7713b1edbc 682 */
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684 /*!
AnnaBridge 171:3a7713b1edbc 685 * @brief Writes data to the QSPI transmit buffer.
AnnaBridge 171:3a7713b1edbc 686 *
AnnaBridge 171:3a7713b1edbc 687 * This function writes a continuous data to the QSPI transmit FIFO. This function is a block function
AnnaBridge 171:3a7713b1edbc 688 * and can return only when finished. This function uses polling methods.
AnnaBridge 171:3a7713b1edbc 689 *
AnnaBridge 171:3a7713b1edbc 690 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 691 * @param xfer QSPI transfer structure.
AnnaBridge 171:3a7713b1edbc 692 */
AnnaBridge 171:3a7713b1edbc 693 static inline void QSPI_TransferSendBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)
AnnaBridge 171:3a7713b1edbc 694 {
AnnaBridge 171:3a7713b1edbc 695 QSPI_WriteBlocking(base, xfer->data, xfer->dataSize);
AnnaBridge 171:3a7713b1edbc 696 }
AnnaBridge 171:3a7713b1edbc 697
AnnaBridge 171:3a7713b1edbc 698 /*!
AnnaBridge 171:3a7713b1edbc 699 * @brief Reads data from the QSPI receive buffer in polling way.
AnnaBridge 171:3a7713b1edbc 700 *
AnnaBridge 171:3a7713b1edbc 701 * This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking
AnnaBridge 171:3a7713b1edbc 702 * function and can return only when finished. This function uses polling methods. Users shall notice that
AnnaBridge 171:3a7713b1edbc 703 * this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
AnnaBridge 171:3a7713b1edbc 704 * For flash contents read, please use AHB bus read, this is much more efficiency.
AnnaBridge 171:3a7713b1edbc 705 *
AnnaBridge 171:3a7713b1edbc 706 * @param base Pointer to QuadSPI Type.
AnnaBridge 171:3a7713b1edbc 707 * @param xfer QSPI transfer structure.
AnnaBridge 171:3a7713b1edbc 708 */
AnnaBridge 171:3a7713b1edbc 709 static inline void QSPI_TransferReceiveBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)
AnnaBridge 171:3a7713b1edbc 710 {
AnnaBridge 171:3a7713b1edbc 711 QSPI_ReadBlocking(base, xfer->data, xfer->dataSize);
AnnaBridge 171:3a7713b1edbc 712 }
AnnaBridge 171:3a7713b1edbc 713
AnnaBridge 171:3a7713b1edbc 714 /*! @} */
AnnaBridge 171:3a7713b1edbc 715
AnnaBridge 171:3a7713b1edbc 716 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 717 }
AnnaBridge 171:3a7713b1edbc 718 #endif
AnnaBridge 171:3a7713b1edbc 719
AnnaBridge 171:3a7713b1edbc 720 /* @}*/
AnnaBridge 171:3a7713b1edbc 721
AnnaBridge 171:3a7713b1edbc 722 #endif /* _FSL_QSPI_H_*/