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TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 3 ** Processors: MKL46Z256VLH4
AnnaBridge 171:3a7713b1edbc 4 ** MKL46Z128VLH4
AnnaBridge 171:3a7713b1edbc 5 ** MKL46Z256VLL4
AnnaBridge 171:3a7713b1edbc 6 ** MKL46Z128VLL4
AnnaBridge 171:3a7713b1edbc 7 ** MKL46Z256VMC4
AnnaBridge 171:3a7713b1edbc 8 ** MKL46Z128VMC4
AnnaBridge 171:3a7713b1edbc 9 **
AnnaBridge 171:3a7713b1edbc 10 ** Compilers: ARM Compiler
AnnaBridge 171:3a7713b1edbc 11 ** Freescale C/C++ for Embedded ARM
AnnaBridge 171:3a7713b1edbc 12 ** GNU C Compiler
AnnaBridge 171:3a7713b1edbc 13 ** IAR ANSI C/C++ Compiler for ARM
AnnaBridge 171:3a7713b1edbc 14 **
AnnaBridge 171:3a7713b1edbc 15 ** Reference manual: KL46P121M48SF4RM, Rev.2, Dec 2012
AnnaBridge 171:3a7713b1edbc 16 ** Version: rev. 2.2, 2013-04-12
AnnaBridge 171:3a7713b1edbc 17 **
AnnaBridge 171:3a7713b1edbc 18 ** Abstract:
AnnaBridge 171:3a7713b1edbc 19 ** CMSIS Peripheral Access Layer for MKL46Z4
AnnaBridge 171:3a7713b1edbc 20 **
AnnaBridge 171:3a7713b1edbc 21 ** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 22 **
AnnaBridge 171:3a7713b1edbc 23 ** http: www.freescale.com
AnnaBridge 171:3a7713b1edbc 24 ** mail: support@freescale.com
AnnaBridge 171:3a7713b1edbc 25 **
AnnaBridge 171:3a7713b1edbc 26 ** Revisions:
AnnaBridge 171:3a7713b1edbc 27 ** - rev. 1.0 (2012-10-16)
AnnaBridge 171:3a7713b1edbc 28 ** Initial version.
AnnaBridge 171:3a7713b1edbc 29 ** - rev. 2.0 (2012-12-12)
AnnaBridge 171:3a7713b1edbc 30 ** Update to reference manual rev. 1.
AnnaBridge 171:3a7713b1edbc 31 ** - rev. 2.1 (2013-04-05)
AnnaBridge 171:3a7713b1edbc 32 ** Changed start of doxygen comment.
AnnaBridge 171:3a7713b1edbc 33 ** - rev. 2.2 (2013-04-12)
AnnaBridge 171:3a7713b1edbc 34 ** SystemInit function fixed for clock configuration 1.
AnnaBridge 171:3a7713b1edbc 35 ** Name of the interrupt num. 31 updated to reflect proper function.
AnnaBridge 171:3a7713b1edbc 36 **
AnnaBridge 171:3a7713b1edbc 37 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 38 */
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /*!
AnnaBridge 171:3a7713b1edbc 41 * @file MKL46Z4.h
AnnaBridge 171:3a7713b1edbc 42 * @version 2.2
AnnaBridge 171:3a7713b1edbc 43 * @date 2013-04-12
AnnaBridge 171:3a7713b1edbc 44 * @brief CMSIS Peripheral Access Layer for MKL46Z4
AnnaBridge 171:3a7713b1edbc 45 *
AnnaBridge 171:3a7713b1edbc 46 * CMSIS Peripheral Access Layer for MKL46Z4
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 #if !defined(MKL46Z4_H_)
AnnaBridge 171:3a7713b1edbc 50 #define MKL46Z4_H_ /**< Symbol preventing repeated inclusion */
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 /** Memory map major version (memory maps with equal major version number are
AnnaBridge 171:3a7713b1edbc 53 * compatible) */
AnnaBridge 171:3a7713b1edbc 54 #define MCU_MEM_MAP_VERSION 0x0200u
AnnaBridge 171:3a7713b1edbc 55 /** Memory map minor version */
AnnaBridge 171:3a7713b1edbc 56 #define MCU_MEM_MAP_VERSION_MINOR 0x0002u
AnnaBridge 171:3a7713b1edbc 57
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 60 -- Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 61 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 /*!
AnnaBridge 171:3a7713b1edbc 64 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 65 * @{
AnnaBridge 171:3a7713b1edbc 66 */
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 /** Interrupt Number Definitions */
AnnaBridge 171:3a7713b1edbc 69 typedef enum IRQn {
AnnaBridge 171:3a7713b1edbc 70 /* Core interrupts */
AnnaBridge 171:3a7713b1edbc 71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 72 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 73 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 74 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 75 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 /* Device specific interrupts */
AnnaBridge 171:3a7713b1edbc 78 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
AnnaBridge 171:3a7713b1edbc 79 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
AnnaBridge 171:3a7713b1edbc 80 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
AnnaBridge 171:3a7713b1edbc 81 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
AnnaBridge 171:3a7713b1edbc 82 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
AnnaBridge 171:3a7713b1edbc 83 FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
AnnaBridge 171:3a7713b1edbc 84 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
AnnaBridge 171:3a7713b1edbc 85 LLW_IRQn = 7, /**< Low Leakage Wakeup */
AnnaBridge 171:3a7713b1edbc 86 I2C0_IRQn = 8, /**< I2C0 interrupt */
AnnaBridge 171:3a7713b1edbc 87 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
AnnaBridge 171:3a7713b1edbc 88 SPI0_IRQn = 10, /**< SPI0 interrupt */
AnnaBridge 171:3a7713b1edbc 89 SPI1_IRQn = 11, /**< SPI1 interrupt */
AnnaBridge 171:3a7713b1edbc 90 UART0_IRQn = 12, /**< UART0 status/error interrupt */
AnnaBridge 171:3a7713b1edbc 91 UART1_IRQn = 13, /**< UART1 status/error interrupt */
AnnaBridge 171:3a7713b1edbc 92 UART2_IRQn = 14, /**< UART2 status/error interrupt */
AnnaBridge 171:3a7713b1edbc 93 ADC0_IRQn = 15, /**< ADC0 interrupt */
AnnaBridge 171:3a7713b1edbc 94 CMP0_IRQn = 16, /**< CMP0 interrupt */
AnnaBridge 171:3a7713b1edbc 95 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 96 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 97 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 98 RTC_IRQn = 20, /**< RTC interrupt */
AnnaBridge 171:3a7713b1edbc 99 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
AnnaBridge 171:3a7713b1edbc 100 PIT_IRQn = 22, /**< PIT timer interrupt */
AnnaBridge 171:3a7713b1edbc 101 I2S0_IRQn = 23, /**< I2S0 transmit interrupt */
AnnaBridge 171:3a7713b1edbc 102 USB0_IRQn = 24, /**< USB0 interrupt */
AnnaBridge 171:3a7713b1edbc 103 DAC0_IRQn = 25, /**< DAC0 interrupt */
AnnaBridge 171:3a7713b1edbc 104 TSI0_IRQn = 26, /**< TSI0 interrupt */
AnnaBridge 171:3a7713b1edbc 105 MCG_IRQn = 27, /**< MCG interrupt */
AnnaBridge 171:3a7713b1edbc 106 LPTimer_IRQn = 28, /**< LPTimer interrupt */
AnnaBridge 171:3a7713b1edbc 107 LCD_IRQn = 29, /**< Segment LCD Interrupt */
AnnaBridge 171:3a7713b1edbc 108 PORTA_IRQn = 30, /**< Port A interrupt */
AnnaBridge 171:3a7713b1edbc 109 PORTC_PORTD_IRQn = 31 /**< Port C and port D interrupt */
AnnaBridge 171:3a7713b1edbc 110 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 /*!
AnnaBridge 171:3a7713b1edbc 113 * @}
AnnaBridge 171:3a7713b1edbc 114 */ /* end of group Interrupt_vector_numbers */
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 118 -- Cortex M0 Core Configuration
AnnaBridge 171:3a7713b1edbc 119 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 /*!
AnnaBridge 171:3a7713b1edbc 122 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
AnnaBridge 171:3a7713b1edbc 123 * @{
AnnaBridge 171:3a7713b1edbc 124 */
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
AnnaBridge 171:3a7713b1edbc 127 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
AnnaBridge 171:3a7713b1edbc 128 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
AnnaBridge 171:3a7713b1edbc 129 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
AnnaBridge 171:3a7713b1edbc 130 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
AnnaBridge 171:3a7713b1edbc 133 #include "system_MKL46Z4.h" /* Device specific configuration file */
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 /*!
AnnaBridge 171:3a7713b1edbc 136 * @}
AnnaBridge 171:3a7713b1edbc 137 */ /* end of group Cortex_Core_Configuration */
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 141 -- Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 142 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 143
AnnaBridge 171:3a7713b1edbc 144 /*!
AnnaBridge 171:3a7713b1edbc 145 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 146 * @{
AnnaBridge 171:3a7713b1edbc 147 */
AnnaBridge 171:3a7713b1edbc 148
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 /*
AnnaBridge 171:3a7713b1edbc 151 ** Start of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 152 */
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 155 #pragma push
AnnaBridge 171:3a7713b1edbc 156 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 157 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 158 #pragma push
AnnaBridge 171:3a7713b1edbc 159 #pragma cpp_extensions on
AnnaBridge 171:3a7713b1edbc 160 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 161 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 162 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 163 #pragma language=extended
AnnaBridge 171:3a7713b1edbc 164 #else
AnnaBridge 171:3a7713b1edbc 165 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 166 #endif
AnnaBridge 171:3a7713b1edbc 167
AnnaBridge 171:3a7713b1edbc 168 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 169 -- ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 170 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 /*!
AnnaBridge 171:3a7713b1edbc 173 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 174 * @{
AnnaBridge 171:3a7713b1edbc 175 */
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 /** ADC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 178 typedef struct {
AnnaBridge 171:3a7713b1edbc 179 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 180 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 181 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 182 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 183 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 184 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 185 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 186 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 187 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 188 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 189 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 190 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 191 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 192 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 193 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 194 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 195 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 196 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 197 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 198 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 199 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 200 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 201 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 202 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 203 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 204 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 205 } ADC_Type;
AnnaBridge 171:3a7713b1edbc 206
AnnaBridge 171:3a7713b1edbc 207 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 208 -- ADC Register Masks
AnnaBridge 171:3a7713b1edbc 209 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 210
AnnaBridge 171:3a7713b1edbc 211 /*!
AnnaBridge 171:3a7713b1edbc 212 * @addtogroup ADC_Register_Masks ADC Register Masks
AnnaBridge 171:3a7713b1edbc 213 * @{
AnnaBridge 171:3a7713b1edbc 214 */
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /* SC1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 217 #define ADC_SC1_ADCH_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 218 #define ADC_SC1_ADCH_SHIFT 0
AnnaBridge 171:3a7713b1edbc 219 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
AnnaBridge 171:3a7713b1edbc 220 #define ADC_SC1_DIFF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 221 #define ADC_SC1_DIFF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 222 #define ADC_SC1_AIEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 223 #define ADC_SC1_AIEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 224 #define ADC_SC1_COCO_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 225 #define ADC_SC1_COCO_SHIFT 7
AnnaBridge 171:3a7713b1edbc 226 /* CFG1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 227 #define ADC_CFG1_ADICLK_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 228 #define ADC_CFG1_ADICLK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 229 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
AnnaBridge 171:3a7713b1edbc 230 #define ADC_CFG1_MODE_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 231 #define ADC_CFG1_MODE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 232 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 233 #define ADC_CFG1_ADLSMP_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 234 #define ADC_CFG1_ADLSMP_SHIFT 4
AnnaBridge 171:3a7713b1edbc 235 #define ADC_CFG1_ADIV_MASK 0x60u
AnnaBridge 171:3a7713b1edbc 236 #define ADC_CFG1_ADIV_SHIFT 5
AnnaBridge 171:3a7713b1edbc 237 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
AnnaBridge 171:3a7713b1edbc 238 #define ADC_CFG1_ADLPC_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 239 #define ADC_CFG1_ADLPC_SHIFT 7
AnnaBridge 171:3a7713b1edbc 240 /* CFG2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 241 #define ADC_CFG2_ADLSTS_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 242 #define ADC_CFG2_ADLSTS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 243 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
AnnaBridge 171:3a7713b1edbc 244 #define ADC_CFG2_ADHSC_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 245 #define ADC_CFG2_ADHSC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 246 #define ADC_CFG2_ADACKEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 247 #define ADC_CFG2_ADACKEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 248 #define ADC_CFG2_MUXSEL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 249 #define ADC_CFG2_MUXSEL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 250 /* R Bit Fields */
AnnaBridge 171:3a7713b1edbc 251 #define ADC_R_D_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 252 #define ADC_R_D_SHIFT 0
AnnaBridge 171:3a7713b1edbc 253 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
AnnaBridge 171:3a7713b1edbc 254 /* CV1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 255 #define ADC_CV1_CV_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 256 #define ADC_CV1_CV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 257 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
AnnaBridge 171:3a7713b1edbc 258 /* CV2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 259 #define ADC_CV2_CV_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 260 #define ADC_CV2_CV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 261 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
AnnaBridge 171:3a7713b1edbc 262 /* SC2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 263 #define ADC_SC2_REFSEL_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 264 #define ADC_SC2_REFSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 265 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
AnnaBridge 171:3a7713b1edbc 266 #define ADC_SC2_DMAEN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 267 #define ADC_SC2_DMAEN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 268 #define ADC_SC2_ACREN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 269 #define ADC_SC2_ACREN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 270 #define ADC_SC2_ACFGT_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 271 #define ADC_SC2_ACFGT_SHIFT 4
AnnaBridge 171:3a7713b1edbc 272 #define ADC_SC2_ACFE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 273 #define ADC_SC2_ACFE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 274 #define ADC_SC2_ADTRG_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 275 #define ADC_SC2_ADTRG_SHIFT 6
AnnaBridge 171:3a7713b1edbc 276 #define ADC_SC2_ADACT_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 277 #define ADC_SC2_ADACT_SHIFT 7
AnnaBridge 171:3a7713b1edbc 278 /* SC3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 279 #define ADC_SC3_AVGS_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 280 #define ADC_SC3_AVGS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 281 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
AnnaBridge 171:3a7713b1edbc 282 #define ADC_SC3_AVGE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 283 #define ADC_SC3_AVGE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 284 #define ADC_SC3_ADCO_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 285 #define ADC_SC3_ADCO_SHIFT 3
AnnaBridge 171:3a7713b1edbc 286 #define ADC_SC3_CALF_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 287 #define ADC_SC3_CALF_SHIFT 6
AnnaBridge 171:3a7713b1edbc 288 #define ADC_SC3_CAL_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 289 #define ADC_SC3_CAL_SHIFT 7
AnnaBridge 171:3a7713b1edbc 290 /* OFS Bit Fields */
AnnaBridge 171:3a7713b1edbc 291 #define ADC_OFS_OFS_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 292 #define ADC_OFS_OFS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 293 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
AnnaBridge 171:3a7713b1edbc 294 /* PG Bit Fields */
AnnaBridge 171:3a7713b1edbc 295 #define ADC_PG_PG_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 296 #define ADC_PG_PG_SHIFT 0
AnnaBridge 171:3a7713b1edbc 297 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
AnnaBridge 171:3a7713b1edbc 298 /* MG Bit Fields */
AnnaBridge 171:3a7713b1edbc 299 #define ADC_MG_MG_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 300 #define ADC_MG_MG_SHIFT 0
AnnaBridge 171:3a7713b1edbc 301 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
AnnaBridge 171:3a7713b1edbc 302 /* CLPD Bit Fields */
AnnaBridge 171:3a7713b1edbc 303 #define ADC_CLPD_CLPD_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 304 #define ADC_CLPD_CLPD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 305 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
AnnaBridge 171:3a7713b1edbc 306 /* CLPS Bit Fields */
AnnaBridge 171:3a7713b1edbc 307 #define ADC_CLPS_CLPS_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 308 #define ADC_CLPS_CLPS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 309 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
AnnaBridge 171:3a7713b1edbc 310 /* CLP4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 311 #define ADC_CLP4_CLP4_MASK 0x3FFu
AnnaBridge 171:3a7713b1edbc 312 #define ADC_CLP4_CLP4_SHIFT 0
AnnaBridge 171:3a7713b1edbc 313 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
AnnaBridge 171:3a7713b1edbc 314 /* CLP3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 315 #define ADC_CLP3_CLP3_MASK 0x1FFu
AnnaBridge 171:3a7713b1edbc 316 #define ADC_CLP3_CLP3_SHIFT 0
AnnaBridge 171:3a7713b1edbc 317 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
AnnaBridge 171:3a7713b1edbc 318 /* CLP2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 319 #define ADC_CLP2_CLP2_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 320 #define ADC_CLP2_CLP2_SHIFT 0
AnnaBridge 171:3a7713b1edbc 321 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
AnnaBridge 171:3a7713b1edbc 322 /* CLP1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 323 #define ADC_CLP1_CLP1_MASK 0x7Fu
AnnaBridge 171:3a7713b1edbc 324 #define ADC_CLP1_CLP1_SHIFT 0
AnnaBridge 171:3a7713b1edbc 325 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
AnnaBridge 171:3a7713b1edbc 326 /* CLP0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 327 #define ADC_CLP0_CLP0_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 328 #define ADC_CLP0_CLP0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 329 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
AnnaBridge 171:3a7713b1edbc 330 /* CLMD Bit Fields */
AnnaBridge 171:3a7713b1edbc 331 #define ADC_CLMD_CLMD_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 332 #define ADC_CLMD_CLMD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 333 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
AnnaBridge 171:3a7713b1edbc 334 /* CLMS Bit Fields */
AnnaBridge 171:3a7713b1edbc 335 #define ADC_CLMS_CLMS_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 336 #define ADC_CLMS_CLMS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 337 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
AnnaBridge 171:3a7713b1edbc 338 /* CLM4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 339 #define ADC_CLM4_CLM4_MASK 0x3FFu
AnnaBridge 171:3a7713b1edbc 340 #define ADC_CLM4_CLM4_SHIFT 0
AnnaBridge 171:3a7713b1edbc 341 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
AnnaBridge 171:3a7713b1edbc 342 /* CLM3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 343 #define ADC_CLM3_CLM3_MASK 0x1FFu
AnnaBridge 171:3a7713b1edbc 344 #define ADC_CLM3_CLM3_SHIFT 0
AnnaBridge 171:3a7713b1edbc 345 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
AnnaBridge 171:3a7713b1edbc 346 /* CLM2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 347 #define ADC_CLM2_CLM2_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 348 #define ADC_CLM2_CLM2_SHIFT 0
AnnaBridge 171:3a7713b1edbc 349 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
AnnaBridge 171:3a7713b1edbc 350 /* CLM1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 351 #define ADC_CLM1_CLM1_MASK 0x7Fu
AnnaBridge 171:3a7713b1edbc 352 #define ADC_CLM1_CLM1_SHIFT 0
AnnaBridge 171:3a7713b1edbc 353 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
AnnaBridge 171:3a7713b1edbc 354 /* CLM0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 355 #define ADC_CLM0_CLM0_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 356 #define ADC_CLM0_CLM0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 357 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 /*!
AnnaBridge 171:3a7713b1edbc 360 * @}
AnnaBridge 171:3a7713b1edbc 361 */ /* end of group ADC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363
AnnaBridge 171:3a7713b1edbc 364 /* ADC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 365 /** Peripheral ADC0 base address */
AnnaBridge 171:3a7713b1edbc 366 #define ADC0_BASE (0x4003B000u)
AnnaBridge 171:3a7713b1edbc 367 /** Peripheral ADC0 base pointer */
AnnaBridge 171:3a7713b1edbc 368 #define ADC0 ((ADC_Type *)ADC0_BASE)
AnnaBridge 171:3a7713b1edbc 369 /** Array initializer of ADC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 370 #define ADC_BASES { ADC0 }
AnnaBridge 171:3a7713b1edbc 371
AnnaBridge 171:3a7713b1edbc 372 /*!
AnnaBridge 171:3a7713b1edbc 373 * @}
AnnaBridge 171:3a7713b1edbc 374 */ /* end of group ADC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 375
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 378 -- CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 379 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 380
AnnaBridge 171:3a7713b1edbc 381 /*!
AnnaBridge 171:3a7713b1edbc 382 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 383 * @{
AnnaBridge 171:3a7713b1edbc 384 */
AnnaBridge 171:3a7713b1edbc 385
AnnaBridge 171:3a7713b1edbc 386 /** CMP - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 387 typedef struct {
AnnaBridge 171:3a7713b1edbc 388 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 389 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 390 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 391 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 392 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 393 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 394 } CMP_Type;
AnnaBridge 171:3a7713b1edbc 395
AnnaBridge 171:3a7713b1edbc 396 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 397 -- CMP Register Masks
AnnaBridge 171:3a7713b1edbc 398 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 399
AnnaBridge 171:3a7713b1edbc 400 /*!
AnnaBridge 171:3a7713b1edbc 401 * @addtogroup CMP_Register_Masks CMP Register Masks
AnnaBridge 171:3a7713b1edbc 402 * @{
AnnaBridge 171:3a7713b1edbc 403 */
AnnaBridge 171:3a7713b1edbc 404
AnnaBridge 171:3a7713b1edbc 405 /* CR0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 406 #define CMP_CR0_HYSTCTR_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 407 #define CMP_CR0_HYSTCTR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 408 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
AnnaBridge 171:3a7713b1edbc 409 #define CMP_CR0_FILTER_CNT_MASK 0x70u
AnnaBridge 171:3a7713b1edbc 410 #define CMP_CR0_FILTER_CNT_SHIFT 4
AnnaBridge 171:3a7713b1edbc 411 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 412 /* CR1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 413 #define CMP_CR1_EN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 414 #define CMP_CR1_EN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 415 #define CMP_CR1_OPE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 416 #define CMP_CR1_OPE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 417 #define CMP_CR1_COS_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 418 #define CMP_CR1_COS_SHIFT 2
AnnaBridge 171:3a7713b1edbc 419 #define CMP_CR1_INV_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 420 #define CMP_CR1_INV_SHIFT 3
AnnaBridge 171:3a7713b1edbc 421 #define CMP_CR1_PMODE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 422 #define CMP_CR1_PMODE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 423 #define CMP_CR1_TRIGM_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 424 #define CMP_CR1_TRIGM_SHIFT 5
AnnaBridge 171:3a7713b1edbc 425 #define CMP_CR1_WE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 426 #define CMP_CR1_WE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 427 #define CMP_CR1_SE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 428 #define CMP_CR1_SE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 429 /* FPR Bit Fields */
AnnaBridge 171:3a7713b1edbc 430 #define CMP_FPR_FILT_PER_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 431 #define CMP_FPR_FILT_PER_SHIFT 0
AnnaBridge 171:3a7713b1edbc 432 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
AnnaBridge 171:3a7713b1edbc 433 /* SCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 434 #define CMP_SCR_COUT_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 435 #define CMP_SCR_COUT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 436 #define CMP_SCR_CFF_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 437 #define CMP_SCR_CFF_SHIFT 1
AnnaBridge 171:3a7713b1edbc 438 #define CMP_SCR_CFR_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 439 #define CMP_SCR_CFR_SHIFT 2
AnnaBridge 171:3a7713b1edbc 440 #define CMP_SCR_IEF_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 441 #define CMP_SCR_IEF_SHIFT 3
AnnaBridge 171:3a7713b1edbc 442 #define CMP_SCR_IER_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 443 #define CMP_SCR_IER_SHIFT 4
AnnaBridge 171:3a7713b1edbc 444 #define CMP_SCR_DMAEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 445 #define CMP_SCR_DMAEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 446 /* DACCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 447 #define CMP_DACCR_VOSEL_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 448 #define CMP_DACCR_VOSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 449 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
AnnaBridge 171:3a7713b1edbc 450 #define CMP_DACCR_VRSEL_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 451 #define CMP_DACCR_VRSEL_SHIFT 6
AnnaBridge 171:3a7713b1edbc 452 #define CMP_DACCR_DACEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 453 #define CMP_DACCR_DACEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 454 /* MUXCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 455 #define CMP_MUXCR_MSEL_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 456 #define CMP_MUXCR_MSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 457 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 458 #define CMP_MUXCR_PSEL_MASK 0x38u
AnnaBridge 171:3a7713b1edbc 459 #define CMP_MUXCR_PSEL_SHIFT 3
AnnaBridge 171:3a7713b1edbc 460 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
AnnaBridge 171:3a7713b1edbc 461 #define CMP_MUXCR_PSTM_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 462 #define CMP_MUXCR_PSTM_SHIFT 7
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 /*!
AnnaBridge 171:3a7713b1edbc 465 * @}
AnnaBridge 171:3a7713b1edbc 466 */ /* end of group CMP_Register_Masks */
AnnaBridge 171:3a7713b1edbc 467
AnnaBridge 171:3a7713b1edbc 468
AnnaBridge 171:3a7713b1edbc 469 /* CMP - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 470 /** Peripheral CMP0 base address */
AnnaBridge 171:3a7713b1edbc 471 #define CMP0_BASE (0x40073000u)
AnnaBridge 171:3a7713b1edbc 472 /** Peripheral CMP0 base pointer */
AnnaBridge 171:3a7713b1edbc 473 #define CMP0 ((CMP_Type *)CMP0_BASE)
AnnaBridge 171:3a7713b1edbc 474 /** Array initializer of CMP peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 475 #define CMP_BASES { CMP0 }
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 /*!
AnnaBridge 171:3a7713b1edbc 478 * @}
AnnaBridge 171:3a7713b1edbc 479 */ /* end of group CMP_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 480
AnnaBridge 171:3a7713b1edbc 481
AnnaBridge 171:3a7713b1edbc 482 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 483 -- DAC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 484 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 485
AnnaBridge 171:3a7713b1edbc 486 /*!
AnnaBridge 171:3a7713b1edbc 487 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 488 * @{
AnnaBridge 171:3a7713b1edbc 489 */
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 /** DAC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 492 typedef struct {
AnnaBridge 171:3a7713b1edbc 493 struct { /* offset: 0x0, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 494 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 495 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 496 } DAT[2];
AnnaBridge 171:3a7713b1edbc 497 uint8_t RESERVED_0[28];
AnnaBridge 171:3a7713b1edbc 498 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 499 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
AnnaBridge 171:3a7713b1edbc 500 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
AnnaBridge 171:3a7713b1edbc 501 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
AnnaBridge 171:3a7713b1edbc 502 } DAC_Type;
AnnaBridge 171:3a7713b1edbc 503
AnnaBridge 171:3a7713b1edbc 504 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 505 -- DAC Register Masks
AnnaBridge 171:3a7713b1edbc 506 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 507
AnnaBridge 171:3a7713b1edbc 508 /*!
AnnaBridge 171:3a7713b1edbc 509 * @addtogroup DAC_Register_Masks DAC Register Masks
AnnaBridge 171:3a7713b1edbc 510 * @{
AnnaBridge 171:3a7713b1edbc 511 */
AnnaBridge 171:3a7713b1edbc 512
AnnaBridge 171:3a7713b1edbc 513 /* DATL Bit Fields */
AnnaBridge 171:3a7713b1edbc 514 #define DAC_DATL_DATA0_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 515 #define DAC_DATL_DATA0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 516 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
AnnaBridge 171:3a7713b1edbc 517 /* DATH Bit Fields */
AnnaBridge 171:3a7713b1edbc 518 #define DAC_DATH_DATA1_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 519 #define DAC_DATH_DATA1_SHIFT 0
AnnaBridge 171:3a7713b1edbc 520 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
AnnaBridge 171:3a7713b1edbc 521 /* SR Bit Fields */
AnnaBridge 171:3a7713b1edbc 522 #define DAC_SR_DACBFRPBF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 523 #define DAC_SR_DACBFRPBF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 524 #define DAC_SR_DACBFRPTF_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 525 #define DAC_SR_DACBFRPTF_SHIFT 1
AnnaBridge 171:3a7713b1edbc 526 /* C0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 527 #define DAC_C0_DACBBIEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 528 #define DAC_C0_DACBBIEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 529 #define DAC_C0_DACBTIEN_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 530 #define DAC_C0_DACBTIEN_SHIFT 1
AnnaBridge 171:3a7713b1edbc 531 #define DAC_C0_LPEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 532 #define DAC_C0_LPEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 533 #define DAC_C0_DACSWTRG_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 534 #define DAC_C0_DACSWTRG_SHIFT 4
AnnaBridge 171:3a7713b1edbc 535 #define DAC_C0_DACTRGSEL_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 536 #define DAC_C0_DACTRGSEL_SHIFT 5
AnnaBridge 171:3a7713b1edbc 537 #define DAC_C0_DACRFS_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 538 #define DAC_C0_DACRFS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 539 #define DAC_C0_DACEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 540 #define DAC_C0_DACEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 541 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 542 #define DAC_C1_DACBFEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 543 #define DAC_C1_DACBFEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 544 #define DAC_C1_DACBFMD_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 545 #define DAC_C1_DACBFMD_SHIFT 2
AnnaBridge 171:3a7713b1edbc 546 #define DAC_C1_DMAEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 547 #define DAC_C1_DMAEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 548 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 549 #define DAC_C2_DACBFUP_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 550 #define DAC_C2_DACBFUP_SHIFT 0
AnnaBridge 171:3a7713b1edbc 551 #define DAC_C2_DACBFRP_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 552 #define DAC_C2_DACBFRP_SHIFT 4
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 /*!
AnnaBridge 171:3a7713b1edbc 555 * @}
AnnaBridge 171:3a7713b1edbc 556 */ /* end of group DAC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558
AnnaBridge 171:3a7713b1edbc 559 /* DAC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 560 /** Peripheral DAC0 base address */
AnnaBridge 171:3a7713b1edbc 561 #define DAC0_BASE (0x4003F000u)
AnnaBridge 171:3a7713b1edbc 562 /** Peripheral DAC0 base pointer */
AnnaBridge 171:3a7713b1edbc 563 #define DAC0 ((DAC_Type *)DAC0_BASE)
AnnaBridge 171:3a7713b1edbc 564 /** Array initializer of DAC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 565 #define DAC_BASES { DAC0 }
AnnaBridge 171:3a7713b1edbc 566
AnnaBridge 171:3a7713b1edbc 567 /*!
AnnaBridge 171:3a7713b1edbc 568 * @}
AnnaBridge 171:3a7713b1edbc 569 */ /* end of group DAC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 570
AnnaBridge 171:3a7713b1edbc 571
AnnaBridge 171:3a7713b1edbc 572 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 573 -- DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 574 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 575
AnnaBridge 171:3a7713b1edbc 576 /*!
AnnaBridge 171:3a7713b1edbc 577 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 578 * @{
AnnaBridge 171:3a7713b1edbc 579 */
AnnaBridge 171:3a7713b1edbc 580
AnnaBridge 171:3a7713b1edbc 581 /** DMA - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 582 typedef struct {
AnnaBridge 171:3a7713b1edbc 583 uint8_t RESERVED_0[256];
AnnaBridge 171:3a7713b1edbc 584 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 585 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 586 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 587 union { /* offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 588 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 589 struct { /* offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 590 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 591 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 592 } DMA_DSR_ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 593 };
AnnaBridge 171:3a7713b1edbc 594 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 595 } DMA[4];
AnnaBridge 171:3a7713b1edbc 596 } DMA_Type;
AnnaBridge 171:3a7713b1edbc 597
AnnaBridge 171:3a7713b1edbc 598 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 599 -- DMA Register Masks
AnnaBridge 171:3a7713b1edbc 600 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 601
AnnaBridge 171:3a7713b1edbc 602 /*!
AnnaBridge 171:3a7713b1edbc 603 * @addtogroup DMA_Register_Masks DMA Register Masks
AnnaBridge 171:3a7713b1edbc 604 * @{
AnnaBridge 171:3a7713b1edbc 605 */
AnnaBridge 171:3a7713b1edbc 606
AnnaBridge 171:3a7713b1edbc 607 /* SAR Bit Fields */
AnnaBridge 171:3a7713b1edbc 608 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 609 #define DMA_SAR_SAR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 610 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
AnnaBridge 171:3a7713b1edbc 611 /* DAR Bit Fields */
AnnaBridge 171:3a7713b1edbc 612 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 613 #define DMA_DAR_DAR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 614 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
AnnaBridge 171:3a7713b1edbc 615 /* DSR_BCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 616 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
AnnaBridge 171:3a7713b1edbc 617 #define DMA_DSR_BCR_BCR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 618 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
AnnaBridge 171:3a7713b1edbc 619 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 620 #define DMA_DSR_BCR_DONE_SHIFT 24
AnnaBridge 171:3a7713b1edbc 621 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 622 #define DMA_DSR_BCR_BSY_SHIFT 25
AnnaBridge 171:3a7713b1edbc 623 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
AnnaBridge 171:3a7713b1edbc 624 #define DMA_DSR_BCR_REQ_SHIFT 26
AnnaBridge 171:3a7713b1edbc 625 #define DMA_DSR_BCR_BED_MASK 0x10000000u
AnnaBridge 171:3a7713b1edbc 626 #define DMA_DSR_BCR_BED_SHIFT 28
AnnaBridge 171:3a7713b1edbc 627 #define DMA_DSR_BCR_BES_MASK 0x20000000u
AnnaBridge 171:3a7713b1edbc 628 #define DMA_DSR_BCR_BES_SHIFT 29
AnnaBridge 171:3a7713b1edbc 629 #define DMA_DSR_BCR_CE_MASK 0x40000000u
AnnaBridge 171:3a7713b1edbc 630 #define DMA_DSR_BCR_CE_SHIFT 30
AnnaBridge 171:3a7713b1edbc 631 /* DCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 632 #define DMA_DCR_LCH2_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 633 #define DMA_DCR_LCH2_SHIFT 0
AnnaBridge 171:3a7713b1edbc 634 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
AnnaBridge 171:3a7713b1edbc 635 #define DMA_DCR_LCH1_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 636 #define DMA_DCR_LCH1_SHIFT 2
AnnaBridge 171:3a7713b1edbc 637 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
AnnaBridge 171:3a7713b1edbc 638 #define DMA_DCR_LINKCC_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 639 #define DMA_DCR_LINKCC_SHIFT 4
AnnaBridge 171:3a7713b1edbc 640 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
AnnaBridge 171:3a7713b1edbc 641 #define DMA_DCR_D_REQ_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 642 #define DMA_DCR_D_REQ_SHIFT 7
AnnaBridge 171:3a7713b1edbc 643 #define DMA_DCR_DMOD_MASK 0xF00u
AnnaBridge 171:3a7713b1edbc 644 #define DMA_DCR_DMOD_SHIFT 8
AnnaBridge 171:3a7713b1edbc 645 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
AnnaBridge 171:3a7713b1edbc 646 #define DMA_DCR_SMOD_MASK 0xF000u
AnnaBridge 171:3a7713b1edbc 647 #define DMA_DCR_SMOD_SHIFT 12
AnnaBridge 171:3a7713b1edbc 648 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
AnnaBridge 171:3a7713b1edbc 649 #define DMA_DCR_START_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 650 #define DMA_DCR_START_SHIFT 16
AnnaBridge 171:3a7713b1edbc 651 #define DMA_DCR_DSIZE_MASK 0x60000u
AnnaBridge 171:3a7713b1edbc 652 #define DMA_DCR_DSIZE_SHIFT 17
AnnaBridge 171:3a7713b1edbc 653 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 654 #define DMA_DCR_DINC_MASK 0x80000u
AnnaBridge 171:3a7713b1edbc 655 #define DMA_DCR_DINC_SHIFT 19
AnnaBridge 171:3a7713b1edbc 656 #define DMA_DCR_SSIZE_MASK 0x300000u
AnnaBridge 171:3a7713b1edbc 657 #define DMA_DCR_SSIZE_SHIFT 20
AnnaBridge 171:3a7713b1edbc 658 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 659 #define DMA_DCR_SINC_MASK 0x400000u
AnnaBridge 171:3a7713b1edbc 660 #define DMA_DCR_SINC_SHIFT 22
AnnaBridge 171:3a7713b1edbc 661 #define DMA_DCR_EADREQ_MASK 0x800000u
AnnaBridge 171:3a7713b1edbc 662 #define DMA_DCR_EADREQ_SHIFT 23
AnnaBridge 171:3a7713b1edbc 663 #define DMA_DCR_AA_MASK 0x10000000u
AnnaBridge 171:3a7713b1edbc 664 #define DMA_DCR_AA_SHIFT 28
AnnaBridge 171:3a7713b1edbc 665 #define DMA_DCR_CS_MASK 0x20000000u
AnnaBridge 171:3a7713b1edbc 666 #define DMA_DCR_CS_SHIFT 29
AnnaBridge 171:3a7713b1edbc 667 #define DMA_DCR_ERQ_MASK 0x40000000u
AnnaBridge 171:3a7713b1edbc 668 #define DMA_DCR_ERQ_SHIFT 30
AnnaBridge 171:3a7713b1edbc 669 #define DMA_DCR_EINT_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 670 #define DMA_DCR_EINT_SHIFT 31
AnnaBridge 171:3a7713b1edbc 671
AnnaBridge 171:3a7713b1edbc 672 /*!
AnnaBridge 171:3a7713b1edbc 673 * @}
AnnaBridge 171:3a7713b1edbc 674 */ /* end of group DMA_Register_Masks */
AnnaBridge 171:3a7713b1edbc 675
AnnaBridge 171:3a7713b1edbc 676
AnnaBridge 171:3a7713b1edbc 677 /* DMA - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 678 /** Peripheral DMA base address */
AnnaBridge 171:3a7713b1edbc 679 #define DMA_BASE (0x40008000u)
AnnaBridge 171:3a7713b1edbc 680 /** Peripheral DMA base pointer */
AnnaBridge 171:3a7713b1edbc 681 #define DMA0 ((DMA_Type *)DMA_BASE)
AnnaBridge 171:3a7713b1edbc 682 /** Array initializer of DMA peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 683 #define DMA_BASES { DMA0 }
AnnaBridge 171:3a7713b1edbc 684
AnnaBridge 171:3a7713b1edbc 685 /*!
AnnaBridge 171:3a7713b1edbc 686 * @}
AnnaBridge 171:3a7713b1edbc 687 */ /* end of group DMA_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 688
AnnaBridge 171:3a7713b1edbc 689
AnnaBridge 171:3a7713b1edbc 690 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 691 -- DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 692 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 693
AnnaBridge 171:3a7713b1edbc 694 /*!
AnnaBridge 171:3a7713b1edbc 695 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 696 * @{
AnnaBridge 171:3a7713b1edbc 697 */
AnnaBridge 171:3a7713b1edbc 698
AnnaBridge 171:3a7713b1edbc 699 /** DMAMUX - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 700 typedef struct {
AnnaBridge 171:3a7713b1edbc 701 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
AnnaBridge 171:3a7713b1edbc 702 } DMAMUX_Type;
AnnaBridge 171:3a7713b1edbc 703
AnnaBridge 171:3a7713b1edbc 704 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 705 -- DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 706 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 707
AnnaBridge 171:3a7713b1edbc 708 /*!
AnnaBridge 171:3a7713b1edbc 709 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 710 * @{
AnnaBridge 171:3a7713b1edbc 711 */
AnnaBridge 171:3a7713b1edbc 712
AnnaBridge 171:3a7713b1edbc 713 /* CHCFG Bit Fields */
AnnaBridge 171:3a7713b1edbc 714 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 715 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 716 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
AnnaBridge 171:3a7713b1edbc 717 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 718 #define DMAMUX_CHCFG_TRIG_SHIFT 6
AnnaBridge 171:3a7713b1edbc 719 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 720 #define DMAMUX_CHCFG_ENBL_SHIFT 7
AnnaBridge 171:3a7713b1edbc 721
AnnaBridge 171:3a7713b1edbc 722 /*!
AnnaBridge 171:3a7713b1edbc 723 * @}
AnnaBridge 171:3a7713b1edbc 724 */ /* end of group DMAMUX_Register_Masks */
AnnaBridge 171:3a7713b1edbc 725
AnnaBridge 171:3a7713b1edbc 726
AnnaBridge 171:3a7713b1edbc 727 /* DMAMUX - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 728 /** Peripheral DMAMUX0 base address */
AnnaBridge 171:3a7713b1edbc 729 #define DMAMUX0_BASE (0x40021000u)
AnnaBridge 171:3a7713b1edbc 730 /** Peripheral DMAMUX0 base pointer */
AnnaBridge 171:3a7713b1edbc 731 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
AnnaBridge 171:3a7713b1edbc 732 /** Array initializer of DMAMUX peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 733 #define DMAMUX_BASES { DMAMUX0 }
AnnaBridge 171:3a7713b1edbc 734
AnnaBridge 171:3a7713b1edbc 735 /*!
AnnaBridge 171:3a7713b1edbc 736 * @}
AnnaBridge 171:3a7713b1edbc 737 */ /* end of group DMAMUX_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 738
AnnaBridge 171:3a7713b1edbc 739
AnnaBridge 171:3a7713b1edbc 740 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 741 -- FGPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 742 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 743
AnnaBridge 171:3a7713b1edbc 744 /*!
AnnaBridge 171:3a7713b1edbc 745 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 746 * @{
AnnaBridge 171:3a7713b1edbc 747 */
AnnaBridge 171:3a7713b1edbc 748
AnnaBridge 171:3a7713b1edbc 749 /** FGPIO - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 750 typedef struct {
AnnaBridge 171:3a7713b1edbc 751 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 752 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 753 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 754 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 755 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 756 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 757 } FGPIO_Type;
AnnaBridge 171:3a7713b1edbc 758
AnnaBridge 171:3a7713b1edbc 759 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 760 -- FGPIO Register Masks
AnnaBridge 171:3a7713b1edbc 761 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 762
AnnaBridge 171:3a7713b1edbc 763 /*!
AnnaBridge 171:3a7713b1edbc 764 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
AnnaBridge 171:3a7713b1edbc 765 * @{
AnnaBridge 171:3a7713b1edbc 766 */
AnnaBridge 171:3a7713b1edbc 767
AnnaBridge 171:3a7713b1edbc 768 /* PDOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 769 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 770 #define FGPIO_PDOR_PDO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 771 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
AnnaBridge 171:3a7713b1edbc 772 /* PSOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 773 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 774 #define FGPIO_PSOR_PTSO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 775 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
AnnaBridge 171:3a7713b1edbc 776 /* PCOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 777 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 778 #define FGPIO_PCOR_PTCO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 779 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
AnnaBridge 171:3a7713b1edbc 780 /* PTOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 781 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 782 #define FGPIO_PTOR_PTTO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 783 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
AnnaBridge 171:3a7713b1edbc 784 /* PDIR Bit Fields */
AnnaBridge 171:3a7713b1edbc 785 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 786 #define FGPIO_PDIR_PDI_SHIFT 0
AnnaBridge 171:3a7713b1edbc 787 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
AnnaBridge 171:3a7713b1edbc 788 /* PDDR Bit Fields */
AnnaBridge 171:3a7713b1edbc 789 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 790 #define FGPIO_PDDR_PDD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 791 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
AnnaBridge 171:3a7713b1edbc 792
AnnaBridge 171:3a7713b1edbc 793 /*!
AnnaBridge 171:3a7713b1edbc 794 * @}
AnnaBridge 171:3a7713b1edbc 795 */ /* end of group FGPIO_Register_Masks */
AnnaBridge 171:3a7713b1edbc 796
AnnaBridge 171:3a7713b1edbc 797
AnnaBridge 171:3a7713b1edbc 798 /* FGPIO - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 799 /** Peripheral FPTA base address */
AnnaBridge 171:3a7713b1edbc 800 #define FPTA_BASE (0xF80FF000u)
AnnaBridge 171:3a7713b1edbc 801 /** Peripheral FPTA base pointer */
AnnaBridge 171:3a7713b1edbc 802 #define FPTA ((FGPIO_Type *)FPTA_BASE)
AnnaBridge 171:3a7713b1edbc 803 /** Peripheral FPTB base address */
AnnaBridge 171:3a7713b1edbc 804 #define FPTB_BASE (0xF80FF040u)
AnnaBridge 171:3a7713b1edbc 805 /** Peripheral FPTB base pointer */
AnnaBridge 171:3a7713b1edbc 806 #define FPTB ((FGPIO_Type *)FPTB_BASE)
AnnaBridge 171:3a7713b1edbc 807 /** Peripheral FPTC base address */
AnnaBridge 171:3a7713b1edbc 808 #define FPTC_BASE (0xF80FF080u)
AnnaBridge 171:3a7713b1edbc 809 /** Peripheral FPTC base pointer */
AnnaBridge 171:3a7713b1edbc 810 #define FPTC ((FGPIO_Type *)FPTC_BASE)
AnnaBridge 171:3a7713b1edbc 811 /** Peripheral FPTD base address */
AnnaBridge 171:3a7713b1edbc 812 #define FPTD_BASE (0xF80FF0C0u)
AnnaBridge 171:3a7713b1edbc 813 /** Peripheral FPTD base pointer */
AnnaBridge 171:3a7713b1edbc 814 #define FPTD ((FGPIO_Type *)FPTD_BASE)
AnnaBridge 171:3a7713b1edbc 815 /** Peripheral FPTE base address */
AnnaBridge 171:3a7713b1edbc 816 #define FPTE_BASE (0xF80FF100u)
AnnaBridge 171:3a7713b1edbc 817 /** Peripheral FPTE base pointer */
AnnaBridge 171:3a7713b1edbc 818 #define FPTE ((FGPIO_Type *)FPTE_BASE)
AnnaBridge 171:3a7713b1edbc 819 /** Array initializer of FGPIO peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 820 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
AnnaBridge 171:3a7713b1edbc 821
AnnaBridge 171:3a7713b1edbc 822 /*!
AnnaBridge 171:3a7713b1edbc 823 * @}
AnnaBridge 171:3a7713b1edbc 824 */ /* end of group FGPIO_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 825
AnnaBridge 171:3a7713b1edbc 826
AnnaBridge 171:3a7713b1edbc 827 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 828 -- FTFA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 829 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 830
AnnaBridge 171:3a7713b1edbc 831 /*!
AnnaBridge 171:3a7713b1edbc 832 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 833 * @{
AnnaBridge 171:3a7713b1edbc 834 */
AnnaBridge 171:3a7713b1edbc 835
AnnaBridge 171:3a7713b1edbc 836 /** FTFA - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 837 typedef struct {
AnnaBridge 171:3a7713b1edbc 838 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 839 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 840 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 841 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 842 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 843 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 844 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 845 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 846 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 847 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 848 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 849 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 850 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 851 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 852 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 853 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 854 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 855 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
AnnaBridge 171:3a7713b1edbc 856 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 857 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
AnnaBridge 171:3a7713b1edbc 858 } FTFA_Type;
AnnaBridge 171:3a7713b1edbc 859
AnnaBridge 171:3a7713b1edbc 860 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 861 -- FTFA Register Masks
AnnaBridge 171:3a7713b1edbc 862 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 863
AnnaBridge 171:3a7713b1edbc 864 /*!
AnnaBridge 171:3a7713b1edbc 865 * @addtogroup FTFA_Register_Masks FTFA Register Masks
AnnaBridge 171:3a7713b1edbc 866 * @{
AnnaBridge 171:3a7713b1edbc 867 */
AnnaBridge 171:3a7713b1edbc 868
AnnaBridge 171:3a7713b1edbc 869 /* FSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 870 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 871 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 872 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 873 #define FTFA_FSTAT_FPVIOL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 874 #define FTFA_FSTAT_ACCERR_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 875 #define FTFA_FSTAT_ACCERR_SHIFT 5
AnnaBridge 171:3a7713b1edbc 876 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 877 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
AnnaBridge 171:3a7713b1edbc 878 #define FTFA_FSTAT_CCIF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 879 #define FTFA_FSTAT_CCIF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 880 /* FCNFG Bit Fields */
AnnaBridge 171:3a7713b1edbc 881 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 882 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
AnnaBridge 171:3a7713b1edbc 883 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 884 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
AnnaBridge 171:3a7713b1edbc 885 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 886 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 887 #define FTFA_FCNFG_CCIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 888 #define FTFA_FCNFG_CCIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 889 /* FSEC Bit Fields */
AnnaBridge 171:3a7713b1edbc 890 #define FTFA_FSEC_SEC_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 891 #define FTFA_FSEC_SEC_SHIFT 0
AnnaBridge 171:3a7713b1edbc 892 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 893 #define FTFA_FSEC_FSLACC_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 894 #define FTFA_FSEC_FSLACC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 895 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 896 #define FTFA_FSEC_MEEN_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 897 #define FTFA_FSEC_MEEN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 898 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 899 #define FTFA_FSEC_KEYEN_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 900 #define FTFA_FSEC_KEYEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 901 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 902 /* FOPT Bit Fields */
AnnaBridge 171:3a7713b1edbc 903 #define FTFA_FOPT_OPT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 904 #define FTFA_FOPT_OPT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 905 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
AnnaBridge 171:3a7713b1edbc 906 /* FCCOB3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 907 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 908 #define FTFA_FCCOB3_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 909 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 910 /* FCCOB2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 911 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 912 #define FTFA_FCCOB2_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 913 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 914 /* FCCOB1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 915 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 916 #define FTFA_FCCOB1_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 917 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 918 /* FCCOB0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 919 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 920 #define FTFA_FCCOB0_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 921 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 922 /* FCCOB7 Bit Fields */
AnnaBridge 171:3a7713b1edbc 923 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 924 #define FTFA_FCCOB7_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 925 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 926 /* FCCOB6 Bit Fields */
AnnaBridge 171:3a7713b1edbc 927 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 928 #define FTFA_FCCOB6_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 929 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 930 /* FCCOB5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 931 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 932 #define FTFA_FCCOB5_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 933 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 934 /* FCCOB4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 935 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 936 #define FTFA_FCCOB4_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 937 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 938 /* FCCOBB Bit Fields */
AnnaBridge 171:3a7713b1edbc 939 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 940 #define FTFA_FCCOBB_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 941 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 942 /* FCCOBA Bit Fields */
AnnaBridge 171:3a7713b1edbc 943 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 944 #define FTFA_FCCOBA_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 945 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 946 /* FCCOB9 Bit Fields */
AnnaBridge 171:3a7713b1edbc 947 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 948 #define FTFA_FCCOB9_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 949 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 950 /* FCCOB8 Bit Fields */
AnnaBridge 171:3a7713b1edbc 951 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 952 #define FTFA_FCCOB8_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 953 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 954 /* FPROT3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 955 #define FTFA_FPROT3_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 956 #define FTFA_FPROT3_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 957 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 958 /* FPROT2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 959 #define FTFA_FPROT2_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 960 #define FTFA_FPROT2_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 961 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 962 /* FPROT1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 963 #define FTFA_FPROT1_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 964 #define FTFA_FPROT1_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 965 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 966 /* FPROT0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 967 #define FTFA_FPROT0_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 968 #define FTFA_FPROT0_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 969 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 970
AnnaBridge 171:3a7713b1edbc 971 /*!
AnnaBridge 171:3a7713b1edbc 972 * @}
AnnaBridge 171:3a7713b1edbc 973 */ /* end of group FTFA_Register_Masks */
AnnaBridge 171:3a7713b1edbc 974
AnnaBridge 171:3a7713b1edbc 975
AnnaBridge 171:3a7713b1edbc 976 /* FTFA - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 977 /** Peripheral FTFA base address */
AnnaBridge 171:3a7713b1edbc 978 #define FTFA_BASE (0x40020000u)
AnnaBridge 171:3a7713b1edbc 979 /** Peripheral FTFA base pointer */
AnnaBridge 171:3a7713b1edbc 980 #define FTFA ((FTFA_Type *)FTFA_BASE)
AnnaBridge 171:3a7713b1edbc 981 /** Array initializer of FTFA peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 982 #define FTFA_BASES { FTFA }
AnnaBridge 171:3a7713b1edbc 983
AnnaBridge 171:3a7713b1edbc 984 /*!
AnnaBridge 171:3a7713b1edbc 985 * @}
AnnaBridge 171:3a7713b1edbc 986 */ /* end of group FTFA_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 987
AnnaBridge 171:3a7713b1edbc 988
AnnaBridge 171:3a7713b1edbc 989 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 990 -- GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 991 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 992
AnnaBridge 171:3a7713b1edbc 993 /*!
AnnaBridge 171:3a7713b1edbc 994 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 995 * @{
AnnaBridge 171:3a7713b1edbc 996 */
AnnaBridge 171:3a7713b1edbc 997
AnnaBridge 171:3a7713b1edbc 998 /** GPIO - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 999 typedef struct {
AnnaBridge 171:3a7713b1edbc 1000 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1001 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1002 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1003 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1004 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 1005 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 1006 } GPIO_Type;
AnnaBridge 171:3a7713b1edbc 1007
AnnaBridge 171:3a7713b1edbc 1008 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1009 -- GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 1010 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1011
AnnaBridge 171:3a7713b1edbc 1012 /*!
AnnaBridge 171:3a7713b1edbc 1013 * @addtogroup GPIO_Register_Masks GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 1014 * @{
AnnaBridge 171:3a7713b1edbc 1015 */
AnnaBridge 171:3a7713b1edbc 1016
AnnaBridge 171:3a7713b1edbc 1017 /* PDOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1018 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1019 #define GPIO_PDOR_PDO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1020 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
AnnaBridge 171:3a7713b1edbc 1021 /* PSOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1022 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1023 #define GPIO_PSOR_PTSO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1024 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
AnnaBridge 171:3a7713b1edbc 1025 /* PCOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1026 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1027 #define GPIO_PCOR_PTCO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1028 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
AnnaBridge 171:3a7713b1edbc 1029 /* PTOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1030 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1031 #define GPIO_PTOR_PTTO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1032 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
AnnaBridge 171:3a7713b1edbc 1033 /* PDIR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1034 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1035 #define GPIO_PDIR_PDI_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1036 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
AnnaBridge 171:3a7713b1edbc 1037 /* PDDR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1038 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1039 #define GPIO_PDDR_PDD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1040 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
AnnaBridge 171:3a7713b1edbc 1041
AnnaBridge 171:3a7713b1edbc 1042 /*!
AnnaBridge 171:3a7713b1edbc 1043 * @}
AnnaBridge 171:3a7713b1edbc 1044 */ /* end of group GPIO_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1045
AnnaBridge 171:3a7713b1edbc 1046
AnnaBridge 171:3a7713b1edbc 1047 /* GPIO - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1048 /** Peripheral PTA base address */
AnnaBridge 171:3a7713b1edbc 1049 #define PTA_BASE (0x400FF000u)
AnnaBridge 171:3a7713b1edbc 1050 /** Peripheral PTA base pointer */
AnnaBridge 171:3a7713b1edbc 1051 #define PTA ((GPIO_Type *)PTA_BASE)
AnnaBridge 171:3a7713b1edbc 1052 /** Peripheral PTB base address */
AnnaBridge 171:3a7713b1edbc 1053 #define PTB_BASE (0x400FF040u)
AnnaBridge 171:3a7713b1edbc 1054 /** Peripheral PTB base pointer */
AnnaBridge 171:3a7713b1edbc 1055 #define PTB ((GPIO_Type *)PTB_BASE)
AnnaBridge 171:3a7713b1edbc 1056 /** Peripheral PTC base address */
AnnaBridge 171:3a7713b1edbc 1057 #define PTC_BASE (0x400FF080u)
AnnaBridge 171:3a7713b1edbc 1058 /** Peripheral PTC base pointer */
AnnaBridge 171:3a7713b1edbc 1059 #define PTC ((GPIO_Type *)PTC_BASE)
AnnaBridge 171:3a7713b1edbc 1060 /** Peripheral PTD base address */
AnnaBridge 171:3a7713b1edbc 1061 #define PTD_BASE (0x400FF0C0u)
AnnaBridge 171:3a7713b1edbc 1062 /** Peripheral PTD base pointer */
AnnaBridge 171:3a7713b1edbc 1063 #define PTD ((GPIO_Type *)PTD_BASE)
AnnaBridge 171:3a7713b1edbc 1064 /** Peripheral PTE base address */
AnnaBridge 171:3a7713b1edbc 1065 #define PTE_BASE (0x400FF100u)
AnnaBridge 171:3a7713b1edbc 1066 /** Peripheral PTE base pointer */
AnnaBridge 171:3a7713b1edbc 1067 #define PTE ((GPIO_Type *)PTE_BASE)
AnnaBridge 171:3a7713b1edbc 1068 /** Array initializer of GPIO peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1069 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
AnnaBridge 171:3a7713b1edbc 1070
AnnaBridge 171:3a7713b1edbc 1071 /*!
AnnaBridge 171:3a7713b1edbc 1072 * @}
AnnaBridge 171:3a7713b1edbc 1073 */ /* end of group GPIO_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1074
AnnaBridge 171:3a7713b1edbc 1075
AnnaBridge 171:3a7713b1edbc 1076 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1077 -- I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1078 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1079
AnnaBridge 171:3a7713b1edbc 1080 /*!
AnnaBridge 171:3a7713b1edbc 1081 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1082 * @{
AnnaBridge 171:3a7713b1edbc 1083 */
AnnaBridge 171:3a7713b1edbc 1084
AnnaBridge 171:3a7713b1edbc 1085 /** I2C - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1086 typedef struct {
AnnaBridge 171:3a7713b1edbc 1087 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1088 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 1089 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1090 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 1091 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1092 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 1093 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 1094 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 1095 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1096 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 1097 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 1098 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 1099 } I2C_Type;
AnnaBridge 171:3a7713b1edbc 1100
AnnaBridge 171:3a7713b1edbc 1101 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1102 -- I2C Register Masks
AnnaBridge 171:3a7713b1edbc 1103 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1104
AnnaBridge 171:3a7713b1edbc 1105 /*!
AnnaBridge 171:3a7713b1edbc 1106 * @addtogroup I2C_Register_Masks I2C Register Masks
AnnaBridge 171:3a7713b1edbc 1107 * @{
AnnaBridge 171:3a7713b1edbc 1108 */
AnnaBridge 171:3a7713b1edbc 1109
AnnaBridge 171:3a7713b1edbc 1110 /* A1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1111 #define I2C_A1_AD_MASK 0xFEu
AnnaBridge 171:3a7713b1edbc 1112 #define I2C_A1_AD_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1113 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
AnnaBridge 171:3a7713b1edbc 1114 /* F Bit Fields */
AnnaBridge 171:3a7713b1edbc 1115 #define I2C_F_ICR_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 1116 #define I2C_F_ICR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1117 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
AnnaBridge 171:3a7713b1edbc 1118 #define I2C_F_MULT_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 1119 #define I2C_F_MULT_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1120 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
AnnaBridge 171:3a7713b1edbc 1121 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1122 #define I2C_C1_DMAEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1123 #define I2C_C1_DMAEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1124 #define I2C_C1_WUEN_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1125 #define I2C_C1_WUEN_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1126 #define I2C_C1_RSTA_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1127 #define I2C_C1_RSTA_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1128 #define I2C_C1_TXAK_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1129 #define I2C_C1_TXAK_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1130 #define I2C_C1_TX_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1131 #define I2C_C1_TX_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1132 #define I2C_C1_MST_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1133 #define I2C_C1_MST_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1134 #define I2C_C1_IICIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1135 #define I2C_C1_IICIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1136 #define I2C_C1_IICEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1137 #define I2C_C1_IICEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1138 /* S Bit Fields */
AnnaBridge 171:3a7713b1edbc 1139 #define I2C_S_RXAK_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1140 #define I2C_S_RXAK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1141 #define I2C_S_IICIF_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1142 #define I2C_S_IICIF_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1143 #define I2C_S_SRW_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1144 #define I2C_S_SRW_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1145 #define I2C_S_RAM_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1146 #define I2C_S_RAM_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1147 #define I2C_S_ARBL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1148 #define I2C_S_ARBL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1149 #define I2C_S_BUSY_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1150 #define I2C_S_BUSY_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1151 #define I2C_S_IAAS_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1152 #define I2C_S_IAAS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1153 #define I2C_S_TCF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1154 #define I2C_S_TCF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1155 /* D Bit Fields */
AnnaBridge 171:3a7713b1edbc 1156 #define I2C_D_DATA_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1157 #define I2C_D_DATA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1158 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 1159 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1160 #define I2C_C2_AD_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 1161 #define I2C_C2_AD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1162 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
AnnaBridge 171:3a7713b1edbc 1163 #define I2C_C2_RMEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1164 #define I2C_C2_RMEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1165 #define I2C_C2_SBRC_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1166 #define I2C_C2_SBRC_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1167 #define I2C_C2_HDRS_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1168 #define I2C_C2_HDRS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1169 #define I2C_C2_ADEXT_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1170 #define I2C_C2_ADEXT_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1171 #define I2C_C2_GCAEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1172 #define I2C_C2_GCAEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1173 /* FLT Bit Fields */
AnnaBridge 171:3a7713b1edbc 1174 #define I2C_FLT_FLT_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 1175 #define I2C_FLT_FLT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1176 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
AnnaBridge 171:3a7713b1edbc 1177 #define I2C_FLT_STOPIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1178 #define I2C_FLT_STOPIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1179 #define I2C_FLT_STOPF_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1180 #define I2C_FLT_STOPF_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1181 #define I2C_FLT_SHEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1182 #define I2C_FLT_SHEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1183 /* RA Bit Fields */
AnnaBridge 171:3a7713b1edbc 1184 #define I2C_RA_RAD_MASK 0xFEu
AnnaBridge 171:3a7713b1edbc 1185 #define I2C_RA_RAD_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1186 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
AnnaBridge 171:3a7713b1edbc 1187 /* SMB Bit Fields */
AnnaBridge 171:3a7713b1edbc 1188 #define I2C_SMB_SHTF2IE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1189 #define I2C_SMB_SHTF2IE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1190 #define I2C_SMB_SHTF2_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1191 #define I2C_SMB_SHTF2_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1192 #define I2C_SMB_SHTF1_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1193 #define I2C_SMB_SHTF1_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1194 #define I2C_SMB_SLTF_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1195 #define I2C_SMB_SLTF_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1196 #define I2C_SMB_TCKSEL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1197 #define I2C_SMB_TCKSEL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1198 #define I2C_SMB_SIICAEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1199 #define I2C_SMB_SIICAEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1200 #define I2C_SMB_ALERTEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1201 #define I2C_SMB_ALERTEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1202 #define I2C_SMB_FACK_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1203 #define I2C_SMB_FACK_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1204 /* A2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1205 #define I2C_A2_SAD_MASK 0xFEu
AnnaBridge 171:3a7713b1edbc 1206 #define I2C_A2_SAD_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1207 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
AnnaBridge 171:3a7713b1edbc 1208 /* SLTH Bit Fields */
AnnaBridge 171:3a7713b1edbc 1209 #define I2C_SLTH_SSLT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1210 #define I2C_SLTH_SSLT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1211 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 1212 /* SLTL Bit Fields */
AnnaBridge 171:3a7713b1edbc 1213 #define I2C_SLTL_SSLT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1214 #define I2C_SLTL_SSLT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1215 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 1216
AnnaBridge 171:3a7713b1edbc 1217 /*!
AnnaBridge 171:3a7713b1edbc 1218 * @}
AnnaBridge 171:3a7713b1edbc 1219 */ /* end of group I2C_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1220
AnnaBridge 171:3a7713b1edbc 1221
AnnaBridge 171:3a7713b1edbc 1222 /* I2C - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1223 /** Peripheral I2C0 base address */
AnnaBridge 171:3a7713b1edbc 1224 #define I2C0_BASE (0x40066000u)
AnnaBridge 171:3a7713b1edbc 1225 /** Peripheral I2C0 base pointer */
AnnaBridge 171:3a7713b1edbc 1226 #define I2C0 ((I2C_Type *)I2C0_BASE)
AnnaBridge 171:3a7713b1edbc 1227 /** Peripheral I2C1 base address */
AnnaBridge 171:3a7713b1edbc 1228 #define I2C1_BASE (0x40067000u)
AnnaBridge 171:3a7713b1edbc 1229 /** Peripheral I2C1 base pointer */
AnnaBridge 171:3a7713b1edbc 1230 #define I2C1 ((I2C_Type *)I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 1231 /** Array initializer of I2C peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1232 #define I2C_BASES { I2C0, I2C1 }
AnnaBridge 171:3a7713b1edbc 1233
AnnaBridge 171:3a7713b1edbc 1234 /*!
AnnaBridge 171:3a7713b1edbc 1235 * @}
AnnaBridge 171:3a7713b1edbc 1236 */ /* end of group I2C_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1237
AnnaBridge 171:3a7713b1edbc 1238
AnnaBridge 171:3a7713b1edbc 1239 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1240 -- I2S Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1241 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1242
AnnaBridge 171:3a7713b1edbc 1243 /*!
AnnaBridge 171:3a7713b1edbc 1244 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1245 * @{
AnnaBridge 171:3a7713b1edbc 1246 */
AnnaBridge 171:3a7713b1edbc 1247
AnnaBridge 171:3a7713b1edbc 1248 /** I2S - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1249 typedef struct {
AnnaBridge 171:3a7713b1edbc 1250 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1251 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 1252 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1253 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1254 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 1255 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 1256 uint8_t RESERVED_1[8];
AnnaBridge 171:3a7713b1edbc 1257 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1258 uint8_t RESERVED_2[60];
AnnaBridge 171:3a7713b1edbc 1259 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 1260 uint8_t RESERVED_3[28];
AnnaBridge 171:3a7713b1edbc 1261 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 1262 uint8_t RESERVED_4[4];
AnnaBridge 171:3a7713b1edbc 1263 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 1264 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 1265 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 1266 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 1267 uint8_t RESERVED_5[8];
AnnaBridge 171:3a7713b1edbc 1268 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1269 uint8_t RESERVED_6[60];
AnnaBridge 171:3a7713b1edbc 1270 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
AnnaBridge 171:3a7713b1edbc 1271 uint8_t RESERVED_7[28];
AnnaBridge 171:3a7713b1edbc 1272 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 1273 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 1274 } I2S_Type;
AnnaBridge 171:3a7713b1edbc 1275
AnnaBridge 171:3a7713b1edbc 1276 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1277 -- I2S Register Masks
AnnaBridge 171:3a7713b1edbc 1278 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1279
AnnaBridge 171:3a7713b1edbc 1280 /*!
AnnaBridge 171:3a7713b1edbc 1281 * @addtogroup I2S_Register_Masks I2S Register Masks
AnnaBridge 171:3a7713b1edbc 1282 * @{
AnnaBridge 171:3a7713b1edbc 1283 */
AnnaBridge 171:3a7713b1edbc 1284
AnnaBridge 171:3a7713b1edbc 1285 /* TCSR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1286 #define I2S_TCSR_FWDE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1287 #define I2S_TCSR_FWDE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1288 #define I2S_TCSR_FWIE_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 1289 #define I2S_TCSR_FWIE_SHIFT 9
AnnaBridge 171:3a7713b1edbc 1290 #define I2S_TCSR_FEIE_MASK 0x400u
AnnaBridge 171:3a7713b1edbc 1291 #define I2S_TCSR_FEIE_SHIFT 10
AnnaBridge 171:3a7713b1edbc 1292 #define I2S_TCSR_SEIE_MASK 0x800u
AnnaBridge 171:3a7713b1edbc 1293 #define I2S_TCSR_SEIE_SHIFT 11
AnnaBridge 171:3a7713b1edbc 1294 #define I2S_TCSR_WSIE_MASK 0x1000u
AnnaBridge 171:3a7713b1edbc 1295 #define I2S_TCSR_WSIE_SHIFT 12
AnnaBridge 171:3a7713b1edbc 1296 #define I2S_TCSR_FWF_MASK 0x20000u
AnnaBridge 171:3a7713b1edbc 1297 #define I2S_TCSR_FWF_SHIFT 17
AnnaBridge 171:3a7713b1edbc 1298 #define I2S_TCSR_FEF_MASK 0x40000u
AnnaBridge 171:3a7713b1edbc 1299 #define I2S_TCSR_FEF_SHIFT 18
AnnaBridge 171:3a7713b1edbc 1300 #define I2S_TCSR_SEF_MASK 0x80000u
AnnaBridge 171:3a7713b1edbc 1301 #define I2S_TCSR_SEF_SHIFT 19
AnnaBridge 171:3a7713b1edbc 1302 #define I2S_TCSR_WSF_MASK 0x100000u
AnnaBridge 171:3a7713b1edbc 1303 #define I2S_TCSR_WSF_SHIFT 20
AnnaBridge 171:3a7713b1edbc 1304 #define I2S_TCSR_SR_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 1305 #define I2S_TCSR_SR_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1306 #define I2S_TCSR_FR_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 1307 #define I2S_TCSR_FR_SHIFT 25
AnnaBridge 171:3a7713b1edbc 1308 #define I2S_TCSR_BCE_MASK 0x10000000u
AnnaBridge 171:3a7713b1edbc 1309 #define I2S_TCSR_BCE_SHIFT 28
AnnaBridge 171:3a7713b1edbc 1310 #define I2S_TCSR_DBGE_MASK 0x20000000u
AnnaBridge 171:3a7713b1edbc 1311 #define I2S_TCSR_DBGE_SHIFT 29
AnnaBridge 171:3a7713b1edbc 1312 #define I2S_TCSR_STOPE_MASK 0x40000000u
AnnaBridge 171:3a7713b1edbc 1313 #define I2S_TCSR_STOPE_SHIFT 30
AnnaBridge 171:3a7713b1edbc 1314 #define I2S_TCSR_TE_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 1315 #define I2S_TCSR_TE_SHIFT 31
AnnaBridge 171:3a7713b1edbc 1316 /* TCR2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1317 #define I2S_TCR2_DIV_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1318 #define I2S_TCR2_DIV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1319 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
AnnaBridge 171:3a7713b1edbc 1320 #define I2S_TCR2_BCD_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 1321 #define I2S_TCR2_BCD_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1322 #define I2S_TCR2_BCP_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 1323 #define I2S_TCR2_BCP_SHIFT 25
AnnaBridge 171:3a7713b1edbc 1324 #define I2S_TCR2_CLKMODE_MASK 0xC000000u
AnnaBridge 171:3a7713b1edbc 1325 #define I2S_TCR2_CLKMODE_SHIFT 26
AnnaBridge 171:3a7713b1edbc 1326 #define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
AnnaBridge 171:3a7713b1edbc 1327 /* TCR3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1328 #define I2S_TCR3_WDFL_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1329 #define I2S_TCR3_WDFL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1330 #define I2S_TCR3_TCE_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 1331 #define I2S_TCR3_TCE_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1332 /* TCR4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1333 #define I2S_TCR4_FSD_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1334 #define I2S_TCR4_FSD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1335 #define I2S_TCR4_FSP_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1336 #define I2S_TCR4_FSP_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1337 #define I2S_TCR4_FSE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1338 #define I2S_TCR4_FSE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1339 #define I2S_TCR4_MF_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1340 #define I2S_TCR4_MF_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1341 #define I2S_TCR4_SYWD_MASK 0x1F00u
AnnaBridge 171:3a7713b1edbc 1342 #define I2S_TCR4_SYWD_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1343 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
AnnaBridge 171:3a7713b1edbc 1344 #define I2S_TCR4_FRSZ_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 1345 #define I2S_TCR4_FRSZ_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1346 /* TCR5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1347 #define I2S_TCR5_FBT_MASK 0x1F00u
AnnaBridge 171:3a7713b1edbc 1348 #define I2S_TCR5_FBT_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1349 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
AnnaBridge 171:3a7713b1edbc 1350 #define I2S_TCR5_W0W_MASK 0x1F0000u
AnnaBridge 171:3a7713b1edbc 1351 #define I2S_TCR5_W0W_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1352 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
AnnaBridge 171:3a7713b1edbc 1353 #define I2S_TCR5_WNW_MASK 0x1F000000u
AnnaBridge 171:3a7713b1edbc 1354 #define I2S_TCR5_WNW_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1355 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
AnnaBridge 171:3a7713b1edbc 1356 /* TDR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1357 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1358 #define I2S_TDR_TDR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1359 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
AnnaBridge 171:3a7713b1edbc 1360 /* TMR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1361 #define I2S_TMR_TWM_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 1362 #define I2S_TMR_TWM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1363 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
AnnaBridge 171:3a7713b1edbc 1364 /* RCSR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1365 #define I2S_RCSR_FWDE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1366 #define I2S_RCSR_FWDE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1367 #define I2S_RCSR_FWIE_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 1368 #define I2S_RCSR_FWIE_SHIFT 9
AnnaBridge 171:3a7713b1edbc 1369 #define I2S_RCSR_FEIE_MASK 0x400u
AnnaBridge 171:3a7713b1edbc 1370 #define I2S_RCSR_FEIE_SHIFT 10
AnnaBridge 171:3a7713b1edbc 1371 #define I2S_RCSR_SEIE_MASK 0x800u
AnnaBridge 171:3a7713b1edbc 1372 #define I2S_RCSR_SEIE_SHIFT 11
AnnaBridge 171:3a7713b1edbc 1373 #define I2S_RCSR_WSIE_MASK 0x1000u
AnnaBridge 171:3a7713b1edbc 1374 #define I2S_RCSR_WSIE_SHIFT 12
AnnaBridge 171:3a7713b1edbc 1375 #define I2S_RCSR_FWF_MASK 0x20000u
AnnaBridge 171:3a7713b1edbc 1376 #define I2S_RCSR_FWF_SHIFT 17
AnnaBridge 171:3a7713b1edbc 1377 #define I2S_RCSR_FEF_MASK 0x40000u
AnnaBridge 171:3a7713b1edbc 1378 #define I2S_RCSR_FEF_SHIFT 18
AnnaBridge 171:3a7713b1edbc 1379 #define I2S_RCSR_SEF_MASK 0x80000u
AnnaBridge 171:3a7713b1edbc 1380 #define I2S_RCSR_SEF_SHIFT 19
AnnaBridge 171:3a7713b1edbc 1381 #define I2S_RCSR_WSF_MASK 0x100000u
AnnaBridge 171:3a7713b1edbc 1382 #define I2S_RCSR_WSF_SHIFT 20
AnnaBridge 171:3a7713b1edbc 1383 #define I2S_RCSR_SR_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 1384 #define I2S_RCSR_SR_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1385 #define I2S_RCSR_FR_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 1386 #define I2S_RCSR_FR_SHIFT 25
AnnaBridge 171:3a7713b1edbc 1387 #define I2S_RCSR_BCE_MASK 0x10000000u
AnnaBridge 171:3a7713b1edbc 1388 #define I2S_RCSR_BCE_SHIFT 28
AnnaBridge 171:3a7713b1edbc 1389 #define I2S_RCSR_DBGE_MASK 0x20000000u
AnnaBridge 171:3a7713b1edbc 1390 #define I2S_RCSR_DBGE_SHIFT 29
AnnaBridge 171:3a7713b1edbc 1391 #define I2S_RCSR_STOPE_MASK 0x40000000u
AnnaBridge 171:3a7713b1edbc 1392 #define I2S_RCSR_STOPE_SHIFT 30
AnnaBridge 171:3a7713b1edbc 1393 #define I2S_RCSR_RE_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 1394 #define I2S_RCSR_RE_SHIFT 31
AnnaBridge 171:3a7713b1edbc 1395 /* RCR2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1396 #define I2S_RCR2_DIV_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1397 #define I2S_RCR2_DIV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1398 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
AnnaBridge 171:3a7713b1edbc 1399 #define I2S_RCR2_BCD_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 1400 #define I2S_RCR2_BCD_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1401 #define I2S_RCR2_BCP_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 1402 #define I2S_RCR2_BCP_SHIFT 25
AnnaBridge 171:3a7713b1edbc 1403 #define I2S_RCR2_CLKMODE_MASK 0xC000000u
AnnaBridge 171:3a7713b1edbc 1404 #define I2S_RCR2_CLKMODE_SHIFT 26
AnnaBridge 171:3a7713b1edbc 1405 #define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
AnnaBridge 171:3a7713b1edbc 1406 /* RCR3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1407 #define I2S_RCR3_WDFL_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1408 #define I2S_RCR3_WDFL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1409 #define I2S_RCR3_RCE_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 1410 #define I2S_RCR3_RCE_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1411 /* RCR4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1412 #define I2S_RCR4_FSD_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1413 #define I2S_RCR4_FSD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1414 #define I2S_RCR4_FSP_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1415 #define I2S_RCR4_FSP_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1416 #define I2S_RCR4_FSE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1417 #define I2S_RCR4_FSE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1418 #define I2S_RCR4_MF_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1419 #define I2S_RCR4_MF_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1420 #define I2S_RCR4_SYWD_MASK 0x1F00u
AnnaBridge 171:3a7713b1edbc 1421 #define I2S_RCR4_SYWD_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1422 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
AnnaBridge 171:3a7713b1edbc 1423 #define I2S_RCR4_FRSZ_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 1424 #define I2S_RCR4_FRSZ_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1425 /* RCR5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1426 #define I2S_RCR5_FBT_MASK 0x1F00u
AnnaBridge 171:3a7713b1edbc 1427 #define I2S_RCR5_FBT_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1428 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
AnnaBridge 171:3a7713b1edbc 1429 #define I2S_RCR5_W0W_MASK 0x1F0000u
AnnaBridge 171:3a7713b1edbc 1430 #define I2S_RCR5_W0W_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1431 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
AnnaBridge 171:3a7713b1edbc 1432 #define I2S_RCR5_WNW_MASK 0x1F000000u
AnnaBridge 171:3a7713b1edbc 1433 #define I2S_RCR5_WNW_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1434 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
AnnaBridge 171:3a7713b1edbc 1435 /* RDR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1436 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1437 #define I2S_RDR_RDR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1438 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
AnnaBridge 171:3a7713b1edbc 1439 /* RMR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1440 #define I2S_RMR_RWM_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 1441 #define I2S_RMR_RWM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1442 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
AnnaBridge 171:3a7713b1edbc 1443 /* MCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1444 #define I2S_MCR_MICS_MASK 0x3000000u
AnnaBridge 171:3a7713b1edbc 1445 #define I2S_MCR_MICS_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1446 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
AnnaBridge 171:3a7713b1edbc 1447 #define I2S_MCR_MOE_MASK 0x40000000u
AnnaBridge 171:3a7713b1edbc 1448 #define I2S_MCR_MOE_SHIFT 30
AnnaBridge 171:3a7713b1edbc 1449 #define I2S_MCR_DUF_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 1450 #define I2S_MCR_DUF_SHIFT 31
AnnaBridge 171:3a7713b1edbc 1451 /* MDR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1452 #define I2S_MDR_DIVIDE_MASK 0xFFFu
AnnaBridge 171:3a7713b1edbc 1453 #define I2S_MDR_DIVIDE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1454 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
AnnaBridge 171:3a7713b1edbc 1455 #define I2S_MDR_FRACT_MASK 0xFF000u
AnnaBridge 171:3a7713b1edbc 1456 #define I2S_MDR_FRACT_SHIFT 12
AnnaBridge 171:3a7713b1edbc 1457 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
AnnaBridge 171:3a7713b1edbc 1458
AnnaBridge 171:3a7713b1edbc 1459 /*!
AnnaBridge 171:3a7713b1edbc 1460 * @}
AnnaBridge 171:3a7713b1edbc 1461 */ /* end of group I2S_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1462
AnnaBridge 171:3a7713b1edbc 1463
AnnaBridge 171:3a7713b1edbc 1464 /* I2S - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1465 /** Peripheral I2S0 base address */
AnnaBridge 171:3a7713b1edbc 1466 #define I2S0_BASE (0x4002F000u)
AnnaBridge 171:3a7713b1edbc 1467 /** Peripheral I2S0 base pointer */
AnnaBridge 171:3a7713b1edbc 1468 #define I2S0 ((I2S_Type *)I2S0_BASE)
AnnaBridge 171:3a7713b1edbc 1469 /** Array initializer of I2S peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1470 #define I2S_BASES { I2S0 }
AnnaBridge 171:3a7713b1edbc 1471
AnnaBridge 171:3a7713b1edbc 1472 /*!
AnnaBridge 171:3a7713b1edbc 1473 * @}
AnnaBridge 171:3a7713b1edbc 1474 */ /* end of group I2S_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1475
AnnaBridge 171:3a7713b1edbc 1476
AnnaBridge 171:3a7713b1edbc 1477 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1478 -- LCD Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1479 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1480
AnnaBridge 171:3a7713b1edbc 1481 /*!
AnnaBridge 171:3a7713b1edbc 1482 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1483 * @{
AnnaBridge 171:3a7713b1edbc 1484 */
AnnaBridge 171:3a7713b1edbc 1485
AnnaBridge 171:3a7713b1edbc 1486 /** LCD - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1487 typedef struct {
AnnaBridge 171:3a7713b1edbc 1488 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1489 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1490 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1491 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1492 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1493 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1494 union { /* offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 1495 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1496 __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
AnnaBridge 171:3a7713b1edbc 1497 };
AnnaBridge 171:3a7713b1edbc 1498 } LCD_Type;
AnnaBridge 171:3a7713b1edbc 1499
AnnaBridge 171:3a7713b1edbc 1500 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1501 -- LCD Register Masks
AnnaBridge 171:3a7713b1edbc 1502 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1503
AnnaBridge 171:3a7713b1edbc 1504 /*!
AnnaBridge 171:3a7713b1edbc 1505 * @addtogroup LCD_Register_Masks LCD Register Masks
AnnaBridge 171:3a7713b1edbc 1506 * @{
AnnaBridge 171:3a7713b1edbc 1507 */
AnnaBridge 171:3a7713b1edbc 1508
AnnaBridge 171:3a7713b1edbc 1509 /* GCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1510 #define LCD_GCR_DUTY_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 1511 #define LCD_GCR_DUTY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1512 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
AnnaBridge 171:3a7713b1edbc 1513 #define LCD_GCR_LCLK_MASK 0x38u
AnnaBridge 171:3a7713b1edbc 1514 #define LCD_GCR_LCLK_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1515 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
AnnaBridge 171:3a7713b1edbc 1516 #define LCD_GCR_SOURCE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1517 #define LCD_GCR_SOURCE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1518 #define LCD_GCR_LCDEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1519 #define LCD_GCR_LCDEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1520 #define LCD_GCR_LCDSTP_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 1521 #define LCD_GCR_LCDSTP_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1522 #define LCD_GCR_LCDDOZE_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 1523 #define LCD_GCR_LCDDOZE_SHIFT 9
AnnaBridge 171:3a7713b1edbc 1524 #define LCD_GCR_FFR_MASK 0x400u
AnnaBridge 171:3a7713b1edbc 1525 #define LCD_GCR_FFR_SHIFT 10
AnnaBridge 171:3a7713b1edbc 1526 #define LCD_GCR_ALTSOURCE_MASK 0x800u
AnnaBridge 171:3a7713b1edbc 1527 #define LCD_GCR_ALTSOURCE_SHIFT 11
AnnaBridge 171:3a7713b1edbc 1528 #define LCD_GCR_ALTDIV_MASK 0x3000u
AnnaBridge 171:3a7713b1edbc 1529 #define LCD_GCR_ALTDIV_SHIFT 12
AnnaBridge 171:3a7713b1edbc 1530 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
AnnaBridge 171:3a7713b1edbc 1531 #define LCD_GCR_FDCIEN_MASK 0x4000u
AnnaBridge 171:3a7713b1edbc 1532 #define LCD_GCR_FDCIEN_SHIFT 14
AnnaBridge 171:3a7713b1edbc 1533 #define LCD_GCR_PADSAFE_MASK 0x8000u
AnnaBridge 171:3a7713b1edbc 1534 #define LCD_GCR_PADSAFE_SHIFT 15
AnnaBridge 171:3a7713b1edbc 1535 #define LCD_GCR_VSUPPLY_MASK 0x20000u
AnnaBridge 171:3a7713b1edbc 1536 #define LCD_GCR_VSUPPLY_SHIFT 17
AnnaBridge 171:3a7713b1edbc 1537 #define LCD_GCR_LADJ_MASK 0x300000u
AnnaBridge 171:3a7713b1edbc 1538 #define LCD_GCR_LADJ_SHIFT 20
AnnaBridge 171:3a7713b1edbc 1539 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
AnnaBridge 171:3a7713b1edbc 1540 #define LCD_GCR_CPSEL_MASK 0x800000u
AnnaBridge 171:3a7713b1edbc 1541 #define LCD_GCR_CPSEL_SHIFT 23
AnnaBridge 171:3a7713b1edbc 1542 #define LCD_GCR_RVTRIM_MASK 0xF000000u
AnnaBridge 171:3a7713b1edbc 1543 #define LCD_GCR_RVTRIM_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1544 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 1545 #define LCD_GCR_RVEN_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 1546 #define LCD_GCR_RVEN_SHIFT 31
AnnaBridge 171:3a7713b1edbc 1547 /* AR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1548 #define LCD_AR_BRATE_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 1549 #define LCD_AR_BRATE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1550 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
AnnaBridge 171:3a7713b1edbc 1551 #define LCD_AR_BMODE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1552 #define LCD_AR_BMODE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1553 #define LCD_AR_BLANK_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1554 #define LCD_AR_BLANK_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1555 #define LCD_AR_ALT_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1556 #define LCD_AR_ALT_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1557 #define LCD_AR_BLINK_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1558 #define LCD_AR_BLINK_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1559 /* FDCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1560 #define LCD_FDCR_FDPINID_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 1561 #define LCD_FDCR_FDPINID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1562 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
AnnaBridge 171:3a7713b1edbc 1563 #define LCD_FDCR_FDBPEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1564 #define LCD_FDCR_FDBPEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1565 #define LCD_FDCR_FDEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1566 #define LCD_FDCR_FDEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1567 #define LCD_FDCR_FDSWW_MASK 0xE00u
AnnaBridge 171:3a7713b1edbc 1568 #define LCD_FDCR_FDSWW_SHIFT 9
AnnaBridge 171:3a7713b1edbc 1569 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
AnnaBridge 171:3a7713b1edbc 1570 #define LCD_FDCR_FDPRS_MASK 0x7000u
AnnaBridge 171:3a7713b1edbc 1571 #define LCD_FDCR_FDPRS_SHIFT 12
AnnaBridge 171:3a7713b1edbc 1572 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
AnnaBridge 171:3a7713b1edbc 1573 /* FDSR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1574 #define LCD_FDSR_FDCNT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1575 #define LCD_FDSR_FDCNT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1576 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
AnnaBridge 171:3a7713b1edbc 1577 #define LCD_FDSR_FDCF_MASK 0x8000u
AnnaBridge 171:3a7713b1edbc 1578 #define LCD_FDSR_FDCF_SHIFT 15
AnnaBridge 171:3a7713b1edbc 1579 /* PEN Bit Fields */
AnnaBridge 171:3a7713b1edbc 1580 #define LCD_PEN_PEN_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1581 #define LCD_PEN_PEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1582 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
AnnaBridge 171:3a7713b1edbc 1583 /* BPEN Bit Fields */
AnnaBridge 171:3a7713b1edbc 1584 #define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1585 #define LCD_BPEN_BPEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1586 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
AnnaBridge 171:3a7713b1edbc 1587 /* WF Bit Fields */
AnnaBridge 171:3a7713b1edbc 1588 #define LCD_WF_WF0_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1589 #define LCD_WF_WF0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1590 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
AnnaBridge 171:3a7713b1edbc 1591 #define LCD_WF_WF60_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1592 #define LCD_WF_WF60_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1593 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
AnnaBridge 171:3a7713b1edbc 1594 #define LCD_WF_WF56_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1595 #define LCD_WF_WF56_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1596 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
AnnaBridge 171:3a7713b1edbc 1597 #define LCD_WF_WF52_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1598 #define LCD_WF_WF52_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1599 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
AnnaBridge 171:3a7713b1edbc 1600 #define LCD_WF_WF4_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1601 #define LCD_WF_WF4_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1602 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
AnnaBridge 171:3a7713b1edbc 1603 #define LCD_WF_WF48_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1604 #define LCD_WF_WF48_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1605 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
AnnaBridge 171:3a7713b1edbc 1606 #define LCD_WF_WF44_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1607 #define LCD_WF_WF44_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1608 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
AnnaBridge 171:3a7713b1edbc 1609 #define LCD_WF_WF40_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1610 #define LCD_WF_WF40_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1611 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
AnnaBridge 171:3a7713b1edbc 1612 #define LCD_WF_WF8_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1613 #define LCD_WF_WF8_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1614 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
AnnaBridge 171:3a7713b1edbc 1615 #define LCD_WF_WF36_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1616 #define LCD_WF_WF36_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1617 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
AnnaBridge 171:3a7713b1edbc 1618 #define LCD_WF_WF32_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1619 #define LCD_WF_WF32_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1620 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
AnnaBridge 171:3a7713b1edbc 1621 #define LCD_WF_WF28_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1622 #define LCD_WF_WF28_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1623 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
AnnaBridge 171:3a7713b1edbc 1624 #define LCD_WF_WF12_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1625 #define LCD_WF_WF12_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1626 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
AnnaBridge 171:3a7713b1edbc 1627 #define LCD_WF_WF24_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1628 #define LCD_WF_WF24_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1629 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
AnnaBridge 171:3a7713b1edbc 1630 #define LCD_WF_WF20_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1631 #define LCD_WF_WF20_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1632 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
AnnaBridge 171:3a7713b1edbc 1633 #define LCD_WF_WF16_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1634 #define LCD_WF_WF16_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1635 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
AnnaBridge 171:3a7713b1edbc 1636 #define LCD_WF_WF5_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1637 #define LCD_WF_WF5_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1638 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
AnnaBridge 171:3a7713b1edbc 1639 #define LCD_WF_WF49_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1640 #define LCD_WF_WF49_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1641 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
AnnaBridge 171:3a7713b1edbc 1642 #define LCD_WF_WF45_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1643 #define LCD_WF_WF45_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1644 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
AnnaBridge 171:3a7713b1edbc 1645 #define LCD_WF_WF61_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1646 #define LCD_WF_WF61_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1647 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
AnnaBridge 171:3a7713b1edbc 1648 #define LCD_WF_WF25_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1649 #define LCD_WF_WF25_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1650 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
AnnaBridge 171:3a7713b1edbc 1651 #define LCD_WF_WF17_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1652 #define LCD_WF_WF17_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1653 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
AnnaBridge 171:3a7713b1edbc 1654 #define LCD_WF_WF41_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1655 #define LCD_WF_WF41_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1656 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
AnnaBridge 171:3a7713b1edbc 1657 #define LCD_WF_WF13_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1658 #define LCD_WF_WF13_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1659 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
AnnaBridge 171:3a7713b1edbc 1660 #define LCD_WF_WF57_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1661 #define LCD_WF_WF57_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1662 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
AnnaBridge 171:3a7713b1edbc 1663 #define LCD_WF_WF53_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1664 #define LCD_WF_WF53_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1665 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
AnnaBridge 171:3a7713b1edbc 1666 #define LCD_WF_WF37_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1667 #define LCD_WF_WF37_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1668 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
AnnaBridge 171:3a7713b1edbc 1669 #define LCD_WF_WF9_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1670 #define LCD_WF_WF9_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1671 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
AnnaBridge 171:3a7713b1edbc 1672 #define LCD_WF_WF1_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1673 #define LCD_WF_WF1_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1674 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
AnnaBridge 171:3a7713b1edbc 1675 #define LCD_WF_WF29_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1676 #define LCD_WF_WF29_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1677 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
AnnaBridge 171:3a7713b1edbc 1678 #define LCD_WF_WF33_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1679 #define LCD_WF_WF33_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1680 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
AnnaBridge 171:3a7713b1edbc 1681 #define LCD_WF_WF21_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 1682 #define LCD_WF_WF21_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1683 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
AnnaBridge 171:3a7713b1edbc 1684 #define LCD_WF_WF26_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1685 #define LCD_WF_WF26_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1686 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
AnnaBridge 171:3a7713b1edbc 1687 #define LCD_WF_WF46_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1688 #define LCD_WF_WF46_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1689 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
AnnaBridge 171:3a7713b1edbc 1690 #define LCD_WF_WF6_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1691 #define LCD_WF_WF6_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1692 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
AnnaBridge 171:3a7713b1edbc 1693 #define LCD_WF_WF42_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1694 #define LCD_WF_WF42_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1695 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
AnnaBridge 171:3a7713b1edbc 1696 #define LCD_WF_WF18_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1697 #define LCD_WF_WF18_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1698 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
AnnaBridge 171:3a7713b1edbc 1699 #define LCD_WF_WF38_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1700 #define LCD_WF_WF38_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1701 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
AnnaBridge 171:3a7713b1edbc 1702 #define LCD_WF_WF22_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1703 #define LCD_WF_WF22_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1704 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
AnnaBridge 171:3a7713b1edbc 1705 #define LCD_WF_WF34_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1706 #define LCD_WF_WF34_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1707 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
AnnaBridge 171:3a7713b1edbc 1708 #define LCD_WF_WF50_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1709 #define LCD_WF_WF50_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1710 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
AnnaBridge 171:3a7713b1edbc 1711 #define LCD_WF_WF14_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1712 #define LCD_WF_WF14_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1713 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
AnnaBridge 171:3a7713b1edbc 1714 #define LCD_WF_WF54_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1715 #define LCD_WF_WF54_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1716 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
AnnaBridge 171:3a7713b1edbc 1717 #define LCD_WF_WF2_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1718 #define LCD_WF_WF2_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1719 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
AnnaBridge 171:3a7713b1edbc 1720 #define LCD_WF_WF58_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1721 #define LCD_WF_WF58_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1722 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
AnnaBridge 171:3a7713b1edbc 1723 #define LCD_WF_WF30_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1724 #define LCD_WF_WF30_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1725 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
AnnaBridge 171:3a7713b1edbc 1726 #define LCD_WF_WF62_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1727 #define LCD_WF_WF62_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1728 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
AnnaBridge 171:3a7713b1edbc 1729 #define LCD_WF_WF10_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 1730 #define LCD_WF_WF10_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1731 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
AnnaBridge 171:3a7713b1edbc 1732 #define LCD_WF_WF63_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1733 #define LCD_WF_WF63_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1734 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
AnnaBridge 171:3a7713b1edbc 1735 #define LCD_WF_WF59_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1736 #define LCD_WF_WF59_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1737 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
AnnaBridge 171:3a7713b1edbc 1738 #define LCD_WF_WF55_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1739 #define LCD_WF_WF55_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1740 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
AnnaBridge 171:3a7713b1edbc 1741 #define LCD_WF_WF3_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1742 #define LCD_WF_WF3_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1743 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
AnnaBridge 171:3a7713b1edbc 1744 #define LCD_WF_WF51_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1745 #define LCD_WF_WF51_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1746 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
AnnaBridge 171:3a7713b1edbc 1747 #define LCD_WF_WF47_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1748 #define LCD_WF_WF47_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1749 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
AnnaBridge 171:3a7713b1edbc 1750 #define LCD_WF_WF43_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1751 #define LCD_WF_WF43_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1752 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
AnnaBridge 171:3a7713b1edbc 1753 #define LCD_WF_WF7_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1754 #define LCD_WF_WF7_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1755 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
AnnaBridge 171:3a7713b1edbc 1756 #define LCD_WF_WF39_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1757 #define LCD_WF_WF39_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1758 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
AnnaBridge 171:3a7713b1edbc 1759 #define LCD_WF_WF35_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1760 #define LCD_WF_WF35_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1761 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
AnnaBridge 171:3a7713b1edbc 1762 #define LCD_WF_WF31_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1763 #define LCD_WF_WF31_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1764 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
AnnaBridge 171:3a7713b1edbc 1765 #define LCD_WF_WF11_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1766 #define LCD_WF_WF11_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1767 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
AnnaBridge 171:3a7713b1edbc 1768 #define LCD_WF_WF27_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1769 #define LCD_WF_WF27_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1770 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
AnnaBridge 171:3a7713b1edbc 1771 #define LCD_WF_WF23_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1772 #define LCD_WF_WF23_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1773 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
AnnaBridge 171:3a7713b1edbc 1774 #define LCD_WF_WF19_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1775 #define LCD_WF_WF19_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1776 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
AnnaBridge 171:3a7713b1edbc 1777 #define LCD_WF_WF15_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 1778 #define LCD_WF_WF15_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1779 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
AnnaBridge 171:3a7713b1edbc 1780 /* WF8B Bit Fields */
AnnaBridge 171:3a7713b1edbc 1781 #define LCD_WF8B_BPALCD0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1782 #define LCD_WF8B_BPALCD0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1783 #define LCD_WF8B_BPALCD63_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1784 #define LCD_WF8B_BPALCD63_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1785 #define LCD_WF8B_BPALCD62_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1786 #define LCD_WF8B_BPALCD62_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1787 #define LCD_WF8B_BPALCD61_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1788 #define LCD_WF8B_BPALCD61_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1789 #define LCD_WF8B_BPALCD60_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1790 #define LCD_WF8B_BPALCD60_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1791 #define LCD_WF8B_BPALCD59_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1792 #define LCD_WF8B_BPALCD59_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1793 #define LCD_WF8B_BPALCD58_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1794 #define LCD_WF8B_BPALCD58_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1795 #define LCD_WF8B_BPALCD57_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1796 #define LCD_WF8B_BPALCD57_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1797 #define LCD_WF8B_BPALCD1_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1798 #define LCD_WF8B_BPALCD1_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1799 #define LCD_WF8B_BPALCD56_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1800 #define LCD_WF8B_BPALCD56_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1801 #define LCD_WF8B_BPALCD55_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1802 #define LCD_WF8B_BPALCD55_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1803 #define LCD_WF8B_BPALCD54_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1804 #define LCD_WF8B_BPALCD54_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1805 #define LCD_WF8B_BPALCD53_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1806 #define LCD_WF8B_BPALCD53_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1807 #define LCD_WF8B_BPALCD52_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1808 #define LCD_WF8B_BPALCD52_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1809 #define LCD_WF8B_BPALCD51_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1810 #define LCD_WF8B_BPALCD51_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1811 #define LCD_WF8B_BPALCD50_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1812 #define LCD_WF8B_BPALCD50_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1813 #define LCD_WF8B_BPALCD2_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1814 #define LCD_WF8B_BPALCD2_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1815 #define LCD_WF8B_BPALCD49_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1816 #define LCD_WF8B_BPALCD49_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1817 #define LCD_WF8B_BPALCD48_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1818 #define LCD_WF8B_BPALCD48_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1819 #define LCD_WF8B_BPALCD47_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1820 #define LCD_WF8B_BPALCD47_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1821 #define LCD_WF8B_BPALCD46_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1822 #define LCD_WF8B_BPALCD46_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1823 #define LCD_WF8B_BPALCD45_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1824 #define LCD_WF8B_BPALCD45_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1825 #define LCD_WF8B_BPALCD44_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1826 #define LCD_WF8B_BPALCD44_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1827 #define LCD_WF8B_BPALCD43_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1828 #define LCD_WF8B_BPALCD43_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1829 #define LCD_WF8B_BPALCD3_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1830 #define LCD_WF8B_BPALCD3_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1831 #define LCD_WF8B_BPALCD42_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1832 #define LCD_WF8B_BPALCD42_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1833 #define LCD_WF8B_BPALCD41_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1834 #define LCD_WF8B_BPALCD41_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1835 #define LCD_WF8B_BPALCD40_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1836 #define LCD_WF8B_BPALCD40_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1837 #define LCD_WF8B_BPALCD39_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1838 #define LCD_WF8B_BPALCD39_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1839 #define LCD_WF8B_BPALCD38_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1840 #define LCD_WF8B_BPALCD38_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1841 #define LCD_WF8B_BPALCD37_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1842 #define LCD_WF8B_BPALCD37_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1843 #define LCD_WF8B_BPALCD36_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1844 #define LCD_WF8B_BPALCD36_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1845 #define LCD_WF8B_BPALCD4_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1846 #define LCD_WF8B_BPALCD4_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1847 #define LCD_WF8B_BPALCD35_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1848 #define LCD_WF8B_BPALCD35_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1849 #define LCD_WF8B_BPALCD34_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1850 #define LCD_WF8B_BPALCD34_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1851 #define LCD_WF8B_BPALCD33_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1852 #define LCD_WF8B_BPALCD33_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1853 #define LCD_WF8B_BPALCD32_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1854 #define LCD_WF8B_BPALCD32_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1855 #define LCD_WF8B_BPALCD31_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1856 #define LCD_WF8B_BPALCD31_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1857 #define LCD_WF8B_BPALCD30_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1858 #define LCD_WF8B_BPALCD30_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1859 #define LCD_WF8B_BPALCD29_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1860 #define LCD_WF8B_BPALCD29_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1861 #define LCD_WF8B_BPALCD5_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1862 #define LCD_WF8B_BPALCD5_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1863 #define LCD_WF8B_BPALCD28_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1864 #define LCD_WF8B_BPALCD28_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1865 #define LCD_WF8B_BPALCD27_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1866 #define LCD_WF8B_BPALCD27_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1867 #define LCD_WF8B_BPALCD26_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1868 #define LCD_WF8B_BPALCD26_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1869 #define LCD_WF8B_BPALCD25_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1870 #define LCD_WF8B_BPALCD25_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1871 #define LCD_WF8B_BPALCD24_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1872 #define LCD_WF8B_BPALCD24_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1873 #define LCD_WF8B_BPALCD23_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1874 #define LCD_WF8B_BPALCD23_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1875 #define LCD_WF8B_BPALCD22_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1876 #define LCD_WF8B_BPALCD22_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1877 #define LCD_WF8B_BPALCD6_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1878 #define LCD_WF8B_BPALCD6_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1879 #define LCD_WF8B_BPALCD21_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1880 #define LCD_WF8B_BPALCD21_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1881 #define LCD_WF8B_BPALCD20_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1882 #define LCD_WF8B_BPALCD20_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1883 #define LCD_WF8B_BPALCD19_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1884 #define LCD_WF8B_BPALCD19_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1885 #define LCD_WF8B_BPALCD18_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1886 #define LCD_WF8B_BPALCD18_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1887 #define LCD_WF8B_BPALCD17_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1888 #define LCD_WF8B_BPALCD17_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1889 #define LCD_WF8B_BPALCD16_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1890 #define LCD_WF8B_BPALCD16_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1891 #define LCD_WF8B_BPALCD15_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1892 #define LCD_WF8B_BPALCD15_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1893 #define LCD_WF8B_BPALCD7_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1894 #define LCD_WF8B_BPALCD7_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1895 #define LCD_WF8B_BPALCD14_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1896 #define LCD_WF8B_BPALCD14_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1897 #define LCD_WF8B_BPALCD13_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1898 #define LCD_WF8B_BPALCD13_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1899 #define LCD_WF8B_BPALCD12_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1900 #define LCD_WF8B_BPALCD12_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1901 #define LCD_WF8B_BPALCD11_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1902 #define LCD_WF8B_BPALCD11_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1903 #define LCD_WF8B_BPALCD10_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1904 #define LCD_WF8B_BPALCD10_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1905 #define LCD_WF8B_BPALCD9_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1906 #define LCD_WF8B_BPALCD9_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1907 #define LCD_WF8B_BPALCD8_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1908 #define LCD_WF8B_BPALCD8_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1909 #define LCD_WF8B_BPBLCD1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1910 #define LCD_WF8B_BPBLCD1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1911 #define LCD_WF8B_BPBLCD32_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1912 #define LCD_WF8B_BPBLCD32_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1913 #define LCD_WF8B_BPBLCD30_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1914 #define LCD_WF8B_BPBLCD30_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1915 #define LCD_WF8B_BPBLCD60_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1916 #define LCD_WF8B_BPBLCD60_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1917 #define LCD_WF8B_BPBLCD24_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1918 #define LCD_WF8B_BPBLCD24_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1919 #define LCD_WF8B_BPBLCD28_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1920 #define LCD_WF8B_BPBLCD28_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1921 #define LCD_WF8B_BPBLCD23_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1922 #define LCD_WF8B_BPBLCD23_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1923 #define LCD_WF8B_BPBLCD48_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1924 #define LCD_WF8B_BPBLCD48_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1925 #define LCD_WF8B_BPBLCD10_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1926 #define LCD_WF8B_BPBLCD10_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1927 #define LCD_WF8B_BPBLCD15_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1928 #define LCD_WF8B_BPBLCD15_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1929 #define LCD_WF8B_BPBLCD36_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1930 #define LCD_WF8B_BPBLCD36_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1931 #define LCD_WF8B_BPBLCD44_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1932 #define LCD_WF8B_BPBLCD44_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1933 #define LCD_WF8B_BPBLCD62_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1934 #define LCD_WF8B_BPBLCD62_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1935 #define LCD_WF8B_BPBLCD53_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1936 #define LCD_WF8B_BPBLCD53_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1937 #define LCD_WF8B_BPBLCD22_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1938 #define LCD_WF8B_BPBLCD22_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1939 #define LCD_WF8B_BPBLCD47_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1940 #define LCD_WF8B_BPBLCD47_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1941 #define LCD_WF8B_BPBLCD33_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1942 #define LCD_WF8B_BPBLCD33_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1943 #define LCD_WF8B_BPBLCD2_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1944 #define LCD_WF8B_BPBLCD2_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1945 #define LCD_WF8B_BPBLCD49_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1946 #define LCD_WF8B_BPBLCD49_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1947 #define LCD_WF8B_BPBLCD0_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1948 #define LCD_WF8B_BPBLCD0_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1949 #define LCD_WF8B_BPBLCD55_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1950 #define LCD_WF8B_BPBLCD55_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1951 #define LCD_WF8B_BPBLCD56_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1952 #define LCD_WF8B_BPBLCD56_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1953 #define LCD_WF8B_BPBLCD21_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1954 #define LCD_WF8B_BPBLCD21_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1955 #define LCD_WF8B_BPBLCD6_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1956 #define LCD_WF8B_BPBLCD6_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1957 #define LCD_WF8B_BPBLCD29_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1958 #define LCD_WF8B_BPBLCD29_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1959 #define LCD_WF8B_BPBLCD25_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1960 #define LCD_WF8B_BPBLCD25_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1961 #define LCD_WF8B_BPBLCD8_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1962 #define LCD_WF8B_BPBLCD8_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1963 #define LCD_WF8B_BPBLCD54_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1964 #define LCD_WF8B_BPBLCD54_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1965 #define LCD_WF8B_BPBLCD38_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1966 #define LCD_WF8B_BPBLCD38_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1967 #define LCD_WF8B_BPBLCD43_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1968 #define LCD_WF8B_BPBLCD43_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1969 #define LCD_WF8B_BPBLCD20_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1970 #define LCD_WF8B_BPBLCD20_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1971 #define LCD_WF8B_BPBLCD9_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1972 #define LCD_WF8B_BPBLCD9_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1973 #define LCD_WF8B_BPBLCD7_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1974 #define LCD_WF8B_BPBLCD7_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1975 #define LCD_WF8B_BPBLCD50_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1976 #define LCD_WF8B_BPBLCD50_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1977 #define LCD_WF8B_BPBLCD40_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1978 #define LCD_WF8B_BPBLCD40_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1979 #define LCD_WF8B_BPBLCD63_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1980 #define LCD_WF8B_BPBLCD63_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1981 #define LCD_WF8B_BPBLCD26_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1982 #define LCD_WF8B_BPBLCD26_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1983 #define LCD_WF8B_BPBLCD12_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1984 #define LCD_WF8B_BPBLCD12_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1985 #define LCD_WF8B_BPBLCD19_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1986 #define LCD_WF8B_BPBLCD19_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1987 #define LCD_WF8B_BPBLCD34_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1988 #define LCD_WF8B_BPBLCD34_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1989 #define LCD_WF8B_BPBLCD39_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1990 #define LCD_WF8B_BPBLCD39_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1991 #define LCD_WF8B_BPBLCD59_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1992 #define LCD_WF8B_BPBLCD59_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1993 #define LCD_WF8B_BPBLCD61_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1994 #define LCD_WF8B_BPBLCD61_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1995 #define LCD_WF8B_BPBLCD37_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1996 #define LCD_WF8B_BPBLCD37_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1997 #define LCD_WF8B_BPBLCD31_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1998 #define LCD_WF8B_BPBLCD31_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1999 #define LCD_WF8B_BPBLCD58_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2000 #define LCD_WF8B_BPBLCD58_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2001 #define LCD_WF8B_BPBLCD18_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2002 #define LCD_WF8B_BPBLCD18_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2003 #define LCD_WF8B_BPBLCD45_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2004 #define LCD_WF8B_BPBLCD45_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2005 #define LCD_WF8B_BPBLCD27_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2006 #define LCD_WF8B_BPBLCD27_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2007 #define LCD_WF8B_BPBLCD14_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2008 #define LCD_WF8B_BPBLCD14_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2009 #define LCD_WF8B_BPBLCD51_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2010 #define LCD_WF8B_BPBLCD51_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2011 #define LCD_WF8B_BPBLCD52_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2012 #define LCD_WF8B_BPBLCD52_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2013 #define LCD_WF8B_BPBLCD4_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2014 #define LCD_WF8B_BPBLCD4_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2015 #define LCD_WF8B_BPBLCD35_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2016 #define LCD_WF8B_BPBLCD35_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2017 #define LCD_WF8B_BPBLCD17_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2018 #define LCD_WF8B_BPBLCD17_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2019 #define LCD_WF8B_BPBLCD41_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2020 #define LCD_WF8B_BPBLCD41_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2021 #define LCD_WF8B_BPBLCD11_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2022 #define LCD_WF8B_BPBLCD11_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2023 #define LCD_WF8B_BPBLCD46_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2024 #define LCD_WF8B_BPBLCD46_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2025 #define LCD_WF8B_BPBLCD57_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2026 #define LCD_WF8B_BPBLCD57_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2027 #define LCD_WF8B_BPBLCD42_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2028 #define LCD_WF8B_BPBLCD42_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2029 #define LCD_WF8B_BPBLCD5_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2030 #define LCD_WF8B_BPBLCD5_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2031 #define LCD_WF8B_BPBLCD3_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2032 #define LCD_WF8B_BPBLCD3_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2033 #define LCD_WF8B_BPBLCD16_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2034 #define LCD_WF8B_BPBLCD16_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2035 #define LCD_WF8B_BPBLCD13_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2036 #define LCD_WF8B_BPBLCD13_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2037 #define LCD_WF8B_BPCLCD10_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2038 #define LCD_WF8B_BPCLCD10_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2039 #define LCD_WF8B_BPCLCD55_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2040 #define LCD_WF8B_BPCLCD55_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2041 #define LCD_WF8B_BPCLCD2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2042 #define LCD_WF8B_BPCLCD2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2043 #define LCD_WF8B_BPCLCD23_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2044 #define LCD_WF8B_BPCLCD23_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2045 #define LCD_WF8B_BPCLCD48_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2046 #define LCD_WF8B_BPCLCD48_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2047 #define LCD_WF8B_BPCLCD24_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2048 #define LCD_WF8B_BPCLCD24_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2049 #define LCD_WF8B_BPCLCD60_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2050 #define LCD_WF8B_BPCLCD60_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2051 #define LCD_WF8B_BPCLCD47_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2052 #define LCD_WF8B_BPCLCD47_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2053 #define LCD_WF8B_BPCLCD22_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2054 #define LCD_WF8B_BPCLCD22_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2055 #define LCD_WF8B_BPCLCD8_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2056 #define LCD_WF8B_BPCLCD8_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2057 #define LCD_WF8B_BPCLCD21_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2058 #define LCD_WF8B_BPCLCD21_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2059 #define LCD_WF8B_BPCLCD49_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2060 #define LCD_WF8B_BPCLCD49_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2061 #define LCD_WF8B_BPCLCD25_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2062 #define LCD_WF8B_BPCLCD25_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2063 #define LCD_WF8B_BPCLCD1_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2064 #define LCD_WF8B_BPCLCD1_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2065 #define LCD_WF8B_BPCLCD20_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2066 #define LCD_WF8B_BPCLCD20_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2067 #define LCD_WF8B_BPCLCD50_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2068 #define LCD_WF8B_BPCLCD50_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2069 #define LCD_WF8B_BPCLCD19_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2070 #define LCD_WF8B_BPCLCD19_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2071 #define LCD_WF8B_BPCLCD26_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2072 #define LCD_WF8B_BPCLCD26_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2073 #define LCD_WF8B_BPCLCD59_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2074 #define LCD_WF8B_BPCLCD59_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2075 #define LCD_WF8B_BPCLCD61_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2076 #define LCD_WF8B_BPCLCD61_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2077 #define LCD_WF8B_BPCLCD46_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2078 #define LCD_WF8B_BPCLCD46_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2079 #define LCD_WF8B_BPCLCD18_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2080 #define LCD_WF8B_BPCLCD18_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2081 #define LCD_WF8B_BPCLCD5_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2082 #define LCD_WF8B_BPCLCD5_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2083 #define LCD_WF8B_BPCLCD63_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2084 #define LCD_WF8B_BPCLCD63_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2085 #define LCD_WF8B_BPCLCD27_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2086 #define LCD_WF8B_BPCLCD27_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2087 #define LCD_WF8B_BPCLCD17_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2088 #define LCD_WF8B_BPCLCD17_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2089 #define LCD_WF8B_BPCLCD51_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2090 #define LCD_WF8B_BPCLCD51_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2091 #define LCD_WF8B_BPCLCD9_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2092 #define LCD_WF8B_BPCLCD9_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2093 #define LCD_WF8B_BPCLCD54_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2094 #define LCD_WF8B_BPCLCD54_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2095 #define LCD_WF8B_BPCLCD15_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2096 #define LCD_WF8B_BPCLCD15_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2097 #define LCD_WF8B_BPCLCD16_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2098 #define LCD_WF8B_BPCLCD16_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2099 #define LCD_WF8B_BPCLCD14_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2100 #define LCD_WF8B_BPCLCD14_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2101 #define LCD_WF8B_BPCLCD32_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2102 #define LCD_WF8B_BPCLCD32_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2103 #define LCD_WF8B_BPCLCD28_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2104 #define LCD_WF8B_BPCLCD28_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2105 #define LCD_WF8B_BPCLCD53_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2106 #define LCD_WF8B_BPCLCD53_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2107 #define LCD_WF8B_BPCLCD33_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2108 #define LCD_WF8B_BPCLCD33_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2109 #define LCD_WF8B_BPCLCD0_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2110 #define LCD_WF8B_BPCLCD0_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2111 #define LCD_WF8B_BPCLCD43_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2112 #define LCD_WF8B_BPCLCD43_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2113 #define LCD_WF8B_BPCLCD7_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2114 #define LCD_WF8B_BPCLCD7_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2115 #define LCD_WF8B_BPCLCD4_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2116 #define LCD_WF8B_BPCLCD4_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2117 #define LCD_WF8B_BPCLCD34_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2118 #define LCD_WF8B_BPCLCD34_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2119 #define LCD_WF8B_BPCLCD29_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2120 #define LCD_WF8B_BPCLCD29_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2121 #define LCD_WF8B_BPCLCD45_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2122 #define LCD_WF8B_BPCLCD45_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2123 #define LCD_WF8B_BPCLCD57_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2124 #define LCD_WF8B_BPCLCD57_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2125 #define LCD_WF8B_BPCLCD42_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2126 #define LCD_WF8B_BPCLCD42_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2127 #define LCD_WF8B_BPCLCD35_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2128 #define LCD_WF8B_BPCLCD35_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2129 #define LCD_WF8B_BPCLCD13_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2130 #define LCD_WF8B_BPCLCD13_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2131 #define LCD_WF8B_BPCLCD36_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2132 #define LCD_WF8B_BPCLCD36_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2133 #define LCD_WF8B_BPCLCD30_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2134 #define LCD_WF8B_BPCLCD30_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2135 #define LCD_WF8B_BPCLCD52_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2136 #define LCD_WF8B_BPCLCD52_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2137 #define LCD_WF8B_BPCLCD58_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2138 #define LCD_WF8B_BPCLCD58_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2139 #define LCD_WF8B_BPCLCD41_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2140 #define LCD_WF8B_BPCLCD41_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2141 #define LCD_WF8B_BPCLCD37_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2142 #define LCD_WF8B_BPCLCD37_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2143 #define LCD_WF8B_BPCLCD3_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2144 #define LCD_WF8B_BPCLCD3_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2145 #define LCD_WF8B_BPCLCD12_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2146 #define LCD_WF8B_BPCLCD12_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2147 #define LCD_WF8B_BPCLCD11_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2148 #define LCD_WF8B_BPCLCD11_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2149 #define LCD_WF8B_BPCLCD38_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2150 #define LCD_WF8B_BPCLCD38_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2151 #define LCD_WF8B_BPCLCD44_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2152 #define LCD_WF8B_BPCLCD44_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2153 #define LCD_WF8B_BPCLCD31_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2154 #define LCD_WF8B_BPCLCD31_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2155 #define LCD_WF8B_BPCLCD40_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2156 #define LCD_WF8B_BPCLCD40_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2157 #define LCD_WF8B_BPCLCD62_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2158 #define LCD_WF8B_BPCLCD62_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2159 #define LCD_WF8B_BPCLCD56_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2160 #define LCD_WF8B_BPCLCD56_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2161 #define LCD_WF8B_BPCLCD39_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2162 #define LCD_WF8B_BPCLCD39_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2163 #define LCD_WF8B_BPCLCD6_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2164 #define LCD_WF8B_BPCLCD6_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2165 #define LCD_WF8B_BPDLCD47_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2166 #define LCD_WF8B_BPDLCD47_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2167 #define LCD_WF8B_BPDLCD23_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2168 #define LCD_WF8B_BPDLCD23_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2169 #define LCD_WF8B_BPDLCD48_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2170 #define LCD_WF8B_BPDLCD48_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2171 #define LCD_WF8B_BPDLCD24_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2172 #define LCD_WF8B_BPDLCD24_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2173 #define LCD_WF8B_BPDLCD15_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2174 #define LCD_WF8B_BPDLCD15_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2175 #define LCD_WF8B_BPDLCD22_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2176 #define LCD_WF8B_BPDLCD22_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2177 #define LCD_WF8B_BPDLCD60_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2178 #define LCD_WF8B_BPDLCD60_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2179 #define LCD_WF8B_BPDLCD10_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2180 #define LCD_WF8B_BPDLCD10_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2181 #define LCD_WF8B_BPDLCD21_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2182 #define LCD_WF8B_BPDLCD21_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2183 #define LCD_WF8B_BPDLCD49_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2184 #define LCD_WF8B_BPDLCD49_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2185 #define LCD_WF8B_BPDLCD1_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2186 #define LCD_WF8B_BPDLCD1_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2187 #define LCD_WF8B_BPDLCD25_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2188 #define LCD_WF8B_BPDLCD25_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2189 #define LCD_WF8B_BPDLCD20_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2190 #define LCD_WF8B_BPDLCD20_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2191 #define LCD_WF8B_BPDLCD2_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2192 #define LCD_WF8B_BPDLCD2_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2193 #define LCD_WF8B_BPDLCD55_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2194 #define LCD_WF8B_BPDLCD55_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2195 #define LCD_WF8B_BPDLCD59_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2196 #define LCD_WF8B_BPDLCD59_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2197 #define LCD_WF8B_BPDLCD5_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2198 #define LCD_WF8B_BPDLCD5_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2199 #define LCD_WF8B_BPDLCD19_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2200 #define LCD_WF8B_BPDLCD19_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2201 #define LCD_WF8B_BPDLCD6_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2202 #define LCD_WF8B_BPDLCD6_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2203 #define LCD_WF8B_BPDLCD26_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2204 #define LCD_WF8B_BPDLCD26_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2205 #define LCD_WF8B_BPDLCD0_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2206 #define LCD_WF8B_BPDLCD0_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2207 #define LCD_WF8B_BPDLCD50_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2208 #define LCD_WF8B_BPDLCD50_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2209 #define LCD_WF8B_BPDLCD46_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2210 #define LCD_WF8B_BPDLCD46_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2211 #define LCD_WF8B_BPDLCD18_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2212 #define LCD_WF8B_BPDLCD18_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2213 #define LCD_WF8B_BPDLCD61_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2214 #define LCD_WF8B_BPDLCD61_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2215 #define LCD_WF8B_BPDLCD9_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2216 #define LCD_WF8B_BPDLCD9_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2217 #define LCD_WF8B_BPDLCD17_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2218 #define LCD_WF8B_BPDLCD17_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2219 #define LCD_WF8B_BPDLCD27_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2220 #define LCD_WF8B_BPDLCD27_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2221 #define LCD_WF8B_BPDLCD53_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2222 #define LCD_WF8B_BPDLCD53_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2223 #define LCD_WF8B_BPDLCD51_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2224 #define LCD_WF8B_BPDLCD51_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2225 #define LCD_WF8B_BPDLCD54_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2226 #define LCD_WF8B_BPDLCD54_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2227 #define LCD_WF8B_BPDLCD13_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2228 #define LCD_WF8B_BPDLCD13_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2229 #define LCD_WF8B_BPDLCD16_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2230 #define LCD_WF8B_BPDLCD16_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2231 #define LCD_WF8B_BPDLCD32_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2232 #define LCD_WF8B_BPDLCD32_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2233 #define LCD_WF8B_BPDLCD14_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2234 #define LCD_WF8B_BPDLCD14_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2235 #define LCD_WF8B_BPDLCD28_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2236 #define LCD_WF8B_BPDLCD28_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2237 #define LCD_WF8B_BPDLCD43_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2238 #define LCD_WF8B_BPDLCD43_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2239 #define LCD_WF8B_BPDLCD4_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2240 #define LCD_WF8B_BPDLCD4_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2241 #define LCD_WF8B_BPDLCD45_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2242 #define LCD_WF8B_BPDLCD45_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2243 #define LCD_WF8B_BPDLCD8_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2244 #define LCD_WF8B_BPDLCD8_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2245 #define LCD_WF8B_BPDLCD62_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2246 #define LCD_WF8B_BPDLCD62_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2247 #define LCD_WF8B_BPDLCD33_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2248 #define LCD_WF8B_BPDLCD33_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2249 #define LCD_WF8B_BPDLCD34_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2250 #define LCD_WF8B_BPDLCD34_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2251 #define LCD_WF8B_BPDLCD29_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2252 #define LCD_WF8B_BPDLCD29_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2253 #define LCD_WF8B_BPDLCD58_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2254 #define LCD_WF8B_BPDLCD58_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2255 #define LCD_WF8B_BPDLCD57_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2256 #define LCD_WF8B_BPDLCD57_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2257 #define LCD_WF8B_BPDLCD42_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2258 #define LCD_WF8B_BPDLCD42_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2259 #define LCD_WF8B_BPDLCD35_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2260 #define LCD_WF8B_BPDLCD35_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2261 #define LCD_WF8B_BPDLCD52_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2262 #define LCD_WF8B_BPDLCD52_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2263 #define LCD_WF8B_BPDLCD7_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2264 #define LCD_WF8B_BPDLCD7_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2265 #define LCD_WF8B_BPDLCD36_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2266 #define LCD_WF8B_BPDLCD36_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2267 #define LCD_WF8B_BPDLCD30_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2268 #define LCD_WF8B_BPDLCD30_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2269 #define LCD_WF8B_BPDLCD41_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2270 #define LCD_WF8B_BPDLCD41_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2271 #define LCD_WF8B_BPDLCD37_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2272 #define LCD_WF8B_BPDLCD37_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2273 #define LCD_WF8B_BPDLCD44_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2274 #define LCD_WF8B_BPDLCD44_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2275 #define LCD_WF8B_BPDLCD63_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2276 #define LCD_WF8B_BPDLCD63_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2277 #define LCD_WF8B_BPDLCD38_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2278 #define LCD_WF8B_BPDLCD38_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2279 #define LCD_WF8B_BPDLCD56_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2280 #define LCD_WF8B_BPDLCD56_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2281 #define LCD_WF8B_BPDLCD40_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2282 #define LCD_WF8B_BPDLCD40_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2283 #define LCD_WF8B_BPDLCD31_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2284 #define LCD_WF8B_BPDLCD31_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2285 #define LCD_WF8B_BPDLCD12_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2286 #define LCD_WF8B_BPDLCD12_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2287 #define LCD_WF8B_BPDLCD39_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2288 #define LCD_WF8B_BPDLCD39_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2289 #define LCD_WF8B_BPDLCD3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2290 #define LCD_WF8B_BPDLCD3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2291 #define LCD_WF8B_BPDLCD11_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2292 #define LCD_WF8B_BPDLCD11_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2293 #define LCD_WF8B_BPELCD12_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2294 #define LCD_WF8B_BPELCD12_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2295 #define LCD_WF8B_BPELCD39_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2296 #define LCD_WF8B_BPELCD39_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2297 #define LCD_WF8B_BPELCD3_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2298 #define LCD_WF8B_BPELCD3_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2299 #define LCD_WF8B_BPELCD38_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2300 #define LCD_WF8B_BPELCD38_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2301 #define LCD_WF8B_BPELCD40_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2302 #define LCD_WF8B_BPELCD40_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2303 #define LCD_WF8B_BPELCD37_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2304 #define LCD_WF8B_BPELCD37_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2305 #define LCD_WF8B_BPELCD41_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2306 #define LCD_WF8B_BPELCD41_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2307 #define LCD_WF8B_BPELCD36_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2308 #define LCD_WF8B_BPELCD36_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2309 #define LCD_WF8B_BPELCD8_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2310 #define LCD_WF8B_BPELCD8_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2311 #define LCD_WF8B_BPELCD35_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2312 #define LCD_WF8B_BPELCD35_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2313 #define LCD_WF8B_BPELCD42_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2314 #define LCD_WF8B_BPELCD42_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2315 #define LCD_WF8B_BPELCD34_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2316 #define LCD_WF8B_BPELCD34_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2317 #define LCD_WF8B_BPELCD33_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2318 #define LCD_WF8B_BPELCD33_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2319 #define LCD_WF8B_BPELCD11_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2320 #define LCD_WF8B_BPELCD11_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2321 #define LCD_WF8B_BPELCD43_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2322 #define LCD_WF8B_BPELCD43_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2323 #define LCD_WF8B_BPELCD32_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2324 #define LCD_WF8B_BPELCD32_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2325 #define LCD_WF8B_BPELCD31_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2326 #define LCD_WF8B_BPELCD31_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2327 #define LCD_WF8B_BPELCD44_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2328 #define LCD_WF8B_BPELCD44_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2329 #define LCD_WF8B_BPELCD30_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2330 #define LCD_WF8B_BPELCD30_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2331 #define LCD_WF8B_BPELCD29_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2332 #define LCD_WF8B_BPELCD29_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2333 #define LCD_WF8B_BPELCD7_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2334 #define LCD_WF8B_BPELCD7_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2335 #define LCD_WF8B_BPELCD45_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2336 #define LCD_WF8B_BPELCD45_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2337 #define LCD_WF8B_BPELCD28_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2338 #define LCD_WF8B_BPELCD28_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2339 #define LCD_WF8B_BPELCD2_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2340 #define LCD_WF8B_BPELCD2_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2341 #define LCD_WF8B_BPELCD27_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2342 #define LCD_WF8B_BPELCD27_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2343 #define LCD_WF8B_BPELCD46_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2344 #define LCD_WF8B_BPELCD46_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2345 #define LCD_WF8B_BPELCD26_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2346 #define LCD_WF8B_BPELCD26_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2347 #define LCD_WF8B_BPELCD10_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2348 #define LCD_WF8B_BPELCD10_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2349 #define LCD_WF8B_BPELCD13_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2350 #define LCD_WF8B_BPELCD13_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2351 #define LCD_WF8B_BPELCD25_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2352 #define LCD_WF8B_BPELCD25_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2353 #define LCD_WF8B_BPELCD5_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2354 #define LCD_WF8B_BPELCD5_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2355 #define LCD_WF8B_BPELCD24_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2356 #define LCD_WF8B_BPELCD24_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2357 #define LCD_WF8B_BPELCD47_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2358 #define LCD_WF8B_BPELCD47_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2359 #define LCD_WF8B_BPELCD23_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2360 #define LCD_WF8B_BPELCD23_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2361 #define LCD_WF8B_BPELCD22_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2362 #define LCD_WF8B_BPELCD22_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2363 #define LCD_WF8B_BPELCD48_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2364 #define LCD_WF8B_BPELCD48_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2365 #define LCD_WF8B_BPELCD21_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2366 #define LCD_WF8B_BPELCD21_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2367 #define LCD_WF8B_BPELCD49_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2368 #define LCD_WF8B_BPELCD49_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2369 #define LCD_WF8B_BPELCD20_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2370 #define LCD_WF8B_BPELCD20_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2371 #define LCD_WF8B_BPELCD19_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2372 #define LCD_WF8B_BPELCD19_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2373 #define LCD_WF8B_BPELCD9_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2374 #define LCD_WF8B_BPELCD9_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2375 #define LCD_WF8B_BPELCD50_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2376 #define LCD_WF8B_BPELCD50_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2377 #define LCD_WF8B_BPELCD18_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2378 #define LCD_WF8B_BPELCD18_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2379 #define LCD_WF8B_BPELCD6_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2380 #define LCD_WF8B_BPELCD6_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2381 #define LCD_WF8B_BPELCD17_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2382 #define LCD_WF8B_BPELCD17_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2383 #define LCD_WF8B_BPELCD51_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2384 #define LCD_WF8B_BPELCD51_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2385 #define LCD_WF8B_BPELCD16_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2386 #define LCD_WF8B_BPELCD16_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2387 #define LCD_WF8B_BPELCD56_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2388 #define LCD_WF8B_BPELCD56_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2389 #define LCD_WF8B_BPELCD57_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2390 #define LCD_WF8B_BPELCD57_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2391 #define LCD_WF8B_BPELCD52_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2392 #define LCD_WF8B_BPELCD52_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2393 #define LCD_WF8B_BPELCD1_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2394 #define LCD_WF8B_BPELCD1_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2395 #define LCD_WF8B_BPELCD58_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2396 #define LCD_WF8B_BPELCD58_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2397 #define LCD_WF8B_BPELCD59_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2398 #define LCD_WF8B_BPELCD59_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2399 #define LCD_WF8B_BPELCD53_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2400 #define LCD_WF8B_BPELCD53_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2401 #define LCD_WF8B_BPELCD14_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2402 #define LCD_WF8B_BPELCD14_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2403 #define LCD_WF8B_BPELCD0_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2404 #define LCD_WF8B_BPELCD0_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2405 #define LCD_WF8B_BPELCD60_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2406 #define LCD_WF8B_BPELCD60_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2407 #define LCD_WF8B_BPELCD15_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2408 #define LCD_WF8B_BPELCD15_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2409 #define LCD_WF8B_BPELCD61_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2410 #define LCD_WF8B_BPELCD61_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2411 #define LCD_WF8B_BPELCD54_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2412 #define LCD_WF8B_BPELCD54_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2413 #define LCD_WF8B_BPELCD62_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2414 #define LCD_WF8B_BPELCD62_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2415 #define LCD_WF8B_BPELCD63_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2416 #define LCD_WF8B_BPELCD63_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2417 #define LCD_WF8B_BPELCD55_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2418 #define LCD_WF8B_BPELCD55_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2419 #define LCD_WF8B_BPELCD4_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2420 #define LCD_WF8B_BPELCD4_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2421 #define LCD_WF8B_BPFLCD13_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2422 #define LCD_WF8B_BPFLCD13_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2423 #define LCD_WF8B_BPFLCD39_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2424 #define LCD_WF8B_BPFLCD39_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2425 #define LCD_WF8B_BPFLCD55_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2426 #define LCD_WF8B_BPFLCD55_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2427 #define LCD_WF8B_BPFLCD47_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2428 #define LCD_WF8B_BPFLCD47_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2429 #define LCD_WF8B_BPFLCD63_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2430 #define LCD_WF8B_BPFLCD63_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2431 #define LCD_WF8B_BPFLCD43_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2432 #define LCD_WF8B_BPFLCD43_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2433 #define LCD_WF8B_BPFLCD5_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2434 #define LCD_WF8B_BPFLCD5_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2435 #define LCD_WF8B_BPFLCD62_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2436 #define LCD_WF8B_BPFLCD62_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2437 #define LCD_WF8B_BPFLCD14_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2438 #define LCD_WF8B_BPFLCD14_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2439 #define LCD_WF8B_BPFLCD24_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2440 #define LCD_WF8B_BPFLCD24_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2441 #define LCD_WF8B_BPFLCD54_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2442 #define LCD_WF8B_BPFLCD54_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2443 #define LCD_WF8B_BPFLCD15_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2444 #define LCD_WF8B_BPFLCD15_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2445 #define LCD_WF8B_BPFLCD32_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2446 #define LCD_WF8B_BPFLCD32_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2447 #define LCD_WF8B_BPFLCD61_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2448 #define LCD_WF8B_BPFLCD61_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2449 #define LCD_WF8B_BPFLCD25_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2450 #define LCD_WF8B_BPFLCD25_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2451 #define LCD_WF8B_BPFLCD60_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2452 #define LCD_WF8B_BPFLCD60_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2453 #define LCD_WF8B_BPFLCD41_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2454 #define LCD_WF8B_BPFLCD41_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2455 #define LCD_WF8B_BPFLCD33_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2456 #define LCD_WF8B_BPFLCD33_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2457 #define LCD_WF8B_BPFLCD53_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2458 #define LCD_WF8B_BPFLCD53_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2459 #define LCD_WF8B_BPFLCD59_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2460 #define LCD_WF8B_BPFLCD59_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2461 #define LCD_WF8B_BPFLCD0_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2462 #define LCD_WF8B_BPFLCD0_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2463 #define LCD_WF8B_BPFLCD46_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2464 #define LCD_WF8B_BPFLCD46_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2465 #define LCD_WF8B_BPFLCD58_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2466 #define LCD_WF8B_BPFLCD58_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2467 #define LCD_WF8B_BPFLCD26_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2468 #define LCD_WF8B_BPFLCD26_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2469 #define LCD_WF8B_BPFLCD36_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2470 #define LCD_WF8B_BPFLCD36_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2471 #define LCD_WF8B_BPFLCD10_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2472 #define LCD_WF8B_BPFLCD10_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2473 #define LCD_WF8B_BPFLCD52_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2474 #define LCD_WF8B_BPFLCD52_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2475 #define LCD_WF8B_BPFLCD57_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2476 #define LCD_WF8B_BPFLCD57_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2477 #define LCD_WF8B_BPFLCD27_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2478 #define LCD_WF8B_BPFLCD27_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2479 #define LCD_WF8B_BPFLCD11_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2480 #define LCD_WF8B_BPFLCD11_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2481 #define LCD_WF8B_BPFLCD56_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2482 #define LCD_WF8B_BPFLCD56_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2483 #define LCD_WF8B_BPFLCD1_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2484 #define LCD_WF8B_BPFLCD1_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2485 #define LCD_WF8B_BPFLCD8_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2486 #define LCD_WF8B_BPFLCD8_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2487 #define LCD_WF8B_BPFLCD40_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2488 #define LCD_WF8B_BPFLCD40_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2489 #define LCD_WF8B_BPFLCD51_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2490 #define LCD_WF8B_BPFLCD51_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2491 #define LCD_WF8B_BPFLCD16_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2492 #define LCD_WF8B_BPFLCD16_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2493 #define LCD_WF8B_BPFLCD45_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2494 #define LCD_WF8B_BPFLCD45_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2495 #define LCD_WF8B_BPFLCD6_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2496 #define LCD_WF8B_BPFLCD6_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2497 #define LCD_WF8B_BPFLCD17_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2498 #define LCD_WF8B_BPFLCD17_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2499 #define LCD_WF8B_BPFLCD28_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2500 #define LCD_WF8B_BPFLCD28_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2501 #define LCD_WF8B_BPFLCD42_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2502 #define LCD_WF8B_BPFLCD42_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2503 #define LCD_WF8B_BPFLCD29_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2504 #define LCD_WF8B_BPFLCD29_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2505 #define LCD_WF8B_BPFLCD50_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2506 #define LCD_WF8B_BPFLCD50_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2507 #define LCD_WF8B_BPFLCD18_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2508 #define LCD_WF8B_BPFLCD18_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2509 #define LCD_WF8B_BPFLCD34_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2510 #define LCD_WF8B_BPFLCD34_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2511 #define LCD_WF8B_BPFLCD19_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2512 #define LCD_WF8B_BPFLCD19_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2513 #define LCD_WF8B_BPFLCD2_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2514 #define LCD_WF8B_BPFLCD2_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2515 #define LCD_WF8B_BPFLCD9_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2516 #define LCD_WF8B_BPFLCD9_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2517 #define LCD_WF8B_BPFLCD3_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2518 #define LCD_WF8B_BPFLCD3_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2519 #define LCD_WF8B_BPFLCD37_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2520 #define LCD_WF8B_BPFLCD37_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2521 #define LCD_WF8B_BPFLCD49_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2522 #define LCD_WF8B_BPFLCD49_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2523 #define LCD_WF8B_BPFLCD20_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2524 #define LCD_WF8B_BPFLCD20_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2525 #define LCD_WF8B_BPFLCD44_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2526 #define LCD_WF8B_BPFLCD44_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2527 #define LCD_WF8B_BPFLCD30_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2528 #define LCD_WF8B_BPFLCD30_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2529 #define LCD_WF8B_BPFLCD21_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2530 #define LCD_WF8B_BPFLCD21_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2531 #define LCD_WF8B_BPFLCD35_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2532 #define LCD_WF8B_BPFLCD35_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2533 #define LCD_WF8B_BPFLCD4_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2534 #define LCD_WF8B_BPFLCD4_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2535 #define LCD_WF8B_BPFLCD31_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2536 #define LCD_WF8B_BPFLCD31_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2537 #define LCD_WF8B_BPFLCD48_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2538 #define LCD_WF8B_BPFLCD48_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2539 #define LCD_WF8B_BPFLCD7_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2540 #define LCD_WF8B_BPFLCD7_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2541 #define LCD_WF8B_BPFLCD22_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2542 #define LCD_WF8B_BPFLCD22_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2543 #define LCD_WF8B_BPFLCD38_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2544 #define LCD_WF8B_BPFLCD38_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2545 #define LCD_WF8B_BPFLCD12_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2546 #define LCD_WF8B_BPFLCD12_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2547 #define LCD_WF8B_BPFLCD23_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2548 #define LCD_WF8B_BPFLCD23_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2549 #define LCD_WF8B_BPGLCD14_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2550 #define LCD_WF8B_BPGLCD14_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2551 #define LCD_WF8B_BPGLCD55_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2552 #define LCD_WF8B_BPGLCD55_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2553 #define LCD_WF8B_BPGLCD63_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2554 #define LCD_WF8B_BPGLCD63_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2555 #define LCD_WF8B_BPGLCD15_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2556 #define LCD_WF8B_BPGLCD15_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2557 #define LCD_WF8B_BPGLCD62_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2558 #define LCD_WF8B_BPGLCD62_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2559 #define LCD_WF8B_BPGLCD54_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2560 #define LCD_WF8B_BPGLCD54_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2561 #define LCD_WF8B_BPGLCD61_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2562 #define LCD_WF8B_BPGLCD61_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2563 #define LCD_WF8B_BPGLCD60_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2564 #define LCD_WF8B_BPGLCD60_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2565 #define LCD_WF8B_BPGLCD59_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2566 #define LCD_WF8B_BPGLCD59_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2567 #define LCD_WF8B_BPGLCD53_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2568 #define LCD_WF8B_BPGLCD53_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2569 #define LCD_WF8B_BPGLCD58_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2570 #define LCD_WF8B_BPGLCD58_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2571 #define LCD_WF8B_BPGLCD0_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2572 #define LCD_WF8B_BPGLCD0_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2573 #define LCD_WF8B_BPGLCD57_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2574 #define LCD_WF8B_BPGLCD57_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2575 #define LCD_WF8B_BPGLCD52_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2576 #define LCD_WF8B_BPGLCD52_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2577 #define LCD_WF8B_BPGLCD7_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2578 #define LCD_WF8B_BPGLCD7_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2579 #define LCD_WF8B_BPGLCD56_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2580 #define LCD_WF8B_BPGLCD56_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2581 #define LCD_WF8B_BPGLCD6_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2582 #define LCD_WF8B_BPGLCD6_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2583 #define LCD_WF8B_BPGLCD51_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2584 #define LCD_WF8B_BPGLCD51_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2585 #define LCD_WF8B_BPGLCD16_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2586 #define LCD_WF8B_BPGLCD16_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2587 #define LCD_WF8B_BPGLCD1_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2588 #define LCD_WF8B_BPGLCD1_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2589 #define LCD_WF8B_BPGLCD17_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2590 #define LCD_WF8B_BPGLCD17_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2591 #define LCD_WF8B_BPGLCD50_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2592 #define LCD_WF8B_BPGLCD50_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2593 #define LCD_WF8B_BPGLCD18_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2594 #define LCD_WF8B_BPGLCD18_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2595 #define LCD_WF8B_BPGLCD19_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2596 #define LCD_WF8B_BPGLCD19_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2597 #define LCD_WF8B_BPGLCD8_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2598 #define LCD_WF8B_BPGLCD8_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2599 #define LCD_WF8B_BPGLCD49_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2600 #define LCD_WF8B_BPGLCD49_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2601 #define LCD_WF8B_BPGLCD20_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2602 #define LCD_WF8B_BPGLCD20_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2603 #define LCD_WF8B_BPGLCD9_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2604 #define LCD_WF8B_BPGLCD9_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2605 #define LCD_WF8B_BPGLCD21_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2606 #define LCD_WF8B_BPGLCD21_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2607 #define LCD_WF8B_BPGLCD13_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2608 #define LCD_WF8B_BPGLCD13_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2609 #define LCD_WF8B_BPGLCD48_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2610 #define LCD_WF8B_BPGLCD48_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2611 #define LCD_WF8B_BPGLCD22_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2612 #define LCD_WF8B_BPGLCD22_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2613 #define LCD_WF8B_BPGLCD5_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2614 #define LCD_WF8B_BPGLCD5_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2615 #define LCD_WF8B_BPGLCD47_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2616 #define LCD_WF8B_BPGLCD47_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2617 #define LCD_WF8B_BPGLCD23_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2618 #define LCD_WF8B_BPGLCD23_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2619 #define LCD_WF8B_BPGLCD24_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2620 #define LCD_WF8B_BPGLCD24_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2621 #define LCD_WF8B_BPGLCD25_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2622 #define LCD_WF8B_BPGLCD25_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2623 #define LCD_WF8B_BPGLCD46_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2624 #define LCD_WF8B_BPGLCD46_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2625 #define LCD_WF8B_BPGLCD26_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2626 #define LCD_WF8B_BPGLCD26_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2627 #define LCD_WF8B_BPGLCD27_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2628 #define LCD_WF8B_BPGLCD27_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2629 #define LCD_WF8B_BPGLCD10_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2630 #define LCD_WF8B_BPGLCD10_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2631 #define LCD_WF8B_BPGLCD45_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2632 #define LCD_WF8B_BPGLCD45_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2633 #define LCD_WF8B_BPGLCD28_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2634 #define LCD_WF8B_BPGLCD28_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2635 #define LCD_WF8B_BPGLCD29_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2636 #define LCD_WF8B_BPGLCD29_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2637 #define LCD_WF8B_BPGLCD4_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2638 #define LCD_WF8B_BPGLCD4_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2639 #define LCD_WF8B_BPGLCD44_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2640 #define LCD_WF8B_BPGLCD44_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2641 #define LCD_WF8B_BPGLCD30_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2642 #define LCD_WF8B_BPGLCD30_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2643 #define LCD_WF8B_BPGLCD2_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2644 #define LCD_WF8B_BPGLCD2_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2645 #define LCD_WF8B_BPGLCD31_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2646 #define LCD_WF8B_BPGLCD31_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2647 #define LCD_WF8B_BPGLCD43_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2648 #define LCD_WF8B_BPGLCD43_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2649 #define LCD_WF8B_BPGLCD32_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2650 #define LCD_WF8B_BPGLCD32_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2651 #define LCD_WF8B_BPGLCD33_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2652 #define LCD_WF8B_BPGLCD33_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2653 #define LCD_WF8B_BPGLCD42_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2654 #define LCD_WF8B_BPGLCD42_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2655 #define LCD_WF8B_BPGLCD34_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2656 #define LCD_WF8B_BPGLCD34_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2657 #define LCD_WF8B_BPGLCD11_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2658 #define LCD_WF8B_BPGLCD11_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2659 #define LCD_WF8B_BPGLCD35_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2660 #define LCD_WF8B_BPGLCD35_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2661 #define LCD_WF8B_BPGLCD12_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2662 #define LCD_WF8B_BPGLCD12_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2663 #define LCD_WF8B_BPGLCD41_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2664 #define LCD_WF8B_BPGLCD41_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2665 #define LCD_WF8B_BPGLCD36_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2666 #define LCD_WF8B_BPGLCD36_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2667 #define LCD_WF8B_BPGLCD3_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2668 #define LCD_WF8B_BPGLCD3_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2669 #define LCD_WF8B_BPGLCD37_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2670 #define LCD_WF8B_BPGLCD37_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2671 #define LCD_WF8B_BPGLCD40_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2672 #define LCD_WF8B_BPGLCD40_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2673 #define LCD_WF8B_BPGLCD38_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2674 #define LCD_WF8B_BPGLCD38_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2675 #define LCD_WF8B_BPGLCD39_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2676 #define LCD_WF8B_BPGLCD39_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2677 #define LCD_WF8B_BPHLCD63_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2678 #define LCD_WF8B_BPHLCD63_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2679 #define LCD_WF8B_BPHLCD62_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2680 #define LCD_WF8B_BPHLCD62_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2681 #define LCD_WF8B_BPHLCD61_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2682 #define LCD_WF8B_BPHLCD61_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2683 #define LCD_WF8B_BPHLCD60_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2684 #define LCD_WF8B_BPHLCD60_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2685 #define LCD_WF8B_BPHLCD59_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2686 #define LCD_WF8B_BPHLCD59_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2687 #define LCD_WF8B_BPHLCD58_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2688 #define LCD_WF8B_BPHLCD58_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2689 #define LCD_WF8B_BPHLCD57_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2690 #define LCD_WF8B_BPHLCD57_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2691 #define LCD_WF8B_BPHLCD0_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2692 #define LCD_WF8B_BPHLCD0_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2693 #define LCD_WF8B_BPHLCD56_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2694 #define LCD_WF8B_BPHLCD56_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2695 #define LCD_WF8B_BPHLCD55_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2696 #define LCD_WF8B_BPHLCD55_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2697 #define LCD_WF8B_BPHLCD54_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2698 #define LCD_WF8B_BPHLCD54_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2699 #define LCD_WF8B_BPHLCD53_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2700 #define LCD_WF8B_BPHLCD53_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2701 #define LCD_WF8B_BPHLCD52_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2702 #define LCD_WF8B_BPHLCD52_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2703 #define LCD_WF8B_BPHLCD51_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2704 #define LCD_WF8B_BPHLCD51_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2705 #define LCD_WF8B_BPHLCD50_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2706 #define LCD_WF8B_BPHLCD50_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2707 #define LCD_WF8B_BPHLCD1_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2708 #define LCD_WF8B_BPHLCD1_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2709 #define LCD_WF8B_BPHLCD49_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2710 #define LCD_WF8B_BPHLCD49_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2711 #define LCD_WF8B_BPHLCD48_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2712 #define LCD_WF8B_BPHLCD48_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2713 #define LCD_WF8B_BPHLCD47_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2714 #define LCD_WF8B_BPHLCD47_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2715 #define LCD_WF8B_BPHLCD46_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2716 #define LCD_WF8B_BPHLCD46_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2717 #define LCD_WF8B_BPHLCD45_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2718 #define LCD_WF8B_BPHLCD45_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2719 #define LCD_WF8B_BPHLCD44_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2720 #define LCD_WF8B_BPHLCD44_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2721 #define LCD_WF8B_BPHLCD43_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2722 #define LCD_WF8B_BPHLCD43_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2723 #define LCD_WF8B_BPHLCD2_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2724 #define LCD_WF8B_BPHLCD2_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2725 #define LCD_WF8B_BPHLCD42_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2726 #define LCD_WF8B_BPHLCD42_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2727 #define LCD_WF8B_BPHLCD41_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2728 #define LCD_WF8B_BPHLCD41_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2729 #define LCD_WF8B_BPHLCD40_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2730 #define LCD_WF8B_BPHLCD40_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2731 #define LCD_WF8B_BPHLCD39_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2732 #define LCD_WF8B_BPHLCD39_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2733 #define LCD_WF8B_BPHLCD38_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2734 #define LCD_WF8B_BPHLCD38_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2735 #define LCD_WF8B_BPHLCD37_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2736 #define LCD_WF8B_BPHLCD37_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2737 #define LCD_WF8B_BPHLCD36_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2738 #define LCD_WF8B_BPHLCD36_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2739 #define LCD_WF8B_BPHLCD3_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2740 #define LCD_WF8B_BPHLCD3_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2741 #define LCD_WF8B_BPHLCD35_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2742 #define LCD_WF8B_BPHLCD35_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2743 #define LCD_WF8B_BPHLCD34_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2744 #define LCD_WF8B_BPHLCD34_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2745 #define LCD_WF8B_BPHLCD33_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2746 #define LCD_WF8B_BPHLCD33_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2747 #define LCD_WF8B_BPHLCD32_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2748 #define LCD_WF8B_BPHLCD32_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2749 #define LCD_WF8B_BPHLCD31_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2750 #define LCD_WF8B_BPHLCD31_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2751 #define LCD_WF8B_BPHLCD30_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2752 #define LCD_WF8B_BPHLCD30_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2753 #define LCD_WF8B_BPHLCD29_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2754 #define LCD_WF8B_BPHLCD29_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2755 #define LCD_WF8B_BPHLCD4_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2756 #define LCD_WF8B_BPHLCD4_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2757 #define LCD_WF8B_BPHLCD28_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2758 #define LCD_WF8B_BPHLCD28_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2759 #define LCD_WF8B_BPHLCD27_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2760 #define LCD_WF8B_BPHLCD27_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2761 #define LCD_WF8B_BPHLCD26_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2762 #define LCD_WF8B_BPHLCD26_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2763 #define LCD_WF8B_BPHLCD25_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2764 #define LCD_WF8B_BPHLCD25_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2765 #define LCD_WF8B_BPHLCD24_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2766 #define LCD_WF8B_BPHLCD24_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2767 #define LCD_WF8B_BPHLCD23_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2768 #define LCD_WF8B_BPHLCD23_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2769 #define LCD_WF8B_BPHLCD22_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2770 #define LCD_WF8B_BPHLCD22_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2771 #define LCD_WF8B_BPHLCD5_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2772 #define LCD_WF8B_BPHLCD5_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2773 #define LCD_WF8B_BPHLCD21_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2774 #define LCD_WF8B_BPHLCD21_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2775 #define LCD_WF8B_BPHLCD20_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2776 #define LCD_WF8B_BPHLCD20_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2777 #define LCD_WF8B_BPHLCD19_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2778 #define LCD_WF8B_BPHLCD19_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2779 #define LCD_WF8B_BPHLCD18_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2780 #define LCD_WF8B_BPHLCD18_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2781 #define LCD_WF8B_BPHLCD17_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2782 #define LCD_WF8B_BPHLCD17_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2783 #define LCD_WF8B_BPHLCD16_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2784 #define LCD_WF8B_BPHLCD16_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2785 #define LCD_WF8B_BPHLCD15_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2786 #define LCD_WF8B_BPHLCD15_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2787 #define LCD_WF8B_BPHLCD6_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2788 #define LCD_WF8B_BPHLCD6_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2789 #define LCD_WF8B_BPHLCD14_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2790 #define LCD_WF8B_BPHLCD14_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2791 #define LCD_WF8B_BPHLCD13_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2792 #define LCD_WF8B_BPHLCD13_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2793 #define LCD_WF8B_BPHLCD12_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2794 #define LCD_WF8B_BPHLCD12_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2795 #define LCD_WF8B_BPHLCD11_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2796 #define LCD_WF8B_BPHLCD11_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2797 #define LCD_WF8B_BPHLCD10_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2798 #define LCD_WF8B_BPHLCD10_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2799 #define LCD_WF8B_BPHLCD9_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2800 #define LCD_WF8B_BPHLCD9_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2801 #define LCD_WF8B_BPHLCD8_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2802 #define LCD_WF8B_BPHLCD8_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2803 #define LCD_WF8B_BPHLCD7_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2804 #define LCD_WF8B_BPHLCD7_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2805
AnnaBridge 171:3a7713b1edbc 2806 /*!
AnnaBridge 171:3a7713b1edbc 2807 * @}
AnnaBridge 171:3a7713b1edbc 2808 */ /* end of group LCD_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2809
AnnaBridge 171:3a7713b1edbc 2810
AnnaBridge 171:3a7713b1edbc 2811 /* LCD - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2812 /** Peripheral LCD base address */
AnnaBridge 171:3a7713b1edbc 2813 #define LCD_BASE (0x40053000u)
AnnaBridge 171:3a7713b1edbc 2814 /** Peripheral LCD base pointer */
AnnaBridge 171:3a7713b1edbc 2815 #define LCD ((LCD_Type *)LCD_BASE)
AnnaBridge 171:3a7713b1edbc 2816 /** Array initializer of LCD peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2817 #define LCD_BASES { LCD }
AnnaBridge 171:3a7713b1edbc 2818
AnnaBridge 171:3a7713b1edbc 2819 /*!
AnnaBridge 171:3a7713b1edbc 2820 * @}
AnnaBridge 171:3a7713b1edbc 2821 */ /* end of group LCD_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2822
AnnaBridge 171:3a7713b1edbc 2823
AnnaBridge 171:3a7713b1edbc 2824 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2825 -- LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2826 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2827
AnnaBridge 171:3a7713b1edbc 2828 /*!
AnnaBridge 171:3a7713b1edbc 2829 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2830 * @{
AnnaBridge 171:3a7713b1edbc 2831 */
AnnaBridge 171:3a7713b1edbc 2832
AnnaBridge 171:3a7713b1edbc 2833 /** LLWU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2834 typedef struct {
AnnaBridge 171:3a7713b1edbc 2835 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2836 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 2837 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 2838 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 2839 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2840 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 2841 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 2842 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 2843 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2844 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 2845 } LLWU_Type;
AnnaBridge 171:3a7713b1edbc 2846
AnnaBridge 171:3a7713b1edbc 2847 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2848 -- LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 2849 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2850
AnnaBridge 171:3a7713b1edbc 2851 /*!
AnnaBridge 171:3a7713b1edbc 2852 * @addtogroup LLWU_Register_Masks LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 2853 * @{
AnnaBridge 171:3a7713b1edbc 2854 */
AnnaBridge 171:3a7713b1edbc 2855
AnnaBridge 171:3a7713b1edbc 2856 /* PE1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2857 #define LLWU_PE1_WUPE0_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 2858 #define LLWU_PE1_WUPE0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2859 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
AnnaBridge 171:3a7713b1edbc 2860 #define LLWU_PE1_WUPE1_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 2861 #define LLWU_PE1_WUPE1_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2862 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
AnnaBridge 171:3a7713b1edbc 2863 #define LLWU_PE1_WUPE2_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 2864 #define LLWU_PE1_WUPE2_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2865 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
AnnaBridge 171:3a7713b1edbc 2866 #define LLWU_PE1_WUPE3_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 2867 #define LLWU_PE1_WUPE3_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2868 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
AnnaBridge 171:3a7713b1edbc 2869 /* PE2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2870 #define LLWU_PE2_WUPE4_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 2871 #define LLWU_PE2_WUPE4_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2872 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
AnnaBridge 171:3a7713b1edbc 2873 #define LLWU_PE2_WUPE5_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 2874 #define LLWU_PE2_WUPE5_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2875 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
AnnaBridge 171:3a7713b1edbc 2876 #define LLWU_PE2_WUPE6_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 2877 #define LLWU_PE2_WUPE6_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2878 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
AnnaBridge 171:3a7713b1edbc 2879 #define LLWU_PE2_WUPE7_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 2880 #define LLWU_PE2_WUPE7_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2881 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
AnnaBridge 171:3a7713b1edbc 2882 /* PE3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2883 #define LLWU_PE3_WUPE8_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 2884 #define LLWU_PE3_WUPE8_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2885 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
AnnaBridge 171:3a7713b1edbc 2886 #define LLWU_PE3_WUPE9_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 2887 #define LLWU_PE3_WUPE9_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2888 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
AnnaBridge 171:3a7713b1edbc 2889 #define LLWU_PE3_WUPE10_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 2890 #define LLWU_PE3_WUPE10_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2891 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
AnnaBridge 171:3a7713b1edbc 2892 #define LLWU_PE3_WUPE11_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 2893 #define LLWU_PE3_WUPE11_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2894 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
AnnaBridge 171:3a7713b1edbc 2895 /* PE4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2896 #define LLWU_PE4_WUPE12_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 2897 #define LLWU_PE4_WUPE12_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2898 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
AnnaBridge 171:3a7713b1edbc 2899 #define LLWU_PE4_WUPE13_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 2900 #define LLWU_PE4_WUPE13_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2901 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
AnnaBridge 171:3a7713b1edbc 2902 #define LLWU_PE4_WUPE14_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 2903 #define LLWU_PE4_WUPE14_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2904 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
AnnaBridge 171:3a7713b1edbc 2905 #define LLWU_PE4_WUPE15_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 2906 #define LLWU_PE4_WUPE15_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2907 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
AnnaBridge 171:3a7713b1edbc 2908 /* ME Bit Fields */
AnnaBridge 171:3a7713b1edbc 2909 #define LLWU_ME_WUME0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2910 #define LLWU_ME_WUME0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2911 #define LLWU_ME_WUME1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2912 #define LLWU_ME_WUME1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2913 #define LLWU_ME_WUME2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2914 #define LLWU_ME_WUME2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2915 #define LLWU_ME_WUME3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2916 #define LLWU_ME_WUME3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2917 #define LLWU_ME_WUME4_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2918 #define LLWU_ME_WUME4_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2919 #define LLWU_ME_WUME5_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2920 #define LLWU_ME_WUME5_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2921 #define LLWU_ME_WUME6_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2922 #define LLWU_ME_WUME6_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2923 #define LLWU_ME_WUME7_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2924 #define LLWU_ME_WUME7_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2925 /* F1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2926 #define LLWU_F1_WUF0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2927 #define LLWU_F1_WUF0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2928 #define LLWU_F1_WUF1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2929 #define LLWU_F1_WUF1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2930 #define LLWU_F1_WUF2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2931 #define LLWU_F1_WUF2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2932 #define LLWU_F1_WUF3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2933 #define LLWU_F1_WUF3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2934 #define LLWU_F1_WUF4_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2935 #define LLWU_F1_WUF4_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2936 #define LLWU_F1_WUF5_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2937 #define LLWU_F1_WUF5_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2938 #define LLWU_F1_WUF6_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2939 #define LLWU_F1_WUF6_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2940 #define LLWU_F1_WUF7_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2941 #define LLWU_F1_WUF7_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2942 /* F2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2943 #define LLWU_F2_WUF8_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2944 #define LLWU_F2_WUF8_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2945 #define LLWU_F2_WUF9_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2946 #define LLWU_F2_WUF9_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2947 #define LLWU_F2_WUF10_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2948 #define LLWU_F2_WUF10_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2949 #define LLWU_F2_WUF11_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2950 #define LLWU_F2_WUF11_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2951 #define LLWU_F2_WUF12_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2952 #define LLWU_F2_WUF12_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2953 #define LLWU_F2_WUF13_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2954 #define LLWU_F2_WUF13_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2955 #define LLWU_F2_WUF14_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2956 #define LLWU_F2_WUF14_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2957 #define LLWU_F2_WUF15_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2958 #define LLWU_F2_WUF15_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2959 /* F3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2960 #define LLWU_F3_MWUF0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2961 #define LLWU_F3_MWUF0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2962 #define LLWU_F3_MWUF1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2963 #define LLWU_F3_MWUF1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2964 #define LLWU_F3_MWUF2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2965 #define LLWU_F3_MWUF2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2966 #define LLWU_F3_MWUF3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2967 #define LLWU_F3_MWUF3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2968 #define LLWU_F3_MWUF4_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2969 #define LLWU_F3_MWUF4_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2970 #define LLWU_F3_MWUF5_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2971 #define LLWU_F3_MWUF5_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2972 #define LLWU_F3_MWUF6_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2973 #define LLWU_F3_MWUF6_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2974 #define LLWU_F3_MWUF7_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2975 #define LLWU_F3_MWUF7_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2976 /* FILT1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2977 #define LLWU_FILT1_FILTSEL_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 2978 #define LLWU_FILT1_FILTSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2979 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 2980 #define LLWU_FILT1_FILTE_MASK 0x60u
AnnaBridge 171:3a7713b1edbc 2981 #define LLWU_FILT1_FILTE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2982 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 2983 #define LLWU_FILT1_FILTF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2984 #define LLWU_FILT1_FILTF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2985 /* FILT2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2986 #define LLWU_FILT2_FILTSEL_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 2987 #define LLWU_FILT2_FILTSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2988 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 2989 #define LLWU_FILT2_FILTE_MASK 0x60u
AnnaBridge 171:3a7713b1edbc 2990 #define LLWU_FILT2_FILTE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2991 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 2992 #define LLWU_FILT2_FILTF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2993 #define LLWU_FILT2_FILTF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2994
AnnaBridge 171:3a7713b1edbc 2995 /*!
AnnaBridge 171:3a7713b1edbc 2996 * @}
AnnaBridge 171:3a7713b1edbc 2997 */ /* end of group LLWU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2998
AnnaBridge 171:3a7713b1edbc 2999
AnnaBridge 171:3a7713b1edbc 3000 /* LLWU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3001 /** Peripheral LLWU base address */
AnnaBridge 171:3a7713b1edbc 3002 #define LLWU_BASE (0x4007C000u)
AnnaBridge 171:3a7713b1edbc 3003 /** Peripheral LLWU base pointer */
AnnaBridge 171:3a7713b1edbc 3004 #define LLWU ((LLWU_Type *)LLWU_BASE)
AnnaBridge 171:3a7713b1edbc 3005 /** Array initializer of LLWU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3006 #define LLWU_BASES { LLWU }
AnnaBridge 171:3a7713b1edbc 3007
AnnaBridge 171:3a7713b1edbc 3008 /*!
AnnaBridge 171:3a7713b1edbc 3009 * @}
AnnaBridge 171:3a7713b1edbc 3010 */ /* end of group LLWU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3011
AnnaBridge 171:3a7713b1edbc 3012
AnnaBridge 171:3a7713b1edbc 3013 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3014 -- LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3015 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3016
AnnaBridge 171:3a7713b1edbc 3017 /*!
AnnaBridge 171:3a7713b1edbc 3018 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3019 * @{
AnnaBridge 171:3a7713b1edbc 3020 */
AnnaBridge 171:3a7713b1edbc 3021
AnnaBridge 171:3a7713b1edbc 3022 /** LPTMR - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3023 typedef struct {
AnnaBridge 171:3a7713b1edbc 3024 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3025 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3026 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3027 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3028 } LPTMR_Type;
AnnaBridge 171:3a7713b1edbc 3029
AnnaBridge 171:3a7713b1edbc 3030 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3031 -- LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 3032 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3033
AnnaBridge 171:3a7713b1edbc 3034 /*!
AnnaBridge 171:3a7713b1edbc 3035 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 3036 * @{
AnnaBridge 171:3a7713b1edbc 3037 */
AnnaBridge 171:3a7713b1edbc 3038
AnnaBridge 171:3a7713b1edbc 3039 /* CSR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3040 #define LPTMR_CSR_TEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3041 #define LPTMR_CSR_TEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3042 #define LPTMR_CSR_TMS_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3043 #define LPTMR_CSR_TMS_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3044 #define LPTMR_CSR_TFC_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3045 #define LPTMR_CSR_TFC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3046 #define LPTMR_CSR_TPP_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3047 #define LPTMR_CSR_TPP_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3048 #define LPTMR_CSR_TPS_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 3049 #define LPTMR_CSR_TPS_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3050 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
AnnaBridge 171:3a7713b1edbc 3051 #define LPTMR_CSR_TIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3052 #define LPTMR_CSR_TIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3053 #define LPTMR_CSR_TCF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3054 #define LPTMR_CSR_TCF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3055 /* PSR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3056 #define LPTMR_PSR_PCS_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 3057 #define LPTMR_PSR_PCS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3058 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
AnnaBridge 171:3a7713b1edbc 3059 #define LPTMR_PSR_PBYP_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3060 #define LPTMR_PSR_PBYP_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3061 #define LPTMR_PSR_PRESCALE_MASK 0x78u
AnnaBridge 171:3a7713b1edbc 3062 #define LPTMR_PSR_PRESCALE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3063 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
AnnaBridge 171:3a7713b1edbc 3064 /* CMR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3065 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 3066 #define LPTMR_CMR_COMPARE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3067 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
AnnaBridge 171:3a7713b1edbc 3068 /* CNR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3069 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 3070 #define LPTMR_CNR_COUNTER_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3071 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 3072
AnnaBridge 171:3a7713b1edbc 3073 /*!
AnnaBridge 171:3a7713b1edbc 3074 * @}
AnnaBridge 171:3a7713b1edbc 3075 */ /* end of group LPTMR_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3076
AnnaBridge 171:3a7713b1edbc 3077
AnnaBridge 171:3a7713b1edbc 3078 /* LPTMR - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3079 /** Peripheral LPTMR0 base address */
AnnaBridge 171:3a7713b1edbc 3080 #define LPTMR0_BASE (0x40040000u)
AnnaBridge 171:3a7713b1edbc 3081 /** Peripheral LPTMR0 base pointer */
AnnaBridge 171:3a7713b1edbc 3082 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
AnnaBridge 171:3a7713b1edbc 3083 /** Array initializer of LPTMR peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3084 #define LPTMR_BASES { LPTMR0 }
AnnaBridge 171:3a7713b1edbc 3085
AnnaBridge 171:3a7713b1edbc 3086 /*!
AnnaBridge 171:3a7713b1edbc 3087 * @}
AnnaBridge 171:3a7713b1edbc 3088 */ /* end of group LPTMR_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3089
AnnaBridge 171:3a7713b1edbc 3090
AnnaBridge 171:3a7713b1edbc 3091 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3092 -- MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3093 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3094
AnnaBridge 171:3a7713b1edbc 3095 /*!
AnnaBridge 171:3a7713b1edbc 3096 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3097 * @{
AnnaBridge 171:3a7713b1edbc 3098 */
AnnaBridge 171:3a7713b1edbc 3099
AnnaBridge 171:3a7713b1edbc 3100 /** MCG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3101 typedef struct {
AnnaBridge 171:3a7713b1edbc 3102 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3103 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3104 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3105 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3106 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3107 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3108 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3109 uint8_t RESERVED_0[1];
AnnaBridge 171:3a7713b1edbc 3110 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3111 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 3112 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 3113 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 3114 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3115 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 3116 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 3117 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 3118 } MCG_Type;
AnnaBridge 171:3a7713b1edbc 3119
AnnaBridge 171:3a7713b1edbc 3120 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3121 -- MCG Register Masks
AnnaBridge 171:3a7713b1edbc 3122 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3123
AnnaBridge 171:3a7713b1edbc 3124 /*!
AnnaBridge 171:3a7713b1edbc 3125 * @addtogroup MCG_Register_Masks MCG Register Masks
AnnaBridge 171:3a7713b1edbc 3126 * @{
AnnaBridge 171:3a7713b1edbc 3127 */
AnnaBridge 171:3a7713b1edbc 3128
AnnaBridge 171:3a7713b1edbc 3129 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3130 #define MCG_C1_IREFSTEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3131 #define MCG_C1_IREFSTEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3132 #define MCG_C1_IRCLKEN_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3133 #define MCG_C1_IRCLKEN_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3134 #define MCG_C1_IREFS_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3135 #define MCG_C1_IREFS_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3136 #define MCG_C1_FRDIV_MASK 0x38u
AnnaBridge 171:3a7713b1edbc 3137 #define MCG_C1_FRDIV_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3138 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 3139 #define MCG_C1_CLKS_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 3140 #define MCG_C1_CLKS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3141 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 3142 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3143 #define MCG_C2_IRCS_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3144 #define MCG_C2_IRCS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3145 #define MCG_C2_LP_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3146 #define MCG_C2_LP_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3147 #define MCG_C2_EREFS0_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3148 #define MCG_C2_EREFS0_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3149 #define MCG_C2_HGO0_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3150 #define MCG_C2_HGO0_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3151 #define MCG_C2_RANGE0_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 3152 #define MCG_C2_RANGE0_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3153 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
AnnaBridge 171:3a7713b1edbc 3154 #define MCG_C2_FCFTRIM_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3155 #define MCG_C2_FCFTRIM_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3156 #define MCG_C2_LOCRE0_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3157 #define MCG_C2_LOCRE0_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3158 /* C3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3159 #define MCG_C3_SCTRIM_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3160 #define MCG_C3_SCTRIM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3161 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 3162 /* C4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3163 #define MCG_C4_SCFTRIM_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3164 #define MCG_C4_SCFTRIM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3165 #define MCG_C4_FCTRIM_MASK 0x1Eu
AnnaBridge 171:3a7713b1edbc 3166 #define MCG_C4_FCTRIM_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3167 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 3168 #define MCG_C4_DRST_DRS_MASK 0x60u
AnnaBridge 171:3a7713b1edbc 3169 #define MCG_C4_DRST_DRS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3170 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
AnnaBridge 171:3a7713b1edbc 3171 #define MCG_C4_DMX32_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3172 #define MCG_C4_DMX32_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3173 /* C5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3174 #define MCG_C5_PRDIV0_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 3175 #define MCG_C5_PRDIV0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3176 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
AnnaBridge 171:3a7713b1edbc 3177 #define MCG_C5_PLLSTEN0_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3178 #define MCG_C5_PLLSTEN0_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3179 #define MCG_C5_PLLCLKEN0_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3180 #define MCG_C5_PLLCLKEN0_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3181 /* C6 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3182 #define MCG_C6_VDIV0_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 3183 #define MCG_C6_VDIV0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3184 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
AnnaBridge 171:3a7713b1edbc 3185 #define MCG_C6_CME0_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3186 #define MCG_C6_CME0_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3187 #define MCG_C6_PLLS_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3188 #define MCG_C6_PLLS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3189 #define MCG_C6_LOLIE0_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3190 #define MCG_C6_LOLIE0_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3191 /* S Bit Fields */
AnnaBridge 171:3a7713b1edbc 3192 #define MCG_S_IRCST_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3193 #define MCG_S_IRCST_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3194 #define MCG_S_OSCINIT0_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3195 #define MCG_S_OSCINIT0_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3196 #define MCG_S_CLKST_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 3197 #define MCG_S_CLKST_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3198 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
AnnaBridge 171:3a7713b1edbc 3199 #define MCG_S_IREFST_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3200 #define MCG_S_IREFST_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3201 #define MCG_S_PLLST_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3202 #define MCG_S_PLLST_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3203 #define MCG_S_LOCK0_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3204 #define MCG_S_LOCK0_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3205 #define MCG_S_LOLS_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3206 #define MCG_S_LOLS_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3207 /* SC Bit Fields */
AnnaBridge 171:3a7713b1edbc 3208 #define MCG_SC_LOCS0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3209 #define MCG_SC_LOCS0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3210 #define MCG_SC_FCRDIV_MASK 0xEu
AnnaBridge 171:3a7713b1edbc 3211 #define MCG_SC_FCRDIV_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3212 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 3213 #define MCG_SC_FLTPRSRV_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3214 #define MCG_SC_FLTPRSRV_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3215 #define MCG_SC_ATMF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3216 #define MCG_SC_ATMF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3217 #define MCG_SC_ATMS_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3218 #define MCG_SC_ATMS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3219 #define MCG_SC_ATME_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3220 #define MCG_SC_ATME_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3221 /* ATCVH Bit Fields */
AnnaBridge 171:3a7713b1edbc 3222 #define MCG_ATCVH_ATCVH_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3223 #define MCG_ATCVH_ATCVH_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3224 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
AnnaBridge 171:3a7713b1edbc 3225 /* ATCVL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3226 #define MCG_ATCVL_ATCVL_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3227 #define MCG_ATCVL_ATCVL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3228 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
AnnaBridge 171:3a7713b1edbc 3229 /* C8 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3230 #define MCG_C8_LOLRE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3231 #define MCG_C8_LOLRE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3232
AnnaBridge 171:3a7713b1edbc 3233 /*!
AnnaBridge 171:3a7713b1edbc 3234 * @}
AnnaBridge 171:3a7713b1edbc 3235 */ /* end of group MCG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3236
AnnaBridge 171:3a7713b1edbc 3237
AnnaBridge 171:3a7713b1edbc 3238 /* MCG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3239 /** Peripheral MCG base address */
AnnaBridge 171:3a7713b1edbc 3240 #define MCG_BASE (0x40064000u)
AnnaBridge 171:3a7713b1edbc 3241 /** Peripheral MCG base pointer */
AnnaBridge 171:3a7713b1edbc 3242 #define MCG ((MCG_Type *)MCG_BASE)
AnnaBridge 171:3a7713b1edbc 3243 /** Array initializer of MCG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3244 #define MCG_BASES { MCG }
AnnaBridge 171:3a7713b1edbc 3245
AnnaBridge 171:3a7713b1edbc 3246 /*!
AnnaBridge 171:3a7713b1edbc 3247 * @}
AnnaBridge 171:3a7713b1edbc 3248 */ /* end of group MCG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3249
AnnaBridge 171:3a7713b1edbc 3250
AnnaBridge 171:3a7713b1edbc 3251 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3252 -- MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3253 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3254
AnnaBridge 171:3a7713b1edbc 3255 /*!
AnnaBridge 171:3a7713b1edbc 3256 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3257 * @{
AnnaBridge 171:3a7713b1edbc 3258 */
AnnaBridge 171:3a7713b1edbc 3259
AnnaBridge 171:3a7713b1edbc 3260 /** MCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3261 typedef struct {
AnnaBridge 171:3a7713b1edbc 3262 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 3263 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3264 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 3265 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3266 uint8_t RESERVED_1[48];
AnnaBridge 171:3a7713b1edbc 3267 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 3268 } MCM_Type;
AnnaBridge 171:3a7713b1edbc 3269
AnnaBridge 171:3a7713b1edbc 3270 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3271 -- MCM Register Masks
AnnaBridge 171:3a7713b1edbc 3272 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3273
AnnaBridge 171:3a7713b1edbc 3274 /*!
AnnaBridge 171:3a7713b1edbc 3275 * @addtogroup MCM_Register_Masks MCM Register Masks
AnnaBridge 171:3a7713b1edbc 3276 * @{
AnnaBridge 171:3a7713b1edbc 3277 */
AnnaBridge 171:3a7713b1edbc 3278
AnnaBridge 171:3a7713b1edbc 3279 /* PLASC Bit Fields */
AnnaBridge 171:3a7713b1edbc 3280 #define MCM_PLASC_ASC_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3281 #define MCM_PLASC_ASC_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3282 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
AnnaBridge 171:3a7713b1edbc 3283 /* PLAMC Bit Fields */
AnnaBridge 171:3a7713b1edbc 3284 #define MCM_PLAMC_AMC_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3285 #define MCM_PLAMC_AMC_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3286 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
AnnaBridge 171:3a7713b1edbc 3287 /* PLACR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3288 #define MCM_PLACR_ARB_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 3289 #define MCM_PLACR_ARB_SHIFT 9
AnnaBridge 171:3a7713b1edbc 3290 #define MCM_PLACR_CFCC_MASK 0x400u
AnnaBridge 171:3a7713b1edbc 3291 #define MCM_PLACR_CFCC_SHIFT 10
AnnaBridge 171:3a7713b1edbc 3292 #define MCM_PLACR_DFCDA_MASK 0x800u
AnnaBridge 171:3a7713b1edbc 3293 #define MCM_PLACR_DFCDA_SHIFT 11
AnnaBridge 171:3a7713b1edbc 3294 #define MCM_PLACR_DFCIC_MASK 0x1000u
AnnaBridge 171:3a7713b1edbc 3295 #define MCM_PLACR_DFCIC_SHIFT 12
AnnaBridge 171:3a7713b1edbc 3296 #define MCM_PLACR_DFCC_MASK 0x2000u
AnnaBridge 171:3a7713b1edbc 3297 #define MCM_PLACR_DFCC_SHIFT 13
AnnaBridge 171:3a7713b1edbc 3298 #define MCM_PLACR_EFDS_MASK 0x4000u
AnnaBridge 171:3a7713b1edbc 3299 #define MCM_PLACR_EFDS_SHIFT 14
AnnaBridge 171:3a7713b1edbc 3300 #define MCM_PLACR_DFCS_MASK 0x8000u
AnnaBridge 171:3a7713b1edbc 3301 #define MCM_PLACR_DFCS_SHIFT 15
AnnaBridge 171:3a7713b1edbc 3302 #define MCM_PLACR_ESFC_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 3303 #define MCM_PLACR_ESFC_SHIFT 16
AnnaBridge 171:3a7713b1edbc 3304 /* CPO Bit Fields */
AnnaBridge 171:3a7713b1edbc 3305 #define MCM_CPO_CPOREQ_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3306 #define MCM_CPO_CPOREQ_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3307 #define MCM_CPO_CPOACK_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3308 #define MCM_CPO_CPOACK_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3309 #define MCM_CPO_CPOWOI_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3310 #define MCM_CPO_CPOWOI_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3311
AnnaBridge 171:3a7713b1edbc 3312 /*!
AnnaBridge 171:3a7713b1edbc 3313 * @}
AnnaBridge 171:3a7713b1edbc 3314 */ /* end of group MCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3315
AnnaBridge 171:3a7713b1edbc 3316
AnnaBridge 171:3a7713b1edbc 3317 /* MCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3318 /** Peripheral MCM base address */
AnnaBridge 171:3a7713b1edbc 3319 #define MCM_BASE (0xF0003000u)
AnnaBridge 171:3a7713b1edbc 3320 /** Peripheral MCM base pointer */
AnnaBridge 171:3a7713b1edbc 3321 #define MCM ((MCM_Type *)MCM_BASE)
AnnaBridge 171:3a7713b1edbc 3322 /** Array initializer of MCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3323 #define MCM_BASES { MCM }
AnnaBridge 171:3a7713b1edbc 3324
AnnaBridge 171:3a7713b1edbc 3325 /*!
AnnaBridge 171:3a7713b1edbc 3326 * @}
AnnaBridge 171:3a7713b1edbc 3327 */ /* end of group MCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3328
AnnaBridge 171:3a7713b1edbc 3329
AnnaBridge 171:3a7713b1edbc 3330 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3331 -- MTB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3332 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3333
AnnaBridge 171:3a7713b1edbc 3334 /*!
AnnaBridge 171:3a7713b1edbc 3335 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3336 * @{
AnnaBridge 171:3a7713b1edbc 3337 */
AnnaBridge 171:3a7713b1edbc 3338
AnnaBridge 171:3a7713b1edbc 3339 /** MTB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3340 typedef struct {
AnnaBridge 171:3a7713b1edbc 3341 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3342 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3343 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3344 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3345 uint8_t RESERVED_0[3824];
AnnaBridge 171:3a7713b1edbc 3346 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
AnnaBridge 171:3a7713b1edbc 3347 uint8_t RESERVED_1[156];
AnnaBridge 171:3a7713b1edbc 3348 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
AnnaBridge 171:3a7713b1edbc 3349 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
AnnaBridge 171:3a7713b1edbc 3350 uint8_t RESERVED_2[8];
AnnaBridge 171:3a7713b1edbc 3351 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
AnnaBridge 171:3a7713b1edbc 3352 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
AnnaBridge 171:3a7713b1edbc 3353 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
AnnaBridge 171:3a7713b1edbc 3354 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
AnnaBridge 171:3a7713b1edbc 3355 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 3356 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
AnnaBridge 171:3a7713b1edbc 3357 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 3358 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 3359 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 3360 } MTB_Type;
AnnaBridge 171:3a7713b1edbc 3361
AnnaBridge 171:3a7713b1edbc 3362 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3363 -- MTB Register Masks
AnnaBridge 171:3a7713b1edbc 3364 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3365
AnnaBridge 171:3a7713b1edbc 3366 /*!
AnnaBridge 171:3a7713b1edbc 3367 * @addtogroup MTB_Register_Masks MTB Register Masks
AnnaBridge 171:3a7713b1edbc 3368 * @{
AnnaBridge 171:3a7713b1edbc 3369 */
AnnaBridge 171:3a7713b1edbc 3370
AnnaBridge 171:3a7713b1edbc 3371 /* POSITION Bit Fields */
AnnaBridge 171:3a7713b1edbc 3372 #define MTB_POSITION_WRAP_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3373 #define MTB_POSITION_WRAP_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3374 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
AnnaBridge 171:3a7713b1edbc 3375 #define MTB_POSITION_POINTER_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3376 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
AnnaBridge 171:3a7713b1edbc 3377 /* MASTER Bit Fields */
AnnaBridge 171:3a7713b1edbc 3378 #define MTB_MASTER_MASK_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 3379 #define MTB_MASTER_MASK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3380 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
AnnaBridge 171:3a7713b1edbc 3381 #define MTB_MASTER_TSTARTEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3382 #define MTB_MASTER_TSTARTEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3383 #define MTB_MASTER_TSTOPEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3384 #define MTB_MASTER_TSTOPEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3385 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3386 #define MTB_MASTER_SFRWPRIV_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3387 #define MTB_MASTER_RAMPRIV_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 3388 #define MTB_MASTER_RAMPRIV_SHIFT 8
AnnaBridge 171:3a7713b1edbc 3389 #define MTB_MASTER_HALTREQ_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 3390 #define MTB_MASTER_HALTREQ_SHIFT 9
AnnaBridge 171:3a7713b1edbc 3391 #define MTB_MASTER_EN_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 3392 #define MTB_MASTER_EN_SHIFT 31
AnnaBridge 171:3a7713b1edbc 3393 /* FLOW Bit Fields */
AnnaBridge 171:3a7713b1edbc 3394 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3395 #define MTB_FLOW_AUTOSTOP_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3396 #define MTB_FLOW_AUTOHALT_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3397 #define MTB_FLOW_AUTOHALT_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3398 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
AnnaBridge 171:3a7713b1edbc 3399 #define MTB_FLOW_WATERMARK_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3400 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
AnnaBridge 171:3a7713b1edbc 3401 /* BASE Bit Fields */
AnnaBridge 171:3a7713b1edbc 3402 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3403 #define MTB_BASE_BASEADDR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3404 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
AnnaBridge 171:3a7713b1edbc 3405 /* MODECTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3406 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3407 #define MTB_MODECTRL_MODECTRL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3408 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
AnnaBridge 171:3a7713b1edbc 3409 /* TAGSET Bit Fields */
AnnaBridge 171:3a7713b1edbc 3410 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3411 #define MTB_TAGSET_TAGSET_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3412 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
AnnaBridge 171:3a7713b1edbc 3413 /* TAGCLEAR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3414 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3415 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3416 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
AnnaBridge 171:3a7713b1edbc 3417 /* LOCKACCESS Bit Fields */
AnnaBridge 171:3a7713b1edbc 3418 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3419 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3420 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
AnnaBridge 171:3a7713b1edbc 3421 /* LOCKSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3422 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3423 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3424 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 3425 /* AUTHSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3426 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3427 #define MTB_AUTHSTAT_BIT0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3428 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3429 #define MTB_AUTHSTAT_BIT1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3430 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3431 #define MTB_AUTHSTAT_BIT2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3432 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3433 #define MTB_AUTHSTAT_BIT3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3434 /* DEVICEARCH Bit Fields */
AnnaBridge 171:3a7713b1edbc 3435 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3436 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3437 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
AnnaBridge 171:3a7713b1edbc 3438 /* DEVICECFG Bit Fields */
AnnaBridge 171:3a7713b1edbc 3439 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3440 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3441 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
AnnaBridge 171:3a7713b1edbc 3442 /* DEVICETYPID Bit Fields */
AnnaBridge 171:3a7713b1edbc 3443 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3444 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3445 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
AnnaBridge 171:3a7713b1edbc 3446 /* PERIPHID Bit Fields */
AnnaBridge 171:3a7713b1edbc 3447 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3448 #define MTB_PERIPHID_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3449 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 3450 /* COMPID Bit Fields */
AnnaBridge 171:3a7713b1edbc 3451 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3452 #define MTB_COMPID_COMPID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3453 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 3454
AnnaBridge 171:3a7713b1edbc 3455 /*!
AnnaBridge 171:3a7713b1edbc 3456 * @}
AnnaBridge 171:3a7713b1edbc 3457 */ /* end of group MTB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3458
AnnaBridge 171:3a7713b1edbc 3459
AnnaBridge 171:3a7713b1edbc 3460 /* MTB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3461 /** Peripheral MTB base address */
AnnaBridge 171:3a7713b1edbc 3462 #define MTB_BASE (0xF0000000u)
AnnaBridge 171:3a7713b1edbc 3463 /** Peripheral MTB base pointer */
AnnaBridge 171:3a7713b1edbc 3464 #define MTB ((MTB_Type *)MTB_BASE)
AnnaBridge 171:3a7713b1edbc 3465 /** Array initializer of MTB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3466 #define MTB_BASES { MTB }
AnnaBridge 171:3a7713b1edbc 3467
AnnaBridge 171:3a7713b1edbc 3468 /*!
AnnaBridge 171:3a7713b1edbc 3469 * @}
AnnaBridge 171:3a7713b1edbc 3470 */ /* end of group MTB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3471
AnnaBridge 171:3a7713b1edbc 3472
AnnaBridge 171:3a7713b1edbc 3473 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3474 -- MTBDWT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3475 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3476
AnnaBridge 171:3a7713b1edbc 3477 /*!
AnnaBridge 171:3a7713b1edbc 3478 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3479 * @{
AnnaBridge 171:3a7713b1edbc 3480 */
AnnaBridge 171:3a7713b1edbc 3481
AnnaBridge 171:3a7713b1edbc 3482 /** MTBDWT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3483 typedef struct {
AnnaBridge 171:3a7713b1edbc 3484 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3485 uint8_t RESERVED_0[28];
AnnaBridge 171:3a7713b1edbc 3486 struct { /* offset: 0x20, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3487 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3488 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3489 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3490 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 3491 } COMPARATOR[2];
AnnaBridge 171:3a7713b1edbc 3492 uint8_t RESERVED_1[448];
AnnaBridge 171:3a7713b1edbc 3493 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
AnnaBridge 171:3a7713b1edbc 3494 uint8_t RESERVED_2[3524];
AnnaBridge 171:3a7713b1edbc 3495 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
AnnaBridge 171:3a7713b1edbc 3496 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 3497 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 3498 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 3499 } MTBDWT_Type;
AnnaBridge 171:3a7713b1edbc 3500
AnnaBridge 171:3a7713b1edbc 3501 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3502 -- MTBDWT Register Masks
AnnaBridge 171:3a7713b1edbc 3503 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3504
AnnaBridge 171:3a7713b1edbc 3505 /*!
AnnaBridge 171:3a7713b1edbc 3506 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
AnnaBridge 171:3a7713b1edbc 3507 * @{
AnnaBridge 171:3a7713b1edbc 3508 */
AnnaBridge 171:3a7713b1edbc 3509
AnnaBridge 171:3a7713b1edbc 3510 /* CTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3511 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3512 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3513 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
AnnaBridge 171:3a7713b1edbc 3514 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
AnnaBridge 171:3a7713b1edbc 3515 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
AnnaBridge 171:3a7713b1edbc 3516 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
AnnaBridge 171:3a7713b1edbc 3517 /* COMP Bit Fields */
AnnaBridge 171:3a7713b1edbc 3518 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3519 #define MTBDWT_COMP_COMP_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3520 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
AnnaBridge 171:3a7713b1edbc 3521 /* MASK Bit Fields */
AnnaBridge 171:3a7713b1edbc 3522 #define MTBDWT_MASK_MASK_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 3523 #define MTBDWT_MASK_MASK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3524 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
AnnaBridge 171:3a7713b1edbc 3525 /* FCT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3526 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 3527 #define MTBDWT_FCT_FUNCTION_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3528 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
AnnaBridge 171:3a7713b1edbc 3529 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 3530 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
AnnaBridge 171:3a7713b1edbc 3531 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
AnnaBridge 171:3a7713b1edbc 3532 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
AnnaBridge 171:3a7713b1edbc 3533 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 3534 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
AnnaBridge 171:3a7713b1edbc 3535 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
AnnaBridge 171:3a7713b1edbc 3536 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
AnnaBridge 171:3a7713b1edbc 3537 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 3538 #define MTBDWT_FCT_MATCHED_SHIFT 24
AnnaBridge 171:3a7713b1edbc 3539 /* TBCTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3540 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3541 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3542 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3543 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3544 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
AnnaBridge 171:3a7713b1edbc 3545 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
AnnaBridge 171:3a7713b1edbc 3546 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
AnnaBridge 171:3a7713b1edbc 3547 /* DEVICECFG Bit Fields */
AnnaBridge 171:3a7713b1edbc 3548 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3549 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3550 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
AnnaBridge 171:3a7713b1edbc 3551 /* DEVICETYPID Bit Fields */
AnnaBridge 171:3a7713b1edbc 3552 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3553 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3554 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
AnnaBridge 171:3a7713b1edbc 3555 /* PERIPHID Bit Fields */
AnnaBridge 171:3a7713b1edbc 3556 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3557 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3558 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 3559 /* COMPID Bit Fields */
AnnaBridge 171:3a7713b1edbc 3560 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3561 #define MTBDWT_COMPID_COMPID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3562 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 3563
AnnaBridge 171:3a7713b1edbc 3564 /*!
AnnaBridge 171:3a7713b1edbc 3565 * @}
AnnaBridge 171:3a7713b1edbc 3566 */ /* end of group MTBDWT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3567
AnnaBridge 171:3a7713b1edbc 3568
AnnaBridge 171:3a7713b1edbc 3569 /* MTBDWT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3570 /** Peripheral MTBDWT base address */
AnnaBridge 171:3a7713b1edbc 3571 #define MTBDWT_BASE (0xF0001000u)
AnnaBridge 171:3a7713b1edbc 3572 /** Peripheral MTBDWT base pointer */
AnnaBridge 171:3a7713b1edbc 3573 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
AnnaBridge 171:3a7713b1edbc 3574 /** Array initializer of MTBDWT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3575 #define MTBDWT_BASES { MTBDWT }
AnnaBridge 171:3a7713b1edbc 3576
AnnaBridge 171:3a7713b1edbc 3577 /*!
AnnaBridge 171:3a7713b1edbc 3578 * @}
AnnaBridge 171:3a7713b1edbc 3579 */ /* end of group MTBDWT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3580
AnnaBridge 171:3a7713b1edbc 3581
AnnaBridge 171:3a7713b1edbc 3582 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3583 -- NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3584 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3585
AnnaBridge 171:3a7713b1edbc 3586 /*!
AnnaBridge 171:3a7713b1edbc 3587 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3588 * @{
AnnaBridge 171:3a7713b1edbc 3589 */
AnnaBridge 171:3a7713b1edbc 3590
AnnaBridge 171:3a7713b1edbc 3591 /** NV - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3592 typedef struct {
AnnaBridge 171:3a7713b1edbc 3593 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3594 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3595 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3596 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3597 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3598 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3599 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3600 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3601 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3602 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 3603 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 3604 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 3605 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3606 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 3607 } NV_Type;
AnnaBridge 171:3a7713b1edbc 3608
AnnaBridge 171:3a7713b1edbc 3609 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3610 -- NV Register Masks
AnnaBridge 171:3a7713b1edbc 3611 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3612
AnnaBridge 171:3a7713b1edbc 3613 /*!
AnnaBridge 171:3a7713b1edbc 3614 * @addtogroup NV_Register_Masks NV Register Masks
AnnaBridge 171:3a7713b1edbc 3615 * @{
AnnaBridge 171:3a7713b1edbc 3616 */
AnnaBridge 171:3a7713b1edbc 3617
AnnaBridge 171:3a7713b1edbc 3618 /* BACKKEY3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3619 #define NV_BACKKEY3_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3620 #define NV_BACKKEY3_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3621 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3622 /* BACKKEY2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3623 #define NV_BACKKEY2_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3624 #define NV_BACKKEY2_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3625 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3626 /* BACKKEY1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3627 #define NV_BACKKEY1_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3628 #define NV_BACKKEY1_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3629 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3630 /* BACKKEY0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3631 #define NV_BACKKEY0_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3632 #define NV_BACKKEY0_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3633 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3634 /* BACKKEY7 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3635 #define NV_BACKKEY7_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3636 #define NV_BACKKEY7_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3637 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3638 /* BACKKEY6 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3639 #define NV_BACKKEY6_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3640 #define NV_BACKKEY6_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3641 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3642 /* BACKKEY5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3643 #define NV_BACKKEY5_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3644 #define NV_BACKKEY5_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3645 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3646 /* BACKKEY4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3647 #define NV_BACKKEY4_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3648 #define NV_BACKKEY4_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3649 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3650 /* FPROT3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3651 #define NV_FPROT3_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3652 #define NV_FPROT3_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3653 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 3654 /* FPROT2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3655 #define NV_FPROT2_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3656 #define NV_FPROT2_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3657 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 3658 /* FPROT1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3659 #define NV_FPROT1_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3660 #define NV_FPROT1_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3661 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 3662 /* FPROT0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3663 #define NV_FPROT0_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3664 #define NV_FPROT0_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3665 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 3666 /* FSEC Bit Fields */
AnnaBridge 171:3a7713b1edbc 3667 #define NV_FSEC_SEC_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 3668 #define NV_FSEC_SEC_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3669 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 3670 #define NV_FSEC_FSLACC_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 3671 #define NV_FSEC_FSLACC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3672 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 3673 #define NV_FSEC_MEEN_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 3674 #define NV_FSEC_MEEN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3675 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 3676 #define NV_FSEC_KEYEN_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 3677 #define NV_FSEC_KEYEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3678 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 3679 /* FOPT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3680 #define NV_FOPT_LPBOOT0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3681 #define NV_FOPT_LPBOOT0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3682 #define NV_FOPT_NMI_DIS_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3683 #define NV_FOPT_NMI_DIS_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3684 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3685 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3686 #define NV_FOPT_LPBOOT1_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3687 #define NV_FOPT_LPBOOT1_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3688 #define NV_FOPT_FAST_INIT_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3689 #define NV_FOPT_FAST_INIT_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3690
AnnaBridge 171:3a7713b1edbc 3691 /*!
AnnaBridge 171:3a7713b1edbc 3692 * @}
AnnaBridge 171:3a7713b1edbc 3693 */ /* end of group NV_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3694
AnnaBridge 171:3a7713b1edbc 3695
AnnaBridge 171:3a7713b1edbc 3696 /* NV - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3697 /** Peripheral FTFA_FlashConfig base address */
AnnaBridge 171:3a7713b1edbc 3698 #define FTFA_FlashConfig_BASE (0x400u)
AnnaBridge 171:3a7713b1edbc 3699 /** Peripheral FTFA_FlashConfig base pointer */
AnnaBridge 171:3a7713b1edbc 3700 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
AnnaBridge 171:3a7713b1edbc 3701 /** Array initializer of NV peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3702 #define NV_BASES { FTFA_FlashConfig }
AnnaBridge 171:3a7713b1edbc 3703
AnnaBridge 171:3a7713b1edbc 3704 /*!
AnnaBridge 171:3a7713b1edbc 3705 * @}
AnnaBridge 171:3a7713b1edbc 3706 */ /* end of group NV_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3707
AnnaBridge 171:3a7713b1edbc 3708
AnnaBridge 171:3a7713b1edbc 3709 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3710 -- OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3711 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3712
AnnaBridge 171:3a7713b1edbc 3713 /*!
AnnaBridge 171:3a7713b1edbc 3714 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3715 * @{
AnnaBridge 171:3a7713b1edbc 3716 */
AnnaBridge 171:3a7713b1edbc 3717
AnnaBridge 171:3a7713b1edbc 3718 /** OSC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3719 typedef struct {
AnnaBridge 171:3a7713b1edbc 3720 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3721 } OSC_Type;
AnnaBridge 171:3a7713b1edbc 3722
AnnaBridge 171:3a7713b1edbc 3723 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3724 -- OSC Register Masks
AnnaBridge 171:3a7713b1edbc 3725 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3726
AnnaBridge 171:3a7713b1edbc 3727 /*!
AnnaBridge 171:3a7713b1edbc 3728 * @addtogroup OSC_Register_Masks OSC Register Masks
AnnaBridge 171:3a7713b1edbc 3729 * @{
AnnaBridge 171:3a7713b1edbc 3730 */
AnnaBridge 171:3a7713b1edbc 3731
AnnaBridge 171:3a7713b1edbc 3732 /* CR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3733 #define OSC_CR_SC16P_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3734 #define OSC_CR_SC16P_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3735 #define OSC_CR_SC8P_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3736 #define OSC_CR_SC8P_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3737 #define OSC_CR_SC4P_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3738 #define OSC_CR_SC4P_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3739 #define OSC_CR_SC2P_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3740 #define OSC_CR_SC2P_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3741 #define OSC_CR_EREFSTEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3742 #define OSC_CR_EREFSTEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3743 #define OSC_CR_ERCLKEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3744 #define OSC_CR_ERCLKEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3745
AnnaBridge 171:3a7713b1edbc 3746 /*!
AnnaBridge 171:3a7713b1edbc 3747 * @}
AnnaBridge 171:3a7713b1edbc 3748 */ /* end of group OSC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3749
AnnaBridge 171:3a7713b1edbc 3750
AnnaBridge 171:3a7713b1edbc 3751 /* OSC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3752 /** Peripheral OSC0 base address */
AnnaBridge 171:3a7713b1edbc 3753 #define OSC0_BASE (0x40065000u)
AnnaBridge 171:3a7713b1edbc 3754 /** Peripheral OSC0 base pointer */
AnnaBridge 171:3a7713b1edbc 3755 #define OSC0 ((OSC_Type *)OSC0_BASE)
AnnaBridge 171:3a7713b1edbc 3756 /** Array initializer of OSC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3757 #define OSC_BASES { OSC0 }
AnnaBridge 171:3a7713b1edbc 3758
AnnaBridge 171:3a7713b1edbc 3759 /*!
AnnaBridge 171:3a7713b1edbc 3760 * @}
AnnaBridge 171:3a7713b1edbc 3761 */ /* end of group OSC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3762
AnnaBridge 171:3a7713b1edbc 3763
AnnaBridge 171:3a7713b1edbc 3764 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3765 -- PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3766 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3767
AnnaBridge 171:3a7713b1edbc 3768 /*!
AnnaBridge 171:3a7713b1edbc 3769 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3770 * @{
AnnaBridge 171:3a7713b1edbc 3771 */
AnnaBridge 171:3a7713b1edbc 3772
AnnaBridge 171:3a7713b1edbc 3773 /** PIT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3774 typedef struct {
AnnaBridge 171:3a7713b1edbc 3775 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3776 uint8_t RESERVED_0[220];
AnnaBridge 171:3a7713b1edbc 3777 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
AnnaBridge 171:3a7713b1edbc 3778 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
AnnaBridge 171:3a7713b1edbc 3779 uint8_t RESERVED_1[24];
AnnaBridge 171:3a7713b1edbc 3780 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3781 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3782 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3783 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3784 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3785 } CHANNEL[2];
AnnaBridge 171:3a7713b1edbc 3786 } PIT_Type;
AnnaBridge 171:3a7713b1edbc 3787
AnnaBridge 171:3a7713b1edbc 3788 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3789 -- PIT Register Masks
AnnaBridge 171:3a7713b1edbc 3790 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3791
AnnaBridge 171:3a7713b1edbc 3792 /*!
AnnaBridge 171:3a7713b1edbc 3793 * @addtogroup PIT_Register_Masks PIT Register Masks
AnnaBridge 171:3a7713b1edbc 3794 * @{
AnnaBridge 171:3a7713b1edbc 3795 */
AnnaBridge 171:3a7713b1edbc 3796
AnnaBridge 171:3a7713b1edbc 3797 /* MCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3798 #define PIT_MCR_FRZ_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3799 #define PIT_MCR_FRZ_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3800 #define PIT_MCR_MDIS_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3801 #define PIT_MCR_MDIS_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3802 /* LTMR64H Bit Fields */
AnnaBridge 171:3a7713b1edbc 3803 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3804 #define PIT_LTMR64H_LTH_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3805 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
AnnaBridge 171:3a7713b1edbc 3806 /* LTMR64L Bit Fields */
AnnaBridge 171:3a7713b1edbc 3807 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3808 #define PIT_LTMR64L_LTL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3809 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
AnnaBridge 171:3a7713b1edbc 3810 /* LDVAL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3811 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3812 #define PIT_LDVAL_TSV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3813 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
AnnaBridge 171:3a7713b1edbc 3814 /* CVAL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3815 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3816 #define PIT_CVAL_TVL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3817 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
AnnaBridge 171:3a7713b1edbc 3818 /* TCTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3819 #define PIT_TCTRL_TEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3820 #define PIT_TCTRL_TEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3821 #define PIT_TCTRL_TIE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3822 #define PIT_TCTRL_TIE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3823 #define PIT_TCTRL_CHN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3824 #define PIT_TCTRL_CHN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3825 /* TFLG Bit Fields */
AnnaBridge 171:3a7713b1edbc 3826 #define PIT_TFLG_TIF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3827 #define PIT_TFLG_TIF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3828
AnnaBridge 171:3a7713b1edbc 3829 /*!
AnnaBridge 171:3a7713b1edbc 3830 * @}
AnnaBridge 171:3a7713b1edbc 3831 */ /* end of group PIT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3832
AnnaBridge 171:3a7713b1edbc 3833
AnnaBridge 171:3a7713b1edbc 3834 /* PIT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3835 /** Peripheral PIT base address */
AnnaBridge 171:3a7713b1edbc 3836 #define PIT_BASE (0x40037000u)
AnnaBridge 171:3a7713b1edbc 3837 /** Peripheral PIT base pointer */
AnnaBridge 171:3a7713b1edbc 3838 #define PIT ((PIT_Type *)PIT_BASE)
AnnaBridge 171:3a7713b1edbc 3839 /** Array initializer of PIT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3840 #define PIT_BASES { PIT }
AnnaBridge 171:3a7713b1edbc 3841
AnnaBridge 171:3a7713b1edbc 3842 /*!
AnnaBridge 171:3a7713b1edbc 3843 * @}
AnnaBridge 171:3a7713b1edbc 3844 */ /* end of group PIT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3845
AnnaBridge 171:3a7713b1edbc 3846
AnnaBridge 171:3a7713b1edbc 3847 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3848 -- PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3849 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3850
AnnaBridge 171:3a7713b1edbc 3851 /*!
AnnaBridge 171:3a7713b1edbc 3852 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3853 * @{
AnnaBridge 171:3a7713b1edbc 3854 */
AnnaBridge 171:3a7713b1edbc 3855
AnnaBridge 171:3a7713b1edbc 3856 /** PMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3857 typedef struct {
AnnaBridge 171:3a7713b1edbc 3858 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3859 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3860 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3861 } PMC_Type;
AnnaBridge 171:3a7713b1edbc 3862
AnnaBridge 171:3a7713b1edbc 3863 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3864 -- PMC Register Masks
AnnaBridge 171:3a7713b1edbc 3865 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3866
AnnaBridge 171:3a7713b1edbc 3867 /*!
AnnaBridge 171:3a7713b1edbc 3868 * @addtogroup PMC_Register_Masks PMC Register Masks
AnnaBridge 171:3a7713b1edbc 3869 * @{
AnnaBridge 171:3a7713b1edbc 3870 */
AnnaBridge 171:3a7713b1edbc 3871
AnnaBridge 171:3a7713b1edbc 3872 /* LVDSC1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3873 #define PMC_LVDSC1_LVDV_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 3874 #define PMC_LVDSC1_LVDV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3875 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
AnnaBridge 171:3a7713b1edbc 3876 #define PMC_LVDSC1_LVDRE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3877 #define PMC_LVDSC1_LVDRE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3878 #define PMC_LVDSC1_LVDIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3879 #define PMC_LVDSC1_LVDIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3880 #define PMC_LVDSC1_LVDACK_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3881 #define PMC_LVDSC1_LVDACK_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3882 #define PMC_LVDSC1_LVDF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3883 #define PMC_LVDSC1_LVDF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3884 /* LVDSC2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3885 #define PMC_LVDSC2_LVWV_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 3886 #define PMC_LVDSC2_LVWV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3887 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
AnnaBridge 171:3a7713b1edbc 3888 #define PMC_LVDSC2_LVWIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3889 #define PMC_LVDSC2_LVWIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3890 #define PMC_LVDSC2_LVWACK_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3891 #define PMC_LVDSC2_LVWACK_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3892 #define PMC_LVDSC2_LVWF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3893 #define PMC_LVDSC2_LVWF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3894 /* REGSC Bit Fields */
AnnaBridge 171:3a7713b1edbc 3895 #define PMC_REGSC_BGBE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3896 #define PMC_REGSC_BGBE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3897 #define PMC_REGSC_REGONS_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3898 #define PMC_REGSC_REGONS_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3899 #define PMC_REGSC_ACKISO_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3900 #define PMC_REGSC_ACKISO_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3901 #define PMC_REGSC_BGEN_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3902 #define PMC_REGSC_BGEN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3903
AnnaBridge 171:3a7713b1edbc 3904 /*!
AnnaBridge 171:3a7713b1edbc 3905 * @}
AnnaBridge 171:3a7713b1edbc 3906 */ /* end of group PMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3907
AnnaBridge 171:3a7713b1edbc 3908
AnnaBridge 171:3a7713b1edbc 3909 /* PMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3910 /** Peripheral PMC base address */
AnnaBridge 171:3a7713b1edbc 3911 #define PMC_BASE (0x4007D000u)
AnnaBridge 171:3a7713b1edbc 3912 /** Peripheral PMC base pointer */
AnnaBridge 171:3a7713b1edbc 3913 #define PMC ((PMC_Type *)PMC_BASE)
AnnaBridge 171:3a7713b1edbc 3914 /** Array initializer of PMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3915 #define PMC_BASES { PMC }
AnnaBridge 171:3a7713b1edbc 3916
AnnaBridge 171:3a7713b1edbc 3917 /*!
AnnaBridge 171:3a7713b1edbc 3918 * @}
AnnaBridge 171:3a7713b1edbc 3919 */ /* end of group PMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3920
AnnaBridge 171:3a7713b1edbc 3921
AnnaBridge 171:3a7713b1edbc 3922 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3923 -- PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3924 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3925
AnnaBridge 171:3a7713b1edbc 3926 /*!
AnnaBridge 171:3a7713b1edbc 3927 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3928 * @{
AnnaBridge 171:3a7713b1edbc 3929 */
AnnaBridge 171:3a7713b1edbc 3930
AnnaBridge 171:3a7713b1edbc 3931 /** PORT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3932 typedef struct {
AnnaBridge 171:3a7713b1edbc 3933 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 3934 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 3935 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 3936 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 3937 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 3938 } PORT_Type;
AnnaBridge 171:3a7713b1edbc 3939
AnnaBridge 171:3a7713b1edbc 3940 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3941 -- PORT Register Masks
AnnaBridge 171:3a7713b1edbc 3942 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3943
AnnaBridge 171:3a7713b1edbc 3944 /*!
AnnaBridge 171:3a7713b1edbc 3945 * @addtogroup PORT_Register_Masks PORT Register Masks
AnnaBridge 171:3a7713b1edbc 3946 * @{
AnnaBridge 171:3a7713b1edbc 3947 */
AnnaBridge 171:3a7713b1edbc 3948
AnnaBridge 171:3a7713b1edbc 3949 /* PCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3950 #define PORT_PCR_PS_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3951 #define PORT_PCR_PS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3952 #define PORT_PCR_PE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3953 #define PORT_PCR_PE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3954 #define PORT_PCR_SRE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3955 #define PORT_PCR_SRE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3956 #define PORT_PCR_PFE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3957 #define PORT_PCR_PFE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3958 #define PORT_PCR_DSE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3959 #define PORT_PCR_DSE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3960 #define PORT_PCR_MUX_MASK 0x700u
AnnaBridge 171:3a7713b1edbc 3961 #define PORT_PCR_MUX_SHIFT 8
AnnaBridge 171:3a7713b1edbc 3962 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
AnnaBridge 171:3a7713b1edbc 3963 #define PORT_PCR_IRQC_MASK 0xF0000u
AnnaBridge 171:3a7713b1edbc 3964 #define PORT_PCR_IRQC_SHIFT 16
AnnaBridge 171:3a7713b1edbc 3965 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
AnnaBridge 171:3a7713b1edbc 3966 #define PORT_PCR_ISF_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 3967 #define PORT_PCR_ISF_SHIFT 24
AnnaBridge 171:3a7713b1edbc 3968 /* GPCLR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3969 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 3970 #define PORT_GPCLR_GPWD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3971 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 3972 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
AnnaBridge 171:3a7713b1edbc 3973 #define PORT_GPCLR_GPWE_SHIFT 16
AnnaBridge 171:3a7713b1edbc 3974 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 3975 /* GPCHR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3976 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 3977 #define PORT_GPCHR_GPWD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3978 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 3979 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
AnnaBridge 171:3a7713b1edbc 3980 #define PORT_GPCHR_GPWE_SHIFT 16
AnnaBridge 171:3a7713b1edbc 3981 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 3982 /* ISFR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3983 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 3984 #define PORT_ISFR_ISF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3985 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 3986
AnnaBridge 171:3a7713b1edbc 3987 /*!
AnnaBridge 171:3a7713b1edbc 3988 * @}
AnnaBridge 171:3a7713b1edbc 3989 */ /* end of group PORT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3990
AnnaBridge 171:3a7713b1edbc 3991
AnnaBridge 171:3a7713b1edbc 3992 /* PORT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3993 /** Peripheral PORTA base address */
AnnaBridge 171:3a7713b1edbc 3994 #define PORTA_BASE (0x40049000u)
AnnaBridge 171:3a7713b1edbc 3995 /** Peripheral PORTA base pointer */
AnnaBridge 171:3a7713b1edbc 3996 #define PORTA ((PORT_Type *)PORTA_BASE)
AnnaBridge 171:3a7713b1edbc 3997 /** Peripheral PORTB base address */
AnnaBridge 171:3a7713b1edbc 3998 #define PORTB_BASE (0x4004A000u)
AnnaBridge 171:3a7713b1edbc 3999 /** Peripheral PORTB base pointer */
AnnaBridge 171:3a7713b1edbc 4000 #define PORTB ((PORT_Type *)PORTB_BASE)
AnnaBridge 171:3a7713b1edbc 4001 /** Peripheral PORTC base address */
AnnaBridge 171:3a7713b1edbc 4002 #define PORTC_BASE (0x4004B000u)
AnnaBridge 171:3a7713b1edbc 4003 /** Peripheral PORTC base pointer */
AnnaBridge 171:3a7713b1edbc 4004 #define PORTC ((PORT_Type *)PORTC_BASE)
AnnaBridge 171:3a7713b1edbc 4005 /** Peripheral PORTD base address */
AnnaBridge 171:3a7713b1edbc 4006 #define PORTD_BASE (0x4004C000u)
AnnaBridge 171:3a7713b1edbc 4007 /** Peripheral PORTD base pointer */
AnnaBridge 171:3a7713b1edbc 4008 #define PORTD ((PORT_Type *)PORTD_BASE)
AnnaBridge 171:3a7713b1edbc 4009 /** Peripheral PORTE base address */
AnnaBridge 171:3a7713b1edbc 4010 #define PORTE_BASE (0x4004D000u)
AnnaBridge 171:3a7713b1edbc 4011 /** Peripheral PORTE base pointer */
AnnaBridge 171:3a7713b1edbc 4012 #define PORTE ((PORT_Type *)PORTE_BASE)
AnnaBridge 171:3a7713b1edbc 4013 /** Array initializer of PORT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4014 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
AnnaBridge 171:3a7713b1edbc 4015
AnnaBridge 171:3a7713b1edbc 4016 /*!
AnnaBridge 171:3a7713b1edbc 4017 * @}
AnnaBridge 171:3a7713b1edbc 4018 */ /* end of group PORT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4019
AnnaBridge 171:3a7713b1edbc 4020
AnnaBridge 171:3a7713b1edbc 4021 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4022 -- RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4023 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4024
AnnaBridge 171:3a7713b1edbc 4025 /*!
AnnaBridge 171:3a7713b1edbc 4026 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4027 * @{
AnnaBridge 171:3a7713b1edbc 4028 */
AnnaBridge 171:3a7713b1edbc 4029
AnnaBridge 171:3a7713b1edbc 4030 /** RCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4031 typedef struct {
AnnaBridge 171:3a7713b1edbc 4032 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4033 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 4034 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 4035 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4036 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 4037 } RCM_Type;
AnnaBridge 171:3a7713b1edbc 4038
AnnaBridge 171:3a7713b1edbc 4039 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4040 -- RCM Register Masks
AnnaBridge 171:3a7713b1edbc 4041 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4042
AnnaBridge 171:3a7713b1edbc 4043 /*!
AnnaBridge 171:3a7713b1edbc 4044 * @addtogroup RCM_Register_Masks RCM Register Masks
AnnaBridge 171:3a7713b1edbc 4045 * @{
AnnaBridge 171:3a7713b1edbc 4046 */
AnnaBridge 171:3a7713b1edbc 4047
AnnaBridge 171:3a7713b1edbc 4048 /* SRS0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4049 #define RCM_SRS0_WAKEUP_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4050 #define RCM_SRS0_WAKEUP_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4051 #define RCM_SRS0_LVD_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4052 #define RCM_SRS0_LVD_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4053 #define RCM_SRS0_LOC_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4054 #define RCM_SRS0_LOC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4055 #define RCM_SRS0_LOL_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4056 #define RCM_SRS0_LOL_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4057 #define RCM_SRS0_WDOG_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4058 #define RCM_SRS0_WDOG_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4059 #define RCM_SRS0_PIN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4060 #define RCM_SRS0_PIN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4061 #define RCM_SRS0_POR_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4062 #define RCM_SRS0_POR_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4063 /* SRS1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4064 #define RCM_SRS1_LOCKUP_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4065 #define RCM_SRS1_LOCKUP_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4066 #define RCM_SRS1_SW_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4067 #define RCM_SRS1_SW_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4068 #define RCM_SRS1_MDM_AP_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4069 #define RCM_SRS1_MDM_AP_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4070 #define RCM_SRS1_SACKERR_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4071 #define RCM_SRS1_SACKERR_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4072 /* RPFC Bit Fields */
AnnaBridge 171:3a7713b1edbc 4073 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 4074 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4075 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
AnnaBridge 171:3a7713b1edbc 4076 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4077 #define RCM_RPFC_RSTFLTSS_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4078 /* RPFW Bit Fields */
AnnaBridge 171:3a7713b1edbc 4079 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 4080 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4081 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4082
AnnaBridge 171:3a7713b1edbc 4083 /*!
AnnaBridge 171:3a7713b1edbc 4084 * @}
AnnaBridge 171:3a7713b1edbc 4085 */ /* end of group RCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4086
AnnaBridge 171:3a7713b1edbc 4087
AnnaBridge 171:3a7713b1edbc 4088 /* RCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4089 /** Peripheral RCM base address */
AnnaBridge 171:3a7713b1edbc 4090 #define RCM_BASE (0x4007F000u)
AnnaBridge 171:3a7713b1edbc 4091 /** Peripheral RCM base pointer */
AnnaBridge 171:3a7713b1edbc 4092 #define RCM ((RCM_Type *)RCM_BASE)
AnnaBridge 171:3a7713b1edbc 4093 /** Array initializer of RCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4094 #define RCM_BASES { RCM }
AnnaBridge 171:3a7713b1edbc 4095
AnnaBridge 171:3a7713b1edbc 4096 /*!
AnnaBridge 171:3a7713b1edbc 4097 * @}
AnnaBridge 171:3a7713b1edbc 4098 */ /* end of group RCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4099
AnnaBridge 171:3a7713b1edbc 4100
AnnaBridge 171:3a7713b1edbc 4101 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4102 -- ROM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4103 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4104
AnnaBridge 171:3a7713b1edbc 4105 /*!
AnnaBridge 171:3a7713b1edbc 4106 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4107 * @{
AnnaBridge 171:3a7713b1edbc 4108 */
AnnaBridge 171:3a7713b1edbc 4109
AnnaBridge 171:3a7713b1edbc 4110 /** ROM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4111 typedef struct {
AnnaBridge 171:3a7713b1edbc 4112 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 4113 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 4114 uint8_t RESERVED_0[4028];
AnnaBridge 171:3a7713b1edbc 4115 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 4116 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
AnnaBridge 171:3a7713b1edbc 4117 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
AnnaBridge 171:3a7713b1edbc 4118 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
AnnaBridge 171:3a7713b1edbc 4119 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
AnnaBridge 171:3a7713b1edbc 4120 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
AnnaBridge 171:3a7713b1edbc 4121 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
AnnaBridge 171:3a7713b1edbc 4122 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
AnnaBridge 171:3a7713b1edbc 4123 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
AnnaBridge 171:3a7713b1edbc 4124 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 4125 } ROM_Type;
AnnaBridge 171:3a7713b1edbc 4126
AnnaBridge 171:3a7713b1edbc 4127 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4128 -- ROM Register Masks
AnnaBridge 171:3a7713b1edbc 4129 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4130
AnnaBridge 171:3a7713b1edbc 4131 /*!
AnnaBridge 171:3a7713b1edbc 4132 * @addtogroup ROM_Register_Masks ROM Register Masks
AnnaBridge 171:3a7713b1edbc 4133 * @{
AnnaBridge 171:3a7713b1edbc 4134 */
AnnaBridge 171:3a7713b1edbc 4135
AnnaBridge 171:3a7713b1edbc 4136 /* ENTRY Bit Fields */
AnnaBridge 171:3a7713b1edbc 4137 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4138 #define ROM_ENTRY_ENTRY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4139 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
AnnaBridge 171:3a7713b1edbc 4140 /* TABLEMARK Bit Fields */
AnnaBridge 171:3a7713b1edbc 4141 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4142 #define ROM_TABLEMARK_MARK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4143 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
AnnaBridge 171:3a7713b1edbc 4144 /* SYSACCESS Bit Fields */
AnnaBridge 171:3a7713b1edbc 4145 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4146 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4147 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
AnnaBridge 171:3a7713b1edbc 4148 /* PERIPHID4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4149 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4150 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4151 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4152 /* PERIPHID5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4153 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4154 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4155 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4156 /* PERIPHID6 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4157 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4158 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4159 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4160 /* PERIPHID7 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4161 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4162 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4163 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4164 /* PERIPHID0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4165 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4166 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4167 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4168 /* PERIPHID1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4169 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4170 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4171 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4172 /* PERIPHID2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4173 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4174 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4175 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4176 /* PERIPHID3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4177 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4178 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4179 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4180 /* COMPID Bit Fields */
AnnaBridge 171:3a7713b1edbc 4181 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4182 #define ROM_COMPID_COMPID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4183 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 4184
AnnaBridge 171:3a7713b1edbc 4185 /*!
AnnaBridge 171:3a7713b1edbc 4186 * @}
AnnaBridge 171:3a7713b1edbc 4187 */ /* end of group ROM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4188
AnnaBridge 171:3a7713b1edbc 4189
AnnaBridge 171:3a7713b1edbc 4190 /* ROM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4191 /** Peripheral ROM base address */
AnnaBridge 171:3a7713b1edbc 4192 #define ROM_BASE (0xF0002000u)
AnnaBridge 171:3a7713b1edbc 4193 /** Peripheral ROM base pointer */
AnnaBridge 171:3a7713b1edbc 4194 #define ROM ((ROM_Type *)ROM_BASE)
AnnaBridge 171:3a7713b1edbc 4195 /** Array initializer of ROM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4196 #define ROM_BASES { ROM }
AnnaBridge 171:3a7713b1edbc 4197
AnnaBridge 171:3a7713b1edbc 4198 /*!
AnnaBridge 171:3a7713b1edbc 4199 * @}
AnnaBridge 171:3a7713b1edbc 4200 */ /* end of group ROM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4201
AnnaBridge 171:3a7713b1edbc 4202
AnnaBridge 171:3a7713b1edbc 4203 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4204 -- RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4205 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4206
AnnaBridge 171:3a7713b1edbc 4207 /*!
AnnaBridge 171:3a7713b1edbc 4208 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4209 * @{
AnnaBridge 171:3a7713b1edbc 4210 */
AnnaBridge 171:3a7713b1edbc 4211
AnnaBridge 171:3a7713b1edbc 4212 /** RTC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4213 typedef struct {
AnnaBridge 171:3a7713b1edbc 4214 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4215 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4216 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4217 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 4218 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 4219 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 4220 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 4221 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 4222 } RTC_Type;
AnnaBridge 171:3a7713b1edbc 4223
AnnaBridge 171:3a7713b1edbc 4224 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4225 -- RTC Register Masks
AnnaBridge 171:3a7713b1edbc 4226 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4227
AnnaBridge 171:3a7713b1edbc 4228 /*!
AnnaBridge 171:3a7713b1edbc 4229 * @addtogroup RTC_Register_Masks RTC Register Masks
AnnaBridge 171:3a7713b1edbc 4230 * @{
AnnaBridge 171:3a7713b1edbc 4231 */
AnnaBridge 171:3a7713b1edbc 4232
AnnaBridge 171:3a7713b1edbc 4233 /* TSR Bit Fields */
AnnaBridge 171:3a7713b1edbc 4234 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4235 #define RTC_TSR_TSR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4236 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
AnnaBridge 171:3a7713b1edbc 4237 /* TPR Bit Fields */
AnnaBridge 171:3a7713b1edbc 4238 #define RTC_TPR_TPR_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 4239 #define RTC_TPR_TPR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4240 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
AnnaBridge 171:3a7713b1edbc 4241 /* TAR Bit Fields */
AnnaBridge 171:3a7713b1edbc 4242 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4243 #define RTC_TAR_TAR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4244 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
AnnaBridge 171:3a7713b1edbc 4245 /* TCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 4246 #define RTC_TCR_TCR_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 4247 #define RTC_TCR_TCR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4248 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
AnnaBridge 171:3a7713b1edbc 4249 #define RTC_TCR_CIR_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 4250 #define RTC_TCR_CIR_SHIFT 8
AnnaBridge 171:3a7713b1edbc 4251 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
AnnaBridge 171:3a7713b1edbc 4252 #define RTC_TCR_TCV_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 4253 #define RTC_TCR_TCV_SHIFT 16
AnnaBridge 171:3a7713b1edbc 4254 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
AnnaBridge 171:3a7713b1edbc 4255 #define RTC_TCR_CIC_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 4256 #define RTC_TCR_CIC_SHIFT 24
AnnaBridge 171:3a7713b1edbc 4257 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
AnnaBridge 171:3a7713b1edbc 4258 /* CR Bit Fields */
AnnaBridge 171:3a7713b1edbc 4259 #define RTC_CR_SWR_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4260 #define RTC_CR_SWR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4261 #define RTC_CR_WPE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4262 #define RTC_CR_WPE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4263 #define RTC_CR_SUP_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4264 #define RTC_CR_SUP_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4265 #define RTC_CR_UM_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4266 #define RTC_CR_UM_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4267 #define RTC_CR_OSCE_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 4268 #define RTC_CR_OSCE_SHIFT 8
AnnaBridge 171:3a7713b1edbc 4269 #define RTC_CR_CLKO_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 4270 #define RTC_CR_CLKO_SHIFT 9
AnnaBridge 171:3a7713b1edbc 4271 #define RTC_CR_SC16P_MASK 0x400u
AnnaBridge 171:3a7713b1edbc 4272 #define RTC_CR_SC16P_SHIFT 10
AnnaBridge 171:3a7713b1edbc 4273 #define RTC_CR_SC8P_MASK 0x800u
AnnaBridge 171:3a7713b1edbc 4274 #define RTC_CR_SC8P_SHIFT 11
AnnaBridge 171:3a7713b1edbc 4275 #define RTC_CR_SC4P_MASK 0x1000u
AnnaBridge 171:3a7713b1edbc 4276 #define RTC_CR_SC4P_SHIFT 12
AnnaBridge 171:3a7713b1edbc 4277 #define RTC_CR_SC2P_MASK 0x2000u
AnnaBridge 171:3a7713b1edbc 4278 #define RTC_CR_SC2P_SHIFT 13
AnnaBridge 171:3a7713b1edbc 4279 /* SR Bit Fields */
AnnaBridge 171:3a7713b1edbc 4280 #define RTC_SR_TIF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4281 #define RTC_SR_TIF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4282 #define RTC_SR_TOF_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4283 #define RTC_SR_TOF_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4284 #define RTC_SR_TAF_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4285 #define RTC_SR_TAF_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4286 #define RTC_SR_TCE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4287 #define RTC_SR_TCE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4288 /* LR Bit Fields */
AnnaBridge 171:3a7713b1edbc 4289 #define RTC_LR_TCL_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4290 #define RTC_LR_TCL_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4291 #define RTC_LR_CRL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4292 #define RTC_LR_CRL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4293 #define RTC_LR_SRL_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4294 #define RTC_LR_SRL_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4295 #define RTC_LR_LRL_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4296 #define RTC_LR_LRL_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4297 /* IER Bit Fields */
AnnaBridge 171:3a7713b1edbc 4298 #define RTC_IER_TIIE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4299 #define RTC_IER_TIIE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4300 #define RTC_IER_TOIE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4301 #define RTC_IER_TOIE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4302 #define RTC_IER_TAIE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4303 #define RTC_IER_TAIE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4304 #define RTC_IER_TSIE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4305 #define RTC_IER_TSIE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4306 #define RTC_IER_WPON_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4307 #define RTC_IER_WPON_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4308
AnnaBridge 171:3a7713b1edbc 4309 /*!
AnnaBridge 171:3a7713b1edbc 4310 * @}
AnnaBridge 171:3a7713b1edbc 4311 */ /* end of group RTC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4312
AnnaBridge 171:3a7713b1edbc 4313
AnnaBridge 171:3a7713b1edbc 4314 /* RTC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4315 /** Peripheral RTC base address */
AnnaBridge 171:3a7713b1edbc 4316 #define RTC_BASE (0x4003D000u)
AnnaBridge 171:3a7713b1edbc 4317 /** Peripheral RTC base pointer */
AnnaBridge 171:3a7713b1edbc 4318 #define RTC ((RTC_Type *)RTC_BASE)
AnnaBridge 171:3a7713b1edbc 4319 /** Array initializer of RTC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4320 #define RTC_BASES { RTC }
AnnaBridge 171:3a7713b1edbc 4321
AnnaBridge 171:3a7713b1edbc 4322 /*!
AnnaBridge 171:3a7713b1edbc 4323 * @}
AnnaBridge 171:3a7713b1edbc 4324 */ /* end of group RTC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4325
AnnaBridge 171:3a7713b1edbc 4326
AnnaBridge 171:3a7713b1edbc 4327 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4328 -- SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4329 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4330
AnnaBridge 171:3a7713b1edbc 4331 /*!
AnnaBridge 171:3a7713b1edbc 4332 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4333 * @{
AnnaBridge 171:3a7713b1edbc 4334 */
AnnaBridge 171:3a7713b1edbc 4335
AnnaBridge 171:3a7713b1edbc 4336 /** SIM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4337 typedef struct {
AnnaBridge 171:3a7713b1edbc 4338 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4339 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4340 uint8_t RESERVED_0[4092];
AnnaBridge 171:3a7713b1edbc 4341 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
AnnaBridge 171:3a7713b1edbc 4342 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 4343 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
AnnaBridge 171:3a7713b1edbc 4344 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
AnnaBridge 171:3a7713b1edbc 4345 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 4346 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
AnnaBridge 171:3a7713b1edbc 4347 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 4348 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
AnnaBridge 171:3a7713b1edbc 4349 uint8_t RESERVED_4[12];
AnnaBridge 171:3a7713b1edbc 4350 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
AnnaBridge 171:3a7713b1edbc 4351 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
AnnaBridge 171:3a7713b1edbc 4352 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
AnnaBridge 171:3a7713b1edbc 4353 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
AnnaBridge 171:3a7713b1edbc 4354 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
AnnaBridge 171:3a7713b1edbc 4355 uint8_t RESERVED_5[4];
AnnaBridge 171:3a7713b1edbc 4356 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
AnnaBridge 171:3a7713b1edbc 4357 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
AnnaBridge 171:3a7713b1edbc 4358 uint8_t RESERVED_6[4];
AnnaBridge 171:3a7713b1edbc 4359 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
AnnaBridge 171:3a7713b1edbc 4360 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
AnnaBridge 171:3a7713b1edbc 4361 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
AnnaBridge 171:3a7713b1edbc 4362 uint8_t RESERVED_7[156];
AnnaBridge 171:3a7713b1edbc 4363 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
AnnaBridge 171:3a7713b1edbc 4364 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
AnnaBridge 171:3a7713b1edbc 4365 } SIM_Type;
AnnaBridge 171:3a7713b1edbc 4366
AnnaBridge 171:3a7713b1edbc 4367 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4368 -- SIM Register Masks
AnnaBridge 171:3a7713b1edbc 4369 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4370
AnnaBridge 171:3a7713b1edbc 4371 /*!
AnnaBridge 171:3a7713b1edbc 4372 * @addtogroup SIM_Register_Masks SIM Register Masks
AnnaBridge 171:3a7713b1edbc 4373 * @{
AnnaBridge 171:3a7713b1edbc 4374 */
AnnaBridge 171:3a7713b1edbc 4375
AnnaBridge 171:3a7713b1edbc 4376 /* SOPT1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4377 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
AnnaBridge 171:3a7713b1edbc 4378 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
AnnaBridge 171:3a7713b1edbc 4379 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4380 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
AnnaBridge 171:3a7713b1edbc 4381 #define SIM_SOPT1_USBVSTBY_SHIFT 29
AnnaBridge 171:3a7713b1edbc 4382 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
AnnaBridge 171:3a7713b1edbc 4383 #define SIM_SOPT1_USBSSTBY_SHIFT 30
AnnaBridge 171:3a7713b1edbc 4384 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 4385 #define SIM_SOPT1_USBREGEN_SHIFT 31
AnnaBridge 171:3a7713b1edbc 4386 /* SOPT1CFG Bit Fields */
AnnaBridge 171:3a7713b1edbc 4387 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 4388 #define SIM_SOPT1CFG_URWE_SHIFT 24
AnnaBridge 171:3a7713b1edbc 4389 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 4390 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
AnnaBridge 171:3a7713b1edbc 4391 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
AnnaBridge 171:3a7713b1edbc 4392 #define SIM_SOPT1CFG_USSWE_SHIFT 26
AnnaBridge 171:3a7713b1edbc 4393 /* SOPT2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4394 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4395 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4396 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
AnnaBridge 171:3a7713b1edbc 4397 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4398 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4399 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 4400 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
AnnaBridge 171:3a7713b1edbc 4401 #define SIM_SOPT2_USBSRC_MASK 0x40000u
AnnaBridge 171:3a7713b1edbc 4402 #define SIM_SOPT2_USBSRC_SHIFT 18
AnnaBridge 171:3a7713b1edbc 4403 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
AnnaBridge 171:3a7713b1edbc 4404 #define SIM_SOPT2_TPMSRC_SHIFT 24
AnnaBridge 171:3a7713b1edbc 4405 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4406 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
AnnaBridge 171:3a7713b1edbc 4407 #define SIM_SOPT2_UART0SRC_SHIFT 26
AnnaBridge 171:3a7713b1edbc 4408 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 4409 /* SOPT4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4410 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
AnnaBridge 171:3a7713b1edbc 4411 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
AnnaBridge 171:3a7713b1edbc 4412 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 4413 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
AnnaBridge 171:3a7713b1edbc 4414 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
AnnaBridge 171:3a7713b1edbc 4415 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 4416 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
AnnaBridge 171:3a7713b1edbc 4417 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 4418 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
AnnaBridge 171:3a7713b1edbc 4419 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
AnnaBridge 171:3a7713b1edbc 4420 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
AnnaBridge 171:3a7713b1edbc 4421 /* SOPT5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4422 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 4423 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4424 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4425 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4426 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4427 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 4428 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4429 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4430 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4431 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4432 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 4433 #define SIM_SOPT5_UART0ODE_SHIFT 16
AnnaBridge 171:3a7713b1edbc 4434 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
AnnaBridge 171:3a7713b1edbc 4435 #define SIM_SOPT5_UART1ODE_SHIFT 17
AnnaBridge 171:3a7713b1edbc 4436 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
AnnaBridge 171:3a7713b1edbc 4437 #define SIM_SOPT5_UART2ODE_SHIFT 18
AnnaBridge 171:3a7713b1edbc 4438 /* SOPT7 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4439 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 4440 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4441 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4442 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4443 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4444 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4445 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4446 /* SDID Bit Fields */
AnnaBridge 171:3a7713b1edbc 4447 #define SIM_SDID_PINID_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 4448 #define SIM_SDID_PINID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4449 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
AnnaBridge 171:3a7713b1edbc 4450 #define SIM_SDID_DIEID_MASK 0xF80u
AnnaBridge 171:3a7713b1edbc 4451 #define SIM_SDID_DIEID_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4452 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
AnnaBridge 171:3a7713b1edbc 4453 #define SIM_SDID_REVID_MASK 0xF000u
AnnaBridge 171:3a7713b1edbc 4454 #define SIM_SDID_REVID_SHIFT 12
AnnaBridge 171:3a7713b1edbc 4455 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
AnnaBridge 171:3a7713b1edbc 4456 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
AnnaBridge 171:3a7713b1edbc 4457 #define SIM_SDID_SRAMSIZE_SHIFT 16
AnnaBridge 171:3a7713b1edbc 4458 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 4459 #define SIM_SDID_SERIESID_MASK 0xF00000u
AnnaBridge 171:3a7713b1edbc 4460 #define SIM_SDID_SERIESID_SHIFT 20
AnnaBridge 171:3a7713b1edbc 4461 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
AnnaBridge 171:3a7713b1edbc 4462 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
AnnaBridge 171:3a7713b1edbc 4463 #define SIM_SDID_SUBFAMID_SHIFT 24
AnnaBridge 171:3a7713b1edbc 4464 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
AnnaBridge 171:3a7713b1edbc 4465 #define SIM_SDID_FAMID_MASK 0xF0000000u
AnnaBridge 171:3a7713b1edbc 4466 #define SIM_SDID_FAMID_SHIFT 28
AnnaBridge 171:3a7713b1edbc 4467 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
AnnaBridge 171:3a7713b1edbc 4468 /* SCGC4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4469 #define SIM_SCGC4_I2C0_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4470 #define SIM_SCGC4_I2C0_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4471 #define SIM_SCGC4_I2C1_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4472 #define SIM_SCGC4_I2C1_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4473 #define SIM_SCGC4_UART0_MASK 0x400u
AnnaBridge 171:3a7713b1edbc 4474 #define SIM_SCGC4_UART0_SHIFT 10
AnnaBridge 171:3a7713b1edbc 4475 #define SIM_SCGC4_UART1_MASK 0x800u
AnnaBridge 171:3a7713b1edbc 4476 #define SIM_SCGC4_UART1_SHIFT 11
AnnaBridge 171:3a7713b1edbc 4477 #define SIM_SCGC4_UART2_MASK 0x1000u
AnnaBridge 171:3a7713b1edbc 4478 #define SIM_SCGC4_UART2_SHIFT 12
AnnaBridge 171:3a7713b1edbc 4479 #define SIM_SCGC4_USBOTG_MASK 0x40000u
AnnaBridge 171:3a7713b1edbc 4480 #define SIM_SCGC4_USBOTG_SHIFT 18
AnnaBridge 171:3a7713b1edbc 4481 #define SIM_SCGC4_CMP_MASK 0x80000u
AnnaBridge 171:3a7713b1edbc 4482 #define SIM_SCGC4_CMP_SHIFT 19
AnnaBridge 171:3a7713b1edbc 4483 #define SIM_SCGC4_SPI0_MASK 0x400000u
AnnaBridge 171:3a7713b1edbc 4484 #define SIM_SCGC4_SPI0_SHIFT 22
AnnaBridge 171:3a7713b1edbc 4485 #define SIM_SCGC4_SPI1_MASK 0x800000u
AnnaBridge 171:3a7713b1edbc 4486 #define SIM_SCGC4_SPI1_SHIFT 23
AnnaBridge 171:3a7713b1edbc 4487 /* SCGC5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4488 #define SIM_SCGC5_LPTMR_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4489 #define SIM_SCGC5_LPTMR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4490 #define SIM_SCGC5_TSI_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4491 #define SIM_SCGC5_TSI_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4492 #define SIM_SCGC5_PORTA_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 4493 #define SIM_SCGC5_PORTA_SHIFT 9
AnnaBridge 171:3a7713b1edbc 4494 #define SIM_SCGC5_PORTB_MASK 0x400u
AnnaBridge 171:3a7713b1edbc 4495 #define SIM_SCGC5_PORTB_SHIFT 10
AnnaBridge 171:3a7713b1edbc 4496 #define SIM_SCGC5_PORTC_MASK 0x800u
AnnaBridge 171:3a7713b1edbc 4497 #define SIM_SCGC5_PORTC_SHIFT 11
AnnaBridge 171:3a7713b1edbc 4498 #define SIM_SCGC5_PORTD_MASK 0x1000u
AnnaBridge 171:3a7713b1edbc 4499 #define SIM_SCGC5_PORTD_SHIFT 12
AnnaBridge 171:3a7713b1edbc 4500 #define SIM_SCGC5_PORTE_MASK 0x2000u
AnnaBridge 171:3a7713b1edbc 4501 #define SIM_SCGC5_PORTE_SHIFT 13
AnnaBridge 171:3a7713b1edbc 4502 #define SIM_SCGC5_SLCD_MASK 0x80000u
AnnaBridge 171:3a7713b1edbc 4503 #define SIM_SCGC5_SLCD_SHIFT 19
AnnaBridge 171:3a7713b1edbc 4504 /* SCGC6 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4505 #define SIM_SCGC6_FTF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4506 #define SIM_SCGC6_FTF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4507 #define SIM_SCGC6_DMAMUX_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4508 #define SIM_SCGC6_DMAMUX_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4509 #define SIM_SCGC6_I2S_MASK 0x8000u
AnnaBridge 171:3a7713b1edbc 4510 #define SIM_SCGC6_I2S_SHIFT 15
AnnaBridge 171:3a7713b1edbc 4511 #define SIM_SCGC6_PIT_MASK 0x800000u
AnnaBridge 171:3a7713b1edbc 4512 #define SIM_SCGC6_PIT_SHIFT 23
AnnaBridge 171:3a7713b1edbc 4513 #define SIM_SCGC6_TPM0_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 4514 #define SIM_SCGC6_TPM0_SHIFT 24
AnnaBridge 171:3a7713b1edbc 4515 #define SIM_SCGC6_TPM1_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 4516 #define SIM_SCGC6_TPM1_SHIFT 25
AnnaBridge 171:3a7713b1edbc 4517 #define SIM_SCGC6_TPM2_MASK 0x4000000u
AnnaBridge 171:3a7713b1edbc 4518 #define SIM_SCGC6_TPM2_SHIFT 26
AnnaBridge 171:3a7713b1edbc 4519 #define SIM_SCGC6_ADC0_MASK 0x8000000u
AnnaBridge 171:3a7713b1edbc 4520 #define SIM_SCGC6_ADC0_SHIFT 27
AnnaBridge 171:3a7713b1edbc 4521 #define SIM_SCGC6_RTC_MASK 0x20000000u
AnnaBridge 171:3a7713b1edbc 4522 #define SIM_SCGC6_RTC_SHIFT 29
AnnaBridge 171:3a7713b1edbc 4523 #define SIM_SCGC6_DAC0_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 4524 #define SIM_SCGC6_DAC0_SHIFT 31
AnnaBridge 171:3a7713b1edbc 4525 /* SCGC7 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4526 #define SIM_SCGC7_DMA_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 4527 #define SIM_SCGC7_DMA_SHIFT 8
AnnaBridge 171:3a7713b1edbc 4528 /* CLKDIV1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4529 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
AnnaBridge 171:3a7713b1edbc 4530 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
AnnaBridge 171:3a7713b1edbc 4531 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
AnnaBridge 171:3a7713b1edbc 4532 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
AnnaBridge 171:3a7713b1edbc 4533 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
AnnaBridge 171:3a7713b1edbc 4534 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
AnnaBridge 171:3a7713b1edbc 4535 /* FCFG1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4536 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4537 #define SIM_FCFG1_FLASHDIS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4538 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4539 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4540 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
AnnaBridge 171:3a7713b1edbc 4541 #define SIM_FCFG1_PFSIZE_SHIFT 24
AnnaBridge 171:3a7713b1edbc 4542 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 4543 /* FCFG2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4544 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
AnnaBridge 171:3a7713b1edbc 4545 #define SIM_FCFG2_MAXADDR1_SHIFT 16
AnnaBridge 171:3a7713b1edbc 4546 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
AnnaBridge 171:3a7713b1edbc 4547 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
AnnaBridge 171:3a7713b1edbc 4548 #define SIM_FCFG2_MAXADDR0_SHIFT 24
AnnaBridge 171:3a7713b1edbc 4549 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
AnnaBridge 171:3a7713b1edbc 4550 /* UIDMH Bit Fields */
AnnaBridge 171:3a7713b1edbc 4551 #define SIM_UIDMH_UID_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 4552 #define SIM_UIDMH_UID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4553 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
AnnaBridge 171:3a7713b1edbc 4554 /* UIDML Bit Fields */
AnnaBridge 171:3a7713b1edbc 4555 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4556 #define SIM_UIDML_UID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4557 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
AnnaBridge 171:3a7713b1edbc 4558 /* UIDL Bit Fields */
AnnaBridge 171:3a7713b1edbc 4559 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 4560 #define SIM_UIDL_UID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4561 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
AnnaBridge 171:3a7713b1edbc 4562 /* COPC Bit Fields */
AnnaBridge 171:3a7713b1edbc 4563 #define SIM_COPC_COPW_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4564 #define SIM_COPC_COPW_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4565 #define SIM_COPC_COPCLKS_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4566 #define SIM_COPC_COPCLKS_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4567 #define SIM_COPC_COPT_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 4568 #define SIM_COPC_COPT_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4569 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
AnnaBridge 171:3a7713b1edbc 4570 /* SRVCOP Bit Fields */
AnnaBridge 171:3a7713b1edbc 4571 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 4572 #define SIM_SRVCOP_SRVCOP_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4573 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
AnnaBridge 171:3a7713b1edbc 4574
AnnaBridge 171:3a7713b1edbc 4575 /*!
AnnaBridge 171:3a7713b1edbc 4576 * @}
AnnaBridge 171:3a7713b1edbc 4577 */ /* end of group SIM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4578
AnnaBridge 171:3a7713b1edbc 4579
AnnaBridge 171:3a7713b1edbc 4580 /* SIM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4581 /** Peripheral SIM base address */
AnnaBridge 171:3a7713b1edbc 4582 #define SIM_BASE (0x40047000u)
AnnaBridge 171:3a7713b1edbc 4583 /** Peripheral SIM base pointer */
AnnaBridge 171:3a7713b1edbc 4584 #define SIM ((SIM_Type *)SIM_BASE)
AnnaBridge 171:3a7713b1edbc 4585 /** Array initializer of SIM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4586 #define SIM_BASES { SIM }
AnnaBridge 171:3a7713b1edbc 4587
AnnaBridge 171:3a7713b1edbc 4588 /*!
AnnaBridge 171:3a7713b1edbc 4589 * @}
AnnaBridge 171:3a7713b1edbc 4590 */ /* end of group SIM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4591
AnnaBridge 171:3a7713b1edbc 4592
AnnaBridge 171:3a7713b1edbc 4593 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4594 -- SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4595 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4596
AnnaBridge 171:3a7713b1edbc 4597 /*!
AnnaBridge 171:3a7713b1edbc 4598 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4599 * @{
AnnaBridge 171:3a7713b1edbc 4600 */
AnnaBridge 171:3a7713b1edbc 4601
AnnaBridge 171:3a7713b1edbc 4602 /** SMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4603 typedef struct {
AnnaBridge 171:3a7713b1edbc 4604 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4605 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 4606 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 4607 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 4608 } SMC_Type;
AnnaBridge 171:3a7713b1edbc 4609
AnnaBridge 171:3a7713b1edbc 4610 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4611 -- SMC Register Masks
AnnaBridge 171:3a7713b1edbc 4612 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4613
AnnaBridge 171:3a7713b1edbc 4614 /*!
AnnaBridge 171:3a7713b1edbc 4615 * @addtogroup SMC_Register_Masks SMC Register Masks
AnnaBridge 171:3a7713b1edbc 4616 * @{
AnnaBridge 171:3a7713b1edbc 4617 */
AnnaBridge 171:3a7713b1edbc 4618
AnnaBridge 171:3a7713b1edbc 4619 /* PMPROT Bit Fields */
AnnaBridge 171:3a7713b1edbc 4620 #define SMC_PMPROT_AVLLS_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4621 #define SMC_PMPROT_AVLLS_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4622 #define SMC_PMPROT_ALLS_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4623 #define SMC_PMPROT_ALLS_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4624 #define SMC_PMPROT_AVLP_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4625 #define SMC_PMPROT_AVLP_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4626 /* PMCTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 4627 #define SMC_PMCTRL_STOPM_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 4628 #define SMC_PMCTRL_STOPM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4629 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
AnnaBridge 171:3a7713b1edbc 4630 #define SMC_PMCTRL_STOPA_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4631 #define SMC_PMCTRL_STOPA_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4632 #define SMC_PMCTRL_RUNM_MASK 0x60u
AnnaBridge 171:3a7713b1edbc 4633 #define SMC_PMCTRL_RUNM_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4634 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
AnnaBridge 171:3a7713b1edbc 4635 /* STOPCTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 4636 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 4637 #define SMC_STOPCTRL_VLLSM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4638 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
AnnaBridge 171:3a7713b1edbc 4639 #define SMC_STOPCTRL_PORPO_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4640 #define SMC_STOPCTRL_PORPO_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4641 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 4642 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4643 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
AnnaBridge 171:3a7713b1edbc 4644 /* PMSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 4645 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
AnnaBridge 171:3a7713b1edbc 4646 #define SMC_PMSTAT_PMSTAT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4647 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 4648
AnnaBridge 171:3a7713b1edbc 4649 /*!
AnnaBridge 171:3a7713b1edbc 4650 * @}
AnnaBridge 171:3a7713b1edbc 4651 */ /* end of group SMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4652
AnnaBridge 171:3a7713b1edbc 4653
AnnaBridge 171:3a7713b1edbc 4654 /* SMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4655 /** Peripheral SMC base address */
AnnaBridge 171:3a7713b1edbc 4656 #define SMC_BASE (0x4007E000u)
AnnaBridge 171:3a7713b1edbc 4657 /** Peripheral SMC base pointer */
AnnaBridge 171:3a7713b1edbc 4658 #define SMC ((SMC_Type *)SMC_BASE)
AnnaBridge 171:3a7713b1edbc 4659 /** Array initializer of SMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4660 #define SMC_BASES { SMC }
AnnaBridge 171:3a7713b1edbc 4661
AnnaBridge 171:3a7713b1edbc 4662 /*!
AnnaBridge 171:3a7713b1edbc 4663 * @}
AnnaBridge 171:3a7713b1edbc 4664 */ /* end of group SMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4665
AnnaBridge 171:3a7713b1edbc 4666
AnnaBridge 171:3a7713b1edbc 4667 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4668 -- SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4669 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4670
AnnaBridge 171:3a7713b1edbc 4671 /*!
AnnaBridge 171:3a7713b1edbc 4672 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4673 * @{
AnnaBridge 171:3a7713b1edbc 4674 */
AnnaBridge 171:3a7713b1edbc 4675
AnnaBridge 171:3a7713b1edbc 4676 /** SPI - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4677 typedef struct {
AnnaBridge 171:3a7713b1edbc 4678 __I uint8_t S; /**< SPI status register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4679 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 4680 __IO uint8_t C2; /**< SPI control register 2, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 4681 __IO uint8_t C1; /**< SPI control register 1, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 4682 __IO uint8_t ML; /**< SPI match register low, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4683 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 4684 __IO uint8_t DL; /**< SPI data register low, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 4685 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 4686 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 4687 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 4688 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 4689 } SPI_Type;
AnnaBridge 171:3a7713b1edbc 4690
AnnaBridge 171:3a7713b1edbc 4691 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4692 -- SPI Register Masks
AnnaBridge 171:3a7713b1edbc 4693 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4694
AnnaBridge 171:3a7713b1edbc 4695 /*!
AnnaBridge 171:3a7713b1edbc 4696 * @addtogroup SPI_Register_Masks SPI Register Masks
AnnaBridge 171:3a7713b1edbc 4697 * @{
AnnaBridge 171:3a7713b1edbc 4698 */
AnnaBridge 171:3a7713b1edbc 4699
AnnaBridge 171:3a7713b1edbc 4700 /* S Bit Fields */
AnnaBridge 171:3a7713b1edbc 4701 #define SPI_S_RFIFOEF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4702 #define SPI_S_RFIFOEF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4703 #define SPI_S_TXFULLF_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4704 #define SPI_S_TXFULLF_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4705 #define SPI_S_TNEAREF_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4706 #define SPI_S_TNEAREF_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4707 #define SPI_S_RNFULLF_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4708 #define SPI_S_RNFULLF_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4709 #define SPI_S_MODF_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4710 #define SPI_S_MODF_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4711 #define SPI_S_SPTEF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4712 #define SPI_S_SPTEF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4713 #define SPI_S_SPMF_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4714 #define SPI_S_SPMF_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4715 #define SPI_S_SPRF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4716 #define SPI_S_SPRF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4717 /* BR Bit Fields */
AnnaBridge 171:3a7713b1edbc 4718 #define SPI_BR_SPR_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 4719 #define SPI_BR_SPR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4720 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
AnnaBridge 171:3a7713b1edbc 4721 #define SPI_BR_SPPR_MASK 0x70u
AnnaBridge 171:3a7713b1edbc 4722 #define SPI_BR_SPPR_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4723 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
AnnaBridge 171:3a7713b1edbc 4724 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4725 #define SPI_C2_SPC0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4726 #define SPI_C2_SPC0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4727 #define SPI_C2_SPISWAI_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4728 #define SPI_C2_SPISWAI_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4729 #define SPI_C2_RXDMAE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4730 #define SPI_C2_RXDMAE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4731 #define SPI_C2_BIDIROE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4732 #define SPI_C2_BIDIROE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4733 #define SPI_C2_MODFEN_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4734 #define SPI_C2_MODFEN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4735 #define SPI_C2_TXDMAE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4736 #define SPI_C2_TXDMAE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4737 #define SPI_C2_SPIMODE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4738 #define SPI_C2_SPIMODE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4739 #define SPI_C2_SPMIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4740 #define SPI_C2_SPMIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4741 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4742 #define SPI_C1_LSBFE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4743 #define SPI_C1_LSBFE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4744 #define SPI_C1_SSOE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4745 #define SPI_C1_SSOE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4746 #define SPI_C1_CPHA_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4747 #define SPI_C1_CPHA_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4748 #define SPI_C1_CPOL_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4749 #define SPI_C1_CPOL_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4750 #define SPI_C1_MSTR_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4751 #define SPI_C1_MSTR_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4752 #define SPI_C1_SPTIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4753 #define SPI_C1_SPTIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4754 #define SPI_C1_SPE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4755 #define SPI_C1_SPE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4756 #define SPI_C1_SPIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4757 #define SPI_C1_SPIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4758 /* ML Bit Fields */
AnnaBridge 171:3a7713b1edbc 4759 #define SPI_ML_Bits_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 4760 #define SPI_ML_Bits_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4761 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
AnnaBridge 171:3a7713b1edbc 4762 /* MH Bit Fields */
AnnaBridge 171:3a7713b1edbc 4763 #define SPI_MH_Bits_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 4764 #define SPI_MH_Bits_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4765 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
AnnaBridge 171:3a7713b1edbc 4766 /* DL Bit Fields */
AnnaBridge 171:3a7713b1edbc 4767 #define SPI_DL_Bits_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 4768 #define SPI_DL_Bits_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4769 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
AnnaBridge 171:3a7713b1edbc 4770 /* DH Bit Fields */
AnnaBridge 171:3a7713b1edbc 4771 #define SPI_DH_Bits_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 4772 #define SPI_DH_Bits_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4773 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
AnnaBridge 171:3a7713b1edbc 4774 /* CI Bit Fields */
AnnaBridge 171:3a7713b1edbc 4775 #define SPI_CI_SPRFCI_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4776 #define SPI_CI_SPRFCI_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4777 #define SPI_CI_SPTEFCI_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4778 #define SPI_CI_SPTEFCI_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4779 #define SPI_CI_RNFULLFCI_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4780 #define SPI_CI_RNFULLFCI_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4781 #define SPI_CI_TNEAREFCI_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4782 #define SPI_CI_TNEAREFCI_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4783 #define SPI_CI_RXFOF_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4784 #define SPI_CI_RXFOF_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4785 #define SPI_CI_TXFOF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4786 #define SPI_CI_TXFOF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4787 #define SPI_CI_RXFERR_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4788 #define SPI_CI_RXFERR_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4789 #define SPI_CI_TXFERR_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4790 #define SPI_CI_TXFERR_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4791 /* C3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4792 #define SPI_C3_FIFOMODE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4793 #define SPI_C3_FIFOMODE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4794 #define SPI_C3_RNFULLIEN_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4795 #define SPI_C3_RNFULLIEN_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4796 #define SPI_C3_TNEARIEN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4797 #define SPI_C3_TNEARIEN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4798 #define SPI_C3_INTCLR_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4799 #define SPI_C3_INTCLR_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4800 #define SPI_C3_RNFULLF_MARK_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4801 #define SPI_C3_RNFULLF_MARK_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4802 #define SPI_C3_TNEAREF_MARK_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4803 #define SPI_C3_TNEAREF_MARK_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4804
AnnaBridge 171:3a7713b1edbc 4805 /*!
AnnaBridge 171:3a7713b1edbc 4806 * @}
AnnaBridge 171:3a7713b1edbc 4807 */ /* end of group SPI_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4808
AnnaBridge 171:3a7713b1edbc 4809
AnnaBridge 171:3a7713b1edbc 4810 /* SPI - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4811 /** Peripheral SPI0 base address */
AnnaBridge 171:3a7713b1edbc 4812 #define SPI0_BASE (0x40076000u)
AnnaBridge 171:3a7713b1edbc 4813 /** Peripheral SPI0 base pointer */
AnnaBridge 171:3a7713b1edbc 4814 #define SPI0 ((SPI_Type *)SPI0_BASE)
AnnaBridge 171:3a7713b1edbc 4815 /** Peripheral SPI1 base address */
AnnaBridge 171:3a7713b1edbc 4816 #define SPI1_BASE (0x40077000u)
AnnaBridge 171:3a7713b1edbc 4817 /** Peripheral SPI1 base pointer */
AnnaBridge 171:3a7713b1edbc 4818 #define SPI1 ((SPI_Type *)SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 4819 /** Array initializer of SPI peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4820 #define SPI_BASES { SPI0, SPI1 }
AnnaBridge 171:3a7713b1edbc 4821
AnnaBridge 171:3a7713b1edbc 4822 /*!
AnnaBridge 171:3a7713b1edbc 4823 * @}
AnnaBridge 171:3a7713b1edbc 4824 */ /* end of group SPI_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4825
AnnaBridge 171:3a7713b1edbc 4826
AnnaBridge 171:3a7713b1edbc 4827 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4828 -- TPM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4829 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4830
AnnaBridge 171:3a7713b1edbc 4831 /*!
AnnaBridge 171:3a7713b1edbc 4832 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4833 * @{
AnnaBridge 171:3a7713b1edbc 4834 */
AnnaBridge 171:3a7713b1edbc 4835
AnnaBridge 171:3a7713b1edbc 4836 /** TPM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4837 typedef struct {
AnnaBridge 171:3a7713b1edbc 4838 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4839 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4840 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4841 struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 4842 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 4843 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 4844 } CONTROLS[6];
AnnaBridge 171:3a7713b1edbc 4845 uint8_t RESERVED_0[20];
AnnaBridge 171:3a7713b1edbc 4846 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 4847 uint8_t RESERVED_1[48];
AnnaBridge 171:3a7713b1edbc 4848 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 4849 } TPM_Type;
AnnaBridge 171:3a7713b1edbc 4850
AnnaBridge 171:3a7713b1edbc 4851 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4852 -- TPM Register Masks
AnnaBridge 171:3a7713b1edbc 4853 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4854
AnnaBridge 171:3a7713b1edbc 4855 /*!
AnnaBridge 171:3a7713b1edbc 4856 * @addtogroup TPM_Register_Masks TPM Register Masks
AnnaBridge 171:3a7713b1edbc 4857 * @{
AnnaBridge 171:3a7713b1edbc 4858 */
AnnaBridge 171:3a7713b1edbc 4859
AnnaBridge 171:3a7713b1edbc 4860 /* SC Bit Fields */
AnnaBridge 171:3a7713b1edbc 4861 #define TPM_SC_PS_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 4862 #define TPM_SC_PS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4863 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
AnnaBridge 171:3a7713b1edbc 4864 #define TPM_SC_CMOD_MASK 0x18u
AnnaBridge 171:3a7713b1edbc 4865 #define TPM_SC_CMOD_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4866 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
AnnaBridge 171:3a7713b1edbc 4867 #define TPM_SC_CPWMS_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4868 #define TPM_SC_CPWMS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4869 #define TPM_SC_TOIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4870 #define TPM_SC_TOIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4871 #define TPM_SC_TOF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4872 #define TPM_SC_TOF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4873 #define TPM_SC_DMA_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 4874 #define TPM_SC_DMA_SHIFT 8
AnnaBridge 171:3a7713b1edbc 4875 /* CNT Bit Fields */
AnnaBridge 171:3a7713b1edbc 4876 #define TPM_CNT_COUNT_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 4877 #define TPM_CNT_COUNT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4878 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 4879 /* MOD Bit Fields */
AnnaBridge 171:3a7713b1edbc 4880 #define TPM_MOD_MOD_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 4881 #define TPM_MOD_MOD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4882 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
AnnaBridge 171:3a7713b1edbc 4883 /* CnSC Bit Fields */
AnnaBridge 171:3a7713b1edbc 4884 #define TPM_CnSC_DMA_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4885 #define TPM_CnSC_DMA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4886 #define TPM_CnSC_ELSA_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4887 #define TPM_CnSC_ELSA_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4888 #define TPM_CnSC_ELSB_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4889 #define TPM_CnSC_ELSB_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4890 #define TPM_CnSC_MSA_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4891 #define TPM_CnSC_MSA_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4892 #define TPM_CnSC_MSB_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4893 #define TPM_CnSC_MSB_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4894 #define TPM_CnSC_CHIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4895 #define TPM_CnSC_CHIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4896 #define TPM_CnSC_CHF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4897 #define TPM_CnSC_CHF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4898 /* CnV Bit Fields */
AnnaBridge 171:3a7713b1edbc 4899 #define TPM_CnV_VAL_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 4900 #define TPM_CnV_VAL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4901 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 4902 /* STATUS Bit Fields */
AnnaBridge 171:3a7713b1edbc 4903 #define TPM_STATUS_CH0F_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4904 #define TPM_STATUS_CH0F_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4905 #define TPM_STATUS_CH1F_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4906 #define TPM_STATUS_CH1F_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4907 #define TPM_STATUS_CH2F_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4908 #define TPM_STATUS_CH2F_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4909 #define TPM_STATUS_CH3F_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4910 #define TPM_STATUS_CH3F_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4911 #define TPM_STATUS_CH4F_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4912 #define TPM_STATUS_CH4F_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4913 #define TPM_STATUS_CH5F_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4914 #define TPM_STATUS_CH5F_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4915 #define TPM_STATUS_TOF_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 4916 #define TPM_STATUS_TOF_SHIFT 8
AnnaBridge 171:3a7713b1edbc 4917 /* CONF Bit Fields */
AnnaBridge 171:3a7713b1edbc 4918 #define TPM_CONF_DOZEEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4919 #define TPM_CONF_DOZEEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4920 #define TPM_CONF_DBGMODE_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 4921 #define TPM_CONF_DBGMODE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4922 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
AnnaBridge 171:3a7713b1edbc 4923 #define TPM_CONF_GTBEEN_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 4924 #define TPM_CONF_GTBEEN_SHIFT 9
AnnaBridge 171:3a7713b1edbc 4925 #define TPM_CONF_CSOT_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 4926 #define TPM_CONF_CSOT_SHIFT 16
AnnaBridge 171:3a7713b1edbc 4927 #define TPM_CONF_CSOO_MASK 0x20000u
AnnaBridge 171:3a7713b1edbc 4928 #define TPM_CONF_CSOO_SHIFT 17
AnnaBridge 171:3a7713b1edbc 4929 #define TPM_CONF_CROT_MASK 0x40000u
AnnaBridge 171:3a7713b1edbc 4930 #define TPM_CONF_CROT_SHIFT 18
AnnaBridge 171:3a7713b1edbc 4931 #define TPM_CONF_TRGSEL_MASK 0xF000000u
AnnaBridge 171:3a7713b1edbc 4932 #define TPM_CONF_TRGSEL_SHIFT 24
AnnaBridge 171:3a7713b1edbc 4933 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4934
AnnaBridge 171:3a7713b1edbc 4935 /*!
AnnaBridge 171:3a7713b1edbc 4936 * @}
AnnaBridge 171:3a7713b1edbc 4937 */ /* end of group TPM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4938
AnnaBridge 171:3a7713b1edbc 4939
AnnaBridge 171:3a7713b1edbc 4940 /* TPM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4941 /** Peripheral TPM0 base address */
AnnaBridge 171:3a7713b1edbc 4942 #define TPM0_BASE (0x40038000u)
AnnaBridge 171:3a7713b1edbc 4943 /** Peripheral TPM0 base pointer */
AnnaBridge 171:3a7713b1edbc 4944 #define TPM0 ((TPM_Type *)TPM0_BASE)
AnnaBridge 171:3a7713b1edbc 4945 /** Peripheral TPM1 base address */
AnnaBridge 171:3a7713b1edbc 4946 #define TPM1_BASE (0x40039000u)
AnnaBridge 171:3a7713b1edbc 4947 /** Peripheral TPM1 base pointer */
AnnaBridge 171:3a7713b1edbc 4948 #define TPM1 ((TPM_Type *)TPM1_BASE)
AnnaBridge 171:3a7713b1edbc 4949 /** Peripheral TPM2 base address */
AnnaBridge 171:3a7713b1edbc 4950 #define TPM2_BASE (0x4003A000u)
AnnaBridge 171:3a7713b1edbc 4951 /** Peripheral TPM2 base pointer */
AnnaBridge 171:3a7713b1edbc 4952 #define TPM2 ((TPM_Type *)TPM2_BASE)
AnnaBridge 171:3a7713b1edbc 4953 /** Array initializer of TPM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4954 #define TPM_BASES { TPM0, TPM1, TPM2 }
AnnaBridge 171:3a7713b1edbc 4955
AnnaBridge 171:3a7713b1edbc 4956 /*!
AnnaBridge 171:3a7713b1edbc 4957 * @}
AnnaBridge 171:3a7713b1edbc 4958 */ /* end of group TPM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4959
AnnaBridge 171:3a7713b1edbc 4960
AnnaBridge 171:3a7713b1edbc 4961 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4962 -- TSI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4963 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4964
AnnaBridge 171:3a7713b1edbc 4965 /*!
AnnaBridge 171:3a7713b1edbc 4966 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4967 * @{
AnnaBridge 171:3a7713b1edbc 4968 */
AnnaBridge 171:3a7713b1edbc 4969
AnnaBridge 171:3a7713b1edbc 4970 /** TSI - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4971 typedef struct {
AnnaBridge 171:3a7713b1edbc 4972 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4973 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4974 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4975 } TSI_Type;
AnnaBridge 171:3a7713b1edbc 4976
AnnaBridge 171:3a7713b1edbc 4977 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4978 -- TSI Register Masks
AnnaBridge 171:3a7713b1edbc 4979 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4980
AnnaBridge 171:3a7713b1edbc 4981 /*!
AnnaBridge 171:3a7713b1edbc 4982 * @addtogroup TSI_Register_Masks TSI Register Masks
AnnaBridge 171:3a7713b1edbc 4983 * @{
AnnaBridge 171:3a7713b1edbc 4984 */
AnnaBridge 171:3a7713b1edbc 4985
AnnaBridge 171:3a7713b1edbc 4986 /* GENCS Bit Fields */
AnnaBridge 171:3a7713b1edbc 4987 #define TSI_GENCS_CURSW_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4988 #define TSI_GENCS_CURSW_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4989 #define TSI_GENCS_EOSF_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4990 #define TSI_GENCS_EOSF_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4991 #define TSI_GENCS_SCNIP_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4992 #define TSI_GENCS_SCNIP_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4993 #define TSI_GENCS_STM_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4994 #define TSI_GENCS_STM_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4995 #define TSI_GENCS_STPE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4996 #define TSI_GENCS_STPE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4997 #define TSI_GENCS_TSIIEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4998 #define TSI_GENCS_TSIIEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4999 #define TSI_GENCS_TSIEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5000 #define TSI_GENCS_TSIEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5001 #define TSI_GENCS_NSCN_MASK 0x1F00u
AnnaBridge 171:3a7713b1edbc 5002 #define TSI_GENCS_NSCN_SHIFT 8
AnnaBridge 171:3a7713b1edbc 5003 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
AnnaBridge 171:3a7713b1edbc 5004 #define TSI_GENCS_PS_MASK 0xE000u
AnnaBridge 171:3a7713b1edbc 5005 #define TSI_GENCS_PS_SHIFT 13
AnnaBridge 171:3a7713b1edbc 5006 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
AnnaBridge 171:3a7713b1edbc 5007 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
AnnaBridge 171:3a7713b1edbc 5008 #define TSI_GENCS_EXTCHRG_SHIFT 16
AnnaBridge 171:3a7713b1edbc 5009 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
AnnaBridge 171:3a7713b1edbc 5010 #define TSI_GENCS_DVOLT_MASK 0x180000u
AnnaBridge 171:3a7713b1edbc 5011 #define TSI_GENCS_DVOLT_SHIFT 19
AnnaBridge 171:3a7713b1edbc 5012 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
AnnaBridge 171:3a7713b1edbc 5013 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
AnnaBridge 171:3a7713b1edbc 5014 #define TSI_GENCS_REFCHRG_SHIFT 21
AnnaBridge 171:3a7713b1edbc 5015 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
AnnaBridge 171:3a7713b1edbc 5016 #define TSI_GENCS_MODE_MASK 0xF000000u
AnnaBridge 171:3a7713b1edbc 5017 #define TSI_GENCS_MODE_SHIFT 24
AnnaBridge 171:3a7713b1edbc 5018 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 5019 #define TSI_GENCS_ESOR_MASK 0x10000000u
AnnaBridge 171:3a7713b1edbc 5020 #define TSI_GENCS_ESOR_SHIFT 28
AnnaBridge 171:3a7713b1edbc 5021 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 5022 #define TSI_GENCS_OUTRGF_SHIFT 31
AnnaBridge 171:3a7713b1edbc 5023 /* DATA Bit Fields */
AnnaBridge 171:3a7713b1edbc 5024 #define TSI_DATA_TSICNT_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 5025 #define TSI_DATA_TSICNT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5026 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
AnnaBridge 171:3a7713b1edbc 5027 #define TSI_DATA_SWTS_MASK 0x400000u
AnnaBridge 171:3a7713b1edbc 5028 #define TSI_DATA_SWTS_SHIFT 22
AnnaBridge 171:3a7713b1edbc 5029 #define TSI_DATA_DMAEN_MASK 0x800000u
AnnaBridge 171:3a7713b1edbc 5030 #define TSI_DATA_DMAEN_SHIFT 23
AnnaBridge 171:3a7713b1edbc 5031 #define TSI_DATA_TSICH_MASK 0xF0000000u
AnnaBridge 171:3a7713b1edbc 5032 #define TSI_DATA_TSICH_SHIFT 28
AnnaBridge 171:3a7713b1edbc 5033 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
AnnaBridge 171:3a7713b1edbc 5034 /* TSHD Bit Fields */
AnnaBridge 171:3a7713b1edbc 5035 #define TSI_TSHD_THRESL_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 5036 #define TSI_TSHD_THRESL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5037 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
AnnaBridge 171:3a7713b1edbc 5038 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
AnnaBridge 171:3a7713b1edbc 5039 #define TSI_TSHD_THRESH_SHIFT 16
AnnaBridge 171:3a7713b1edbc 5040 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 5041
AnnaBridge 171:3a7713b1edbc 5042 /*!
AnnaBridge 171:3a7713b1edbc 5043 * @}
AnnaBridge 171:3a7713b1edbc 5044 */ /* end of group TSI_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5045
AnnaBridge 171:3a7713b1edbc 5046
AnnaBridge 171:3a7713b1edbc 5047 /* TSI - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5048 /** Peripheral TSI0 base address */
AnnaBridge 171:3a7713b1edbc 5049 #define TSI0_BASE (0x40045000u)
AnnaBridge 171:3a7713b1edbc 5050 /** Peripheral TSI0 base pointer */
AnnaBridge 171:3a7713b1edbc 5051 #define TSI0 ((TSI_Type *)TSI0_BASE)
AnnaBridge 171:3a7713b1edbc 5052 /** Array initializer of TSI peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5053 #define TSI_BASES { TSI0 }
AnnaBridge 171:3a7713b1edbc 5054
AnnaBridge 171:3a7713b1edbc 5055 /*!
AnnaBridge 171:3a7713b1edbc 5056 * @}
AnnaBridge 171:3a7713b1edbc 5057 */ /* end of group TSI_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5058
AnnaBridge 171:3a7713b1edbc 5059
AnnaBridge 171:3a7713b1edbc 5060 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5061 -- UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5062 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5063
AnnaBridge 171:3a7713b1edbc 5064 /*!
AnnaBridge 171:3a7713b1edbc 5065 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5066 * @{
AnnaBridge 171:3a7713b1edbc 5067 */
AnnaBridge 171:3a7713b1edbc 5068
AnnaBridge 171:3a7713b1edbc 5069 /** UART - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5070 typedef struct {
AnnaBridge 171:3a7713b1edbc 5071 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5072 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 5073 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 5074 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 5075 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5076 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 5077 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 5078 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 5079 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 5080 } UART_Type;
AnnaBridge 171:3a7713b1edbc 5081
AnnaBridge 171:3a7713b1edbc 5082 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5083 -- UART Register Masks
AnnaBridge 171:3a7713b1edbc 5084 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5085
AnnaBridge 171:3a7713b1edbc 5086 /*!
AnnaBridge 171:3a7713b1edbc 5087 * @addtogroup UART_Register_Masks UART Register Masks
AnnaBridge 171:3a7713b1edbc 5088 * @{
AnnaBridge 171:3a7713b1edbc 5089 */
AnnaBridge 171:3a7713b1edbc 5090
AnnaBridge 171:3a7713b1edbc 5091 /* BDH Bit Fields */
AnnaBridge 171:3a7713b1edbc 5092 #define UART_BDH_SBR_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 5093 #define UART_BDH_SBR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5094 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 5095 #define UART_BDH_SBNS_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5096 #define UART_BDH_SBNS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5097 #define UART_BDH_RXEDGIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5098 #define UART_BDH_RXEDGIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5099 #define UART_BDH_LBKDIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5100 #define UART_BDH_LBKDIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5101 /* BDL Bit Fields */
AnnaBridge 171:3a7713b1edbc 5102 #define UART_BDL_SBR_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 5103 #define UART_BDL_SBR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5104 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 5105 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5106 #define UART_C1_PT_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5107 #define UART_C1_PT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5108 #define UART_C1_PE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5109 #define UART_C1_PE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5110 #define UART_C1_ILT_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5111 #define UART_C1_ILT_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5112 #define UART_C1_WAKE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5113 #define UART_C1_WAKE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5114 #define UART_C1_M_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5115 #define UART_C1_M_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5116 #define UART_C1_RSRC_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5117 #define UART_C1_RSRC_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5118 #define UART_C1_UARTSWAI_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5119 #define UART_C1_UARTSWAI_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5120 #define UART_C1_LOOPS_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5121 #define UART_C1_LOOPS_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5122 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5123 #define UART_C2_SBK_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5124 #define UART_C2_SBK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5125 #define UART_C2_RWU_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5126 #define UART_C2_RWU_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5127 #define UART_C2_RE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5128 #define UART_C2_RE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5129 #define UART_C2_TE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5130 #define UART_C2_TE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5131 #define UART_C2_ILIE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5132 #define UART_C2_ILIE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5133 #define UART_C2_RIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5134 #define UART_C2_RIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5135 #define UART_C2_TCIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5136 #define UART_C2_TCIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5137 #define UART_C2_TIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5138 #define UART_C2_TIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5139 /* S1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5140 #define UART_S1_PF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5141 #define UART_S1_PF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5142 #define UART_S1_FE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5143 #define UART_S1_FE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5144 #define UART_S1_NF_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5145 #define UART_S1_NF_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5146 #define UART_S1_OR_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5147 #define UART_S1_OR_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5148 #define UART_S1_IDLE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5149 #define UART_S1_IDLE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5150 #define UART_S1_RDRF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5151 #define UART_S1_RDRF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5152 #define UART_S1_TC_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5153 #define UART_S1_TC_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5154 #define UART_S1_TDRE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5155 #define UART_S1_TDRE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5156 /* S2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5157 #define UART_S2_RAF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5158 #define UART_S2_RAF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5159 #define UART_S2_LBKDE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5160 #define UART_S2_LBKDE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5161 #define UART_S2_BRK13_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5162 #define UART_S2_BRK13_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5163 #define UART_S2_RWUID_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5164 #define UART_S2_RWUID_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5165 #define UART_S2_RXINV_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5166 #define UART_S2_RXINV_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5167 #define UART_S2_RXEDGIF_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5168 #define UART_S2_RXEDGIF_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5169 #define UART_S2_LBKDIF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5170 #define UART_S2_LBKDIF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5171 /* C3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5172 #define UART_C3_PEIE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5173 #define UART_C3_PEIE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5174 #define UART_C3_FEIE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5175 #define UART_C3_FEIE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5176 #define UART_C3_NEIE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5177 #define UART_C3_NEIE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5178 #define UART_C3_ORIE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5179 #define UART_C3_ORIE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5180 #define UART_C3_TXINV_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5181 #define UART_C3_TXINV_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5182 #define UART_C3_TXDIR_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5183 #define UART_C3_TXDIR_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5184 #define UART_C3_T8_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5185 #define UART_C3_T8_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5186 #define UART_C3_R8_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5187 #define UART_C3_R8_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5188 /* D Bit Fields */
AnnaBridge 171:3a7713b1edbc 5189 #define UART_D_R0T0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5190 #define UART_D_R0T0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5191 #define UART_D_R1T1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5192 #define UART_D_R1T1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5193 #define UART_D_R2T2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5194 #define UART_D_R2T2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5195 #define UART_D_R3T3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5196 #define UART_D_R3T3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5197 #define UART_D_R4T4_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5198 #define UART_D_R4T4_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5199 #define UART_D_R5T5_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5200 #define UART_D_R5T5_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5201 #define UART_D_R6T6_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5202 #define UART_D_R6T6_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5203 #define UART_D_R7T7_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5204 #define UART_D_R7T7_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5205 /* C4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5206 #define UART_C4_RDMAS_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5207 #define UART_C4_RDMAS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5208 #define UART_C4_TDMAS_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5209 #define UART_C4_TDMAS_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5210
AnnaBridge 171:3a7713b1edbc 5211 /*!
AnnaBridge 171:3a7713b1edbc 5212 * @}
AnnaBridge 171:3a7713b1edbc 5213 */ /* end of group UART_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5214
AnnaBridge 171:3a7713b1edbc 5215
AnnaBridge 171:3a7713b1edbc 5216 /* UART - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5217 /** Peripheral UART1 base address */
AnnaBridge 171:3a7713b1edbc 5218 #define UART1_BASE (0x4006B000u)
AnnaBridge 171:3a7713b1edbc 5219 /** Peripheral UART1 base pointer */
AnnaBridge 171:3a7713b1edbc 5220 #define UART1 ((UART_Type *)UART1_BASE)
AnnaBridge 171:3a7713b1edbc 5221 /** Peripheral UART2 base address */
AnnaBridge 171:3a7713b1edbc 5222 #define UART2_BASE (0x4006C000u)
AnnaBridge 171:3a7713b1edbc 5223 /** Peripheral UART2 base pointer */
AnnaBridge 171:3a7713b1edbc 5224 #define UART2 ((UART_Type *)UART2_BASE)
AnnaBridge 171:3a7713b1edbc 5225 /** Array initializer of UART peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5226 #define UART_BASES { UART1, UART2 }
AnnaBridge 171:3a7713b1edbc 5227
AnnaBridge 171:3a7713b1edbc 5228 /*!
AnnaBridge 171:3a7713b1edbc 5229 * @}
AnnaBridge 171:3a7713b1edbc 5230 */ /* end of group UART_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5231
AnnaBridge 171:3a7713b1edbc 5232
AnnaBridge 171:3a7713b1edbc 5233 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5234 -- UART0 Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5235 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5236
AnnaBridge 171:3a7713b1edbc 5237 /*!
AnnaBridge 171:3a7713b1edbc 5238 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5239 * @{
AnnaBridge 171:3a7713b1edbc 5240 */
AnnaBridge 171:3a7713b1edbc 5241
AnnaBridge 171:3a7713b1edbc 5242 /** UART0 - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5243 typedef struct {
AnnaBridge 171:3a7713b1edbc 5244 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5245 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 5246 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 5247 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 5248 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5249 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 5250 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 5251 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 5252 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 5253 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 5254 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 5255 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 5256 } UART0_Type;
AnnaBridge 171:3a7713b1edbc 5257
AnnaBridge 171:3a7713b1edbc 5258 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5259 -- UART0 Register Masks
AnnaBridge 171:3a7713b1edbc 5260 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5261
AnnaBridge 171:3a7713b1edbc 5262 /*!
AnnaBridge 171:3a7713b1edbc 5263 * @addtogroup UART0_Register_Masks UART0 Register Masks
AnnaBridge 171:3a7713b1edbc 5264 * @{
AnnaBridge 171:3a7713b1edbc 5265 */
AnnaBridge 171:3a7713b1edbc 5266
AnnaBridge 171:3a7713b1edbc 5267 /* BDH Bit Fields */
AnnaBridge 171:3a7713b1edbc 5268 #define UART0_BDH_SBR_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 5269 #define UART0_BDH_SBR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5270 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 5271 #define UART0_BDH_SBNS_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5272 #define UART0_BDH_SBNS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5273 #define UART0_BDH_RXEDGIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5274 #define UART0_BDH_RXEDGIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5275 #define UART0_BDH_LBKDIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5276 #define UART0_BDH_LBKDIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5277 /* BDL Bit Fields */
AnnaBridge 171:3a7713b1edbc 5278 #define UART0_BDL_SBR_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 5279 #define UART0_BDL_SBR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5280 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 5281 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5282 #define UART0_C1_PT_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5283 #define UART0_C1_PT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5284 #define UART0_C1_PE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5285 #define UART0_C1_PE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5286 #define UART0_C1_ILT_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5287 #define UART0_C1_ILT_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5288 #define UART0_C1_WAKE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5289 #define UART0_C1_WAKE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5290 #define UART0_C1_M_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5291 #define UART0_C1_M_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5292 #define UART0_C1_RSRC_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5293 #define UART0_C1_RSRC_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5294 #define UART0_C1_DOZEEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5295 #define UART0_C1_DOZEEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5296 #define UART0_C1_LOOPS_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5297 #define UART0_C1_LOOPS_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5298 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5299 #define UART0_C2_SBK_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5300 #define UART0_C2_SBK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5301 #define UART0_C2_RWU_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5302 #define UART0_C2_RWU_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5303 #define UART0_C2_RE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5304 #define UART0_C2_RE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5305 #define UART0_C2_TE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5306 #define UART0_C2_TE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5307 #define UART0_C2_ILIE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5308 #define UART0_C2_ILIE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5309 #define UART0_C2_RIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5310 #define UART0_C2_RIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5311 #define UART0_C2_TCIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5312 #define UART0_C2_TCIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5313 #define UART0_C2_TIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5314 #define UART0_C2_TIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5315 /* S1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5316 #define UART0_S1_PF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5317 #define UART0_S1_PF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5318 #define UART0_S1_FE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5319 #define UART0_S1_FE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5320 #define UART0_S1_NF_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5321 #define UART0_S1_NF_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5322 #define UART0_S1_OR_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5323 #define UART0_S1_OR_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5324 #define UART0_S1_IDLE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5325 #define UART0_S1_IDLE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5326 #define UART0_S1_RDRF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5327 #define UART0_S1_RDRF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5328 #define UART0_S1_TC_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5329 #define UART0_S1_TC_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5330 #define UART0_S1_TDRE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5331 #define UART0_S1_TDRE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5332 /* S2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5333 #define UART0_S2_RAF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5334 #define UART0_S2_RAF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5335 #define UART0_S2_LBKDE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5336 #define UART0_S2_LBKDE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5337 #define UART0_S2_BRK13_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5338 #define UART0_S2_BRK13_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5339 #define UART0_S2_RWUID_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5340 #define UART0_S2_RWUID_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5341 #define UART0_S2_RXINV_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5342 #define UART0_S2_RXINV_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5343 #define UART0_S2_MSBF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5344 #define UART0_S2_MSBF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5345 #define UART0_S2_RXEDGIF_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5346 #define UART0_S2_RXEDGIF_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5347 #define UART0_S2_LBKDIF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5348 #define UART0_S2_LBKDIF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5349 /* C3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5350 #define UART0_C3_PEIE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5351 #define UART0_C3_PEIE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5352 #define UART0_C3_FEIE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5353 #define UART0_C3_FEIE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5354 #define UART0_C3_NEIE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5355 #define UART0_C3_NEIE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5356 #define UART0_C3_ORIE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5357 #define UART0_C3_ORIE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5358 #define UART0_C3_TXINV_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5359 #define UART0_C3_TXINV_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5360 #define UART0_C3_TXDIR_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5361 #define UART0_C3_TXDIR_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5362 #define UART0_C3_R9T8_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5363 #define UART0_C3_R9T8_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5364 #define UART0_C3_R8T9_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5365 #define UART0_C3_R8T9_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5366 /* D Bit Fields */
AnnaBridge 171:3a7713b1edbc 5367 #define UART0_D_R0T0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5368 #define UART0_D_R0T0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5369 #define UART0_D_R1T1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5370 #define UART0_D_R1T1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5371 #define UART0_D_R2T2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5372 #define UART0_D_R2T2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5373 #define UART0_D_R3T3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5374 #define UART0_D_R3T3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5375 #define UART0_D_R4T4_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5376 #define UART0_D_R4T4_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5377 #define UART0_D_R5T5_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5378 #define UART0_D_R5T5_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5379 #define UART0_D_R6T6_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5380 #define UART0_D_R6T6_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5381 #define UART0_D_R7T7_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5382 #define UART0_D_R7T7_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5383 /* MA1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5384 #define UART0_MA1_MA_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 5385 #define UART0_MA1_MA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5386 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
AnnaBridge 171:3a7713b1edbc 5387 /* MA2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5388 #define UART0_MA2_MA_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 5389 #define UART0_MA2_MA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5390 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
AnnaBridge 171:3a7713b1edbc 5391 /* C4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5392 #define UART0_C4_OSR_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 5393 #define UART0_C4_OSR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5394 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
AnnaBridge 171:3a7713b1edbc 5395 #define UART0_C4_M10_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5396 #define UART0_C4_M10_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5397 #define UART0_C4_MAEN2_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5398 #define UART0_C4_MAEN2_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5399 #define UART0_C4_MAEN1_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5400 #define UART0_C4_MAEN1_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5401 /* C5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5402 #define UART0_C5_RESYNCDIS_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5403 #define UART0_C5_RESYNCDIS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5404 #define UART0_C5_BOTHEDGE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5405 #define UART0_C5_BOTHEDGE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5406 #define UART0_C5_RDMAE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5407 #define UART0_C5_RDMAE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5408 #define UART0_C5_TDMAE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5409 #define UART0_C5_TDMAE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5410
AnnaBridge 171:3a7713b1edbc 5411 /*!
AnnaBridge 171:3a7713b1edbc 5412 * @}
AnnaBridge 171:3a7713b1edbc 5413 */ /* end of group UART0_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5414
AnnaBridge 171:3a7713b1edbc 5415
AnnaBridge 171:3a7713b1edbc 5416 /* UART0 - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5417 /** Peripheral UART0 base address */
AnnaBridge 171:3a7713b1edbc 5418 #define UART0_BASE (0x4006A000u)
AnnaBridge 171:3a7713b1edbc 5419 /** Peripheral UART0 base pointer */
AnnaBridge 171:3a7713b1edbc 5420 #define UART0 ((UART0_Type *)UART0_BASE)
AnnaBridge 171:3a7713b1edbc 5421 /** Array initializer of UART0 peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5422 #define UART0_BASES { UART0 }
AnnaBridge 171:3a7713b1edbc 5423
AnnaBridge 171:3a7713b1edbc 5424 /*!
AnnaBridge 171:3a7713b1edbc 5425 * @}
AnnaBridge 171:3a7713b1edbc 5426 */ /* end of group UART0_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5427
AnnaBridge 171:3a7713b1edbc 5428
AnnaBridge 171:3a7713b1edbc 5429 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5430 -- USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5431 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5432
AnnaBridge 171:3a7713b1edbc 5433 /*!
AnnaBridge 171:3a7713b1edbc 5434 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5435 * @{
AnnaBridge 171:3a7713b1edbc 5436 */
AnnaBridge 171:3a7713b1edbc 5437
AnnaBridge 171:3a7713b1edbc 5438 /** USB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5439 typedef struct {
AnnaBridge 171:3a7713b1edbc 5440 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5441 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 5442 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5443 uint8_t RESERVED_1[3];
AnnaBridge 171:3a7713b1edbc 5444 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 5445 uint8_t RESERVED_2[3];
AnnaBridge 171:3a7713b1edbc 5446 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 5447 uint8_t RESERVED_3[3];
AnnaBridge 171:3a7713b1edbc 5448 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 5449 uint8_t RESERVED_4[3];
AnnaBridge 171:3a7713b1edbc 5450 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 5451 uint8_t RESERVED_5[3];
AnnaBridge 171:3a7713b1edbc 5452 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 5453 uint8_t RESERVED_6[3];
AnnaBridge 171:3a7713b1edbc 5454 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 5455 uint8_t RESERVED_7[99];
AnnaBridge 171:3a7713b1edbc 5456 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 5457 uint8_t RESERVED_8[3];
AnnaBridge 171:3a7713b1edbc 5458 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 5459 uint8_t RESERVED_9[3];
AnnaBridge 171:3a7713b1edbc 5460 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 5461 uint8_t RESERVED_10[3];
AnnaBridge 171:3a7713b1edbc 5462 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 5463 uint8_t RESERVED_11[3];
AnnaBridge 171:3a7713b1edbc 5464 __I uint8_t STAT; /**< Status register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 5465 uint8_t RESERVED_12[3];
AnnaBridge 171:3a7713b1edbc 5466 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 5467 uint8_t RESERVED_13[3];
AnnaBridge 171:3a7713b1edbc 5468 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 5469 uint8_t RESERVED_14[3];
AnnaBridge 171:3a7713b1edbc 5470 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 5471 uint8_t RESERVED_15[3];
AnnaBridge 171:3a7713b1edbc 5472 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 5473 uint8_t RESERVED_16[3];
AnnaBridge 171:3a7713b1edbc 5474 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 5475 uint8_t RESERVED_17[3];
AnnaBridge 171:3a7713b1edbc 5476 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
AnnaBridge 171:3a7713b1edbc 5477 uint8_t RESERVED_18[3];
AnnaBridge 171:3a7713b1edbc 5478 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
AnnaBridge 171:3a7713b1edbc 5479 uint8_t RESERVED_19[3];
AnnaBridge 171:3a7713b1edbc 5480 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 5481 uint8_t RESERVED_20[3];
AnnaBridge 171:3a7713b1edbc 5482 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 5483 uint8_t RESERVED_21[11];
AnnaBridge 171:3a7713b1edbc 5484 struct { /* offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5485 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5486 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 5487 } ENDPOINT[16];
AnnaBridge 171:3a7713b1edbc 5488 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 5489 uint8_t RESERVED_22[3];
AnnaBridge 171:3a7713b1edbc 5490 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 5491 uint8_t RESERVED_23[3];
AnnaBridge 171:3a7713b1edbc 5492 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 5493 uint8_t RESERVED_24[3];
AnnaBridge 171:3a7713b1edbc 5494 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 5495 uint8_t RESERVED_25[7];
AnnaBridge 171:3a7713b1edbc 5496 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
AnnaBridge 171:3a7713b1edbc 5497 } USB_Type;
AnnaBridge 171:3a7713b1edbc 5498
AnnaBridge 171:3a7713b1edbc 5499 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5500 -- USB Register Masks
AnnaBridge 171:3a7713b1edbc 5501 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5502
AnnaBridge 171:3a7713b1edbc 5503 /*!
AnnaBridge 171:3a7713b1edbc 5504 * @addtogroup USB_Register_Masks USB Register Masks
AnnaBridge 171:3a7713b1edbc 5505 * @{
AnnaBridge 171:3a7713b1edbc 5506 */
AnnaBridge 171:3a7713b1edbc 5507
AnnaBridge 171:3a7713b1edbc 5508 /* PERID Bit Fields */
AnnaBridge 171:3a7713b1edbc 5509 #define USB_PERID_ID_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 5510 #define USB_PERID_ID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5511 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
AnnaBridge 171:3a7713b1edbc 5512 /* IDCOMP Bit Fields */
AnnaBridge 171:3a7713b1edbc 5513 #define USB_IDCOMP_NID_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 5514 #define USB_IDCOMP_NID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5515 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
AnnaBridge 171:3a7713b1edbc 5516 /* REV Bit Fields */
AnnaBridge 171:3a7713b1edbc 5517 #define USB_REV_REV_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 5518 #define USB_REV_REV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5519 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
AnnaBridge 171:3a7713b1edbc 5520 /* ADDINFO Bit Fields */
AnnaBridge 171:3a7713b1edbc 5521 #define USB_ADDINFO_IEHOST_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5522 #define USB_ADDINFO_IEHOST_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5523 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
AnnaBridge 171:3a7713b1edbc 5524 #define USB_ADDINFO_IRQNUM_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5525 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
AnnaBridge 171:3a7713b1edbc 5526 /* OTGISTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 5527 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5528 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5529 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5530 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5531 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5532 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5533 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5534 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5535 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5536 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5537 #define USB_OTGISTAT_IDCHG_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5538 #define USB_OTGISTAT_IDCHG_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5539 /* OTGICR Bit Fields */
AnnaBridge 171:3a7713b1edbc 5540 #define USB_OTGICR_AVBUSEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5541 #define USB_OTGICR_AVBUSEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5542 #define USB_OTGICR_BSESSEN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5543 #define USB_OTGICR_BSESSEN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5544 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5545 #define USB_OTGICR_SESSVLDEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5546 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5547 #define USB_OTGICR_LINESTATEEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5548 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5549 #define USB_OTGICR_ONEMSECEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5550 #define USB_OTGICR_IDEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5551 #define USB_OTGICR_IDEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5552 /* OTGSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 5553 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5554 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5555 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5556 #define USB_OTGSTAT_BSESSEND_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5557 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5558 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5559 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5560 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5561 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5562 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5563 #define USB_OTGSTAT_ID_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5564 #define USB_OTGSTAT_ID_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5565 /* OTGCTL Bit Fields */
AnnaBridge 171:3a7713b1edbc 5566 #define USB_OTGCTL_OTGEN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5567 #define USB_OTGCTL_OTGEN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5568 #define USB_OTGCTL_DMLOW_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5569 #define USB_OTGCTL_DMLOW_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5570 #define USB_OTGCTL_DPLOW_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5571 #define USB_OTGCTL_DPLOW_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5572 #define USB_OTGCTL_DPHIGH_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5573 #define USB_OTGCTL_DPHIGH_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5574 /* ISTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 5575 #define USB_ISTAT_USBRST_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5576 #define USB_ISTAT_USBRST_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5577 #define USB_ISTAT_ERROR_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5578 #define USB_ISTAT_ERROR_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5579 #define USB_ISTAT_SOFTOK_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5580 #define USB_ISTAT_SOFTOK_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5581 #define USB_ISTAT_TOKDNE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5582 #define USB_ISTAT_TOKDNE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5583 #define USB_ISTAT_SLEEP_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5584 #define USB_ISTAT_SLEEP_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5585 #define USB_ISTAT_RESUME_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5586 #define USB_ISTAT_RESUME_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5587 #define USB_ISTAT_ATTACH_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5588 #define USB_ISTAT_ATTACH_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5589 #define USB_ISTAT_STALL_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5590 #define USB_ISTAT_STALL_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5591 /* INTEN Bit Fields */
AnnaBridge 171:3a7713b1edbc 5592 #define USB_INTEN_USBRSTEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5593 #define USB_INTEN_USBRSTEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5594 #define USB_INTEN_ERROREN_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5595 #define USB_INTEN_ERROREN_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5596 #define USB_INTEN_SOFTOKEN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5597 #define USB_INTEN_SOFTOKEN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5598 #define USB_INTEN_TOKDNEEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5599 #define USB_INTEN_TOKDNEEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5600 #define USB_INTEN_SLEEPEN_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5601 #define USB_INTEN_SLEEPEN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5602 #define USB_INTEN_RESUMEEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5603 #define USB_INTEN_RESUMEEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5604 #define USB_INTEN_ATTACHEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5605 #define USB_INTEN_ATTACHEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5606 #define USB_INTEN_STALLEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5607 #define USB_INTEN_STALLEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5608 /* ERRSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 5609 #define USB_ERRSTAT_PIDERR_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5610 #define USB_ERRSTAT_PIDERR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5611 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5612 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5613 #define USB_ERRSTAT_CRC16_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5614 #define USB_ERRSTAT_CRC16_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5615 #define USB_ERRSTAT_DFN8_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5616 #define USB_ERRSTAT_DFN8_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5617 #define USB_ERRSTAT_BTOERR_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5618 #define USB_ERRSTAT_BTOERR_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5619 #define USB_ERRSTAT_DMAERR_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5620 #define USB_ERRSTAT_DMAERR_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5621 #define USB_ERRSTAT_BTSERR_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5622 #define USB_ERRSTAT_BTSERR_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5623 /* ERREN Bit Fields */
AnnaBridge 171:3a7713b1edbc 5624 #define USB_ERREN_PIDERREN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5625 #define USB_ERREN_PIDERREN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5626 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5627 #define USB_ERREN_CRC5EOFEN_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5628 #define USB_ERREN_CRC16EN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5629 #define USB_ERREN_CRC16EN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5630 #define USB_ERREN_DFN8EN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5631 #define USB_ERREN_DFN8EN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5632 #define USB_ERREN_BTOERREN_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5633 #define USB_ERREN_BTOERREN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5634 #define USB_ERREN_DMAERREN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5635 #define USB_ERREN_DMAERREN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5636 #define USB_ERREN_BTSERREN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5637 #define USB_ERREN_BTSERREN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5638 /* STAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 5639 #define USB_STAT_ODD_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5640 #define USB_STAT_ODD_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5641 #define USB_STAT_TX_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5642 #define USB_STAT_TX_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5643 #define USB_STAT_ENDP_MASK 0xF0u
AnnaBridge 171:3a7713b1edbc 5644 #define USB_STAT_ENDP_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5645 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
AnnaBridge 171:3a7713b1edbc 5646 /* CTL Bit Fields */
AnnaBridge 171:3a7713b1edbc 5647 #define USB_CTL_USBENSOFEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5648 #define USB_CTL_USBENSOFEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5649 #define USB_CTL_ODDRST_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5650 #define USB_CTL_ODDRST_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5651 #define USB_CTL_RESUME_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5652 #define USB_CTL_RESUME_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5653 #define USB_CTL_HOSTMODEEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5654 #define USB_CTL_HOSTMODEEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5655 #define USB_CTL_RESET_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5656 #define USB_CTL_RESET_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5657 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5658 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5659 #define USB_CTL_SE0_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5660 #define USB_CTL_SE0_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5661 #define USB_CTL_JSTATE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5662 #define USB_CTL_JSTATE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5663 /* ADDR Bit Fields */
AnnaBridge 171:3a7713b1edbc 5664 #define USB_ADDR_ADDR_MASK 0x7Fu
AnnaBridge 171:3a7713b1edbc 5665 #define USB_ADDR_ADDR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5666 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
AnnaBridge 171:3a7713b1edbc 5667 #define USB_ADDR_LSEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5668 #define USB_ADDR_LSEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5669 /* BDTPAGE1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5670 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
AnnaBridge 171:3a7713b1edbc 5671 #define USB_BDTPAGE1_BDTBA_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5672 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 5673 /* FRMNUML Bit Fields */
AnnaBridge 171:3a7713b1edbc 5674 #define USB_FRMNUML_FRM_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 5675 #define USB_FRMNUML_FRM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5676 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 5677 /* FRMNUMH Bit Fields */
AnnaBridge 171:3a7713b1edbc 5678 #define USB_FRMNUMH_FRM_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 5679 #define USB_FRMNUMH_FRM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5680 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 5681 /* TOKEN Bit Fields */
AnnaBridge 171:3a7713b1edbc 5682 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 5683 #define USB_TOKEN_TOKENENDPT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5684 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
AnnaBridge 171:3a7713b1edbc 5685 #define USB_TOKEN_TOKENPID_MASK 0xF0u
AnnaBridge 171:3a7713b1edbc 5686 #define USB_TOKEN_TOKENPID_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5687 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
AnnaBridge 171:3a7713b1edbc 5688 /* SOFTHLD Bit Fields */
AnnaBridge 171:3a7713b1edbc 5689 #define USB_SOFTHLD_CNT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 5690 #define USB_SOFTHLD_CNT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5691 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 5692 /* BDTPAGE2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5693 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 5694 #define USB_BDTPAGE2_BDTBA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5695 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 5696 /* BDTPAGE3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5697 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 5698 #define USB_BDTPAGE3_BDTBA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5699 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 5700 /* ENDPT Bit Fields */
AnnaBridge 171:3a7713b1edbc 5701 #define USB_ENDPT_EPHSHK_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5702 #define USB_ENDPT_EPHSHK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5703 #define USB_ENDPT_EPSTALL_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5704 #define USB_ENDPT_EPSTALL_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5705 #define USB_ENDPT_EPTXEN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 5706 #define USB_ENDPT_EPTXEN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 5707 #define USB_ENDPT_EPRXEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 5708 #define USB_ENDPT_EPRXEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 5709 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5710 #define USB_ENDPT_EPCTLDIS_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5711 #define USB_ENDPT_RETRYDIS_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5712 #define USB_ENDPT_RETRYDIS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5713 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5714 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5715 /* USBCTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 5716 #define USB_USBCTRL_PDE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5717 #define USB_USBCTRL_PDE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5718 #define USB_USBCTRL_SUSP_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5719 #define USB_USBCTRL_SUSP_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5720 /* OBSERVE Bit Fields */
AnnaBridge 171:3a7713b1edbc 5721 #define USB_OBSERVE_DMPD_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5722 #define USB_OBSERVE_DMPD_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5723 #define USB_OBSERVE_DPPD_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 5724 #define USB_OBSERVE_DPPD_SHIFT 6
AnnaBridge 171:3a7713b1edbc 5725 #define USB_OBSERVE_DPPU_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5726 #define USB_OBSERVE_DPPU_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5727 /* CONTROL Bit Fields */
AnnaBridge 171:3a7713b1edbc 5728 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 5729 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
AnnaBridge 171:3a7713b1edbc 5730 /* USBTRC0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 5731 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 5732 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5733 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 5734 #define USB_USBTRC0_SYNC_DET_SHIFT 1
AnnaBridge 171:3a7713b1edbc 5735 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 5736 #define USB_USBTRC0_USBRESMEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 5737 #define USB_USBTRC0_USBRESET_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 5738 #define USB_USBTRC0_USBRESET_SHIFT 7
AnnaBridge 171:3a7713b1edbc 5739 /* USBFRMADJUST Bit Fields */
AnnaBridge 171:3a7713b1edbc 5740 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 5741 #define USB_USBFRMADJUST_ADJ_SHIFT 0
AnnaBridge 171:3a7713b1edbc 5742 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 5743
AnnaBridge 171:3a7713b1edbc 5744 /*!
AnnaBridge 171:3a7713b1edbc 5745 * @}
AnnaBridge 171:3a7713b1edbc 5746 */ /* end of group USB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5747
AnnaBridge 171:3a7713b1edbc 5748
AnnaBridge 171:3a7713b1edbc 5749 /* USB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5750 /** Peripheral USB0 base address */
AnnaBridge 171:3a7713b1edbc 5751 #define USB0_BASE (0x40072000u)
AnnaBridge 171:3a7713b1edbc 5752 /** Peripheral USB0 base pointer */
AnnaBridge 171:3a7713b1edbc 5753 #define USB0 ((USB_Type *)USB0_BASE)
AnnaBridge 171:3a7713b1edbc 5754 /** Array initializer of USB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5755 #define USB_BASES { USB0 }
AnnaBridge 171:3a7713b1edbc 5756
AnnaBridge 171:3a7713b1edbc 5757 /*!
AnnaBridge 171:3a7713b1edbc 5758 * @}
AnnaBridge 171:3a7713b1edbc 5759 */ /* end of group USB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5760
AnnaBridge 171:3a7713b1edbc 5761
AnnaBridge 171:3a7713b1edbc 5762 /*
AnnaBridge 171:3a7713b1edbc 5763 ** End of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 5764 */
AnnaBridge 171:3a7713b1edbc 5765
AnnaBridge 171:3a7713b1edbc 5766 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 5767 #pragma pop
AnnaBridge 171:3a7713b1edbc 5768 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 5769 #pragma pop
AnnaBridge 171:3a7713b1edbc 5770 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 5771 /* leave anonymous unions enabled */
AnnaBridge 171:3a7713b1edbc 5772 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 5773 #pragma language=default
AnnaBridge 171:3a7713b1edbc 5774 #else
AnnaBridge 171:3a7713b1edbc 5775 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 5776 #endif
AnnaBridge 171:3a7713b1edbc 5777
AnnaBridge 171:3a7713b1edbc 5778 /*!
AnnaBridge 171:3a7713b1edbc 5779 * @}
AnnaBridge 171:3a7713b1edbc 5780 */ /* end of group Peripheral_access_layer */
AnnaBridge 171:3a7713b1edbc 5781
AnnaBridge 171:3a7713b1edbc 5782
AnnaBridge 171:3a7713b1edbc 5783 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5784 -- Backward Compatibility
AnnaBridge 171:3a7713b1edbc 5785 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5786
AnnaBridge 171:3a7713b1edbc 5787 /*!
AnnaBridge 171:3a7713b1edbc 5788 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
AnnaBridge 171:3a7713b1edbc 5789 * @{
AnnaBridge 171:3a7713b1edbc 5790 */
AnnaBridge 171:3a7713b1edbc 5791
AnnaBridge 171:3a7713b1edbc 5792 /* No backward compatibility issues. */
AnnaBridge 171:3a7713b1edbc 5793
AnnaBridge 171:3a7713b1edbc 5794 /*!
AnnaBridge 171:3a7713b1edbc 5795 * @}
AnnaBridge 171:3a7713b1edbc 5796 */ /* end of group Backward_Compatibility_Symbols */
AnnaBridge 171:3a7713b1edbc 5797
AnnaBridge 171:3a7713b1edbc 5798
AnnaBridge 171:3a7713b1edbc 5799 #endif /* #if !defined(MKL46Z4_H_) */
AnnaBridge 171:3a7713b1edbc 5800
AnnaBridge 171:3a7713b1edbc 5801 /* MKL46Z4.h, eof. */