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TARGET_K82F/TOOLCHAIN_IAR/fsl_sdramc.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_UBRIDGE/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_sdramc.h@145:64910690c574
mbed library. Release version 164
Who changed what in which revision?
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AnnaBridge | 145:64910690c574 | 1 | /* |
AnnaBridge | 145:64910690c574 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
AnnaBridge | 145:64910690c574 | 3 | * All rights reserved. |
AnnaBridge | 145:64910690c574 | 4 | * |
AnnaBridge | 145:64910690c574 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 145:64910690c574 | 6 | * are permitted provided that the following conditions are met: |
AnnaBridge | 145:64910690c574 | 7 | * |
AnnaBridge | 145:64910690c574 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
AnnaBridge | 145:64910690c574 | 9 | * of conditions and the following disclaimer. |
AnnaBridge | 145:64910690c574 | 10 | * |
AnnaBridge | 145:64910690c574 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
AnnaBridge | 145:64910690c574 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
AnnaBridge | 145:64910690c574 | 13 | * other materials provided with the distribution. |
AnnaBridge | 145:64910690c574 | 14 | * |
AnnaBridge | 145:64910690c574 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
AnnaBridge | 145:64910690c574 | 16 | * contributors may be used to endorse or promote products derived from this |
AnnaBridge | 145:64910690c574 | 17 | * software without specific prior written permission. |
AnnaBridge | 145:64910690c574 | 18 | * |
AnnaBridge | 145:64910690c574 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
AnnaBridge | 145:64910690c574 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
AnnaBridge | 145:64910690c574 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 145:64910690c574 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
AnnaBridge | 145:64910690c574 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
AnnaBridge | 145:64910690c574 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
AnnaBridge | 145:64910690c574 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
AnnaBridge | 145:64910690c574 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
AnnaBridge | 145:64910690c574 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
AnnaBridge | 145:64910690c574 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 145:64910690c574 | 29 | */ |
AnnaBridge | 145:64910690c574 | 30 | #ifndef _FSL_SDRAMC_H_ |
AnnaBridge | 145:64910690c574 | 31 | #define _FSL_SDRAMC_H_ |
AnnaBridge | 145:64910690c574 | 32 | |
AnnaBridge | 145:64910690c574 | 33 | #include "fsl_common.h" |
AnnaBridge | 145:64910690c574 | 34 | |
AnnaBridge | 145:64910690c574 | 35 | /*! |
AnnaBridge | 145:64910690c574 | 36 | * @addtogroup sdramc |
AnnaBridge | 145:64910690c574 | 37 | * @{ |
AnnaBridge | 145:64910690c574 | 38 | */ |
AnnaBridge | 145:64910690c574 | 39 | |
AnnaBridge | 145:64910690c574 | 40 | |
AnnaBridge | 145:64910690c574 | 41 | /******************************************************************************* |
AnnaBridge | 145:64910690c574 | 42 | * Definitions |
AnnaBridge | 145:64910690c574 | 43 | ******************************************************************************/ |
AnnaBridge | 145:64910690c574 | 44 | |
AnnaBridge | 145:64910690c574 | 45 | /*! @name Driver version */ |
AnnaBridge | 145:64910690c574 | 46 | /*@{*/ |
AnnaBridge | 145:64910690c574 | 47 | /*! @brief SDRAMC driver version 2.1.0. */ |
AnnaBridge | 145:64910690c574 | 48 | #define FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) |
AnnaBridge | 145:64910690c574 | 49 | /*@}*/ |
AnnaBridge | 145:64910690c574 | 50 | |
AnnaBridge | 145:64910690c574 | 51 | /*! @brief SDRAM controller auto-refresh timing. */ |
AnnaBridge | 145:64910690c574 | 52 | typedef enum _sdramc_refresh_time |
AnnaBridge | 145:64910690c574 | 53 | { |
AnnaBridge | 145:64910690c574 | 54 | kSDRAMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */ |
AnnaBridge | 145:64910690c574 | 55 | kSDRAMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */ |
AnnaBridge | 145:64910690c574 | 56 | kSDRAMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */ |
AnnaBridge | 145:64910690c574 | 57 | } sdramc_refresh_time_t; |
AnnaBridge | 145:64910690c574 | 58 | |
AnnaBridge | 145:64910690c574 | 59 | /*! |
AnnaBridge | 145:64910690c574 | 60 | * @brief Setting latency for SDRAM controller timing specifications. |
AnnaBridge | 145:64910690c574 | 61 | * |
AnnaBridge | 145:64910690c574 | 62 | * The latency setting affects the following SDRAM timing specifications: |
AnnaBridge | 145:64910690c574 | 63 | * - trcd: SRAS assertion to SCAS assertion \n |
AnnaBridge | 145:64910690c574 | 64 | * - tcasl: SCAS assertion to data out \n |
AnnaBridge | 145:64910690c574 | 65 | * - tras: ACTV command to Precharge command \n |
AnnaBridge | 145:64910690c574 | 66 | * - trp: Precharge command to ACTV command \n |
AnnaBridge | 145:64910690c574 | 67 | * - trwl, trdl: Last data input to Precharge command \n |
AnnaBridge | 145:64910690c574 | 68 | * - tep: Last data out to Precharge command \n |
AnnaBridge | 145:64910690c574 | 69 | * The details of the latency setting and timing specifications are shown in the following table list. \n |
AnnaBridge | 145:64910690c574 | 70 | * latency trcd: tcasl tras trp trwl,trdl tep \n |
AnnaBridge | 145:64910690c574 | 71 | * 0 1 bus clock 1 bus clock 2 bus clocks 1 bus clock 1 bus clock 1 bus clock \n |
AnnaBridge | 145:64910690c574 | 72 | * 1 2 bus clock 2 bus clock 4 bus clocks 2 bus clock 1 bus clock 1 bus clock \n |
AnnaBridge | 145:64910690c574 | 73 | * 2 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n |
AnnaBridge | 145:64910690c574 | 74 | * 3 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n |
AnnaBridge | 145:64910690c574 | 75 | */ |
AnnaBridge | 145:64910690c574 | 76 | typedef enum _sdramc_latency |
AnnaBridge | 145:64910690c574 | 77 | { |
AnnaBridge | 145:64910690c574 | 78 | kSDRAMC_LatencyZero = 0x0U, /*!< Latency 0. */ |
AnnaBridge | 145:64910690c574 | 79 | kSDRAMC_LatencyOne, /*!< Latency 1. */ |
AnnaBridge | 145:64910690c574 | 80 | kSDRAMC_LatencyTwo, /*!< Latency 2. */ |
AnnaBridge | 145:64910690c574 | 81 | kSDRAMC_LatencyThree, /*!< Latency 3. */ |
AnnaBridge | 145:64910690c574 | 82 | } sdramc_latency_t; |
AnnaBridge | 145:64910690c574 | 83 | |
AnnaBridge | 145:64910690c574 | 84 | /*! @brief SDRAM controller command bit location. */ |
AnnaBridge | 145:64910690c574 | 85 | typedef enum _sdramc_command_bit_location |
AnnaBridge | 145:64910690c574 | 86 | { |
AnnaBridge | 145:64910690c574 | 87 | kSDRAMC_Commandbit17 = 0x0U, /*!< Command bit location is bit 17. */ |
AnnaBridge | 145:64910690c574 | 88 | kSDRAMC_Commandbit18, /*!< Command bit location is bit 18. */ |
AnnaBridge | 145:64910690c574 | 89 | kSDRAMC_Commandbit19, /*!< Command bit location is bit 19. */ |
AnnaBridge | 145:64910690c574 | 90 | kSDRAMC_Commandbit20, /*!< Command bit location is bit 20. */ |
AnnaBridge | 145:64910690c574 | 91 | kSDRAMC_Commandbit21, /*!< Command bit location is bit 21. */ |
AnnaBridge | 145:64910690c574 | 92 | kSDRAMC_Commandbit22, /*!< Command bit location is bit 22. */ |
AnnaBridge | 145:64910690c574 | 93 | kSDRAMC_Commandbit23, /*!< Command bit location is bit 23. */ |
AnnaBridge | 145:64910690c574 | 94 | kSDRAMC_Commandbit24 /*!< Command bit location is bit 24. */ |
AnnaBridge | 145:64910690c574 | 95 | } sdramc_command_bit_location_t; |
AnnaBridge | 145:64910690c574 | 96 | |
AnnaBridge | 145:64910690c574 | 97 | /*! @brief SDRAM controller command. */ |
AnnaBridge | 145:64910690c574 | 98 | typedef enum _sdramc_command |
AnnaBridge | 145:64910690c574 | 99 | { |
AnnaBridge | 145:64910690c574 | 100 | kSDRAMC_ImrsCommand = 0x0U, /*!< Initiate MRS command. */ |
AnnaBridge | 145:64910690c574 | 101 | kSDRAMC_PrechargeCommand, /*!< Initiate precharge command. */ |
AnnaBridge | 145:64910690c574 | 102 | kSDRAMC_SelfrefreshEnterCommand, /*!< Enter self-refresh command. */ |
AnnaBridge | 145:64910690c574 | 103 | kSDRAMC_SelfrefreshExitCommand, /*!< Exit self-refresh command. */ |
AnnaBridge | 145:64910690c574 | 104 | kSDRAMC_AutoRefreshEnableCommand, /*!< Enable Auto refresh command. */ |
AnnaBridge | 145:64910690c574 | 105 | kSDRAMC_AutoRefreshDisableCommand, /*!< Disable Auto refresh command. */ |
AnnaBridge | 145:64910690c574 | 106 | } sdramc_command_t; |
AnnaBridge | 145:64910690c574 | 107 | |
AnnaBridge | 145:64910690c574 | 108 | /*! @brief SDRAM port size. */ |
AnnaBridge | 145:64910690c574 | 109 | typedef enum _sdramc_port_size |
AnnaBridge | 145:64910690c574 | 110 | { |
AnnaBridge | 145:64910690c574 | 111 | kSDRAMC_PortSize32Bit = 0x0U, /*!< 32-Bit port size. */ |
AnnaBridge | 145:64910690c574 | 112 | kSDRAMC_PortSize8Bit, /*!< 8-Bit port size. */ |
AnnaBridge | 145:64910690c574 | 113 | kSDRAMC_PortSize16Bit /*!< 16-Bit port size. */ |
AnnaBridge | 145:64910690c574 | 114 | } sdramc_port_size_t; |
AnnaBridge | 145:64910690c574 | 115 | |
AnnaBridge | 145:64910690c574 | 116 | /*! @brief SDRAM controller block selection. */ |
AnnaBridge | 145:64910690c574 | 117 | typedef enum _sdramc_block_selection |
AnnaBridge | 145:64910690c574 | 118 | { |
AnnaBridge | 145:64910690c574 | 119 | kSDRAMC_Block0 = 0x0U, /*!< Select SDRAM block 0. */ |
AnnaBridge | 145:64910690c574 | 120 | kSDRAMC_Block1, /*!< Select SDRAM block 1. */ |
AnnaBridge | 145:64910690c574 | 121 | } sdramc_block_selection_t; |
AnnaBridge | 145:64910690c574 | 122 | |
AnnaBridge | 145:64910690c574 | 123 | /*! @brief SDRAM controller block control configuration structure. */ |
AnnaBridge | 145:64910690c574 | 124 | typedef struct _sdramc_blockctl_config |
AnnaBridge | 145:64910690c574 | 125 | { |
AnnaBridge | 145:64910690c574 | 126 | sdramc_block_selection_t block; /*!< The block number. */ |
AnnaBridge | 145:64910690c574 | 127 | sdramc_port_size_t portSize; /*!< The port size of the associated SDRAM block. */ |
AnnaBridge | 145:64910690c574 | 128 | sdramc_command_bit_location_t location; /*!< The command bit location. */ |
AnnaBridge | 145:64910690c574 | 129 | sdramc_latency_t latency; /*!< The latency for some timing specifications. */ |
AnnaBridge | 145:64910690c574 | 130 | uint32_t address; /*!< The base address of the SDRAM block. */ |
AnnaBridge | 145:64910690c574 | 131 | uint32_t addressMask; /*!< The base address mask of the SDRAM block. */ |
AnnaBridge | 145:64910690c574 | 132 | } sdramc_blockctl_config_t; |
AnnaBridge | 145:64910690c574 | 133 | |
AnnaBridge | 145:64910690c574 | 134 | /*! @brief SDRAM controller refresh timing configuration structure. */ |
AnnaBridge | 145:64910690c574 | 135 | typedef struct _sdramc_refresh_config |
AnnaBridge | 145:64910690c574 | 136 | { |
AnnaBridge | 145:64910690c574 | 137 | sdramc_refresh_time_t refreshTime; /*!< Trc:The number of bus clocks inserted |
AnnaBridge | 145:64910690c574 | 138 | between a REF and next ACTIVE command. */ |
AnnaBridge | 145:64910690c574 | 139 | uint32_t sdramRefreshRow; /*!< The SDRAM refresh time each row: ns/row. */ |
AnnaBridge | 145:64910690c574 | 140 | uint32_t busClock_Hz; /*!< The bus clock for SDRAMC. */ |
AnnaBridge | 145:64910690c574 | 141 | } sdramc_refresh_config_t; |
AnnaBridge | 145:64910690c574 | 142 | |
AnnaBridge | 145:64910690c574 | 143 | /*! |
AnnaBridge | 145:64910690c574 | 144 | * @brief SDRAM controller configuration structure. |
AnnaBridge | 145:64910690c574 | 145 | * |
AnnaBridge | 145:64910690c574 | 146 | * Defines a configure structure and uses the SDRAMC_Configure() function to make necessary |
AnnaBridge | 145:64910690c574 | 147 | * initializations. |
AnnaBridge | 145:64910690c574 | 148 | */ |
AnnaBridge | 145:64910690c574 | 149 | typedef struct _sdramc_config_t |
AnnaBridge | 145:64910690c574 | 150 | { |
AnnaBridge | 145:64910690c574 | 151 | sdramc_refresh_config_t *refreshConfig; /*!< Refresh timing configure structure pointer. */ |
AnnaBridge | 145:64910690c574 | 152 | sdramc_blockctl_config_t *blockConfig; /*!< Block configure structure pointer. If both SDRAM |
AnnaBridge | 145:64910690c574 | 153 | blocks are used, use the two continuous blockConfig. */ |
AnnaBridge | 145:64910690c574 | 154 | uint8_t numBlockConfig; /*!< SDRAM block numbers for configuration. */ |
AnnaBridge | 145:64910690c574 | 155 | } sdramc_config_t; |
AnnaBridge | 145:64910690c574 | 156 | |
AnnaBridge | 145:64910690c574 | 157 | /******************************************************************************* |
AnnaBridge | 145:64910690c574 | 158 | * API |
AnnaBridge | 145:64910690c574 | 159 | ******************************************************************************/ |
AnnaBridge | 145:64910690c574 | 160 | |
AnnaBridge | 145:64910690c574 | 161 | #if defined(__cplusplus) |
AnnaBridge | 145:64910690c574 | 162 | extern "C" { |
AnnaBridge | 145:64910690c574 | 163 | #endif |
AnnaBridge | 145:64910690c574 | 164 | |
AnnaBridge | 145:64910690c574 | 165 | /*! |
AnnaBridge | 145:64910690c574 | 166 | * @name SDRAM Controller Initialization and De-initialization |
AnnaBridge | 145:64910690c574 | 167 | * @{ |
AnnaBridge | 145:64910690c574 | 168 | */ |
AnnaBridge | 145:64910690c574 | 169 | |
AnnaBridge | 145:64910690c574 | 170 | /*! |
AnnaBridge | 145:64910690c574 | 171 | * @brief Initializes the SDRAM controller. |
AnnaBridge | 145:64910690c574 | 172 | * This function ungates the SDRAM controller clock and initializes the SDRAM controller. |
AnnaBridge | 145:64910690c574 | 173 | * This function must be called before calling any other SDRAM controller driver functions. |
AnnaBridge | 145:64910690c574 | 174 | * Example |
AnnaBridge | 145:64910690c574 | 175 | @code |
AnnaBridge | 145:64910690c574 | 176 | sdramc_refresh_config_t refreshConfig; |
AnnaBridge | 145:64910690c574 | 177 | sdramc_blockctl_config_t blockConfig; |
AnnaBridge | 145:64910690c574 | 178 | sdramc_config_t config; |
AnnaBridge | 145:64910690c574 | 179 | |
AnnaBridge | 145:64910690c574 | 180 | refreshConfig.refreshTime = kSDRAM_RefreshThreeClocks; |
AnnaBridge | 145:64910690c574 | 181 | refreshConfig.sdramRefreshRow = 15625; |
AnnaBridge | 145:64910690c574 | 182 | refreshConfig.busClock = 60000000; |
AnnaBridge | 145:64910690c574 | 183 | |
AnnaBridge | 145:64910690c574 | 184 | blockConfig.block = kSDRAMC_Block0; |
AnnaBridge | 145:64910690c574 | 185 | blockConfig.portSize = kSDRAMC_PortSize16Bit; |
AnnaBridge | 145:64910690c574 | 186 | blockConfig.location = kSDRAMC_Commandbit19; |
AnnaBridge | 145:64910690c574 | 187 | blockConfig.latency = kSDRAMC_RefreshThreeClocks; |
AnnaBridge | 145:64910690c574 | 188 | blockConfig.address = SDRAM_START_ADDRESS; |
AnnaBridge | 145:64910690c574 | 189 | blockConfig.addressMask = 0x7c0000; |
AnnaBridge | 145:64910690c574 | 190 | |
AnnaBridge | 145:64910690c574 | 191 | config.refreshConfig = &refreshConfig, |
AnnaBridge | 145:64910690c574 | 192 | config.blockConfig = &blockConfig, |
AnnaBridge | 145:64910690c574 | 193 | config.totalBlocks = 1; |
AnnaBridge | 145:64910690c574 | 194 | |
AnnaBridge | 145:64910690c574 | 195 | SDRAMC_Init(SDRAM, &config); |
AnnaBridge | 145:64910690c574 | 196 | @endcode |
AnnaBridge | 145:64910690c574 | 197 | * |
AnnaBridge | 145:64910690c574 | 198 | * @param base SDRAM controller peripheral base address. |
AnnaBridge | 145:64910690c574 | 199 | * @param configure The SDRAM configuration structure pointer. |
AnnaBridge | 145:64910690c574 | 200 | */ |
AnnaBridge | 145:64910690c574 | 201 | void SDRAMC_Init(SDRAM_Type *base, sdramc_config_t *configure); |
AnnaBridge | 145:64910690c574 | 202 | |
AnnaBridge | 145:64910690c574 | 203 | /*! |
AnnaBridge | 145:64910690c574 | 204 | * @brief Deinitializes the SDRAM controller module and gates the clock. |
AnnaBridge | 145:64910690c574 | 205 | * This function gates the SDRAM controller clock. As a result, the SDRAM |
AnnaBridge | 145:64910690c574 | 206 | * controller module doesn't work after calling this function. |
AnnaBridge | 145:64910690c574 | 207 | * |
AnnaBridge | 145:64910690c574 | 208 | * @param base SDRAM controller peripheral base address. |
AnnaBridge | 145:64910690c574 | 209 | */ |
AnnaBridge | 145:64910690c574 | 210 | void SDRAMC_Deinit(SDRAM_Type *base); |
AnnaBridge | 145:64910690c574 | 211 | |
AnnaBridge | 145:64910690c574 | 212 | /* @} */ |
AnnaBridge | 145:64910690c574 | 213 | |
AnnaBridge | 145:64910690c574 | 214 | /*! |
AnnaBridge | 145:64910690c574 | 215 | * @name SDRAM Controller Basic Operation |
AnnaBridge | 145:64910690c574 | 216 | * @{ |
AnnaBridge | 145:64910690c574 | 217 | */ |
AnnaBridge | 145:64910690c574 | 218 | |
AnnaBridge | 145:64910690c574 | 219 | /*! |
AnnaBridge | 145:64910690c574 | 220 | * @brief Sends the SDRAM command. |
AnnaBridge | 145:64910690c574 | 221 | * This function sends commands to SDRAM. The commands are precharge command, initialization MRS command, |
AnnaBridge | 145:64910690c574 | 222 | * auto-refresh enable/disable command, and self-refresh enter/exit commands. |
AnnaBridge | 145:64910690c574 | 223 | * Note that the self-refresh enter/exit commands are all blocks setting and "block" |
AnnaBridge | 145:64910690c574 | 224 | * is ignored. Ensure to set the correct "block" when send other commands. |
AnnaBridge | 145:64910690c574 | 225 | * |
AnnaBridge | 145:64910690c574 | 226 | * @param base SDRAM controller peripheral base address. |
AnnaBridge | 145:64910690c574 | 227 | * @param block The block selection. |
AnnaBridge | 145:64910690c574 | 228 | * @param command The SDRAM command, see "sdramc_command_t". |
AnnaBridge | 145:64910690c574 | 229 | * kSDRAMC_ImrsCommand - Initialize MRS command \n |
AnnaBridge | 145:64910690c574 | 230 | * kSDRAMC_PrechargeCommand - Initialize precharge command \n |
AnnaBridge | 145:64910690c574 | 231 | * kSDRAMC_SelfrefreshEnterCommand - Enter self-refresh command \n |
AnnaBridge | 145:64910690c574 | 232 | * kSDRAMC_SelfrefreshExitCommand - Exit self-refresh command \n |
AnnaBridge | 145:64910690c574 | 233 | * kSDRAMC_AutoRefreshEnableCommand - Enable auto refresh command \n |
AnnaBridge | 145:64910690c574 | 234 | * kSDRAMC_AutoRefreshDisableCommand - Disable auto refresh command |
AnnaBridge | 145:64910690c574 | 235 | */ |
AnnaBridge | 145:64910690c574 | 236 | void SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command); |
AnnaBridge | 145:64910690c574 | 237 | |
AnnaBridge | 145:64910690c574 | 238 | /*! |
AnnaBridge | 145:64910690c574 | 239 | * @brief Enables/disables the write protection. |
AnnaBridge | 145:64910690c574 | 240 | * |
AnnaBridge | 145:64910690c574 | 241 | * @param base SDRAM peripheral base address. |
AnnaBridge | 145:64910690c574 | 242 | * @param block The block which is selected. |
AnnaBridge | 145:64910690c574 | 243 | * @param enable True enable write protection, false disable write protection. |
AnnaBridge | 145:64910690c574 | 244 | */ |
AnnaBridge | 145:64910690c574 | 245 | static inline void SDRAMC_EnableWriteProtect(SDRAM_Type *base, sdramc_block_selection_t block, bool enable) |
AnnaBridge | 145:64910690c574 | 246 | { |
AnnaBridge | 145:64910690c574 | 247 | if (enable) |
AnnaBridge | 145:64910690c574 | 248 | { |
AnnaBridge | 145:64910690c574 | 249 | base->BLOCK[block].CM |= SDRAM_CM_WP_MASK; |
AnnaBridge | 145:64910690c574 | 250 | } |
AnnaBridge | 145:64910690c574 | 251 | else |
AnnaBridge | 145:64910690c574 | 252 | { |
AnnaBridge | 145:64910690c574 | 253 | base->BLOCK[block].CM &= ~SDRAM_CM_WP_MASK; |
AnnaBridge | 145:64910690c574 | 254 | } |
AnnaBridge | 145:64910690c574 | 255 | } |
AnnaBridge | 145:64910690c574 | 256 | |
AnnaBridge | 145:64910690c574 | 257 | /*! |
AnnaBridge | 145:64910690c574 | 258 | * @brief Enables/disables the valid operation. |
AnnaBridge | 145:64910690c574 | 259 | * |
AnnaBridge | 145:64910690c574 | 260 | * @param base SDRAM peripheral base address. |
AnnaBridge | 145:64910690c574 | 261 | * @param block The block which is selected. |
AnnaBridge | 145:64910690c574 | 262 | * @param enable True enable the valid operation; false disable the valid operation. |
AnnaBridge | 145:64910690c574 | 263 | */ |
AnnaBridge | 145:64910690c574 | 264 | static inline void SDRAMC_EnableOperateValid(SDRAM_Type *base, sdramc_block_selection_t block, bool enable) |
AnnaBridge | 145:64910690c574 | 265 | { |
AnnaBridge | 145:64910690c574 | 266 | if (enable) |
AnnaBridge | 145:64910690c574 | 267 | { |
AnnaBridge | 145:64910690c574 | 268 | base->BLOCK[block].CM |= SDRAM_CM_V_MASK; |
AnnaBridge | 145:64910690c574 | 269 | } |
AnnaBridge | 145:64910690c574 | 270 | else |
AnnaBridge | 145:64910690c574 | 271 | { |
AnnaBridge | 145:64910690c574 | 272 | base->BLOCK[block].CM &= ~SDRAM_CM_V_MASK; |
AnnaBridge | 145:64910690c574 | 273 | } |
AnnaBridge | 145:64910690c574 | 274 | } |
AnnaBridge | 145:64910690c574 | 275 | |
AnnaBridge | 145:64910690c574 | 276 | /* @} */ |
AnnaBridge | 145:64910690c574 | 277 | |
AnnaBridge | 145:64910690c574 | 278 | #if defined(__cplusplus) |
AnnaBridge | 145:64910690c574 | 279 | } |
AnnaBridge | 145:64910690c574 | 280 | #endif |
AnnaBridge | 145:64910690c574 | 281 | |
AnnaBridge | 145:64910690c574 | 282 | /*! @}*/ |
AnnaBridge | 145:64910690c574 | 283 | |
AnnaBridge | 145:64910690c574 | 284 | #endif /* _FSL_SDRAMC_H_*/ |