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TARGET_GR_LYCHEE/TOOLCHAIN_ARM_STD/vdc5_iodefine.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_GR_LYCHEE/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/iodefines/vdc5_iodefine.h@161:aa5281ff4a02
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 161:aa5281ff4a02 | 1 | /******************************************************************************* |
| AnnaBridge | 161:aa5281ff4a02 | 2 | * DISCLAIMER |
| AnnaBridge | 161:aa5281ff4a02 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| AnnaBridge | 161:aa5281ff4a02 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| AnnaBridge | 161:aa5281ff4a02 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| AnnaBridge | 161:aa5281ff4a02 | 6 | * all applicable laws, including copyright laws. |
| AnnaBridge | 161:aa5281ff4a02 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| AnnaBridge | 161:aa5281ff4a02 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| AnnaBridge | 161:aa5281ff4a02 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| AnnaBridge | 161:aa5281ff4a02 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| AnnaBridge | 161:aa5281ff4a02 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| AnnaBridge | 161:aa5281ff4a02 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| AnnaBridge | 161:aa5281ff4a02 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| AnnaBridge | 161:aa5281ff4a02 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| AnnaBridge | 161:aa5281ff4a02 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| AnnaBridge | 161:aa5281ff4a02 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| AnnaBridge | 161:aa5281ff4a02 | 17 | * and to discontinue the availability of this software. By using this software, |
| AnnaBridge | 161:aa5281ff4a02 | 18 | * you agree to the additional terms and conditions found by accessing the |
| AnnaBridge | 161:aa5281ff4a02 | 19 | * following link: |
| AnnaBridge | 161:aa5281ff4a02 | 20 | * http://www.renesas.com/disclaimer* |
| AnnaBridge | 161:aa5281ff4a02 | 21 | * Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved. |
| AnnaBridge | 161:aa5281ff4a02 | 22 | *******************************************************************************/ |
| AnnaBridge | 161:aa5281ff4a02 | 23 | /******************************************************************************* |
| AnnaBridge | 161:aa5281ff4a02 | 24 | * File Name : vdc5_iodefine.h |
| AnnaBridge | 161:aa5281ff4a02 | 25 | * $Rev: $ |
| AnnaBridge | 161:aa5281ff4a02 | 26 | * $Date:: $ |
| AnnaBridge | 161:aa5281ff4a02 | 27 | * Description : Definition of I/O Register for RZ/A1LU (V3.00l) |
| AnnaBridge | 161:aa5281ff4a02 | 28 | ******************************************************************************/ |
| AnnaBridge | 161:aa5281ff4a02 | 29 | #ifndef VDC5_IODEFINE_H |
| AnnaBridge | 161:aa5281ff4a02 | 30 | #define VDC5_IODEFINE_H |
| AnnaBridge | 161:aa5281ff4a02 | 31 | /* ->QAC 0639 : Over 127 members (C90) */ |
| AnnaBridge | 161:aa5281ff4a02 | 32 | /* ->QAC 0857 : Over 1024 #define (C90) */ |
| AnnaBridge | 161:aa5281ff4a02 | 33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 34 | /* ->SEC M1.10.1 : Not magic number */ |
| AnnaBridge | 161:aa5281ff4a02 | 35 | |
| AnnaBridge | 161:aa5281ff4a02 | 36 | #define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ |
| AnnaBridge | 161:aa5281ff4a02 | 37 | |
| AnnaBridge | 161:aa5281ff4a02 | 38 | |
| AnnaBridge | 161:aa5281ff4a02 | 39 | /* Start of channel array defines of VDC5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 40 | |
| AnnaBridge | 161:aa5281ff4a02 | 41 | /* Channel array defines of VDC5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 42 | /*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ |
| AnnaBridge | 161:aa5281ff4a02 | 43 | #define VDC5_COUNT (1) |
| AnnaBridge | 161:aa5281ff4a02 | 44 | #define VDC5_ADDRESS_LIST \ |
| AnnaBridge | 161:aa5281ff4a02 | 45 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| AnnaBridge | 161:aa5281ff4a02 | 46 | &VDC50 \ |
| AnnaBridge | 161:aa5281ff4a02 | 47 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 48 | |
| AnnaBridge | 161:aa5281ff4a02 | 49 | |
| AnnaBridge | 161:aa5281ff4a02 | 50 | |
| AnnaBridge | 161:aa5281ff4a02 | 51 | /* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */ |
| AnnaBridge | 161:aa5281ff4a02 | 52 | /*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ |
| AnnaBridge | 161:aa5281ff4a02 | 53 | #define VDC50_FROM_GR2_AB7_ARRAY_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 54 | #define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ |
| AnnaBridge | 161:aa5281ff4a02 | 55 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| AnnaBridge | 161:aa5281ff4a02 | 56 | { \ |
| AnnaBridge | 161:aa5281ff4a02 | 57 | &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 \ |
| AnnaBridge | 161:aa5281ff4a02 | 58 | } \ |
| AnnaBridge | 161:aa5281ff4a02 | 59 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 60 | #define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 61 | #define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 62 | |
| AnnaBridge | 161:aa5281ff4a02 | 63 | |
| AnnaBridge | 161:aa5281ff4a02 | 64 | |
| AnnaBridge | 161:aa5281ff4a02 | 65 | |
| AnnaBridge | 161:aa5281ff4a02 | 66 | /* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */ |
| AnnaBridge | 161:aa5281ff4a02 | 67 | /*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ |
| AnnaBridge | 161:aa5281ff4a02 | 68 | #define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 69 | #define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ |
| AnnaBridge | 161:aa5281ff4a02 | 70 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| AnnaBridge | 161:aa5281ff4a02 | 71 | { \ |
| AnnaBridge | 161:aa5281ff4a02 | 72 | &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE \ |
| AnnaBridge | 161:aa5281ff4a02 | 73 | } \ |
| AnnaBridge | 161:aa5281ff4a02 | 74 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 75 | #define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 76 | #define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 77 | |
| AnnaBridge | 161:aa5281ff4a02 | 78 | |
| AnnaBridge | 161:aa5281ff4a02 | 79 | |
| AnnaBridge | 161:aa5281ff4a02 | 80 | |
| AnnaBridge | 161:aa5281ff4a02 | 81 | /* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */ |
| AnnaBridge | 161:aa5281ff4a02 | 82 | /*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ |
| AnnaBridge | 161:aa5281ff4a02 | 83 | #define VDC50_FROM_GR0_AB7_ARRAY_COUNT (3) |
| AnnaBridge | 161:aa5281ff4a02 | 84 | #define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ |
| AnnaBridge | 161:aa5281ff4a02 | 85 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| AnnaBridge | 161:aa5281ff4a02 | 86 | { \ |
| AnnaBridge | 161:aa5281ff4a02 | 87 | &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 \ |
| AnnaBridge | 161:aa5281ff4a02 | 88 | } \ |
| AnnaBridge | 161:aa5281ff4a02 | 89 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 90 | #define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 91 | #define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 92 | #define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 93 | |
| AnnaBridge | 161:aa5281ff4a02 | 94 | |
| AnnaBridge | 161:aa5281ff4a02 | 95 | |
| AnnaBridge | 161:aa5281ff4a02 | 96 | |
| AnnaBridge | 161:aa5281ff4a02 | 97 | /* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */ |
| AnnaBridge | 161:aa5281ff4a02 | 98 | /*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ |
| AnnaBridge | 161:aa5281ff4a02 | 99 | #define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT (3) |
| AnnaBridge | 161:aa5281ff4a02 | 100 | #define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ |
| AnnaBridge | 161:aa5281ff4a02 | 101 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| AnnaBridge | 161:aa5281ff4a02 | 102 | { \ |
| AnnaBridge | 161:aa5281ff4a02 | 103 | &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE \ |
| AnnaBridge | 161:aa5281ff4a02 | 104 | } \ |
| AnnaBridge | 161:aa5281ff4a02 | 105 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 106 | #define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 107 | #define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 108 | #define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 109 | |
| AnnaBridge | 161:aa5281ff4a02 | 110 | |
| AnnaBridge | 161:aa5281ff4a02 | 111 | /* End of channel array defines of VDC5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 112 | |
| AnnaBridge | 161:aa5281ff4a02 | 113 | |
| AnnaBridge | 161:aa5281ff4a02 | 114 | #define VDC50INP_UPDATE (VDC50.INP_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 115 | #define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT) |
| AnnaBridge | 161:aa5281ff4a02 | 116 | #define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT) |
| AnnaBridge | 161:aa5281ff4a02 | 117 | #define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ) |
| AnnaBridge | 161:aa5281ff4a02 | 118 | #define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ) |
| AnnaBridge | 161:aa5281ff4a02 | 119 | #define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 120 | #define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0) |
| AnnaBridge | 161:aa5281ff4a02 | 121 | #define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1) |
| AnnaBridge | 161:aa5281ff4a02 | 122 | #define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE) |
| AnnaBridge | 161:aa5281ff4a02 | 123 | #define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0) |
| AnnaBridge | 161:aa5281ff4a02 | 124 | #define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1) |
| AnnaBridge | 161:aa5281ff4a02 | 125 | #define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0) |
| AnnaBridge | 161:aa5281ff4a02 | 126 | #define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1) |
| AnnaBridge | 161:aa5281ff4a02 | 127 | #define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0) |
| AnnaBridge | 161:aa5281ff4a02 | 128 | #define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1) |
| AnnaBridge | 161:aa5281ff4a02 | 129 | #define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 130 | #define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1) |
| AnnaBridge | 161:aa5281ff4a02 | 131 | #define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2) |
| AnnaBridge | 161:aa5281ff4a02 | 132 | #define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3) |
| AnnaBridge | 161:aa5281ff4a02 | 133 | #define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4) |
| AnnaBridge | 161:aa5281ff4a02 | 134 | #define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5) |
| AnnaBridge | 161:aa5281ff4a02 | 135 | #define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6) |
| AnnaBridge | 161:aa5281ff4a02 | 136 | #define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7) |
| AnnaBridge | 161:aa5281ff4a02 | 137 | #define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9) |
| AnnaBridge | 161:aa5281ff4a02 | 138 | #define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0) |
| AnnaBridge | 161:aa5281ff4a02 | 139 | #define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT) |
| AnnaBridge | 161:aa5281ff4a02 | 140 | #define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1) |
| AnnaBridge | 161:aa5281ff4a02 | 141 | #define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2) |
| AnnaBridge | 161:aa5281ff4a02 | 142 | #define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3) |
| AnnaBridge | 161:aa5281ff4a02 | 143 | #define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4) |
| AnnaBridge | 161:aa5281ff4a02 | 144 | #define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5) |
| AnnaBridge | 161:aa5281ff4a02 | 145 | #define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6) |
| AnnaBridge | 161:aa5281ff4a02 | 146 | #define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7) |
| AnnaBridge | 161:aa5281ff4a02 | 147 | #define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1) |
| AnnaBridge | 161:aa5281ff4a02 | 148 | #define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2) |
| AnnaBridge | 161:aa5281ff4a02 | 149 | #define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3) |
| AnnaBridge | 161:aa5281ff4a02 | 150 | #define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4) |
| AnnaBridge | 161:aa5281ff4a02 | 151 | #define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5) |
| AnnaBridge | 161:aa5281ff4a02 | 152 | #define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6) |
| AnnaBridge | 161:aa5281ff4a02 | 153 | #define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7) |
| AnnaBridge | 161:aa5281ff4a02 | 154 | #define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8) |
| AnnaBridge | 161:aa5281ff4a02 | 155 | #define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1) |
| AnnaBridge | 161:aa5281ff4a02 | 156 | #define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 157 | #define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1) |
| AnnaBridge | 161:aa5281ff4a02 | 158 | #define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2) |
| AnnaBridge | 161:aa5281ff4a02 | 159 | #define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3) |
| AnnaBridge | 161:aa5281ff4a02 | 160 | #define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4) |
| AnnaBridge | 161:aa5281ff4a02 | 161 | #define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5) |
| AnnaBridge | 161:aa5281ff4a02 | 162 | #define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6) |
| AnnaBridge | 161:aa5281ff4a02 | 163 | #define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7) |
| AnnaBridge | 161:aa5281ff4a02 | 164 | #define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8) |
| AnnaBridge | 161:aa5281ff4a02 | 165 | #define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9) |
| AnnaBridge | 161:aa5281ff4a02 | 166 | #define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10) |
| AnnaBridge | 161:aa5281ff4a02 | 167 | #define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11) |
| AnnaBridge | 161:aa5281ff4a02 | 168 | #define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1) |
| AnnaBridge | 161:aa5281ff4a02 | 169 | #define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0) |
| AnnaBridge | 161:aa5281ff4a02 | 170 | #define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1) |
| AnnaBridge | 161:aa5281ff4a02 | 171 | #define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2) |
| AnnaBridge | 161:aa5281ff4a02 | 172 | #define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3) |
| AnnaBridge | 161:aa5281ff4a02 | 173 | #define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD) |
| AnnaBridge | 161:aa5281ff4a02 | 174 | #define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT) |
| AnnaBridge | 161:aa5281ff4a02 | 175 | #define VDC50GR0_UPDATE (VDC50.GR0_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 176 | #define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD) |
| AnnaBridge | 161:aa5281ff4a02 | 177 | #define VDC50GR0_FLM1 (VDC50.GR0_FLM1) |
| AnnaBridge | 161:aa5281ff4a02 | 178 | #define VDC50GR0_FLM2 (VDC50.GR0_FLM2) |
| AnnaBridge | 161:aa5281ff4a02 | 179 | #define VDC50GR0_FLM3 (VDC50.GR0_FLM3) |
| AnnaBridge | 161:aa5281ff4a02 | 180 | #define VDC50GR0_FLM4 (VDC50.GR0_FLM4) |
| AnnaBridge | 161:aa5281ff4a02 | 181 | #define VDC50GR0_FLM5 (VDC50.GR0_FLM5) |
| AnnaBridge | 161:aa5281ff4a02 | 182 | #define VDC50GR0_FLM6 (VDC50.GR0_FLM6) |
| AnnaBridge | 161:aa5281ff4a02 | 183 | #define VDC50GR0_AB1 (VDC50.GR0_AB1) |
| AnnaBridge | 161:aa5281ff4a02 | 184 | #define VDC50GR0_AB2 (VDC50.GR0_AB2) |
| AnnaBridge | 161:aa5281ff4a02 | 185 | #define VDC50GR0_AB3 (VDC50.GR0_AB3) |
| AnnaBridge | 161:aa5281ff4a02 | 186 | #define VDC50GR0_AB7 (VDC50.GR0_AB7) |
| AnnaBridge | 161:aa5281ff4a02 | 187 | #define VDC50GR0_AB8 (VDC50.GR0_AB8) |
| AnnaBridge | 161:aa5281ff4a02 | 188 | #define VDC50GR0_AB9 (VDC50.GR0_AB9) |
| AnnaBridge | 161:aa5281ff4a02 | 189 | #define VDC50GR0_AB10 (VDC50.GR0_AB10) |
| AnnaBridge | 161:aa5281ff4a02 | 190 | #define VDC50GR0_AB11 (VDC50.GR0_AB11) |
| AnnaBridge | 161:aa5281ff4a02 | 191 | #define VDC50GR0_BASE (VDC50.GR0_BASE) |
| AnnaBridge | 161:aa5281ff4a02 | 192 | #define VDC50GR0_CLUT (VDC50.GR0_CLUT) |
| AnnaBridge | 161:aa5281ff4a02 | 193 | #define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 194 | #define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET) |
| AnnaBridge | 161:aa5281ff4a02 | 195 | #define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1) |
| AnnaBridge | 161:aa5281ff4a02 | 196 | #define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2) |
| AnnaBridge | 161:aa5281ff4a02 | 197 | #define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3) |
| AnnaBridge | 161:aa5281ff4a02 | 198 | #define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1) |
| AnnaBridge | 161:aa5281ff4a02 | 199 | #define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2) |
| AnnaBridge | 161:aa5281ff4a02 | 200 | #define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3) |
| AnnaBridge | 161:aa5281ff4a02 | 201 | #define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4) |
| AnnaBridge | 161:aa5281ff4a02 | 202 | #define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5) |
| AnnaBridge | 161:aa5281ff4a02 | 203 | #define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6) |
| AnnaBridge | 161:aa5281ff4a02 | 204 | #define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1) |
| AnnaBridge | 161:aa5281ff4a02 | 205 | #define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2) |
| AnnaBridge | 161:aa5281ff4a02 | 206 | #define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE) |
| AnnaBridge | 161:aa5281ff4a02 | 207 | #define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0) |
| AnnaBridge | 161:aa5281ff4a02 | 208 | #define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1) |
| AnnaBridge | 161:aa5281ff4a02 | 209 | #define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0) |
| AnnaBridge | 161:aa5281ff4a02 | 210 | #define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1) |
| AnnaBridge | 161:aa5281ff4a02 | 211 | #define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0) |
| AnnaBridge | 161:aa5281ff4a02 | 212 | #define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1) |
| AnnaBridge | 161:aa5281ff4a02 | 213 | #define VDC50GR2_UPDATE (VDC50.GR2_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 214 | #define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD) |
| AnnaBridge | 161:aa5281ff4a02 | 215 | #define VDC50GR2_FLM1 (VDC50.GR2_FLM1) |
| AnnaBridge | 161:aa5281ff4a02 | 216 | #define VDC50GR2_FLM2 (VDC50.GR2_FLM2) |
| AnnaBridge | 161:aa5281ff4a02 | 217 | #define VDC50GR2_FLM3 (VDC50.GR2_FLM3) |
| AnnaBridge | 161:aa5281ff4a02 | 218 | #define VDC50GR2_FLM4 (VDC50.GR2_FLM4) |
| AnnaBridge | 161:aa5281ff4a02 | 219 | #define VDC50GR2_FLM5 (VDC50.GR2_FLM5) |
| AnnaBridge | 161:aa5281ff4a02 | 220 | #define VDC50GR2_FLM6 (VDC50.GR2_FLM6) |
| AnnaBridge | 161:aa5281ff4a02 | 221 | #define VDC50GR2_AB1 (VDC50.GR2_AB1) |
| AnnaBridge | 161:aa5281ff4a02 | 222 | #define VDC50GR2_AB2 (VDC50.GR2_AB2) |
| AnnaBridge | 161:aa5281ff4a02 | 223 | #define VDC50GR2_AB3 (VDC50.GR2_AB3) |
| AnnaBridge | 161:aa5281ff4a02 | 224 | #define VDC50GR2_AB4 (VDC50.GR2_AB4) |
| AnnaBridge | 161:aa5281ff4a02 | 225 | #define VDC50GR2_AB5 (VDC50.GR2_AB5) |
| AnnaBridge | 161:aa5281ff4a02 | 226 | #define VDC50GR2_AB6 (VDC50.GR2_AB6) |
| AnnaBridge | 161:aa5281ff4a02 | 227 | #define VDC50GR2_AB7 (VDC50.GR2_AB7) |
| AnnaBridge | 161:aa5281ff4a02 | 228 | #define VDC50GR2_AB8 (VDC50.GR2_AB8) |
| AnnaBridge | 161:aa5281ff4a02 | 229 | #define VDC50GR2_AB9 (VDC50.GR2_AB9) |
| AnnaBridge | 161:aa5281ff4a02 | 230 | #define VDC50GR2_AB10 (VDC50.GR2_AB10) |
| AnnaBridge | 161:aa5281ff4a02 | 231 | #define VDC50GR2_AB11 (VDC50.GR2_AB11) |
| AnnaBridge | 161:aa5281ff4a02 | 232 | #define VDC50GR2_BASE (VDC50.GR2_BASE) |
| AnnaBridge | 161:aa5281ff4a02 | 233 | #define VDC50GR2_CLUT (VDC50.GR2_CLUT) |
| AnnaBridge | 161:aa5281ff4a02 | 234 | #define VDC50GR2_MON (VDC50.GR2_MON) |
| AnnaBridge | 161:aa5281ff4a02 | 235 | #define VDC50GR3_UPDATE (VDC50.GR3_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 236 | #define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD) |
| AnnaBridge | 161:aa5281ff4a02 | 237 | #define VDC50GR3_FLM1 (VDC50.GR3_FLM1) |
| AnnaBridge | 161:aa5281ff4a02 | 238 | #define VDC50GR3_FLM2 (VDC50.GR3_FLM2) |
| AnnaBridge | 161:aa5281ff4a02 | 239 | #define VDC50GR3_FLM3 (VDC50.GR3_FLM3) |
| AnnaBridge | 161:aa5281ff4a02 | 240 | #define VDC50GR3_FLM4 (VDC50.GR3_FLM4) |
| AnnaBridge | 161:aa5281ff4a02 | 241 | #define VDC50GR3_FLM5 (VDC50.GR3_FLM5) |
| AnnaBridge | 161:aa5281ff4a02 | 242 | #define VDC50GR3_FLM6 (VDC50.GR3_FLM6) |
| AnnaBridge | 161:aa5281ff4a02 | 243 | #define VDC50GR3_AB1 (VDC50.GR3_AB1) |
| AnnaBridge | 161:aa5281ff4a02 | 244 | #define VDC50GR3_AB2 (VDC50.GR3_AB2) |
| AnnaBridge | 161:aa5281ff4a02 | 245 | #define VDC50GR3_AB3 (VDC50.GR3_AB3) |
| AnnaBridge | 161:aa5281ff4a02 | 246 | #define VDC50GR3_AB4 (VDC50.GR3_AB4) |
| AnnaBridge | 161:aa5281ff4a02 | 247 | #define VDC50GR3_AB5 (VDC50.GR3_AB5) |
| AnnaBridge | 161:aa5281ff4a02 | 248 | #define VDC50GR3_AB6 (VDC50.GR3_AB6) |
| AnnaBridge | 161:aa5281ff4a02 | 249 | #define VDC50GR3_AB7 (VDC50.GR3_AB7) |
| AnnaBridge | 161:aa5281ff4a02 | 250 | #define VDC50GR3_AB8 (VDC50.GR3_AB8) |
| AnnaBridge | 161:aa5281ff4a02 | 251 | #define VDC50GR3_AB9 (VDC50.GR3_AB9) |
| AnnaBridge | 161:aa5281ff4a02 | 252 | #define VDC50GR3_AB10 (VDC50.GR3_AB10) |
| AnnaBridge | 161:aa5281ff4a02 | 253 | #define VDC50GR3_AB11 (VDC50.GR3_AB11) |
| AnnaBridge | 161:aa5281ff4a02 | 254 | #define VDC50GR3_BASE (VDC50.GR3_BASE) |
| AnnaBridge | 161:aa5281ff4a02 | 255 | #define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT) |
| AnnaBridge | 161:aa5281ff4a02 | 256 | #define VDC50GR3_MON (VDC50.GR3_MON) |
| AnnaBridge | 161:aa5281ff4a02 | 257 | #define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 258 | #define VDC50GAM_SW (VDC50.GAM_SW) |
| AnnaBridge | 161:aa5281ff4a02 | 259 | #define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1) |
| AnnaBridge | 161:aa5281ff4a02 | 260 | #define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2) |
| AnnaBridge | 161:aa5281ff4a02 | 261 | #define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3) |
| AnnaBridge | 161:aa5281ff4a02 | 262 | #define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4) |
| AnnaBridge | 161:aa5281ff4a02 | 263 | #define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5) |
| AnnaBridge | 161:aa5281ff4a02 | 264 | #define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6) |
| AnnaBridge | 161:aa5281ff4a02 | 265 | #define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7) |
| AnnaBridge | 161:aa5281ff4a02 | 266 | #define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8) |
| AnnaBridge | 161:aa5281ff4a02 | 267 | #define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9) |
| AnnaBridge | 161:aa5281ff4a02 | 268 | #define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10) |
| AnnaBridge | 161:aa5281ff4a02 | 269 | #define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11) |
| AnnaBridge | 161:aa5281ff4a02 | 270 | #define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12) |
| AnnaBridge | 161:aa5281ff4a02 | 271 | #define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13) |
| AnnaBridge | 161:aa5281ff4a02 | 272 | #define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14) |
| AnnaBridge | 161:aa5281ff4a02 | 273 | #define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15) |
| AnnaBridge | 161:aa5281ff4a02 | 274 | #define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16) |
| AnnaBridge | 161:aa5281ff4a02 | 275 | #define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1) |
| AnnaBridge | 161:aa5281ff4a02 | 276 | #define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2) |
| AnnaBridge | 161:aa5281ff4a02 | 277 | #define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3) |
| AnnaBridge | 161:aa5281ff4a02 | 278 | #define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4) |
| AnnaBridge | 161:aa5281ff4a02 | 279 | #define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5) |
| AnnaBridge | 161:aa5281ff4a02 | 280 | #define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6) |
| AnnaBridge | 161:aa5281ff4a02 | 281 | #define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7) |
| AnnaBridge | 161:aa5281ff4a02 | 282 | #define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8) |
| AnnaBridge | 161:aa5281ff4a02 | 283 | #define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 284 | #define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1) |
| AnnaBridge | 161:aa5281ff4a02 | 285 | #define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2) |
| AnnaBridge | 161:aa5281ff4a02 | 286 | #define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3) |
| AnnaBridge | 161:aa5281ff4a02 | 287 | #define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4) |
| AnnaBridge | 161:aa5281ff4a02 | 288 | #define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5) |
| AnnaBridge | 161:aa5281ff4a02 | 289 | #define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6) |
| AnnaBridge | 161:aa5281ff4a02 | 290 | #define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7) |
| AnnaBridge | 161:aa5281ff4a02 | 291 | #define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8) |
| AnnaBridge | 161:aa5281ff4a02 | 292 | #define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9) |
| AnnaBridge | 161:aa5281ff4a02 | 293 | #define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10) |
| AnnaBridge | 161:aa5281ff4a02 | 294 | #define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11) |
| AnnaBridge | 161:aa5281ff4a02 | 295 | #define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12) |
| AnnaBridge | 161:aa5281ff4a02 | 296 | #define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13) |
| AnnaBridge | 161:aa5281ff4a02 | 297 | #define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14) |
| AnnaBridge | 161:aa5281ff4a02 | 298 | #define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15) |
| AnnaBridge | 161:aa5281ff4a02 | 299 | #define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16) |
| AnnaBridge | 161:aa5281ff4a02 | 300 | #define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1) |
| AnnaBridge | 161:aa5281ff4a02 | 301 | #define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2) |
| AnnaBridge | 161:aa5281ff4a02 | 302 | #define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3) |
| AnnaBridge | 161:aa5281ff4a02 | 303 | #define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4) |
| AnnaBridge | 161:aa5281ff4a02 | 304 | #define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5) |
| AnnaBridge | 161:aa5281ff4a02 | 305 | #define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6) |
| AnnaBridge | 161:aa5281ff4a02 | 306 | #define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7) |
| AnnaBridge | 161:aa5281ff4a02 | 307 | #define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8) |
| AnnaBridge | 161:aa5281ff4a02 | 308 | #define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 309 | #define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1) |
| AnnaBridge | 161:aa5281ff4a02 | 310 | #define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2) |
| AnnaBridge | 161:aa5281ff4a02 | 311 | #define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3) |
| AnnaBridge | 161:aa5281ff4a02 | 312 | #define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4) |
| AnnaBridge | 161:aa5281ff4a02 | 313 | #define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5) |
| AnnaBridge | 161:aa5281ff4a02 | 314 | #define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6) |
| AnnaBridge | 161:aa5281ff4a02 | 315 | #define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7) |
| AnnaBridge | 161:aa5281ff4a02 | 316 | #define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8) |
| AnnaBridge | 161:aa5281ff4a02 | 317 | #define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9) |
| AnnaBridge | 161:aa5281ff4a02 | 318 | #define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10) |
| AnnaBridge | 161:aa5281ff4a02 | 319 | #define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11) |
| AnnaBridge | 161:aa5281ff4a02 | 320 | #define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12) |
| AnnaBridge | 161:aa5281ff4a02 | 321 | #define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13) |
| AnnaBridge | 161:aa5281ff4a02 | 322 | #define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14) |
| AnnaBridge | 161:aa5281ff4a02 | 323 | #define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15) |
| AnnaBridge | 161:aa5281ff4a02 | 324 | #define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16) |
| AnnaBridge | 161:aa5281ff4a02 | 325 | #define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1) |
| AnnaBridge | 161:aa5281ff4a02 | 326 | #define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2) |
| AnnaBridge | 161:aa5281ff4a02 | 327 | #define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3) |
| AnnaBridge | 161:aa5281ff4a02 | 328 | #define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4) |
| AnnaBridge | 161:aa5281ff4a02 | 329 | #define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5) |
| AnnaBridge | 161:aa5281ff4a02 | 330 | #define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6) |
| AnnaBridge | 161:aa5281ff4a02 | 331 | #define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7) |
| AnnaBridge | 161:aa5281ff4a02 | 332 | #define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8) |
| AnnaBridge | 161:aa5281ff4a02 | 333 | #define VDC50TCON_UPDATE (VDC50.TCON_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 334 | #define VDC50TCON_TIM (VDC50.TCON_TIM) |
| AnnaBridge | 161:aa5281ff4a02 | 335 | #define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1) |
| AnnaBridge | 161:aa5281ff4a02 | 336 | #define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2) |
| AnnaBridge | 161:aa5281ff4a02 | 337 | #define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1) |
| AnnaBridge | 161:aa5281ff4a02 | 338 | #define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2) |
| AnnaBridge | 161:aa5281ff4a02 | 339 | #define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1) |
| AnnaBridge | 161:aa5281ff4a02 | 340 | #define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2) |
| AnnaBridge | 161:aa5281ff4a02 | 341 | #define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1) |
| AnnaBridge | 161:aa5281ff4a02 | 342 | #define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2) |
| AnnaBridge | 161:aa5281ff4a02 | 343 | #define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1) |
| AnnaBridge | 161:aa5281ff4a02 | 344 | #define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2) |
| AnnaBridge | 161:aa5281ff4a02 | 345 | #define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1) |
| AnnaBridge | 161:aa5281ff4a02 | 346 | #define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2) |
| AnnaBridge | 161:aa5281ff4a02 | 347 | #define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1) |
| AnnaBridge | 161:aa5281ff4a02 | 348 | #define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2) |
| AnnaBridge | 161:aa5281ff4a02 | 349 | #define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE) |
| AnnaBridge | 161:aa5281ff4a02 | 350 | #define VDC50OUT_UPDATE (VDC50.OUT_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 351 | #define VDC50OUT_SET (VDC50.OUT_SET) |
| AnnaBridge | 161:aa5281ff4a02 | 352 | #define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1) |
| AnnaBridge | 161:aa5281ff4a02 | 353 | #define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2) |
| AnnaBridge | 161:aa5281ff4a02 | 354 | #define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST) |
| AnnaBridge | 161:aa5281ff4a02 | 355 | #define VDC50OUT_PDTHA (VDC50.OUT_PDTHA) |
| AnnaBridge | 161:aa5281ff4a02 | 356 | #define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE) |
| AnnaBridge | 161:aa5281ff4a02 | 357 | #define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1) |
| AnnaBridge | 161:aa5281ff4a02 | 358 | #define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2) |
| AnnaBridge | 161:aa5281ff4a02 | 359 | #define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4) |
| AnnaBridge | 161:aa5281ff4a02 | 360 | #define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5) |
| AnnaBridge | 161:aa5281ff4a02 | 361 | #define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK) |
| AnnaBridge | 161:aa5281ff4a02 | 362 | #define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT) |
| AnnaBridge | 161:aa5281ff4a02 | 363 | #define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE) |
| AnnaBridge | 161:aa5281ff4a02 | 364 | #define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1) |
| AnnaBridge | 161:aa5281ff4a02 | 365 | |
| AnnaBridge | 161:aa5281ff4a02 | 366 | #define VDC5_IMGCNT_NR_CNT0_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 367 | #define VDC5_SC0_SCL0_FRC1_COUNT (7) |
| AnnaBridge | 161:aa5281ff4a02 | 368 | #define VDC5_SC0_SCL0_DS1_COUNT (7) |
| AnnaBridge | 161:aa5281ff4a02 | 369 | #define VDC5_SC0_SCL0_US1_COUNT (8) |
| AnnaBridge | 161:aa5281ff4a02 | 370 | #define VDC5_SC0_SCL1_WR1_COUNT (4) |
| AnnaBridge | 161:aa5281ff4a02 | 371 | #define VDC5_SC0_SCL1_PBUF0_COUNT (4) |
| AnnaBridge | 161:aa5281ff4a02 | 372 | #define VDC5_GR0_FLM1_COUNT (6) |
| AnnaBridge | 161:aa5281ff4a02 | 373 | #define VDC5_GR0_AB1_COUNT (3) |
| AnnaBridge | 161:aa5281ff4a02 | 374 | #define VDC5_ADJ0_ENH_TIM1_COUNT (3) |
| AnnaBridge | 161:aa5281ff4a02 | 375 | #define VDC5_ADJ0_ENH_SHP1_COUNT (6) |
| AnnaBridge | 161:aa5281ff4a02 | 376 | #define VDC5_ADJ0_ENH_LTI1_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 377 | #define VDC5_GR2_FLM1_COUNT (6) |
| AnnaBridge | 161:aa5281ff4a02 | 378 | #define VDC5_GR2_AB1_COUNT (3) |
| AnnaBridge | 161:aa5281ff4a02 | 379 | #define VDC5_GR3_FLM1_COUNT (6) |
| AnnaBridge | 161:aa5281ff4a02 | 380 | #define VDC5_GR3_AB1_COUNT (3) |
| AnnaBridge | 161:aa5281ff4a02 | 381 | #define VDC5_GAM_G_LUT1_COUNT (16) |
| AnnaBridge | 161:aa5281ff4a02 | 382 | #define VDC5_GAM_G_AREA1_COUNT (8) |
| AnnaBridge | 161:aa5281ff4a02 | 383 | #define VDC5_GAM_B_LUT1_COUNT (16) |
| AnnaBridge | 161:aa5281ff4a02 | 384 | #define VDC5_GAM_B_AREA1_COUNT (8) |
| AnnaBridge | 161:aa5281ff4a02 | 385 | #define VDC5_GAM_R_LUT1_COUNT (16) |
| AnnaBridge | 161:aa5281ff4a02 | 386 | #define VDC5_GAM_R_AREA1_COUNT (8) |
| AnnaBridge | 161:aa5281ff4a02 | 387 | #define VDC5_TCON_TIM_STVA1_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 388 | #define VDC5_TCON_TIM_STVB1_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 389 | #define VDC5_TCON_TIM_STH1_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 390 | #define VDC5_TCON_TIM_STB1_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 391 | #define VDC5_TCON_TIM_CPV1_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 392 | #define VDC5_TCON_TIM_POLA1_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 393 | #define VDC5_TCON_TIM_POLB1_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 394 | #define VDC5_OUT_BRIGHT1_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 395 | #define VDC5_SYSCNT_INT1_COUNT (2) |
| AnnaBridge | 161:aa5281ff4a02 | 396 | #define VDC5_GR_VIN_AB1_COUNT (1) |
| AnnaBridge | 161:aa5281ff4a02 | 397 | |
| AnnaBridge | 161:aa5281ff4a02 | 398 | |
| AnnaBridge | 161:aa5281ff4a02 | 399 | typedef struct st_vdc5 |
| AnnaBridge | 161:aa5281ff4a02 | 400 | { |
| AnnaBridge | 161:aa5281ff4a02 | 401 | /* VDC5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 402 | volatile uint32_t INP_UPDATE; /* INP_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 403 | volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */ |
| AnnaBridge | 161:aa5281ff4a02 | 404 | volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */ |
| AnnaBridge | 161:aa5281ff4a02 | 405 | volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */ |
| AnnaBridge | 161:aa5281ff4a02 | 406 | volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */ |
| AnnaBridge | 161:aa5281ff4a02 | 407 | volatile uint8_t dummy1[108]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 408 | volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 409 | |
| AnnaBridge | 161:aa5281ff4a02 | 410 | /* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */ |
| AnnaBridge | 161:aa5281ff4a02 | 411 | volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */ |
| AnnaBridge | 161:aa5281ff4a02 | 412 | volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 413 | volatile uint8_t dummy2[20]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 414 | volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */ |
| AnnaBridge | 161:aa5281ff4a02 | 415 | volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */ |
| AnnaBridge | 161:aa5281ff4a02 | 416 | volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 417 | volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */ |
| AnnaBridge | 161:aa5281ff4a02 | 418 | volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 419 | volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */ |
| AnnaBridge | 161:aa5281ff4a02 | 420 | volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 421 | volatile uint8_t dummy3[68]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 422 | volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 423 | |
| AnnaBridge | 161:aa5281ff4a02 | 424 | /* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */ |
| AnnaBridge | 161:aa5281ff4a02 | 425 | volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 426 | volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 427 | volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 428 | volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 429 | volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 430 | volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 431 | volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 432 | volatile uint8_t dummy4[4]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 433 | volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ |
| AnnaBridge | 161:aa5281ff4a02 | 434 | volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ |
| AnnaBridge | 161:aa5281ff4a02 | 435 | volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ |
| AnnaBridge | 161:aa5281ff4a02 | 436 | |
| AnnaBridge | 161:aa5281ff4a02 | 437 | /* #define VDC5_SC0_SCL0_DS1_COUNT (7) */ |
| AnnaBridge | 161:aa5281ff4a02 | 438 | volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 439 | volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 440 | volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 441 | volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 442 | volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 443 | volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 444 | volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 445 | |
| AnnaBridge | 161:aa5281ff4a02 | 446 | /* #define VDC5_SC0_SCL0_US1_COUNT (8) */ |
| AnnaBridge | 161:aa5281ff4a02 | 447 | volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 448 | volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 449 | volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 450 | volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 451 | volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 452 | volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 453 | volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 454 | volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 455 | volatile uint8_t dummy5[4]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 456 | volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 457 | volatile uint8_t dummy6[16]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 458 | volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 459 | volatile uint8_t dummy7[4]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 460 | |
| AnnaBridge | 161:aa5281ff4a02 | 461 | /* #define VDC5_SC0_SCL1_WR1_COUNT (4) */ |
| AnnaBridge | 161:aa5281ff4a02 | 462 | volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 463 | volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 464 | volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 465 | volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 466 | volatile uint8_t dummy8[4]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 467 | volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 468 | volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 469 | volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 470 | volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 471 | volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ |
| AnnaBridge | 161:aa5281ff4a02 | 472 | volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ |
| AnnaBridge | 161:aa5281ff4a02 | 473 | volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */ |
| AnnaBridge | 161:aa5281ff4a02 | 474 | volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 475 | |
| AnnaBridge | 161:aa5281ff4a02 | 476 | /* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */ |
| AnnaBridge | 161:aa5281ff4a02 | 477 | volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ |
| AnnaBridge | 161:aa5281ff4a02 | 478 | volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 479 | volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 480 | volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 481 | volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ |
| AnnaBridge | 161:aa5281ff4a02 | 482 | volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ |
| AnnaBridge | 161:aa5281ff4a02 | 483 | volatile uint8_t dummy9[44]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 484 | |
| AnnaBridge | 161:aa5281ff4a02 | 485 | /* start of struct st_vdc5_from_gr0_update */ |
| AnnaBridge | 161:aa5281ff4a02 | 486 | volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 487 | volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ |
| AnnaBridge | 161:aa5281ff4a02 | 488 | |
| AnnaBridge | 161:aa5281ff4a02 | 489 | /* #define VDC5_GR0_FLM1_COUNT (6) */ |
| AnnaBridge | 161:aa5281ff4a02 | 490 | volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 491 | volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 492 | volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 493 | volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 494 | volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 495 | volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 496 | |
| AnnaBridge | 161:aa5281ff4a02 | 497 | /* #define VDC5_GR0_AB1_COUNT (3) */ |
| AnnaBridge | 161:aa5281ff4a02 | 498 | volatile uint32_t GR0_AB1; /* GR0_AB1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 499 | volatile uint32_t GR0_AB2; /* GR0_AB2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 500 | volatile uint32_t GR0_AB3; /* GR0_AB3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 501 | |
| AnnaBridge | 161:aa5281ff4a02 | 502 | /* end of struct st_vdc5_from_gr0_update */ |
| AnnaBridge | 161:aa5281ff4a02 | 503 | volatile uint8_t dummy10[12]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 504 | |
| AnnaBridge | 161:aa5281ff4a02 | 505 | /* start of struct st_vdc5_from_gr0_ab7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 506 | volatile uint32_t GR0_AB7; /* GR0_AB7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 507 | volatile uint32_t GR0_AB8; /* GR0_AB8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 508 | volatile uint32_t GR0_AB9; /* GR0_AB9 */ |
| AnnaBridge | 161:aa5281ff4a02 | 509 | volatile uint32_t GR0_AB10; /* GR0_AB10 */ |
| AnnaBridge | 161:aa5281ff4a02 | 510 | volatile uint32_t GR0_AB11; /* GR0_AB11 */ |
| AnnaBridge | 161:aa5281ff4a02 | 511 | volatile uint32_t GR0_BASE; /* GR0_BASE */ |
| AnnaBridge | 161:aa5281ff4a02 | 512 | |
| AnnaBridge | 161:aa5281ff4a02 | 513 | /* end of struct st_vdc5_from_gr0_ab7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 514 | volatile uint32_t GR0_CLUT; /* GR0_CLUT */ |
| AnnaBridge | 161:aa5281ff4a02 | 515 | volatile uint8_t dummy11[44]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 516 | volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 517 | volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ |
| AnnaBridge | 161:aa5281ff4a02 | 518 | |
| AnnaBridge | 161:aa5281ff4a02 | 519 | /* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */ |
| AnnaBridge | 161:aa5281ff4a02 | 520 | volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 521 | volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 522 | volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 523 | |
| AnnaBridge | 161:aa5281ff4a02 | 524 | /* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */ |
| AnnaBridge | 161:aa5281ff4a02 | 525 | volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 526 | volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 527 | volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 528 | volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 529 | volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 530 | volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 531 | |
| AnnaBridge | 161:aa5281ff4a02 | 532 | /* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */ |
| AnnaBridge | 161:aa5281ff4a02 | 533 | volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 534 | volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 535 | volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ |
| AnnaBridge | 161:aa5281ff4a02 | 536 | volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */ |
| AnnaBridge | 161:aa5281ff4a02 | 537 | volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 538 | volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */ |
| AnnaBridge | 161:aa5281ff4a02 | 539 | volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 540 | volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ |
| AnnaBridge | 161:aa5281ff4a02 | 541 | volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 542 | volatile uint8_t dummy12[48]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 543 | |
| AnnaBridge | 161:aa5281ff4a02 | 544 | /* start of struct st_vdc5_from_gr0_update */ |
| AnnaBridge | 161:aa5281ff4a02 | 545 | |
| AnnaBridge | 161:aa5281ff4a02 | 546 | /* start of struct st_vdc5_from_gr0_update */ |
| AnnaBridge | 161:aa5281ff4a02 | 547 | volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 548 | volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */ |
| AnnaBridge | 161:aa5281ff4a02 | 549 | |
| AnnaBridge | 161:aa5281ff4a02 | 550 | /* #define VDC5_GR2_FLM1_COUNT (6) */ |
| AnnaBridge | 161:aa5281ff4a02 | 551 | volatile uint32_t GR2_FLM1; /* GR2_FLM1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 552 | volatile uint32_t GR2_FLM2; /* GR2_FLM2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 553 | volatile uint32_t GR2_FLM3; /* GR2_FLM3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 554 | volatile uint32_t GR2_FLM4; /* GR2_FLM4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 555 | volatile uint32_t GR2_FLM5; /* GR2_FLM5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 556 | volatile uint32_t GR2_FLM6; /* GR2_FLM6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 557 | |
| AnnaBridge | 161:aa5281ff4a02 | 558 | /* #define VDC5_GR2_AB1_COUNT (3) */ |
| AnnaBridge | 161:aa5281ff4a02 | 559 | volatile uint32_t GR2_AB1; /* GR2_AB1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 560 | volatile uint32_t GR2_AB2; /* GR2_AB2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 561 | volatile uint32_t GR2_AB3; /* GR2_AB3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 562 | |
| AnnaBridge | 161:aa5281ff4a02 | 563 | /* end of struct st_vdc5_from_gr0_update */ |
| AnnaBridge | 161:aa5281ff4a02 | 564 | |
| AnnaBridge | 161:aa5281ff4a02 | 565 | /* end of struct st_vdc5_from_gr0_update */ |
| AnnaBridge | 161:aa5281ff4a02 | 566 | volatile uint32_t GR2_AB4; /* GR2_AB4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 567 | volatile uint32_t GR2_AB5; /* GR2_AB5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 568 | volatile uint32_t GR2_AB6; /* GR2_AB6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 569 | |
| AnnaBridge | 161:aa5281ff4a02 | 570 | /* start of struct st_vdc5_from_gr0_ab7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 571 | |
| AnnaBridge | 161:aa5281ff4a02 | 572 | /* start of struct st_vdc5_from_gr0_ab7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 573 | volatile uint32_t GR2_AB7; /* GR2_AB7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 574 | volatile uint32_t GR2_AB8; /* GR2_AB8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 575 | volatile uint32_t GR2_AB9; /* GR2_AB9 */ |
| AnnaBridge | 161:aa5281ff4a02 | 576 | volatile uint32_t GR2_AB10; /* GR2_AB10 */ |
| AnnaBridge | 161:aa5281ff4a02 | 577 | volatile uint32_t GR2_AB11; /* GR2_AB11 */ |
| AnnaBridge | 161:aa5281ff4a02 | 578 | volatile uint32_t GR2_BASE; /* GR2_BASE */ |
| AnnaBridge | 161:aa5281ff4a02 | 579 | |
| AnnaBridge | 161:aa5281ff4a02 | 580 | /* end of struct st_vdc5_from_gr0_ab7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 581 | |
| AnnaBridge | 161:aa5281ff4a02 | 582 | /* end of struct st_vdc5_from_gr0_ab7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 583 | volatile uint32_t GR2_CLUT; /* GR2_CLUT */ |
| AnnaBridge | 161:aa5281ff4a02 | 584 | volatile uint32_t GR2_MON; /* GR2_MON */ |
| AnnaBridge | 161:aa5281ff4a02 | 585 | volatile uint8_t dummy13[40]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 586 | |
| AnnaBridge | 161:aa5281ff4a02 | 587 | /* start of struct st_vdc5_from_gr0_update */ |
| AnnaBridge | 161:aa5281ff4a02 | 588 | |
| AnnaBridge | 161:aa5281ff4a02 | 589 | /* start of struct st_vdc5_from_gr0_update */ |
| AnnaBridge | 161:aa5281ff4a02 | 590 | volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 591 | volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */ |
| AnnaBridge | 161:aa5281ff4a02 | 592 | |
| AnnaBridge | 161:aa5281ff4a02 | 593 | /* #define VDC5_GR3_FLM1_COUNT (6) */ |
| AnnaBridge | 161:aa5281ff4a02 | 594 | volatile uint32_t GR3_FLM1; /* GR3_FLM1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 595 | volatile uint32_t GR3_FLM2; /* GR3_FLM2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 596 | volatile uint32_t GR3_FLM3; /* GR3_FLM3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 597 | volatile uint32_t GR3_FLM4; /* GR3_FLM4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 598 | volatile uint32_t GR3_FLM5; /* GR3_FLM5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 599 | volatile uint32_t GR3_FLM6; /* GR3_FLM6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 600 | |
| AnnaBridge | 161:aa5281ff4a02 | 601 | /* #define VDC5_GR3_AB1_COUNT (3) */ |
| AnnaBridge | 161:aa5281ff4a02 | 602 | volatile uint32_t GR3_AB1; /* GR3_AB1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 603 | volatile uint32_t GR3_AB2; /* GR3_AB2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 604 | volatile uint32_t GR3_AB3; /* GR3_AB3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 605 | |
| AnnaBridge | 161:aa5281ff4a02 | 606 | /* end of struct st_vdc5_from_gr0_update */ |
| AnnaBridge | 161:aa5281ff4a02 | 607 | |
| AnnaBridge | 161:aa5281ff4a02 | 608 | /* end of struct st_vdc5_from_gr0_update */ |
| AnnaBridge | 161:aa5281ff4a02 | 609 | volatile uint32_t GR3_AB4; /* GR3_AB4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 610 | volatile uint32_t GR3_AB5; /* GR3_AB5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 611 | volatile uint32_t GR3_AB6; /* GR3_AB6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 612 | |
| AnnaBridge | 161:aa5281ff4a02 | 613 | /* start of struct st_vdc5_from_gr0_ab7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 614 | |
| AnnaBridge | 161:aa5281ff4a02 | 615 | /* start of struct st_vdc5_from_gr0_ab7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 616 | volatile uint32_t GR3_AB7; /* GR3_AB7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 617 | volatile uint32_t GR3_AB8; /* GR3_AB8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 618 | volatile uint32_t GR3_AB9; /* GR3_AB9 */ |
| AnnaBridge | 161:aa5281ff4a02 | 619 | volatile uint32_t GR3_AB10; /* GR3_AB10 */ |
| AnnaBridge | 161:aa5281ff4a02 | 620 | volatile uint32_t GR3_AB11; /* GR3_AB11 */ |
| AnnaBridge | 161:aa5281ff4a02 | 621 | volatile uint32_t GR3_BASE; /* GR3_BASE */ |
| AnnaBridge | 161:aa5281ff4a02 | 622 | |
| AnnaBridge | 161:aa5281ff4a02 | 623 | /* end of struct st_vdc5_from_gr0_ab7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 624 | |
| AnnaBridge | 161:aa5281ff4a02 | 625 | /* end of struct st_vdc5_from_gr0_ab7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 626 | volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */ |
| AnnaBridge | 161:aa5281ff4a02 | 627 | volatile uint32_t GR3_MON; /* GR3_MON */ |
| AnnaBridge | 161:aa5281ff4a02 | 628 | volatile uint8_t dummy14[40]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 629 | volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 630 | volatile uint32_t GAM_SW; /* GAM_SW */ |
| AnnaBridge | 161:aa5281ff4a02 | 631 | |
| AnnaBridge | 161:aa5281ff4a02 | 632 | /* #define VDC5_GAM_G_LUT1_COUNT (16) */ |
| AnnaBridge | 161:aa5281ff4a02 | 633 | volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 634 | volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 635 | volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 636 | volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 637 | volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 638 | volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 639 | volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 640 | volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 641 | volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */ |
| AnnaBridge | 161:aa5281ff4a02 | 642 | volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */ |
| AnnaBridge | 161:aa5281ff4a02 | 643 | volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */ |
| AnnaBridge | 161:aa5281ff4a02 | 644 | volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */ |
| AnnaBridge | 161:aa5281ff4a02 | 645 | volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */ |
| AnnaBridge | 161:aa5281ff4a02 | 646 | volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */ |
| AnnaBridge | 161:aa5281ff4a02 | 647 | volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */ |
| AnnaBridge | 161:aa5281ff4a02 | 648 | volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */ |
| AnnaBridge | 161:aa5281ff4a02 | 649 | |
| AnnaBridge | 161:aa5281ff4a02 | 650 | /* #define VDC5_GAM_G_AREA1_COUNT (8) */ |
| AnnaBridge | 161:aa5281ff4a02 | 651 | volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 652 | volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 653 | volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 654 | volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 655 | volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 656 | volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 657 | volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 658 | volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 659 | volatile uint8_t dummy15[24]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 660 | volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 661 | volatile uint8_t dummy16[4]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 662 | |
| AnnaBridge | 161:aa5281ff4a02 | 663 | /* #define VDC5_GAM_B_LUT1_COUNT (16) */ |
| AnnaBridge | 161:aa5281ff4a02 | 664 | volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 665 | volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 666 | volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 667 | volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 668 | volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 669 | volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 670 | volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 671 | volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 672 | volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */ |
| AnnaBridge | 161:aa5281ff4a02 | 673 | volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */ |
| AnnaBridge | 161:aa5281ff4a02 | 674 | volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */ |
| AnnaBridge | 161:aa5281ff4a02 | 675 | volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */ |
| AnnaBridge | 161:aa5281ff4a02 | 676 | volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */ |
| AnnaBridge | 161:aa5281ff4a02 | 677 | volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */ |
| AnnaBridge | 161:aa5281ff4a02 | 678 | volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */ |
| AnnaBridge | 161:aa5281ff4a02 | 679 | volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */ |
| AnnaBridge | 161:aa5281ff4a02 | 680 | |
| AnnaBridge | 161:aa5281ff4a02 | 681 | /* #define VDC5_GAM_B_AREA1_COUNT (8) */ |
| AnnaBridge | 161:aa5281ff4a02 | 682 | volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 683 | volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 684 | volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 685 | volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 686 | volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 687 | volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 688 | volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 689 | volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 690 | volatile uint8_t dummy17[24]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 691 | volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 692 | volatile uint8_t dummy18[4]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 693 | |
| AnnaBridge | 161:aa5281ff4a02 | 694 | /* #define VDC5_GAM_R_LUT1_COUNT (16) */ |
| AnnaBridge | 161:aa5281ff4a02 | 695 | volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 696 | volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 697 | volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 698 | volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 699 | volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 700 | volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 701 | volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 702 | volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 703 | volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */ |
| AnnaBridge | 161:aa5281ff4a02 | 704 | volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */ |
| AnnaBridge | 161:aa5281ff4a02 | 705 | volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */ |
| AnnaBridge | 161:aa5281ff4a02 | 706 | volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */ |
| AnnaBridge | 161:aa5281ff4a02 | 707 | volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */ |
| AnnaBridge | 161:aa5281ff4a02 | 708 | volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */ |
| AnnaBridge | 161:aa5281ff4a02 | 709 | volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */ |
| AnnaBridge | 161:aa5281ff4a02 | 710 | volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */ |
| AnnaBridge | 161:aa5281ff4a02 | 711 | |
| AnnaBridge | 161:aa5281ff4a02 | 712 | /* #define VDC5_GAM_R_AREA1_COUNT (8) */ |
| AnnaBridge | 161:aa5281ff4a02 | 713 | volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 714 | volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 715 | volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 716 | volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 717 | volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 718 | volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 719 | volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 720 | volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 721 | volatile uint8_t dummy19[24]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 722 | volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 723 | volatile uint32_t TCON_TIM; /* TCON_TIM */ |
| AnnaBridge | 161:aa5281ff4a02 | 724 | |
| AnnaBridge | 161:aa5281ff4a02 | 725 | /* #define VDC5_TCON_TIM_STVA1_COUNT (2) */ |
| AnnaBridge | 161:aa5281ff4a02 | 726 | volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 727 | volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 728 | |
| AnnaBridge | 161:aa5281ff4a02 | 729 | /* #define VDC5_TCON_TIM_STVB1_COUNT (2) */ |
| AnnaBridge | 161:aa5281ff4a02 | 730 | volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 731 | volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 732 | |
| AnnaBridge | 161:aa5281ff4a02 | 733 | /* #define VDC5_TCON_TIM_STH1_COUNT (2) */ |
| AnnaBridge | 161:aa5281ff4a02 | 734 | volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 735 | volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 736 | |
| AnnaBridge | 161:aa5281ff4a02 | 737 | /* #define VDC5_TCON_TIM_STB1_COUNT (2) */ |
| AnnaBridge | 161:aa5281ff4a02 | 738 | volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 739 | volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 740 | |
| AnnaBridge | 161:aa5281ff4a02 | 741 | /* #define VDC5_TCON_TIM_CPV1_COUNT (2) */ |
| AnnaBridge | 161:aa5281ff4a02 | 742 | volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 743 | volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 744 | |
| AnnaBridge | 161:aa5281ff4a02 | 745 | /* #define VDC5_TCON_TIM_POLA1_COUNT (2) */ |
| AnnaBridge | 161:aa5281ff4a02 | 746 | volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 747 | volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 748 | |
| AnnaBridge | 161:aa5281ff4a02 | 749 | /* #define VDC5_TCON_TIM_POLB1_COUNT (2) */ |
| AnnaBridge | 161:aa5281ff4a02 | 750 | volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 751 | volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 752 | volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */ |
| AnnaBridge | 161:aa5281ff4a02 | 753 | volatile uint8_t dummy20[60]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 754 | volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 755 | volatile uint32_t OUT_SET; /* OUT_SET */ |
| AnnaBridge | 161:aa5281ff4a02 | 756 | |
| AnnaBridge | 161:aa5281ff4a02 | 757 | /* #define VDC5_OUT_BRIGHT1_COUNT (2) */ |
| AnnaBridge | 161:aa5281ff4a02 | 758 | volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 759 | volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 760 | volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */ |
| AnnaBridge | 161:aa5281ff4a02 | 761 | volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */ |
| AnnaBridge | 161:aa5281ff4a02 | 762 | volatile uint8_t dummy21[12]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 763 | volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */ |
| AnnaBridge | 161:aa5281ff4a02 | 764 | volatile uint8_t dummy22[88]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 765 | |
| AnnaBridge | 161:aa5281ff4a02 | 766 | /* #define VDC5_SYSCNT_INT1_COUNT (2) */ |
| AnnaBridge | 161:aa5281ff4a02 | 767 | volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 768 | volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 769 | volatile uint8_t dummy23[4]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 770 | volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 771 | volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 772 | volatile uint8_t dummy24[4]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 773 | volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */ |
| AnnaBridge | 161:aa5281ff4a02 | 774 | volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */ |
| AnnaBridge | 161:aa5281ff4a02 | 775 | volatile uint8_t dummy25[868]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 776 | volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 777 | volatile uint8_t dummy26[28]; /* */ |
| AnnaBridge | 161:aa5281ff4a02 | 778 | |
| AnnaBridge | 161:aa5281ff4a02 | 779 | /* #define VDC5_GR_VIN_AB1_COUNT (1) */ |
| AnnaBridge | 161:aa5281ff4a02 | 780 | volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 781 | } r_io_vdc5_t; |
| AnnaBridge | 161:aa5281ff4a02 | 782 | |
| AnnaBridge | 161:aa5281ff4a02 | 783 | |
| AnnaBridge | 161:aa5281ff4a02 | 784 | typedef struct st_vdc5_from_gr0_update |
| AnnaBridge | 161:aa5281ff4a02 | 785 | { |
| AnnaBridge | 161:aa5281ff4a02 | 786 | |
| AnnaBridge | 161:aa5281ff4a02 | 787 | volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ |
| AnnaBridge | 161:aa5281ff4a02 | 788 | volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ |
| AnnaBridge | 161:aa5281ff4a02 | 789 | volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 790 | volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 791 | volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 792 | volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ |
| AnnaBridge | 161:aa5281ff4a02 | 793 | volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ |
| AnnaBridge | 161:aa5281ff4a02 | 794 | volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ |
| AnnaBridge | 161:aa5281ff4a02 | 795 | volatile uint32_t GR0_AB1; /* GR0_AB1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 796 | volatile uint32_t GR0_AB2; /* GR0_AB2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 797 | volatile uint32_t GR0_AB3; /* GR0_AB3 */ |
| AnnaBridge | 161:aa5281ff4a02 | 798 | } r_io_vdc5_from_gr0_update_t; |
| AnnaBridge | 161:aa5281ff4a02 | 799 | |
| AnnaBridge | 161:aa5281ff4a02 | 800 | |
| AnnaBridge | 161:aa5281ff4a02 | 801 | typedef struct st_vdc5_from_gr0_ab7 |
| AnnaBridge | 161:aa5281ff4a02 | 802 | { |
| AnnaBridge | 161:aa5281ff4a02 | 803 | |
| AnnaBridge | 161:aa5281ff4a02 | 804 | volatile uint32_t GR0_AB7; /* GR0_AB7 */ |
| AnnaBridge | 161:aa5281ff4a02 | 805 | volatile uint32_t GR0_AB8; /* GR0_AB8 */ |
| AnnaBridge | 161:aa5281ff4a02 | 806 | volatile uint32_t GR0_AB9; /* GR0_AB9 */ |
| AnnaBridge | 161:aa5281ff4a02 | 807 | volatile uint32_t GR0_AB10; /* GR0_AB10 */ |
| AnnaBridge | 161:aa5281ff4a02 | 808 | volatile uint32_t GR0_AB11; /* GR0_AB11 */ |
| AnnaBridge | 161:aa5281ff4a02 | 809 | volatile uint32_t GR0_BASE; /* GR0_BASE */ |
| AnnaBridge | 161:aa5281ff4a02 | 810 | } r_io_vdc5_from_gr0_ab7_t; |
| AnnaBridge | 161:aa5281ff4a02 | 811 | |
| AnnaBridge | 161:aa5281ff4a02 | 812 | |
| AnnaBridge | 161:aa5281ff4a02 | 813 | /* Channel array defines of VDC5 (2)*/ |
| AnnaBridge | 161:aa5281ff4a02 | 814 | #ifdef DECLARE_VDC5_CHANNELS |
| AnnaBridge | 161:aa5281ff4a02 | 815 | volatile struct st_vdc5* VDC5[ VDC5_COUNT ] = |
| AnnaBridge | 161:aa5281ff4a02 | 816 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 817 | VDC5_ADDRESS_LIST; |
| AnnaBridge | 161:aa5281ff4a02 | 818 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 819 | #endif /* DECLARE_VDC5_CHANNELS */ |
| AnnaBridge | 161:aa5281ff4a02 | 820 | |
| AnnaBridge | 161:aa5281ff4a02 | 821 | #ifdef DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS |
| AnnaBridge | 161:aa5281ff4a02 | 822 | volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] = |
| AnnaBridge | 161:aa5281ff4a02 | 823 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 824 | VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST; |
| AnnaBridge | 161:aa5281ff4a02 | 825 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 826 | #endif /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */ |
| AnnaBridge | 161:aa5281ff4a02 | 827 | |
| AnnaBridge | 161:aa5281ff4a02 | 828 | #ifdef DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS |
| AnnaBridge | 161:aa5281ff4a02 | 829 | volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] = |
| AnnaBridge | 161:aa5281ff4a02 | 830 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 831 | VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST; |
| AnnaBridge | 161:aa5281ff4a02 | 832 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 833 | #endif /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */ |
| AnnaBridge | 161:aa5281ff4a02 | 834 | |
| AnnaBridge | 161:aa5281ff4a02 | 835 | #ifdef DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS |
| AnnaBridge | 161:aa5281ff4a02 | 836 | volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] = |
| AnnaBridge | 161:aa5281ff4a02 | 837 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 838 | VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST; |
| AnnaBridge | 161:aa5281ff4a02 | 839 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 840 | #endif /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */ |
| AnnaBridge | 161:aa5281ff4a02 | 841 | |
| AnnaBridge | 161:aa5281ff4a02 | 842 | #ifdef DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS |
| AnnaBridge | 161:aa5281ff4a02 | 843 | volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] = |
| AnnaBridge | 161:aa5281ff4a02 | 844 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 845 | VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST; |
| AnnaBridge | 161:aa5281ff4a02 | 846 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 847 | #endif /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */ |
| AnnaBridge | 161:aa5281ff4a02 | 848 | /* End of channel array defines of VDC5 (2)*/ |
| AnnaBridge | 161:aa5281ff4a02 | 849 | |
| AnnaBridge | 161:aa5281ff4a02 | 850 | |
| AnnaBridge | 161:aa5281ff4a02 | 851 | /* <-SEC M1.10.1 */ |
| AnnaBridge | 161:aa5281ff4a02 | 852 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ |
| AnnaBridge | 161:aa5281ff4a02 | 853 | /* <-QAC 0857 */ |
| AnnaBridge | 161:aa5281ff4a02 | 854 | /* <-QAC 0639 */ |
| AnnaBridge | 161:aa5281ff4a02 | 855 | #endif |
