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TARGET_FF_LPC546XX/TOOLCHAIN_GCC_ARM/fsl_ctimer.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * The Clear BSD License
AnnaBridge 171:3a7713b1edbc 3 * Copyright (c) 2016, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 4 * Copyright 2016-2017 NXP
AnnaBridge 171:3a7713b1edbc 5 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 6 *
AnnaBridge 171:3a7713b1edbc 7 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 8 * are permitted (subject to the limitations in the disclaimer below) provided
AnnaBridge 171:3a7713b1edbc 9 * that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 12 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 15 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 16 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 171:3a7713b1edbc 19 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 20 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
AnnaBridge 171:3a7713b1edbc 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 33 */
AnnaBridge 171:3a7713b1edbc 34 #ifndef _FSL_CTIMER_H_
AnnaBridge 171:3a7713b1edbc 35 #define _FSL_CTIMER_H_
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 38
AnnaBridge 171:3a7713b1edbc 39 /*!
AnnaBridge 171:3a7713b1edbc 40 * @addtogroup ctimer
AnnaBridge 171:3a7713b1edbc 41 * @{
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /*! @file */
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 47 * Definitions
AnnaBridge 171:3a7713b1edbc 48 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52 #define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
AnnaBridge 171:3a7713b1edbc 53 /*@}*/
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /*! @brief List of Timer capture channels */
AnnaBridge 171:3a7713b1edbc 56 typedef enum _ctimer_capture_channel
AnnaBridge 171:3a7713b1edbc 57 {
AnnaBridge 171:3a7713b1edbc 58 kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
AnnaBridge 171:3a7713b1edbc 59 kCTIMER_Capture_1, /*!< Timer capture channel 1 */
AnnaBridge 171:3a7713b1edbc 60 kCTIMER_Capture_2, /*!< Timer capture channel 2 */
AnnaBridge 171:3a7713b1edbc 61 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
AnnaBridge 171:3a7713b1edbc 62 kCTIMER_Capture_3 /*!< Timer capture channel 3 */
AnnaBridge 171:3a7713b1edbc 63 #endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
AnnaBridge 171:3a7713b1edbc 64 } ctimer_capture_channel_t;
AnnaBridge 171:3a7713b1edbc 65
AnnaBridge 171:3a7713b1edbc 66 /*! @brief List of capture edge options */
AnnaBridge 171:3a7713b1edbc 67 typedef enum _ctimer_capture_edge
AnnaBridge 171:3a7713b1edbc 68 {
AnnaBridge 171:3a7713b1edbc 69 kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */
AnnaBridge 171:3a7713b1edbc 70 kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */
AnnaBridge 171:3a7713b1edbc 71 kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */
AnnaBridge 171:3a7713b1edbc 72 } ctimer_capture_edge_t;
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 /*! @brief List of Timer match registers */
AnnaBridge 171:3a7713b1edbc 75 typedef enum _ctimer_match
AnnaBridge 171:3a7713b1edbc 76 {
AnnaBridge 171:3a7713b1edbc 77 kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */
AnnaBridge 171:3a7713b1edbc 78 kCTIMER_Match_1, /*!< Timer match register 1 */
AnnaBridge 171:3a7713b1edbc 79 kCTIMER_Match_2, /*!< Timer match register 2 */
AnnaBridge 171:3a7713b1edbc 80 kCTIMER_Match_3 /*!< Timer match register 3 */
AnnaBridge 171:3a7713b1edbc 81 } ctimer_match_t;
AnnaBridge 171:3a7713b1edbc 82
AnnaBridge 171:3a7713b1edbc 83 /*! @brief List of output control options */
AnnaBridge 171:3a7713b1edbc 84 typedef enum _ctimer_match_output_control
AnnaBridge 171:3a7713b1edbc 85 {
AnnaBridge 171:3a7713b1edbc 86 kCTIMER_Output_NoAction = 0U, /*!< No action is taken */
AnnaBridge 171:3a7713b1edbc 87 kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */
AnnaBridge 171:3a7713b1edbc 88 kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */
AnnaBridge 171:3a7713b1edbc 89 kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */
AnnaBridge 171:3a7713b1edbc 90 } ctimer_match_output_control_t;
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 /*! @brief List of Timer modes */
AnnaBridge 171:3a7713b1edbc 93 typedef enum _ctimer_timer_mode
AnnaBridge 171:3a7713b1edbc 94 {
AnnaBridge 171:3a7713b1edbc 95 kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */
AnnaBridge 171:3a7713b1edbc 96 kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */
AnnaBridge 171:3a7713b1edbc 97 kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */
AnnaBridge 171:3a7713b1edbc 98 kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */
AnnaBridge 171:3a7713b1edbc 99 } ctimer_timer_mode_t;
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 /*! @brief List of Timer interrupts */
AnnaBridge 171:3a7713b1edbc 102 typedef enum _ctimer_interrupt_enable
AnnaBridge 171:3a7713b1edbc 103 {
AnnaBridge 171:3a7713b1edbc 104 kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */
AnnaBridge 171:3a7713b1edbc 105 kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */
AnnaBridge 171:3a7713b1edbc 106 kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */
AnnaBridge 171:3a7713b1edbc 107 kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */
AnnaBridge 171:3a7713b1edbc 108 kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
AnnaBridge 171:3a7713b1edbc 109 kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
AnnaBridge 171:3a7713b1edbc 110 kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
AnnaBridge 171:3a7713b1edbc 111 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
AnnaBridge 171:3a7713b1edbc 112 kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
AnnaBridge 171:3a7713b1edbc 113 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
AnnaBridge 171:3a7713b1edbc 114 } ctimer_interrupt_enable_t;
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 /*! @brief List of Timer flags */
AnnaBridge 171:3a7713b1edbc 117 typedef enum _ctimer_status_flags
AnnaBridge 171:3a7713b1edbc 118 {
AnnaBridge 171:3a7713b1edbc 119 kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */
AnnaBridge 171:3a7713b1edbc 120 kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */
AnnaBridge 171:3a7713b1edbc 121 kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */
AnnaBridge 171:3a7713b1edbc 122 kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */
AnnaBridge 171:3a7713b1edbc 123 kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
AnnaBridge 171:3a7713b1edbc 124 kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
AnnaBridge 171:3a7713b1edbc 125 kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
AnnaBridge 171:3a7713b1edbc 126 #if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
AnnaBridge 171:3a7713b1edbc 127 kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
AnnaBridge 171:3a7713b1edbc 128 #endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
AnnaBridge 171:3a7713b1edbc 129 } ctimer_status_flags_t;
AnnaBridge 171:3a7713b1edbc 130
AnnaBridge 171:3a7713b1edbc 131 typedef void (*ctimer_callback_t)(uint32_t flags);
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 /*! @brief Callback type when registering for a callback. When registering a callback
AnnaBridge 171:3a7713b1edbc 134 * an array of function pointers is passed the size could be 1 or 8, the callback
AnnaBridge 171:3a7713b1edbc 135 * type will tell that.
AnnaBridge 171:3a7713b1edbc 136 */
AnnaBridge 171:3a7713b1edbc 137 typedef enum
AnnaBridge 171:3a7713b1edbc 138 {
AnnaBridge 171:3a7713b1edbc 139 kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer.
AnnaBridge 171:3a7713b1edbc 140 based on the status flags different channels needs to be handled differently */
AnnaBridge 171:3a7713b1edbc 141 kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel.
AnnaBridge 171:3a7713b1edbc 142 for both match/capture */
AnnaBridge 171:3a7713b1edbc 143 } ctimer_callback_type_t;
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 /*!
AnnaBridge 171:3a7713b1edbc 146 * @brief Match configuration
AnnaBridge 171:3a7713b1edbc 147 *
AnnaBridge 171:3a7713b1edbc 148 * This structure holds the configuration settings for each match register.
AnnaBridge 171:3a7713b1edbc 149 */
AnnaBridge 171:3a7713b1edbc 150 typedef struct _ctimer_match_config
AnnaBridge 171:3a7713b1edbc 151 {
AnnaBridge 171:3a7713b1edbc 152 uint32_t matchValue; /*!< This is stored in the match register */
AnnaBridge 171:3a7713b1edbc 153 bool enableCounterReset; /*!< true: Match will reset the counter
AnnaBridge 171:3a7713b1edbc 154 false: Match will not reser the counter */
AnnaBridge 171:3a7713b1edbc 155 bool enableCounterStop; /*!< true: Match will stop the counter
AnnaBridge 171:3a7713b1edbc 156 false: Match will not stop the counter */
AnnaBridge 171:3a7713b1edbc 157 ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */
AnnaBridge 171:3a7713b1edbc 158 bool outPinInitState; /*!< Initial value of the EM bit/output */
AnnaBridge 171:3a7713b1edbc 159 bool enableInterrupt; /*!< true: Generate interrupt upon match
AnnaBridge 171:3a7713b1edbc 160 false: Do not generate interrupt on match */
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 } ctimer_match_config_t;
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 /*!
AnnaBridge 171:3a7713b1edbc 165 * @brief Timer configuration structure
AnnaBridge 171:3a7713b1edbc 166 *
AnnaBridge 171:3a7713b1edbc 167 * This structure holds the configuration settings for the Timer peripheral. To initialize this
AnnaBridge 171:3a7713b1edbc 168 * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a
AnnaBridge 171:3a7713b1edbc 169 * pointer to the configuration structure instance.
AnnaBridge 171:3a7713b1edbc 170 *
AnnaBridge 171:3a7713b1edbc 171 * The configuration structure can be made constant so as to reside in flash.
AnnaBridge 171:3a7713b1edbc 172 */
AnnaBridge 171:3a7713b1edbc 173 typedef struct _ctimer_config
AnnaBridge 171:3a7713b1edbc 174 {
AnnaBridge 171:3a7713b1edbc 175 ctimer_timer_mode_t mode; /*!< Timer mode */
AnnaBridge 171:3a7713b1edbc 176 ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer
AnnaBridge 171:3a7713b1edbc 177 modes that rely on this input signal to increment TC */
AnnaBridge 171:3a7713b1edbc 178 uint32_t prescale; /*!< Prescale value */
AnnaBridge 171:3a7713b1edbc 179 } ctimer_config_t;
AnnaBridge 171:3a7713b1edbc 180
AnnaBridge 171:3a7713b1edbc 181 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 182 * API
AnnaBridge 171:3a7713b1edbc 183 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 186 extern "C" {
AnnaBridge 171:3a7713b1edbc 187 #endif
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /*!
AnnaBridge 171:3a7713b1edbc 190 * @name Initialization and deinitialization
AnnaBridge 171:3a7713b1edbc 191 * @{
AnnaBridge 171:3a7713b1edbc 192 */
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 /*!
AnnaBridge 171:3a7713b1edbc 195 * @brief Ungates the clock and configures the peripheral for basic operation.
AnnaBridge 171:3a7713b1edbc 196 *
AnnaBridge 171:3a7713b1edbc 197 * @note This API should be called at the beginning of the application before using the driver.
AnnaBridge 171:3a7713b1edbc 198 *
AnnaBridge 171:3a7713b1edbc 199 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 200 * @param config Pointer to the user configuration structure.
AnnaBridge 171:3a7713b1edbc 201 */
AnnaBridge 171:3a7713b1edbc 202 void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config);
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204 /*!
AnnaBridge 171:3a7713b1edbc 205 * @brief Gates the timer clock.
AnnaBridge 171:3a7713b1edbc 206 *
AnnaBridge 171:3a7713b1edbc 207 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 208 */
AnnaBridge 171:3a7713b1edbc 209 void CTIMER_Deinit(CTIMER_Type *base);
AnnaBridge 171:3a7713b1edbc 210
AnnaBridge 171:3a7713b1edbc 211 /*!
AnnaBridge 171:3a7713b1edbc 212 * @brief Fills in the timers configuration structure with the default settings.
AnnaBridge 171:3a7713b1edbc 213 *
AnnaBridge 171:3a7713b1edbc 214 * The default values are:
AnnaBridge 171:3a7713b1edbc 215 * @code
AnnaBridge 171:3a7713b1edbc 216 * config->mode = kCTIMER_TimerMode;
AnnaBridge 171:3a7713b1edbc 217 * config->input = kCTIMER_Capture_0;
AnnaBridge 171:3a7713b1edbc 218 * config->prescale = 0;
AnnaBridge 171:3a7713b1edbc 219 * @endcode
AnnaBridge 171:3a7713b1edbc 220 * @param config Pointer to the user configuration structure.
AnnaBridge 171:3a7713b1edbc 221 */
AnnaBridge 171:3a7713b1edbc 222 void CTIMER_GetDefaultConfig(ctimer_config_t *config);
AnnaBridge 171:3a7713b1edbc 223
AnnaBridge 171:3a7713b1edbc 224 /*! @}*/
AnnaBridge 171:3a7713b1edbc 225
AnnaBridge 171:3a7713b1edbc 226 /*!
AnnaBridge 171:3a7713b1edbc 227 * @name PWM setup operations
AnnaBridge 171:3a7713b1edbc 228 * @{
AnnaBridge 171:3a7713b1edbc 229 */
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /*!
AnnaBridge 171:3a7713b1edbc 232 * @brief Configures the PWM signal parameters.
AnnaBridge 171:3a7713b1edbc 233 *
AnnaBridge 171:3a7713b1edbc 234 * Enables PWM mode on the match channel passed in and will then setup the match value
AnnaBridge 171:3a7713b1edbc 235 * and other match parameters to generate a PWM signal.
AnnaBridge 171:3a7713b1edbc 236 * This function will assign match channel 3 to set the PWM cycle.
AnnaBridge 171:3a7713b1edbc 237 *
AnnaBridge 171:3a7713b1edbc 238 * @note When setting PWM output from multiple output pins, all should use the same PWM
AnnaBridge 171:3a7713b1edbc 239 * frequency
AnnaBridge 171:3a7713b1edbc 240 *
AnnaBridge 171:3a7713b1edbc 241 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 242 * @param matchChannel Match pin to be used to output the PWM signal
AnnaBridge 171:3a7713b1edbc 243 * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
AnnaBridge 171:3a7713b1edbc 244 * @param pwmFreq_Hz PWM signal frequency in Hz
AnnaBridge 171:3a7713b1edbc 245 * @param srcClock_Hz Timer counter clock in Hz
AnnaBridge 171:3a7713b1edbc 246 * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse,
AnnaBridge 171:3a7713b1edbc 247 * if it is 0 then no interrupt is generated
AnnaBridge 171:3a7713b1edbc 248 *
AnnaBridge 171:3a7713b1edbc 249 * @return kStatus_Success on success
AnnaBridge 171:3a7713b1edbc 250 * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
AnnaBridge 171:3a7713b1edbc 251 */
AnnaBridge 171:3a7713b1edbc 252 status_t CTIMER_SetupPwm(CTIMER_Type *base,
AnnaBridge 171:3a7713b1edbc 253 ctimer_match_t matchChannel,
AnnaBridge 171:3a7713b1edbc 254 uint8_t dutyCyclePercent,
AnnaBridge 171:3a7713b1edbc 255 uint32_t pwmFreq_Hz,
AnnaBridge 171:3a7713b1edbc 256 uint32_t srcClock_Hz,
AnnaBridge 171:3a7713b1edbc 257 bool enableInt);
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 /*!
AnnaBridge 171:3a7713b1edbc 260 * @brief Updates the duty cycle of an active PWM signal.
AnnaBridge 171:3a7713b1edbc 261 *
AnnaBridge 171:3a7713b1edbc 262 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 263 * @param matchChannel Match pin to be used to output the PWM signal
AnnaBridge 171:3a7713b1edbc 264 * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
AnnaBridge 171:3a7713b1edbc 265 */
AnnaBridge 171:3a7713b1edbc 266 void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent);
AnnaBridge 171:3a7713b1edbc 267
AnnaBridge 171:3a7713b1edbc 268 /*! @}*/
AnnaBridge 171:3a7713b1edbc 269
AnnaBridge 171:3a7713b1edbc 270 /*!
AnnaBridge 171:3a7713b1edbc 271 * @brief Setup the match register.
AnnaBridge 171:3a7713b1edbc 272 *
AnnaBridge 171:3a7713b1edbc 273 * User configuration is used to setup the match value and action to be taken when a match occurs.
AnnaBridge 171:3a7713b1edbc 274 *
AnnaBridge 171:3a7713b1edbc 275 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 276 * @param matchChannel Match register to configure
AnnaBridge 171:3a7713b1edbc 277 * @param config Pointer to the match configuration structure
AnnaBridge 171:3a7713b1edbc 278 */
AnnaBridge 171:3a7713b1edbc 279 void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config);
AnnaBridge 171:3a7713b1edbc 280
AnnaBridge 171:3a7713b1edbc 281 /*!
AnnaBridge 171:3a7713b1edbc 282 * @brief Setup the capture.
AnnaBridge 171:3a7713b1edbc 283 *
AnnaBridge 171:3a7713b1edbc 284 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 285 * @param capture Capture channel to configure
AnnaBridge 171:3a7713b1edbc 286 * @param edge Edge on the channel that will trigger a capture
AnnaBridge 171:3a7713b1edbc 287 * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back
AnnaBridge 171:3a7713b1edbc 288 * is called upon capture
AnnaBridge 171:3a7713b1edbc 289 */
AnnaBridge 171:3a7713b1edbc 290 void CTIMER_SetupCapture(CTIMER_Type *base,
AnnaBridge 171:3a7713b1edbc 291 ctimer_capture_channel_t capture,
AnnaBridge 171:3a7713b1edbc 292 ctimer_capture_edge_t edge,
AnnaBridge 171:3a7713b1edbc 293 bool enableInt);
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 /*!
AnnaBridge 171:3a7713b1edbc 296 * @brief Register callback.
AnnaBridge 171:3a7713b1edbc 297 *
AnnaBridge 171:3a7713b1edbc 298 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 299 * @param cb_func callback function
AnnaBridge 171:3a7713b1edbc 300 * @param cb_type callback function type, singular or multiple
AnnaBridge 171:3a7713b1edbc 301 */
AnnaBridge 171:3a7713b1edbc 302 void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type);
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304 /*!
AnnaBridge 171:3a7713b1edbc 305 * @name Interrupt Interface
AnnaBridge 171:3a7713b1edbc 306 * @{
AnnaBridge 171:3a7713b1edbc 307 */
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309 /*!
AnnaBridge 171:3a7713b1edbc 310 * @brief Enables the selected Timer interrupts.
AnnaBridge 171:3a7713b1edbc 311 *
AnnaBridge 171:3a7713b1edbc 312 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 313 * @param mask The interrupts to enable. This is a logical OR of members of the
AnnaBridge 171:3a7713b1edbc 314 * enumeration ::ctimer_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 315 */
AnnaBridge 171:3a7713b1edbc 316 static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 317 {
AnnaBridge 171:3a7713b1edbc 318 /* Enable match interrupts */
AnnaBridge 171:3a7713b1edbc 319 base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 /* Enable capture interrupts */
AnnaBridge 171:3a7713b1edbc 322 base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
AnnaBridge 171:3a7713b1edbc 323 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
AnnaBridge 171:3a7713b1edbc 324 | CTIMER_CCR_CAP3I_MASK
AnnaBridge 171:3a7713b1edbc 325 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
AnnaBridge 171:3a7713b1edbc 326 );
AnnaBridge 171:3a7713b1edbc 327 }
AnnaBridge 171:3a7713b1edbc 328
AnnaBridge 171:3a7713b1edbc 329 /*!
AnnaBridge 171:3a7713b1edbc 330 * @brief Disables the selected Timer interrupts.
AnnaBridge 171:3a7713b1edbc 331 *
AnnaBridge 171:3a7713b1edbc 332 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 333 * @param mask The interrupts to enable. This is a logical OR of members of the
AnnaBridge 171:3a7713b1edbc 334 * enumeration ::ctimer_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 335 */
AnnaBridge 171:3a7713b1edbc 336 static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 337 {
AnnaBridge 171:3a7713b1edbc 338 /* Disable match interrupts */
AnnaBridge 171:3a7713b1edbc 339 base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK));
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341 /* Disable capture interrupts */
AnnaBridge 171:3a7713b1edbc 342 base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
AnnaBridge 171:3a7713b1edbc 343 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
AnnaBridge 171:3a7713b1edbc 344 | CTIMER_CCR_CAP3I_MASK
AnnaBridge 171:3a7713b1edbc 345 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
AnnaBridge 171:3a7713b1edbc 346 ));
AnnaBridge 171:3a7713b1edbc 347 }
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349 /*!
AnnaBridge 171:3a7713b1edbc 350 * @brief Gets the enabled Timer interrupts.
AnnaBridge 171:3a7713b1edbc 351 *
AnnaBridge 171:3a7713b1edbc 352 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 353 *
AnnaBridge 171:3a7713b1edbc 354 * @return The enabled interrupts. This is the logical OR of members of the
AnnaBridge 171:3a7713b1edbc 355 * enumeration ::ctimer_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 356 */
AnnaBridge 171:3a7713b1edbc 357 static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)
AnnaBridge 171:3a7713b1edbc 358 {
AnnaBridge 171:3a7713b1edbc 359 uint32_t enabledIntrs = 0;
AnnaBridge 171:3a7713b1edbc 360
AnnaBridge 171:3a7713b1edbc 361 /* Get all the match interrupts enabled */
AnnaBridge 171:3a7713b1edbc 362 enabledIntrs =
AnnaBridge 171:3a7713b1edbc 363 base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365 /* Get all the capture interrupts enabled */
AnnaBridge 171:3a7713b1edbc 366 enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
AnnaBridge 171:3a7713b1edbc 367 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
AnnaBridge 171:3a7713b1edbc 368 | CTIMER_CCR_CAP3I_MASK
AnnaBridge 171:3a7713b1edbc 369 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
AnnaBridge 171:3a7713b1edbc 370 );
AnnaBridge 171:3a7713b1edbc 371
AnnaBridge 171:3a7713b1edbc 372 return enabledIntrs;
AnnaBridge 171:3a7713b1edbc 373 }
AnnaBridge 171:3a7713b1edbc 374
AnnaBridge 171:3a7713b1edbc 375 /*! @}*/
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 /*!
AnnaBridge 171:3a7713b1edbc 378 * @name Status Interface
AnnaBridge 171:3a7713b1edbc 379 * @{
AnnaBridge 171:3a7713b1edbc 380 */
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382 /*!
AnnaBridge 171:3a7713b1edbc 383 * @brief Gets the Timer status flags.
AnnaBridge 171:3a7713b1edbc 384 *
AnnaBridge 171:3a7713b1edbc 385 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 386 *
AnnaBridge 171:3a7713b1edbc 387 * @return The status flags. This is the logical OR of members of the
AnnaBridge 171:3a7713b1edbc 388 * enumeration ::ctimer_status_flags_t
AnnaBridge 171:3a7713b1edbc 389 */
AnnaBridge 171:3a7713b1edbc 390 static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)
AnnaBridge 171:3a7713b1edbc 391 {
AnnaBridge 171:3a7713b1edbc 392 return base->IR;
AnnaBridge 171:3a7713b1edbc 393 }
AnnaBridge 171:3a7713b1edbc 394
AnnaBridge 171:3a7713b1edbc 395 /*!
AnnaBridge 171:3a7713b1edbc 396 * @brief Clears the Timer status flags.
AnnaBridge 171:3a7713b1edbc 397 *
AnnaBridge 171:3a7713b1edbc 398 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 399 * @param mask The status flags to clear. This is a logical OR of members of the
AnnaBridge 171:3a7713b1edbc 400 * enumeration ::ctimer_status_flags_t
AnnaBridge 171:3a7713b1edbc 401 */
AnnaBridge 171:3a7713b1edbc 402 static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 403 {
AnnaBridge 171:3a7713b1edbc 404 base->IR = mask;
AnnaBridge 171:3a7713b1edbc 405 }
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /*! @}*/
AnnaBridge 171:3a7713b1edbc 408
AnnaBridge 171:3a7713b1edbc 409 /*!
AnnaBridge 171:3a7713b1edbc 410 * @name Counter Start and Stop
AnnaBridge 171:3a7713b1edbc 411 * @{
AnnaBridge 171:3a7713b1edbc 412 */
AnnaBridge 171:3a7713b1edbc 413
AnnaBridge 171:3a7713b1edbc 414 /*!
AnnaBridge 171:3a7713b1edbc 415 * @brief Starts the Timer counter.
AnnaBridge 171:3a7713b1edbc 416 *
AnnaBridge 171:3a7713b1edbc 417 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 418 */
AnnaBridge 171:3a7713b1edbc 419 static inline void CTIMER_StartTimer(CTIMER_Type *base)
AnnaBridge 171:3a7713b1edbc 420 {
AnnaBridge 171:3a7713b1edbc 421 base->TCR |= CTIMER_TCR_CEN_MASK;
AnnaBridge 171:3a7713b1edbc 422 }
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424 /*!
AnnaBridge 171:3a7713b1edbc 425 * @brief Stops the Timer counter.
AnnaBridge 171:3a7713b1edbc 426 *
AnnaBridge 171:3a7713b1edbc 427 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 428 */
AnnaBridge 171:3a7713b1edbc 429 static inline void CTIMER_StopTimer(CTIMER_Type *base)
AnnaBridge 171:3a7713b1edbc 430 {
AnnaBridge 171:3a7713b1edbc 431 base->TCR &= ~CTIMER_TCR_CEN_MASK;
AnnaBridge 171:3a7713b1edbc 432 }
AnnaBridge 171:3a7713b1edbc 433
AnnaBridge 171:3a7713b1edbc 434 /*! @}*/
AnnaBridge 171:3a7713b1edbc 435
AnnaBridge 171:3a7713b1edbc 436 /*!
AnnaBridge 171:3a7713b1edbc 437 * @brief Reset the counter.
AnnaBridge 171:3a7713b1edbc 438 *
AnnaBridge 171:3a7713b1edbc 439 * The timer counter and prescale counter are reset on the next positive edge of the APB clock.
AnnaBridge 171:3a7713b1edbc 440 *
AnnaBridge 171:3a7713b1edbc 441 * @param base Ctimer peripheral base address
AnnaBridge 171:3a7713b1edbc 442 */
AnnaBridge 171:3a7713b1edbc 443 static inline void CTIMER_Reset(CTIMER_Type *base)
AnnaBridge 171:3a7713b1edbc 444 {
AnnaBridge 171:3a7713b1edbc 445 base->TCR |= CTIMER_TCR_CRST_MASK;
AnnaBridge 171:3a7713b1edbc 446 base->TCR &= ~CTIMER_TCR_CRST_MASK;
AnnaBridge 171:3a7713b1edbc 447 }
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 450 }
AnnaBridge 171:3a7713b1edbc 451 #endif
AnnaBridge 171:3a7713b1edbc 452
AnnaBridge 171:3a7713b1edbc 453 /*! @}*/
AnnaBridge 171:3a7713b1edbc 454
AnnaBridge 171:3a7713b1edbc 455 #endif /* _FSL_CTIMER_H_ */