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TARGET_EFM32PG_STK3401/TOOLCHAIN_GCC_ARM/efm32pg1b_leuart.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32pg1b_leuart.h |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @brief EFM32PG1B_LEUART register and bit field definitions |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @version 5.1.2 |
| AnnaBridge | 171:3a7713b1edbc | 5 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 6 | * @section License |
| AnnaBridge | 171:3a7713b1edbc | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 9 | * |
| AnnaBridge | 171:3a7713b1edbc | 10 | * Permission is granted to anyone to use this software for any purpose, |
| AnnaBridge | 171:3a7713b1edbc | 11 | * including commercial applications, and to alter it and redistribute it |
| AnnaBridge | 171:3a7713b1edbc | 12 | * freely, subject to the following restrictions: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * |
| AnnaBridge | 171:3a7713b1edbc | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| AnnaBridge | 171:3a7713b1edbc | 15 | * claim that you wrote the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| AnnaBridge | 171:3a7713b1edbc | 17 | * misrepresented as being the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| AnnaBridge | 171:3a7713b1edbc | 19 | * |
| AnnaBridge | 171:3a7713b1edbc | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| AnnaBridge | 171:3a7713b1edbc | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| AnnaBridge | 171:3a7713b1edbc | 23 | * kind, including, but not limited to, any implied warranties of |
| AnnaBridge | 171:3a7713b1edbc | 24 | * merchantability or fitness for any particular purpose or warranties against |
| AnnaBridge | 171:3a7713b1edbc | 25 | * infringement of any proprietary rights of a third party. |
| AnnaBridge | 171:3a7713b1edbc | 26 | * |
| AnnaBridge | 171:3a7713b1edbc | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| AnnaBridge | 171:3a7713b1edbc | 29 | * any third party, arising from your use of this Software. |
| AnnaBridge | 171:3a7713b1edbc | 30 | * |
| AnnaBridge | 171:3a7713b1edbc | 31 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 32 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 33 | * @addtogroup Parts |
| AnnaBridge | 171:3a7713b1edbc | 34 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 35 | ******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 36 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 37 | * @defgroup EFM32PG1B_LEUART |
| AnnaBridge | 171:3a7713b1edbc | 38 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 39 | * @brief EFM32PG1B_LEUART Register Declaration |
| AnnaBridge | 171:3a7713b1edbc | 40 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 41 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 42 | { |
| AnnaBridge | 171:3a7713b1edbc | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 44 | __IOM uint32_t CMD; /**< Command Register */ |
| AnnaBridge | 171:3a7713b1edbc | 45 | __IM uint32_t STATUS; /**< Status Register */ |
| AnnaBridge | 171:3a7713b1edbc | 46 | __IOM uint32_t CLKDIV; /**< Clock Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 47 | __IOM uint32_t STARTFRAME; /**< Start Frame Register */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | __IOM uint32_t SIGFRAME; /**< Signal Frame Register */ |
| AnnaBridge | 171:3a7713b1edbc | 49 | __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ |
| AnnaBridge | 171:3a7713b1edbc | 51 | __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| AnnaBridge | 171:3a7713b1edbc | 58 | __IOM uint32_t PULSECTRL; /**< Pulse Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | |
| AnnaBridge | 171:3a7713b1edbc | 60 | __IOM uint32_t FREEZE; /**< Freeze Register */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | |
| AnnaBridge | 171:3a7713b1edbc | 63 | uint32_t RESERVED0[3]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 64 | __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ |
| AnnaBridge | 171:3a7713b1edbc | 66 | uint32_t RESERVED1[2]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 67 | __IOM uint32_t INPUT; /**< LEUART Input Register */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | } LEUART_TypeDef; /** @} */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | |
| AnnaBridge | 171:3a7713b1edbc | 70 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 71 | * @defgroup EFM32PG1B_LEUART_BitFields |
| AnnaBridge | 171:3a7713b1edbc | 72 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 73 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 74 | |
| AnnaBridge | 171:3a7713b1edbc | 75 | /* Bit fields for LEUART CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | #define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | #define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | #define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | #define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | #define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | #define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | #define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | #define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | #define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | #define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | #define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | #define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | #define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | #define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | #define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | #define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */ |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | #define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | #define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | #define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */ |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | |
| AnnaBridge | 171:3a7713b1edbc | 169 | /* Bit fields for LEUART CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */ |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | #define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | |
| AnnaBridge | 171:3a7713b1edbc | 213 | /* Bit fields for LEUART STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */ |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 225 | #define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */ |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */ |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */ |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | |
| AnnaBridge | 171:3a7713b1edbc | 252 | /* Bit fields for LEUART CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */ |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | |
| AnnaBridge | 171:3a7713b1edbc | 260 | /* Bit fields for LEUART STARTFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | |
| AnnaBridge | 171:3a7713b1edbc | 268 | /* Bit fields for LEUART SIGFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 275 | |
| AnnaBridge | 171:3a7713b1edbc | 276 | /* Bit fields for LEUART RXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | |
| AnnaBridge | 171:3a7713b1edbc | 294 | /* Bit fields for LEUART RXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | |
| AnnaBridge | 171:3a7713b1edbc | 302 | /* Bit fields for LEUART RXDATAXP */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */ |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | |
| AnnaBridge | 171:3a7713b1edbc | 320 | /* Bit fields for LEUART TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | #define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 324 | #define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */ |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */ |
| AnnaBridge | 171:3a7713b1edbc | 330 | #define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 331 | #define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | |
| AnnaBridge | 171:3a7713b1edbc | 343 | /* Bit fields for LEUART TXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | |
| AnnaBridge | 171:3a7713b1edbc | 351 | /* Bit fields for LEUART IF */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | #define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 374 | #define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | #define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ |
| AnnaBridge | 171:3a7713b1edbc | 392 | #define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | #define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 409 | |
| AnnaBridge | 171:3a7713b1edbc | 410 | /* Bit fields for LEUART IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | #define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | #define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 421 | #define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 422 | #define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 423 | #define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 424 | #define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ |
| AnnaBridge | 171:3a7713b1edbc | 425 | #define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ |
| AnnaBridge | 171:3a7713b1edbc | 426 | #define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 427 | #define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 428 | #define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 430 | #define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | #define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 432 | #define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 433 | #define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 434 | #define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ |
| AnnaBridge | 171:3a7713b1edbc | 435 | #define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | #define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 437 | #define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | #define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 439 | #define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 442 | #define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 444 | #define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ |
| AnnaBridge | 171:3a7713b1edbc | 445 | #define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ |
| AnnaBridge | 171:3a7713b1edbc | 446 | #define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | #define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 448 | #define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 449 | #define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 454 | #define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ |
| AnnaBridge | 171:3a7713b1edbc | 456 | #define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 457 | #define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 458 | |
| AnnaBridge | 171:3a7713b1edbc | 459 | /* Bit fields for LEUART IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 460 | #define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 461 | #define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ |
| AnnaBridge | 171:3a7713b1edbc | 465 | #define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 466 | #define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 467 | #define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 468 | #define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 469 | #define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 470 | #define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 471 | #define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 472 | #define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 473 | #define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ |
| AnnaBridge | 171:3a7713b1edbc | 474 | #define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ |
| AnnaBridge | 171:3a7713b1edbc | 475 | #define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 476 | #define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 477 | #define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 478 | #define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 479 | #define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 480 | #define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 481 | #define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 482 | #define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 483 | #define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ |
| AnnaBridge | 171:3a7713b1edbc | 484 | #define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ |
| AnnaBridge | 171:3a7713b1edbc | 485 | #define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | #define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 487 | #define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 488 | #define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ |
| AnnaBridge | 171:3a7713b1edbc | 489 | #define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ |
| AnnaBridge | 171:3a7713b1edbc | 490 | #define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 491 | #define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 492 | #define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 493 | #define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ |
| AnnaBridge | 171:3a7713b1edbc | 494 | #define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ |
| AnnaBridge | 171:3a7713b1edbc | 495 | #define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 496 | #define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 497 | #define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 498 | #define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ |
| AnnaBridge | 171:3a7713b1edbc | 499 | #define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ |
| AnnaBridge | 171:3a7713b1edbc | 500 | #define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 501 | #define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 502 | #define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 503 | #define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ |
| AnnaBridge | 171:3a7713b1edbc | 504 | #define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ |
| AnnaBridge | 171:3a7713b1edbc | 505 | #define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 506 | #define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 507 | |
| AnnaBridge | 171:3a7713b1edbc | 508 | /* Bit fields for LEUART IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 509 | #define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 510 | #define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 511 | #define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 512 | #define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ |
| AnnaBridge | 171:3a7713b1edbc | 513 | #define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ |
| AnnaBridge | 171:3a7713b1edbc | 514 | #define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 515 | #define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 516 | #define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 517 | #define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ |
| AnnaBridge | 171:3a7713b1edbc | 518 | #define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ |
| AnnaBridge | 171:3a7713b1edbc | 519 | #define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 520 | #define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 521 | #define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 522 | #define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ |
| AnnaBridge | 171:3a7713b1edbc | 523 | #define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ |
| AnnaBridge | 171:3a7713b1edbc | 524 | #define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 525 | #define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 526 | #define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 527 | #define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 528 | #define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 529 | #define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 530 | #define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 531 | #define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 532 | #define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ |
| AnnaBridge | 171:3a7713b1edbc | 533 | #define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ |
| AnnaBridge | 171:3a7713b1edbc | 534 | #define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 535 | #define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 536 | #define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | #define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 538 | #define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 539 | #define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 540 | #define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | #define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 542 | #define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ |
| AnnaBridge | 171:3a7713b1edbc | 543 | #define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ |
| AnnaBridge | 171:3a7713b1edbc | 544 | #define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 545 | #define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 546 | #define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 547 | #define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ |
| AnnaBridge | 171:3a7713b1edbc | 548 | #define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ |
| AnnaBridge | 171:3a7713b1edbc | 549 | #define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 550 | #define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 551 | #define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 552 | #define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ |
| AnnaBridge | 171:3a7713b1edbc | 553 | #define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ |
| AnnaBridge | 171:3a7713b1edbc | 554 | #define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 555 | #define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 556 | #define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 557 | #define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ |
| AnnaBridge | 171:3a7713b1edbc | 558 | #define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ |
| AnnaBridge | 171:3a7713b1edbc | 559 | #define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 560 | #define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 561 | #define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 562 | #define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ |
| AnnaBridge | 171:3a7713b1edbc | 563 | #define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ |
| AnnaBridge | 171:3a7713b1edbc | 564 | #define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 565 | #define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | |
| AnnaBridge | 171:3a7713b1edbc | 567 | /* Bit fields for LEUART PULSECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 568 | #define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 569 | #define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 570 | #define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */ |
| AnnaBridge | 171:3a7713b1edbc | 571 | #define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */ |
| AnnaBridge | 171:3a7713b1edbc | 572 | #define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 573 | #define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | #define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 575 | #define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */ |
| AnnaBridge | 171:3a7713b1edbc | 576 | #define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */ |
| AnnaBridge | 171:3a7713b1edbc | 577 | #define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 578 | #define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 579 | #define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */ |
| AnnaBridge | 171:3a7713b1edbc | 580 | #define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */ |
| AnnaBridge | 171:3a7713b1edbc | 581 | #define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */ |
| AnnaBridge | 171:3a7713b1edbc | 582 | #define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 583 | #define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 584 | |
| AnnaBridge | 171:3a7713b1edbc | 585 | /* Bit fields for LEUART FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 586 | #define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 587 | #define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 588 | #define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 590 | #define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 591 | #define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 592 | #define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 593 | #define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 594 | #define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 595 | #define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 596 | #define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 597 | |
| AnnaBridge | 171:3a7713b1edbc | 598 | /* Bit fields for LEUART SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 599 | #define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 600 | #define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 601 | #define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 602 | #define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 603 | #define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 604 | #define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 605 | #define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 606 | #define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 607 | #define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 608 | #define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 609 | #define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 610 | #define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 611 | #define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 612 | #define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 613 | #define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 614 | #define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 615 | #define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 616 | #define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 617 | #define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 618 | #define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 619 | #define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 620 | #define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 621 | #define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 622 | #define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 623 | #define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */ |
| AnnaBridge | 171:3a7713b1edbc | 624 | #define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 625 | #define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 626 | #define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 627 | #define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 628 | #define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */ |
| AnnaBridge | 171:3a7713b1edbc | 629 | #define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 630 | #define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 631 | #define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 632 | #define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 633 | #define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */ |
| AnnaBridge | 171:3a7713b1edbc | 634 | #define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 635 | #define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 636 | #define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 637 | #define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 638 | #define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 639 | #define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 640 | #define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 641 | |
| AnnaBridge | 171:3a7713b1edbc | 642 | /* Bit fields for LEUART ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 643 | #define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 644 | #define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 645 | #define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 646 | #define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 647 | #define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 648 | #define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 649 | #define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 650 | #define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 651 | #define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 652 | #define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 653 | #define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 654 | #define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 655 | |
| AnnaBridge | 171:3a7713b1edbc | 656 | /* Bit fields for LEUART ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 657 | #define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 658 | #define _LEUART_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 659 | #define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */ |
| AnnaBridge | 171:3a7713b1edbc | 660 | #define _LEUART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for LEUART_RXLOC */ |
| AnnaBridge | 171:3a7713b1edbc | 661 | #define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 662 | #define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 663 | #define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 664 | #define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 665 | #define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 666 | #define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 667 | #define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 668 | #define _LEUART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 669 | #define _LEUART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 670 | #define _LEUART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 671 | #define _LEUART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 672 | #define _LEUART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 673 | #define _LEUART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 674 | #define _LEUART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 675 | #define _LEUART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 676 | #define _LEUART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 677 | #define _LEUART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 678 | #define _LEUART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 679 | #define _LEUART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 680 | #define _LEUART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 681 | #define _LEUART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 682 | #define _LEUART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 683 | #define _LEUART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 684 | #define _LEUART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 685 | #define _LEUART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 686 | #define _LEUART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 687 | #define _LEUART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 688 | #define _LEUART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 689 | #define _LEUART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 690 | #define _LEUART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 691 | #define _LEUART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 692 | #define _LEUART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 693 | #define _LEUART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 694 | #define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 695 | #define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 696 | #define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 697 | #define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 698 | #define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 699 | #define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 700 | #define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 701 | #define LEUART_ROUTELOC0_RXLOC_LOC6 (_LEUART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 702 | #define LEUART_ROUTELOC0_RXLOC_LOC7 (_LEUART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 703 | #define LEUART_ROUTELOC0_RXLOC_LOC8 (_LEUART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 704 | #define LEUART_ROUTELOC0_RXLOC_LOC9 (_LEUART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 705 | #define LEUART_ROUTELOC0_RXLOC_LOC10 (_LEUART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 706 | #define LEUART_ROUTELOC0_RXLOC_LOC11 (_LEUART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 707 | #define LEUART_ROUTELOC0_RXLOC_LOC12 (_LEUART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 708 | #define LEUART_ROUTELOC0_RXLOC_LOC13 (_LEUART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 709 | #define LEUART_ROUTELOC0_RXLOC_LOC14 (_LEUART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 710 | #define LEUART_ROUTELOC0_RXLOC_LOC15 (_LEUART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 711 | #define LEUART_ROUTELOC0_RXLOC_LOC16 (_LEUART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 712 | #define LEUART_ROUTELOC0_RXLOC_LOC17 (_LEUART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 713 | #define LEUART_ROUTELOC0_RXLOC_LOC18 (_LEUART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 714 | #define LEUART_ROUTELOC0_RXLOC_LOC19 (_LEUART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 715 | #define LEUART_ROUTELOC0_RXLOC_LOC20 (_LEUART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 716 | #define LEUART_ROUTELOC0_RXLOC_LOC21 (_LEUART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 717 | #define LEUART_ROUTELOC0_RXLOC_LOC22 (_LEUART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 718 | #define LEUART_ROUTELOC0_RXLOC_LOC23 (_LEUART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 719 | #define LEUART_ROUTELOC0_RXLOC_LOC24 (_LEUART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 720 | #define LEUART_ROUTELOC0_RXLOC_LOC25 (_LEUART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 721 | #define LEUART_ROUTELOC0_RXLOC_LOC26 (_LEUART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 722 | #define LEUART_ROUTELOC0_RXLOC_LOC27 (_LEUART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 723 | #define LEUART_ROUTELOC0_RXLOC_LOC28 (_LEUART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 724 | #define LEUART_ROUTELOC0_RXLOC_LOC29 (_LEUART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 725 | #define LEUART_ROUTELOC0_RXLOC_LOC30 (_LEUART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 726 | #define LEUART_ROUTELOC0_RXLOC_LOC31 (_LEUART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 727 | #define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */ |
| AnnaBridge | 171:3a7713b1edbc | 728 | #define _LEUART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for LEUART_TXLOC */ |
| AnnaBridge | 171:3a7713b1edbc | 729 | #define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 730 | #define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 731 | #define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 732 | #define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 733 | #define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 734 | #define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 735 | #define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 736 | #define _LEUART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 737 | #define _LEUART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 738 | #define _LEUART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 739 | #define _LEUART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 740 | #define _LEUART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 741 | #define _LEUART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 742 | #define _LEUART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 743 | #define _LEUART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 744 | #define _LEUART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 745 | #define _LEUART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 746 | #define _LEUART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 747 | #define _LEUART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 748 | #define _LEUART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 749 | #define _LEUART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 750 | #define _LEUART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 751 | #define _LEUART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 752 | #define _LEUART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 753 | #define _LEUART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 754 | #define _LEUART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 755 | #define _LEUART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 756 | #define _LEUART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 757 | #define _LEUART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 758 | #define _LEUART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 759 | #define _LEUART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 760 | #define _LEUART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 761 | #define _LEUART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 762 | #define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 763 | #define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 764 | #define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 765 | #define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 766 | #define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 767 | #define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 768 | #define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 769 | #define LEUART_ROUTELOC0_TXLOC_LOC6 (_LEUART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 770 | #define LEUART_ROUTELOC0_TXLOC_LOC7 (_LEUART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 771 | #define LEUART_ROUTELOC0_TXLOC_LOC8 (_LEUART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 772 | #define LEUART_ROUTELOC0_TXLOC_LOC9 (_LEUART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 773 | #define LEUART_ROUTELOC0_TXLOC_LOC10 (_LEUART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 774 | #define LEUART_ROUTELOC0_TXLOC_LOC11 (_LEUART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 775 | #define LEUART_ROUTELOC0_TXLOC_LOC12 (_LEUART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 776 | #define LEUART_ROUTELOC0_TXLOC_LOC13 (_LEUART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 777 | #define LEUART_ROUTELOC0_TXLOC_LOC14 (_LEUART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 778 | #define LEUART_ROUTELOC0_TXLOC_LOC15 (_LEUART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 779 | #define LEUART_ROUTELOC0_TXLOC_LOC16 (_LEUART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 780 | #define LEUART_ROUTELOC0_TXLOC_LOC17 (_LEUART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 781 | #define LEUART_ROUTELOC0_TXLOC_LOC18 (_LEUART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 782 | #define LEUART_ROUTELOC0_TXLOC_LOC19 (_LEUART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 783 | #define LEUART_ROUTELOC0_TXLOC_LOC20 (_LEUART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 784 | #define LEUART_ROUTELOC0_TXLOC_LOC21 (_LEUART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 785 | #define LEUART_ROUTELOC0_TXLOC_LOC22 (_LEUART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 786 | #define LEUART_ROUTELOC0_TXLOC_LOC23 (_LEUART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 787 | #define LEUART_ROUTELOC0_TXLOC_LOC24 (_LEUART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 788 | #define LEUART_ROUTELOC0_TXLOC_LOC25 (_LEUART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 789 | #define LEUART_ROUTELOC0_TXLOC_LOC26 (_LEUART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 790 | #define LEUART_ROUTELOC0_TXLOC_LOC27 (_LEUART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 791 | #define LEUART_ROUTELOC0_TXLOC_LOC28 (_LEUART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 792 | #define LEUART_ROUTELOC0_TXLOC_LOC29 (_LEUART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 793 | #define LEUART_ROUTELOC0_TXLOC_LOC30 (_LEUART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 794 | #define LEUART_ROUTELOC0_TXLOC_LOC31 (_LEUART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ |
| AnnaBridge | 171:3a7713b1edbc | 795 | |
| AnnaBridge | 171:3a7713b1edbc | 796 | /* Bit fields for LEUART INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 797 | #define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 798 | #define _LEUART_INPUT_MASK 0x0000002FUL /**< Mask for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 799 | #define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 800 | #define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 801 | #define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 802 | #define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 803 | #define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 804 | #define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 805 | #define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 806 | #define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 807 | #define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 808 | #define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 809 | #define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 810 | #define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 811 | #define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 812 | #define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 813 | #define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 814 | #define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 815 | #define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 816 | #define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 817 | #define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 818 | #define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 819 | #define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 820 | #define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 821 | #define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 822 | #define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 823 | #define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 824 | #define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 825 | #define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 826 | #define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 827 | #define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 828 | #define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */ |
| AnnaBridge | 171:3a7713b1edbc | 829 | #define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */ |
| AnnaBridge | 171:3a7713b1edbc | 830 | #define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 831 | #define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 832 | |
| AnnaBridge | 171:3a7713b1edbc | 833 | /** @} End of group EFM32PG1B_LEUART */ |
| AnnaBridge | 171:3a7713b1edbc | 834 | /** @} End of group Parts */ |
| AnnaBridge | 171:3a7713b1edbc | 835 |
