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TARGET_EFM32LG_STK3600/TOOLCHAIN_GCC_ARM/efm32lg_ebi.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32lg_ebi.h |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @brief EFM32LG_EBI register and bit field definitions |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @version 5.1.2 |
| AnnaBridge | 171:3a7713b1edbc | 5 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 6 | * @section License |
| AnnaBridge | 171:3a7713b1edbc | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 9 | * |
| AnnaBridge | 171:3a7713b1edbc | 10 | * Permission is granted to anyone to use this software for any purpose, |
| AnnaBridge | 171:3a7713b1edbc | 11 | * including commercial applications, and to alter it and redistribute it |
| AnnaBridge | 171:3a7713b1edbc | 12 | * freely, subject to the following restrictions: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * |
| AnnaBridge | 171:3a7713b1edbc | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| AnnaBridge | 171:3a7713b1edbc | 15 | * claim that you wrote the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| AnnaBridge | 171:3a7713b1edbc | 17 | * misrepresented as being the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| AnnaBridge | 171:3a7713b1edbc | 19 | * |
| AnnaBridge | 171:3a7713b1edbc | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| AnnaBridge | 171:3a7713b1edbc | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| AnnaBridge | 171:3a7713b1edbc | 23 | * kind, including, but not limited to, any implied warranties of |
| AnnaBridge | 171:3a7713b1edbc | 24 | * merchantability or fitness for any particular purpose or warranties against |
| AnnaBridge | 171:3a7713b1edbc | 25 | * infringement of any proprietary rights of a third party. |
| AnnaBridge | 171:3a7713b1edbc | 26 | * |
| AnnaBridge | 171:3a7713b1edbc | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| AnnaBridge | 171:3a7713b1edbc | 29 | * any third party, arising from your use of this Software. |
| AnnaBridge | 171:3a7713b1edbc | 30 | * |
| AnnaBridge | 171:3a7713b1edbc | 31 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 32 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 33 | * @addtogroup Parts |
| AnnaBridge | 171:3a7713b1edbc | 34 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 35 | ******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 36 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 37 | * @defgroup EFM32LG_EBI |
| AnnaBridge | 171:3a7713b1edbc | 38 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 39 | * @brief EFM32LG_EBI Register Declaration |
| AnnaBridge | 171:3a7713b1edbc | 40 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 41 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 42 | { |
| AnnaBridge | 171:3a7713b1edbc | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 44 | __IOM uint32_t ADDRTIMING; /**< Address Timing Register */ |
| AnnaBridge | 171:3a7713b1edbc | 45 | __IOM uint32_t RDTIMING; /**< Read Timing Register */ |
| AnnaBridge | 171:3a7713b1edbc | 46 | __IOM uint32_t WRTIMING; /**< Write Timing Register */ |
| AnnaBridge | 171:3a7713b1edbc | 47 | __IOM uint32_t POLARITY; /**< Polarity Register */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | __IOM uint32_t ROUTE; /**< I/O Routing Register */ |
| AnnaBridge | 171:3a7713b1edbc | 49 | __IOM uint32_t ADDRTIMING1; /**< Address Timing Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | __IOM uint32_t RDTIMING1; /**< Read Timing Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 51 | __IOM uint32_t WRTIMING1; /**< Write Timing Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | __IOM uint32_t POLARITY1; /**< Polarity Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | __IOM uint32_t ADDRTIMING2; /**< Address Timing Register 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | __IOM uint32_t RDTIMING2; /**< Read Timing Register 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | __IOM uint32_t WRTIMING2; /**< Write Timing Register 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | __IOM uint32_t POLARITY2; /**< Polarity Register 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | __IOM uint32_t ADDRTIMING3; /**< Address Timing Register 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 58 | __IOM uint32_t RDTIMING3; /**< Read Timing Register 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | __IOM uint32_t WRTIMING3; /**< Write Timing Register 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | __IOM uint32_t POLARITY3; /**< Polarity Register 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | __IOM uint32_t PAGECTRL; /**< Page Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | __IOM uint32_t NANDCTRL; /**< NAND Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | __IOM uint32_t CMD; /**< Command Register */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | __IM uint32_t STATUS; /**< Status Register */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | __IM uint32_t ECCPARITY; /**< ECC Parity register */ |
| AnnaBridge | 171:3a7713b1edbc | 66 | __IOM uint32_t TFTCTRL; /**< TFT Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | __IM uint32_t TFTSTATUS; /**< TFT Status Register */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | __IOM uint32_t TFTFRAMEBASE; /**< TFT Frame Base Register */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | __IOM uint32_t TFTSTRIDE; /**< TFT Stride Register */ |
| AnnaBridge | 171:3a7713b1edbc | 70 | __IOM uint32_t TFTSIZE; /**< TFT Size Register */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | __IOM uint32_t TFTHPORCH; /**< TFT Horizontal Porch Register */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | __IOM uint32_t TFTVPORCH; /**< TFT Vertical Porch Register */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | __IOM uint32_t TFTTIMING; /**< TFT Timing Register */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | __IOM uint32_t TFTPOLARITY; /**< TFT Polarity Register */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | __IOM uint32_t TFTDD; /**< TFT Direct Drive Data Register */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | __IOM uint32_t TFTALPHA; /**< TFT Alpha Blending Register */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | __IOM uint32_t TFTPIXEL0; /**< TFT Pixel 0 Register */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | __IOM uint32_t TFTPIXEL1; /**< TFT Pixel 1 Register */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | __IM uint32_t TFTPIXEL; /**< TFT Alpha Blending Result Pixel Register */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | __IOM uint32_t TFTMASK; /**< TFT Masking Register */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | } EBI_TypeDef; /** @} */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | |
| AnnaBridge | 171:3a7713b1edbc | 87 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 88 | * @defgroup EFM32LG_EBI_BitFields |
| AnnaBridge | 171:3a7713b1edbc | 89 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 90 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 91 | |
| AnnaBridge | 171:3a7713b1edbc | 92 | /* Bit fields for EBI CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define _EBI_CTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define _EBI_CTRL_MASK 0xCFFFFFFFUL /**< Mask for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define _EBI_CTRL_MODE_SHIFT 0 /**< Shift value for EBI_MODE */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define _EBI_CTRL_MODE_MASK 0x3UL /**< Bit mask for EBI_MODE */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define _EBI_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define _EBI_CTRL_MODE_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define _EBI_CTRL_MODE_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define _EBI_CTRL_MODE_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define _EBI_CTRL_MODE_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define EBI_CTRL_MODE_DEFAULT (_EBI_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define EBI_CTRL_MODE_D8A8 (_EBI_CTRL_MODE_D8A8 << 0) /**< Shifted mode D8A8 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define EBI_CTRL_MODE_D16A16ALE (_EBI_CTRL_MODE_D16A16ALE << 0) /**< Shifted mode D16A16ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define EBI_CTRL_MODE_D8A24ALE (_EBI_CTRL_MODE_D8A24ALE << 0) /**< Shifted mode D8A24ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define EBI_CTRL_MODE_D16 (_EBI_CTRL_MODE_D16 << 0) /**< Shifted mode D16 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define _EBI_CTRL_MODE1_SHIFT 2 /**< Shift value for EBI_MODE1 */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define _EBI_CTRL_MODE1_MASK 0xCUL /**< Bit mask for EBI_MODE1 */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define _EBI_CTRL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | #define _EBI_CTRL_MODE1_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | #define _EBI_CTRL_MODE1_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define _EBI_CTRL_MODE1_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define _EBI_CTRL_MODE1_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define EBI_CTRL_MODE1_DEFAULT (_EBI_CTRL_MODE1_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define EBI_CTRL_MODE1_D8A8 (_EBI_CTRL_MODE1_D8A8 << 2) /**< Shifted mode D8A8 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define EBI_CTRL_MODE1_D16A16ALE (_EBI_CTRL_MODE1_D16A16ALE << 2) /**< Shifted mode D16A16ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define EBI_CTRL_MODE1_D8A24ALE (_EBI_CTRL_MODE1_D8A24ALE << 2) /**< Shifted mode D8A24ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define EBI_CTRL_MODE1_D16 (_EBI_CTRL_MODE1_D16 << 2) /**< Shifted mode D16 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define _EBI_CTRL_MODE2_SHIFT 4 /**< Shift value for EBI_MODE2 */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define _EBI_CTRL_MODE2_MASK 0x30UL /**< Bit mask for EBI_MODE2 */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define _EBI_CTRL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define _EBI_CTRL_MODE2_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define _EBI_CTRL_MODE2_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define _EBI_CTRL_MODE2_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define _EBI_CTRL_MODE2_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define EBI_CTRL_MODE2_DEFAULT (_EBI_CTRL_MODE2_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define EBI_CTRL_MODE2_D8A8 (_EBI_CTRL_MODE2_D8A8 << 4) /**< Shifted mode D8A8 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define EBI_CTRL_MODE2_D16A16ALE (_EBI_CTRL_MODE2_D16A16ALE << 4) /**< Shifted mode D16A16ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define EBI_CTRL_MODE2_D8A24ALE (_EBI_CTRL_MODE2_D8A24ALE << 4) /**< Shifted mode D8A24ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define EBI_CTRL_MODE2_D16 (_EBI_CTRL_MODE2_D16 << 4) /**< Shifted mode D16 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define _EBI_CTRL_MODE3_SHIFT 6 /**< Shift value for EBI_MODE3 */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define _EBI_CTRL_MODE3_MASK 0xC0UL /**< Bit mask for EBI_MODE3 */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define _EBI_CTRL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define _EBI_CTRL_MODE3_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define _EBI_CTRL_MODE3_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define _EBI_CTRL_MODE3_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define _EBI_CTRL_MODE3_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define EBI_CTRL_MODE3_DEFAULT (_EBI_CTRL_MODE3_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | #define EBI_CTRL_MODE3_D8A8 (_EBI_CTRL_MODE3_D8A8 << 6) /**< Shifted mode D8A8 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define EBI_CTRL_MODE3_D16A16ALE (_EBI_CTRL_MODE3_D16A16ALE << 6) /**< Shifted mode D16A16ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define EBI_CTRL_MODE3_D8A24ALE (_EBI_CTRL_MODE3_D8A24ALE << 6) /**< Shifted mode D8A24ALE for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define EBI_CTRL_MODE3_D16 (_EBI_CTRL_MODE3_D16 << 6) /**< Shifted mode D16 for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define EBI_CTRL_BANK0EN (0x1UL << 8) /**< Bank 0 Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define _EBI_CTRL_BANK0EN_SHIFT 8 /**< Shift value for EBI_BANK0EN */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define _EBI_CTRL_BANK0EN_MASK 0x100UL /**< Bit mask for EBI_BANK0EN */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define _EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define EBI_CTRL_BANK0EN_DEFAULT (_EBI_CTRL_BANK0EN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define EBI_CTRL_BANK1EN (0x1UL << 9) /**< Bank 1 Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define _EBI_CTRL_BANK1EN_SHIFT 9 /**< Shift value for EBI_BANK1EN */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define _EBI_CTRL_BANK1EN_MASK 0x200UL /**< Bit mask for EBI_BANK1EN */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define _EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define EBI_CTRL_BANK1EN_DEFAULT (_EBI_CTRL_BANK1EN_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define EBI_CTRL_BANK2EN (0x1UL << 10) /**< Bank 2 Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define _EBI_CTRL_BANK2EN_SHIFT 10 /**< Shift value for EBI_BANK2EN */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define _EBI_CTRL_BANK2EN_MASK 0x400UL /**< Bit mask for EBI_BANK2EN */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define _EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define EBI_CTRL_BANK2EN_DEFAULT (_EBI_CTRL_BANK2EN_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define EBI_CTRL_BANK3EN (0x1UL << 11) /**< Bank 3 Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define _EBI_CTRL_BANK3EN_SHIFT 11 /**< Shift value for EBI_BANK3EN */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define _EBI_CTRL_BANK3EN_MASK 0x800UL /**< Bit mask for EBI_BANK3EN */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define _EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define EBI_CTRL_BANK3EN_DEFAULT (_EBI_CTRL_BANK3EN_DEFAULT << 11) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define EBI_CTRL_NOIDLE (0x1UL << 12) /**< No idle cycle insertion on bank 0. */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define _EBI_CTRL_NOIDLE_SHIFT 12 /**< Shift value for EBI_NOIDLE */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define _EBI_CTRL_NOIDLE_MASK 0x1000UL /**< Bit mask for EBI_NOIDLE */ |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define _EBI_CTRL_NOIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define EBI_CTRL_NOIDLE_DEFAULT (_EBI_CTRL_NOIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define EBI_CTRL_NOIDLE1 (0x1UL << 13) /**< No idle cycle insertion on bank 1. */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define _EBI_CTRL_NOIDLE1_SHIFT 13 /**< Shift value for EBI_NOIDLE1 */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define _EBI_CTRL_NOIDLE1_MASK 0x2000UL /**< Bit mask for EBI_NOIDLE1 */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define _EBI_CTRL_NOIDLE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define EBI_CTRL_NOIDLE1_DEFAULT (_EBI_CTRL_NOIDLE1_DEFAULT << 13) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define EBI_CTRL_NOIDLE2 (0x1UL << 14) /**< No idle cycle insertion on bank 2. */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define _EBI_CTRL_NOIDLE2_SHIFT 14 /**< Shift value for EBI_NOIDLE2 */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define _EBI_CTRL_NOIDLE2_MASK 0x4000UL /**< Bit mask for EBI_NOIDLE2 */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define _EBI_CTRL_NOIDLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define EBI_CTRL_NOIDLE2_DEFAULT (_EBI_CTRL_NOIDLE2_DEFAULT << 14) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define EBI_CTRL_NOIDLE3 (0x1UL << 15) /**< No idle cycle insertion on bank 3. */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define _EBI_CTRL_NOIDLE3_SHIFT 15 /**< Shift value for EBI_NOIDLE3 */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define _EBI_CTRL_NOIDLE3_MASK 0x8000UL /**< Bit mask for EBI_NOIDLE3 */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define _EBI_CTRL_NOIDLE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define EBI_CTRL_NOIDLE3_DEFAULT (_EBI_CTRL_NOIDLE3_DEFAULT << 15) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define EBI_CTRL_ARDYEN (0x1UL << 16) /**< ARDY Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define _EBI_CTRL_ARDYEN_SHIFT 16 /**< Shift value for EBI_ARDYEN */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define _EBI_CTRL_ARDYEN_MASK 0x10000UL /**< Bit mask for EBI_ARDYEN */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define _EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define EBI_CTRL_ARDYEN_DEFAULT (_EBI_CTRL_ARDYEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define EBI_CTRL_ARDYTODIS (0x1UL << 17) /**< ARDY Timeout Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define _EBI_CTRL_ARDYTODIS_SHIFT 17 /**< Shift value for EBI_ARDYTODIS */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define _EBI_CTRL_ARDYTODIS_MASK 0x20000UL /**< Bit mask for EBI_ARDYTODIS */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define _EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define EBI_CTRL_ARDYTODIS_DEFAULT (_EBI_CTRL_ARDYTODIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define EBI_CTRL_ARDY1EN (0x1UL << 18) /**< ARDY Enable for bank 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define _EBI_CTRL_ARDY1EN_SHIFT 18 /**< Shift value for EBI_ARDY1EN */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | #define _EBI_CTRL_ARDY1EN_MASK 0x40000UL /**< Bit mask for EBI_ARDY1EN */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define _EBI_CTRL_ARDY1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define EBI_CTRL_ARDY1EN_DEFAULT (_EBI_CTRL_ARDY1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define EBI_CTRL_ARDYTO1DIS (0x1UL << 19) /**< ARDY Timeout Disable for bank 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define _EBI_CTRL_ARDYTO1DIS_SHIFT 19 /**< Shift value for EBI_ARDYTO1DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define _EBI_CTRL_ARDYTO1DIS_MASK 0x80000UL /**< Bit mask for EBI_ARDYTO1DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define _EBI_CTRL_ARDYTO1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define EBI_CTRL_ARDYTO1DIS_DEFAULT (_EBI_CTRL_ARDYTO1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define EBI_CTRL_ARDY2EN (0x1UL << 20) /**< ARDY Enable for bank 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define _EBI_CTRL_ARDY2EN_SHIFT 20 /**< Shift value for EBI_ARDY2EN */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define _EBI_CTRL_ARDY2EN_MASK 0x100000UL /**< Bit mask for EBI_ARDY2EN */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define _EBI_CTRL_ARDY2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define EBI_CTRL_ARDY2EN_DEFAULT (_EBI_CTRL_ARDY2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define EBI_CTRL_ARDYTO2DIS (0x1UL << 21) /**< ARDY Timeout Disable for bank 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define _EBI_CTRL_ARDYTO2DIS_SHIFT 21 /**< Shift value for EBI_ARDYTO2DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define _EBI_CTRL_ARDYTO2DIS_MASK 0x200000UL /**< Bit mask for EBI_ARDYTO2DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define _EBI_CTRL_ARDYTO2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define EBI_CTRL_ARDYTO2DIS_DEFAULT (_EBI_CTRL_ARDYTO2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define EBI_CTRL_ARDY3EN (0x1UL << 22) /**< ARDY Enable for bank 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define _EBI_CTRL_ARDY3EN_SHIFT 22 /**< Shift value for EBI_ARDY3EN */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define _EBI_CTRL_ARDY3EN_MASK 0x400000UL /**< Bit mask for EBI_ARDY3EN */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define _EBI_CTRL_ARDY3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define EBI_CTRL_ARDY3EN_DEFAULT (_EBI_CTRL_ARDY3EN_DEFAULT << 22) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define EBI_CTRL_ARDYTO3DIS (0x1UL << 23) /**< ARDY Timeout Disable for bank 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define _EBI_CTRL_ARDYTO3DIS_SHIFT 23 /**< Shift value for EBI_ARDYTO3DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define _EBI_CTRL_ARDYTO3DIS_MASK 0x800000UL /**< Bit mask for EBI_ARDYTO3DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define _EBI_CTRL_ARDYTO3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define EBI_CTRL_ARDYTO3DIS_DEFAULT (_EBI_CTRL_ARDYTO3DIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define EBI_CTRL_BL (0x1UL << 24) /**< Byte Lane Enable for bank 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define _EBI_CTRL_BL_SHIFT 24 /**< Shift value for EBI_BL */ |
| AnnaBridge | 171:3a7713b1edbc | 225 | #define _EBI_CTRL_BL_MASK 0x1000000UL /**< Bit mask for EBI_BL */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define _EBI_CTRL_BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define EBI_CTRL_BL_DEFAULT (_EBI_CTRL_BL_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define EBI_CTRL_BL1 (0x1UL << 25) /**< Byte Lane Enable for bank 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define _EBI_CTRL_BL1_SHIFT 25 /**< Shift value for EBI_BL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define _EBI_CTRL_BL1_MASK 0x2000000UL /**< Bit mask for EBI_BL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define _EBI_CTRL_BL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define EBI_CTRL_BL1_DEFAULT (_EBI_CTRL_BL1_DEFAULT << 25) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define EBI_CTRL_BL2 (0x1UL << 26) /**< Byte Lane Enable for bank 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define _EBI_CTRL_BL2_SHIFT 26 /**< Shift value for EBI_BL2 */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define _EBI_CTRL_BL2_MASK 0x4000000UL /**< Bit mask for EBI_BL2 */ |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define _EBI_CTRL_BL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define EBI_CTRL_BL2_DEFAULT (_EBI_CTRL_BL2_DEFAULT << 26) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define EBI_CTRL_BL3 (0x1UL << 27) /**< Byte Lane Enable for bank 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define _EBI_CTRL_BL3_SHIFT 27 /**< Shift value for EBI_BL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define _EBI_CTRL_BL3_MASK 0x8000000UL /**< Bit mask for EBI_BL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define _EBI_CTRL_BL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define EBI_CTRL_BL3_DEFAULT (_EBI_CTRL_BL3_DEFAULT << 27) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define EBI_CTRL_ITS (0x1UL << 30) /**< Individual Timing Set, Line Polarity and Mode Definition Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define _EBI_CTRL_ITS_SHIFT 30 /**< Shift value for EBI_ITS */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define _EBI_CTRL_ITS_MASK 0x40000000UL /**< Bit mask for EBI_ITS */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define _EBI_CTRL_ITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define EBI_CTRL_ITS_DEFAULT (_EBI_CTRL_ITS_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define EBI_CTRL_ALTMAP (0x1UL << 31) /**< Alternative Address Map Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define _EBI_CTRL_ALTMAP_SHIFT 31 /**< Shift value for EBI_ALTMAP */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define _EBI_CTRL_ALTMAP_MASK 0x80000000UL /**< Bit mask for EBI_ALTMAP */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define _EBI_CTRL_ALTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define EBI_CTRL_ALTMAP_DEFAULT (_EBI_CTRL_ALTMAP_DEFAULT << 31) /**< Shifted mode DEFAULT for EBI_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | |
| AnnaBridge | 171:3a7713b1edbc | 254 | /* Bit fields for EBI ADDRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define _EBI_ADDRTIMING_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define _EBI_ADDRTIMING_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define _EBI_ADDRTIMING_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define _EBI_ADDRTIMING_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define _EBI_ADDRTIMING_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define EBI_ADDRTIMING_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define _EBI_ADDRTIMING_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define _EBI_ADDRTIMING_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define _EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define EBI_ADDRTIMING_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define EBI_ADDRTIMING_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define _EBI_ADDRTIMING_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define _EBI_ADDRTIMING_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define _EBI_ADDRTIMING_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define EBI_ADDRTIMING_HALFALE_DEFAULT (_EBI_ADDRTIMING_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | |
| AnnaBridge | 171:3a7713b1edbc | 271 | /* Bit fields for EBI RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define _EBI_RDTIMING_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define _EBI_RDTIMING_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define _EBI_RDTIMING_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define _EBI_RDTIMING_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define _EBI_RDTIMING_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define EBI_RDTIMING_RDSETUP_DEFAULT (_EBI_RDTIMING_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define _EBI_RDTIMING_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define _EBI_RDTIMING_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define _EBI_RDTIMING_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define EBI_RDTIMING_RDSTRB_DEFAULT (_EBI_RDTIMING_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define _EBI_RDTIMING_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define _EBI_RDTIMING_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define _EBI_RDTIMING_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define EBI_RDTIMING_RDHOLD_DEFAULT (_EBI_RDTIMING_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define EBI_RDTIMING_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define _EBI_RDTIMING_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define _EBI_RDTIMING_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define _EBI_RDTIMING_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define EBI_RDTIMING_HALFRE_DEFAULT (_EBI_RDTIMING_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define EBI_RDTIMING_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define _EBI_RDTIMING_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define _EBI_RDTIMING_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define _EBI_RDTIMING_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define EBI_RDTIMING_PREFETCH_DEFAULT (_EBI_RDTIMING_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define EBI_RDTIMING_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define _EBI_RDTIMING_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define _EBI_RDTIMING_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define _EBI_RDTIMING_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define EBI_RDTIMING_PAGEMODE_DEFAULT (_EBI_RDTIMING_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | |
| AnnaBridge | 171:3a7713b1edbc | 302 | /* Bit fields for EBI WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define _EBI_WRTIMING_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define _EBI_WRTIMING_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define _EBI_WRTIMING_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define _EBI_WRTIMING_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define _EBI_WRTIMING_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define EBI_WRTIMING_WRSETUP_DEFAULT (_EBI_WRTIMING_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define _EBI_WRTIMING_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define _EBI_WRTIMING_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define _EBI_WRTIMING_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define EBI_WRTIMING_WRSTRB_DEFAULT (_EBI_WRTIMING_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define _EBI_WRTIMING_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define _EBI_WRTIMING_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define _EBI_WRTIMING_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define EBI_WRTIMING_WRHOLD_DEFAULT (_EBI_WRTIMING_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define EBI_WRTIMING_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define _EBI_WRTIMING_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define _EBI_WRTIMING_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define _EBI_WRTIMING_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define EBI_WRTIMING_HALFWE_DEFAULT (_EBI_WRTIMING_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define EBI_WRTIMING_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | #define _EBI_WRTIMING_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 324 | #define _EBI_WRTIMING_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define _EBI_WRTIMING_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define EBI_WRTIMING_WBUFDIS_DEFAULT (_EBI_WRTIMING_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | |
| AnnaBridge | 171:3a7713b1edbc | 328 | /* Bit fields for EBI POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define _EBI_POLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 330 | #define _EBI_POLARITY_MASK 0x0000003FUL /**< Mask for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 331 | #define EBI_POLARITY_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define _EBI_POLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define _EBI_POLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define _EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define _EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define _EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define EBI_POLARITY_CSPOL_DEFAULT (_EBI_POLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define EBI_POLARITY_CSPOL_ACTIVELOW (_EBI_POLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define EBI_POLARITY_CSPOL_ACTIVEHIGH (_EBI_POLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define EBI_POLARITY_REPOL (0x1UL << 1) /**< Read Enable Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define _EBI_POLARITY_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | #define _EBI_POLARITY_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define _EBI_POLARITY_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define _EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define _EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define EBI_POLARITY_REPOL_DEFAULT (_EBI_POLARITY_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define EBI_POLARITY_REPOL_ACTIVELOW (_EBI_POLARITY_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define EBI_POLARITY_REPOL_ACTIVEHIGH (_EBI_POLARITY_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define EBI_POLARITY_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define _EBI_POLARITY_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define _EBI_POLARITY_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define _EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define _EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define _EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define EBI_POLARITY_WEPOL_DEFAULT (_EBI_POLARITY_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define EBI_POLARITY_WEPOL_ACTIVELOW (_EBI_POLARITY_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define EBI_POLARITY_WEPOL_ACTIVEHIGH (_EBI_POLARITY_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define EBI_POLARITY_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define _EBI_POLARITY_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define _EBI_POLARITY_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define _EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define _EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define _EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define EBI_POLARITY_ALEPOL_DEFAULT (_EBI_POLARITY_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define EBI_POLARITY_ALEPOL_ACTIVELOW (_EBI_POLARITY_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define EBI_POLARITY_ALEPOL_ACTIVEHIGH (_EBI_POLARITY_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define EBI_POLARITY_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define _EBI_POLARITY_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define _EBI_POLARITY_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define _EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define _EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define _EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | #define EBI_POLARITY_ARDYPOL_DEFAULT (_EBI_POLARITY_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 374 | #define EBI_POLARITY_ARDYPOL_ACTIVELOW (_EBI_POLARITY_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define EBI_POLARITY_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define EBI_POLARITY_BLPOL (0x1UL << 5) /**< BL Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | #define _EBI_POLARITY_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define _EBI_POLARITY_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define _EBI_POLARITY_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define _EBI_POLARITY_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define _EBI_POLARITY_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define EBI_POLARITY_BLPOL_DEFAULT (_EBI_POLARITY_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define EBI_POLARITY_BLPOL_ACTIVELOW (_EBI_POLARITY_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define EBI_POLARITY_BLPOL_ACTIVEHIGH (_EBI_POLARITY_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | |
| AnnaBridge | 171:3a7713b1edbc | 386 | /* Bit fields for EBI ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define _EBI_ROUTE_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define _EBI_ROUTE_MASK 0x777F10FFUL /**< Mask for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define EBI_ROUTE_EBIPEN (0x1UL << 0) /**< EBI Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define _EBI_ROUTE_EBIPEN_SHIFT 0 /**< Shift value for EBI_EBIPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define _EBI_ROUTE_EBIPEN_MASK 0x1UL /**< Bit mask for EBI_EBIPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 392 | #define _EBI_ROUTE_EBIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | #define EBI_ROUTE_EBIPEN_DEFAULT (_EBI_ROUTE_EBIPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define EBI_ROUTE_CS0PEN (0x1UL << 1) /**< EBI_CS0 Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define _EBI_ROUTE_CS0PEN_SHIFT 1 /**< Shift value for EBI_CS0PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define _EBI_ROUTE_CS0PEN_MASK 0x2UL /**< Bit mask for EBI_CS0PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define _EBI_ROUTE_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define EBI_ROUTE_CS0PEN_DEFAULT (_EBI_ROUTE_CS0PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define EBI_ROUTE_CS1PEN (0x1UL << 2) /**< EBI_CS1 Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define _EBI_ROUTE_CS1PEN_SHIFT 2 /**< Shift value for EBI_CS1PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define _EBI_ROUTE_CS1PEN_MASK 0x4UL /**< Bit mask for EBI_CS1PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define _EBI_ROUTE_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define EBI_ROUTE_CS1PEN_DEFAULT (_EBI_ROUTE_CS1PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define EBI_ROUTE_CS2PEN (0x1UL << 3) /**< EBI_CS2 Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define _EBI_ROUTE_CS2PEN_SHIFT 3 /**< Shift value for EBI_CS2PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define _EBI_ROUTE_CS2PEN_MASK 0x8UL /**< Bit mask for EBI_CS2PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define _EBI_ROUTE_CS2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define EBI_ROUTE_CS2PEN_DEFAULT (_EBI_ROUTE_CS2PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 409 | #define EBI_ROUTE_CS3PEN (0x1UL << 4) /**< EBI_CS3 Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 410 | #define _EBI_ROUTE_CS3PEN_SHIFT 4 /**< Shift value for EBI_CS3PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define _EBI_ROUTE_CS3PEN_MASK 0x10UL /**< Bit mask for EBI_CS3PEN */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define _EBI_ROUTE_CS3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define EBI_ROUTE_CS3PEN_DEFAULT (_EBI_ROUTE_CS3PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define EBI_ROUTE_ALEPEN (0x1UL << 5) /**< EBI_ALE Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define _EBI_ROUTE_ALEPEN_SHIFT 5 /**< Shift value for EBI_ALEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define _EBI_ROUTE_ALEPEN_MASK 0x20UL /**< Bit mask for EBI_ALEPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define _EBI_ROUTE_ALEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | #define EBI_ROUTE_ALEPEN_DEFAULT (_EBI_ROUTE_ALEPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define EBI_ROUTE_ARDYPEN (0x1UL << 6) /**< EBI_ARDY Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | #define _EBI_ROUTE_ARDYPEN_SHIFT 6 /**< Shift value for EBI_ARDYPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 421 | #define _EBI_ROUTE_ARDYPEN_MASK 0x40UL /**< Bit mask for EBI_ARDYPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 422 | #define _EBI_ROUTE_ARDYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 423 | #define EBI_ROUTE_ARDYPEN_DEFAULT (_EBI_ROUTE_ARDYPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 424 | #define EBI_ROUTE_BLPEN (0x1UL << 7) /**< EBI_BL[1:0] Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 425 | #define _EBI_ROUTE_BLPEN_SHIFT 7 /**< Shift value for EBI_BLPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 426 | #define _EBI_ROUTE_BLPEN_MASK 0x80UL /**< Bit mask for EBI_BLPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 427 | #define _EBI_ROUTE_BLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 428 | #define EBI_ROUTE_BLPEN_DEFAULT (_EBI_ROUTE_BLPEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define EBI_ROUTE_NANDPEN (0x1UL << 12) /**< NANDRE and NANDWE Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 430 | #define _EBI_ROUTE_NANDPEN_SHIFT 12 /**< Shift value for EBI_NANDPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | #define _EBI_ROUTE_NANDPEN_MASK 0x1000UL /**< Bit mask for EBI_NANDPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 432 | #define _EBI_ROUTE_NANDPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 433 | #define EBI_ROUTE_NANDPEN_DEFAULT (_EBI_ROUTE_NANDPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 434 | #define _EBI_ROUTE_ALB_SHIFT 16 /**< Shift value for EBI_ALB */ |
| AnnaBridge | 171:3a7713b1edbc | 435 | #define _EBI_ROUTE_ALB_MASK 0x30000UL /**< Bit mask for EBI_ALB */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | #define _EBI_ROUTE_ALB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 437 | #define _EBI_ROUTE_ALB_A0 0x00000000UL /**< Mode A0 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | #define _EBI_ROUTE_ALB_A8 0x00000001UL /**< Mode A8 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 439 | #define _EBI_ROUTE_ALB_A16 0x00000002UL /**< Mode A16 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define _EBI_ROUTE_ALB_A24 0x00000003UL /**< Mode A24 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define EBI_ROUTE_ALB_DEFAULT (_EBI_ROUTE_ALB_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 442 | #define EBI_ROUTE_ALB_A0 (_EBI_ROUTE_ALB_A0 << 16) /**< Shifted mode A0 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define EBI_ROUTE_ALB_A8 (_EBI_ROUTE_ALB_A8 << 16) /**< Shifted mode A8 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 444 | #define EBI_ROUTE_ALB_A16 (_EBI_ROUTE_ALB_A16 << 16) /**< Shifted mode A16 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 445 | #define EBI_ROUTE_ALB_A24 (_EBI_ROUTE_ALB_A24 << 16) /**< Shifted mode A24 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 446 | #define _EBI_ROUTE_APEN_SHIFT 18 /**< Shift value for EBI_APEN */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | #define _EBI_ROUTE_APEN_MASK 0x7C0000UL /**< Bit mask for EBI_APEN */ |
| AnnaBridge | 171:3a7713b1edbc | 448 | #define _EBI_ROUTE_APEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 449 | #define _EBI_ROUTE_APEN_A0 0x00000000UL /**< Mode A0 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define _EBI_ROUTE_APEN_A5 0x00000005UL /**< Mode A5 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define _EBI_ROUTE_APEN_A6 0x00000006UL /**< Mode A6 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define _EBI_ROUTE_APEN_A7 0x00000007UL /**< Mode A7 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define _EBI_ROUTE_APEN_A8 0x00000008UL /**< Mode A8 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 454 | #define _EBI_ROUTE_APEN_A9 0x00000009UL /**< Mode A9 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define _EBI_ROUTE_APEN_A10 0x0000000AUL /**< Mode A10 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 456 | #define _EBI_ROUTE_APEN_A11 0x0000000BUL /**< Mode A11 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 457 | #define _EBI_ROUTE_APEN_A12 0x0000000CUL /**< Mode A12 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 458 | #define _EBI_ROUTE_APEN_A13 0x0000000DUL /**< Mode A13 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 459 | #define _EBI_ROUTE_APEN_A14 0x0000000EUL /**< Mode A14 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 460 | #define _EBI_ROUTE_APEN_A15 0x0000000FUL /**< Mode A15 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 461 | #define _EBI_ROUTE_APEN_A16 0x00000010UL /**< Mode A16 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define _EBI_ROUTE_APEN_A17 0x00000011UL /**< Mode A17 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define _EBI_ROUTE_APEN_A18 0x00000012UL /**< Mode A18 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define _EBI_ROUTE_APEN_A19 0x00000013UL /**< Mode A19 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 465 | #define _EBI_ROUTE_APEN_A20 0x00000014UL /**< Mode A20 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 466 | #define _EBI_ROUTE_APEN_A21 0x00000015UL /**< Mode A21 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 467 | #define _EBI_ROUTE_APEN_A22 0x00000016UL /**< Mode A22 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 468 | #define _EBI_ROUTE_APEN_A23 0x00000017UL /**< Mode A23 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 469 | #define _EBI_ROUTE_APEN_A24 0x00000018UL /**< Mode A24 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 470 | #define _EBI_ROUTE_APEN_A25 0x00000019UL /**< Mode A25 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 471 | #define _EBI_ROUTE_APEN_A26 0x0000001AUL /**< Mode A26 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 472 | #define _EBI_ROUTE_APEN_A27 0x0000001BUL /**< Mode A27 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 473 | #define _EBI_ROUTE_APEN_A28 0x0000001CUL /**< Mode A28 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 474 | #define EBI_ROUTE_APEN_DEFAULT (_EBI_ROUTE_APEN_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 475 | #define EBI_ROUTE_APEN_A0 (_EBI_ROUTE_APEN_A0 << 18) /**< Shifted mode A0 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 476 | #define EBI_ROUTE_APEN_A5 (_EBI_ROUTE_APEN_A5 << 18) /**< Shifted mode A5 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 477 | #define EBI_ROUTE_APEN_A6 (_EBI_ROUTE_APEN_A6 << 18) /**< Shifted mode A6 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 478 | #define EBI_ROUTE_APEN_A7 (_EBI_ROUTE_APEN_A7 << 18) /**< Shifted mode A7 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 479 | #define EBI_ROUTE_APEN_A8 (_EBI_ROUTE_APEN_A8 << 18) /**< Shifted mode A8 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 480 | #define EBI_ROUTE_APEN_A9 (_EBI_ROUTE_APEN_A9 << 18) /**< Shifted mode A9 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 481 | #define EBI_ROUTE_APEN_A10 (_EBI_ROUTE_APEN_A10 << 18) /**< Shifted mode A10 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 482 | #define EBI_ROUTE_APEN_A11 (_EBI_ROUTE_APEN_A11 << 18) /**< Shifted mode A11 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 483 | #define EBI_ROUTE_APEN_A12 (_EBI_ROUTE_APEN_A12 << 18) /**< Shifted mode A12 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 484 | #define EBI_ROUTE_APEN_A13 (_EBI_ROUTE_APEN_A13 << 18) /**< Shifted mode A13 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 485 | #define EBI_ROUTE_APEN_A14 (_EBI_ROUTE_APEN_A14 << 18) /**< Shifted mode A14 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | #define EBI_ROUTE_APEN_A15 (_EBI_ROUTE_APEN_A15 << 18) /**< Shifted mode A15 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 487 | #define EBI_ROUTE_APEN_A16 (_EBI_ROUTE_APEN_A16 << 18) /**< Shifted mode A16 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 488 | #define EBI_ROUTE_APEN_A17 (_EBI_ROUTE_APEN_A17 << 18) /**< Shifted mode A17 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 489 | #define EBI_ROUTE_APEN_A18 (_EBI_ROUTE_APEN_A18 << 18) /**< Shifted mode A18 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 490 | #define EBI_ROUTE_APEN_A19 (_EBI_ROUTE_APEN_A19 << 18) /**< Shifted mode A19 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 491 | #define EBI_ROUTE_APEN_A20 (_EBI_ROUTE_APEN_A20 << 18) /**< Shifted mode A20 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 492 | #define EBI_ROUTE_APEN_A21 (_EBI_ROUTE_APEN_A21 << 18) /**< Shifted mode A21 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 493 | #define EBI_ROUTE_APEN_A22 (_EBI_ROUTE_APEN_A22 << 18) /**< Shifted mode A22 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 494 | #define EBI_ROUTE_APEN_A23 (_EBI_ROUTE_APEN_A23 << 18) /**< Shifted mode A23 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 495 | #define EBI_ROUTE_APEN_A24 (_EBI_ROUTE_APEN_A24 << 18) /**< Shifted mode A24 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 496 | #define EBI_ROUTE_APEN_A25 (_EBI_ROUTE_APEN_A25 << 18) /**< Shifted mode A25 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 497 | #define EBI_ROUTE_APEN_A26 (_EBI_ROUTE_APEN_A26 << 18) /**< Shifted mode A26 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 498 | #define EBI_ROUTE_APEN_A27 (_EBI_ROUTE_APEN_A27 << 18) /**< Shifted mode A27 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 499 | #define EBI_ROUTE_APEN_A28 (_EBI_ROUTE_APEN_A28 << 18) /**< Shifted mode A28 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 500 | #define EBI_ROUTE_TFTPEN (0x1UL << 24) /**< EBI_TFT Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 501 | #define _EBI_ROUTE_TFTPEN_SHIFT 24 /**< Shift value for EBI_TFTPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 502 | #define _EBI_ROUTE_TFTPEN_MASK 0x1000000UL /**< Bit mask for EBI_TFTPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 503 | #define _EBI_ROUTE_TFTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 504 | #define EBI_ROUTE_TFTPEN_DEFAULT (_EBI_ROUTE_TFTPEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 505 | #define EBI_ROUTE_DATAENPEN (0x1UL << 25) /**< EBI_TFT Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 506 | #define _EBI_ROUTE_DATAENPEN_SHIFT 25 /**< Shift value for EBI_DATAENPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 507 | #define _EBI_ROUTE_DATAENPEN_MASK 0x2000000UL /**< Bit mask for EBI_DATAENPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 508 | #define _EBI_ROUTE_DATAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 509 | #define EBI_ROUTE_DATAENPEN_DEFAULT (_EBI_ROUTE_DATAENPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 510 | #define EBI_ROUTE_CSTFTPEN (0x1UL << 26) /**< EBI_CSTFT Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 511 | #define _EBI_ROUTE_CSTFTPEN_SHIFT 26 /**< Shift value for EBI_CSTFTPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 512 | #define _EBI_ROUTE_CSTFTPEN_MASK 0x4000000UL /**< Bit mask for EBI_CSTFTPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 513 | #define _EBI_ROUTE_CSTFTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 514 | #define EBI_ROUTE_CSTFTPEN_DEFAULT (_EBI_ROUTE_CSTFTPEN_DEFAULT << 26) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 515 | #define _EBI_ROUTE_LOCATION_SHIFT 28 /**< Shift value for EBI_LOCATION */ |
| AnnaBridge | 171:3a7713b1edbc | 516 | #define _EBI_ROUTE_LOCATION_MASK 0x70000000UL /**< Bit mask for EBI_LOCATION */ |
| AnnaBridge | 171:3a7713b1edbc | 517 | #define _EBI_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 518 | #define _EBI_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 519 | #define _EBI_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 520 | #define _EBI_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 521 | #define EBI_ROUTE_LOCATION_LOC0 (_EBI_ROUTE_LOCATION_LOC0 << 28) /**< Shifted mode LOC0 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 522 | #define EBI_ROUTE_LOCATION_DEFAULT (_EBI_ROUTE_LOCATION_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 523 | #define EBI_ROUTE_LOCATION_LOC1 (_EBI_ROUTE_LOCATION_LOC1 << 28) /**< Shifted mode LOC1 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 524 | #define EBI_ROUTE_LOCATION_LOC2 (_EBI_ROUTE_LOCATION_LOC2 << 28) /**< Shifted mode LOC2 for EBI_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 525 | |
| AnnaBridge | 171:3a7713b1edbc | 526 | /* Bit fields for EBI ADDRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 527 | #define _EBI_ADDRTIMING1_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 528 | #define _EBI_ADDRTIMING1_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 529 | #define _EBI_ADDRTIMING1_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 530 | #define _EBI_ADDRTIMING1_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 531 | #define _EBI_ADDRTIMING1_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 532 | #define EBI_ADDRTIMING1_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING1_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 533 | #define _EBI_ADDRTIMING1_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 534 | #define _EBI_ADDRTIMING1_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 535 | #define _EBI_ADDRTIMING1_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 536 | #define EBI_ADDRTIMING1_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING1_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | #define EBI_ADDRTIMING1_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 538 | #define _EBI_ADDRTIMING1_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ |
| AnnaBridge | 171:3a7713b1edbc | 539 | #define _EBI_ADDRTIMING1_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ |
| AnnaBridge | 171:3a7713b1edbc | 540 | #define _EBI_ADDRTIMING1_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | #define EBI_ADDRTIMING1_HALFALE_DEFAULT (_EBI_ADDRTIMING1_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 542 | |
| AnnaBridge | 171:3a7713b1edbc | 543 | /* Bit fields for EBI RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 544 | #define _EBI_RDTIMING1_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 545 | #define _EBI_RDTIMING1_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 546 | #define _EBI_RDTIMING1_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 547 | #define _EBI_RDTIMING1_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 548 | #define _EBI_RDTIMING1_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 549 | #define EBI_RDTIMING1_RDSETUP_DEFAULT (_EBI_RDTIMING1_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 550 | #define _EBI_RDTIMING1_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 551 | #define _EBI_RDTIMING1_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 552 | #define _EBI_RDTIMING1_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 553 | #define EBI_RDTIMING1_RDSTRB_DEFAULT (_EBI_RDTIMING1_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 554 | #define _EBI_RDTIMING1_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 555 | #define _EBI_RDTIMING1_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 556 | #define _EBI_RDTIMING1_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 557 | #define EBI_RDTIMING1_RDHOLD_DEFAULT (_EBI_RDTIMING1_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 558 | #define EBI_RDTIMING1_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 559 | #define _EBI_RDTIMING1_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ |
| AnnaBridge | 171:3a7713b1edbc | 560 | #define _EBI_RDTIMING1_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ |
| AnnaBridge | 171:3a7713b1edbc | 561 | #define _EBI_RDTIMING1_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 562 | #define EBI_RDTIMING1_HALFRE_DEFAULT (_EBI_RDTIMING1_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 563 | #define EBI_RDTIMING1_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 564 | #define _EBI_RDTIMING1_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ |
| AnnaBridge | 171:3a7713b1edbc | 565 | #define _EBI_RDTIMING1_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | #define _EBI_RDTIMING1_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 567 | #define EBI_RDTIMING1_PREFETCH_DEFAULT (_EBI_RDTIMING1_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 568 | #define EBI_RDTIMING1_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 569 | #define _EBI_RDTIMING1_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 570 | #define _EBI_RDTIMING1_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 571 | #define _EBI_RDTIMING1_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 572 | #define EBI_RDTIMING1_PAGEMODE_DEFAULT (_EBI_RDTIMING1_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 573 | |
| AnnaBridge | 171:3a7713b1edbc | 574 | /* Bit fields for EBI WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 575 | #define _EBI_WRTIMING1_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 576 | #define _EBI_WRTIMING1_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 577 | #define _EBI_WRTIMING1_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 578 | #define _EBI_WRTIMING1_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 579 | #define _EBI_WRTIMING1_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 580 | #define EBI_WRTIMING1_WRSETUP_DEFAULT (_EBI_WRTIMING1_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 581 | #define _EBI_WRTIMING1_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 582 | #define _EBI_WRTIMING1_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 583 | #define _EBI_WRTIMING1_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 584 | #define EBI_WRTIMING1_WRSTRB_DEFAULT (_EBI_WRTIMING1_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 585 | #define _EBI_WRTIMING1_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 586 | #define _EBI_WRTIMING1_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 587 | #define _EBI_WRTIMING1_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 588 | #define EBI_WRTIMING1_WRHOLD_DEFAULT (_EBI_WRTIMING1_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define EBI_WRTIMING1_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 590 | #define _EBI_WRTIMING1_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ |
| AnnaBridge | 171:3a7713b1edbc | 591 | #define _EBI_WRTIMING1_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ |
| AnnaBridge | 171:3a7713b1edbc | 592 | #define _EBI_WRTIMING1_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 593 | #define EBI_WRTIMING1_HALFWE_DEFAULT (_EBI_WRTIMING1_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 594 | #define EBI_WRTIMING1_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 595 | #define _EBI_WRTIMING1_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 596 | #define _EBI_WRTIMING1_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 597 | #define _EBI_WRTIMING1_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 598 | #define EBI_WRTIMING1_WBUFDIS_DEFAULT (_EBI_WRTIMING1_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ |
| AnnaBridge | 171:3a7713b1edbc | 599 | |
| AnnaBridge | 171:3a7713b1edbc | 600 | /* Bit fields for EBI POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 601 | #define _EBI_POLARITY1_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 602 | #define _EBI_POLARITY1_MASK 0x0000003FUL /**< Mask for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 603 | #define EBI_POLARITY1_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 604 | #define _EBI_POLARITY1_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 605 | #define _EBI_POLARITY1_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 606 | #define _EBI_POLARITY1_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 607 | #define _EBI_POLARITY1_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 608 | #define _EBI_POLARITY1_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 609 | #define EBI_POLARITY1_CSPOL_DEFAULT (_EBI_POLARITY1_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 610 | #define EBI_POLARITY1_CSPOL_ACTIVELOW (_EBI_POLARITY1_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 611 | #define EBI_POLARITY1_CSPOL_ACTIVEHIGH (_EBI_POLARITY1_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 612 | #define EBI_POLARITY1_REPOL (0x1UL << 1) /**< Read Enable Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 613 | #define _EBI_POLARITY1_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 614 | #define _EBI_POLARITY1_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 615 | #define _EBI_POLARITY1_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 616 | #define _EBI_POLARITY1_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 617 | #define _EBI_POLARITY1_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 618 | #define EBI_POLARITY1_REPOL_DEFAULT (_EBI_POLARITY1_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 619 | #define EBI_POLARITY1_REPOL_ACTIVELOW (_EBI_POLARITY1_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 620 | #define EBI_POLARITY1_REPOL_ACTIVEHIGH (_EBI_POLARITY1_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 621 | #define EBI_POLARITY1_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 622 | #define _EBI_POLARITY1_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 623 | #define _EBI_POLARITY1_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 624 | #define _EBI_POLARITY1_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 625 | #define _EBI_POLARITY1_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 626 | #define _EBI_POLARITY1_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 627 | #define EBI_POLARITY1_WEPOL_DEFAULT (_EBI_POLARITY1_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 628 | #define EBI_POLARITY1_WEPOL_ACTIVELOW (_EBI_POLARITY1_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 629 | #define EBI_POLARITY1_WEPOL_ACTIVEHIGH (_EBI_POLARITY1_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 630 | #define EBI_POLARITY1_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 631 | #define _EBI_POLARITY1_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 632 | #define _EBI_POLARITY1_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 633 | #define _EBI_POLARITY1_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 634 | #define _EBI_POLARITY1_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 635 | #define _EBI_POLARITY1_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 636 | #define EBI_POLARITY1_ALEPOL_DEFAULT (_EBI_POLARITY1_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 637 | #define EBI_POLARITY1_ALEPOL_ACTIVELOW (_EBI_POLARITY1_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 638 | #define EBI_POLARITY1_ALEPOL_ACTIVEHIGH (_EBI_POLARITY1_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 639 | #define EBI_POLARITY1_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 640 | #define _EBI_POLARITY1_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 641 | #define _EBI_POLARITY1_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 642 | #define _EBI_POLARITY1_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 643 | #define _EBI_POLARITY1_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 644 | #define _EBI_POLARITY1_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 645 | #define EBI_POLARITY1_ARDYPOL_DEFAULT (_EBI_POLARITY1_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 646 | #define EBI_POLARITY1_ARDYPOL_ACTIVELOW (_EBI_POLARITY1_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 647 | #define EBI_POLARITY1_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY1_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 648 | #define EBI_POLARITY1_BLPOL (0x1UL << 5) /**< BL Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 649 | #define _EBI_POLARITY1_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 650 | #define _EBI_POLARITY1_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 651 | #define _EBI_POLARITY1_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 652 | #define _EBI_POLARITY1_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 653 | #define _EBI_POLARITY1_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 654 | #define EBI_POLARITY1_BLPOL_DEFAULT (_EBI_POLARITY1_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 655 | #define EBI_POLARITY1_BLPOL_ACTIVELOW (_EBI_POLARITY1_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 656 | #define EBI_POLARITY1_BLPOL_ACTIVEHIGH (_EBI_POLARITY1_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ |
| AnnaBridge | 171:3a7713b1edbc | 657 | |
| AnnaBridge | 171:3a7713b1edbc | 658 | /* Bit fields for EBI ADDRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 659 | #define _EBI_ADDRTIMING2_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 660 | #define _EBI_ADDRTIMING2_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 661 | #define _EBI_ADDRTIMING2_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 662 | #define _EBI_ADDRTIMING2_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 663 | #define _EBI_ADDRTIMING2_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 664 | #define EBI_ADDRTIMING2_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING2_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 665 | #define _EBI_ADDRTIMING2_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 666 | #define _EBI_ADDRTIMING2_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 667 | #define _EBI_ADDRTIMING2_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 668 | #define EBI_ADDRTIMING2_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING2_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 669 | #define EBI_ADDRTIMING2_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 670 | #define _EBI_ADDRTIMING2_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ |
| AnnaBridge | 171:3a7713b1edbc | 671 | #define _EBI_ADDRTIMING2_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ |
| AnnaBridge | 171:3a7713b1edbc | 672 | #define _EBI_ADDRTIMING2_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 673 | #define EBI_ADDRTIMING2_HALFALE_DEFAULT (_EBI_ADDRTIMING2_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 674 | |
| AnnaBridge | 171:3a7713b1edbc | 675 | /* Bit fields for EBI RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 676 | #define _EBI_RDTIMING2_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 677 | #define _EBI_RDTIMING2_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 678 | #define _EBI_RDTIMING2_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 679 | #define _EBI_RDTIMING2_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 680 | #define _EBI_RDTIMING2_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 681 | #define EBI_RDTIMING2_RDSETUP_DEFAULT (_EBI_RDTIMING2_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 682 | #define _EBI_RDTIMING2_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 683 | #define _EBI_RDTIMING2_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 684 | #define _EBI_RDTIMING2_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 685 | #define EBI_RDTIMING2_RDSTRB_DEFAULT (_EBI_RDTIMING2_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 686 | #define _EBI_RDTIMING2_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 687 | #define _EBI_RDTIMING2_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 688 | #define _EBI_RDTIMING2_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 689 | #define EBI_RDTIMING2_RDHOLD_DEFAULT (_EBI_RDTIMING2_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 690 | #define EBI_RDTIMING2_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 691 | #define _EBI_RDTIMING2_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ |
| AnnaBridge | 171:3a7713b1edbc | 692 | #define _EBI_RDTIMING2_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ |
| AnnaBridge | 171:3a7713b1edbc | 693 | #define _EBI_RDTIMING2_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 694 | #define EBI_RDTIMING2_HALFRE_DEFAULT (_EBI_RDTIMING2_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 695 | #define EBI_RDTIMING2_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 696 | #define _EBI_RDTIMING2_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ |
| AnnaBridge | 171:3a7713b1edbc | 697 | #define _EBI_RDTIMING2_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ |
| AnnaBridge | 171:3a7713b1edbc | 698 | #define _EBI_RDTIMING2_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 699 | #define EBI_RDTIMING2_PREFETCH_DEFAULT (_EBI_RDTIMING2_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 700 | #define EBI_RDTIMING2_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 701 | #define _EBI_RDTIMING2_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 702 | #define _EBI_RDTIMING2_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 703 | #define _EBI_RDTIMING2_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 704 | #define EBI_RDTIMING2_PAGEMODE_DEFAULT (_EBI_RDTIMING2_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 705 | |
| AnnaBridge | 171:3a7713b1edbc | 706 | /* Bit fields for EBI WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 707 | #define _EBI_WRTIMING2_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 708 | #define _EBI_WRTIMING2_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 709 | #define _EBI_WRTIMING2_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 710 | #define _EBI_WRTIMING2_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 711 | #define _EBI_WRTIMING2_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 712 | #define EBI_WRTIMING2_WRSETUP_DEFAULT (_EBI_WRTIMING2_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 713 | #define _EBI_WRTIMING2_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 714 | #define _EBI_WRTIMING2_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 715 | #define _EBI_WRTIMING2_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 716 | #define EBI_WRTIMING2_WRSTRB_DEFAULT (_EBI_WRTIMING2_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 717 | #define _EBI_WRTIMING2_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 718 | #define _EBI_WRTIMING2_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 719 | #define _EBI_WRTIMING2_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 720 | #define EBI_WRTIMING2_WRHOLD_DEFAULT (_EBI_WRTIMING2_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 721 | #define EBI_WRTIMING2_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 722 | #define _EBI_WRTIMING2_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ |
| AnnaBridge | 171:3a7713b1edbc | 723 | #define _EBI_WRTIMING2_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ |
| AnnaBridge | 171:3a7713b1edbc | 724 | #define _EBI_WRTIMING2_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 725 | #define EBI_WRTIMING2_HALFWE_DEFAULT (_EBI_WRTIMING2_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 726 | #define EBI_WRTIMING2_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 727 | #define _EBI_WRTIMING2_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 728 | #define _EBI_WRTIMING2_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 729 | #define _EBI_WRTIMING2_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 730 | #define EBI_WRTIMING2_WBUFDIS_DEFAULT (_EBI_WRTIMING2_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ |
| AnnaBridge | 171:3a7713b1edbc | 731 | |
| AnnaBridge | 171:3a7713b1edbc | 732 | /* Bit fields for EBI POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 733 | #define _EBI_POLARITY2_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 734 | #define _EBI_POLARITY2_MASK 0x0000003FUL /**< Mask for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 735 | #define EBI_POLARITY2_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 736 | #define _EBI_POLARITY2_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 737 | #define _EBI_POLARITY2_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 738 | #define _EBI_POLARITY2_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 739 | #define _EBI_POLARITY2_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 740 | #define _EBI_POLARITY2_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 741 | #define EBI_POLARITY2_CSPOL_DEFAULT (_EBI_POLARITY2_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 742 | #define EBI_POLARITY2_CSPOL_ACTIVELOW (_EBI_POLARITY2_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 743 | #define EBI_POLARITY2_CSPOL_ACTIVEHIGH (_EBI_POLARITY2_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 744 | #define EBI_POLARITY2_REPOL (0x1UL << 1) /**< Read Enable Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 745 | #define _EBI_POLARITY2_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 746 | #define _EBI_POLARITY2_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 747 | #define _EBI_POLARITY2_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 748 | #define _EBI_POLARITY2_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 749 | #define _EBI_POLARITY2_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 750 | #define EBI_POLARITY2_REPOL_DEFAULT (_EBI_POLARITY2_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 751 | #define EBI_POLARITY2_REPOL_ACTIVELOW (_EBI_POLARITY2_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 752 | #define EBI_POLARITY2_REPOL_ACTIVEHIGH (_EBI_POLARITY2_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 753 | #define EBI_POLARITY2_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 754 | #define _EBI_POLARITY2_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 755 | #define _EBI_POLARITY2_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 756 | #define _EBI_POLARITY2_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 757 | #define _EBI_POLARITY2_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 758 | #define _EBI_POLARITY2_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 759 | #define EBI_POLARITY2_WEPOL_DEFAULT (_EBI_POLARITY2_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 760 | #define EBI_POLARITY2_WEPOL_ACTIVELOW (_EBI_POLARITY2_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 761 | #define EBI_POLARITY2_WEPOL_ACTIVEHIGH (_EBI_POLARITY2_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 762 | #define EBI_POLARITY2_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 763 | #define _EBI_POLARITY2_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 764 | #define _EBI_POLARITY2_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 765 | #define _EBI_POLARITY2_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 766 | #define _EBI_POLARITY2_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 767 | #define _EBI_POLARITY2_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 768 | #define EBI_POLARITY2_ALEPOL_DEFAULT (_EBI_POLARITY2_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 769 | #define EBI_POLARITY2_ALEPOL_ACTIVELOW (_EBI_POLARITY2_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 770 | #define EBI_POLARITY2_ALEPOL_ACTIVEHIGH (_EBI_POLARITY2_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 771 | #define EBI_POLARITY2_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 772 | #define _EBI_POLARITY2_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 773 | #define _EBI_POLARITY2_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 774 | #define _EBI_POLARITY2_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 775 | #define _EBI_POLARITY2_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 776 | #define _EBI_POLARITY2_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 777 | #define EBI_POLARITY2_ARDYPOL_DEFAULT (_EBI_POLARITY2_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 778 | #define EBI_POLARITY2_ARDYPOL_ACTIVELOW (_EBI_POLARITY2_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 779 | #define EBI_POLARITY2_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY2_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 780 | #define EBI_POLARITY2_BLPOL (0x1UL << 5) /**< BL Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 781 | #define _EBI_POLARITY2_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 782 | #define _EBI_POLARITY2_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 783 | #define _EBI_POLARITY2_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 784 | #define _EBI_POLARITY2_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 785 | #define _EBI_POLARITY2_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 786 | #define EBI_POLARITY2_BLPOL_DEFAULT (_EBI_POLARITY2_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 787 | #define EBI_POLARITY2_BLPOL_ACTIVELOW (_EBI_POLARITY2_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 788 | #define EBI_POLARITY2_BLPOL_ACTIVEHIGH (_EBI_POLARITY2_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ |
| AnnaBridge | 171:3a7713b1edbc | 789 | |
| AnnaBridge | 171:3a7713b1edbc | 790 | /* Bit fields for EBI ADDRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 791 | #define _EBI_ADDRTIMING3_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 792 | #define _EBI_ADDRTIMING3_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 793 | #define _EBI_ADDRTIMING3_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 794 | #define _EBI_ADDRTIMING3_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 795 | #define _EBI_ADDRTIMING3_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 796 | #define EBI_ADDRTIMING3_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING3_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 797 | #define _EBI_ADDRTIMING3_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 798 | #define _EBI_ADDRTIMING3_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 799 | #define _EBI_ADDRTIMING3_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 800 | #define EBI_ADDRTIMING3_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING3_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 801 | #define EBI_ADDRTIMING3_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 802 | #define _EBI_ADDRTIMING3_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ |
| AnnaBridge | 171:3a7713b1edbc | 803 | #define _EBI_ADDRTIMING3_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ |
| AnnaBridge | 171:3a7713b1edbc | 804 | #define _EBI_ADDRTIMING3_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 805 | #define EBI_ADDRTIMING3_HALFALE_DEFAULT (_EBI_ADDRTIMING3_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 806 | |
| AnnaBridge | 171:3a7713b1edbc | 807 | /* Bit fields for EBI RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 808 | #define _EBI_RDTIMING3_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 809 | #define _EBI_RDTIMING3_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 810 | #define _EBI_RDTIMING3_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 811 | #define _EBI_RDTIMING3_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 812 | #define _EBI_RDTIMING3_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 813 | #define EBI_RDTIMING3_RDSETUP_DEFAULT (_EBI_RDTIMING3_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 814 | #define _EBI_RDTIMING3_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 815 | #define _EBI_RDTIMING3_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 816 | #define _EBI_RDTIMING3_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 817 | #define EBI_RDTIMING3_RDSTRB_DEFAULT (_EBI_RDTIMING3_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 818 | #define _EBI_RDTIMING3_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 819 | #define _EBI_RDTIMING3_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 820 | #define _EBI_RDTIMING3_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 821 | #define EBI_RDTIMING3_RDHOLD_DEFAULT (_EBI_RDTIMING3_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 822 | #define EBI_RDTIMING3_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 823 | #define _EBI_RDTIMING3_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ |
| AnnaBridge | 171:3a7713b1edbc | 824 | #define _EBI_RDTIMING3_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ |
| AnnaBridge | 171:3a7713b1edbc | 825 | #define _EBI_RDTIMING3_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 826 | #define EBI_RDTIMING3_HALFRE_DEFAULT (_EBI_RDTIMING3_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 827 | #define EBI_RDTIMING3_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 828 | #define _EBI_RDTIMING3_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ |
| AnnaBridge | 171:3a7713b1edbc | 829 | #define _EBI_RDTIMING3_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ |
| AnnaBridge | 171:3a7713b1edbc | 830 | #define _EBI_RDTIMING3_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 831 | #define EBI_RDTIMING3_PREFETCH_DEFAULT (_EBI_RDTIMING3_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 832 | #define EBI_RDTIMING3_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 833 | #define _EBI_RDTIMING3_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 834 | #define _EBI_RDTIMING3_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 835 | #define _EBI_RDTIMING3_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 836 | #define EBI_RDTIMING3_PAGEMODE_DEFAULT (_EBI_RDTIMING3_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 837 | |
| AnnaBridge | 171:3a7713b1edbc | 838 | /* Bit fields for EBI WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 839 | #define _EBI_WRTIMING3_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 840 | #define _EBI_WRTIMING3_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 841 | #define _EBI_WRTIMING3_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 842 | #define _EBI_WRTIMING3_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 843 | #define _EBI_WRTIMING3_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 844 | #define EBI_WRTIMING3_WRSETUP_DEFAULT (_EBI_WRTIMING3_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 845 | #define _EBI_WRTIMING3_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 846 | #define _EBI_WRTIMING3_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */ |
| AnnaBridge | 171:3a7713b1edbc | 847 | #define _EBI_WRTIMING3_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 848 | #define EBI_WRTIMING3_WRSTRB_DEFAULT (_EBI_WRTIMING3_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 849 | #define _EBI_WRTIMING3_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 850 | #define _EBI_WRTIMING3_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 851 | #define _EBI_WRTIMING3_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 852 | #define EBI_WRTIMING3_WRHOLD_DEFAULT (_EBI_WRTIMING3_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 853 | #define EBI_WRTIMING3_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 854 | #define _EBI_WRTIMING3_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ |
| AnnaBridge | 171:3a7713b1edbc | 855 | #define _EBI_WRTIMING3_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ |
| AnnaBridge | 171:3a7713b1edbc | 856 | #define _EBI_WRTIMING3_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 857 | #define EBI_WRTIMING3_HALFWE_DEFAULT (_EBI_WRTIMING3_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 858 | #define EBI_WRTIMING3_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 859 | #define _EBI_WRTIMING3_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 860 | #define _EBI_WRTIMING3_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 861 | #define _EBI_WRTIMING3_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 862 | #define EBI_WRTIMING3_WBUFDIS_DEFAULT (_EBI_WRTIMING3_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ |
| AnnaBridge | 171:3a7713b1edbc | 863 | |
| AnnaBridge | 171:3a7713b1edbc | 864 | /* Bit fields for EBI POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 865 | #define _EBI_POLARITY3_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 866 | #define _EBI_POLARITY3_MASK 0x0000003FUL /**< Mask for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 867 | #define EBI_POLARITY3_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 868 | #define _EBI_POLARITY3_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 869 | #define _EBI_POLARITY3_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 870 | #define _EBI_POLARITY3_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 871 | #define _EBI_POLARITY3_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 872 | #define _EBI_POLARITY3_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 873 | #define EBI_POLARITY3_CSPOL_DEFAULT (_EBI_POLARITY3_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 874 | #define EBI_POLARITY3_CSPOL_ACTIVELOW (_EBI_POLARITY3_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 875 | #define EBI_POLARITY3_CSPOL_ACTIVEHIGH (_EBI_POLARITY3_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 876 | #define EBI_POLARITY3_REPOL (0x1UL << 1) /**< Read Enable Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 877 | #define _EBI_POLARITY3_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 878 | #define _EBI_POLARITY3_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 879 | #define _EBI_POLARITY3_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 880 | #define _EBI_POLARITY3_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 881 | #define _EBI_POLARITY3_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 882 | #define EBI_POLARITY3_REPOL_DEFAULT (_EBI_POLARITY3_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 883 | #define EBI_POLARITY3_REPOL_ACTIVELOW (_EBI_POLARITY3_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 884 | #define EBI_POLARITY3_REPOL_ACTIVEHIGH (_EBI_POLARITY3_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 885 | #define EBI_POLARITY3_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 886 | #define _EBI_POLARITY3_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 887 | #define _EBI_POLARITY3_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 888 | #define _EBI_POLARITY3_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 889 | #define _EBI_POLARITY3_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 890 | #define _EBI_POLARITY3_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 891 | #define EBI_POLARITY3_WEPOL_DEFAULT (_EBI_POLARITY3_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 892 | #define EBI_POLARITY3_WEPOL_ACTIVELOW (_EBI_POLARITY3_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 893 | #define EBI_POLARITY3_WEPOL_ACTIVEHIGH (_EBI_POLARITY3_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 894 | #define EBI_POLARITY3_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 895 | #define _EBI_POLARITY3_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 896 | #define _EBI_POLARITY3_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 897 | #define _EBI_POLARITY3_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 898 | #define _EBI_POLARITY3_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 899 | #define _EBI_POLARITY3_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 900 | #define EBI_POLARITY3_ALEPOL_DEFAULT (_EBI_POLARITY3_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 901 | #define EBI_POLARITY3_ALEPOL_ACTIVELOW (_EBI_POLARITY3_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 902 | #define EBI_POLARITY3_ALEPOL_ACTIVEHIGH (_EBI_POLARITY3_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 903 | #define EBI_POLARITY3_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 904 | #define _EBI_POLARITY3_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 905 | #define _EBI_POLARITY3_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 906 | #define _EBI_POLARITY3_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 907 | #define _EBI_POLARITY3_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 908 | #define _EBI_POLARITY3_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 909 | #define EBI_POLARITY3_ARDYPOL_DEFAULT (_EBI_POLARITY3_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 910 | #define EBI_POLARITY3_ARDYPOL_ACTIVELOW (_EBI_POLARITY3_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 911 | #define EBI_POLARITY3_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY3_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 912 | #define EBI_POLARITY3_BLPOL (0x1UL << 5) /**< BL Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 913 | #define _EBI_POLARITY3_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 914 | #define _EBI_POLARITY3_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 915 | #define _EBI_POLARITY3_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 916 | #define _EBI_POLARITY3_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 917 | #define _EBI_POLARITY3_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 918 | #define EBI_POLARITY3_BLPOL_DEFAULT (_EBI_POLARITY3_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 919 | #define EBI_POLARITY3_BLPOL_ACTIVELOW (_EBI_POLARITY3_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 920 | #define EBI_POLARITY3_BLPOL_ACTIVEHIGH (_EBI_POLARITY3_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ |
| AnnaBridge | 171:3a7713b1edbc | 921 | |
| AnnaBridge | 171:3a7713b1edbc | 922 | /* Bit fields for EBI PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 923 | #define _EBI_PAGECTRL_RESETVALUE 0x00000700UL /**< Default value for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 924 | #define _EBI_PAGECTRL_MASK 0x07F00713UL /**< Mask for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 925 | #define _EBI_PAGECTRL_PAGELEN_SHIFT 0 /**< Shift value for EBI_PAGELEN */ |
| AnnaBridge | 171:3a7713b1edbc | 926 | #define _EBI_PAGECTRL_PAGELEN_MASK 0x3UL /**< Bit mask for EBI_PAGELEN */ |
| AnnaBridge | 171:3a7713b1edbc | 927 | #define _EBI_PAGECTRL_PAGELEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 928 | #define _EBI_PAGECTRL_PAGELEN_MEMBER4 0x00000000UL /**< Mode MEMBER4 for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 929 | #define _EBI_PAGECTRL_PAGELEN_MEMBER8 0x00000001UL /**< Mode MEMBER8 for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 930 | #define _EBI_PAGECTRL_PAGELEN_MEMBER16 0x00000002UL /**< Mode MEMBER16 for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 931 | #define _EBI_PAGECTRL_PAGELEN_MEMBER32 0x00000003UL /**< Mode MEMBER32 for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 932 | #define EBI_PAGECTRL_PAGELEN_DEFAULT (_EBI_PAGECTRL_PAGELEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 933 | #define EBI_PAGECTRL_PAGELEN_MEMBER4 (_EBI_PAGECTRL_PAGELEN_MEMBER4 << 0) /**< Shifted mode MEMBER4 for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 934 | #define EBI_PAGECTRL_PAGELEN_MEMBER8 (_EBI_PAGECTRL_PAGELEN_MEMBER8 << 0) /**< Shifted mode MEMBER8 for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 935 | #define EBI_PAGECTRL_PAGELEN_MEMBER16 (_EBI_PAGECTRL_PAGELEN_MEMBER16 << 0) /**< Shifted mode MEMBER16 for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 936 | #define EBI_PAGECTRL_PAGELEN_MEMBER32 (_EBI_PAGECTRL_PAGELEN_MEMBER32 << 0) /**< Shifted mode MEMBER32 for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 937 | #define EBI_PAGECTRL_INCHIT (0x1UL << 4) /**< Intrapage hit only on incremental addresses */ |
| AnnaBridge | 171:3a7713b1edbc | 938 | #define _EBI_PAGECTRL_INCHIT_SHIFT 4 /**< Shift value for EBI_INCHIT */ |
| AnnaBridge | 171:3a7713b1edbc | 939 | #define _EBI_PAGECTRL_INCHIT_MASK 0x10UL /**< Bit mask for EBI_INCHIT */ |
| AnnaBridge | 171:3a7713b1edbc | 940 | #define _EBI_PAGECTRL_INCHIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 941 | #define EBI_PAGECTRL_INCHIT_DEFAULT (_EBI_PAGECTRL_INCHIT_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 942 | #define _EBI_PAGECTRL_RDPA_SHIFT 8 /**< Shift value for EBI_RDPA */ |
| AnnaBridge | 171:3a7713b1edbc | 943 | #define _EBI_PAGECTRL_RDPA_MASK 0x700UL /**< Bit mask for EBI_RDPA */ |
| AnnaBridge | 171:3a7713b1edbc | 944 | #define _EBI_PAGECTRL_RDPA_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 945 | #define EBI_PAGECTRL_RDPA_DEFAULT (_EBI_PAGECTRL_RDPA_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 946 | #define _EBI_PAGECTRL_KEEPOPEN_SHIFT 20 /**< Shift value for EBI_KEEPOPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 947 | #define _EBI_PAGECTRL_KEEPOPEN_MASK 0x7F00000UL /**< Bit mask for EBI_KEEPOPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 948 | #define _EBI_PAGECTRL_KEEPOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 949 | #define EBI_PAGECTRL_KEEPOPEN_DEFAULT (_EBI_PAGECTRL_KEEPOPEN_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 950 | |
| AnnaBridge | 171:3a7713b1edbc | 951 | /* Bit fields for EBI NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 952 | #define _EBI_NANDCTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 953 | #define _EBI_NANDCTRL_MASK 0x00000031UL /**< Mask for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 954 | #define EBI_NANDCTRL_EN (0x1UL << 0) /**< NAND Flash control enable */ |
| AnnaBridge | 171:3a7713b1edbc | 955 | #define _EBI_NANDCTRL_EN_SHIFT 0 /**< Shift value for EBI_EN */ |
| AnnaBridge | 171:3a7713b1edbc | 956 | #define _EBI_NANDCTRL_EN_MASK 0x1UL /**< Bit mask for EBI_EN */ |
| AnnaBridge | 171:3a7713b1edbc | 957 | #define _EBI_NANDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 958 | #define EBI_NANDCTRL_EN_DEFAULT (_EBI_NANDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 959 | #define _EBI_NANDCTRL_BANKSEL_SHIFT 4 /**< Shift value for EBI_BANKSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 960 | #define _EBI_NANDCTRL_BANKSEL_MASK 0x30UL /**< Bit mask for EBI_BANKSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 961 | #define _EBI_NANDCTRL_BANKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 962 | #define _EBI_NANDCTRL_BANKSEL_BANK0 0x00000000UL /**< Mode BANK0 for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 963 | #define _EBI_NANDCTRL_BANKSEL_BANK1 0x00000001UL /**< Mode BANK1 for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 964 | #define _EBI_NANDCTRL_BANKSEL_BANK2 0x00000002UL /**< Mode BANK2 for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 965 | #define _EBI_NANDCTRL_BANKSEL_BANK3 0x00000003UL /**< Mode BANK3 for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 966 | #define EBI_NANDCTRL_BANKSEL_DEFAULT (_EBI_NANDCTRL_BANKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 967 | #define EBI_NANDCTRL_BANKSEL_BANK0 (_EBI_NANDCTRL_BANKSEL_BANK0 << 4) /**< Shifted mode BANK0 for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 968 | #define EBI_NANDCTRL_BANKSEL_BANK1 (_EBI_NANDCTRL_BANKSEL_BANK1 << 4) /**< Shifted mode BANK1 for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 969 | #define EBI_NANDCTRL_BANKSEL_BANK2 (_EBI_NANDCTRL_BANKSEL_BANK2 << 4) /**< Shifted mode BANK2 for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 970 | #define EBI_NANDCTRL_BANKSEL_BANK3 (_EBI_NANDCTRL_BANKSEL_BANK3 << 4) /**< Shifted mode BANK3 for EBI_NANDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 971 | |
| AnnaBridge | 171:3a7713b1edbc | 972 | /* Bit fields for EBI CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 973 | #define _EBI_CMD_RESETVALUE 0x00000000UL /**< Default value for EBI_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 974 | #define _EBI_CMD_MASK 0x00000007UL /**< Mask for EBI_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 975 | #define EBI_CMD_ECCSTART (0x1UL << 0) /**< Error Correction Code Generation Start */ |
| AnnaBridge | 171:3a7713b1edbc | 976 | #define _EBI_CMD_ECCSTART_SHIFT 0 /**< Shift value for EBI_ECCSTART */ |
| AnnaBridge | 171:3a7713b1edbc | 977 | #define _EBI_CMD_ECCSTART_MASK 0x1UL /**< Bit mask for EBI_ECCSTART */ |
| AnnaBridge | 171:3a7713b1edbc | 978 | #define _EBI_CMD_ECCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 979 | #define EBI_CMD_ECCSTART_DEFAULT (_EBI_CMD_ECCSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 980 | #define EBI_CMD_ECCSTOP (0x1UL << 1) /**< Error Correction Code Generation Stop */ |
| AnnaBridge | 171:3a7713b1edbc | 981 | #define _EBI_CMD_ECCSTOP_SHIFT 1 /**< Shift value for EBI_ECCSTOP */ |
| AnnaBridge | 171:3a7713b1edbc | 982 | #define _EBI_CMD_ECCSTOP_MASK 0x2UL /**< Bit mask for EBI_ECCSTOP */ |
| AnnaBridge | 171:3a7713b1edbc | 983 | #define _EBI_CMD_ECCSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 984 | #define EBI_CMD_ECCSTOP_DEFAULT (_EBI_CMD_ECCSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 985 | #define EBI_CMD_ECCCLEAR (0x1UL << 2) /**< Error Correction Code Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 986 | #define _EBI_CMD_ECCCLEAR_SHIFT 2 /**< Shift value for EBI_ECCCLEAR */ |
| AnnaBridge | 171:3a7713b1edbc | 987 | #define _EBI_CMD_ECCCLEAR_MASK 0x4UL /**< Bit mask for EBI_ECCCLEAR */ |
| AnnaBridge | 171:3a7713b1edbc | 988 | #define _EBI_CMD_ECCCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 989 | #define EBI_CMD_ECCCLEAR_DEFAULT (_EBI_CMD_ECCCLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 990 | |
| AnnaBridge | 171:3a7713b1edbc | 991 | /* Bit fields for EBI STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 992 | #define _EBI_STATUS_RESETVALUE 0x00000000UL /**< Default value for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 993 | #define _EBI_STATUS_MASK 0x00003711UL /**< Mask for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 994 | #define EBI_STATUS_AHBACT (0x1UL << 0) /**< EBI Busy with AHB Transaction. */ |
| AnnaBridge | 171:3a7713b1edbc | 995 | #define _EBI_STATUS_AHBACT_SHIFT 0 /**< Shift value for EBI_AHBACT */ |
| AnnaBridge | 171:3a7713b1edbc | 996 | #define _EBI_STATUS_AHBACT_MASK 0x1UL /**< Bit mask for EBI_AHBACT */ |
| AnnaBridge | 171:3a7713b1edbc | 997 | #define _EBI_STATUS_AHBACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 998 | #define EBI_STATUS_AHBACT_DEFAULT (_EBI_STATUS_AHBACT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 999 | #define EBI_STATUS_ECCACT (0x1UL << 4) /**< EBI ECC Generation Active. */ |
| AnnaBridge | 171:3a7713b1edbc | 1000 | #define _EBI_STATUS_ECCACT_SHIFT 4 /**< Shift value for EBI_ECCACT */ |
| AnnaBridge | 171:3a7713b1edbc | 1001 | #define _EBI_STATUS_ECCACT_MASK 0x10UL /**< Bit mask for EBI_ECCACT */ |
| AnnaBridge | 171:3a7713b1edbc | 1002 | #define _EBI_STATUS_ECCACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1003 | #define EBI_STATUS_ECCACT_DEFAULT (_EBI_STATUS_ECCACT_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1004 | #define EBI_STATUS_TFTPIXEL0EMPTY (0x1UL << 8) /**< EBI_TFTPIXEL0 is empty. */ |
| AnnaBridge | 171:3a7713b1edbc | 1005 | #define _EBI_STATUS_TFTPIXEL0EMPTY_SHIFT 8 /**< Shift value for EBI_TFTPIXEL0EMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1006 | #define _EBI_STATUS_TFTPIXEL0EMPTY_MASK 0x100UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1007 | #define _EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1008 | #define EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1009 | #define EBI_STATUS_TFTPIXEL1EMPTY (0x1UL << 9) /**< EBI_TFTPIXEL1 is empty. */ |
| AnnaBridge | 171:3a7713b1edbc | 1010 | #define _EBI_STATUS_TFTPIXEL1EMPTY_SHIFT 9 /**< Shift value for EBI_TFTPIXEL1EMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1011 | #define _EBI_STATUS_TFTPIXEL1EMPTY_MASK 0x200UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1012 | #define _EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1013 | #define EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1014 | #define EBI_STATUS_TFTPIXELFULL (0x1UL << 10) /**< EBI_TFTPIXEL0 is full. */ |
| AnnaBridge | 171:3a7713b1edbc | 1015 | #define _EBI_STATUS_TFTPIXELFULL_SHIFT 10 /**< Shift value for EBI_TFTPIXELFULL */ |
| AnnaBridge | 171:3a7713b1edbc | 1016 | #define _EBI_STATUS_TFTPIXELFULL_MASK 0x400UL /**< Bit mask for EBI_TFTPIXELFULL */ |
| AnnaBridge | 171:3a7713b1edbc | 1017 | #define _EBI_STATUS_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1018 | #define EBI_STATUS_TFTPIXELFULL_DEFAULT (_EBI_STATUS_TFTPIXELFULL_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1019 | #define EBI_STATUS_DDACT (0x1UL << 12) /**< EBI Busy with Direct Drive Transactions. */ |
| AnnaBridge | 171:3a7713b1edbc | 1020 | #define _EBI_STATUS_DDACT_SHIFT 12 /**< Shift value for EBI_DDACT */ |
| AnnaBridge | 171:3a7713b1edbc | 1021 | #define _EBI_STATUS_DDACT_MASK 0x1000UL /**< Bit mask for EBI_DDACT */ |
| AnnaBridge | 171:3a7713b1edbc | 1022 | #define _EBI_STATUS_DDACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1023 | #define EBI_STATUS_DDACT_DEFAULT (_EBI_STATUS_DDACT_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1024 | #define EBI_STATUS_TFTDDEMPTY (0x1UL << 13) /**< EBI_TFTDD register is empty. */ |
| AnnaBridge | 171:3a7713b1edbc | 1025 | #define _EBI_STATUS_TFTDDEMPTY_SHIFT 13 /**< Shift value for EBI_TFTDDEMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1026 | #define _EBI_STATUS_TFTDDEMPTY_MASK 0x2000UL /**< Bit mask for EBI_TFTDDEMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1027 | #define _EBI_STATUS_TFTDDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1028 | #define EBI_STATUS_TFTDDEMPTY_DEFAULT (_EBI_STATUS_TFTDDEMPTY_DEFAULT << 13) /**< Shifted mode DEFAULT for EBI_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1029 | |
| AnnaBridge | 171:3a7713b1edbc | 1030 | /* Bit fields for EBI ECCPARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1031 | #define _EBI_ECCPARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_ECCPARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1032 | #define _EBI_ECCPARITY_MASK 0xFFFFFFFFUL /**< Mask for EBI_ECCPARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1033 | #define _EBI_ECCPARITY_ECCPARITY_SHIFT 0 /**< Shift value for EBI_ECCPARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1034 | #define _EBI_ECCPARITY_ECCPARITY_MASK 0xFFFFFFFFUL /**< Bit mask for EBI_ECCPARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1035 | #define _EBI_ECCPARITY_ECCPARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ECCPARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1036 | #define EBI_ECCPARITY_ECCPARITY_DEFAULT (_EBI_ECCPARITY_ECCPARITY_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ECCPARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1037 | |
| AnnaBridge | 171:3a7713b1edbc | 1038 | /* Bit fields for EBI TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1039 | #define _EBI_TFTCTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1040 | #define _EBI_TFTCTRL_MASK 0x01311F1FUL /**< Mask for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1041 | #define _EBI_TFTCTRL_DD_SHIFT 0 /**< Shift value for EBI_DD */ |
| AnnaBridge | 171:3a7713b1edbc | 1042 | #define _EBI_TFTCTRL_DD_MASK 0x3UL /**< Bit mask for EBI_DD */ |
| AnnaBridge | 171:3a7713b1edbc | 1043 | #define _EBI_TFTCTRL_DD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1044 | #define _EBI_TFTCTRL_DD_DISABLED 0x00000000UL /**< Mode DISABLED for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1045 | #define _EBI_TFTCTRL_DD_INTERNAL 0x00000001UL /**< Mode INTERNAL for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1046 | #define _EBI_TFTCTRL_DD_EXTERNAL 0x00000002UL /**< Mode EXTERNAL for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1047 | #define EBI_TFTCTRL_DD_DEFAULT (_EBI_TFTCTRL_DD_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1048 | #define EBI_TFTCTRL_DD_DISABLED (_EBI_TFTCTRL_DD_DISABLED << 0) /**< Shifted mode DISABLED for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1049 | #define EBI_TFTCTRL_DD_INTERNAL (_EBI_TFTCTRL_DD_INTERNAL << 0) /**< Shifted mode INTERNAL for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1050 | #define EBI_TFTCTRL_DD_EXTERNAL (_EBI_TFTCTRL_DD_EXTERNAL << 0) /**< Shifted mode EXTERNAL for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1051 | #define _EBI_TFTCTRL_MASKBLEND_SHIFT 2 /**< Shift value for EBI_MASKBLEND */ |
| AnnaBridge | 171:3a7713b1edbc | 1052 | #define _EBI_TFTCTRL_MASKBLEND_MASK 0x1CUL /**< Bit mask for EBI_MASKBLEND */ |
| AnnaBridge | 171:3a7713b1edbc | 1053 | #define _EBI_TFTCTRL_MASKBLEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1054 | #define _EBI_TFTCTRL_MASKBLEND_DISABLED 0x00000000UL /**< Mode DISABLED for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1055 | #define _EBI_TFTCTRL_MASKBLEND_IMASK 0x00000001UL /**< Mode IMASK for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1056 | #define _EBI_TFTCTRL_MASKBLEND_IALPHA 0x00000002UL /**< Mode IALPHA for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1057 | #define _EBI_TFTCTRL_MASKBLEND_IMASKIALPHA 0x00000003UL /**< Mode IMASKIALPHA for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1058 | #define _EBI_TFTCTRL_MASKBLEND_EMASK 0x00000005UL /**< Mode EMASK for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1059 | #define _EBI_TFTCTRL_MASKBLEND_EALPHA 0x00000006UL /**< Mode EALPHA for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1060 | #define _EBI_TFTCTRL_MASKBLEND_EMASKEALPHA 0x00000007UL /**< Mode EMASKEALPHA for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1061 | #define EBI_TFTCTRL_MASKBLEND_DEFAULT (_EBI_TFTCTRL_MASKBLEND_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1062 | #define EBI_TFTCTRL_MASKBLEND_DISABLED (_EBI_TFTCTRL_MASKBLEND_DISABLED << 2) /**< Shifted mode DISABLED for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1063 | #define EBI_TFTCTRL_MASKBLEND_IMASK (_EBI_TFTCTRL_MASKBLEND_IMASK << 2) /**< Shifted mode IMASK for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1064 | #define EBI_TFTCTRL_MASKBLEND_IALPHA (_EBI_TFTCTRL_MASKBLEND_IALPHA << 2) /**< Shifted mode IALPHA for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1065 | #define EBI_TFTCTRL_MASKBLEND_IMASKIALPHA (_EBI_TFTCTRL_MASKBLEND_IMASKIALPHA << 2) /**< Shifted mode IMASKIALPHA for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1066 | #define EBI_TFTCTRL_MASKBLEND_EMASK (_EBI_TFTCTRL_MASKBLEND_EMASK << 2) /**< Shifted mode EMASK for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1067 | #define EBI_TFTCTRL_MASKBLEND_EALPHA (_EBI_TFTCTRL_MASKBLEND_EALPHA << 2) /**< Shifted mode EALPHA for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1068 | #define EBI_TFTCTRL_MASKBLEND_EMASKEALPHA (_EBI_TFTCTRL_MASKBLEND_EMASKEALPHA << 2) /**< Shifted mode EMASKEALPHA for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1069 | #define EBI_TFTCTRL_SHIFTDCLKEN (0x1UL << 8) /**< TFT EBI_DCLK Shift Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1070 | #define _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT 8 /**< Shift value for EBI_SHIFTDCLKEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1071 | #define _EBI_TFTCTRL_SHIFTDCLKEN_MASK 0x100UL /**< Bit mask for EBI_SHIFTDCLKEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1072 | #define _EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1073 | #define EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT (_EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1074 | #define EBI_TFTCTRL_FBCTRIG (0x1UL << 9) /**< TFT Frame Base Copy Trigger */ |
| AnnaBridge | 171:3a7713b1edbc | 1075 | #define _EBI_TFTCTRL_FBCTRIG_SHIFT 9 /**< Shift value for EBI_FBCTRIG */ |
| AnnaBridge | 171:3a7713b1edbc | 1076 | #define _EBI_TFTCTRL_FBCTRIG_MASK 0x200UL /**< Bit mask for EBI_FBCTRIG */ |
| AnnaBridge | 171:3a7713b1edbc | 1077 | #define _EBI_TFTCTRL_FBCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1078 | #define _EBI_TFTCTRL_FBCTRIG_VSYNC 0x00000000UL /**< Mode VSYNC for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1079 | #define _EBI_TFTCTRL_FBCTRIG_HSYNC 0x00000001UL /**< Mode HSYNC for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1080 | #define EBI_TFTCTRL_FBCTRIG_DEFAULT (_EBI_TFTCTRL_FBCTRIG_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1081 | #define EBI_TFTCTRL_FBCTRIG_VSYNC (_EBI_TFTCTRL_FBCTRIG_VSYNC << 9) /**< Shifted mode VSYNC for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1082 | #define EBI_TFTCTRL_FBCTRIG_HSYNC (_EBI_TFTCTRL_FBCTRIG_HSYNC << 9) /**< Shifted mode HSYNC for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1083 | #define _EBI_TFTCTRL_INTERLEAVE_SHIFT 10 /**< Shift value for EBI_INTERLEAVE */ |
| AnnaBridge | 171:3a7713b1edbc | 1084 | #define _EBI_TFTCTRL_INTERLEAVE_MASK 0xC00UL /**< Bit mask for EBI_INTERLEAVE */ |
| AnnaBridge | 171:3a7713b1edbc | 1085 | #define _EBI_TFTCTRL_INTERLEAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1086 | #define _EBI_TFTCTRL_INTERLEAVE_UNLIMITED 0x00000000UL /**< Mode UNLIMITED for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1087 | #define _EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK 0x00000001UL /**< Mode ONEPERDCLK for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1088 | #define _EBI_TFTCTRL_INTERLEAVE_PORCH 0x00000002UL /**< Mode PORCH for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1089 | #define EBI_TFTCTRL_INTERLEAVE_DEFAULT (_EBI_TFTCTRL_INTERLEAVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1090 | #define EBI_TFTCTRL_INTERLEAVE_UNLIMITED (_EBI_TFTCTRL_INTERLEAVE_UNLIMITED << 10) /**< Shifted mode UNLIMITED for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1091 | #define EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK (_EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK << 10) /**< Shifted mode ONEPERDCLK for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1092 | #define EBI_TFTCTRL_INTERLEAVE_PORCH (_EBI_TFTCTRL_INTERLEAVE_PORCH << 10) /**< Shifted mode PORCH for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1093 | #define EBI_TFTCTRL_COLOR1SRC (0x1UL << 12) /**< Masking/Alpha Blending Color1 Source */ |
| AnnaBridge | 171:3a7713b1edbc | 1094 | #define _EBI_TFTCTRL_COLOR1SRC_SHIFT 12 /**< Shift value for EBI_COLOR1SRC */ |
| AnnaBridge | 171:3a7713b1edbc | 1095 | #define _EBI_TFTCTRL_COLOR1SRC_MASK 0x1000UL /**< Bit mask for EBI_COLOR1SRC */ |
| AnnaBridge | 171:3a7713b1edbc | 1096 | #define _EBI_TFTCTRL_COLOR1SRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1097 | #define _EBI_TFTCTRL_COLOR1SRC_MEM 0x00000000UL /**< Mode MEM for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1098 | #define _EBI_TFTCTRL_COLOR1SRC_PIXEL1 0x00000001UL /**< Mode PIXEL1 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1099 | #define EBI_TFTCTRL_COLOR1SRC_DEFAULT (_EBI_TFTCTRL_COLOR1SRC_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1100 | #define EBI_TFTCTRL_COLOR1SRC_MEM (_EBI_TFTCTRL_COLOR1SRC_MEM << 12) /**< Shifted mode MEM for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1101 | #define EBI_TFTCTRL_COLOR1SRC_PIXEL1 (_EBI_TFTCTRL_COLOR1SRC_PIXEL1 << 12) /**< Shifted mode PIXEL1 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1102 | #define EBI_TFTCTRL_WIDTH (0x1UL << 16) /**< TFT Transaction Width */ |
| AnnaBridge | 171:3a7713b1edbc | 1103 | #define _EBI_TFTCTRL_WIDTH_SHIFT 16 /**< Shift value for EBI_WIDTH */ |
| AnnaBridge | 171:3a7713b1edbc | 1104 | #define _EBI_TFTCTRL_WIDTH_MASK 0x10000UL /**< Bit mask for EBI_WIDTH */ |
| AnnaBridge | 171:3a7713b1edbc | 1105 | #define _EBI_TFTCTRL_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1106 | #define _EBI_TFTCTRL_WIDTH_BYTE 0x00000000UL /**< Mode BYTE for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1107 | #define _EBI_TFTCTRL_WIDTH_HALFWORD 0x00000001UL /**< Mode HALFWORD for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1108 | #define EBI_TFTCTRL_WIDTH_DEFAULT (_EBI_TFTCTRL_WIDTH_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1109 | #define EBI_TFTCTRL_WIDTH_BYTE (_EBI_TFTCTRL_WIDTH_BYTE << 16) /**< Shifted mode BYTE for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1110 | #define EBI_TFTCTRL_WIDTH_HALFWORD (_EBI_TFTCTRL_WIDTH_HALFWORD << 16) /**< Shifted mode HALFWORD for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1111 | #define _EBI_TFTCTRL_BANKSEL_SHIFT 20 /**< Shift value for EBI_BANKSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1112 | #define _EBI_TFTCTRL_BANKSEL_MASK 0x300000UL /**< Bit mask for EBI_BANKSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1113 | #define _EBI_TFTCTRL_BANKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1114 | #define _EBI_TFTCTRL_BANKSEL_BANK0 0x00000000UL /**< Mode BANK0 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1115 | #define _EBI_TFTCTRL_BANKSEL_BANK1 0x00000001UL /**< Mode BANK1 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1116 | #define _EBI_TFTCTRL_BANKSEL_BANK2 0x00000002UL /**< Mode BANK2 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1117 | #define _EBI_TFTCTRL_BANKSEL_BANK3 0x00000003UL /**< Mode BANK3 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1118 | #define EBI_TFTCTRL_BANKSEL_DEFAULT (_EBI_TFTCTRL_BANKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1119 | #define EBI_TFTCTRL_BANKSEL_BANK0 (_EBI_TFTCTRL_BANKSEL_BANK0 << 20) /**< Shifted mode BANK0 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1120 | #define EBI_TFTCTRL_BANKSEL_BANK1 (_EBI_TFTCTRL_BANKSEL_BANK1 << 20) /**< Shifted mode BANK1 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1121 | #define EBI_TFTCTRL_BANKSEL_BANK2 (_EBI_TFTCTRL_BANKSEL_BANK2 << 20) /**< Shifted mode BANK2 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1122 | #define EBI_TFTCTRL_BANKSEL_BANK3 (_EBI_TFTCTRL_BANKSEL_BANK3 << 20) /**< Shifted mode BANK3 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1123 | #define EBI_TFTCTRL_RGBMODE (0x1UL << 24) /**< TFT RGB Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 1124 | #define _EBI_TFTCTRL_RGBMODE_SHIFT 24 /**< Shift value for EBI_RGBMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 1125 | #define _EBI_TFTCTRL_RGBMODE_MASK 0x1000000UL /**< Bit mask for EBI_RGBMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 1126 | #define _EBI_TFTCTRL_RGBMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1127 | #define _EBI_TFTCTRL_RGBMODE_RGB565 0x00000000UL /**< Mode RGB565 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1128 | #define _EBI_TFTCTRL_RGBMODE_RGB555 0x00000001UL /**< Mode RGB555 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1129 | #define EBI_TFTCTRL_RGBMODE_DEFAULT (_EBI_TFTCTRL_RGBMODE_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1130 | #define EBI_TFTCTRL_RGBMODE_RGB565 (_EBI_TFTCTRL_RGBMODE_RGB565 << 24) /**< Shifted mode RGB565 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1131 | #define EBI_TFTCTRL_RGBMODE_RGB555 (_EBI_TFTCTRL_RGBMODE_RGB555 << 24) /**< Shifted mode RGB555 for EBI_TFTCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1132 | |
| AnnaBridge | 171:3a7713b1edbc | 1133 | /* Bit fields for EBI TFTSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1134 | #define _EBI_TFTSTATUS_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1135 | #define _EBI_TFTSTATUS_MASK 0x07FF07FFUL /**< Mask for EBI_TFTSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1136 | #define _EBI_TFTSTATUS_HCNT_SHIFT 0 /**< Shift value for EBI_HCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1137 | #define _EBI_TFTSTATUS_HCNT_MASK 0x7FFUL /**< Bit mask for EBI_HCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1138 | #define _EBI_TFTSTATUS_HCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1139 | #define EBI_TFTSTATUS_HCNT_DEFAULT (_EBI_TFTSTATUS_HCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1140 | #define _EBI_TFTSTATUS_VCNT_SHIFT 16 /**< Shift value for EBI_VCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1141 | #define _EBI_TFTSTATUS_VCNT_MASK 0x7FF0000UL /**< Bit mask for EBI_VCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1142 | #define _EBI_TFTSTATUS_VCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1143 | #define EBI_TFTSTATUS_VCNT_DEFAULT (_EBI_TFTSTATUS_VCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1144 | |
| AnnaBridge | 171:3a7713b1edbc | 1145 | /* Bit fields for EBI TFTFRAMEBASE */ |
| AnnaBridge | 171:3a7713b1edbc | 1146 | #define _EBI_TFTFRAMEBASE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTFRAMEBASE */ |
| AnnaBridge | 171:3a7713b1edbc | 1147 | #define _EBI_TFTFRAMEBASE_MASK 0x0FFFFFFFUL /**< Mask for EBI_TFTFRAMEBASE */ |
| AnnaBridge | 171:3a7713b1edbc | 1148 | #define _EBI_TFTFRAMEBASE_FRAMEBASE_SHIFT 0 /**< Shift value for EBI_FRAMEBASE */ |
| AnnaBridge | 171:3a7713b1edbc | 1149 | #define _EBI_TFTFRAMEBASE_FRAMEBASE_MASK 0xFFFFFFFUL /**< Bit mask for EBI_FRAMEBASE */ |
| AnnaBridge | 171:3a7713b1edbc | 1150 | #define _EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTFRAMEBASE */ |
| AnnaBridge | 171:3a7713b1edbc | 1151 | #define EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT (_EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTFRAMEBASE */ |
| AnnaBridge | 171:3a7713b1edbc | 1152 | |
| AnnaBridge | 171:3a7713b1edbc | 1153 | /* Bit fields for EBI TFTSTRIDE */ |
| AnnaBridge | 171:3a7713b1edbc | 1154 | #define _EBI_TFTSTRIDE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSTRIDE */ |
| AnnaBridge | 171:3a7713b1edbc | 1155 | #define _EBI_TFTSTRIDE_MASK 0x00000FFFUL /**< Mask for EBI_TFTSTRIDE */ |
| AnnaBridge | 171:3a7713b1edbc | 1156 | #define _EBI_TFTSTRIDE_HSTRIDE_SHIFT 0 /**< Shift value for EBI_HSTRIDE */ |
| AnnaBridge | 171:3a7713b1edbc | 1157 | #define _EBI_TFTSTRIDE_HSTRIDE_MASK 0xFFFUL /**< Bit mask for EBI_HSTRIDE */ |
| AnnaBridge | 171:3a7713b1edbc | 1158 | #define _EBI_TFTSTRIDE_HSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTRIDE */ |
| AnnaBridge | 171:3a7713b1edbc | 1159 | #define EBI_TFTSTRIDE_HSTRIDE_DEFAULT (_EBI_TFTSTRIDE_HSTRIDE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSTRIDE */ |
| AnnaBridge | 171:3a7713b1edbc | 1160 | |
| AnnaBridge | 171:3a7713b1edbc | 1161 | /* Bit fields for EBI TFTSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1162 | #define _EBI_TFTSIZE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1163 | #define _EBI_TFTSIZE_MASK 0x03FF03FFUL /**< Mask for EBI_TFTSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1164 | #define _EBI_TFTSIZE_HSZ_SHIFT 0 /**< Shift value for EBI_HSZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1165 | #define _EBI_TFTSIZE_HSZ_MASK 0x3FFUL /**< Bit mask for EBI_HSZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1166 | #define _EBI_TFTSIZE_HSZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1167 | #define EBI_TFTSIZE_HSZ_DEFAULT (_EBI_TFTSIZE_HSZ_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1168 | #define _EBI_TFTSIZE_VSZ_SHIFT 16 /**< Shift value for EBI_VSZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1169 | #define _EBI_TFTSIZE_VSZ_MASK 0x3FF0000UL /**< Bit mask for EBI_VSZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1170 | #define _EBI_TFTSIZE_VSZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1171 | #define EBI_TFTSIZE_VSZ_DEFAULT (_EBI_TFTSIZE_VSZ_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1172 | |
| AnnaBridge | 171:3a7713b1edbc | 1173 | /* Bit fields for EBI TFTHPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1174 | #define _EBI_TFTHPORCH_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTHPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1175 | #define _EBI_TFTHPORCH_MASK 0x33FCFF7FUL /**< Mask for EBI_TFTHPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1176 | #define _EBI_TFTHPORCH_HSYNC_SHIFT 0 /**< Shift value for EBI_HSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1177 | #define _EBI_TFTHPORCH_HSYNC_MASK 0x7FUL /**< Bit mask for EBI_HSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1178 | #define _EBI_TFTHPORCH_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1179 | #define EBI_TFTHPORCH_HSYNC_DEFAULT (_EBI_TFTHPORCH_HSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1180 | #define _EBI_TFTHPORCH_HFPORCH_SHIFT 8 /**< Shift value for EBI_HFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1181 | #define _EBI_TFTHPORCH_HFPORCH_MASK 0xFF00UL /**< Bit mask for EBI_HFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1182 | #define _EBI_TFTHPORCH_HFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1183 | #define EBI_TFTHPORCH_HFPORCH_DEFAULT (_EBI_TFTHPORCH_HFPORCH_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1184 | #define _EBI_TFTHPORCH_HBPORCH_SHIFT 18 /**< Shift value for EBI_HBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1185 | #define _EBI_TFTHPORCH_HBPORCH_MASK 0x3FC0000UL /**< Bit mask for EBI_HBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1186 | #define _EBI_TFTHPORCH_HBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1187 | #define EBI_TFTHPORCH_HBPORCH_DEFAULT (_EBI_TFTHPORCH_HBPORCH_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1188 | #define _EBI_TFTHPORCH_HSYNCSTART_SHIFT 28 /**< Shift value for EBI_HSYNCSTART */ |
| AnnaBridge | 171:3a7713b1edbc | 1189 | #define _EBI_TFTHPORCH_HSYNCSTART_MASK 0x30000000UL /**< Bit mask for EBI_HSYNCSTART */ |
| AnnaBridge | 171:3a7713b1edbc | 1190 | #define _EBI_TFTHPORCH_HSYNCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1191 | #define EBI_TFTHPORCH_HSYNCSTART_DEFAULT (_EBI_TFTHPORCH_HSYNCSTART_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1192 | |
| AnnaBridge | 171:3a7713b1edbc | 1193 | /* Bit fields for EBI TFTVPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1194 | #define _EBI_TFTVPORCH_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTVPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1195 | #define _EBI_TFTVPORCH_MASK 0x03FCFF7FUL /**< Mask for EBI_TFTVPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1196 | #define _EBI_TFTVPORCH_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1197 | #define _EBI_TFTVPORCH_VSYNC_MASK 0x7FUL /**< Bit mask for EBI_VSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1198 | #define _EBI_TFTVPORCH_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1199 | #define EBI_TFTVPORCH_VSYNC_DEFAULT (_EBI_TFTVPORCH_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1200 | #define _EBI_TFTVPORCH_VFPORCH_SHIFT 8 /**< Shift value for EBI_VFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1201 | #define _EBI_TFTVPORCH_VFPORCH_MASK 0xFF00UL /**< Bit mask for EBI_VFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1202 | #define _EBI_TFTVPORCH_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1203 | #define EBI_TFTVPORCH_VFPORCH_DEFAULT (_EBI_TFTVPORCH_VFPORCH_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1204 | #define _EBI_TFTVPORCH_VBPORCH_SHIFT 18 /**< Shift value for EBI_VBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1205 | #define _EBI_TFTVPORCH_VBPORCH_MASK 0x3FC0000UL /**< Bit mask for EBI_VBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1206 | #define _EBI_TFTVPORCH_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1207 | #define EBI_TFTVPORCH_VBPORCH_DEFAULT (_EBI_TFTVPORCH_VBPORCH_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1208 | |
| AnnaBridge | 171:3a7713b1edbc | 1209 | /* Bit fields for EBI TFTTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 1210 | #define _EBI_TFTTIMING_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 1211 | #define _EBI_TFTTIMING_MASK 0x337FF7FFUL /**< Mask for EBI_TFTTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 1212 | #define _EBI_TFTTIMING_DCLKPERIOD_SHIFT 0 /**< Shift value for EBI_DCLKPERIOD */ |
| AnnaBridge | 171:3a7713b1edbc | 1213 | #define _EBI_TFTTIMING_DCLKPERIOD_MASK 0x7FFUL /**< Bit mask for EBI_DCLKPERIOD */ |
| AnnaBridge | 171:3a7713b1edbc | 1214 | #define _EBI_TFTTIMING_DCLKPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 1215 | #define EBI_TFTTIMING_DCLKPERIOD_DEFAULT (_EBI_TFTTIMING_DCLKPERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 1216 | #define _EBI_TFTTIMING_TFTSTART_SHIFT 12 /**< Shift value for EBI_TFTSTART */ |
| AnnaBridge | 171:3a7713b1edbc | 1217 | #define _EBI_TFTTIMING_TFTSTART_MASK 0x7FF000UL /**< Bit mask for EBI_TFTSTART */ |
| AnnaBridge | 171:3a7713b1edbc | 1218 | #define _EBI_TFTTIMING_TFTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 1219 | #define EBI_TFTTIMING_TFTSTART_DEFAULT (_EBI_TFTTIMING_TFTSTART_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 1220 | #define _EBI_TFTTIMING_TFTSETUP_SHIFT 24 /**< Shift value for EBI_TFTSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1221 | #define _EBI_TFTTIMING_TFTSETUP_MASK 0x3000000UL /**< Bit mask for EBI_TFTSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1222 | #define _EBI_TFTTIMING_TFTSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 1223 | #define EBI_TFTTIMING_TFTSETUP_DEFAULT (_EBI_TFTTIMING_TFTSETUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 1224 | #define _EBI_TFTTIMING_TFTHOLD_SHIFT 28 /**< Shift value for EBI_TFTHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 1225 | #define _EBI_TFTTIMING_TFTHOLD_MASK 0x30000000UL /**< Bit mask for EBI_TFTHOLD */ |
| AnnaBridge | 171:3a7713b1edbc | 1226 | #define _EBI_TFTTIMING_TFTHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 1227 | #define EBI_TFTTIMING_TFTHOLD_DEFAULT (_EBI_TFTTIMING_TFTHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ |
| AnnaBridge | 171:3a7713b1edbc | 1228 | |
| AnnaBridge | 171:3a7713b1edbc | 1229 | /* Bit fields for EBI TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1230 | #define _EBI_TFTPOLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1231 | #define _EBI_TFTPOLARITY_MASK 0x0000001FUL /**< Mask for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1232 | #define EBI_TFTPOLARITY_CSPOL (0x1UL << 0) /**< TFT Chip Select Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 1233 | #define _EBI_TFTPOLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1234 | #define _EBI_TFTPOLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1235 | #define _EBI_TFTPOLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1236 | #define _EBI_TFTPOLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1237 | #define _EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1238 | #define EBI_TFTPOLARITY_CSPOL_DEFAULT (_EBI_TFTPOLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1239 | #define EBI_TFTPOLARITY_CSPOL_ACTIVELOW (_EBI_TFTPOLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1240 | #define EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1241 | #define EBI_TFTPOLARITY_DCLKPOL (0x1UL << 1) /**< TFT DCLK Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 1242 | #define _EBI_TFTPOLARITY_DCLKPOL_SHIFT 1 /**< Shift value for EBI_DCLKPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1243 | #define _EBI_TFTPOLARITY_DCLKPOL_MASK 0x2UL /**< Bit mask for EBI_DCLKPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1244 | #define _EBI_TFTPOLARITY_DCLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1245 | #define _EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING 0x00000000UL /**< Mode ACTIVEFALLING for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1246 | #define _EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING 0x00000001UL /**< Mode ACTIVERISING for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1247 | #define EBI_TFTPOLARITY_DCLKPOL_DEFAULT (_EBI_TFTPOLARITY_DCLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1248 | #define EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING << 1) /**< Shifted mode ACTIVEFALLING for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1249 | #define EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING << 1) /**< Shifted mode ACTIVERISING for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1250 | #define EBI_TFTPOLARITY_DATAENPOL (0x1UL << 2) /**< TFT DATAEN Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 1251 | #define _EBI_TFTPOLARITY_DATAENPOL_SHIFT 2 /**< Shift value for EBI_DATAENPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1252 | #define _EBI_TFTPOLARITY_DATAENPOL_MASK 0x4UL /**< Bit mask for EBI_DATAENPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1253 | #define _EBI_TFTPOLARITY_DATAENPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1254 | #define _EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1255 | #define _EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1256 | #define EBI_TFTPOLARITY_DATAENPOL_DEFAULT (_EBI_TFTPOLARITY_DATAENPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1257 | #define EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW (_EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1258 | #define EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1259 | #define EBI_TFTPOLARITY_HSYNCPOL (0x1UL << 3) /**< Address Latch Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 1260 | #define _EBI_TFTPOLARITY_HSYNCPOL_SHIFT 3 /**< Shift value for EBI_HSYNCPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1261 | #define _EBI_TFTPOLARITY_HSYNCPOL_MASK 0x8UL /**< Bit mask for EBI_HSYNCPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1262 | #define _EBI_TFTPOLARITY_HSYNCPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1263 | #define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1264 | #define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1265 | #define EBI_TFTPOLARITY_HSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_HSYNCPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1266 | #define EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1267 | #define EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1268 | #define EBI_TFTPOLARITY_VSYNCPOL (0x1UL << 4) /**< VSYNC Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 1269 | #define _EBI_TFTPOLARITY_VSYNCPOL_SHIFT 4 /**< Shift value for EBI_VSYNCPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1270 | #define _EBI_TFTPOLARITY_VSYNCPOL_MASK 0x10UL /**< Bit mask for EBI_VSYNCPOL */ |
| AnnaBridge | 171:3a7713b1edbc | 1271 | #define _EBI_TFTPOLARITY_VSYNCPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1272 | #define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1273 | #define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1274 | #define EBI_TFTPOLARITY_VSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_VSYNCPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1275 | #define EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1276 | #define EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ |
| AnnaBridge | 171:3a7713b1edbc | 1277 | |
| AnnaBridge | 171:3a7713b1edbc | 1278 | /* Bit fields for EBI TFTDD */ |
| AnnaBridge | 171:3a7713b1edbc | 1279 | #define _EBI_TFTDD_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTDD */ |
| AnnaBridge | 171:3a7713b1edbc | 1280 | #define _EBI_TFTDD_MASK 0x0000FFFFUL /**< Mask for EBI_TFTDD */ |
| AnnaBridge | 171:3a7713b1edbc | 1281 | #define _EBI_TFTDD_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ |
| AnnaBridge | 171:3a7713b1edbc | 1282 | #define _EBI_TFTDD_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */ |
| AnnaBridge | 171:3a7713b1edbc | 1283 | #define _EBI_TFTDD_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTDD */ |
| AnnaBridge | 171:3a7713b1edbc | 1284 | #define EBI_TFTDD_DATA_DEFAULT (_EBI_TFTDD_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTDD */ |
| AnnaBridge | 171:3a7713b1edbc | 1285 | |
| AnnaBridge | 171:3a7713b1edbc | 1286 | /* Bit fields for EBI TFTALPHA */ |
| AnnaBridge | 171:3a7713b1edbc | 1287 | #define _EBI_TFTALPHA_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTALPHA */ |
| AnnaBridge | 171:3a7713b1edbc | 1288 | #define _EBI_TFTALPHA_MASK 0x000001FFUL /**< Mask for EBI_TFTALPHA */ |
| AnnaBridge | 171:3a7713b1edbc | 1289 | #define _EBI_TFTALPHA_ALPHA_SHIFT 0 /**< Shift value for EBI_ALPHA */ |
| AnnaBridge | 171:3a7713b1edbc | 1290 | #define _EBI_TFTALPHA_ALPHA_MASK 0x1FFUL /**< Bit mask for EBI_ALPHA */ |
| AnnaBridge | 171:3a7713b1edbc | 1291 | #define _EBI_TFTALPHA_ALPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTALPHA */ |
| AnnaBridge | 171:3a7713b1edbc | 1292 | #define EBI_TFTALPHA_ALPHA_DEFAULT (_EBI_TFTALPHA_ALPHA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTALPHA */ |
| AnnaBridge | 171:3a7713b1edbc | 1293 | |
| AnnaBridge | 171:3a7713b1edbc | 1294 | /* Bit fields for EBI TFTPIXEL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1295 | #define _EBI_TFTPIXEL0_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1296 | #define _EBI_TFTPIXEL0_MASK 0x0000FFFFUL /**< Mask for EBI_TFTPIXEL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1297 | #define _EBI_TFTPIXEL0_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ |
| AnnaBridge | 171:3a7713b1edbc | 1298 | #define _EBI_TFTPIXEL0_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */ |
| AnnaBridge | 171:3a7713b1edbc | 1299 | #define _EBI_TFTPIXEL0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1300 | #define EBI_TFTPIXEL0_DATA_DEFAULT (_EBI_TFTPIXEL0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1301 | |
| AnnaBridge | 171:3a7713b1edbc | 1302 | /* Bit fields for EBI TFTPIXEL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1303 | #define _EBI_TFTPIXEL1_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1304 | #define _EBI_TFTPIXEL1_MASK 0x0000FFFFUL /**< Mask for EBI_TFTPIXEL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1305 | #define _EBI_TFTPIXEL1_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ |
| AnnaBridge | 171:3a7713b1edbc | 1306 | #define _EBI_TFTPIXEL1_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */ |
| AnnaBridge | 171:3a7713b1edbc | 1307 | #define _EBI_TFTPIXEL1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1308 | #define EBI_TFTPIXEL1_DATA_DEFAULT (_EBI_TFTPIXEL1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1309 | |
| AnnaBridge | 171:3a7713b1edbc | 1310 | /* Bit fields for EBI TFTPIXEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1311 | #define _EBI_TFTPIXEL_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1312 | #define _EBI_TFTPIXEL_MASK 0x0000FFFFUL /**< Mask for EBI_TFTPIXEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1313 | #define _EBI_TFTPIXEL_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ |
| AnnaBridge | 171:3a7713b1edbc | 1314 | #define _EBI_TFTPIXEL_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */ |
| AnnaBridge | 171:3a7713b1edbc | 1315 | #define _EBI_TFTPIXEL_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1316 | #define EBI_TFTPIXEL_DATA_DEFAULT (_EBI_TFTPIXEL_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL */ |
| AnnaBridge | 171:3a7713b1edbc | 1317 | |
| AnnaBridge | 171:3a7713b1edbc | 1318 | /* Bit fields for EBI TFTMASK */ |
| AnnaBridge | 171:3a7713b1edbc | 1319 | #define _EBI_TFTMASK_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTMASK */ |
| AnnaBridge | 171:3a7713b1edbc | 1320 | #define _EBI_TFTMASK_MASK 0x0000FFFFUL /**< Mask for EBI_TFTMASK */ |
| AnnaBridge | 171:3a7713b1edbc | 1321 | #define _EBI_TFTMASK_TFTMASK_SHIFT 0 /**< Shift value for EBI_TFTMASK */ |
| AnnaBridge | 171:3a7713b1edbc | 1322 | #define _EBI_TFTMASK_TFTMASK_MASK 0xFFFFUL /**< Bit mask for EBI_TFTMASK */ |
| AnnaBridge | 171:3a7713b1edbc | 1323 | #define _EBI_TFTMASK_TFTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTMASK */ |
| AnnaBridge | 171:3a7713b1edbc | 1324 | #define EBI_TFTMASK_TFTMASK_DEFAULT (_EBI_TFTMASK_TFTMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTMASK */ |
| AnnaBridge | 171:3a7713b1edbc | 1325 | |
| AnnaBridge | 171:3a7713b1edbc | 1326 | /* Bit fields for EBI IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1327 | #define _EBI_IF_RESETVALUE 0x00000000UL /**< Default value for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1328 | #define _EBI_IF_MASK 0x0000003FUL /**< Mask for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1329 | #define EBI_IF_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 1330 | #define _EBI_IF_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1331 | #define _EBI_IF_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1332 | #define _EBI_IF_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1333 | #define EBI_IF_VSYNC_DEFAULT (_EBI_IF_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1334 | #define EBI_IF_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 1335 | #define _EBI_IF_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1336 | #define _EBI_IF_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1337 | #define _EBI_IF_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1338 | #define EBI_IF_HSYNC_DEFAULT (_EBI_IF_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1339 | #define EBI_IF_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 1340 | #define _EBI_IF_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1341 | #define _EBI_IF_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1342 | #define _EBI_IF_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1343 | #define EBI_IF_VBPORCH_DEFAULT (_EBI_IF_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1344 | #define EBI_IF_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 1345 | #define _EBI_IF_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1346 | #define _EBI_IF_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1347 | #define _EBI_IF_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1348 | #define EBI_IF_VFPORCH_DEFAULT (_EBI_IF_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1349 | #define EBI_IF_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 1350 | #define _EBI_IF_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1351 | #define _EBI_IF_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1352 | #define _EBI_IF_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1353 | #define EBI_IF_DDEMPTY_DEFAULT (_EBI_IF_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1354 | #define EBI_IF_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 1355 | #define _EBI_IF_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ |
| AnnaBridge | 171:3a7713b1edbc | 1356 | #define _EBI_IF_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ |
| AnnaBridge | 171:3a7713b1edbc | 1357 | #define _EBI_IF_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1358 | #define EBI_IF_DDJIT_DEFAULT (_EBI_IF_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 1359 | |
| AnnaBridge | 171:3a7713b1edbc | 1360 | /* Bit fields for EBI IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1361 | #define _EBI_IFS_RESETVALUE 0x00000000UL /**< Default value for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1362 | #define _EBI_IFS_MASK 0x0000003FUL /**< Mask for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1363 | #define EBI_IFS_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag Set */ |
| AnnaBridge | 171:3a7713b1edbc | 1364 | #define _EBI_IFS_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1365 | #define _EBI_IFS_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1366 | #define _EBI_IFS_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1367 | #define EBI_IFS_VSYNC_DEFAULT (_EBI_IFS_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1368 | #define EBI_IFS_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag Set */ |
| AnnaBridge | 171:3a7713b1edbc | 1369 | #define _EBI_IFS_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1370 | #define _EBI_IFS_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1371 | #define _EBI_IFS_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1372 | #define EBI_IFS_HSYNC_DEFAULT (_EBI_IFS_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1373 | #define EBI_IFS_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag Set */ |
| AnnaBridge | 171:3a7713b1edbc | 1374 | #define _EBI_IFS_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1375 | #define _EBI_IFS_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1376 | #define _EBI_IFS_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1377 | #define EBI_IFS_VBPORCH_DEFAULT (_EBI_IFS_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1378 | #define EBI_IFS_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag Set */ |
| AnnaBridge | 171:3a7713b1edbc | 1379 | #define _EBI_IFS_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1380 | #define _EBI_IFS_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1381 | #define _EBI_IFS_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1382 | #define EBI_IFS_VFPORCH_DEFAULT (_EBI_IFS_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1383 | #define EBI_IFS_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag Set */ |
| AnnaBridge | 171:3a7713b1edbc | 1384 | #define _EBI_IFS_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1385 | #define _EBI_IFS_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1386 | #define _EBI_IFS_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1387 | #define EBI_IFS_DDEMPTY_DEFAULT (_EBI_IFS_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1388 | #define EBI_IFS_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag Set */ |
| AnnaBridge | 171:3a7713b1edbc | 1389 | #define _EBI_IFS_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ |
| AnnaBridge | 171:3a7713b1edbc | 1390 | #define _EBI_IFS_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ |
| AnnaBridge | 171:3a7713b1edbc | 1391 | #define _EBI_IFS_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1392 | #define EBI_IFS_DDJIT_DEFAULT (_EBI_IFS_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 1393 | |
| AnnaBridge | 171:3a7713b1edbc | 1394 | /* Bit fields for EBI IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1395 | #define _EBI_IFC_RESETVALUE 0x00000000UL /**< Default value for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1396 | #define _EBI_IFC_MASK 0x0000003FUL /**< Mask for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1397 | #define EBI_IFC_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 1398 | #define _EBI_IFC_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1399 | #define _EBI_IFC_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1400 | #define _EBI_IFC_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1401 | #define EBI_IFC_VSYNC_DEFAULT (_EBI_IFC_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1402 | #define EBI_IFC_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 1403 | #define _EBI_IFC_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1404 | #define _EBI_IFC_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1405 | #define _EBI_IFC_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1406 | #define EBI_IFC_HSYNC_DEFAULT (_EBI_IFC_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1407 | #define EBI_IFC_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 1408 | #define _EBI_IFC_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1409 | #define _EBI_IFC_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1410 | #define _EBI_IFC_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1411 | #define EBI_IFC_VBPORCH_DEFAULT (_EBI_IFC_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1412 | #define EBI_IFC_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 1413 | #define _EBI_IFC_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1414 | #define _EBI_IFC_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1415 | #define _EBI_IFC_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1416 | #define EBI_IFC_VFPORCH_DEFAULT (_EBI_IFC_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1417 | #define EBI_IFC_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 1418 | #define _EBI_IFC_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1419 | #define _EBI_IFC_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1420 | #define _EBI_IFC_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1421 | #define EBI_IFC_DDEMPTY_DEFAULT (_EBI_IFC_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1422 | #define EBI_IFC_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 1423 | #define _EBI_IFC_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ |
| AnnaBridge | 171:3a7713b1edbc | 1424 | #define _EBI_IFC_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ |
| AnnaBridge | 171:3a7713b1edbc | 1425 | #define _EBI_IFC_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1426 | #define EBI_IFC_DDJIT_DEFAULT (_EBI_IFC_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 1427 | |
| AnnaBridge | 171:3a7713b1edbc | 1428 | /* Bit fields for EBI IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1429 | #define _EBI_IEN_RESETVALUE 0x00000000UL /**< Default value for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1430 | #define _EBI_IEN_MASK 0x0000003FUL /**< Mask for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1431 | #define EBI_IEN_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1432 | #define _EBI_IEN_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1433 | #define _EBI_IEN_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1434 | #define _EBI_IEN_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1435 | #define EBI_IEN_VSYNC_DEFAULT (_EBI_IEN_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1436 | #define EBI_IEN_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1437 | #define _EBI_IEN_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1438 | #define _EBI_IEN_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1439 | #define _EBI_IEN_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1440 | #define EBI_IEN_HSYNC_DEFAULT (_EBI_IEN_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1441 | #define EBI_IEN_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1442 | #define _EBI_IEN_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1443 | #define _EBI_IEN_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1444 | #define _EBI_IEN_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1445 | #define EBI_IEN_VBPORCH_DEFAULT (_EBI_IEN_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1446 | #define EBI_IEN_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1447 | #define _EBI_IEN_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1448 | #define _EBI_IEN_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ |
| AnnaBridge | 171:3a7713b1edbc | 1449 | #define _EBI_IEN_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1450 | #define EBI_IEN_VFPORCH_DEFAULT (_EBI_IEN_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1451 | #define EBI_IEN_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1452 | #define _EBI_IEN_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1453 | #define _EBI_IEN_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ |
| AnnaBridge | 171:3a7713b1edbc | 1454 | #define _EBI_IEN_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1455 | #define EBI_IEN_DDEMPTY_DEFAULT (_EBI_IEN_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1456 | #define EBI_IEN_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1457 | #define _EBI_IEN_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ |
| AnnaBridge | 171:3a7713b1edbc | 1458 | #define _EBI_IEN_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ |
| AnnaBridge | 171:3a7713b1edbc | 1459 | #define _EBI_IEN_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1460 | #define EBI_IEN_DDJIT_DEFAULT (_EBI_IEN_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 1461 | |
| AnnaBridge | 171:3a7713b1edbc | 1462 | /** @} End of group EFM32LG_EBI */ |
| AnnaBridge | 171:3a7713b1edbc | 1463 | /** @} End of group Parts */ |
| AnnaBridge | 171:3a7713b1edbc | 1464 |
