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TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/efm32hg_dma.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32hg_dma.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32HG_DMA register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32HG_DMA
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32HG_DMA Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IM uint32_t STATUS; /**< DMA Status Registers */
AnnaBridge 171:3a7713b1edbc 44 __OM uint32_t CONFIG; /**< DMA Configuration Register */
AnnaBridge 171:3a7713b1edbc 45 __IOM uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
AnnaBridge 171:3a7713b1edbc 46 __IM uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
AnnaBridge 171:3a7713b1edbc 47 __IM uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
AnnaBridge 171:3a7713b1edbc 48 __OM uint32_t CHSWREQ; /**< Channel Software Request Register */
AnnaBridge 171:3a7713b1edbc 49 __IOM uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
AnnaBridge 171:3a7713b1edbc 50 __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
AnnaBridge 171:3a7713b1edbc 51 __IOM uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
AnnaBridge 171:3a7713b1edbc 52 __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
AnnaBridge 171:3a7713b1edbc 53 __IOM uint32_t CHENS; /**< Channel Enable Set Register */
AnnaBridge 171:3a7713b1edbc 54 __OM uint32_t CHENC; /**< Channel Enable Clear Register */
AnnaBridge 171:3a7713b1edbc 55 __IOM uint32_t CHALTS; /**< Channel Alternate Set Register */
AnnaBridge 171:3a7713b1edbc 56 __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */
AnnaBridge 171:3a7713b1edbc 57 __IOM uint32_t CHPRIS; /**< Channel Priority Set Register */
AnnaBridge 171:3a7713b1edbc 58 __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
AnnaBridge 171:3a7713b1edbc 59 uint32_t RESERVED0[3]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 60 __IOM uint32_t ERRORC; /**< Bus Error Clear Register */
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 uint32_t RESERVED1[880]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 63 __IM uint32_t CHREQSTATUS; /**< Channel Request Status */
AnnaBridge 171:3a7713b1edbc 64 uint32_t RESERVED2[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 65 __IM uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 uint32_t RESERVED3[121]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 68 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 69 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 70 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 71 __IOM uint32_t IEN; /**< Interrupt Enable register */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 uint32_t RESERVED4[60]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 74 DMA_CH_TypeDef CH[6]; /**< Channel registers */
AnnaBridge 171:3a7713b1edbc 75 } DMA_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 78 * @defgroup EFM32HG_DMA_BitFields
AnnaBridge 171:3a7713b1edbc 79 * @{
AnnaBridge 171:3a7713b1edbc 80 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 /* Bit fields for DMA STATUS */
AnnaBridge 171:3a7713b1edbc 83 #define _DMA_STATUS_RESETVALUE 0x10050000UL /**< Default value for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 84 #define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 85 #define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */
AnnaBridge 171:3a7713b1edbc 86 #define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */
AnnaBridge 171:3a7713b1edbc 87 #define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
AnnaBridge 171:3a7713b1edbc 88 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 89 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 90 #define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */
AnnaBridge 171:3a7713b1edbc 91 #define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */
AnnaBridge 171:3a7713b1edbc 92 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 93 #define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 94 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 95 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 96 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 97 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 98 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 99 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 100 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 101 #define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 102 #define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 103 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 104 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 105 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 106 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 107 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 108 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 109 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 110 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 111 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 112 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 113 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 114 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 115 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 116 #define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */
AnnaBridge 171:3a7713b1edbc 117 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */
AnnaBridge 171:3a7713b1edbc 118 #define _DMA_STATUS_CHNUM_DEFAULT 0x00000005UL /**< Mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 119 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 /* Bit fields for DMA CONFIG */
AnnaBridge 171:3a7713b1edbc 122 #define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 123 #define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 124 #define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */
AnnaBridge 171:3a7713b1edbc 125 #define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */
AnnaBridge 171:3a7713b1edbc 126 #define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
AnnaBridge 171:3a7713b1edbc 127 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 128 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 129 #define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */
AnnaBridge 171:3a7713b1edbc 130 #define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */
AnnaBridge 171:3a7713b1edbc 131 #define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */
AnnaBridge 171:3a7713b1edbc 132 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 133 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 /* Bit fields for DMA CTRLBASE */
AnnaBridge 171:3a7713b1edbc 136 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 137 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 138 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 139 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 140 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 141 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 /* Bit fields for DMA ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 144 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL /**< Default value for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 145 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 146 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 147 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 148 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 149 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 /* Bit fields for DMA CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 152 #define _DMA_CHWAITSTATUS_RESETVALUE 0x0000003FUL /**< Default value for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 153 #define _DMA_CHWAITSTATUS_MASK 0x0000003FUL /**< Mask for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 154 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 155 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 156 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 157 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 158 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 159 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 160 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 161 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 162 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 163 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 164 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 165 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 166 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 167 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 168 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 169 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 170 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 171 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 172 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 173 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 174 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 175 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 176 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 177 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 178 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 179 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 180 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 181 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 182 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 183 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 /* Bit fields for DMA CHSWREQ */
AnnaBridge 171:3a7713b1edbc 186 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 187 #define _DMA_CHSWREQ_MASK 0x0000003FUL /**< Mask for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 188 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */
AnnaBridge 171:3a7713b1edbc 189 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */
AnnaBridge 171:3a7713b1edbc 190 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */
AnnaBridge 171:3a7713b1edbc 191 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 192 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 193 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */
AnnaBridge 171:3a7713b1edbc 194 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */
AnnaBridge 171:3a7713b1edbc 195 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */
AnnaBridge 171:3a7713b1edbc 196 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 197 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 198 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */
AnnaBridge 171:3a7713b1edbc 199 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */
AnnaBridge 171:3a7713b1edbc 200 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */
AnnaBridge 171:3a7713b1edbc 201 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 202 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 203 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */
AnnaBridge 171:3a7713b1edbc 204 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */
AnnaBridge 171:3a7713b1edbc 205 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */
AnnaBridge 171:3a7713b1edbc 206 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 207 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 208 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */
AnnaBridge 171:3a7713b1edbc 209 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */
AnnaBridge 171:3a7713b1edbc 210 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */
AnnaBridge 171:3a7713b1edbc 211 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 212 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 213 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */
AnnaBridge 171:3a7713b1edbc 214 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */
AnnaBridge 171:3a7713b1edbc 215 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */
AnnaBridge 171:3a7713b1edbc 216 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 217 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 218
AnnaBridge 171:3a7713b1edbc 219 /* Bit fields for DMA CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 220 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 221 #define _DMA_CHUSEBURSTS_MASK 0x0000003FUL /**< Mask for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 222 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */
AnnaBridge 171:3a7713b1edbc 223 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */
AnnaBridge 171:3a7713b1edbc 224 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */
AnnaBridge 171:3a7713b1edbc 225 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 226 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 227 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 228 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 229 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 230 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 231 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */
AnnaBridge 171:3a7713b1edbc 232 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */
AnnaBridge 171:3a7713b1edbc 233 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */
AnnaBridge 171:3a7713b1edbc 234 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 235 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 236 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */
AnnaBridge 171:3a7713b1edbc 237 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */
AnnaBridge 171:3a7713b1edbc 238 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */
AnnaBridge 171:3a7713b1edbc 239 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 240 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 241 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */
AnnaBridge 171:3a7713b1edbc 242 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */
AnnaBridge 171:3a7713b1edbc 243 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */
AnnaBridge 171:3a7713b1edbc 244 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 245 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 246 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */
AnnaBridge 171:3a7713b1edbc 247 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */
AnnaBridge 171:3a7713b1edbc 248 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */
AnnaBridge 171:3a7713b1edbc 249 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 250 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 251 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */
AnnaBridge 171:3a7713b1edbc 252 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */
AnnaBridge 171:3a7713b1edbc 253 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */
AnnaBridge 171:3a7713b1edbc 254 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 255 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 256
AnnaBridge 171:3a7713b1edbc 257 /* Bit fields for DMA CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 258 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 259 #define _DMA_CHUSEBURSTC_MASK 0x0000003FUL /**< Mask for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 260 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 261 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */
AnnaBridge 171:3a7713b1edbc 262 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */
AnnaBridge 171:3a7713b1edbc 263 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 264 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 265 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 266 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */
AnnaBridge 171:3a7713b1edbc 267 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */
AnnaBridge 171:3a7713b1edbc 268 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 269 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 270 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 271 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */
AnnaBridge 171:3a7713b1edbc 272 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */
AnnaBridge 171:3a7713b1edbc 273 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 274 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 275 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 276 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */
AnnaBridge 171:3a7713b1edbc 277 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */
AnnaBridge 171:3a7713b1edbc 278 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 279 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 280 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 281 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */
AnnaBridge 171:3a7713b1edbc 282 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */
AnnaBridge 171:3a7713b1edbc 283 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 284 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 285 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 286 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */
AnnaBridge 171:3a7713b1edbc 287 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */
AnnaBridge 171:3a7713b1edbc 288 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 289 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 290
AnnaBridge 171:3a7713b1edbc 291 /* Bit fields for DMA CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 292 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 293 #define _DMA_CHREQMASKS_MASK 0x0000003FUL /**< Mask for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 294 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 295 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */
AnnaBridge 171:3a7713b1edbc 296 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */
AnnaBridge 171:3a7713b1edbc 297 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 298 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 299 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 300 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */
AnnaBridge 171:3a7713b1edbc 301 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */
AnnaBridge 171:3a7713b1edbc 302 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 303 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 304 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 305 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */
AnnaBridge 171:3a7713b1edbc 306 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */
AnnaBridge 171:3a7713b1edbc 307 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 308 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 309 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 310 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */
AnnaBridge 171:3a7713b1edbc 311 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */
AnnaBridge 171:3a7713b1edbc 312 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 313 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 314 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 315 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */
AnnaBridge 171:3a7713b1edbc 316 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */
AnnaBridge 171:3a7713b1edbc 317 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 318 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 319 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 320 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */
AnnaBridge 171:3a7713b1edbc 321 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */
AnnaBridge 171:3a7713b1edbc 322 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 323 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 /* Bit fields for DMA CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 326 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 327 #define _DMA_CHREQMASKC_MASK 0x0000003FUL /**< Mask for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 328 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 329 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */
AnnaBridge 171:3a7713b1edbc 330 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */
AnnaBridge 171:3a7713b1edbc 331 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 332 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 333 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 334 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */
AnnaBridge 171:3a7713b1edbc 335 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */
AnnaBridge 171:3a7713b1edbc 336 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 337 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 338 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 339 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */
AnnaBridge 171:3a7713b1edbc 340 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */
AnnaBridge 171:3a7713b1edbc 341 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 342 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 343 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 344 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */
AnnaBridge 171:3a7713b1edbc 345 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */
AnnaBridge 171:3a7713b1edbc 346 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 347 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 348 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 349 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */
AnnaBridge 171:3a7713b1edbc 350 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */
AnnaBridge 171:3a7713b1edbc 351 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 352 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 353 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 354 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */
AnnaBridge 171:3a7713b1edbc 355 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */
AnnaBridge 171:3a7713b1edbc 356 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 357 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 /* Bit fields for DMA CHENS */
AnnaBridge 171:3a7713b1edbc 360 #define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 361 #define _DMA_CHENS_MASK 0x0000003FUL /**< Mask for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 362 #define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */
AnnaBridge 171:3a7713b1edbc 363 #define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */
AnnaBridge 171:3a7713b1edbc 364 #define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */
AnnaBridge 171:3a7713b1edbc 365 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 366 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 367 #define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */
AnnaBridge 171:3a7713b1edbc 368 #define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */
AnnaBridge 171:3a7713b1edbc 369 #define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */
AnnaBridge 171:3a7713b1edbc 370 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 371 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 372 #define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */
AnnaBridge 171:3a7713b1edbc 373 #define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */
AnnaBridge 171:3a7713b1edbc 374 #define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */
AnnaBridge 171:3a7713b1edbc 375 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 376 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 377 #define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */
AnnaBridge 171:3a7713b1edbc 378 #define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */
AnnaBridge 171:3a7713b1edbc 379 #define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */
AnnaBridge 171:3a7713b1edbc 380 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 381 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 382 #define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */
AnnaBridge 171:3a7713b1edbc 383 #define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */
AnnaBridge 171:3a7713b1edbc 384 #define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */
AnnaBridge 171:3a7713b1edbc 385 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 386 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 387 #define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */
AnnaBridge 171:3a7713b1edbc 388 #define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */
AnnaBridge 171:3a7713b1edbc 389 #define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */
AnnaBridge 171:3a7713b1edbc 390 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 391 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 392
AnnaBridge 171:3a7713b1edbc 393 /* Bit fields for DMA CHENC */
AnnaBridge 171:3a7713b1edbc 394 #define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 395 #define _DMA_CHENC_MASK 0x0000003FUL /**< Mask for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 396 #define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */
AnnaBridge 171:3a7713b1edbc 397 #define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */
AnnaBridge 171:3a7713b1edbc 398 #define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */
AnnaBridge 171:3a7713b1edbc 399 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 400 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 401 #define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */
AnnaBridge 171:3a7713b1edbc 402 #define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */
AnnaBridge 171:3a7713b1edbc 403 #define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */
AnnaBridge 171:3a7713b1edbc 404 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 405 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 406 #define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */
AnnaBridge 171:3a7713b1edbc 407 #define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */
AnnaBridge 171:3a7713b1edbc 408 #define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */
AnnaBridge 171:3a7713b1edbc 409 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 410 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 411 #define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */
AnnaBridge 171:3a7713b1edbc 412 #define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */
AnnaBridge 171:3a7713b1edbc 413 #define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */
AnnaBridge 171:3a7713b1edbc 414 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 415 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 416 #define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */
AnnaBridge 171:3a7713b1edbc 417 #define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */
AnnaBridge 171:3a7713b1edbc 418 #define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */
AnnaBridge 171:3a7713b1edbc 419 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 420 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 421 #define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */
AnnaBridge 171:3a7713b1edbc 422 #define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */
AnnaBridge 171:3a7713b1edbc 423 #define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */
AnnaBridge 171:3a7713b1edbc 424 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 425 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 /* Bit fields for DMA CHALTS */
AnnaBridge 171:3a7713b1edbc 428 #define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 429 #define _DMA_CHALTS_MASK 0x0000003FUL /**< Mask for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 430 #define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 431 #define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */
AnnaBridge 171:3a7713b1edbc 432 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */
AnnaBridge 171:3a7713b1edbc 433 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 434 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 435 #define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 436 #define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */
AnnaBridge 171:3a7713b1edbc 437 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */
AnnaBridge 171:3a7713b1edbc 438 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 439 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 440 #define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 441 #define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */
AnnaBridge 171:3a7713b1edbc 442 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */
AnnaBridge 171:3a7713b1edbc 443 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 444 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 445 #define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 446 #define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */
AnnaBridge 171:3a7713b1edbc 447 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */
AnnaBridge 171:3a7713b1edbc 448 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 449 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 450 #define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 451 #define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */
AnnaBridge 171:3a7713b1edbc 452 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */
AnnaBridge 171:3a7713b1edbc 453 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 454 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 455 #define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 456 #define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */
AnnaBridge 171:3a7713b1edbc 457 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */
AnnaBridge 171:3a7713b1edbc 458 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 459 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 460
AnnaBridge 171:3a7713b1edbc 461 /* Bit fields for DMA CHALTC */
AnnaBridge 171:3a7713b1edbc 462 #define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 463 #define _DMA_CHALTC_MASK 0x0000003FUL /**< Mask for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 464 #define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 465 #define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */
AnnaBridge 171:3a7713b1edbc 466 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */
AnnaBridge 171:3a7713b1edbc 467 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 468 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 469 #define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 470 #define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */
AnnaBridge 171:3a7713b1edbc 471 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */
AnnaBridge 171:3a7713b1edbc 472 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 473 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 474 #define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 475 #define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */
AnnaBridge 171:3a7713b1edbc 476 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */
AnnaBridge 171:3a7713b1edbc 477 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 478 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 479 #define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 480 #define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */
AnnaBridge 171:3a7713b1edbc 481 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */
AnnaBridge 171:3a7713b1edbc 482 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 483 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 484 #define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 485 #define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */
AnnaBridge 171:3a7713b1edbc 486 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */
AnnaBridge 171:3a7713b1edbc 487 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 488 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 489 #define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 490 #define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */
AnnaBridge 171:3a7713b1edbc 491 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */
AnnaBridge 171:3a7713b1edbc 492 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 493 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 /* Bit fields for DMA CHPRIS */
AnnaBridge 171:3a7713b1edbc 496 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 497 #define _DMA_CHPRIS_MASK 0x0000003FUL /**< Mask for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 498 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */
AnnaBridge 171:3a7713b1edbc 499 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */
AnnaBridge 171:3a7713b1edbc 500 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */
AnnaBridge 171:3a7713b1edbc 501 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 502 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 503 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */
AnnaBridge 171:3a7713b1edbc 504 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */
AnnaBridge 171:3a7713b1edbc 505 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */
AnnaBridge 171:3a7713b1edbc 506 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 507 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 508 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */
AnnaBridge 171:3a7713b1edbc 509 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */
AnnaBridge 171:3a7713b1edbc 510 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */
AnnaBridge 171:3a7713b1edbc 511 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 512 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 513 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */
AnnaBridge 171:3a7713b1edbc 514 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */
AnnaBridge 171:3a7713b1edbc 515 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */
AnnaBridge 171:3a7713b1edbc 516 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 517 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 518 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */
AnnaBridge 171:3a7713b1edbc 519 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */
AnnaBridge 171:3a7713b1edbc 520 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */
AnnaBridge 171:3a7713b1edbc 521 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 522 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 523 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */
AnnaBridge 171:3a7713b1edbc 524 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */
AnnaBridge 171:3a7713b1edbc 525 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */
AnnaBridge 171:3a7713b1edbc 526 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 527 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 528
AnnaBridge 171:3a7713b1edbc 529 /* Bit fields for DMA CHPRIC */
AnnaBridge 171:3a7713b1edbc 530 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 531 #define _DMA_CHPRIC_MASK 0x0000003FUL /**< Mask for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 532 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 533 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */
AnnaBridge 171:3a7713b1edbc 534 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */
AnnaBridge 171:3a7713b1edbc 535 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 536 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 537 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 538 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */
AnnaBridge 171:3a7713b1edbc 539 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */
AnnaBridge 171:3a7713b1edbc 540 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 541 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 542 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 543 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */
AnnaBridge 171:3a7713b1edbc 544 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */
AnnaBridge 171:3a7713b1edbc 545 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 546 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 547 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 548 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */
AnnaBridge 171:3a7713b1edbc 549 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */
AnnaBridge 171:3a7713b1edbc 550 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 551 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 552 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 553 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */
AnnaBridge 171:3a7713b1edbc 554 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */
AnnaBridge 171:3a7713b1edbc 555 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 556 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 557 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 558 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */
AnnaBridge 171:3a7713b1edbc 559 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */
AnnaBridge 171:3a7713b1edbc 560 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 561 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 562
AnnaBridge 171:3a7713b1edbc 563 /* Bit fields for DMA ERRORC */
AnnaBridge 171:3a7713b1edbc 564 #define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 565 #define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 566 #define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */
AnnaBridge 171:3a7713b1edbc 567 #define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 568 #define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 569 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 570 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 571
AnnaBridge 171:3a7713b1edbc 572 /* Bit fields for DMA CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 573 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 574 #define _DMA_CHREQSTATUS_MASK 0x0000003FUL /**< Mask for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 575 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */
AnnaBridge 171:3a7713b1edbc 576 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */
AnnaBridge 171:3a7713b1edbc 577 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */
AnnaBridge 171:3a7713b1edbc 578 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 579 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 580 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */
AnnaBridge 171:3a7713b1edbc 581 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */
AnnaBridge 171:3a7713b1edbc 582 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */
AnnaBridge 171:3a7713b1edbc 583 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 584 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 585 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */
AnnaBridge 171:3a7713b1edbc 586 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */
AnnaBridge 171:3a7713b1edbc 587 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */
AnnaBridge 171:3a7713b1edbc 588 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 589 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 590 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */
AnnaBridge 171:3a7713b1edbc 591 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */
AnnaBridge 171:3a7713b1edbc 592 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */
AnnaBridge 171:3a7713b1edbc 593 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 594 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 595 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */
AnnaBridge 171:3a7713b1edbc 596 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */
AnnaBridge 171:3a7713b1edbc 597 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */
AnnaBridge 171:3a7713b1edbc 598 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 599 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 600 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */
AnnaBridge 171:3a7713b1edbc 601 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */
AnnaBridge 171:3a7713b1edbc 602 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */
AnnaBridge 171:3a7713b1edbc 603 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 604 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 605
AnnaBridge 171:3a7713b1edbc 606 /* Bit fields for DMA CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 607 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 608 #define _DMA_CHSREQSTATUS_MASK 0x0000003FUL /**< Mask for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 609 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */
AnnaBridge 171:3a7713b1edbc 610 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 611 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 612 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 613 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 614 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */
AnnaBridge 171:3a7713b1edbc 615 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 616 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 617 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 618 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 619 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */
AnnaBridge 171:3a7713b1edbc 620 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 621 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 622 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 623 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 624 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */
AnnaBridge 171:3a7713b1edbc 625 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 626 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 627 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 628 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 629 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */
AnnaBridge 171:3a7713b1edbc 630 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 631 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 632 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 633 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 634 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */
AnnaBridge 171:3a7713b1edbc 635 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 636 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 637 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 638 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 639
AnnaBridge 171:3a7713b1edbc 640 /* Bit fields for DMA IF */
AnnaBridge 171:3a7713b1edbc 641 #define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */
AnnaBridge 171:3a7713b1edbc 642 #define _DMA_IF_MASK 0x8000003FUL /**< Mask for DMA_IF */
AnnaBridge 171:3a7713b1edbc 643 #define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 644 #define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 645 #define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 646 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 647 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 648 #define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 649 #define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 650 #define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 651 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 652 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 653 #define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 654 #define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 655 #define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 656 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 657 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 658 #define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 659 #define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 660 #define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 661 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 662 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 663 #define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 664 #define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 665 #define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 666 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 667 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 668 #define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 669 #define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 670 #define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 671 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 672 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 673 #define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 674 #define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 675 #define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 676 #define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 677 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679 /* Bit fields for DMA IFS */
AnnaBridge 171:3a7713b1edbc 680 #define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 681 #define _DMA_IFS_MASK 0x8000003FUL /**< Mask for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 682 #define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 683 #define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 684 #define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 685 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 686 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 687 #define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 688 #define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 689 #define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 690 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 691 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 692 #define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 693 #define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 694 #define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 695 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 696 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 697 #define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 698 #define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 699 #define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 700 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 701 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 702 #define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 703 #define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 704 #define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 705 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 706 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 707 #define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 708 #define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 709 #define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 710 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 711 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 712 #define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 713 #define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 714 #define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 715 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 716 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 717
AnnaBridge 171:3a7713b1edbc 718 /* Bit fields for DMA IFC */
AnnaBridge 171:3a7713b1edbc 719 #define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 720 #define _DMA_IFC_MASK 0x8000003FUL /**< Mask for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 721 #define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 722 #define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 723 #define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 724 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 725 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 726 #define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 727 #define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 728 #define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 729 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 730 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 731 #define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 732 #define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 733 #define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 734 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 735 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 736 #define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 737 #define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 738 #define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 739 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 740 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 741 #define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 742 #define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 743 #define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 744 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 745 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 746 #define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 747 #define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 748 #define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 749 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 750 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 751 #define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 752 #define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 753 #define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 754 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 755 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 756
AnnaBridge 171:3a7713b1edbc 757 /* Bit fields for DMA IEN */
AnnaBridge 171:3a7713b1edbc 758 #define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 759 #define _DMA_IEN_MASK 0x8000003FUL /**< Mask for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 760 #define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 761 #define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 762 #define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 763 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 764 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 765 #define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 766 #define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 767 #define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 768 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 769 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 770 #define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 771 #define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 772 #define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 773 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 774 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 775 #define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 776 #define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 777 #define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 778 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 779 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 780 #define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 781 #define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 782 #define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 783 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 784 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 785 #define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 786 #define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 787 #define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 788 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 789 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 790 #define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */
AnnaBridge 171:3a7713b1edbc 791 #define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 792 #define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 793 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 794 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 795
AnnaBridge 171:3a7713b1edbc 796 /* Bit fields for DMA CH_CTRL */
AnnaBridge 171:3a7713b1edbc 797 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 798 #define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 799 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */
AnnaBridge 171:3a7713b1edbc 800 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */
AnnaBridge 171:3a7713b1edbc 801 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 802 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 803 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 804 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 805 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 806 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 807 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 808 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 809 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 810 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 811 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 812 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 813 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 814 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 815 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 816 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 817 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 818 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 819 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 820 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 821 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 822 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 823 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 824 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 825 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 826 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 827 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 828 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 829 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 830 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 831 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 832 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 833 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 834 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 835 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 836 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 837 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 838 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 839 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 840 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 841 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 842 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 843 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 844 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 845 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 846 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 847 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 848 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 849 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 850 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 851 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 852 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 853 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 854 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 855 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 856 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 857 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 858 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 859 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 860 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 861 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 862 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 863 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 864 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 865 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */
AnnaBridge 171:3a7713b1edbc 866 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */
AnnaBridge 171:3a7713b1edbc 867 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 868 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 869 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 870 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 871 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 872 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 873 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 874 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 875 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 876 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 877 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 878 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 879 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 880 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 881 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 882 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 883 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 884 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 885 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 886 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 887 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 888 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 889
AnnaBridge 171:3a7713b1edbc 890 /** @} End of group EFM32HG_DMA */
AnnaBridge 171:3a7713b1edbc 891 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 892