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TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/efm32hg_cmu.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32hg_cmu.h |
AnnaBridge | 171:3a7713b1edbc | 3 | * @brief EFM32HG_CMU register and bit field definitions |
AnnaBridge | 171:3a7713b1edbc | 4 | * @version 5.1.2 |
AnnaBridge | 171:3a7713b1edbc | 5 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 6 | * @section License |
AnnaBridge | 171:3a7713b1edbc | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * Permission is granted to anyone to use this software for any purpose, |
AnnaBridge | 171:3a7713b1edbc | 11 | * including commercial applications, and to alter it and redistribute it |
AnnaBridge | 171:3a7713b1edbc | 12 | * freely, subject to the following restrictions: |
AnnaBridge | 171:3a7713b1edbc | 13 | * |
AnnaBridge | 171:3a7713b1edbc | 14 | * 1. The origin of this software must not be misrepresented; you must not |
AnnaBridge | 171:3a7713b1edbc | 15 | * claim that you wrote the original software.@n |
AnnaBridge | 171:3a7713b1edbc | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
AnnaBridge | 171:3a7713b1edbc | 17 | * misrepresented as being the original software.@n |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. This notice may not be removed or altered from any source distribution. |
AnnaBridge | 171:3a7713b1edbc | 19 | * |
AnnaBridge | 171:3a7713b1edbc | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
AnnaBridge | 171:3a7713b1edbc | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
AnnaBridge | 171:3a7713b1edbc | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
AnnaBridge | 171:3a7713b1edbc | 23 | * kind, including, but not limited to, any implied warranties of |
AnnaBridge | 171:3a7713b1edbc | 24 | * merchantability or fitness for any particular purpose or warranties against |
AnnaBridge | 171:3a7713b1edbc | 25 | * infringement of any proprietary rights of a third party. |
AnnaBridge | 171:3a7713b1edbc | 26 | * |
AnnaBridge | 171:3a7713b1edbc | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
AnnaBridge | 171:3a7713b1edbc | 28 | * incidental, or special damages, or any other relief, or for any claim by |
AnnaBridge | 171:3a7713b1edbc | 29 | * any third party, arising from your use of this Software. |
AnnaBridge | 171:3a7713b1edbc | 30 | * |
AnnaBridge | 171:3a7713b1edbc | 31 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 32 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 33 | * @addtogroup Parts |
AnnaBridge | 171:3a7713b1edbc | 34 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 35 | ******************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 36 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 37 | * @defgroup EFM32HG_CMU |
AnnaBridge | 171:3a7713b1edbc | 38 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 39 | * @brief EFM32HG_CMU Register Declaration |
AnnaBridge | 171:3a7713b1edbc | 40 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 41 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 42 | { |
AnnaBridge | 171:3a7713b1edbc | 43 | __IOM uint32_t CTRL; /**< CMU Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 44 | __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */ |
AnnaBridge | 171:3a7713b1edbc | 45 | __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */ |
AnnaBridge | 171:3a7713b1edbc | 46 | __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 47 | __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 48 | __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 49 | __IOM uint32_t CALCTRL; /**< Calibration Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 50 | __IOM uint32_t CALCNT; /**< Calibration Counter Register */ |
AnnaBridge | 171:3a7713b1edbc | 51 | __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ |
AnnaBridge | 171:3a7713b1edbc | 52 | __IOM uint32_t CMD; /**< Command Register */ |
AnnaBridge | 171:3a7713b1edbc | 53 | __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */ |
AnnaBridge | 171:3a7713b1edbc | 54 | __IM uint32_t STATUS; /**< Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 55 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
AnnaBridge | 171:3a7713b1edbc | 56 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
AnnaBridge | 171:3a7713b1edbc | 57 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
AnnaBridge | 171:3a7713b1edbc | 58 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 59 | __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 60 | __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 61 | uint32_t RESERVED0[2]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 62 | __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
AnnaBridge | 171:3a7713b1edbc | 63 | __IOM uint32_t FREEZE; /**< Freeze Register */ |
AnnaBridge | 171:3a7713b1edbc | 64 | __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ |
AnnaBridge | 171:3a7713b1edbc | 65 | uint32_t RESERVED1[1]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 66 | __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ |
AnnaBridge | 171:3a7713b1edbc | 67 | __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ |
AnnaBridge | 171:3a7713b1edbc | 68 | __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */ |
AnnaBridge | 171:3a7713b1edbc | 69 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 70 | __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ |
AnnaBridge | 171:3a7713b1edbc | 71 | uint32_t RESERVED3[1]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 72 | __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 73 | |
AnnaBridge | 171:3a7713b1edbc | 74 | uint32_t RESERVED4[1]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 75 | __IOM uint32_t ROUTE; /**< I/O Routing Register */ |
AnnaBridge | 171:3a7713b1edbc | 76 | __IOM uint32_t LOCK; /**< Configuration Lock Register */ |
AnnaBridge | 171:3a7713b1edbc | 77 | |
AnnaBridge | 171:3a7713b1edbc | 78 | uint32_t RESERVED5[18]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 79 | __IOM uint32_t USBCRCTRL; /**< USB Clock Recovery Control */ |
AnnaBridge | 171:3a7713b1edbc | 80 | __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control */ |
AnnaBridge | 171:3a7713b1edbc | 81 | __IOM uint32_t USHFRCOTUNE; /**< USHFRCO Frequency Tune */ |
AnnaBridge | 171:3a7713b1edbc | 82 | __IOM uint32_t USHFRCOCONF; /**< USHFRCO Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 83 | } CMU_TypeDef; /** @} */ |
AnnaBridge | 171:3a7713b1edbc | 84 | |
AnnaBridge | 171:3a7713b1edbc | 85 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 86 | * @defgroup EFM32HG_CMU_BitFields |
AnnaBridge | 171:3a7713b1edbc | 87 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 88 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 89 | |
AnnaBridge | 171:3a7713b1edbc | 90 | /* Bit fields for CMU CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #define _CMU_CTRL_MASK 0x07FFFEEFUL /**< Mask for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 93 | #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */ |
AnnaBridge | 171:3a7713b1edbc | 94 | #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */ |
AnnaBridge | 171:3a7713b1edbc | 95 | #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 96 | #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 98 | #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 99 | #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 100 | #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 101 | #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 102 | #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 103 | #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */ |
AnnaBridge | 171:3a7713b1edbc | 104 | #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */ |
AnnaBridge | 171:3a7713b1edbc | 105 | #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 106 | #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 107 | #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 109 | #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 110 | #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 112 | #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 113 | #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 114 | #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 115 | #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */ |
AnnaBridge | 171:3a7713b1edbc | 116 | #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */ |
AnnaBridge | 171:3a7713b1edbc | 117 | #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 118 | #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 119 | #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */ |
AnnaBridge | 171:3a7713b1edbc | 120 | #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */ |
AnnaBridge | 171:3a7713b1edbc | 121 | #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */ |
AnnaBridge | 171:3a7713b1edbc | 122 | #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 123 | #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 124 | #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */ |
AnnaBridge | 171:3a7713b1edbc | 125 | #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */ |
AnnaBridge | 171:3a7713b1edbc | 126 | #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 127 | #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 128 | #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 129 | #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 130 | #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 134 | #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 135 | #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */ |
AnnaBridge | 171:3a7713b1edbc | 137 | #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */ |
AnnaBridge | 171:3a7713b1edbc | 138 | #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 140 | #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 146 | #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */ |
AnnaBridge | 171:3a7713b1edbc | 147 | #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */ |
AnnaBridge | 171:3a7713b1edbc | 148 | #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */ |
AnnaBridge | 171:3a7713b1edbc | 149 | #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 150 | #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 151 | #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 152 | #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 154 | #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 156 | #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 157 | #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 158 | #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 159 | #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */ |
AnnaBridge | 171:3a7713b1edbc | 160 | #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */ |
AnnaBridge | 171:3a7713b1edbc | 162 | #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 163 | #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 164 | #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */ |
AnnaBridge | 171:3a7713b1edbc | 165 | #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */ |
AnnaBridge | 171:3a7713b1edbc | 166 | #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 167 | #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 168 | #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 169 | #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 170 | #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 171 | #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 172 | #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 173 | #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 174 | #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 175 | #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 176 | #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */ |
AnnaBridge | 171:3a7713b1edbc | 177 | #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */ |
AnnaBridge | 171:3a7713b1edbc | 178 | #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 179 | #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 180 | #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 181 | #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 182 | #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 183 | #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 184 | #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 185 | #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 186 | #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 187 | #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 188 | #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 189 | #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 190 | #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 191 | #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 192 | #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 194 | #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 196 | #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */ |
AnnaBridge | 171:3a7713b1edbc | 197 | #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */ |
AnnaBridge | 171:3a7713b1edbc | 198 | #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 200 | #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 201 | #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 202 | #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 204 | #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define _CMU_CTRL_CLKOUTSEL1_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 208 | #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 209 | #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 210 | #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 211 | #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 212 | #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 214 | #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 215 | #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 216 | #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 217 | #define CMU_CTRL_CLKOUTSEL1_USHFRCO (_CMU_CTRL_CLKOUTSEL1_USHFRCO << 23) /**< Shifted mode USHFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 218 | |
AnnaBridge | 171:3a7713b1edbc | 219 | /* Bit fields for CMU HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 220 | #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 221 | #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 222 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 223 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 224 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 225 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 226 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 227 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 228 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 229 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 230 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 232 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 233 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 234 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 236 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 237 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 238 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 239 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 240 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 241 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 242 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 243 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 244 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 245 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 246 | #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */ |
AnnaBridge | 171:3a7713b1edbc | 248 | #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 252 | #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 254 | #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 255 | |
AnnaBridge | 171:3a7713b1edbc | 256 | /* Bit fields for CMU HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 257 | #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 258 | #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 259 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 260 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 261 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 262 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 263 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 264 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 265 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 266 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 268 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 269 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 270 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 272 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 273 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 274 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 275 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 276 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 278 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 279 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 280 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 281 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 282 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */ |
AnnaBridge | 171:3a7713b1edbc | 284 | #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 286 | #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 287 | #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 288 | |
AnnaBridge | 171:3a7713b1edbc | 289 | /* Bit fields for CMU HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 290 | #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 291 | #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 292 | #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 293 | #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 294 | #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 295 | #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 296 | #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */ |
AnnaBridge | 171:3a7713b1edbc | 297 | #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */ |
AnnaBridge | 171:3a7713b1edbc | 298 | #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 299 | #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 300 | #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 301 | #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 302 | #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 303 | #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 304 | #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 305 | #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 306 | #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 307 | #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 308 | #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 309 | #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 310 | #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */ |
AnnaBridge | 171:3a7713b1edbc | 311 | #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */ |
AnnaBridge | 171:3a7713b1edbc | 312 | #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 313 | #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 314 | |
AnnaBridge | 171:3a7713b1edbc | 315 | /* Bit fields for CMU LFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 316 | #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 317 | #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 318 | #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 319 | #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 320 | #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 321 | #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 322 | |
AnnaBridge | 171:3a7713b1edbc | 323 | /* Bit fields for CMU AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 324 | #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 325 | #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 326 | #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 327 | #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 328 | #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 329 | #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 330 | #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */ |
AnnaBridge | 171:3a7713b1edbc | 331 | #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */ |
AnnaBridge | 171:3a7713b1edbc | 332 | #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 333 | #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 334 | #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 335 | #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 336 | #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 337 | #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 338 | #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 339 | #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 340 | #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 341 | #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 342 | #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 344 | |
AnnaBridge | 171:3a7713b1edbc | 345 | /* Bit fields for CMU CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 346 | #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 347 | #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 348 | #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ |
AnnaBridge | 171:3a7713b1edbc | 349 | #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ |
AnnaBridge | 171:3a7713b1edbc | 350 | #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 351 | #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 352 | #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 353 | #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 354 | #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 355 | #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 356 | #define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000005UL /**< Mode USHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 357 | #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 358 | #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 359 | #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 360 | #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 361 | #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 362 | #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 363 | #define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 364 | #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */ |
AnnaBridge | 171:3a7713b1edbc | 365 | #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */ |
AnnaBridge | 171:3a7713b1edbc | 366 | #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 367 | #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 368 | #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 369 | #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 370 | #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 371 | #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 372 | #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 373 | #define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 374 | #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 375 | #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 376 | #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 377 | #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 378 | #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 379 | #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 380 | #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 381 | #define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 382 | #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 383 | #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */ |
AnnaBridge | 171:3a7713b1edbc | 384 | #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */ |
AnnaBridge | 171:3a7713b1edbc | 385 | #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 386 | #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 387 | |
AnnaBridge | 171:3a7713b1edbc | 388 | /* Bit fields for CMU CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 389 | #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 390 | #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 391 | #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 392 | #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 393 | #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 394 | #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 395 | |
AnnaBridge | 171:3a7713b1edbc | 396 | /* Bit fields for CMU OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 397 | #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 398 | #define _CMU_OSCENCMD_MASK 0x00000FFFUL /**< Mask for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 399 | #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ |
AnnaBridge | 171:3a7713b1edbc | 400 | #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 401 | #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 402 | #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 403 | #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 404 | #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ |
AnnaBridge | 171:3a7713b1edbc | 405 | #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 406 | #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 407 | #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 408 | #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 409 | #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ |
AnnaBridge | 171:3a7713b1edbc | 410 | #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ |
AnnaBridge | 171:3a7713b1edbc | 411 | #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ |
AnnaBridge | 171:3a7713b1edbc | 412 | #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 413 | #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 414 | #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ |
AnnaBridge | 171:3a7713b1edbc | 415 | #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ |
AnnaBridge | 171:3a7713b1edbc | 416 | #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ |
AnnaBridge | 171:3a7713b1edbc | 417 | #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 418 | #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 419 | #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ |
AnnaBridge | 171:3a7713b1edbc | 420 | #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 421 | #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 422 | #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 423 | #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 424 | #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ |
AnnaBridge | 171:3a7713b1edbc | 425 | #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 426 | #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 427 | #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 428 | #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 429 | #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ |
AnnaBridge | 171:3a7713b1edbc | 430 | #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 431 | #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 432 | #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 433 | #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 434 | #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ |
AnnaBridge | 171:3a7713b1edbc | 435 | #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 436 | #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 437 | #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 438 | #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 439 | #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ |
AnnaBridge | 171:3a7713b1edbc | 440 | #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ |
AnnaBridge | 171:3a7713b1edbc | 441 | #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ |
AnnaBridge | 171:3a7713b1edbc | 442 | #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 443 | #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 444 | #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ |
AnnaBridge | 171:3a7713b1edbc | 445 | #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ |
AnnaBridge | 171:3a7713b1edbc | 446 | #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ |
AnnaBridge | 171:3a7713b1edbc | 447 | #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 448 | #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 449 | #define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ |
AnnaBridge | 171:3a7713b1edbc | 450 | #define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 451 | #define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 452 | #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 453 | #define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 454 | #define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ |
AnnaBridge | 171:3a7713b1edbc | 455 | #define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 456 | #define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 457 | #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 458 | #define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 459 | |
AnnaBridge | 171:3a7713b1edbc | 460 | /* Bit fields for CMU CMD */ |
AnnaBridge | 171:3a7713b1edbc | 461 | #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 462 | #define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 463 | #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 464 | #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 465 | #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 466 | #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 467 | #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 468 | #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 469 | #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 470 | #define _CMU_CMD_HFCLKSEL_USHFRCODIV2 0x00000005UL /**< Mode USHFRCODIV2 for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 471 | #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 472 | #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 473 | #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 474 | #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 475 | #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 476 | #define CMU_CMD_HFCLKSEL_USHFRCODIV2 (_CMU_CMD_HFCLKSEL_USHFRCODIV2 << 0) /**< Shifted mode USHFRCODIV2 for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 477 | #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */ |
AnnaBridge | 171:3a7713b1edbc | 478 | #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */ |
AnnaBridge | 171:3a7713b1edbc | 479 | #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */ |
AnnaBridge | 171:3a7713b1edbc | 480 | #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 481 | #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 482 | #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */ |
AnnaBridge | 171:3a7713b1edbc | 483 | #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */ |
AnnaBridge | 171:3a7713b1edbc | 484 | #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */ |
AnnaBridge | 171:3a7713b1edbc | 485 | #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 486 | #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 487 | #define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 488 | #define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 489 | #define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 490 | #define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 491 | #define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 492 | #define _CMU_CMD_USBCCLKSEL_USHFRCO 0x00000004UL /**< Mode USHFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 493 | #define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 494 | #define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 495 | #define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 496 | #define CMU_CMD_USBCCLKSEL_USHFRCO (_CMU_CMD_USBCCLKSEL_USHFRCO << 5) /**< Shifted mode USHFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 497 | |
AnnaBridge | 171:3a7713b1edbc | 498 | /* Bit fields for CMU LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 499 | #define _CMU_LFCLKSEL_RESETVALUE 0x00000015UL /**< Default value for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 500 | #define _CMU_LFCLKSEL_MASK 0x0011003FUL /**< Mask for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 501 | #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ |
AnnaBridge | 171:3a7713b1edbc | 502 | #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */ |
AnnaBridge | 171:3a7713b1edbc | 503 | #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 504 | #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 505 | #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 506 | #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 507 | #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 508 | #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 509 | #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 510 | #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 511 | #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 512 | #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 513 | #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */ |
AnnaBridge | 171:3a7713b1edbc | 514 | #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */ |
AnnaBridge | 171:3a7713b1edbc | 515 | #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 516 | #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 517 | #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 518 | #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 519 | #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 520 | #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 521 | #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 522 | #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 523 | #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 524 | #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 525 | #define _CMU_LFCLKSEL_LFC_SHIFT 4 /**< Shift value for CMU_LFC */ |
AnnaBridge | 171:3a7713b1edbc | 526 | #define _CMU_LFCLKSEL_LFC_MASK 0x30UL /**< Bit mask for CMU_LFC */ |
AnnaBridge | 171:3a7713b1edbc | 527 | #define _CMU_LFCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 528 | #define _CMU_LFCLKSEL_LFC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 529 | #define _CMU_LFCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 530 | #define _CMU_LFCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 531 | #define CMU_LFCLKSEL_LFC_DISABLED (_CMU_LFCLKSEL_LFC_DISABLED << 4) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 532 | #define CMU_LFCLKSEL_LFC_DEFAULT (_CMU_LFCLKSEL_LFC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 533 | #define CMU_LFCLKSEL_LFC_LFRCO (_CMU_LFCLKSEL_LFC_LFRCO << 4) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 534 | #define CMU_LFCLKSEL_LFC_LFXO (_CMU_LFCLKSEL_LFC_LFXO << 4) /**< Shifted mode LFXO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 535 | #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */ |
AnnaBridge | 171:3a7713b1edbc | 536 | #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */ |
AnnaBridge | 171:3a7713b1edbc | 537 | #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */ |
AnnaBridge | 171:3a7713b1edbc | 538 | #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 539 | #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 540 | #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 541 | #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 542 | #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 543 | #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 544 | #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */ |
AnnaBridge | 171:3a7713b1edbc | 545 | #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */ |
AnnaBridge | 171:3a7713b1edbc | 546 | #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */ |
AnnaBridge | 171:3a7713b1edbc | 547 | #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 548 | #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 549 | #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 550 | #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 551 | #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 552 | #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 553 | |
AnnaBridge | 171:3a7713b1edbc | 554 | /* Bit fields for CMU STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 555 | #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 556 | #define _CMU_STATUS_MASK 0x04F77FFFUL /**< Mask for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 557 | #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ |
AnnaBridge | 171:3a7713b1edbc | 558 | #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 559 | #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 560 | #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 561 | #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 562 | #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ |
AnnaBridge | 171:3a7713b1edbc | 563 | #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 564 | #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 565 | #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 566 | #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 567 | #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ |
AnnaBridge | 171:3a7713b1edbc | 568 | #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ |
AnnaBridge | 171:3a7713b1edbc | 569 | #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ |
AnnaBridge | 171:3a7713b1edbc | 570 | #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 571 | #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 572 | #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ |
AnnaBridge | 171:3a7713b1edbc | 573 | #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 574 | #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 575 | #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 576 | #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 577 | #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ |
AnnaBridge | 171:3a7713b1edbc | 578 | #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 579 | #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 580 | #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 581 | #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 582 | #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ |
AnnaBridge | 171:3a7713b1edbc | 583 | #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 584 | #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 585 | #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 586 | #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 587 | #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ |
AnnaBridge | 171:3a7713b1edbc | 588 | #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 589 | #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 590 | #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 591 | #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 592 | #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ |
AnnaBridge | 171:3a7713b1edbc | 593 | #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 594 | #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 595 | #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 596 | #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 597 | #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ |
AnnaBridge | 171:3a7713b1edbc | 598 | #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ |
AnnaBridge | 171:3a7713b1edbc | 599 | #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ |
AnnaBridge | 171:3a7713b1edbc | 600 | #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 601 | #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 602 | #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ |
AnnaBridge | 171:3a7713b1edbc | 603 | #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 604 | #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 605 | #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 606 | #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 607 | #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */ |
AnnaBridge | 171:3a7713b1edbc | 608 | #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 609 | #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 610 | #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 611 | #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 612 | #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */ |
AnnaBridge | 171:3a7713b1edbc | 613 | #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 614 | #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 615 | #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 616 | #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 617 | #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */ |
AnnaBridge | 171:3a7713b1edbc | 618 | #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 619 | #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 620 | #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 621 | #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 622 | #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */ |
AnnaBridge | 171:3a7713b1edbc | 623 | #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 624 | #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 625 | #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 626 | #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 627 | #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */ |
AnnaBridge | 171:3a7713b1edbc | 628 | #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */ |
AnnaBridge | 171:3a7713b1edbc | 629 | #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */ |
AnnaBridge | 171:3a7713b1edbc | 630 | #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 631 | #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 632 | #define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */ |
AnnaBridge | 171:3a7713b1edbc | 633 | #define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 634 | #define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 635 | #define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 636 | #define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 637 | #define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */ |
AnnaBridge | 171:3a7713b1edbc | 638 | #define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 639 | #define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 640 | #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 641 | #define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 642 | #define CMU_STATUS_USBCUSHFRCOSEL (0x1UL << 18) /**< USBC USHFRCO Selected */ |
AnnaBridge | 171:3a7713b1edbc | 643 | #define _CMU_STATUS_USBCUSHFRCOSEL_SHIFT 18 /**< Shift value for CMU_USBCUSHFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 644 | #define _CMU_STATUS_USBCUSHFRCOSEL_MASK 0x40000UL /**< Bit mask for CMU_USBCUSHFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 645 | #define _CMU_STATUS_USBCUSHFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 646 | #define CMU_STATUS_USBCUSHFRCOSEL_DEFAULT (_CMU_STATUS_USBCUSHFRCOSEL_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 647 | #define CMU_STATUS_USBCHFCLKSYNC (0x1UL << 20) /**< USBC is synchronous to HFCLK */ |
AnnaBridge | 171:3a7713b1edbc | 648 | #define _CMU_STATUS_USBCHFCLKSYNC_SHIFT 20 /**< Shift value for CMU_USBCHFCLKSYNC */ |
AnnaBridge | 171:3a7713b1edbc | 649 | #define _CMU_STATUS_USBCHFCLKSYNC_MASK 0x100000UL /**< Bit mask for CMU_USBCHFCLKSYNC */ |
AnnaBridge | 171:3a7713b1edbc | 650 | #define _CMU_STATUS_USBCHFCLKSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 651 | #define CMU_STATUS_USBCHFCLKSYNC_DEFAULT (_CMU_STATUS_USBCHFCLKSYNC_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 652 | #define CMU_STATUS_USHFRCOENS (0x1UL << 21) /**< USHFRCO Enable Status */ |
AnnaBridge | 171:3a7713b1edbc | 653 | #define _CMU_STATUS_USHFRCOENS_SHIFT 21 /**< Shift value for CMU_USHFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 654 | #define _CMU_STATUS_USHFRCOENS_MASK 0x200000UL /**< Bit mask for CMU_USHFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 655 | #define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 656 | #define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 657 | #define CMU_STATUS_USHFRCORDY (0x1UL << 22) /**< USHFRCO Ready */ |
AnnaBridge | 171:3a7713b1edbc | 658 | #define _CMU_STATUS_USHFRCORDY_SHIFT 22 /**< Shift value for CMU_USHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 659 | #define _CMU_STATUS_USHFRCORDY_MASK 0x400000UL /**< Bit mask for CMU_USHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 660 | #define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 661 | #define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 662 | #define CMU_STATUS_USHFRCOSUSPEND (0x1UL << 23) /**< USHFRCO is suspended */ |
AnnaBridge | 171:3a7713b1edbc | 663 | #define _CMU_STATUS_USHFRCOSUSPEND_SHIFT 23 /**< Shift value for CMU_USHFRCOSUSPEND */ |
AnnaBridge | 171:3a7713b1edbc | 664 | #define _CMU_STATUS_USHFRCOSUSPEND_MASK 0x800000UL /**< Bit mask for CMU_USHFRCOSUSPEND */ |
AnnaBridge | 171:3a7713b1edbc | 665 | #define _CMU_STATUS_USHFRCOSUSPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 666 | #define CMU_STATUS_USHFRCOSUSPEND_DEFAULT (_CMU_STATUS_USHFRCOSUSPEND_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 667 | #define CMU_STATUS_USHFRCODIV2SEL (0x1UL << 26) /**< USHFRCODIV2 Selected */ |
AnnaBridge | 171:3a7713b1edbc | 668 | #define _CMU_STATUS_USHFRCODIV2SEL_SHIFT 26 /**< Shift value for CMU_USHFRCODIV2SEL */ |
AnnaBridge | 171:3a7713b1edbc | 669 | #define _CMU_STATUS_USHFRCODIV2SEL_MASK 0x4000000UL /**< Bit mask for CMU_USHFRCODIV2SEL */ |
AnnaBridge | 171:3a7713b1edbc | 670 | #define _CMU_STATUS_USHFRCODIV2SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 671 | #define CMU_STATUS_USHFRCODIV2SEL_DEFAULT (_CMU_STATUS_USHFRCODIV2SEL_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 672 | |
AnnaBridge | 171:3a7713b1edbc | 673 | /* Bit fields for CMU IF */ |
AnnaBridge | 171:3a7713b1edbc | 674 | #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 675 | #define _CMU_IF_MASK 0x0000037FUL /**< Mask for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 676 | #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 677 | #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 678 | #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 679 | #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 680 | #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 681 | #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 682 | #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 683 | #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 684 | #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 685 | #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 686 | #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 687 | #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 688 | #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 689 | #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 690 | #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 691 | #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 692 | #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 693 | #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 694 | #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 695 | #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 696 | #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 697 | #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 698 | #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 699 | #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 700 | #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 701 | #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 702 | #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 703 | #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 704 | #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 705 | #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 706 | #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 707 | #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 708 | #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 709 | #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 710 | #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 711 | #define CMU_IF_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 712 | #define _CMU_IF_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 713 | #define _CMU_IF_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 714 | #define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 715 | #define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 716 | #define CMU_IF_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 717 | #define _CMU_IF_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */ |
AnnaBridge | 171:3a7713b1edbc | 718 | #define _CMU_IF_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */ |
AnnaBridge | 171:3a7713b1edbc | 719 | #define _CMU_IF_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 720 | #define CMU_IF_USBCHFOSCSEL_DEFAULT (_CMU_IF_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 721 | |
AnnaBridge | 171:3a7713b1edbc | 722 | /* Bit fields for CMU IFS */ |
AnnaBridge | 171:3a7713b1edbc | 723 | #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 724 | #define _CMU_IFS_MASK 0x0000037FUL /**< Mask for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 725 | #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 726 | #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 727 | #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 728 | #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 729 | #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 730 | #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 731 | #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 732 | #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 733 | #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 734 | #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 735 | #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 736 | #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 737 | #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 738 | #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 739 | #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 740 | #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 741 | #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 742 | #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 743 | #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 744 | #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 745 | #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 746 | #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 747 | #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 748 | #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 749 | #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 750 | #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 751 | #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 752 | #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 753 | #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 754 | #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 755 | #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 756 | #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 757 | #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 758 | #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 759 | #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 760 | #define CMU_IFS_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 761 | #define _CMU_IFS_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 762 | #define _CMU_IFS_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 763 | #define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 764 | #define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 765 | #define CMU_IFS_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 766 | #define _CMU_IFS_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */ |
AnnaBridge | 171:3a7713b1edbc | 767 | #define _CMU_IFS_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */ |
AnnaBridge | 171:3a7713b1edbc | 768 | #define _CMU_IFS_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 769 | #define CMU_IFS_USBCHFOSCSEL_DEFAULT (_CMU_IFS_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 770 | |
AnnaBridge | 171:3a7713b1edbc | 771 | /* Bit fields for CMU IFC */ |
AnnaBridge | 171:3a7713b1edbc | 772 | #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 773 | #define _CMU_IFC_MASK 0x0000037FUL /**< Mask for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 774 | #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 775 | #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 776 | #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 777 | #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 778 | #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 779 | #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 780 | #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 781 | #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 782 | #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 783 | #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 784 | #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 785 | #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 786 | #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 787 | #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 788 | #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 789 | #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 790 | #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 791 | #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 792 | #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 793 | #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 794 | #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 795 | #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 796 | #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 797 | #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 798 | #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 799 | #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 800 | #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 801 | #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 802 | #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 803 | #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 804 | #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 805 | #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 806 | #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 807 | #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 808 | #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 809 | #define CMU_IFC_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 810 | #define _CMU_IFC_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 811 | #define _CMU_IFC_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 812 | #define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 813 | #define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 814 | #define CMU_IFC_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 815 | #define _CMU_IFC_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */ |
AnnaBridge | 171:3a7713b1edbc | 816 | #define _CMU_IFC_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */ |
AnnaBridge | 171:3a7713b1edbc | 817 | #define _CMU_IFC_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 818 | #define CMU_IFC_USBCHFOSCSEL_DEFAULT (_CMU_IFC_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 819 | |
AnnaBridge | 171:3a7713b1edbc | 820 | /* Bit fields for CMU IEN */ |
AnnaBridge | 171:3a7713b1edbc | 821 | #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 822 | #define _CMU_IEN_MASK 0x0000037FUL /**< Mask for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 823 | #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 824 | #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 825 | #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 826 | #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 827 | #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 828 | #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 829 | #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 830 | #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 831 | #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 832 | #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 833 | #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 834 | #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 835 | #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 836 | #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 837 | #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 838 | #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 839 | #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 840 | #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 841 | #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 842 | #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 843 | #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 844 | #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 845 | #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 846 | #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 847 | #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 848 | #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 849 | #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 850 | #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 851 | #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 852 | #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 853 | #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 854 | #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 855 | #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 856 | #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 857 | #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 858 | #define CMU_IEN_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 859 | #define _CMU_IEN_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 860 | #define _CMU_IEN_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 861 | #define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 862 | #define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 863 | #define CMU_IEN_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 864 | #define _CMU_IEN_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */ |
AnnaBridge | 171:3a7713b1edbc | 865 | #define _CMU_IEN_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */ |
AnnaBridge | 171:3a7713b1edbc | 866 | #define _CMU_IEN_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 867 | #define CMU_IEN_USBCHFOSCSEL_DEFAULT (_CMU_IEN_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 868 | |
AnnaBridge | 171:3a7713b1edbc | 869 | /* Bit fields for CMU HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 870 | #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 871 | #define _CMU_HFCORECLKEN0_MASK 0x0000001FUL /**< Mask for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 872 | #define CMU_HFCORECLKEN0_AES (0x1UL << 0) /**< Advanced Encryption Standard Accelerator Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 873 | #define _CMU_HFCORECLKEN0_AES_SHIFT 0 /**< Shift value for CMU_AES */ |
AnnaBridge | 171:3a7713b1edbc | 874 | #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL /**< Bit mask for CMU_AES */ |
AnnaBridge | 171:3a7713b1edbc | 875 | #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 876 | #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 877 | #define CMU_HFCORECLKEN0_DMA (0x1UL << 1) /**< Direct Memory Access Controller Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 878 | #define _CMU_HFCORECLKEN0_DMA_SHIFT 1 /**< Shift value for CMU_DMA */ |
AnnaBridge | 171:3a7713b1edbc | 879 | #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL /**< Bit mask for CMU_DMA */ |
AnnaBridge | 171:3a7713b1edbc | 880 | #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 881 | #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 882 | #define CMU_HFCORECLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 883 | #define _CMU_HFCORECLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */ |
AnnaBridge | 171:3a7713b1edbc | 884 | #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */ |
AnnaBridge | 171:3a7713b1edbc | 885 | #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 886 | #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 887 | #define CMU_HFCORECLKEN0_USBC (0x1UL << 3) /**< Universal Serial Bus Interface Core Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 888 | #define _CMU_HFCORECLKEN0_USBC_SHIFT 3 /**< Shift value for CMU_USBC */ |
AnnaBridge | 171:3a7713b1edbc | 889 | #define _CMU_HFCORECLKEN0_USBC_MASK 0x8UL /**< Bit mask for CMU_USBC */ |
AnnaBridge | 171:3a7713b1edbc | 890 | #define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 891 | #define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 892 | #define CMU_HFCORECLKEN0_USB (0x1UL << 4) /**< Universal Serial Bus Interface Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 893 | #define _CMU_HFCORECLKEN0_USB_SHIFT 4 /**< Shift value for CMU_USB */ |
AnnaBridge | 171:3a7713b1edbc | 894 | #define _CMU_HFCORECLKEN0_USB_MASK 0x10UL /**< Bit mask for CMU_USB */ |
AnnaBridge | 171:3a7713b1edbc | 895 | #define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 896 | #define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 897 | |
AnnaBridge | 171:3a7713b1edbc | 898 | /* Bit fields for CMU HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 899 | #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 900 | #define _CMU_HFPERCLKEN0_MASK 0x00000FFFUL /**< Mask for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 901 | #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 902 | #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ |
AnnaBridge | 171:3a7713b1edbc | 903 | #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ |
AnnaBridge | 171:3a7713b1edbc | 904 | #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 905 | #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 906 | #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 907 | #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ |
AnnaBridge | 171:3a7713b1edbc | 908 | #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ |
AnnaBridge | 171:3a7713b1edbc | 909 | #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 910 | #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 911 | #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 912 | #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ |
AnnaBridge | 171:3a7713b1edbc | 913 | #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ |
AnnaBridge | 171:3a7713b1edbc | 914 | #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 915 | #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 916 | #define CMU_HFPERCLKEN0_USART0 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 917 | #define _CMU_HFPERCLKEN0_USART0_SHIFT 3 /**< Shift value for CMU_USART0 */ |
AnnaBridge | 171:3a7713b1edbc | 918 | #define _CMU_HFPERCLKEN0_USART0_MASK 0x8UL /**< Bit mask for CMU_USART0 */ |
AnnaBridge | 171:3a7713b1edbc | 919 | #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 920 | #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 921 | #define CMU_HFPERCLKEN0_USART1 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 922 | #define _CMU_HFPERCLKEN0_USART1_SHIFT 4 /**< Shift value for CMU_USART1 */ |
AnnaBridge | 171:3a7713b1edbc | 923 | #define _CMU_HFPERCLKEN0_USART1_MASK 0x10UL /**< Bit mask for CMU_USART1 */ |
AnnaBridge | 171:3a7713b1edbc | 924 | #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 925 | #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 926 | #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 5) /**< Analog Comparator 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 927 | #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 5 /**< Shift value for CMU_ACMP0 */ |
AnnaBridge | 171:3a7713b1edbc | 928 | #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x20UL /**< Bit mask for CMU_ACMP0 */ |
AnnaBridge | 171:3a7713b1edbc | 929 | #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 930 | #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 931 | #define CMU_HFPERCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 932 | #define _CMU_HFPERCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ |
AnnaBridge | 171:3a7713b1edbc | 933 | #define _CMU_HFPERCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ |
AnnaBridge | 171:3a7713b1edbc | 934 | #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 935 | #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 936 | #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 7) /**< Current Digital to Analog Converter 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 937 | #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 7 /**< Shift value for CMU_IDAC0 */ |
AnnaBridge | 171:3a7713b1edbc | 938 | #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x80UL /**< Bit mask for CMU_IDAC0 */ |
AnnaBridge | 171:3a7713b1edbc | 939 | #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 940 | #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 941 | #define CMU_HFPERCLKEN0_GPIO (0x1UL << 8) /**< General purpose Input/Output Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 942 | #define _CMU_HFPERCLKEN0_GPIO_SHIFT 8 /**< Shift value for CMU_GPIO */ |
AnnaBridge | 171:3a7713b1edbc | 943 | #define _CMU_HFPERCLKEN0_GPIO_MASK 0x100UL /**< Bit mask for CMU_GPIO */ |
AnnaBridge | 171:3a7713b1edbc | 944 | #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 945 | #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 946 | #define CMU_HFPERCLKEN0_VCMP (0x1UL << 9) /**< Voltage Comparator Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 947 | #define _CMU_HFPERCLKEN0_VCMP_SHIFT 9 /**< Shift value for CMU_VCMP */ |
AnnaBridge | 171:3a7713b1edbc | 948 | #define _CMU_HFPERCLKEN0_VCMP_MASK 0x200UL /**< Bit mask for CMU_VCMP */ |
AnnaBridge | 171:3a7713b1edbc | 949 | #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 950 | #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 951 | #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 10) /**< Analog to Digital Converter 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 952 | #define _CMU_HFPERCLKEN0_ADC0_SHIFT 10 /**< Shift value for CMU_ADC0 */ |
AnnaBridge | 171:3a7713b1edbc | 953 | #define _CMU_HFPERCLKEN0_ADC0_MASK 0x400UL /**< Bit mask for CMU_ADC0 */ |
AnnaBridge | 171:3a7713b1edbc | 954 | #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 955 | #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 956 | #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 957 | #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */ |
AnnaBridge | 171:3a7713b1edbc | 958 | #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */ |
AnnaBridge | 171:3a7713b1edbc | 959 | #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 960 | #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 961 | |
AnnaBridge | 171:3a7713b1edbc | 962 | /* Bit fields for CMU SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 963 | #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 964 | #define _CMU_SYNCBUSY_MASK 0x00000155UL /**< Mask for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 965 | #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */ |
AnnaBridge | 171:3a7713b1edbc | 966 | #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 967 | #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 968 | #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 969 | #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 970 | #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */ |
AnnaBridge | 171:3a7713b1edbc | 971 | #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 972 | #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 973 | #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 974 | #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 975 | #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ |
AnnaBridge | 171:3a7713b1edbc | 976 | #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 977 | #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 978 | #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 979 | #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 980 | #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ |
AnnaBridge | 171:3a7713b1edbc | 981 | #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 982 | #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 983 | #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 984 | #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 985 | #define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ |
AnnaBridge | 171:3a7713b1edbc | 986 | #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 987 | #define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 988 | #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 989 | #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 990 | |
AnnaBridge | 171:3a7713b1edbc | 991 | /* Bit fields for CMU FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 992 | #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 993 | #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 994 | #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ |
AnnaBridge | 171:3a7713b1edbc | 995 | #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 996 | #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 997 | #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 998 | #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 999 | #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1000 | #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1001 | #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1002 | #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1003 | |
AnnaBridge | 171:3a7713b1edbc | 1004 | /* Bit fields for CMU LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1005 | #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1006 | #define _CMU_LFACLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1007 | #define CMU_LFACLKEN0_RTC (0x1UL << 0) /**< Real-Time Counter Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1008 | #define _CMU_LFACLKEN0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */ |
AnnaBridge | 171:3a7713b1edbc | 1009 | #define _CMU_LFACLKEN0_RTC_MASK 0x1UL /**< Bit mask for CMU_RTC */ |
AnnaBridge | 171:3a7713b1edbc | 1010 | #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1011 | #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1012 | |
AnnaBridge | 171:3a7713b1edbc | 1013 | /* Bit fields for CMU LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1014 | #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1015 | #define _CMU_LFBCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1016 | #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1017 | #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1018 | #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1019 | #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1020 | #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1021 | |
AnnaBridge | 171:3a7713b1edbc | 1022 | /* Bit fields for CMU LFCCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1023 | #define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1024 | #define _CMU_LFCCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFCCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1025 | #define CMU_LFCCLKEN0_USBLE (0x1UL << 0) /**< Universal Serial Bus Low Energy Clock Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1026 | #define _CMU_LFCCLKEN0_USBLE_SHIFT 0 /**< Shift value for CMU_USBLE */ |
AnnaBridge | 171:3a7713b1edbc | 1027 | #define _CMU_LFCCLKEN0_USBLE_MASK 0x1UL /**< Bit mask for CMU_USBLE */ |
AnnaBridge | 171:3a7713b1edbc | 1028 | #define _CMU_LFCCLKEN0_USBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1029 | #define CMU_LFCCLKEN0_USBLE_DEFAULT (_CMU_LFCCLKEN0_USBLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1030 | |
AnnaBridge | 171:3a7713b1edbc | 1031 | /* Bit fields for CMU LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1032 | #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1033 | #define _CMU_LFAPRESC0_MASK 0x0000000FUL /**< Mask for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1034 | #define _CMU_LFAPRESC0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */ |
AnnaBridge | 171:3a7713b1edbc | 1035 | #define _CMU_LFAPRESC0_RTC_MASK 0xFUL /**< Bit mask for CMU_RTC */ |
AnnaBridge | 171:3a7713b1edbc | 1036 | #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1037 | #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1038 | #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1039 | #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1040 | #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1041 | #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1042 | #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1043 | #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1044 | #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1045 | #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1046 | #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1047 | #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1048 | #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1049 | #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1050 | #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1051 | #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1052 | #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1053 | #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1054 | #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1055 | #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1056 | #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1057 | #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1058 | #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1059 | #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1060 | #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1061 | #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1062 | #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1063 | #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1064 | #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1065 | #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1066 | #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1067 | #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1068 | |
AnnaBridge | 171:3a7713b1edbc | 1069 | /* Bit fields for CMU LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1070 | #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1071 | #define _CMU_LFBPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1072 | #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1073 | #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1074 | #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1075 | #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1076 | #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1077 | #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1078 | #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1079 | #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1080 | #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1081 | #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1082 | |
AnnaBridge | 171:3a7713b1edbc | 1083 | /* Bit fields for CMU PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1084 | #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1085 | #define _CMU_PCNTCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1086 | #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1087 | #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 1088 | #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 1089 | #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1090 | #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1091 | #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 1092 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1093 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1094 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1095 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1096 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1097 | #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1098 | #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1099 | #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1100 | |
AnnaBridge | 171:3a7713b1edbc | 1101 | /* Bit fields for CMU ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1102 | #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1103 | #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1104 | #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1105 | #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1106 | #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1107 | #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1108 | #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1109 | #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1110 | #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1111 | #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1112 | #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1113 | #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1114 | #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */ |
AnnaBridge | 171:3a7713b1edbc | 1115 | #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */ |
AnnaBridge | 171:3a7713b1edbc | 1116 | #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1117 | #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1118 | #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1119 | #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1120 | #define _CMU_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1121 | #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1122 | #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1123 | #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1124 | #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1125 | #define CMU_ROUTE_LOCATION_LOC3 (_CMU_ROUTE_LOCATION_LOC3 << 2) /**< Shifted mode LOC3 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1126 | |
AnnaBridge | 171:3a7713b1edbc | 1127 | /* Bit fields for CMU LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1128 | #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1129 | #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1130 | #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ |
AnnaBridge | 171:3a7713b1edbc | 1131 | #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ |
AnnaBridge | 171:3a7713b1edbc | 1132 | #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1133 | #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1134 | #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1135 | #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1136 | #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1137 | #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1138 | #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1139 | #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1140 | #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1141 | #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1142 | |
AnnaBridge | 171:3a7713b1edbc | 1143 | /* Bit fields for CMU USBCRCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1144 | #define _CMU_USBCRCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCRCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1145 | #define _CMU_USBCRCTRL_MASK 0x00000003UL /**< Mask for CMU_USBCRCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1146 | #define CMU_USBCRCTRL_EN (0x1UL << 0) /**< Clock Recovery Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1147 | #define _CMU_USBCRCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ |
AnnaBridge | 171:3a7713b1edbc | 1148 | #define _CMU_USBCRCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ |
AnnaBridge | 171:3a7713b1edbc | 1149 | #define _CMU_USBCRCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1150 | #define CMU_USBCRCTRL_EN_DEFAULT (_CMU_USBCRCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1151 | #define CMU_USBCRCTRL_LSMODE (0x1UL << 1) /**< Low Speed Clock Recovery Mode */ |
AnnaBridge | 171:3a7713b1edbc | 1152 | #define _CMU_USBCRCTRL_LSMODE_SHIFT 1 /**< Shift value for CMU_LSMODE */ |
AnnaBridge | 171:3a7713b1edbc | 1153 | #define _CMU_USBCRCTRL_LSMODE_MASK 0x2UL /**< Bit mask for CMU_LSMODE */ |
AnnaBridge | 171:3a7713b1edbc | 1154 | #define _CMU_USBCRCTRL_LSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1155 | #define CMU_USBCRCTRL_LSMODE_DEFAULT (_CMU_USBCRCTRL_LSMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1156 | |
AnnaBridge | 171:3a7713b1edbc | 1157 | /* Bit fields for CMU USHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1158 | #define _CMU_USHFRCOCTRL_RESETVALUE 0x000FF040UL /**< Default value for CMU_USHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1159 | #define _CMU_USHFRCOCTRL_MASK 0x000FF37FUL /**< Mask for CMU_USHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1160 | #define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 1161 | #define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 1162 | #define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1163 | #define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1164 | #define CMU_USHFRCOCTRL_DITHEN (0x1UL << 8) /**< USHFRCO dither enable */ |
AnnaBridge | 171:3a7713b1edbc | 1165 | #define _CMU_USHFRCOCTRL_DITHEN_SHIFT 8 /**< Shift value for CMU_DITHEN */ |
AnnaBridge | 171:3a7713b1edbc | 1166 | #define _CMU_USHFRCOCTRL_DITHEN_MASK 0x100UL /**< Bit mask for CMU_DITHEN */ |
AnnaBridge | 171:3a7713b1edbc | 1167 | #define _CMU_USHFRCOCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1168 | #define CMU_USHFRCOCTRL_DITHEN_DEFAULT (_CMU_USHFRCOCTRL_DITHEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1169 | #define CMU_USHFRCOCTRL_SUSPEND (0x1UL << 9) /**< USHFRCO suspend */ |
AnnaBridge | 171:3a7713b1edbc | 1170 | #define _CMU_USHFRCOCTRL_SUSPEND_SHIFT 9 /**< Shift value for CMU_SUSPEND */ |
AnnaBridge | 171:3a7713b1edbc | 1171 | #define _CMU_USHFRCOCTRL_SUSPEND_MASK 0x200UL /**< Bit mask for CMU_SUSPEND */ |
AnnaBridge | 171:3a7713b1edbc | 1172 | #define _CMU_USHFRCOCTRL_SUSPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1173 | #define CMU_USHFRCOCTRL_SUSPEND_DEFAULT (_CMU_USHFRCOCTRL_SUSPEND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1174 | #define _CMU_USHFRCOCTRL_TIMEOUT_SHIFT 12 /**< Shift value for CMU_TIMEOUT */ |
AnnaBridge | 171:3a7713b1edbc | 1175 | #define _CMU_USHFRCOCTRL_TIMEOUT_MASK 0xFF000UL /**< Bit mask for CMU_TIMEOUT */ |
AnnaBridge | 171:3a7713b1edbc | 1176 | #define _CMU_USHFRCOCTRL_TIMEOUT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1177 | #define CMU_USHFRCOCTRL_TIMEOUT_DEFAULT (_CMU_USHFRCOCTRL_TIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1178 | |
AnnaBridge | 171:3a7713b1edbc | 1179 | /* Bit fields for CMU USHFRCOTUNE */ |
AnnaBridge | 171:3a7713b1edbc | 1180 | #define _CMU_USHFRCOTUNE_RESETVALUE 0x00000020UL /**< Default value for CMU_USHFRCOTUNE */ |
AnnaBridge | 171:3a7713b1edbc | 1181 | #define _CMU_USHFRCOTUNE_MASK 0x0000003FUL /**< Mask for CMU_USHFRCOTUNE */ |
AnnaBridge | 171:3a7713b1edbc | 1182 | #define _CMU_USHFRCOTUNE_FINETUNING_SHIFT 0 /**< Shift value for CMU_FINETUNING */ |
AnnaBridge | 171:3a7713b1edbc | 1183 | #define _CMU_USHFRCOTUNE_FINETUNING_MASK 0x3FUL /**< Bit mask for CMU_FINETUNING */ |
AnnaBridge | 171:3a7713b1edbc | 1184 | #define _CMU_USHFRCOTUNE_FINETUNING_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_USHFRCOTUNE */ |
AnnaBridge | 171:3a7713b1edbc | 1185 | #define CMU_USHFRCOTUNE_FINETUNING_DEFAULT (_CMU_USHFRCOTUNE_FINETUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOTUNE */ |
AnnaBridge | 171:3a7713b1edbc | 1186 | |
AnnaBridge | 171:3a7713b1edbc | 1187 | /* Bit fields for CMU USHFRCOCONF */ |
AnnaBridge | 171:3a7713b1edbc | 1188 | #define _CMU_USHFRCOCONF_RESETVALUE 0x00000001UL /**< Default value for CMU_USHFRCOCONF */ |
AnnaBridge | 171:3a7713b1edbc | 1189 | #define _CMU_USHFRCOCONF_MASK 0x00000017UL /**< Mask for CMU_USHFRCOCONF */ |
AnnaBridge | 171:3a7713b1edbc | 1190 | #define _CMU_USHFRCOCONF_BAND_SHIFT 0 /**< Shift value for CMU_BAND */ |
AnnaBridge | 171:3a7713b1edbc | 1191 | #define _CMU_USHFRCOCONF_BAND_MASK 0x7UL /**< Bit mask for CMU_BAND */ |
AnnaBridge | 171:3a7713b1edbc | 1192 | #define _CMU_USHFRCOCONF_BAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCONF */ |
AnnaBridge | 171:3a7713b1edbc | 1193 | #define _CMU_USHFRCOCONF_BAND_48MHZ 0x00000001UL /**< Mode 48MHZ for CMU_USHFRCOCONF */ |
AnnaBridge | 171:3a7713b1edbc | 1194 | #define _CMU_USHFRCOCONF_BAND_24MHZ 0x00000003UL /**< Mode 24MHZ for CMU_USHFRCOCONF */ |
AnnaBridge | 171:3a7713b1edbc | 1195 | #define CMU_USHFRCOCONF_BAND_DEFAULT (_CMU_USHFRCOCONF_BAND_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCONF */ |
AnnaBridge | 171:3a7713b1edbc | 1196 | #define CMU_USHFRCOCONF_BAND_48MHZ (_CMU_USHFRCOCONF_BAND_48MHZ << 0) /**< Shifted mode 48MHZ for CMU_USHFRCOCONF */ |
AnnaBridge | 171:3a7713b1edbc | 1197 | #define CMU_USHFRCOCONF_BAND_24MHZ (_CMU_USHFRCOCONF_BAND_24MHZ << 0) /**< Shifted mode 24MHZ for CMU_USHFRCOCONF */ |
AnnaBridge | 171:3a7713b1edbc | 1198 | #define CMU_USHFRCOCONF_USHFRCODIV2DIS (0x1UL << 4) /**< USHFRCO divider for HFCLK disable */ |
AnnaBridge | 171:3a7713b1edbc | 1199 | #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT 4 /**< Shift value for CMU_USHFRCODIV2DIS */ |
AnnaBridge | 171:3a7713b1edbc | 1200 | #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_MASK 0x10UL /**< Bit mask for CMU_USHFRCODIV2DIS */ |
AnnaBridge | 171:3a7713b1edbc | 1201 | #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCONF */ |
AnnaBridge | 171:3a7713b1edbc | 1202 | #define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_USHFRCOCONF */ |
AnnaBridge | 171:3a7713b1edbc | 1203 | |
AnnaBridge | 171:3a7713b1edbc | 1204 | /** @} End of group EFM32HG_CMU */ |
AnnaBridge | 171:3a7713b1edbc | 1205 | /** @} End of group Parts */ |
AnnaBridge | 171:3a7713b1edbc | 1206 |