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TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/efm32hg_usb.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32hg_usb.h |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @brief EFM32HG_USB register and bit field definitions |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @version 5.1.2 |
| AnnaBridge | 171:3a7713b1edbc | 5 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 6 | * @section License |
| AnnaBridge | 171:3a7713b1edbc | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 9 | * |
| AnnaBridge | 171:3a7713b1edbc | 10 | * Permission is granted to anyone to use this software for any purpose, |
| AnnaBridge | 171:3a7713b1edbc | 11 | * including commercial applications, and to alter it and redistribute it |
| AnnaBridge | 171:3a7713b1edbc | 12 | * freely, subject to the following restrictions: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * |
| AnnaBridge | 171:3a7713b1edbc | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| AnnaBridge | 171:3a7713b1edbc | 15 | * claim that you wrote the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| AnnaBridge | 171:3a7713b1edbc | 17 | * misrepresented as being the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| AnnaBridge | 171:3a7713b1edbc | 19 | * |
| AnnaBridge | 171:3a7713b1edbc | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| AnnaBridge | 171:3a7713b1edbc | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| AnnaBridge | 171:3a7713b1edbc | 23 | * kind, including, but not limited to, any implied warranties of |
| AnnaBridge | 171:3a7713b1edbc | 24 | * merchantability or fitness for any particular purpose or warranties against |
| AnnaBridge | 171:3a7713b1edbc | 25 | * infringement of any proprietary rights of a third party. |
| AnnaBridge | 171:3a7713b1edbc | 26 | * |
| AnnaBridge | 171:3a7713b1edbc | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| AnnaBridge | 171:3a7713b1edbc | 29 | * any third party, arising from your use of this Software. |
| AnnaBridge | 171:3a7713b1edbc | 30 | * |
| AnnaBridge | 171:3a7713b1edbc | 31 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 32 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 33 | * @addtogroup Parts |
| AnnaBridge | 171:3a7713b1edbc | 34 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 35 | ******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 36 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 37 | * @defgroup EFM32HG_USB |
| AnnaBridge | 171:3a7713b1edbc | 38 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 39 | * @brief EFM32HG_USB Register Declaration |
| AnnaBridge | 171:3a7713b1edbc | 40 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 41 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 42 | { |
| AnnaBridge | 171:3a7713b1edbc | 43 | __IOM uint32_t CTRL; /**< System Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 44 | __IM uint32_t STATUS; /**< System Status Register */ |
| AnnaBridge | 171:3a7713b1edbc | 45 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| AnnaBridge | 171:3a7713b1edbc | 46 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| AnnaBridge | 171:3a7713b1edbc | 47 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| AnnaBridge | 171:3a7713b1edbc | 49 | __IOM uint32_t ROUTE; /**< I/O Routing Register */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | uint32_t RESERVED0[61435]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 52 | __IOM uint32_t GAHBCFG; /**< AHB Configuration Register */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | __IOM uint32_t GUSBCFG; /**< USB Configuration Register */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | __IOM uint32_t GRSTCTL; /**< Reset Register */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | __IOM uint32_t GINTSTS; /**< Interrupt Register */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | __IOM uint32_t GINTMSK; /**< Interrupt Mask Register */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | __IM uint32_t GRXSTSR; /**< Receive Status Debug Read Register */ |
| AnnaBridge | 171:3a7713b1edbc | 58 | __IM uint32_t GRXSTSP; /**< Receive Status Read and Pop Register */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | __IOM uint32_t GRXFSIZ; /**< Receive FIFO Size Register */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | __IOM uint32_t GNPTXFSIZ; /**< Non-periodic Transmit FIFO Size Register */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | |
| AnnaBridge | 171:3a7713b1edbc | 62 | uint32_t RESERVED1[12]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 63 | __IOM uint32_t GDFIFOCFG; /**< Global DFIFO Configuration Register */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | |
| AnnaBridge | 171:3a7713b1edbc | 65 | uint32_t RESERVED2[41]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 66 | __IOM uint32_t DIEPTXF1; /**< Device IN Endpoint Transmit FIFO 1 Size Register */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | __IOM uint32_t DIEPTXF2; /**< Device IN Endpoint Transmit FIFO 2 Size Register */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | __IOM uint32_t DIEPTXF3; /**< Device IN Endpoint Transmit FIFO 3 Size Register */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | |
| AnnaBridge | 171:3a7713b1edbc | 70 | uint32_t RESERVED3[444]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 71 | __IOM uint32_t DCFG; /**< Device Configuration Register */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | __IOM uint32_t DCTL; /**< Device Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | __IM uint32_t DSTS; /**< Device Status Register */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | uint32_t RESERVED4[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 75 | __IOM uint32_t DIEPMSK; /**< Device IN Endpoint Common Interrupt Mask Register */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | __IOM uint32_t DOEPMSK; /**< Device OUT Endpoint Common Interrupt Mask Register */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | __IM uint32_t DAINT; /**< Device All Endpoints Interrupt Register */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | __IOM uint32_t DAINTMSK; /**< Device All Endpoints Interrupt Mask Register */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | |
| AnnaBridge | 171:3a7713b1edbc | 80 | uint32_t RESERVED5[5]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 81 | __IOM uint32_t DIEPEMPMSK; /**< Device IN Endpoint FIFO Empty Interrupt Mask Register */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | |
| AnnaBridge | 171:3a7713b1edbc | 83 | uint32_t RESERVED6[50]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 84 | __IOM uint32_t DIEP0CTL; /**< Device IN Endpoint 0 Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | uint32_t RESERVED7[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 86 | __IOM uint32_t DIEP0INT; /**< Device IN Endpoint 0 Interrupt Register */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | uint32_t RESERVED8[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 88 | __IOM uint32_t DIEP0TSIZ; /**< Device IN Endpoint 0 Transfer Size Register */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | __IOM uint32_t DIEP0DMAADDR; /**< Device IN Endpoint 0 DMA Address Register */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | __IM uint32_t DIEP0TXFSTS; /**< Device IN Endpoint 0 Transmit FIFO Status Register */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | |
| AnnaBridge | 171:3a7713b1edbc | 92 | uint32_t RESERVED9[1]; /**< Reserved registers */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | USB_DIEP_TypeDef DIEP[3]; /**< Device IN Endpoint x+1 Registers */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | |
| AnnaBridge | 171:3a7713b1edbc | 95 | uint32_t RESERVED10[96]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 96 | __IOM uint32_t DOEP0CTL; /**< Device OUT Endpoint 0 Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | uint32_t RESERVED11[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 98 | __IOM uint32_t DOEP0INT; /**< Device OUT Endpoint 0 Interrupt Register */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | uint32_t RESERVED12[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 100 | __IOM uint32_t DOEP0TSIZ; /**< Device OUT Endpoint 0 Transfer Size Register */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | __IOM uint32_t DOEP0DMAADDR; /**< Device OUT Endpoint 0 DMA Address Register */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | |
| AnnaBridge | 171:3a7713b1edbc | 103 | uint32_t RESERVED13[2]; /**< Reserved registers */ |
| AnnaBridge | 171:3a7713b1edbc | 104 | USB_DOEP_TypeDef DOEP[3]; /**< Device OUT Endpoint x+1 Registers */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | |
| AnnaBridge | 171:3a7713b1edbc | 106 | uint32_t RESERVED14[160]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 107 | __IOM uint32_t PCGCCTL; /**< Power and Clock Gating Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | |
| AnnaBridge | 171:3a7713b1edbc | 109 | uint32_t RESERVED15[127]; /**< Reserved registers */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | __IOM uint32_t FIFO0D[384]; /**< Device EP 0 FIFO */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | |
| AnnaBridge | 171:3a7713b1edbc | 112 | uint32_t RESERVED16[640]; /**< Reserved registers */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | __IOM uint32_t FIFO1D[384]; /**< Device EP 1 FIFO */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | |
| AnnaBridge | 171:3a7713b1edbc | 115 | uint32_t RESERVED17[640]; /**< Reserved registers */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | __IOM uint32_t FIFO2D[384]; /**< Device EP 2 FIFO */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | |
| AnnaBridge | 171:3a7713b1edbc | 118 | uint32_t RESERVED18[640]; /**< Reserved registers */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | __IOM uint32_t FIFO3D[384]; /**< Device EP 3 FIFO */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | |
| AnnaBridge | 171:3a7713b1edbc | 121 | uint32_t RESERVED19[28288]; /**< Reserved registers */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | __IOM uint32_t FIFORAM[512]; /**< Direct Access to Data FIFO RAM for Debugging (2 KB) */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | } USB_TypeDef; /** @} */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | |
| AnnaBridge | 171:3a7713b1edbc | 125 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 126 | * @defgroup EFM32HG_USB_BitFields |
| AnnaBridge | 171:3a7713b1edbc | 127 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 128 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 129 | |
| AnnaBridge | 171:3a7713b1edbc | 130 | /* Bit fields for USB CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define _USB_CTRL_RESETVALUE 0x00000020UL /**< Default value for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define _USB_CTRL_MASK 0x03330EB2UL /**< Mask for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define USB_CTRL_DMPUAP (0x1UL << 1) /**< DMPU Active Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define _USB_CTRL_DMPUAP_SHIFT 1 /**< Shift value for USB_DMPUAP */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define _USB_CTRL_DMPUAP_MASK 0x2UL /**< Bit mask for USB_DMPUAP */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define _USB_CTRL_DMPUAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define _USB_CTRL_DMPUAP_LOW 0x00000000UL /**< Mode LOW for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define _USB_CTRL_DMPUAP_HIGH 0x00000001UL /**< Mode HIGH for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | #define USB_CTRL_DMPUAP_DEFAULT (_USB_CTRL_DMPUAP_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define USB_CTRL_DMPUAP_LOW (_USB_CTRL_DMPUAP_LOW << 1) /**< Shifted mode LOW for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define USB_CTRL_DMPUAP_HIGH (_USB_CTRL_DMPUAP_HIGH << 1) /**< Shifted mode HIGH for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define _USB_CTRL_LEMOSCCTRL_SHIFT 4 /**< Shift value for USB_LEMOSCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define _USB_CTRL_LEMOSCCTRL_MASK 0x30UL /**< Bit mask for USB_LEMOSCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define _USB_CTRL_LEMOSCCTRL_NONE 0x00000000UL /**< Mode NONE for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define _USB_CTRL_LEMOSCCTRL_GATE 0x00000001UL /**< Mode GATE for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define _USB_CTRL_LEMOSCCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define _USB_CTRL_LEMOSCCTRL_SUSPEND 0x00000002UL /**< Mode SUSPEND for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define USB_CTRL_LEMOSCCTRL_NONE (_USB_CTRL_LEMOSCCTRL_NONE << 4) /**< Shifted mode NONE for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define USB_CTRL_LEMOSCCTRL_GATE (_USB_CTRL_LEMOSCCTRL_GATE << 4) /**< Shifted mode GATE for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define USB_CTRL_LEMOSCCTRL_DEFAULT (_USB_CTRL_LEMOSCCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define USB_CTRL_LEMOSCCTRL_SUSPEND (_USB_CTRL_LEMOSCCTRL_SUSPEND << 4) /**< Shifted mode SUSPEND for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define USB_CTRL_LEMPHYCTRL (0x1UL << 7) /**< Low Energy Mode USB PHY Control */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define _USB_CTRL_LEMPHYCTRL_SHIFT 7 /**< Shift value for USB_LEMPHYCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define _USB_CTRL_LEMPHYCTRL_MASK 0x80UL /**< Bit mask for USB_LEMPHYCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define _USB_CTRL_LEMPHYCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define _USB_CTRL_LEMPHYCTRL_NONE 0x00000000UL /**< Mode NONE for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define _USB_CTRL_LEMPHYCTRL_LEM 0x00000001UL /**< Mode LEM for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define USB_CTRL_LEMPHYCTRL_DEFAULT (_USB_CTRL_LEMPHYCTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define USB_CTRL_LEMPHYCTRL_NONE (_USB_CTRL_LEMPHYCTRL_NONE << 7) /**< Shifted mode NONE for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define USB_CTRL_LEMPHYCTRL_LEM (_USB_CTRL_LEMPHYCTRL_LEM << 7) /**< Shifted mode LEM for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define USB_CTRL_LEMIDLEEN (0x1UL << 9) /**< Low Energy Mode on Bus Idle Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define _USB_CTRL_LEMIDLEEN_SHIFT 9 /**< Shift value for USB_LEMIDLEEN */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define _USB_CTRL_LEMIDLEEN_MASK 0x200UL /**< Bit mask for USB_LEMIDLEEN */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define _USB_CTRL_LEMIDLEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define USB_CTRL_LEMIDLEEN_DEFAULT (_USB_CTRL_LEMIDLEEN_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define USB_CTRL_LEMNAKEN (0x1UL << 10) /**< Low Energy Mode on OUT NAK Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define _USB_CTRL_LEMNAKEN_SHIFT 10 /**< Shift value for USB_LEMNAKEN */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define _USB_CTRL_LEMNAKEN_MASK 0x400UL /**< Bit mask for USB_LEMNAKEN */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define _USB_CTRL_LEMNAKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define USB_CTRL_LEMNAKEN_DEFAULT (_USB_CTRL_LEMNAKEN_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define USB_CTRL_LEMADDRMEN (0x1UL << 11) /**< Low Energy Mode on Device Address Mismatch Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define _USB_CTRL_LEMADDRMEN_SHIFT 11 /**< Shift value for USB_LEMADDRMEN */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define _USB_CTRL_LEMADDRMEN_MASK 0x800UL /**< Bit mask for USB_LEMADDRMEN */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define _USB_CTRL_LEMADDRMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define USB_CTRL_LEMADDRMEN_DEFAULT (_USB_CTRL_LEMADDRMEN_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define USB_CTRL_VREGDIS (0x1UL << 16) /**< Voltage Regulator Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define _USB_CTRL_VREGDIS_SHIFT 16 /**< Shift value for USB_VREGDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define _USB_CTRL_VREGDIS_MASK 0x10000UL /**< Bit mask for USB_VREGDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define _USB_CTRL_VREGDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define USB_CTRL_VREGDIS_DEFAULT (_USB_CTRL_VREGDIS_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define USB_CTRL_VREGOSEN (0x1UL << 17) /**< VREGO Sense Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define _USB_CTRL_VREGOSEN_SHIFT 17 /**< Shift value for USB_VREGOSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define _USB_CTRL_VREGOSEN_MASK 0x20000UL /**< Bit mask for USB_VREGOSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define _USB_CTRL_VREGOSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define USB_CTRL_VREGOSEN_DEFAULT (_USB_CTRL_VREGOSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define _USB_CTRL_BIASPROGEM01_SHIFT 20 /**< Shift value for USB_BIASPROGEM01 */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define _USB_CTRL_BIASPROGEM01_MASK 0x300000UL /**< Bit mask for USB_BIASPROGEM01 */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define _USB_CTRL_BIASPROGEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define USB_CTRL_BIASPROGEM01_DEFAULT (_USB_CTRL_BIASPROGEM01_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define _USB_CTRL_BIASPROGEM23_SHIFT 24 /**< Shift value for USB_BIASPROGEM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define _USB_CTRL_BIASPROGEM23_MASK 0x3000000UL /**< Bit mask for USB_BIASPROGEM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define _USB_CTRL_BIASPROGEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define USB_CTRL_BIASPROGEM23_DEFAULT (_USB_CTRL_BIASPROGEM23_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 194 | |
| AnnaBridge | 171:3a7713b1edbc | 195 | /* Bit fields for USB STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define _USB_STATUS_RESETVALUE 0x00000000UL /**< Default value for USB_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define _USB_STATUS_MASK 0x00000005UL /**< Mask for USB_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define USB_STATUS_VREGOS (0x1UL << 0) /**< VREGO Sense Output */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define _USB_STATUS_VREGOS_SHIFT 0 /**< Shift value for USB_VREGOS */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define _USB_STATUS_VREGOS_MASK 0x1UL /**< Bit mask for USB_VREGOS */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define _USB_STATUS_VREGOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define USB_STATUS_VREGOS_DEFAULT (_USB_STATUS_VREGOS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define USB_STATUS_LEMACTIVE (0x1UL << 2) /**< Low Energy Mode Active */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define _USB_STATUS_LEMACTIVE_SHIFT 2 /**< Shift value for USB_LEMACTIVE */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define _USB_STATUS_LEMACTIVE_MASK 0x4UL /**< Bit mask for USB_LEMACTIVE */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define _USB_STATUS_LEMACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define USB_STATUS_LEMACTIVE_DEFAULT (_USB_STATUS_LEMACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | |
| AnnaBridge | 171:3a7713b1edbc | 209 | /* Bit fields for USB IF */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define _USB_IF_RESETVALUE 0x00000003UL /**< Default value for USB_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define _USB_IF_MASK 0x00000003UL /**< Mask for USB_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define USB_IF_VREGOSH (0x1UL << 0) /**< VREGO Sense High Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define _USB_IF_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define _USB_IF_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define _USB_IF_VREGOSH_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define USB_IF_VREGOSH_DEFAULT (_USB_IF_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define USB_IF_VREGOSL (0x1UL << 1) /**< VREGO Sense Low Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define _USB_IF_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */ |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define _USB_IF_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define _USB_IF_VREGOSL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define USB_IF_VREGOSL_DEFAULT (_USB_IF_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | |
| AnnaBridge | 171:3a7713b1edbc | 223 | /* Bit fields for USB IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define _USB_IFS_RESETVALUE 0x00000000UL /**< Default value for USB_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 225 | #define _USB_IFS_MASK 0x00000003UL /**< Mask for USB_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define USB_IFS_VREGOSH (0x1UL << 0) /**< Set VREGO Sense High Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define _USB_IFS_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define _USB_IFS_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define _USB_IFS_VREGOSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define USB_IFS_VREGOSH_DEFAULT (_USB_IFS_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define USB_IFS_VREGOSL (0x1UL << 1) /**< Set VREGO Sense Low Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define _USB_IFS_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define _USB_IFS_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */ |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define _USB_IFS_VREGOSL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define USB_IFS_VREGOSL_DEFAULT (_USB_IFS_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 236 | |
| AnnaBridge | 171:3a7713b1edbc | 237 | /* Bit fields for USB IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define _USB_IFC_RESETVALUE 0x00000000UL /**< Default value for USB_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define _USB_IFC_MASK 0x00000003UL /**< Mask for USB_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define USB_IFC_VREGOSH (0x1UL << 0) /**< Clear VREGO Sense High Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define _USB_IFC_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define _USB_IFC_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define _USB_IFC_VREGOSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define USB_IFC_VREGOSH_DEFAULT (_USB_IFC_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define USB_IFC_VREGOSL (0x1UL << 1) /**< Clear VREGO Sense Low Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define _USB_IFC_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */ |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define _USB_IFC_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define _USB_IFC_VREGOSL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define USB_IFC_VREGOSL_DEFAULT (_USB_IFC_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | |
| AnnaBridge | 171:3a7713b1edbc | 251 | /* Bit fields for USB IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define _USB_IEN_RESETVALUE 0x00000000UL /**< Default value for USB_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define _USB_IEN_MASK 0x00000003UL /**< Mask for USB_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define USB_IEN_VREGOSH (0x1UL << 0) /**< VREGO Sense High Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define _USB_IEN_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define _USB_IEN_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */ |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define _USB_IEN_VREGOSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define USB_IEN_VREGOSH_DEFAULT (_USB_IEN_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define USB_IEN_VREGOSL (0x1UL << 1) /**< VREGO Sense Low Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define _USB_IEN_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define _USB_IEN_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define _USB_IEN_VREGOSL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define USB_IEN_VREGOSL_DEFAULT (_USB_IEN_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | |
| AnnaBridge | 171:3a7713b1edbc | 265 | /* Bit fields for USB ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define _USB_ROUTE_RESETVALUE 0x00000000UL /**< Default value for USB_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define _USB_ROUTE_MASK 0x00000005UL /**< Mask for USB_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define USB_ROUTE_PHYPEN (0x1UL << 0) /**< USB PHY Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define _USB_ROUTE_PHYPEN_SHIFT 0 /**< Shift value for USB_PHYPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define _USB_ROUTE_PHYPEN_MASK 0x1UL /**< Bit mask for USB_PHYPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define _USB_ROUTE_PHYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define USB_ROUTE_PHYPEN_DEFAULT (_USB_ROUTE_PHYPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define USB_ROUTE_DMPUPEN (0x1UL << 2) /**< DMPU Pin Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define _USB_ROUTE_DMPUPEN_SHIFT 2 /**< Shift value for USB_DMPUPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define _USB_ROUTE_DMPUPEN_MASK 0x4UL /**< Bit mask for USB_DMPUPEN */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define _USB_ROUTE_DMPUPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define USB_ROUTE_DMPUPEN_DEFAULT (_USB_ROUTE_DMPUPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | |
| AnnaBridge | 171:3a7713b1edbc | 279 | /* Bit fields for USB GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define _USB_GAHBCFG_RESETVALUE 0x00000000UL /**< Default value for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define _USB_GAHBCFG_MASK 0x00E000BFUL /**< Mask for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define USB_GAHBCFG_GLBLINTRMSK (0x1UL << 0) /**< Global Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define _USB_GAHBCFG_GLBLINTRMSK_SHIFT 0 /**< Shift value for USB_GLBLINTRMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define _USB_GAHBCFG_GLBLINTRMSK_MASK 0x1UL /**< Bit mask for USB_GLBLINTRMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define _USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define USB_GAHBCFG_GLBLINTRMSK_DEFAULT (_USB_GAHBCFG_GLBLINTRMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define _USB_GAHBCFG_HBSTLEN_SHIFT 1 /**< Shift value for USB_HBSTLEN */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define _USB_GAHBCFG_HBSTLEN_MASK 0x1EUL /**< Bit mask for USB_HBSTLEN */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define _USB_GAHBCFG_HBSTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define _USB_GAHBCFG_HBSTLEN_SINGLE 0x00000000UL /**< Mode SINGLE for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define _USB_GAHBCFG_HBSTLEN_INCR 0x00000001UL /**< Mode INCR for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define _USB_GAHBCFG_HBSTLEN_INCR4 0x00000003UL /**< Mode INCR4 for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define _USB_GAHBCFG_HBSTLEN_INCR8 0x00000005UL /**< Mode INCR8 for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define _USB_GAHBCFG_HBSTLEN_INCR16 0x00000007UL /**< Mode INCR16 for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define USB_GAHBCFG_HBSTLEN_DEFAULT (_USB_GAHBCFG_HBSTLEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define USB_GAHBCFG_HBSTLEN_SINGLE (_USB_GAHBCFG_HBSTLEN_SINGLE << 1) /**< Shifted mode SINGLE for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define USB_GAHBCFG_HBSTLEN_INCR (_USB_GAHBCFG_HBSTLEN_INCR << 1) /**< Shifted mode INCR for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define USB_GAHBCFG_HBSTLEN_INCR4 (_USB_GAHBCFG_HBSTLEN_INCR4 << 1) /**< Shifted mode INCR4 for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define USB_GAHBCFG_HBSTLEN_INCR8 (_USB_GAHBCFG_HBSTLEN_INCR8 << 1) /**< Shifted mode INCR8 for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define USB_GAHBCFG_HBSTLEN_INCR16 (_USB_GAHBCFG_HBSTLEN_INCR16 << 1) /**< Shifted mode INCR16 for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | #define USB_GAHBCFG_DMAEN (0x1UL << 5) /**< DMA Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define _USB_GAHBCFG_DMAEN_SHIFT 5 /**< Shift value for USB_DMAEN */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define _USB_GAHBCFG_DMAEN_MASK 0x20UL /**< Bit mask for USB_DMAEN */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define _USB_GAHBCFG_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define USB_GAHBCFG_DMAEN_DEFAULT (_USB_GAHBCFG_DMAEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define USB_GAHBCFG_NPTXFEMPLVL (0x1UL << 7) /**< Non-Periodic TxFIFO Empty Level */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define _USB_GAHBCFG_NPTXFEMPLVL_SHIFT 7 /**< Shift value for USB_NPTXFEMPLVL */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define _USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80UL /**< Bit mask for USB_NPTXFEMPLVL */ |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define _USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define _USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY 0x00000000UL /**< Mode HALFEMPTY for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define _USB_GAHBCFG_NPTXFEMPLVL_EMPTY 0x00000001UL /**< Mode EMPTY for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define USB_GAHBCFG_NPTXFEMPLVL_DEFAULT (_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY << 7) /**< Shifted mode HALFEMPTY for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define USB_GAHBCFG_NPTXFEMPLVL_EMPTY (_USB_GAHBCFG_NPTXFEMPLVL_EMPTY << 7) /**< Shifted mode EMPTY for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define USB_GAHBCFG_REMMEMSUPP (0x1UL << 21) /**< Remote Memory Support */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define _USB_GAHBCFG_REMMEMSUPP_SHIFT 21 /**< Shift value for USB_REMMEMSUPP */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define _USB_GAHBCFG_REMMEMSUPP_MASK 0x200000UL /**< Bit mask for USB_REMMEMSUPP */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define _USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define USB_GAHBCFG_REMMEMSUPP_DEFAULT (_USB_GAHBCFG_REMMEMSUPP_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define USB_GAHBCFG_NOTIALLDMAWRIT (0x1UL << 22) /**< Notify All DMA Writes */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define _USB_GAHBCFG_NOTIALLDMAWRIT_SHIFT 22 /**< Shift value for USB_NOTIALLDMAWRIT */ |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define _USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000UL /**< Bit mask for USB_NOTIALLDMAWRIT */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | #define _USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 324 | #define USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT (_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define USB_GAHBCFG_AHBSINGLE (0x1UL << 23) /**< AHB Single Support */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define _USB_GAHBCFG_AHBSINGLE_SHIFT 23 /**< Shift value for USB_AHBSINGLE */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define _USB_GAHBCFG_AHBSINGLE_MASK 0x800000UL /**< Bit mask for USB_AHBSINGLE */ |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define _USB_GAHBCFG_AHBSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define USB_GAHBCFG_AHBSINGLE_DEFAULT (_USB_GAHBCFG_AHBSINGLE_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GAHBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 330 | |
| AnnaBridge | 171:3a7713b1edbc | 331 | /* Bit fields for USB GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define _USB_GUSBCFG_RESETVALUE 0x00001440UL /**< Default value for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define _USB_GUSBCFG_MASK 0x90403C27UL /**< Mask for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define _USB_GUSBCFG_TOUTCAL_SHIFT 0 /**< Shift value for USB_TOUTCAL */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define _USB_GUSBCFG_TOUTCAL_MASK 0x7UL /**< Bit mask for USB_TOUTCAL */ |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define _USB_GUSBCFG_TOUTCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define USB_GUSBCFG_TOUTCAL_DEFAULT (_USB_GUSBCFG_TOUTCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define USB_GUSBCFG_FSINTF (0x1UL << 5) /**< Full-Speed Serial Interface Select */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define _USB_GUSBCFG_FSINTF_SHIFT 5 /**< Shift value for USB_FSINTF */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define _USB_GUSBCFG_FSINTF_MASK 0x20UL /**< Bit mask for USB_FSINTF */ |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define _USB_GUSBCFG_FSINTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | #define USB_GUSBCFG_FSINTF_DEFAULT (_USB_GUSBCFG_FSINTF_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define _USB_GUSBCFG_USBTRDTIM_SHIFT 10 /**< Shift value for USB_USBTRDTIM */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define _USB_GUSBCFG_USBTRDTIM_MASK 0x3C00UL /**< Bit mask for USB_USBTRDTIM */ |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define _USB_GUSBCFG_USBTRDTIM_DEFAULT 0x00000005UL /**< Mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define USB_GUSBCFG_USBTRDTIM_DEFAULT (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define USB_GUSBCFG_TERMSELDLPULSE (0x1UL << 22) /**< TermSel DLine Pulsing Selection */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT 22 /**< Shift value for USB_TERMSELDLPULSE */ |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define _USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000UL /**< Bit mask for USB_TERMSELDLPULSE */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define _USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define _USB_GUSBCFG_TERMSELDLPULSE_TXVALID 0x00000000UL /**< Mode TXVALID for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define _USB_GUSBCFG_TERMSELDLPULSE_TERMSEL 0x00000001UL /**< Mode TERMSEL for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define USB_GUSBCFG_TERMSELDLPULSE_DEFAULT (_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define USB_GUSBCFG_TERMSELDLPULSE_TXVALID (_USB_GUSBCFG_TERMSELDLPULSE_TXVALID << 22) /**< Shifted mode TXVALID for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define USB_GUSBCFG_TERMSELDLPULSE_TERMSEL (_USB_GUSBCFG_TERMSELDLPULSE_TERMSEL << 22) /**< Shifted mode TERMSEL for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define USB_GUSBCFG_TXENDDELAY (0x1UL << 28) /**< Tx End Delay */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define _USB_GUSBCFG_TXENDDELAY_SHIFT 28 /**< Shift value for USB_TXENDDELAY */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define _USB_GUSBCFG_TXENDDELAY_MASK 0x10000000UL /**< Bit mask for USB_TXENDDELAY */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define _USB_GUSBCFG_TXENDDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define USB_GUSBCFG_TXENDDELAY_DEFAULT (_USB_GUSBCFG_TXENDDELAY_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define USB_GUSBCFG_CORRUPTTXPKT (0x1UL << 31) /**< Corrupt Tx packet */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define _USB_GUSBCFG_CORRUPTTXPKT_SHIFT 31 /**< Shift value for USB_CORRUPTTXPKT */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define _USB_GUSBCFG_CORRUPTTXPKT_MASK 0x80000000UL /**< Bit mask for USB_CORRUPTTXPKT */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define _USB_GUSBCFG_CORRUPTTXPKT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define USB_GUSBCFG_CORRUPTTXPKT_DEFAULT (_USB_GUSBCFG_CORRUPTTXPKT_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GUSBCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | |
| AnnaBridge | 171:3a7713b1edbc | 367 | /* Bit fields for USB GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define _USB_GRSTCTL_RESETVALUE 0x80000000UL /**< Default value for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define _USB_GRSTCTL_MASK 0xC00007F3UL /**< Mask for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define USB_GRSTCTL_CSFTRST (0x1UL << 0) /**< Core Soft Reset */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define _USB_GRSTCTL_CSFTRST_SHIFT 0 /**< Shift value for USB_CSFTRST */ |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define _USB_GRSTCTL_CSFTRST_MASK 0x1UL /**< Bit mask for USB_CSFTRST */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | #define _USB_GRSTCTL_CSFTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 374 | #define USB_GRSTCTL_CSFTRST_DEFAULT (_USB_GRSTCTL_CSFTRST_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define USB_GRSTCTL_PIUFSSFTRST (0x1UL << 1) /**< PIU FS Dedicated Controller Soft Reset */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define _USB_GRSTCTL_PIUFSSFTRST_SHIFT 1 /**< Shift value for USB_PIUFSSFTRST */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | #define _USB_GRSTCTL_PIUFSSFTRST_MASK 0x2UL /**< Bit mask for USB_PIUFSSFTRST */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define _USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define USB_GRSTCTL_PIUFSSFTRST_DEFAULT (_USB_GRSTCTL_PIUFSSFTRST_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define USB_GRSTCTL_RXFFLSH (0x1UL << 4) /**< RxFIFO Flush */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define _USB_GRSTCTL_RXFFLSH_SHIFT 4 /**< Shift value for USB_RXFFLSH */ |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define _USB_GRSTCTL_RXFFLSH_MASK 0x10UL /**< Bit mask for USB_RXFFLSH */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define _USB_GRSTCTL_RXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define USB_GRSTCTL_RXFFLSH_DEFAULT (_USB_GRSTCTL_RXFFLSH_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define USB_GRSTCTL_TXFFLSH (0x1UL << 5) /**< TxFIFO Flush */ |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define _USB_GRSTCTL_TXFFLSH_SHIFT 5 /**< Shift value for USB_TXFFLSH */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define _USB_GRSTCTL_TXFFLSH_MASK 0x20UL /**< Bit mask for USB_TXFFLSH */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define _USB_GRSTCTL_TXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define USB_GRSTCTL_TXFFLSH_DEFAULT (_USB_GRSTCTL_TXFFLSH_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define _USB_GRSTCTL_TXFNUM_SHIFT 6 /**< Shift value for USB_TXFNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define _USB_GRSTCTL_TXFNUM_MASK 0x7C0UL /**< Bit mask for USB_TXFNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 392 | #define _USB_GRSTCTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | #define _USB_GRSTCTL_TXFNUM_F0 0x00000000UL /**< Mode F0 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define _USB_GRSTCTL_TXFNUM_F1 0x00000001UL /**< Mode F1 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define _USB_GRSTCTL_TXFNUM_F2 0x00000002UL /**< Mode F2 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define _USB_GRSTCTL_TXFNUM_F3 0x00000003UL /**< Mode F3 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define _USB_GRSTCTL_TXFNUM_F4 0x00000004UL /**< Mode F4 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define _USB_GRSTCTL_TXFNUM_F5 0x00000005UL /**< Mode F5 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define _USB_GRSTCTL_TXFNUM_F6 0x00000006UL /**< Mode F6 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define _USB_GRSTCTL_TXFNUM_FALL 0x00000010UL /**< Mode FALL for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define USB_GRSTCTL_TXFNUM_DEFAULT (_USB_GRSTCTL_TXFNUM_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define USB_GRSTCTL_TXFNUM_F0 (_USB_GRSTCTL_TXFNUM_F0 << 6) /**< Shifted mode F0 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define USB_GRSTCTL_TXFNUM_F1 (_USB_GRSTCTL_TXFNUM_F1 << 6) /**< Shifted mode F1 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define USB_GRSTCTL_TXFNUM_F2 (_USB_GRSTCTL_TXFNUM_F2 << 6) /**< Shifted mode F2 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define USB_GRSTCTL_TXFNUM_F3 (_USB_GRSTCTL_TXFNUM_F3 << 6) /**< Shifted mode F3 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define USB_GRSTCTL_TXFNUM_F4 (_USB_GRSTCTL_TXFNUM_F4 << 6) /**< Shifted mode F4 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define USB_GRSTCTL_TXFNUM_F5 (_USB_GRSTCTL_TXFNUM_F5 << 6) /**< Shifted mode F5 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define USB_GRSTCTL_TXFNUM_F6 (_USB_GRSTCTL_TXFNUM_F6 << 6) /**< Shifted mode F6 for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 409 | #define USB_GRSTCTL_TXFNUM_FALL (_USB_GRSTCTL_TXFNUM_FALL << 6) /**< Shifted mode FALL for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 410 | #define USB_GRSTCTL_DMAREQ (0x1UL << 30) /**< DMA Request Signal */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define _USB_GRSTCTL_DMAREQ_SHIFT 30 /**< Shift value for USB_DMAREQ */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define _USB_GRSTCTL_DMAREQ_MASK 0x40000000UL /**< Bit mask for USB_DMAREQ */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define _USB_GRSTCTL_DMAREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define USB_GRSTCTL_DMAREQ_DEFAULT (_USB_GRSTCTL_DMAREQ_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define USB_GRSTCTL_AHBIDLE (0x1UL << 31) /**< AHB Master Idle */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define _USB_GRSTCTL_AHBIDLE_SHIFT 31 /**< Shift value for USB_AHBIDLE */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define _USB_GRSTCTL_AHBIDLE_MASK 0x80000000UL /**< Bit mask for USB_AHBIDLE */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | #define _USB_GRSTCTL_AHBIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define USB_GRSTCTL_AHBIDLE_DEFAULT (_USB_GRSTCTL_AHBIDLE_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GRSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | |
| AnnaBridge | 171:3a7713b1edbc | 421 | /* Bit fields for USB GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 422 | #define _USB_GINTSTS_RESETVALUE 0x00000000UL /**< Default value for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 423 | #define _USB_GINTSTS_MASK 0x80FCFCD9UL /**< Mask for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 424 | #define USB_GINTSTS_CURMOD (0x1UL << 0) /**< Current Mode of Operation */ |
| AnnaBridge | 171:3a7713b1edbc | 425 | #define _USB_GINTSTS_CURMOD_SHIFT 0 /**< Shift value for USB_CURMOD */ |
| AnnaBridge | 171:3a7713b1edbc | 426 | #define _USB_GINTSTS_CURMOD_MASK 0x1UL /**< Bit mask for USB_CURMOD */ |
| AnnaBridge | 171:3a7713b1edbc | 427 | #define _USB_GINTSTS_CURMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 428 | #define _USB_GINTSTS_CURMOD_DEVICE 0x00000000UL /**< Mode DEVICE for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define USB_GINTSTS_CURMOD_DEFAULT (_USB_GINTSTS_CURMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 430 | #define USB_GINTSTS_CURMOD_DEVICE (_USB_GINTSTS_CURMOD_DEVICE << 0) /**< Shifted mode DEVICE for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | #define USB_GINTSTS_SOF (0x1UL << 3) /**< Start of Frame */ |
| AnnaBridge | 171:3a7713b1edbc | 432 | #define _USB_GINTSTS_SOF_SHIFT 3 /**< Shift value for USB_SOF */ |
| AnnaBridge | 171:3a7713b1edbc | 433 | #define _USB_GINTSTS_SOF_MASK 0x8UL /**< Bit mask for USB_SOF */ |
| AnnaBridge | 171:3a7713b1edbc | 434 | #define _USB_GINTSTS_SOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 435 | #define USB_GINTSTS_SOF_DEFAULT (_USB_GINTSTS_SOF_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | #define USB_GINTSTS_RXFLVL (0x1UL << 4) /**< RxFIFO Non-Empty */ |
| AnnaBridge | 171:3a7713b1edbc | 437 | #define _USB_GINTSTS_RXFLVL_SHIFT 4 /**< Shift value for USB_RXFLVL */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | #define _USB_GINTSTS_RXFLVL_MASK 0x10UL /**< Bit mask for USB_RXFLVL */ |
| AnnaBridge | 171:3a7713b1edbc | 439 | #define _USB_GINTSTS_RXFLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define USB_GINTSTS_RXFLVL_DEFAULT (_USB_GINTSTS_RXFLVL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define USB_GINTSTS_GINNAKEFF (0x1UL << 6) /**< Global IN Non-periodic NAK Effective */ |
| AnnaBridge | 171:3a7713b1edbc | 442 | #define _USB_GINTSTS_GINNAKEFF_SHIFT 6 /**< Shift value for USB_GINNAKEFF */ |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define _USB_GINTSTS_GINNAKEFF_MASK 0x40UL /**< Bit mask for USB_GINNAKEFF */ |
| AnnaBridge | 171:3a7713b1edbc | 444 | #define _USB_GINTSTS_GINNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 445 | #define USB_GINTSTS_GINNAKEFF_DEFAULT (_USB_GINTSTS_GINNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 446 | #define USB_GINTSTS_GOUTNAKEFF (0x1UL << 7) /**< Global OUT NAK Effective */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | #define _USB_GINTSTS_GOUTNAKEFF_SHIFT 7 /**< Shift value for USB_GOUTNAKEFF */ |
| AnnaBridge | 171:3a7713b1edbc | 448 | #define _USB_GINTSTS_GOUTNAKEFF_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFF */ |
| AnnaBridge | 171:3a7713b1edbc | 449 | #define _USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define USB_GINTSTS_GOUTNAKEFF_DEFAULT (_USB_GINTSTS_GOUTNAKEFF_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define USB_GINTSTS_ERLYSUSP (0x1UL << 10) /**< Early Suspend */ |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define _USB_GINTSTS_ERLYSUSP_SHIFT 10 /**< Shift value for USB_ERLYSUSP */ |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define _USB_GINTSTS_ERLYSUSP_MASK 0x400UL /**< Bit mask for USB_ERLYSUSP */ |
| AnnaBridge | 171:3a7713b1edbc | 454 | #define _USB_GINTSTS_ERLYSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define USB_GINTSTS_ERLYSUSP_DEFAULT (_USB_GINTSTS_ERLYSUSP_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 456 | #define USB_GINTSTS_USBSUSP (0x1UL << 11) /**< USB Suspend */ |
| AnnaBridge | 171:3a7713b1edbc | 457 | #define _USB_GINTSTS_USBSUSP_SHIFT 11 /**< Shift value for USB_USBSUSP */ |
| AnnaBridge | 171:3a7713b1edbc | 458 | #define _USB_GINTSTS_USBSUSP_MASK 0x800UL /**< Bit mask for USB_USBSUSP */ |
| AnnaBridge | 171:3a7713b1edbc | 459 | #define _USB_GINTSTS_USBSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 460 | #define USB_GINTSTS_USBSUSP_DEFAULT (_USB_GINTSTS_USBSUSP_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 461 | #define USB_GINTSTS_USBRST (0x1UL << 12) /**< USB Reset */ |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define _USB_GINTSTS_USBRST_SHIFT 12 /**< Shift value for USB_USBRST */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define _USB_GINTSTS_USBRST_MASK 0x1000UL /**< Bit mask for USB_USBRST */ |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define _USB_GINTSTS_USBRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 465 | #define USB_GINTSTS_USBRST_DEFAULT (_USB_GINTSTS_USBRST_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 466 | #define USB_GINTSTS_ENUMDONE (0x1UL << 13) /**< Enumeration Done */ |
| AnnaBridge | 171:3a7713b1edbc | 467 | #define _USB_GINTSTS_ENUMDONE_SHIFT 13 /**< Shift value for USB_ENUMDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 468 | #define _USB_GINTSTS_ENUMDONE_MASK 0x2000UL /**< Bit mask for USB_ENUMDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 469 | #define _USB_GINTSTS_ENUMDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 470 | #define USB_GINTSTS_ENUMDONE_DEFAULT (_USB_GINTSTS_ENUMDONE_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 471 | #define USB_GINTSTS_ISOOUTDROP (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 472 | #define _USB_GINTSTS_ISOOUTDROP_SHIFT 14 /**< Shift value for USB_ISOOUTDROP */ |
| AnnaBridge | 171:3a7713b1edbc | 473 | #define _USB_GINTSTS_ISOOUTDROP_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROP */ |
| AnnaBridge | 171:3a7713b1edbc | 474 | #define _USB_GINTSTS_ISOOUTDROP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 475 | #define USB_GINTSTS_ISOOUTDROP_DEFAULT (_USB_GINTSTS_ISOOUTDROP_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 476 | #define USB_GINTSTS_EOPF (0x1UL << 15) /**< End of Periodic Frame Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 477 | #define _USB_GINTSTS_EOPF_SHIFT 15 /**< Shift value for USB_EOPF */ |
| AnnaBridge | 171:3a7713b1edbc | 478 | #define _USB_GINTSTS_EOPF_MASK 0x8000UL /**< Bit mask for USB_EOPF */ |
| AnnaBridge | 171:3a7713b1edbc | 479 | #define _USB_GINTSTS_EOPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 480 | #define USB_GINTSTS_EOPF_DEFAULT (_USB_GINTSTS_EOPF_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 481 | #define USB_GINTSTS_IEPINT (0x1UL << 18) /**< IN Endpoints Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 482 | #define _USB_GINTSTS_IEPINT_SHIFT 18 /**< Shift value for USB_IEPINT */ |
| AnnaBridge | 171:3a7713b1edbc | 483 | #define _USB_GINTSTS_IEPINT_MASK 0x40000UL /**< Bit mask for USB_IEPINT */ |
| AnnaBridge | 171:3a7713b1edbc | 484 | #define _USB_GINTSTS_IEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 485 | #define USB_GINTSTS_IEPINT_DEFAULT (_USB_GINTSTS_IEPINT_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | #define USB_GINTSTS_OEPINT (0x1UL << 19) /**< OUT Endpoints Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 487 | #define _USB_GINTSTS_OEPINT_SHIFT 19 /**< Shift value for USB_OEPINT */ |
| AnnaBridge | 171:3a7713b1edbc | 488 | #define _USB_GINTSTS_OEPINT_MASK 0x80000UL /**< Bit mask for USB_OEPINT */ |
| AnnaBridge | 171:3a7713b1edbc | 489 | #define _USB_GINTSTS_OEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 490 | #define USB_GINTSTS_OEPINT_DEFAULT (_USB_GINTSTS_OEPINT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 491 | #define USB_GINTSTS_INCOMPISOIN (0x1UL << 20) /**< Incomplete Isochronous IN Transfer */ |
| AnnaBridge | 171:3a7713b1edbc | 492 | #define _USB_GINTSTS_INCOMPISOIN_SHIFT 20 /**< Shift value for USB_INCOMPISOIN */ |
| AnnaBridge | 171:3a7713b1edbc | 493 | #define _USB_GINTSTS_INCOMPISOIN_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOIN */ |
| AnnaBridge | 171:3a7713b1edbc | 494 | #define _USB_GINTSTS_INCOMPISOIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 495 | #define USB_GINTSTS_INCOMPISOIN_DEFAULT (_USB_GINTSTS_INCOMPISOIN_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 496 | #define USB_GINTSTS_INCOMPLP (0x1UL << 21) /**< Incomplete Periodic Transfer */ |
| AnnaBridge | 171:3a7713b1edbc | 497 | #define _USB_GINTSTS_INCOMPLP_SHIFT 21 /**< Shift value for USB_INCOMPLP */ |
| AnnaBridge | 171:3a7713b1edbc | 498 | #define _USB_GINTSTS_INCOMPLP_MASK 0x200000UL /**< Bit mask for USB_INCOMPLP */ |
| AnnaBridge | 171:3a7713b1edbc | 499 | #define _USB_GINTSTS_INCOMPLP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 500 | #define USB_GINTSTS_INCOMPLP_DEFAULT (_USB_GINTSTS_INCOMPLP_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 501 | #define USB_GINTSTS_FETSUSP (0x1UL << 22) /**< Data Fetch Suspended */ |
| AnnaBridge | 171:3a7713b1edbc | 502 | #define _USB_GINTSTS_FETSUSP_SHIFT 22 /**< Shift value for USB_FETSUSP */ |
| AnnaBridge | 171:3a7713b1edbc | 503 | #define _USB_GINTSTS_FETSUSP_MASK 0x400000UL /**< Bit mask for USB_FETSUSP */ |
| AnnaBridge | 171:3a7713b1edbc | 504 | #define _USB_GINTSTS_FETSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 505 | #define USB_GINTSTS_FETSUSP_DEFAULT (_USB_GINTSTS_FETSUSP_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 506 | #define USB_GINTSTS_RESETDET (0x1UL << 23) /**< Reset detected Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 507 | #define _USB_GINTSTS_RESETDET_SHIFT 23 /**< Shift value for USB_RESETDET */ |
| AnnaBridge | 171:3a7713b1edbc | 508 | #define _USB_GINTSTS_RESETDET_MASK 0x800000UL /**< Bit mask for USB_RESETDET */ |
| AnnaBridge | 171:3a7713b1edbc | 509 | #define _USB_GINTSTS_RESETDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 510 | #define USB_GINTSTS_RESETDET_DEFAULT (_USB_GINTSTS_RESETDET_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 511 | #define USB_GINTSTS_WKUPINT (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 512 | #define _USB_GINTSTS_WKUPINT_SHIFT 31 /**< Shift value for USB_WKUPINT */ |
| AnnaBridge | 171:3a7713b1edbc | 513 | #define _USB_GINTSTS_WKUPINT_MASK 0x80000000UL /**< Bit mask for USB_WKUPINT */ |
| AnnaBridge | 171:3a7713b1edbc | 514 | #define _USB_GINTSTS_WKUPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 515 | #define USB_GINTSTS_WKUPINT_DEFAULT (_USB_GINTSTS_WKUPINT_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GINTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 516 | |
| AnnaBridge | 171:3a7713b1edbc | 517 | /* Bit fields for USB GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 518 | #define _USB_GINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 519 | #define _USB_GINTMSK_MASK 0x80FCFCDAUL /**< Mask for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 520 | #define USB_GINTMSK_MODEMISMSK (0x1UL << 1) /**< Mode Mismatch Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 521 | #define _USB_GINTMSK_MODEMISMSK_SHIFT 1 /**< Shift value for USB_MODEMISMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 522 | #define _USB_GINTMSK_MODEMISMSK_MASK 0x2UL /**< Bit mask for USB_MODEMISMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 523 | #define _USB_GINTMSK_MODEMISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 524 | #define USB_GINTMSK_MODEMISMSK_DEFAULT (_USB_GINTMSK_MODEMISMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 525 | #define USB_GINTMSK_SOFMSK (0x1UL << 3) /**< Start of Frame Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 526 | #define _USB_GINTMSK_SOFMSK_SHIFT 3 /**< Shift value for USB_SOFMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 527 | #define _USB_GINTMSK_SOFMSK_MASK 0x8UL /**< Bit mask for USB_SOFMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 528 | #define _USB_GINTMSK_SOFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 529 | #define USB_GINTMSK_SOFMSK_DEFAULT (_USB_GINTMSK_SOFMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 530 | #define USB_GINTMSK_RXFLVLMSK (0x1UL << 4) /**< Receive FIFO Non-Empty Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 531 | #define _USB_GINTMSK_RXFLVLMSK_SHIFT 4 /**< Shift value for USB_RXFLVLMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 532 | #define _USB_GINTMSK_RXFLVLMSK_MASK 0x10UL /**< Bit mask for USB_RXFLVLMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 533 | #define _USB_GINTMSK_RXFLVLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 534 | #define USB_GINTMSK_RXFLVLMSK_DEFAULT (_USB_GINTMSK_RXFLVLMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 535 | #define USB_GINTMSK_GINNAKEFFMSK (0x1UL << 6) /**< Global Non-periodic IN NAK Effective Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 536 | #define _USB_GINTMSK_GINNAKEFFMSK_SHIFT 6 /**< Shift value for USB_GINNAKEFFMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | #define _USB_GINTMSK_GINNAKEFFMSK_MASK 0x40UL /**< Bit mask for USB_GINNAKEFFMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 538 | #define _USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 539 | #define USB_GINTMSK_GINNAKEFFMSK_DEFAULT (_USB_GINTMSK_GINNAKEFFMSK_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 540 | #define USB_GINTMSK_GOUTNAKEFFMSK (0x1UL << 7) /**< Global OUT NAK Effective Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | #define _USB_GINTMSK_GOUTNAKEFFMSK_SHIFT 7 /**< Shift value for USB_GOUTNAKEFFMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 542 | #define _USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFFMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 543 | #define _USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 544 | #define USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT (_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 545 | #define USB_GINTMSK_ERLYSUSPMSK (0x1UL << 10) /**< Early Suspend Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 546 | #define _USB_GINTMSK_ERLYSUSPMSK_SHIFT 10 /**< Shift value for USB_ERLYSUSPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 547 | #define _USB_GINTMSK_ERLYSUSPMSK_MASK 0x400UL /**< Bit mask for USB_ERLYSUSPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 548 | #define _USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 549 | #define USB_GINTMSK_ERLYSUSPMSK_DEFAULT (_USB_GINTMSK_ERLYSUSPMSK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 550 | #define USB_GINTMSK_USBSUSPMSK (0x1UL << 11) /**< USB Suspend Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 551 | #define _USB_GINTMSK_USBSUSPMSK_SHIFT 11 /**< Shift value for USB_USBSUSPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 552 | #define _USB_GINTMSK_USBSUSPMSK_MASK 0x800UL /**< Bit mask for USB_USBSUSPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 553 | #define _USB_GINTMSK_USBSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 554 | #define USB_GINTMSK_USBSUSPMSK_DEFAULT (_USB_GINTMSK_USBSUSPMSK_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 555 | #define USB_GINTMSK_USBRSTMSK (0x1UL << 12) /**< USB Reset Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 556 | #define _USB_GINTMSK_USBRSTMSK_SHIFT 12 /**< Shift value for USB_USBRSTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 557 | #define _USB_GINTMSK_USBRSTMSK_MASK 0x1000UL /**< Bit mask for USB_USBRSTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 558 | #define _USB_GINTMSK_USBRSTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 559 | #define USB_GINTMSK_USBRSTMSK_DEFAULT (_USB_GINTMSK_USBRSTMSK_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 560 | #define USB_GINTMSK_ENUMDONEMSK (0x1UL << 13) /**< Enumeration Done Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 561 | #define _USB_GINTMSK_ENUMDONEMSK_SHIFT 13 /**< Shift value for USB_ENUMDONEMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 562 | #define _USB_GINTMSK_ENUMDONEMSK_MASK 0x2000UL /**< Bit mask for USB_ENUMDONEMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 563 | #define _USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 564 | #define USB_GINTMSK_ENUMDONEMSK_DEFAULT (_USB_GINTMSK_ENUMDONEMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 565 | #define USB_GINTMSK_ISOOUTDROPMSK (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | #define _USB_GINTMSK_ISOOUTDROPMSK_SHIFT 14 /**< Shift value for USB_ISOOUTDROPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 567 | #define _USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 568 | #define _USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 569 | #define USB_GINTMSK_ISOOUTDROPMSK_DEFAULT (_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 570 | #define USB_GINTMSK_EOPFMSK (0x1UL << 15) /**< End of Periodic Frame Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 571 | #define _USB_GINTMSK_EOPFMSK_SHIFT 15 /**< Shift value for USB_EOPFMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 572 | #define _USB_GINTMSK_EOPFMSK_MASK 0x8000UL /**< Bit mask for USB_EOPFMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 573 | #define _USB_GINTMSK_EOPFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | #define USB_GINTMSK_EOPFMSK_DEFAULT (_USB_GINTMSK_EOPFMSK_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 575 | #define USB_GINTMSK_IEPINTMSK (0x1UL << 18) /**< IN Endpoints Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 576 | #define _USB_GINTMSK_IEPINTMSK_SHIFT 18 /**< Shift value for USB_IEPINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 577 | #define _USB_GINTMSK_IEPINTMSK_MASK 0x40000UL /**< Bit mask for USB_IEPINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 578 | #define _USB_GINTMSK_IEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 579 | #define USB_GINTMSK_IEPINTMSK_DEFAULT (_USB_GINTMSK_IEPINTMSK_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 580 | #define USB_GINTMSK_OEPINTMSK (0x1UL << 19) /**< OUT Endpoints Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 581 | #define _USB_GINTMSK_OEPINTMSK_SHIFT 19 /**< Shift value for USB_OEPINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 582 | #define _USB_GINTMSK_OEPINTMSK_MASK 0x80000UL /**< Bit mask for USB_OEPINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 583 | #define _USB_GINTMSK_OEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 584 | #define USB_GINTMSK_OEPINTMSK_DEFAULT (_USB_GINTMSK_OEPINTMSK_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 585 | #define USB_GINTMSK_INCOMPISOINMSK (0x1UL << 20) /**< Incomplete Isochronous IN Transfer Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 586 | #define _USB_GINTMSK_INCOMPISOINMSK_SHIFT 20 /**< Shift value for USB_INCOMPISOINMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 587 | #define _USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOINMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 588 | #define _USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define USB_GINTMSK_INCOMPISOINMSK_DEFAULT (_USB_GINTMSK_INCOMPISOINMSK_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 590 | #define USB_GINTMSK_INCOMPLPMSK (0x1UL << 21) /**< Incomplete Periodic Transfer Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 591 | #define _USB_GINTMSK_INCOMPLPMSK_SHIFT 21 /**< Shift value for USB_INCOMPLPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 592 | #define _USB_GINTMSK_INCOMPLPMSK_MASK 0x200000UL /**< Bit mask for USB_INCOMPLPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 593 | #define _USB_GINTMSK_INCOMPLPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 594 | #define USB_GINTMSK_INCOMPLPMSK_DEFAULT (_USB_GINTMSK_INCOMPLPMSK_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 595 | #define USB_GINTMSK_FETSUSPMSK (0x1UL << 22) /**< Data Fetch Suspended Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 596 | #define _USB_GINTMSK_FETSUSPMSK_SHIFT 22 /**< Shift value for USB_FETSUSPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 597 | #define _USB_GINTMSK_FETSUSPMSK_MASK 0x400000UL /**< Bit mask for USB_FETSUSPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 598 | #define _USB_GINTMSK_FETSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 599 | #define USB_GINTMSK_FETSUSPMSK_DEFAULT (_USB_GINTMSK_FETSUSPMSK_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 600 | #define USB_GINTMSK_RESETDETMSK (0x1UL << 23) /**< Reset detected Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 601 | #define _USB_GINTMSK_RESETDETMSK_SHIFT 23 /**< Shift value for USB_RESETDETMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 602 | #define _USB_GINTMSK_RESETDETMSK_MASK 0x800000UL /**< Bit mask for USB_RESETDETMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 603 | #define _USB_GINTMSK_RESETDETMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 604 | #define USB_GINTMSK_RESETDETMSK_DEFAULT (_USB_GINTMSK_RESETDETMSK_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 605 | #define USB_GINTMSK_WKUPINTMSK (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 606 | #define _USB_GINTMSK_WKUPINTMSK_SHIFT 31 /**< Shift value for USB_WKUPINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 607 | #define _USB_GINTMSK_WKUPINTMSK_MASK 0x80000000UL /**< Bit mask for USB_WKUPINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 608 | #define _USB_GINTMSK_WKUPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 609 | #define USB_GINTMSK_WKUPINTMSK_DEFAULT (_USB_GINTMSK_WKUPINTMSK_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 610 | |
| AnnaBridge | 171:3a7713b1edbc | 611 | /* Bit fields for USB GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 612 | #define _USB_GRXSTSR_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 613 | #define _USB_GRXSTSR_MASK 0x01FFFFFFUL /**< Mask for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 614 | #define _USB_GRXSTSR_CHEPNUM_SHIFT 0 /**< Shift value for USB_CHEPNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 615 | #define _USB_GRXSTSR_CHEPNUM_MASK 0xFUL /**< Bit mask for USB_CHEPNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 616 | #define _USB_GRXSTSR_CHEPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 617 | #define USB_GRXSTSR_CHEPNUM_DEFAULT (_USB_GRXSTSR_CHEPNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 618 | #define _USB_GRXSTSR_BCNT_SHIFT 4 /**< Shift value for USB_BCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 619 | #define _USB_GRXSTSR_BCNT_MASK 0x7FF0UL /**< Bit mask for USB_BCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 620 | #define _USB_GRXSTSR_BCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 621 | #define USB_GRXSTSR_BCNT_DEFAULT (_USB_GRXSTSR_BCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 622 | #define _USB_GRXSTSR_DPID_SHIFT 15 /**< Shift value for USB_DPID */ |
| AnnaBridge | 171:3a7713b1edbc | 623 | #define _USB_GRXSTSR_DPID_MASK 0x18000UL /**< Bit mask for USB_DPID */ |
| AnnaBridge | 171:3a7713b1edbc | 624 | #define _USB_GRXSTSR_DPID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 625 | #define _USB_GRXSTSR_DPID_DATA0 0x00000000UL /**< Mode DATA0 for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 626 | #define _USB_GRXSTSR_DPID_DATA1 0x00000001UL /**< Mode DATA1 for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 627 | #define _USB_GRXSTSR_DPID_DATA2 0x00000002UL /**< Mode DATA2 for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 628 | #define _USB_GRXSTSR_DPID_MDATA 0x00000003UL /**< Mode MDATA for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 629 | #define USB_GRXSTSR_DPID_DEFAULT (_USB_GRXSTSR_DPID_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 630 | #define USB_GRXSTSR_DPID_DATA0 (_USB_GRXSTSR_DPID_DATA0 << 15) /**< Shifted mode DATA0 for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 631 | #define USB_GRXSTSR_DPID_DATA1 (_USB_GRXSTSR_DPID_DATA1 << 15) /**< Shifted mode DATA1 for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 632 | #define USB_GRXSTSR_DPID_DATA2 (_USB_GRXSTSR_DPID_DATA2 << 15) /**< Shifted mode DATA2 for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 633 | #define USB_GRXSTSR_DPID_MDATA (_USB_GRXSTSR_DPID_MDATA << 15) /**< Shifted mode MDATA for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 634 | #define _USB_GRXSTSR_PKTSTS_SHIFT 17 /**< Shift value for USB_PKTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 635 | #define _USB_GRXSTSR_PKTSTS_MASK 0x1E0000UL /**< Bit mask for USB_PKTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 636 | #define _USB_GRXSTSR_PKTSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 637 | #define _USB_GRXSTSR_PKTSTS_GOUTNAK 0x00000001UL /**< Mode GOUTNAK for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 638 | #define _USB_GRXSTSR_PKTSTS_PKTRCV 0x00000002UL /**< Mode PKTRCV for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 639 | #define _USB_GRXSTSR_PKTSTS_XFERCOMPL 0x00000003UL /**< Mode XFERCOMPL for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 640 | #define _USB_GRXSTSR_PKTSTS_SETUPCOMPL 0x00000004UL /**< Mode SETUPCOMPL for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 641 | #define _USB_GRXSTSR_PKTSTS_TGLERR 0x00000005UL /**< Mode TGLERR for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 642 | #define _USB_GRXSTSR_PKTSTS_SETUPRCV 0x00000006UL /**< Mode SETUPRCV for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 643 | #define _USB_GRXSTSR_PKTSTS_CHLT 0x00000007UL /**< Mode CHLT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 644 | #define USB_GRXSTSR_PKTSTS_DEFAULT (_USB_GRXSTSR_PKTSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 645 | #define USB_GRXSTSR_PKTSTS_GOUTNAK (_USB_GRXSTSR_PKTSTS_GOUTNAK << 17) /**< Shifted mode GOUTNAK for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 646 | #define USB_GRXSTSR_PKTSTS_PKTRCV (_USB_GRXSTSR_PKTSTS_PKTRCV << 17) /**< Shifted mode PKTRCV for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 647 | #define USB_GRXSTSR_PKTSTS_XFERCOMPL (_USB_GRXSTSR_PKTSTS_XFERCOMPL << 17) /**< Shifted mode XFERCOMPL for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 648 | #define USB_GRXSTSR_PKTSTS_SETUPCOMPL (_USB_GRXSTSR_PKTSTS_SETUPCOMPL << 17) /**< Shifted mode SETUPCOMPL for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 649 | #define USB_GRXSTSR_PKTSTS_TGLERR (_USB_GRXSTSR_PKTSTS_TGLERR << 17) /**< Shifted mode TGLERR for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 650 | #define USB_GRXSTSR_PKTSTS_SETUPRCV (_USB_GRXSTSR_PKTSTS_SETUPRCV << 17) /**< Shifted mode SETUPRCV for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 651 | #define USB_GRXSTSR_PKTSTS_CHLT (_USB_GRXSTSR_PKTSTS_CHLT << 17) /**< Shifted mode CHLT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 652 | #define _USB_GRXSTSR_FN_SHIFT 21 /**< Shift value for USB_FN */ |
| AnnaBridge | 171:3a7713b1edbc | 653 | #define _USB_GRXSTSR_FN_MASK 0x1E00000UL /**< Bit mask for USB_FN */ |
| AnnaBridge | 171:3a7713b1edbc | 654 | #define _USB_GRXSTSR_FN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 655 | #define USB_GRXSTSR_FN_DEFAULT (_USB_GRXSTSR_FN_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GRXSTSR */ |
| AnnaBridge | 171:3a7713b1edbc | 656 | |
| AnnaBridge | 171:3a7713b1edbc | 657 | /* Bit fields for USB GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 658 | #define _USB_GRXSTSP_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 659 | #define _USB_GRXSTSP_MASK 0x01FFFFFFUL /**< Mask for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 660 | #define _USB_GRXSTSP_CHEPNUM_SHIFT 0 /**< Shift value for USB_CHEPNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 661 | #define _USB_GRXSTSP_CHEPNUM_MASK 0xFUL /**< Bit mask for USB_CHEPNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 662 | #define _USB_GRXSTSP_CHEPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 663 | #define USB_GRXSTSP_CHEPNUM_DEFAULT (_USB_GRXSTSP_CHEPNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 664 | #define _USB_GRXSTSP_BCNT_SHIFT 4 /**< Shift value for USB_BCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 665 | #define _USB_GRXSTSP_BCNT_MASK 0x7FF0UL /**< Bit mask for USB_BCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 666 | #define _USB_GRXSTSP_BCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 667 | #define USB_GRXSTSP_BCNT_DEFAULT (_USB_GRXSTSP_BCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 668 | #define _USB_GRXSTSP_DPID_SHIFT 15 /**< Shift value for USB_DPID */ |
| AnnaBridge | 171:3a7713b1edbc | 669 | #define _USB_GRXSTSP_DPID_MASK 0x18000UL /**< Bit mask for USB_DPID */ |
| AnnaBridge | 171:3a7713b1edbc | 670 | #define _USB_GRXSTSP_DPID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 671 | #define _USB_GRXSTSP_DPID_DATA0 0x00000000UL /**< Mode DATA0 for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 672 | #define _USB_GRXSTSP_DPID_DATA1 0x00000001UL /**< Mode DATA1 for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 673 | #define _USB_GRXSTSP_DPID_DATA2 0x00000002UL /**< Mode DATA2 for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 674 | #define _USB_GRXSTSP_DPID_MDATA 0x00000003UL /**< Mode MDATA for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 675 | #define USB_GRXSTSP_DPID_DEFAULT (_USB_GRXSTSP_DPID_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 676 | #define USB_GRXSTSP_DPID_DATA0 (_USB_GRXSTSP_DPID_DATA0 << 15) /**< Shifted mode DATA0 for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 677 | #define USB_GRXSTSP_DPID_DATA1 (_USB_GRXSTSP_DPID_DATA1 << 15) /**< Shifted mode DATA1 for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 678 | #define USB_GRXSTSP_DPID_DATA2 (_USB_GRXSTSP_DPID_DATA2 << 15) /**< Shifted mode DATA2 for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 679 | #define USB_GRXSTSP_DPID_MDATA (_USB_GRXSTSP_DPID_MDATA << 15) /**< Shifted mode MDATA for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 680 | #define _USB_GRXSTSP_PKTSTS_SHIFT 17 /**< Shift value for USB_PKTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 681 | #define _USB_GRXSTSP_PKTSTS_MASK 0x1E0000UL /**< Bit mask for USB_PKTSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 682 | #define _USB_GRXSTSP_PKTSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 683 | #define _USB_GRXSTSP_PKTSTS_GOUTNAK 0x00000001UL /**< Mode GOUTNAK for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 684 | #define _USB_GRXSTSP_PKTSTS_PKTRCV 0x00000002UL /**< Mode PKTRCV for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 685 | #define _USB_GRXSTSP_PKTSTS_XFERCOMPL 0x00000003UL /**< Mode XFERCOMPL for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 686 | #define _USB_GRXSTSP_PKTSTS_SETUPCOMPL 0x00000004UL /**< Mode SETUPCOMPL for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 687 | #define _USB_GRXSTSP_PKTSTS_TGLERR 0x00000005UL /**< Mode TGLERR for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 688 | #define _USB_GRXSTSP_PKTSTS_SETUPRCV 0x00000006UL /**< Mode SETUPRCV for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 689 | #define _USB_GRXSTSP_PKTSTS_CHLT 0x00000007UL /**< Mode CHLT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 690 | #define USB_GRXSTSP_PKTSTS_DEFAULT (_USB_GRXSTSP_PKTSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 691 | #define USB_GRXSTSP_PKTSTS_GOUTNAK (_USB_GRXSTSP_PKTSTS_GOUTNAK << 17) /**< Shifted mode GOUTNAK for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 692 | #define USB_GRXSTSP_PKTSTS_PKTRCV (_USB_GRXSTSP_PKTSTS_PKTRCV << 17) /**< Shifted mode PKTRCV for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 693 | #define USB_GRXSTSP_PKTSTS_XFERCOMPL (_USB_GRXSTSP_PKTSTS_XFERCOMPL << 17) /**< Shifted mode XFERCOMPL for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 694 | #define USB_GRXSTSP_PKTSTS_SETUPCOMPL (_USB_GRXSTSP_PKTSTS_SETUPCOMPL << 17) /**< Shifted mode SETUPCOMPL for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 695 | #define USB_GRXSTSP_PKTSTS_TGLERR (_USB_GRXSTSP_PKTSTS_TGLERR << 17) /**< Shifted mode TGLERR for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 696 | #define USB_GRXSTSP_PKTSTS_SETUPRCV (_USB_GRXSTSP_PKTSTS_SETUPRCV << 17) /**< Shifted mode SETUPRCV for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 697 | #define USB_GRXSTSP_PKTSTS_CHLT (_USB_GRXSTSP_PKTSTS_CHLT << 17) /**< Shifted mode CHLT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 698 | #define _USB_GRXSTSP_FN_SHIFT 21 /**< Shift value for USB_FN */ |
| AnnaBridge | 171:3a7713b1edbc | 699 | #define _USB_GRXSTSP_FN_MASK 0x1E00000UL /**< Bit mask for USB_FN */ |
| AnnaBridge | 171:3a7713b1edbc | 700 | #define _USB_GRXSTSP_FN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 701 | #define USB_GRXSTSP_FN_DEFAULT (_USB_GRXSTSP_FN_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GRXSTSP */ |
| AnnaBridge | 171:3a7713b1edbc | 702 | |
| AnnaBridge | 171:3a7713b1edbc | 703 | /* Bit fields for USB GRXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 704 | #define _USB_GRXFSIZ_RESETVALUE 0x00000200UL /**< Default value for USB_GRXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 705 | #define _USB_GRXFSIZ_MASK 0x000003FFUL /**< Mask for USB_GRXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 706 | #define _USB_GRXFSIZ_RXFDEP_SHIFT 0 /**< Shift value for USB_RXFDEP */ |
| AnnaBridge | 171:3a7713b1edbc | 707 | #define _USB_GRXFSIZ_RXFDEP_MASK 0x3FFUL /**< Bit mask for USB_RXFDEP */ |
| AnnaBridge | 171:3a7713b1edbc | 708 | #define _USB_GRXFSIZ_RXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GRXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 709 | #define USB_GRXFSIZ_RXFDEP_DEFAULT (_USB_GRXFSIZ_RXFDEP_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 710 | |
| AnnaBridge | 171:3a7713b1edbc | 711 | /* Bit fields for USB GNPTXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 712 | #define _USB_GNPTXFSIZ_RESETVALUE 0x02000200UL /**< Default value for USB_GNPTXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 713 | #define _USB_GNPTXFSIZ_MASK 0xFFFF03FFUL /**< Mask for USB_GNPTXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 714 | #define _USB_GNPTXFSIZ_NPTXFSTADDR_SHIFT 0 /**< Shift value for USB_NPTXFSTADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 715 | #define _USB_GNPTXFSIZ_NPTXFSTADDR_MASK 0x3FFUL /**< Bit mask for USB_NPTXFSTADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 716 | #define _USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 717 | #define USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT (_USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GNPTXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 718 | #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_SHIFT 16 /**< Shift value for USB_NPTXFINEPTXF0DEP */ |
| AnnaBridge | 171:3a7713b1edbc | 719 | #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_MASK 0xFFFF0000UL /**< Bit mask for USB_NPTXFINEPTXF0DEP */ |
| AnnaBridge | 171:3a7713b1edbc | 720 | #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 721 | #define USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT (_USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GNPTXFSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 722 | |
| AnnaBridge | 171:3a7713b1edbc | 723 | /* Bit fields for USB GDFIFOCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 724 | #define _USB_GDFIFOCFG_RESETVALUE 0x05F80600UL /**< Default value for USB_GDFIFOCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 725 | #define _USB_GDFIFOCFG_MASK 0xFFFFFFFFUL /**< Mask for USB_GDFIFOCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 726 | #define _USB_GDFIFOCFG_GDFIFOCFG_SHIFT 0 /**< Shift value for USB_GDFIFOCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 727 | #define _USB_GDFIFOCFG_GDFIFOCFG_MASK 0xFFFFUL /**< Bit mask for USB_GDFIFOCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 728 | #define _USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x00000600UL /**< Mode DEFAULT for USB_GDFIFOCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 729 | #define USB_GDFIFOCFG_GDFIFOCFG_DEFAULT (_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GDFIFOCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 730 | #define _USB_GDFIFOCFG_EPINFOBASEADDR_SHIFT 16 /**< Shift value for USB_EPINFOBASEADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 731 | #define _USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xFFFF0000UL /**< Bit mask for USB_EPINFOBASEADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 732 | #define _USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x000005F8UL /**< Mode DEFAULT for USB_GDFIFOCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 733 | #define USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT (_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GDFIFOCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 734 | |
| AnnaBridge | 171:3a7713b1edbc | 735 | /* Bit fields for USB DIEPTXF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 736 | #define _USB_DIEPTXF1_RESETVALUE 0x02000400UL /**< Default value for USB_DIEPTXF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 737 | #define _USB_DIEPTXF1_MASK 0x03FF07FFUL /**< Mask for USB_DIEPTXF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 738 | #define _USB_DIEPTXF1_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 739 | #define _USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_INEPNTXFSTADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 740 | #define _USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x00000400UL /**< Mode DEFAULT for USB_DIEPTXF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 741 | #define USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 742 | #define _USB_DIEPTXF1_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ |
| AnnaBridge | 171:3a7713b1edbc | 743 | #define _USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ |
| AnnaBridge | 171:3a7713b1edbc | 744 | #define _USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 745 | #define USB_DIEPTXF1_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF1 */ |
| AnnaBridge | 171:3a7713b1edbc | 746 | |
| AnnaBridge | 171:3a7713b1edbc | 747 | /* Bit fields for USB DIEPTXF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 748 | #define _USB_DIEPTXF2_RESETVALUE 0x02000600UL /**< Default value for USB_DIEPTXF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 749 | #define _USB_DIEPTXF2_MASK 0x03FF07FFUL /**< Mask for USB_DIEPTXF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 750 | #define _USB_DIEPTXF2_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 751 | #define _USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_INEPNTXFSTADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 752 | #define _USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x00000600UL /**< Mode DEFAULT for USB_DIEPTXF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 753 | #define USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 754 | #define _USB_DIEPTXF2_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ |
| AnnaBridge | 171:3a7713b1edbc | 755 | #define _USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ |
| AnnaBridge | 171:3a7713b1edbc | 756 | #define _USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 757 | #define USB_DIEPTXF2_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF2 */ |
| AnnaBridge | 171:3a7713b1edbc | 758 | |
| AnnaBridge | 171:3a7713b1edbc | 759 | /* Bit fields for USB DIEPTXF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 760 | #define _USB_DIEPTXF3_RESETVALUE 0x02000800UL /**< Default value for USB_DIEPTXF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 761 | #define _USB_DIEPTXF3_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 762 | #define _USB_DIEPTXF3_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 763 | #define _USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 764 | #define _USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x00000800UL /**< Mode DEFAULT for USB_DIEPTXF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 765 | #define USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 766 | #define _USB_DIEPTXF3_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */ |
| AnnaBridge | 171:3a7713b1edbc | 767 | #define _USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */ |
| AnnaBridge | 171:3a7713b1edbc | 768 | #define _USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 769 | #define USB_DIEPTXF3_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF3 */ |
| AnnaBridge | 171:3a7713b1edbc | 770 | |
| AnnaBridge | 171:3a7713b1edbc | 771 | /* Bit fields for USB DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 772 | #define _USB_DCFG_RESETVALUE 0x08000000UL /**< Default value for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 773 | #define _USB_DCFG_MASK 0xFC009FFFUL /**< Mask for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 774 | #define _USB_DCFG_DEVSPD_SHIFT 0 /**< Shift value for USB_DEVSPD */ |
| AnnaBridge | 171:3a7713b1edbc | 775 | #define _USB_DCFG_DEVSPD_MASK 0x3UL /**< Bit mask for USB_DEVSPD */ |
| AnnaBridge | 171:3a7713b1edbc | 776 | #define _USB_DCFG_DEVSPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 777 | #define _USB_DCFG_DEVSPD_LS 0x00000002UL /**< Mode LS for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 778 | #define _USB_DCFG_DEVSPD_FS 0x00000003UL /**< Mode FS for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 779 | #define USB_DCFG_DEVSPD_DEFAULT (_USB_DCFG_DEVSPD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 780 | #define USB_DCFG_DEVSPD_LS (_USB_DCFG_DEVSPD_LS << 0) /**< Shifted mode LS for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 781 | #define USB_DCFG_DEVSPD_FS (_USB_DCFG_DEVSPD_FS << 0) /**< Shifted mode FS for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 782 | #define USB_DCFG_NZSTSOUTHSHK (0x1UL << 2) /**< Non-Zero-Length Status OUT Handshake */ |
| AnnaBridge | 171:3a7713b1edbc | 783 | #define _USB_DCFG_NZSTSOUTHSHK_SHIFT 2 /**< Shift value for USB_NZSTSOUTHSHK */ |
| AnnaBridge | 171:3a7713b1edbc | 784 | #define _USB_DCFG_NZSTSOUTHSHK_MASK 0x4UL /**< Bit mask for USB_NZSTSOUTHSHK */ |
| AnnaBridge | 171:3a7713b1edbc | 785 | #define _USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 786 | #define USB_DCFG_NZSTSOUTHSHK_DEFAULT (_USB_DCFG_NZSTSOUTHSHK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 787 | #define USB_DCFG_ENA32KHZSUSP (0x1UL << 3) /**< Enable 32 KHz Suspend mode */ |
| AnnaBridge | 171:3a7713b1edbc | 788 | #define _USB_DCFG_ENA32KHZSUSP_SHIFT 3 /**< Shift value for USB_ENA32KHZSUSP */ |
| AnnaBridge | 171:3a7713b1edbc | 789 | #define _USB_DCFG_ENA32KHZSUSP_MASK 0x8UL /**< Bit mask for USB_ENA32KHZSUSP */ |
| AnnaBridge | 171:3a7713b1edbc | 790 | #define _USB_DCFG_ENA32KHZSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 791 | #define USB_DCFG_ENA32KHZSUSP_DEFAULT (_USB_DCFG_ENA32KHZSUSP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 792 | #define _USB_DCFG_DEVADDR_SHIFT 4 /**< Shift value for USB_DEVADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 793 | #define _USB_DCFG_DEVADDR_MASK 0x7F0UL /**< Bit mask for USB_DEVADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 794 | #define _USB_DCFG_DEVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 795 | #define USB_DCFG_DEVADDR_DEFAULT (_USB_DCFG_DEVADDR_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 796 | #define _USB_DCFG_PERFRINT_SHIFT 11 /**< Shift value for USB_PERFRINT */ |
| AnnaBridge | 171:3a7713b1edbc | 797 | #define _USB_DCFG_PERFRINT_MASK 0x1800UL /**< Bit mask for USB_PERFRINT */ |
| AnnaBridge | 171:3a7713b1edbc | 798 | #define _USB_DCFG_PERFRINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 799 | #define _USB_DCFG_PERFRINT_80PCNT 0x00000000UL /**< Mode 80PCNT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 800 | #define _USB_DCFG_PERFRINT_85PCNT 0x00000001UL /**< Mode 85PCNT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 801 | #define _USB_DCFG_PERFRINT_90PCNT 0x00000002UL /**< Mode 90PCNT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 802 | #define _USB_DCFG_PERFRINT_95PCNT 0x00000003UL /**< Mode 95PCNT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 803 | #define USB_DCFG_PERFRINT_DEFAULT (_USB_DCFG_PERFRINT_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 804 | #define USB_DCFG_PERFRINT_80PCNT (_USB_DCFG_PERFRINT_80PCNT << 11) /**< Shifted mode 80PCNT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 805 | #define USB_DCFG_PERFRINT_85PCNT (_USB_DCFG_PERFRINT_85PCNT << 11) /**< Shifted mode 85PCNT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 806 | #define USB_DCFG_PERFRINT_90PCNT (_USB_DCFG_PERFRINT_90PCNT << 11) /**< Shifted mode 90PCNT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 807 | #define USB_DCFG_PERFRINT_95PCNT (_USB_DCFG_PERFRINT_95PCNT << 11) /**< Shifted mode 95PCNT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 808 | #define USB_DCFG_ERRATICINTMSK (0x1UL << 15) /**< */ |
| AnnaBridge | 171:3a7713b1edbc | 809 | #define _USB_DCFG_ERRATICINTMSK_SHIFT 15 /**< Shift value for USB_ERRATICINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 810 | #define _USB_DCFG_ERRATICINTMSK_MASK 0x8000UL /**< Bit mask for USB_ERRATICINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 811 | #define _USB_DCFG_ERRATICINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 812 | #define USB_DCFG_ERRATICINTMSK_DEFAULT (_USB_DCFG_ERRATICINTMSK_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 813 | #define _USB_DCFG_RESVALID_SHIFT 26 /**< Shift value for USB_RESVALID */ |
| AnnaBridge | 171:3a7713b1edbc | 814 | #define _USB_DCFG_RESVALID_MASK 0xFC000000UL /**< Bit mask for USB_RESVALID */ |
| AnnaBridge | 171:3a7713b1edbc | 815 | #define _USB_DCFG_RESVALID_DEFAULT 0x00000002UL /**< Mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 816 | #define USB_DCFG_RESVALID_DEFAULT (_USB_DCFG_RESVALID_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 817 | |
| AnnaBridge | 171:3a7713b1edbc | 818 | /* Bit fields for USB DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 819 | #define _USB_DCTL_RESETVALUE 0x00000002UL /**< Default value for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 820 | #define _USB_DCTL_MASK 0x00018FFFUL /**< Mask for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 821 | #define USB_DCTL_RMTWKUPSIG (0x1UL << 0) /**< Remote Wakeup Signaling */ |
| AnnaBridge | 171:3a7713b1edbc | 822 | #define _USB_DCTL_RMTWKUPSIG_SHIFT 0 /**< Shift value for USB_RMTWKUPSIG */ |
| AnnaBridge | 171:3a7713b1edbc | 823 | #define _USB_DCTL_RMTWKUPSIG_MASK 0x1UL /**< Bit mask for USB_RMTWKUPSIG */ |
| AnnaBridge | 171:3a7713b1edbc | 824 | #define _USB_DCTL_RMTWKUPSIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 825 | #define USB_DCTL_RMTWKUPSIG_DEFAULT (_USB_DCTL_RMTWKUPSIG_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 826 | #define USB_DCTL_SFTDISCON (0x1UL << 1) /**< Soft Disconnect */ |
| AnnaBridge | 171:3a7713b1edbc | 827 | #define _USB_DCTL_SFTDISCON_SHIFT 1 /**< Shift value for USB_SFTDISCON */ |
| AnnaBridge | 171:3a7713b1edbc | 828 | #define _USB_DCTL_SFTDISCON_MASK 0x2UL /**< Bit mask for USB_SFTDISCON */ |
| AnnaBridge | 171:3a7713b1edbc | 829 | #define _USB_DCTL_SFTDISCON_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 830 | #define USB_DCTL_SFTDISCON_DEFAULT (_USB_DCTL_SFTDISCON_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 831 | #define USB_DCTL_GNPINNAKSTS (0x1UL << 2) /**< Global Non-periodic IN NAK Status */ |
| AnnaBridge | 171:3a7713b1edbc | 832 | #define _USB_DCTL_GNPINNAKSTS_SHIFT 2 /**< Shift value for USB_GNPINNAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 833 | #define _USB_DCTL_GNPINNAKSTS_MASK 0x4UL /**< Bit mask for USB_GNPINNAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 834 | #define _USB_DCTL_GNPINNAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 835 | #define USB_DCTL_GNPINNAKSTS_DEFAULT (_USB_DCTL_GNPINNAKSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 836 | #define USB_DCTL_GOUTNAKSTS (0x1UL << 3) /**< Global OUT NAK Status */ |
| AnnaBridge | 171:3a7713b1edbc | 837 | #define _USB_DCTL_GOUTNAKSTS_SHIFT 3 /**< Shift value for USB_GOUTNAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 838 | #define _USB_DCTL_GOUTNAKSTS_MASK 0x8UL /**< Bit mask for USB_GOUTNAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 839 | #define _USB_DCTL_GOUTNAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 840 | #define USB_DCTL_GOUTNAKSTS_DEFAULT (_USB_DCTL_GOUTNAKSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 841 | #define _USB_DCTL_TSTCTL_SHIFT 4 /**< Shift value for USB_TSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 842 | #define _USB_DCTL_TSTCTL_MASK 0x70UL /**< Bit mask for USB_TSTCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 843 | #define _USB_DCTL_TSTCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 844 | #define _USB_DCTL_TSTCTL_DISABLE 0x00000000UL /**< Mode DISABLE for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 845 | #define _USB_DCTL_TSTCTL_J 0x00000001UL /**< Mode J for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 846 | #define _USB_DCTL_TSTCTL_K 0x00000002UL /**< Mode K for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 847 | #define _USB_DCTL_TSTCTL_SE0NAK 0x00000003UL /**< Mode SE0NAK for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 848 | #define _USB_DCTL_TSTCTL_PACKET 0x00000004UL /**< Mode PACKET for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 849 | #define _USB_DCTL_TSTCTL_FORCE 0x00000005UL /**< Mode FORCE for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 850 | #define USB_DCTL_TSTCTL_DEFAULT (_USB_DCTL_TSTCTL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 851 | #define USB_DCTL_TSTCTL_DISABLE (_USB_DCTL_TSTCTL_DISABLE << 4) /**< Shifted mode DISABLE for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 852 | #define USB_DCTL_TSTCTL_J (_USB_DCTL_TSTCTL_J << 4) /**< Shifted mode J for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 853 | #define USB_DCTL_TSTCTL_K (_USB_DCTL_TSTCTL_K << 4) /**< Shifted mode K for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 854 | #define USB_DCTL_TSTCTL_SE0NAK (_USB_DCTL_TSTCTL_SE0NAK << 4) /**< Shifted mode SE0NAK for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 855 | #define USB_DCTL_TSTCTL_PACKET (_USB_DCTL_TSTCTL_PACKET << 4) /**< Shifted mode PACKET for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 856 | #define USB_DCTL_TSTCTL_FORCE (_USB_DCTL_TSTCTL_FORCE << 4) /**< Shifted mode FORCE for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 857 | #define USB_DCTL_SGNPINNAK (0x1UL << 7) /**< Set Global Non-periodic IN NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 858 | #define _USB_DCTL_SGNPINNAK_SHIFT 7 /**< Shift value for USB_SGNPINNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 859 | #define _USB_DCTL_SGNPINNAK_MASK 0x80UL /**< Bit mask for USB_SGNPINNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 860 | #define _USB_DCTL_SGNPINNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 861 | #define USB_DCTL_SGNPINNAK_DEFAULT (_USB_DCTL_SGNPINNAK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 862 | #define USB_DCTL_CGNPINNAK (0x1UL << 8) /**< Clear Global Non-periodic IN NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 863 | #define _USB_DCTL_CGNPINNAK_SHIFT 8 /**< Shift value for USB_CGNPINNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 864 | #define _USB_DCTL_CGNPINNAK_MASK 0x100UL /**< Bit mask for USB_CGNPINNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 865 | #define _USB_DCTL_CGNPINNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 866 | #define USB_DCTL_CGNPINNAK_DEFAULT (_USB_DCTL_CGNPINNAK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 867 | #define USB_DCTL_SGOUTNAK (0x1UL << 9) /**< Set Global OUT NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 868 | #define _USB_DCTL_SGOUTNAK_SHIFT 9 /**< Shift value for USB_SGOUTNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 869 | #define _USB_DCTL_SGOUTNAK_MASK 0x200UL /**< Bit mask for USB_SGOUTNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 870 | #define _USB_DCTL_SGOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 871 | #define USB_DCTL_SGOUTNAK_DEFAULT (_USB_DCTL_SGOUTNAK_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 872 | #define USB_DCTL_CGOUTNAK (0x1UL << 10) /**< Clear Global OUT NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 873 | #define _USB_DCTL_CGOUTNAK_SHIFT 10 /**< Shift value for USB_CGOUTNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 874 | #define _USB_DCTL_CGOUTNAK_MASK 0x400UL /**< Bit mask for USB_CGOUTNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 875 | #define _USB_DCTL_CGOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 876 | #define USB_DCTL_CGOUTNAK_DEFAULT (_USB_DCTL_CGOUTNAK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 877 | #define USB_DCTL_PWRONPRGDONE (0x1UL << 11) /**< Power-On Programming Done */ |
| AnnaBridge | 171:3a7713b1edbc | 878 | #define _USB_DCTL_PWRONPRGDONE_SHIFT 11 /**< Shift value for USB_PWRONPRGDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 879 | #define _USB_DCTL_PWRONPRGDONE_MASK 0x800UL /**< Bit mask for USB_PWRONPRGDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 880 | #define _USB_DCTL_PWRONPRGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 881 | #define USB_DCTL_PWRONPRGDONE_DEFAULT (_USB_DCTL_PWRONPRGDONE_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 882 | #define USB_DCTL_IGNRFRMNUM (0x1UL << 15) /**< Ignore Frame number For Isochronous End points */ |
| AnnaBridge | 171:3a7713b1edbc | 883 | #define _USB_DCTL_IGNRFRMNUM_SHIFT 15 /**< Shift value for USB_IGNRFRMNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 884 | #define _USB_DCTL_IGNRFRMNUM_MASK 0x8000UL /**< Bit mask for USB_IGNRFRMNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 885 | #define _USB_DCTL_IGNRFRMNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 886 | #define USB_DCTL_IGNRFRMNUM_DEFAULT (_USB_DCTL_IGNRFRMNUM_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 887 | #define USB_DCTL_NAKONBBLE (0x1UL << 16) /**< NAK on Babble Error */ |
| AnnaBridge | 171:3a7713b1edbc | 888 | #define _USB_DCTL_NAKONBBLE_SHIFT 16 /**< Shift value for USB_NAKONBBLE */ |
| AnnaBridge | 171:3a7713b1edbc | 889 | #define _USB_DCTL_NAKONBBLE_MASK 0x10000UL /**< Bit mask for USB_NAKONBBLE */ |
| AnnaBridge | 171:3a7713b1edbc | 890 | #define _USB_DCTL_NAKONBBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 891 | #define USB_DCTL_NAKONBBLE_DEFAULT (_USB_DCTL_NAKONBBLE_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 892 | |
| AnnaBridge | 171:3a7713b1edbc | 893 | /* Bit fields for USB DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 894 | #define _USB_DSTS_RESETVALUE 0x00000002UL /**< Default value for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 895 | #define _USB_DSTS_MASK 0x00FFFF0FUL /**< Mask for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 896 | #define USB_DSTS_SUSPSTS (0x1UL << 0) /**< Suspend Status */ |
| AnnaBridge | 171:3a7713b1edbc | 897 | #define _USB_DSTS_SUSPSTS_SHIFT 0 /**< Shift value for USB_SUSPSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 898 | #define _USB_DSTS_SUSPSTS_MASK 0x1UL /**< Bit mask for USB_SUSPSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 899 | #define _USB_DSTS_SUSPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 900 | #define USB_DSTS_SUSPSTS_DEFAULT (_USB_DSTS_SUSPSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 901 | #define _USB_DSTS_ENUMSPD_SHIFT 1 /**< Shift value for USB_ENUMSPD */ |
| AnnaBridge | 171:3a7713b1edbc | 902 | #define _USB_DSTS_ENUMSPD_MASK 0x6UL /**< Bit mask for USB_ENUMSPD */ |
| AnnaBridge | 171:3a7713b1edbc | 903 | #define _USB_DSTS_ENUMSPD_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 904 | #define _USB_DSTS_ENUMSPD_LS 0x00000002UL /**< Mode LS for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 905 | #define _USB_DSTS_ENUMSPD_FS 0x00000003UL /**< Mode FS for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 906 | #define USB_DSTS_ENUMSPD_DEFAULT (_USB_DSTS_ENUMSPD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 907 | #define USB_DSTS_ENUMSPD_LS (_USB_DSTS_ENUMSPD_LS << 1) /**< Shifted mode LS for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 908 | #define USB_DSTS_ENUMSPD_FS (_USB_DSTS_ENUMSPD_FS << 1) /**< Shifted mode FS for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 909 | #define USB_DSTS_ERRTICERR (0x1UL << 3) /**< Erratic Error */ |
| AnnaBridge | 171:3a7713b1edbc | 910 | #define _USB_DSTS_ERRTICERR_SHIFT 3 /**< Shift value for USB_ERRTICERR */ |
| AnnaBridge | 171:3a7713b1edbc | 911 | #define _USB_DSTS_ERRTICERR_MASK 0x8UL /**< Bit mask for USB_ERRTICERR */ |
| AnnaBridge | 171:3a7713b1edbc | 912 | #define _USB_DSTS_ERRTICERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 913 | #define USB_DSTS_ERRTICERR_DEFAULT (_USB_DSTS_ERRTICERR_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 914 | #define _USB_DSTS_SOFFN_SHIFT 8 /**< Shift value for USB_SOFFN */ |
| AnnaBridge | 171:3a7713b1edbc | 915 | #define _USB_DSTS_SOFFN_MASK 0x3FFF00UL /**< Bit mask for USB_SOFFN */ |
| AnnaBridge | 171:3a7713b1edbc | 916 | #define _USB_DSTS_SOFFN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 917 | #define USB_DSTS_SOFFN_DEFAULT (_USB_DSTS_SOFFN_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 918 | #define _USB_DSTS_DEVLNSTS_SHIFT 22 /**< Shift value for USB_DEVLNSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 919 | #define _USB_DSTS_DEVLNSTS_MASK 0xC00000UL /**< Bit mask for USB_DEVLNSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 920 | #define _USB_DSTS_DEVLNSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 921 | #define USB_DSTS_DEVLNSTS_DEFAULT (_USB_DSTS_DEVLNSTS_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 922 | |
| AnnaBridge | 171:3a7713b1edbc | 923 | /* Bit fields for USB DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 924 | #define _USB_DIEPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 925 | #define _USB_DIEPMSK_MASK 0x0000215FUL /**< Mask for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 926 | #define USB_DIEPMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 927 | #define _USB_DIEPMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 928 | #define _USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 929 | #define _USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 930 | #define USB_DIEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 931 | #define USB_DIEPMSK_EPDISBLDMSK (0x1UL << 1) /**< Endpoint Disabled Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 932 | #define _USB_DIEPMSK_EPDISBLDMSK_SHIFT 1 /**< Shift value for USB_EPDISBLDMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 933 | #define _USB_DIEPMSK_EPDISBLDMSK_MASK 0x2UL /**< Bit mask for USB_EPDISBLDMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 934 | #define _USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 935 | #define USB_DIEPMSK_EPDISBLDMSK_DEFAULT (_USB_DIEPMSK_EPDISBLDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 936 | #define USB_DIEPMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 937 | #define _USB_DIEPMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 938 | #define _USB_DIEPMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 939 | #define _USB_DIEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 940 | #define USB_DIEPMSK_AHBERRMSK_DEFAULT (_USB_DIEPMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 941 | #define USB_DIEPMSK_TIMEOUTMSK (0x1UL << 3) /**< Timeout Condition Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 942 | #define _USB_DIEPMSK_TIMEOUTMSK_SHIFT 3 /**< Shift value for USB_TIMEOUTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 943 | #define _USB_DIEPMSK_TIMEOUTMSK_MASK 0x8UL /**< Bit mask for USB_TIMEOUTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 944 | #define _USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 945 | #define USB_DIEPMSK_TIMEOUTMSK_DEFAULT (_USB_DIEPMSK_TIMEOUTMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 946 | #define USB_DIEPMSK_INTKNTXFEMPMSK (0x1UL << 4) /**< IN Token Received When TxFIFO Empty Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 947 | #define _USB_DIEPMSK_INTKNTXFEMPMSK_SHIFT 4 /**< Shift value for USB_INTKNTXFEMPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 948 | #define _USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 949 | #define _USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 950 | #define USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT (_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 951 | #define USB_DIEPMSK_INEPNAKEFFMSK (0x1UL << 6) /**< IN Endpoint NAK Effective Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 952 | #define _USB_DIEPMSK_INEPNAKEFFMSK_SHIFT 6 /**< Shift value for USB_INEPNAKEFFMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 953 | #define _USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFFMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 954 | #define _USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 955 | #define USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT (_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 956 | #define USB_DIEPMSK_TXFIFOUNDRNMSK (0x1UL << 8) /**< Fifo Underrun Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 957 | #define _USB_DIEPMSK_TXFIFOUNDRNMSK_SHIFT 8 /**< Shift value for USB_TXFIFOUNDRNMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 958 | #define _USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100UL /**< Bit mask for USB_TXFIFOUNDRNMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 959 | #define _USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 960 | #define USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT (_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 961 | #define USB_DIEPMSK_NAKMSK (0x1UL << 13) /**< NAK interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 962 | #define _USB_DIEPMSK_NAKMSK_SHIFT 13 /**< Shift value for USB_NAKMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 963 | #define _USB_DIEPMSK_NAKMSK_MASK 0x2000UL /**< Bit mask for USB_NAKMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 964 | #define _USB_DIEPMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 965 | #define USB_DIEPMSK_NAKMSK_DEFAULT (_USB_DIEPMSK_NAKMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 966 | |
| AnnaBridge | 171:3a7713b1edbc | 967 | /* Bit fields for USB DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 968 | #define _USB_DOEPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 969 | #define _USB_DOEPMSK_MASK 0x0000317FUL /**< Mask for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 970 | #define USB_DOEPMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 971 | #define _USB_DOEPMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 972 | #define _USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 973 | #define _USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 974 | #define USB_DOEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 975 | #define USB_DOEPMSK_EPDISBLDMSK (0x1UL << 1) /**< Endpoint Disabled Interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 976 | #define _USB_DOEPMSK_EPDISBLDMSK_SHIFT 1 /**< Shift value for USB_EPDISBLDMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 977 | #define _USB_DOEPMSK_EPDISBLDMSK_MASK 0x2UL /**< Bit mask for USB_EPDISBLDMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 978 | #define _USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 979 | #define USB_DOEPMSK_EPDISBLDMSK_DEFAULT (_USB_DOEPMSK_EPDISBLDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 980 | #define USB_DOEPMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error */ |
| AnnaBridge | 171:3a7713b1edbc | 981 | #define _USB_DOEPMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 982 | #define _USB_DOEPMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 983 | #define _USB_DOEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 984 | #define USB_DOEPMSK_AHBERRMSK_DEFAULT (_USB_DOEPMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 985 | #define USB_DOEPMSK_SETUPMSK (0x1UL << 3) /**< SETUP Phase Done Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 986 | #define _USB_DOEPMSK_SETUPMSK_SHIFT 3 /**< Shift value for USB_SETUPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 987 | #define _USB_DOEPMSK_SETUPMSK_MASK 0x8UL /**< Bit mask for USB_SETUPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 988 | #define _USB_DOEPMSK_SETUPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 989 | #define USB_DOEPMSK_SETUPMSK_DEFAULT (_USB_DOEPMSK_SETUPMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 990 | #define USB_DOEPMSK_OUTTKNEPDISMSK (0x1UL << 4) /**< OUT Token Received when Endpoint Disabled Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 991 | #define _USB_DOEPMSK_OUTTKNEPDISMSK_SHIFT 4 /**< Shift value for USB_OUTTKNEPDISMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 992 | #define _USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDISMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 993 | #define _USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 994 | #define USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT (_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 995 | #define USB_DOEPMSK_STSPHSERCVDMSK (0x1UL << 5) /**< Status Phase Received Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 996 | #define _USB_DOEPMSK_STSPHSERCVDMSK_SHIFT 5 /**< Shift value for USB_STSPHSERCVDMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 997 | #define _USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20UL /**< Bit mask for USB_STSPHSERCVDMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 998 | #define _USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 999 | #define USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT (_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1000 | #define USB_DOEPMSK_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 1001 | #define _USB_DOEPMSK_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1002 | #define _USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1003 | #define _USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1004 | #define USB_DOEPMSK_BACK2BACKSETUP_DEFAULT (_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1005 | #define USB_DOEPMSK_OUTPKTERRMSK (0x1UL << 8) /**< OUT Packet Error Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 1006 | #define _USB_DOEPMSK_OUTPKTERRMSK_SHIFT 8 /**< Shift value for USB_OUTPKTERRMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1007 | #define _USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100UL /**< Bit mask for USB_OUTPKTERRMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1008 | #define _USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1009 | #define USB_DOEPMSK_OUTPKTERRMSK_DEFAULT (_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1010 | #define USB_DOEPMSK_BBLEERRMSK (0x1UL << 12) /**< Babble Error interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 1011 | #define _USB_DOEPMSK_BBLEERRMSK_SHIFT 12 /**< Shift value for USB_BBLEERRMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1012 | #define _USB_DOEPMSK_BBLEERRMSK_MASK 0x1000UL /**< Bit mask for USB_BBLEERRMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1013 | #define _USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1014 | #define USB_DOEPMSK_BBLEERRMSK_DEFAULT (_USB_DOEPMSK_BBLEERRMSK_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1015 | #define USB_DOEPMSK_NAKMSK (0x1UL << 13) /**< NAK interrupt Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 1016 | #define _USB_DOEPMSK_NAKMSK_SHIFT 13 /**< Shift value for USB_NAKMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1017 | #define _USB_DOEPMSK_NAKMSK_MASK 0x2000UL /**< Bit mask for USB_NAKMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1018 | #define _USB_DOEPMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1019 | #define USB_DOEPMSK_NAKMSK_DEFAULT (_USB_DOEPMSK_NAKMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1020 | |
| AnnaBridge | 171:3a7713b1edbc | 1021 | /* Bit fields for USB DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1022 | #define _USB_DAINT_RESETVALUE 0x00000000UL /**< Default value for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1023 | #define _USB_DAINT_MASK 0x000F000FUL /**< Mask for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1024 | #define USB_DAINT_INEPINT0 (0x1UL << 0) /**< IN Endpoint 0 Interrupt Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1025 | #define _USB_DAINT_INEPINT0_SHIFT 0 /**< Shift value for USB_INEPINT0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1026 | #define _USB_DAINT_INEPINT0_MASK 0x1UL /**< Bit mask for USB_INEPINT0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1027 | #define _USB_DAINT_INEPINT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1028 | #define USB_DAINT_INEPINT0_DEFAULT (_USB_DAINT_INEPINT0_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1029 | #define USB_DAINT_INEPINT1 (0x1UL << 1) /**< IN Endpoint 1 Interrupt Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1030 | #define _USB_DAINT_INEPINT1_SHIFT 1 /**< Shift value for USB_INEPINT1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1031 | #define _USB_DAINT_INEPINT1_MASK 0x2UL /**< Bit mask for USB_INEPINT1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1032 | #define _USB_DAINT_INEPINT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1033 | #define USB_DAINT_INEPINT1_DEFAULT (_USB_DAINT_INEPINT1_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1034 | #define USB_DAINT_INEPINT2 (0x1UL << 2) /**< IN Endpoint 2 Interrupt Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1035 | #define _USB_DAINT_INEPINT2_SHIFT 2 /**< Shift value for USB_INEPINT2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1036 | #define _USB_DAINT_INEPINT2_MASK 0x4UL /**< Bit mask for USB_INEPINT2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1037 | #define _USB_DAINT_INEPINT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1038 | #define USB_DAINT_INEPINT2_DEFAULT (_USB_DAINT_INEPINT2_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1039 | #define USB_DAINT_INEPINT3 (0x1UL << 3) /**< IN Endpoint 3 Interrupt Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1040 | #define _USB_DAINT_INEPINT3_SHIFT 3 /**< Shift value for USB_INEPINT3 */ |
| AnnaBridge | 171:3a7713b1edbc | 1041 | #define _USB_DAINT_INEPINT3_MASK 0x8UL /**< Bit mask for USB_INEPINT3 */ |
| AnnaBridge | 171:3a7713b1edbc | 1042 | #define _USB_DAINT_INEPINT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1043 | #define USB_DAINT_INEPINT3_DEFAULT (_USB_DAINT_INEPINT3_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1044 | #define USB_DAINT_OUTEPINT0 (0x1UL << 16) /**< OUT Endpoint 0 Interrupt Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1045 | #define _USB_DAINT_OUTEPINT0_SHIFT 16 /**< Shift value for USB_OUTEPINT0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1046 | #define _USB_DAINT_OUTEPINT0_MASK 0x10000UL /**< Bit mask for USB_OUTEPINT0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1047 | #define _USB_DAINT_OUTEPINT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1048 | #define USB_DAINT_OUTEPINT0_DEFAULT (_USB_DAINT_OUTEPINT0_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1049 | #define USB_DAINT_OUTEPINT1 (0x1UL << 17) /**< OUT Endpoint 1 Interrupt Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1050 | #define _USB_DAINT_OUTEPINT1_SHIFT 17 /**< Shift value for USB_OUTEPINT1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1051 | #define _USB_DAINT_OUTEPINT1_MASK 0x20000UL /**< Bit mask for USB_OUTEPINT1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1052 | #define _USB_DAINT_OUTEPINT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1053 | #define USB_DAINT_OUTEPINT1_DEFAULT (_USB_DAINT_OUTEPINT1_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1054 | #define USB_DAINT_OUTEPINT2 (0x1UL << 18) /**< OUT Endpoint 2 Interrupt Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1055 | #define _USB_DAINT_OUTEPINT2_SHIFT 18 /**< Shift value for USB_OUTEPINT2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1056 | #define _USB_DAINT_OUTEPINT2_MASK 0x40000UL /**< Bit mask for USB_OUTEPINT2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1057 | #define _USB_DAINT_OUTEPINT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1058 | #define USB_DAINT_OUTEPINT2_DEFAULT (_USB_DAINT_OUTEPINT2_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1059 | #define USB_DAINT_OUTEPINT3 (0x1UL << 19) /**< OUT Endpoint 3 Interrupt Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1060 | #define _USB_DAINT_OUTEPINT3_SHIFT 19 /**< Shift value for USB_OUTEPINT3 */ |
| AnnaBridge | 171:3a7713b1edbc | 1061 | #define _USB_DAINT_OUTEPINT3_MASK 0x80000UL /**< Bit mask for USB_OUTEPINT3 */ |
| AnnaBridge | 171:3a7713b1edbc | 1062 | #define _USB_DAINT_OUTEPINT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1063 | #define USB_DAINT_OUTEPINT3_DEFAULT (_USB_DAINT_OUTEPINT3_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DAINT */ |
| AnnaBridge | 171:3a7713b1edbc | 1064 | |
| AnnaBridge | 171:3a7713b1edbc | 1065 | /* Bit fields for USB DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1066 | #define _USB_DAINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1067 | #define _USB_DAINTMSK_MASK 0x000F000FUL /**< Mask for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1068 | #define USB_DAINTMSK_INEPMSK0 (0x1UL << 0) /**< IN Endpoint 0 Interrupt mask Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1069 | #define _USB_DAINTMSK_INEPMSK0_SHIFT 0 /**< Shift value for USB_INEPMSK0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1070 | #define _USB_DAINTMSK_INEPMSK0_MASK 0x1UL /**< Bit mask for USB_INEPMSK0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1071 | #define _USB_DAINTMSK_INEPMSK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1072 | #define USB_DAINTMSK_INEPMSK0_DEFAULT (_USB_DAINTMSK_INEPMSK0_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1073 | #define USB_DAINTMSK_INEPMSK1 (0x1UL << 1) /**< IN Endpoint 1 Interrupt mask Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1074 | #define _USB_DAINTMSK_INEPMSK1_SHIFT 1 /**< Shift value for USB_INEPMSK1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1075 | #define _USB_DAINTMSK_INEPMSK1_MASK 0x2UL /**< Bit mask for USB_INEPMSK1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1076 | #define _USB_DAINTMSK_INEPMSK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1077 | #define USB_DAINTMSK_INEPMSK1_DEFAULT (_USB_DAINTMSK_INEPMSK1_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1078 | #define USB_DAINTMSK_INEPMSK2 (0x1UL << 2) /**< IN Endpoint 2 Interrupt mask Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1079 | #define _USB_DAINTMSK_INEPMSK2_SHIFT 2 /**< Shift value for USB_INEPMSK2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1080 | #define _USB_DAINTMSK_INEPMSK2_MASK 0x4UL /**< Bit mask for USB_INEPMSK2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1081 | #define _USB_DAINTMSK_INEPMSK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1082 | #define USB_DAINTMSK_INEPMSK2_DEFAULT (_USB_DAINTMSK_INEPMSK2_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1083 | #define USB_DAINTMSK_INEPMSK3 (0x1UL << 3) /**< IN Endpoint 3 Interrupt mask Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1084 | #define _USB_DAINTMSK_INEPMSK3_SHIFT 3 /**< Shift value for USB_INEPMSK3 */ |
| AnnaBridge | 171:3a7713b1edbc | 1085 | #define _USB_DAINTMSK_INEPMSK3_MASK 0x8UL /**< Bit mask for USB_INEPMSK3 */ |
| AnnaBridge | 171:3a7713b1edbc | 1086 | #define _USB_DAINTMSK_INEPMSK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1087 | #define USB_DAINTMSK_INEPMSK3_DEFAULT (_USB_DAINTMSK_INEPMSK3_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1088 | #define USB_DAINTMSK_OUTEPMSK0 (0x1UL << 16) /**< OUT Endpoint 0 Interrupt mask Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1089 | #define _USB_DAINTMSK_OUTEPMSK0_SHIFT 16 /**< Shift value for USB_OUTEPMSK0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1090 | #define _USB_DAINTMSK_OUTEPMSK0_MASK 0x10000UL /**< Bit mask for USB_OUTEPMSK0 */ |
| AnnaBridge | 171:3a7713b1edbc | 1091 | #define _USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1092 | #define USB_DAINTMSK_OUTEPMSK0_DEFAULT (_USB_DAINTMSK_OUTEPMSK0_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1093 | #define USB_DAINTMSK_OUTEPMSK1 (0x1UL << 17) /**< OUT Endpoint 1 Interrupt mask Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1094 | #define _USB_DAINTMSK_OUTEPMSK1_SHIFT 17 /**< Shift value for USB_OUTEPMSK1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1095 | #define _USB_DAINTMSK_OUTEPMSK1_MASK 0x20000UL /**< Bit mask for USB_OUTEPMSK1 */ |
| AnnaBridge | 171:3a7713b1edbc | 1096 | #define _USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1097 | #define USB_DAINTMSK_OUTEPMSK1_DEFAULT (_USB_DAINTMSK_OUTEPMSK1_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1098 | #define USB_DAINTMSK_OUTEPMSK2 (0x1UL << 18) /**< OUT Endpoint 2 Interrupt mask Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1099 | #define _USB_DAINTMSK_OUTEPMSK2_SHIFT 18 /**< Shift value for USB_OUTEPMSK2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1100 | #define _USB_DAINTMSK_OUTEPMSK2_MASK 0x40000UL /**< Bit mask for USB_OUTEPMSK2 */ |
| AnnaBridge | 171:3a7713b1edbc | 1101 | #define _USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1102 | #define USB_DAINTMSK_OUTEPMSK2_DEFAULT (_USB_DAINTMSK_OUTEPMSK2_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1103 | #define USB_DAINTMSK_OUTEPMSK3 (0x1UL << 19) /**< OUT Endpoint 3 Interrupt mask Bit */ |
| AnnaBridge | 171:3a7713b1edbc | 1104 | #define _USB_DAINTMSK_OUTEPMSK3_SHIFT 19 /**< Shift value for USB_OUTEPMSK3 */ |
| AnnaBridge | 171:3a7713b1edbc | 1105 | #define _USB_DAINTMSK_OUTEPMSK3_MASK 0x80000UL /**< Bit mask for USB_OUTEPMSK3 */ |
| AnnaBridge | 171:3a7713b1edbc | 1106 | #define _USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1107 | #define USB_DAINTMSK_OUTEPMSK3_DEFAULT (_USB_DAINTMSK_OUTEPMSK3_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DAINTMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1108 | |
| AnnaBridge | 171:3a7713b1edbc | 1109 | /* Bit fields for USB DIEPEMPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1110 | #define _USB_DIEPEMPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DIEPEMPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1111 | #define _USB_DIEPEMPMSK_MASK 0x0000FFFFUL /**< Mask for USB_DIEPEMPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1112 | #define _USB_DIEPEMPMSK_DIEPEMPMSK_SHIFT 0 /**< Shift value for USB_DIEPEMPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1113 | #define _USB_DIEPEMPMSK_DIEPEMPMSK_MASK 0xFFFFUL /**< Bit mask for USB_DIEPEMPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1114 | #define _USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPEMPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1115 | #define USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT (_USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPEMPMSK */ |
| AnnaBridge | 171:3a7713b1edbc | 1116 | |
| AnnaBridge | 171:3a7713b1edbc | 1117 | /* Bit fields for USB DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1118 | #define _USB_DIEP0CTL_RESETVALUE 0x00008000UL /**< Default value for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1119 | #define _USB_DIEP0CTL_MASK 0xCFEE8003UL /**< Mask for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1120 | #define _USB_DIEP0CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ |
| AnnaBridge | 171:3a7713b1edbc | 1121 | #define _USB_DIEP0CTL_MPS_MASK 0x3UL /**< Bit mask for USB_MPS */ |
| AnnaBridge | 171:3a7713b1edbc | 1122 | #define _USB_DIEP0CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1123 | #define _USB_DIEP0CTL_MPS_64B 0x00000000UL /**< Mode 64B for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1124 | #define _USB_DIEP0CTL_MPS_32B 0x00000001UL /**< Mode 32B for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1125 | #define _USB_DIEP0CTL_MPS_16B 0x00000002UL /**< Mode 16B for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1126 | #define _USB_DIEP0CTL_MPS_8B 0x00000003UL /**< Mode 8B for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1127 | #define USB_DIEP0CTL_MPS_DEFAULT (_USB_DIEP0CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1128 | #define USB_DIEP0CTL_MPS_64B (_USB_DIEP0CTL_MPS_64B << 0) /**< Shifted mode 64B for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1129 | #define USB_DIEP0CTL_MPS_32B (_USB_DIEP0CTL_MPS_32B << 0) /**< Shifted mode 32B for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1130 | #define USB_DIEP0CTL_MPS_16B (_USB_DIEP0CTL_MPS_16B << 0) /**< Shifted mode 16B for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1131 | #define USB_DIEP0CTL_MPS_8B (_USB_DIEP0CTL_MPS_8B << 0) /**< Shifted mode 8B for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1132 | #define USB_DIEP0CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ |
| AnnaBridge | 171:3a7713b1edbc | 1133 | #define _USB_DIEP0CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ |
| AnnaBridge | 171:3a7713b1edbc | 1134 | #define _USB_DIEP0CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ |
| AnnaBridge | 171:3a7713b1edbc | 1135 | #define _USB_DIEP0CTL_USBACTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1136 | #define USB_DIEP0CTL_USBACTEP_DEFAULT (_USB_DIEP0CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1137 | #define USB_DIEP0CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ |
| AnnaBridge | 171:3a7713b1edbc | 1138 | #define _USB_DIEP0CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1139 | #define _USB_DIEP0CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1140 | #define _USB_DIEP0CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1141 | #define USB_DIEP0CTL_NAKSTS_DEFAULT (_USB_DIEP0CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1142 | #define _USB_DIEP0CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ |
| AnnaBridge | 171:3a7713b1edbc | 1143 | #define _USB_DIEP0CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ |
| AnnaBridge | 171:3a7713b1edbc | 1144 | #define _USB_DIEP0CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1145 | #define USB_DIEP0CTL_EPTYPE_DEFAULT (_USB_DIEP0CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1146 | #define USB_DIEP0CTL_STALL (0x1UL << 21) /**< Handshake */ |
| AnnaBridge | 171:3a7713b1edbc | 1147 | #define _USB_DIEP0CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ |
| AnnaBridge | 171:3a7713b1edbc | 1148 | #define _USB_DIEP0CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ |
| AnnaBridge | 171:3a7713b1edbc | 1149 | #define _USB_DIEP0CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1150 | #define USB_DIEP0CTL_STALL_DEFAULT (_USB_DIEP0CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1151 | #define _USB_DIEP0CTL_TXFNUM_SHIFT 22 /**< Shift value for USB_TXFNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 1152 | #define _USB_DIEP0CTL_TXFNUM_MASK 0x3C00000UL /**< Bit mask for USB_TXFNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 1153 | #define _USB_DIEP0CTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1154 | #define USB_DIEP0CTL_TXFNUM_DEFAULT (_USB_DIEP0CTL_TXFNUM_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1155 | #define USB_DIEP0CTL_CNAK (0x1UL << 26) /**< Clear NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1156 | #define _USB_DIEP0CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1157 | #define _USB_DIEP0CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1158 | #define _USB_DIEP0CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1159 | #define USB_DIEP0CTL_CNAK_DEFAULT (_USB_DIEP0CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1160 | #define USB_DIEP0CTL_SNAK (0x1UL << 27) /**< Set NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1161 | #define _USB_DIEP0CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1162 | #define _USB_DIEP0CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1163 | #define _USB_DIEP0CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1164 | #define USB_DIEP0CTL_SNAK_DEFAULT (_USB_DIEP0CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1165 | #define USB_DIEP0CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 1166 | #define _USB_DIEP0CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1167 | #define _USB_DIEP0CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1168 | #define _USB_DIEP0CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1169 | #define USB_DIEP0CTL_EPDIS_DEFAULT (_USB_DIEP0CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1170 | #define USB_DIEP0CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1171 | #define _USB_DIEP0CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ |
| AnnaBridge | 171:3a7713b1edbc | 1172 | #define _USB_DIEP0CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ |
| AnnaBridge | 171:3a7713b1edbc | 1173 | #define _USB_DIEP0CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1174 | #define USB_DIEP0CTL_EPENA_DEFAULT (_USB_DIEP0CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DIEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1175 | |
| AnnaBridge | 171:3a7713b1edbc | 1176 | /* Bit fields for USB DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1177 | #define _USB_DIEP0INT_RESETVALUE 0x00000080UL /**< Default value for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1178 | #define _USB_DIEP0INT_MASK 0x000038DFUL /**< Mask for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1179 | #define USB_DIEP0INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1180 | #define _USB_DIEP0INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ |
| AnnaBridge | 171:3a7713b1edbc | 1181 | #define _USB_DIEP0INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ |
| AnnaBridge | 171:3a7713b1edbc | 1182 | #define _USB_DIEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1183 | #define USB_DIEP0INT_XFERCOMPL_DEFAULT (_USB_DIEP0INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1184 | #define USB_DIEP0INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1185 | #define _USB_DIEP0INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ |
| AnnaBridge | 171:3a7713b1edbc | 1186 | #define _USB_DIEP0INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ |
| AnnaBridge | 171:3a7713b1edbc | 1187 | #define _USB_DIEP0INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1188 | #define USB_DIEP0INT_EPDISBLD_DEFAULT (_USB_DIEP0INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1189 | #define USB_DIEP0INT_AHBERR (0x1UL << 2) /**< AHB Error */ |
| AnnaBridge | 171:3a7713b1edbc | 1190 | #define _USB_DIEP0INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1191 | #define _USB_DIEP0INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1192 | #define _USB_DIEP0INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1193 | #define USB_DIEP0INT_AHBERR_DEFAULT (_USB_DIEP0INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1194 | #define USB_DIEP0INT_TIMEOUT (0x1UL << 3) /**< Timeout Condition */ |
| AnnaBridge | 171:3a7713b1edbc | 1195 | #define _USB_DIEP0INT_TIMEOUT_SHIFT 3 /**< Shift value for USB_TIMEOUT */ |
| AnnaBridge | 171:3a7713b1edbc | 1196 | #define _USB_DIEP0INT_TIMEOUT_MASK 0x8UL /**< Bit mask for USB_TIMEOUT */ |
| AnnaBridge | 171:3a7713b1edbc | 1197 | #define _USB_DIEP0INT_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1198 | #define USB_DIEP0INT_TIMEOUT_DEFAULT (_USB_DIEP0INT_TIMEOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1199 | #define USB_DIEP0INT_INTKNTXFEMP (0x1UL << 4) /**< IN Token Received When TxFIFO is Empty */ |
| AnnaBridge | 171:3a7713b1edbc | 1200 | #define _USB_DIEP0INT_INTKNTXFEMP_SHIFT 4 /**< Shift value for USB_INTKNTXFEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 1201 | #define _USB_DIEP0INT_INTKNTXFEMP_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 1202 | #define _USB_DIEP0INT_INTKNTXFEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1203 | #define USB_DIEP0INT_INTKNTXFEMP_DEFAULT (_USB_DIEP0INT_INTKNTXFEMP_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1204 | #define USB_DIEP0INT_INEPNAKEFF (0x1UL << 6) /**< IN Endpoint NAK Effective */ |
| AnnaBridge | 171:3a7713b1edbc | 1205 | #define _USB_DIEP0INT_INEPNAKEFF_SHIFT 6 /**< Shift value for USB_INEPNAKEFF */ |
| AnnaBridge | 171:3a7713b1edbc | 1206 | #define _USB_DIEP0INT_INEPNAKEFF_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFF */ |
| AnnaBridge | 171:3a7713b1edbc | 1207 | #define _USB_DIEP0INT_INEPNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1208 | #define USB_DIEP0INT_INEPNAKEFF_DEFAULT (_USB_DIEP0INT_INEPNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1209 | #define USB_DIEP0INT_TXFEMP (0x1UL << 7) /**< Transmit FIFO Empty */ |
| AnnaBridge | 171:3a7713b1edbc | 1210 | #define _USB_DIEP0INT_TXFEMP_SHIFT 7 /**< Shift value for USB_TXFEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 1211 | #define _USB_DIEP0INT_TXFEMP_MASK 0x80UL /**< Bit mask for USB_TXFEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 1212 | #define _USB_DIEP0INT_TXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1213 | #define USB_DIEP0INT_TXFEMP_DEFAULT (_USB_DIEP0INT_TXFEMP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1214 | #define USB_DIEP0INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ |
| AnnaBridge | 171:3a7713b1edbc | 1215 | #define _USB_DIEP0INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1216 | #define _USB_DIEP0INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1217 | #define _USB_DIEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1218 | #define USB_DIEP0INT_PKTDRPSTS_DEFAULT (_USB_DIEP0INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1219 | #define USB_DIEP0INT_BBLEERR (0x1UL << 12) /**< NAK Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1220 | #define _USB_DIEP0INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1221 | #define _USB_DIEP0INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1222 | #define _USB_DIEP0INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1223 | #define USB_DIEP0INT_BBLEERR_DEFAULT (_USB_DIEP0INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1224 | #define USB_DIEP0INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1225 | #define _USB_DIEP0INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ |
| AnnaBridge | 171:3a7713b1edbc | 1226 | #define _USB_DIEP0INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ |
| AnnaBridge | 171:3a7713b1edbc | 1227 | #define _USB_DIEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1228 | #define USB_DIEP0INT_NAKINTRPT_DEFAULT (_USB_DIEP0INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1229 | |
| AnnaBridge | 171:3a7713b1edbc | 1230 | /* Bit fields for USB DIEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1231 | #define _USB_DIEP0TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1232 | #define _USB_DIEP0TSIZ_MASK 0x0018007FUL /**< Mask for USB_DIEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1233 | #define _USB_DIEP0TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1234 | #define _USB_DIEP0TSIZ_XFERSIZE_MASK 0x7FUL /**< Bit mask for USB_XFERSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1235 | #define _USB_DIEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1236 | #define USB_DIEP0TSIZ_XFERSIZE_DEFAULT (_USB_DIEP0TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1237 | #define _USB_DIEP0TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1238 | #define _USB_DIEP0TSIZ_PKTCNT_MASK 0x180000UL /**< Bit mask for USB_PKTCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1239 | #define _USB_DIEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1240 | #define USB_DIEP0TSIZ_PKTCNT_DEFAULT (_USB_DIEP0TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DIEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1241 | |
| AnnaBridge | 171:3a7713b1edbc | 1242 | /* Bit fields for USB DIEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1243 | #define _USB_DIEP0DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1244 | #define _USB_DIEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DIEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1245 | #define _USB_DIEP0DMAADDR_DIEP0DMAADDR_SHIFT 0 /**< Shift value for USB_DIEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1246 | #define _USB_DIEP0DMAADDR_DIEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DIEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1247 | #define _USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1248 | #define USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT (_USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1249 | |
| AnnaBridge | 171:3a7713b1edbc | 1250 | /* Bit fields for USB DIEP0TXFSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1251 | #define _USB_DIEP0TXFSTS_RESETVALUE 0x00000200UL /**< Default value for USB_DIEP0TXFSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1252 | #define _USB_DIEP0TXFSTS_MASK 0x0000FFFFUL /**< Mask for USB_DIEP0TXFSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1253 | #define _USB_DIEP0TXFSTS_SPCAVAIL_SHIFT 0 /**< Shift value for USB_SPCAVAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 1254 | #define _USB_DIEP0TXFSTS_SPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_SPCAVAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 1255 | #define _USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEP0TXFSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1256 | #define USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0TXFSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1257 | |
| AnnaBridge | 171:3a7713b1edbc | 1258 | /* Bit fields for USB DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1259 | #define _USB_DIEP_CTL_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1260 | #define _USB_DIEP_CTL_MASK 0xFFEF87FFUL /**< Mask for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1261 | #define _USB_DIEP_CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ |
| AnnaBridge | 171:3a7713b1edbc | 1262 | #define _USB_DIEP_CTL_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */ |
| AnnaBridge | 171:3a7713b1edbc | 1263 | #define _USB_DIEP_CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1264 | #define USB_DIEP_CTL_MPS_DEFAULT (_USB_DIEP_CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1265 | #define USB_DIEP_CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ |
| AnnaBridge | 171:3a7713b1edbc | 1266 | #define _USB_DIEP_CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ |
| AnnaBridge | 171:3a7713b1edbc | 1267 | #define _USB_DIEP_CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ |
| AnnaBridge | 171:3a7713b1edbc | 1268 | #define _USB_DIEP_CTL_USBACTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1269 | #define USB_DIEP_CTL_USBACTEP_DEFAULT (_USB_DIEP_CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1270 | #define USB_DIEP_CTL_DPIDEOF (0x1UL << 16) /**< Endpoint Data PID / Even or Odd Frame */ |
| AnnaBridge | 171:3a7713b1edbc | 1271 | #define _USB_DIEP_CTL_DPIDEOF_SHIFT 16 /**< Shift value for USB_DPIDEOF */ |
| AnnaBridge | 171:3a7713b1edbc | 1272 | #define _USB_DIEP_CTL_DPIDEOF_MASK 0x10000UL /**< Bit mask for USB_DPIDEOF */ |
| AnnaBridge | 171:3a7713b1edbc | 1273 | #define _USB_DIEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1274 | #define _USB_DIEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /**< Mode DATA0EVEN for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1275 | #define _USB_DIEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /**< Mode DATA1ODD for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1276 | #define USB_DIEP_CTL_DPIDEOF_DEFAULT (_USB_DIEP_CTL_DPIDEOF_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1277 | #define USB_DIEP_CTL_DPIDEOF_DATA0EVEN (_USB_DIEP_CTL_DPIDEOF_DATA0EVEN << 16) /**< Shifted mode DATA0EVEN for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1278 | #define USB_DIEP_CTL_DPIDEOF_DATA1ODD (_USB_DIEP_CTL_DPIDEOF_DATA1ODD << 16) /**< Shifted mode DATA1ODD for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1279 | #define USB_DIEP_CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ |
| AnnaBridge | 171:3a7713b1edbc | 1280 | #define _USB_DIEP_CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1281 | #define _USB_DIEP_CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1282 | #define _USB_DIEP_CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1283 | #define USB_DIEP_CTL_NAKSTS_DEFAULT (_USB_DIEP_CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1284 | #define _USB_DIEP_CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ |
| AnnaBridge | 171:3a7713b1edbc | 1285 | #define _USB_DIEP_CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ |
| AnnaBridge | 171:3a7713b1edbc | 1286 | #define _USB_DIEP_CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1287 | #define _USB_DIEP_CTL_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1288 | #define _USB_DIEP_CTL_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1289 | #define _USB_DIEP_CTL_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1290 | #define _USB_DIEP_CTL_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1291 | #define USB_DIEP_CTL_EPTYPE_DEFAULT (_USB_DIEP_CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1292 | #define USB_DIEP_CTL_EPTYPE_CONTROL (_USB_DIEP_CTL_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1293 | #define USB_DIEP_CTL_EPTYPE_ISO (_USB_DIEP_CTL_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1294 | #define USB_DIEP_CTL_EPTYPE_BULK (_USB_DIEP_CTL_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1295 | #define USB_DIEP_CTL_EPTYPE_INT (_USB_DIEP_CTL_EPTYPE_INT << 18) /**< Shifted mode INT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1296 | #define USB_DIEP_CTL_STALL (0x1UL << 21) /**< Handshake */ |
| AnnaBridge | 171:3a7713b1edbc | 1297 | #define _USB_DIEP_CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ |
| AnnaBridge | 171:3a7713b1edbc | 1298 | #define _USB_DIEP_CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ |
| AnnaBridge | 171:3a7713b1edbc | 1299 | #define _USB_DIEP_CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1300 | #define USB_DIEP_CTL_STALL_DEFAULT (_USB_DIEP_CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1301 | #define _USB_DIEP_CTL_TXFNUM_SHIFT 22 /**< Shift value for USB_TXFNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 1302 | #define _USB_DIEP_CTL_TXFNUM_MASK 0x3C00000UL /**< Bit mask for USB_TXFNUM */ |
| AnnaBridge | 171:3a7713b1edbc | 1303 | #define _USB_DIEP_CTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1304 | #define USB_DIEP_CTL_TXFNUM_DEFAULT (_USB_DIEP_CTL_TXFNUM_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1305 | #define USB_DIEP_CTL_CNAK (0x1UL << 26) /**< Clear NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1306 | #define _USB_DIEP_CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1307 | #define _USB_DIEP_CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1308 | #define _USB_DIEP_CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1309 | #define USB_DIEP_CTL_CNAK_DEFAULT (_USB_DIEP_CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1310 | #define USB_DIEP_CTL_SNAK (0x1UL << 27) /**< Set NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1311 | #define _USB_DIEP_CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1312 | #define _USB_DIEP_CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1313 | #define _USB_DIEP_CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1314 | #define USB_DIEP_CTL_SNAK_DEFAULT (_USB_DIEP_CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1315 | #define USB_DIEP_CTL_SETD0PIDEF (0x1UL << 28) /**< Set DATA0 PID / Even Frame */ |
| AnnaBridge | 171:3a7713b1edbc | 1316 | #define _USB_DIEP_CTL_SETD0PIDEF_SHIFT 28 /**< Shift value for USB_SETD0PIDEF */ |
| AnnaBridge | 171:3a7713b1edbc | 1317 | #define _USB_DIEP_CTL_SETD0PIDEF_MASK 0x10000000UL /**< Bit mask for USB_SETD0PIDEF */ |
| AnnaBridge | 171:3a7713b1edbc | 1318 | #define _USB_DIEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1319 | #define USB_DIEP_CTL_SETD0PIDEF_DEFAULT (_USB_DIEP_CTL_SETD0PIDEF_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1320 | #define USB_DIEP_CTL_SETD1PIDOF (0x1UL << 29) /**< Set DATA1 PID / Odd Frame */ |
| AnnaBridge | 171:3a7713b1edbc | 1321 | #define _USB_DIEP_CTL_SETD1PIDOF_SHIFT 29 /**< Shift value for USB_SETD1PIDOF */ |
| AnnaBridge | 171:3a7713b1edbc | 1322 | #define _USB_DIEP_CTL_SETD1PIDOF_MASK 0x20000000UL /**< Bit mask for USB_SETD1PIDOF */ |
| AnnaBridge | 171:3a7713b1edbc | 1323 | #define _USB_DIEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1324 | #define USB_DIEP_CTL_SETD1PIDOF_DEFAULT (_USB_DIEP_CTL_SETD1PIDOF_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1325 | #define USB_DIEP_CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 1326 | #define _USB_DIEP_CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1327 | #define _USB_DIEP_CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1328 | #define _USB_DIEP_CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1329 | #define USB_DIEP_CTL_EPDIS_DEFAULT (_USB_DIEP_CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1330 | #define USB_DIEP_CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1331 | #define _USB_DIEP_CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ |
| AnnaBridge | 171:3a7713b1edbc | 1332 | #define _USB_DIEP_CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ |
| AnnaBridge | 171:3a7713b1edbc | 1333 | #define _USB_DIEP_CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1334 | #define USB_DIEP_CTL_EPENA_DEFAULT (_USB_DIEP_CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DIEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1335 | |
| AnnaBridge | 171:3a7713b1edbc | 1336 | /* Bit fields for USB DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1337 | #define _USB_DIEP_INT_RESETVALUE 0x00000080UL /**< Default value for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1338 | #define _USB_DIEP_INT_MASK 0x000038DFUL /**< Mask for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1339 | #define USB_DIEP_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1340 | #define _USB_DIEP_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ |
| AnnaBridge | 171:3a7713b1edbc | 1341 | #define _USB_DIEP_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ |
| AnnaBridge | 171:3a7713b1edbc | 1342 | #define _USB_DIEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1343 | #define USB_DIEP_INT_XFERCOMPL_DEFAULT (_USB_DIEP_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1344 | #define USB_DIEP_INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1345 | #define _USB_DIEP_INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ |
| AnnaBridge | 171:3a7713b1edbc | 1346 | #define _USB_DIEP_INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ |
| AnnaBridge | 171:3a7713b1edbc | 1347 | #define _USB_DIEP_INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1348 | #define USB_DIEP_INT_EPDISBLD_DEFAULT (_USB_DIEP_INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1349 | #define USB_DIEP_INT_AHBERR (0x1UL << 2) /**< AHB Error */ |
| AnnaBridge | 171:3a7713b1edbc | 1350 | #define _USB_DIEP_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1351 | #define _USB_DIEP_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1352 | #define _USB_DIEP_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1353 | #define USB_DIEP_INT_AHBERR_DEFAULT (_USB_DIEP_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1354 | #define USB_DIEP_INT_TIMEOUT (0x1UL << 3) /**< Timeout Condition */ |
| AnnaBridge | 171:3a7713b1edbc | 1355 | #define _USB_DIEP_INT_TIMEOUT_SHIFT 3 /**< Shift value for USB_TIMEOUT */ |
| AnnaBridge | 171:3a7713b1edbc | 1356 | #define _USB_DIEP_INT_TIMEOUT_MASK 0x8UL /**< Bit mask for USB_TIMEOUT */ |
| AnnaBridge | 171:3a7713b1edbc | 1357 | #define _USB_DIEP_INT_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1358 | #define USB_DIEP_INT_TIMEOUT_DEFAULT (_USB_DIEP_INT_TIMEOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1359 | #define USB_DIEP_INT_INTKNTXFEMP (0x1UL << 4) /**< IN Token Received When TxFIFO is Empty */ |
| AnnaBridge | 171:3a7713b1edbc | 1360 | #define _USB_DIEP_INT_INTKNTXFEMP_SHIFT 4 /**< Shift value for USB_INTKNTXFEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 1361 | #define _USB_DIEP_INT_INTKNTXFEMP_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 1362 | #define _USB_DIEP_INT_INTKNTXFEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1363 | #define USB_DIEP_INT_INTKNTXFEMP_DEFAULT (_USB_DIEP_INT_INTKNTXFEMP_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1364 | #define USB_DIEP_INT_INEPNAKEFF (0x1UL << 6) /**< IN Endpoint NAK Effective */ |
| AnnaBridge | 171:3a7713b1edbc | 1365 | #define _USB_DIEP_INT_INEPNAKEFF_SHIFT 6 /**< Shift value for USB_INEPNAKEFF */ |
| AnnaBridge | 171:3a7713b1edbc | 1366 | #define _USB_DIEP_INT_INEPNAKEFF_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFF */ |
| AnnaBridge | 171:3a7713b1edbc | 1367 | #define _USB_DIEP_INT_INEPNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1368 | #define USB_DIEP_INT_INEPNAKEFF_DEFAULT (_USB_DIEP_INT_INEPNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1369 | #define USB_DIEP_INT_TXFEMP (0x1UL << 7) /**< Transmit FIFO Empty */ |
| AnnaBridge | 171:3a7713b1edbc | 1370 | #define _USB_DIEP_INT_TXFEMP_SHIFT 7 /**< Shift value for USB_TXFEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 1371 | #define _USB_DIEP_INT_TXFEMP_MASK 0x80UL /**< Bit mask for USB_TXFEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 1372 | #define _USB_DIEP_INT_TXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1373 | #define USB_DIEP_INT_TXFEMP_DEFAULT (_USB_DIEP_INT_TXFEMP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1374 | #define USB_DIEP_INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ |
| AnnaBridge | 171:3a7713b1edbc | 1375 | #define _USB_DIEP_INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1376 | #define _USB_DIEP_INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1377 | #define _USB_DIEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1378 | #define USB_DIEP_INT_PKTDRPSTS_DEFAULT (_USB_DIEP_INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1379 | #define USB_DIEP_INT_BBLEERR (0x1UL << 12) /**< NAK Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1380 | #define _USB_DIEP_INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1381 | #define _USB_DIEP_INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1382 | #define _USB_DIEP_INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1383 | #define USB_DIEP_INT_BBLEERR_DEFAULT (_USB_DIEP_INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1384 | #define USB_DIEP_INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1385 | #define _USB_DIEP_INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ |
| AnnaBridge | 171:3a7713b1edbc | 1386 | #define _USB_DIEP_INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ |
| AnnaBridge | 171:3a7713b1edbc | 1387 | #define _USB_DIEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1388 | #define USB_DIEP_INT_NAKINTRPT_DEFAULT (_USB_DIEP_INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1389 | |
| AnnaBridge | 171:3a7713b1edbc | 1390 | /* Bit fields for USB DIEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1391 | #define _USB_DIEP_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1392 | #define _USB_DIEP_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_DIEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1393 | #define _USB_DIEP_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1394 | #define _USB_DIEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1395 | #define _USB_DIEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1396 | #define USB_DIEP_TSIZ_XFERSIZE_DEFAULT (_USB_DIEP_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1397 | #define _USB_DIEP_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1398 | #define _USB_DIEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1399 | #define _USB_DIEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1400 | #define USB_DIEP_TSIZ_PKTCNT_DEFAULT (_USB_DIEP_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1401 | #define _USB_DIEP_TSIZ_MC_SHIFT 29 /**< Shift value for USB_MC */ |
| AnnaBridge | 171:3a7713b1edbc | 1402 | #define _USB_DIEP_TSIZ_MC_MASK 0x60000000UL /**< Bit mask for USB_MC */ |
| AnnaBridge | 171:3a7713b1edbc | 1403 | #define _USB_DIEP_TSIZ_MC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1404 | #define USB_DIEP_TSIZ_MC_DEFAULT (_USB_DIEP_TSIZ_MC_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1405 | |
| AnnaBridge | 171:3a7713b1edbc | 1406 | /* Bit fields for USB DIEP_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1407 | #define _USB_DIEP_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1408 | #define _USB_DIEP_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DIEP_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1409 | #define _USB_DIEP_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1410 | #define _USB_DIEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1411 | #define _USB_DIEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1412 | #define USB_DIEP_DMAADDR_DMAADDR_DEFAULT (_USB_DIEP_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1413 | |
| AnnaBridge | 171:3a7713b1edbc | 1414 | /* Bit fields for USB DIEP_TXFSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1415 | #define _USB_DIEP_TXFSTS_RESETVALUE 0x00000200UL /**< Default value for USB_DIEP_TXFSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1416 | #define _USB_DIEP_TXFSTS_MASK 0x0000FFFFUL /**< Mask for USB_DIEP_TXFSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1417 | #define _USB_DIEP_TXFSTS_SPCAVAIL_SHIFT 0 /**< Shift value for USB_SPCAVAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 1418 | #define _USB_DIEP_TXFSTS_SPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_SPCAVAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 1419 | #define _USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEP_TXFSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1420 | #define USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_TXFSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1421 | |
| AnnaBridge | 171:3a7713b1edbc | 1422 | /* Bit fields for USB DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1423 | #define _USB_DOEP0CTL_RESETVALUE 0x00008000UL /**< Default value for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1424 | #define _USB_DOEP0CTL_MASK 0xCC3E8003UL /**< Mask for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1425 | #define _USB_DOEP0CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ |
| AnnaBridge | 171:3a7713b1edbc | 1426 | #define _USB_DOEP0CTL_MPS_MASK 0x3UL /**< Bit mask for USB_MPS */ |
| AnnaBridge | 171:3a7713b1edbc | 1427 | #define _USB_DOEP0CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1428 | #define _USB_DOEP0CTL_MPS_64B 0x00000000UL /**< Mode 64B for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1429 | #define _USB_DOEP0CTL_MPS_32B 0x00000001UL /**< Mode 32B for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1430 | #define _USB_DOEP0CTL_MPS_16B 0x00000002UL /**< Mode 16B for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1431 | #define _USB_DOEP0CTL_MPS_8B 0x00000003UL /**< Mode 8B for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1432 | #define USB_DOEP0CTL_MPS_DEFAULT (_USB_DOEP0CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1433 | #define USB_DOEP0CTL_MPS_64B (_USB_DOEP0CTL_MPS_64B << 0) /**< Shifted mode 64B for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1434 | #define USB_DOEP0CTL_MPS_32B (_USB_DOEP0CTL_MPS_32B << 0) /**< Shifted mode 32B for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1435 | #define USB_DOEP0CTL_MPS_16B (_USB_DOEP0CTL_MPS_16B << 0) /**< Shifted mode 16B for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1436 | #define USB_DOEP0CTL_MPS_8B (_USB_DOEP0CTL_MPS_8B << 0) /**< Shifted mode 8B for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1437 | #define USB_DOEP0CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ |
| AnnaBridge | 171:3a7713b1edbc | 1438 | #define _USB_DOEP0CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ |
| AnnaBridge | 171:3a7713b1edbc | 1439 | #define _USB_DOEP0CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ |
| AnnaBridge | 171:3a7713b1edbc | 1440 | #define _USB_DOEP0CTL_USBACTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1441 | #define USB_DOEP0CTL_USBACTEP_DEFAULT (_USB_DOEP0CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1442 | #define USB_DOEP0CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ |
| AnnaBridge | 171:3a7713b1edbc | 1443 | #define _USB_DOEP0CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1444 | #define _USB_DOEP0CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1445 | #define _USB_DOEP0CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1446 | #define USB_DOEP0CTL_NAKSTS_DEFAULT (_USB_DOEP0CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1447 | #define _USB_DOEP0CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ |
| AnnaBridge | 171:3a7713b1edbc | 1448 | #define _USB_DOEP0CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ |
| AnnaBridge | 171:3a7713b1edbc | 1449 | #define _USB_DOEP0CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1450 | #define USB_DOEP0CTL_EPTYPE_DEFAULT (_USB_DOEP0CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1451 | #define USB_DOEP0CTL_SNP (0x1UL << 20) /**< Snoop Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 1452 | #define _USB_DOEP0CTL_SNP_SHIFT 20 /**< Shift value for USB_SNP */ |
| AnnaBridge | 171:3a7713b1edbc | 1453 | #define _USB_DOEP0CTL_SNP_MASK 0x100000UL /**< Bit mask for USB_SNP */ |
| AnnaBridge | 171:3a7713b1edbc | 1454 | #define _USB_DOEP0CTL_SNP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1455 | #define USB_DOEP0CTL_SNP_DEFAULT (_USB_DOEP0CTL_SNP_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1456 | #define USB_DOEP0CTL_STALL (0x1UL << 21) /**< Handshake */ |
| AnnaBridge | 171:3a7713b1edbc | 1457 | #define _USB_DOEP0CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ |
| AnnaBridge | 171:3a7713b1edbc | 1458 | #define _USB_DOEP0CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ |
| AnnaBridge | 171:3a7713b1edbc | 1459 | #define _USB_DOEP0CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1460 | #define USB_DOEP0CTL_STALL_DEFAULT (_USB_DOEP0CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1461 | #define USB_DOEP0CTL_CNAK (0x1UL << 26) /**< Clear NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1462 | #define _USB_DOEP0CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1463 | #define _USB_DOEP0CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1464 | #define _USB_DOEP0CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1465 | #define USB_DOEP0CTL_CNAK_DEFAULT (_USB_DOEP0CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1466 | #define USB_DOEP0CTL_SNAK (0x1UL << 27) /**< Set NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1467 | #define _USB_DOEP0CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1468 | #define _USB_DOEP0CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1469 | #define _USB_DOEP0CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1470 | #define USB_DOEP0CTL_SNAK_DEFAULT (_USB_DOEP0CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1471 | #define USB_DOEP0CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 1472 | #define _USB_DOEP0CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1473 | #define _USB_DOEP0CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1474 | #define _USB_DOEP0CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1475 | #define USB_DOEP0CTL_EPDIS_DEFAULT (_USB_DOEP0CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1476 | #define USB_DOEP0CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1477 | #define _USB_DOEP0CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ |
| AnnaBridge | 171:3a7713b1edbc | 1478 | #define _USB_DOEP0CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ |
| AnnaBridge | 171:3a7713b1edbc | 1479 | #define _USB_DOEP0CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1480 | #define USB_DOEP0CTL_EPENA_DEFAULT (_USB_DOEP0CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DOEP0CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1481 | |
| AnnaBridge | 171:3a7713b1edbc | 1482 | /* Bit fields for USB DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1483 | #define _USB_DOEP0INT_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1484 | #define _USB_DOEP0INT_MASK 0x0000B87FUL /**< Mask for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1485 | #define USB_DOEP0INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1486 | #define _USB_DOEP0INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ |
| AnnaBridge | 171:3a7713b1edbc | 1487 | #define _USB_DOEP0INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ |
| AnnaBridge | 171:3a7713b1edbc | 1488 | #define _USB_DOEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1489 | #define USB_DOEP0INT_XFERCOMPL_DEFAULT (_USB_DOEP0INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1490 | #define USB_DOEP0INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1491 | #define _USB_DOEP0INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ |
| AnnaBridge | 171:3a7713b1edbc | 1492 | #define _USB_DOEP0INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ |
| AnnaBridge | 171:3a7713b1edbc | 1493 | #define _USB_DOEP0INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1494 | #define USB_DOEP0INT_EPDISBLD_DEFAULT (_USB_DOEP0INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1495 | #define USB_DOEP0INT_AHBERR (0x1UL << 2) /**< AHB Error */ |
| AnnaBridge | 171:3a7713b1edbc | 1496 | #define _USB_DOEP0INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1497 | #define _USB_DOEP0INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1498 | #define _USB_DOEP0INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1499 | #define USB_DOEP0INT_AHBERR_DEFAULT (_USB_DOEP0INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1500 | #define USB_DOEP0INT_SETUP (0x1UL << 3) /**< Setup Phase Done */ |
| AnnaBridge | 171:3a7713b1edbc | 1501 | #define _USB_DOEP0INT_SETUP_SHIFT 3 /**< Shift value for USB_SETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1502 | #define _USB_DOEP0INT_SETUP_MASK 0x8UL /**< Bit mask for USB_SETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1503 | #define _USB_DOEP0INT_SETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1504 | #define USB_DOEP0INT_SETUP_DEFAULT (_USB_DOEP0INT_SETUP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1505 | #define USB_DOEP0INT_OUTTKNEPDIS (0x1UL << 4) /**< OUT Token Received When Endpoint Disabled */ |
| AnnaBridge | 171:3a7713b1edbc | 1506 | #define _USB_DOEP0INT_OUTTKNEPDIS_SHIFT 4 /**< Shift value for USB_OUTTKNEPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1507 | #define _USB_DOEP0INT_OUTTKNEPDIS_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1508 | #define _USB_DOEP0INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1509 | #define USB_DOEP0INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP0INT_OUTTKNEPDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1510 | #define USB_DOEP0INT_STSPHSERCVD (0x1UL << 5) /**< Status Phase Received For Control Write */ |
| AnnaBridge | 171:3a7713b1edbc | 1511 | #define _USB_DOEP0INT_STSPHSERCVD_SHIFT 5 /**< Shift value for USB_STSPHSERCVD */ |
| AnnaBridge | 171:3a7713b1edbc | 1512 | #define _USB_DOEP0INT_STSPHSERCVD_MASK 0x20UL /**< Bit mask for USB_STSPHSERCVD */ |
| AnnaBridge | 171:3a7713b1edbc | 1513 | #define _USB_DOEP0INT_STSPHSERCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1514 | #define USB_DOEP0INT_STSPHSERCVD_DEFAULT (_USB_DOEP0INT_STSPHSERCVD_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1515 | #define USB_DOEP0INT_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received */ |
| AnnaBridge | 171:3a7713b1edbc | 1516 | #define _USB_DOEP0INT_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1517 | #define _USB_DOEP0INT_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1518 | #define _USB_DOEP0INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1519 | #define USB_DOEP0INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP0INT_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1520 | #define USB_DOEP0INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ |
| AnnaBridge | 171:3a7713b1edbc | 1521 | #define _USB_DOEP0INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1522 | #define _USB_DOEP0INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1523 | #define _USB_DOEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1524 | #define USB_DOEP0INT_PKTDRPSTS_DEFAULT (_USB_DOEP0INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1525 | #define USB_DOEP0INT_BBLEERR (0x1UL << 12) /**< NAK Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1526 | #define _USB_DOEP0INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1527 | #define _USB_DOEP0INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1528 | #define _USB_DOEP0INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1529 | #define USB_DOEP0INT_BBLEERR_DEFAULT (_USB_DOEP0INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1530 | #define USB_DOEP0INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1531 | #define _USB_DOEP0INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ |
| AnnaBridge | 171:3a7713b1edbc | 1532 | #define _USB_DOEP0INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ |
| AnnaBridge | 171:3a7713b1edbc | 1533 | #define _USB_DOEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1534 | #define USB_DOEP0INT_NAKINTRPT_DEFAULT (_USB_DOEP0INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1535 | #define USB_DOEP0INT_STUPPKTRCVD (0x1UL << 15) /**< Setup Packet Received */ |
| AnnaBridge | 171:3a7713b1edbc | 1536 | #define _USB_DOEP0INT_STUPPKTRCVD_SHIFT 15 /**< Shift value for USB_STUPPKTRCVD */ |
| AnnaBridge | 171:3a7713b1edbc | 1537 | #define _USB_DOEP0INT_STUPPKTRCVD_MASK 0x8000UL /**< Bit mask for USB_STUPPKTRCVD */ |
| AnnaBridge | 171:3a7713b1edbc | 1538 | #define _USB_DOEP0INT_STUPPKTRCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1539 | #define USB_DOEP0INT_STUPPKTRCVD_DEFAULT (_USB_DOEP0INT_STUPPKTRCVD_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP0INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1540 | |
| AnnaBridge | 171:3a7713b1edbc | 1541 | /* Bit fields for USB DOEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1542 | #define _USB_DOEP0TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1543 | #define _USB_DOEP0TSIZ_MASK 0x6008007FUL /**< Mask for USB_DOEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1544 | #define _USB_DOEP0TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1545 | #define _USB_DOEP0TSIZ_XFERSIZE_MASK 0x7FUL /**< Bit mask for USB_XFERSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1546 | #define _USB_DOEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1547 | #define USB_DOEP0TSIZ_XFERSIZE_DEFAULT (_USB_DOEP0TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1548 | #define USB_DOEP0TSIZ_PKTCNT (0x1UL << 19) /**< Packet Count */ |
| AnnaBridge | 171:3a7713b1edbc | 1549 | #define _USB_DOEP0TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1550 | #define _USB_DOEP0TSIZ_PKTCNT_MASK 0x80000UL /**< Bit mask for USB_PKTCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1551 | #define _USB_DOEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1552 | #define USB_DOEP0TSIZ_PKTCNT_DEFAULT (_USB_DOEP0TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1553 | #define _USB_DOEP0TSIZ_SUPCNT_SHIFT 29 /**< Shift value for USB_SUPCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1554 | #define _USB_DOEP0TSIZ_SUPCNT_MASK 0x60000000UL /**< Bit mask for USB_SUPCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1555 | #define _USB_DOEP0TSIZ_SUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1556 | #define USB_DOEP0TSIZ_SUPCNT_DEFAULT (_USB_DOEP0TSIZ_SUPCNT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1557 | |
| AnnaBridge | 171:3a7713b1edbc | 1558 | /* Bit fields for USB DOEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1559 | #define _USB_DOEP0DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1560 | #define _USB_DOEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DOEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1561 | #define _USB_DOEP0DMAADDR_DOEP0DMAADDR_SHIFT 0 /**< Shift value for USB_DOEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1562 | #define _USB_DOEP0DMAADDR_DOEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DOEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1563 | #define _USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1564 | #define USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT (_USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1565 | |
| AnnaBridge | 171:3a7713b1edbc | 1566 | /* Bit fields for USB DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1567 | #define _USB_DOEP_CTL_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1568 | #define _USB_DOEP_CTL_MASK 0xFC3F87FFUL /**< Mask for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1569 | #define _USB_DOEP_CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */ |
| AnnaBridge | 171:3a7713b1edbc | 1570 | #define _USB_DOEP_CTL_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */ |
| AnnaBridge | 171:3a7713b1edbc | 1571 | #define _USB_DOEP_CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1572 | #define USB_DOEP_CTL_MPS_DEFAULT (_USB_DOEP_CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1573 | #define USB_DOEP_CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */ |
| AnnaBridge | 171:3a7713b1edbc | 1574 | #define _USB_DOEP_CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */ |
| AnnaBridge | 171:3a7713b1edbc | 1575 | #define _USB_DOEP_CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */ |
| AnnaBridge | 171:3a7713b1edbc | 1576 | #define _USB_DOEP_CTL_USBACTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1577 | #define USB_DOEP_CTL_USBACTEP_DEFAULT (_USB_DOEP_CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1578 | #define USB_DOEP_CTL_DPIDEOF (0x1UL << 16) /**< Endpoint Data PID / Even-odd Frame */ |
| AnnaBridge | 171:3a7713b1edbc | 1579 | #define _USB_DOEP_CTL_DPIDEOF_SHIFT 16 /**< Shift value for USB_DPIDEOF */ |
| AnnaBridge | 171:3a7713b1edbc | 1580 | #define _USB_DOEP_CTL_DPIDEOF_MASK 0x10000UL /**< Bit mask for USB_DPIDEOF */ |
| AnnaBridge | 171:3a7713b1edbc | 1581 | #define _USB_DOEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1582 | #define _USB_DOEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /**< Mode DATA0EVEN for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1583 | #define _USB_DOEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /**< Mode DATA1ODD for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1584 | #define USB_DOEP_CTL_DPIDEOF_DEFAULT (_USB_DOEP_CTL_DPIDEOF_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1585 | #define USB_DOEP_CTL_DPIDEOF_DATA0EVEN (_USB_DOEP_CTL_DPIDEOF_DATA0EVEN << 16) /**< Shifted mode DATA0EVEN for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1586 | #define USB_DOEP_CTL_DPIDEOF_DATA1ODD (_USB_DOEP_CTL_DPIDEOF_DATA1ODD << 16) /**< Shifted mode DATA1ODD for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1587 | #define USB_DOEP_CTL_NAKSTS (0x1UL << 17) /**< NAK Status */ |
| AnnaBridge | 171:3a7713b1edbc | 1588 | #define _USB_DOEP_CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1589 | #define _USB_DOEP_CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1590 | #define _USB_DOEP_CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1591 | #define USB_DOEP_CTL_NAKSTS_DEFAULT (_USB_DOEP_CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1592 | #define _USB_DOEP_CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */ |
| AnnaBridge | 171:3a7713b1edbc | 1593 | #define _USB_DOEP_CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */ |
| AnnaBridge | 171:3a7713b1edbc | 1594 | #define _USB_DOEP_CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1595 | #define _USB_DOEP_CTL_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1596 | #define _USB_DOEP_CTL_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1597 | #define _USB_DOEP_CTL_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1598 | #define _USB_DOEP_CTL_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1599 | #define USB_DOEP_CTL_EPTYPE_DEFAULT (_USB_DOEP_CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1600 | #define USB_DOEP_CTL_EPTYPE_CONTROL (_USB_DOEP_CTL_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1601 | #define USB_DOEP_CTL_EPTYPE_ISO (_USB_DOEP_CTL_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1602 | #define USB_DOEP_CTL_EPTYPE_BULK (_USB_DOEP_CTL_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1603 | #define USB_DOEP_CTL_EPTYPE_INT (_USB_DOEP_CTL_EPTYPE_INT << 18) /**< Shifted mode INT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1604 | #define USB_DOEP_CTL_SNP (0x1UL << 20) /**< Snoop Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 1605 | #define _USB_DOEP_CTL_SNP_SHIFT 20 /**< Shift value for USB_SNP */ |
| AnnaBridge | 171:3a7713b1edbc | 1606 | #define _USB_DOEP_CTL_SNP_MASK 0x100000UL /**< Bit mask for USB_SNP */ |
| AnnaBridge | 171:3a7713b1edbc | 1607 | #define _USB_DOEP_CTL_SNP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1608 | #define USB_DOEP_CTL_SNP_DEFAULT (_USB_DOEP_CTL_SNP_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1609 | #define USB_DOEP_CTL_STALL (0x1UL << 21) /**< STALL Handshake */ |
| AnnaBridge | 171:3a7713b1edbc | 1610 | #define _USB_DOEP_CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */ |
| AnnaBridge | 171:3a7713b1edbc | 1611 | #define _USB_DOEP_CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */ |
| AnnaBridge | 171:3a7713b1edbc | 1612 | #define _USB_DOEP_CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1613 | #define USB_DOEP_CTL_STALL_DEFAULT (_USB_DOEP_CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1614 | #define USB_DOEP_CTL_CNAK (0x1UL << 26) /**< Clear NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1615 | #define _USB_DOEP_CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1616 | #define _USB_DOEP_CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1617 | #define _USB_DOEP_CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1618 | #define USB_DOEP_CTL_CNAK_DEFAULT (_USB_DOEP_CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1619 | #define USB_DOEP_CTL_SNAK (0x1UL << 27) /**< Set NAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1620 | #define _USB_DOEP_CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1621 | #define _USB_DOEP_CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */ |
| AnnaBridge | 171:3a7713b1edbc | 1622 | #define _USB_DOEP_CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1623 | #define USB_DOEP_CTL_SNAK_DEFAULT (_USB_DOEP_CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1624 | #define USB_DOEP_CTL_SETD0PIDEF (0x1UL << 28) /**< Set DATA0 PID / Even Frame */ |
| AnnaBridge | 171:3a7713b1edbc | 1625 | #define _USB_DOEP_CTL_SETD0PIDEF_SHIFT 28 /**< Shift value for USB_SETD0PIDEF */ |
| AnnaBridge | 171:3a7713b1edbc | 1626 | #define _USB_DOEP_CTL_SETD0PIDEF_MASK 0x10000000UL /**< Bit mask for USB_SETD0PIDEF */ |
| AnnaBridge | 171:3a7713b1edbc | 1627 | #define _USB_DOEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1628 | #define USB_DOEP_CTL_SETD0PIDEF_DEFAULT (_USB_DOEP_CTL_SETD0PIDEF_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1629 | #define USB_DOEP_CTL_SETD1PIDOF (0x1UL << 29) /**< Set DATA1 PID / Odd Frame */ |
| AnnaBridge | 171:3a7713b1edbc | 1630 | #define _USB_DOEP_CTL_SETD1PIDOF_SHIFT 29 /**< Shift value for USB_SETD1PIDOF */ |
| AnnaBridge | 171:3a7713b1edbc | 1631 | #define _USB_DOEP_CTL_SETD1PIDOF_MASK 0x20000000UL /**< Bit mask for USB_SETD1PIDOF */ |
| AnnaBridge | 171:3a7713b1edbc | 1632 | #define _USB_DOEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1633 | #define USB_DOEP_CTL_SETD1PIDOF_DEFAULT (_USB_DOEP_CTL_SETD1PIDOF_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1634 | #define USB_DOEP_CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 1635 | #define _USB_DOEP_CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1636 | #define _USB_DOEP_CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1637 | #define _USB_DOEP_CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1638 | #define USB_DOEP_CTL_EPDIS_DEFAULT (_USB_DOEP_CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1639 | #define USB_DOEP_CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1640 | #define _USB_DOEP_CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */ |
| AnnaBridge | 171:3a7713b1edbc | 1641 | #define _USB_DOEP_CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */ |
| AnnaBridge | 171:3a7713b1edbc | 1642 | #define _USB_DOEP_CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1643 | #define USB_DOEP_CTL_EPENA_DEFAULT (_USB_DOEP_CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DOEP_CTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1644 | |
| AnnaBridge | 171:3a7713b1edbc | 1645 | /* Bit fields for USB DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1646 | #define _USB_DOEP_INT_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1647 | #define _USB_DOEP_INT_MASK 0x0000B87FUL /**< Mask for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1648 | #define USB_DOEP_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1649 | #define _USB_DOEP_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */ |
| AnnaBridge | 171:3a7713b1edbc | 1650 | #define _USB_DOEP_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */ |
| AnnaBridge | 171:3a7713b1edbc | 1651 | #define _USB_DOEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1652 | #define USB_DOEP_INT_XFERCOMPL_DEFAULT (_USB_DOEP_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1653 | #define USB_DOEP_INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1654 | #define _USB_DOEP_INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */ |
| AnnaBridge | 171:3a7713b1edbc | 1655 | #define _USB_DOEP_INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */ |
| AnnaBridge | 171:3a7713b1edbc | 1656 | #define _USB_DOEP_INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1657 | #define USB_DOEP_INT_EPDISBLD_DEFAULT (_USB_DOEP_INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1658 | #define USB_DOEP_INT_AHBERR (0x1UL << 2) /**< AHB Error */ |
| AnnaBridge | 171:3a7713b1edbc | 1659 | #define _USB_DOEP_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1660 | #define _USB_DOEP_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1661 | #define _USB_DOEP_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1662 | #define USB_DOEP_INT_AHBERR_DEFAULT (_USB_DOEP_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1663 | #define USB_DOEP_INT_SETUP (0x1UL << 3) /**< Setup Phase Done */ |
| AnnaBridge | 171:3a7713b1edbc | 1664 | #define _USB_DOEP_INT_SETUP_SHIFT 3 /**< Shift value for USB_SETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1665 | #define _USB_DOEP_INT_SETUP_MASK 0x8UL /**< Bit mask for USB_SETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1666 | #define _USB_DOEP_INT_SETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1667 | #define USB_DOEP_INT_SETUP_DEFAULT (_USB_DOEP_INT_SETUP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1668 | #define USB_DOEP_INT_OUTTKNEPDIS (0x1UL << 4) /**< OUT Token Received When Endpoint Disabled */ |
| AnnaBridge | 171:3a7713b1edbc | 1669 | #define _USB_DOEP_INT_OUTTKNEPDIS_SHIFT 4 /**< Shift value for USB_OUTTKNEPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1670 | #define _USB_DOEP_INT_OUTTKNEPDIS_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1671 | #define _USB_DOEP_INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1672 | #define USB_DOEP_INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP_INT_OUTTKNEPDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1673 | #define USB_DOEP_INT_STSPHSERCVD (0x1UL << 5) /**< Status Phase Received For Control Write */ |
| AnnaBridge | 171:3a7713b1edbc | 1674 | #define _USB_DOEP_INT_STSPHSERCVD_SHIFT 5 /**< Shift value for USB_STSPHSERCVD */ |
| AnnaBridge | 171:3a7713b1edbc | 1675 | #define _USB_DOEP_INT_STSPHSERCVD_MASK 0x20UL /**< Bit mask for USB_STSPHSERCVD */ |
| AnnaBridge | 171:3a7713b1edbc | 1676 | #define _USB_DOEP_INT_STSPHSERCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1677 | #define USB_DOEP_INT_STSPHSERCVD_DEFAULT (_USB_DOEP_INT_STSPHSERCVD_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1678 | #define USB_DOEP_INT_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received */ |
| AnnaBridge | 171:3a7713b1edbc | 1679 | #define _USB_DOEP_INT_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1680 | #define _USB_DOEP_INT_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */ |
| AnnaBridge | 171:3a7713b1edbc | 1681 | #define _USB_DOEP_INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1682 | #define USB_DOEP_INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP_INT_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1683 | #define USB_DOEP_INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */ |
| AnnaBridge | 171:3a7713b1edbc | 1684 | #define _USB_DOEP_INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1685 | #define _USB_DOEP_INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */ |
| AnnaBridge | 171:3a7713b1edbc | 1686 | #define _USB_DOEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1687 | #define USB_DOEP_INT_PKTDRPSTS_DEFAULT (_USB_DOEP_INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1688 | #define USB_DOEP_INT_BBLEERR (0x1UL << 12) /**< Babble Error */ |
| AnnaBridge | 171:3a7713b1edbc | 1689 | #define _USB_DOEP_INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1690 | #define _USB_DOEP_INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */ |
| AnnaBridge | 171:3a7713b1edbc | 1691 | #define _USB_DOEP_INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1692 | #define USB_DOEP_INT_BBLEERR_DEFAULT (_USB_DOEP_INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1693 | #define USB_DOEP_INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 1694 | #define _USB_DOEP_INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */ |
| AnnaBridge | 171:3a7713b1edbc | 1695 | #define _USB_DOEP_INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */ |
| AnnaBridge | 171:3a7713b1edbc | 1696 | #define _USB_DOEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1697 | #define USB_DOEP_INT_NAKINTRPT_DEFAULT (_USB_DOEP_INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1698 | #define USB_DOEP_INT_STUPPKTRCVD (0x1UL << 15) /**< Setup Packet Received */ |
| AnnaBridge | 171:3a7713b1edbc | 1699 | #define _USB_DOEP_INT_STUPPKTRCVD_SHIFT 15 /**< Shift value for USB_STUPPKTRCVD */ |
| AnnaBridge | 171:3a7713b1edbc | 1700 | #define _USB_DOEP_INT_STUPPKTRCVD_MASK 0x8000UL /**< Bit mask for USB_STUPPKTRCVD */ |
| AnnaBridge | 171:3a7713b1edbc | 1701 | #define _USB_DOEP_INT_STUPPKTRCVD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1702 | #define USB_DOEP_INT_STUPPKTRCVD_DEFAULT (_USB_DOEP_INT_STUPPKTRCVD_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP_INT */ |
| AnnaBridge | 171:3a7713b1edbc | 1703 | |
| AnnaBridge | 171:3a7713b1edbc | 1704 | /* Bit fields for USB DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1705 | #define _USB_DOEP_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1706 | #define _USB_DOEP_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1707 | #define _USB_DOEP_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1708 | #define _USB_DOEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 1709 | #define _USB_DOEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1710 | #define USB_DOEP_TSIZ_XFERSIZE_DEFAULT (_USB_DOEP_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1711 | #define _USB_DOEP_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1712 | #define _USB_DOEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1713 | #define _USB_DOEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1714 | #define USB_DOEP_TSIZ_PKTCNT_DEFAULT (_USB_DOEP_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1715 | #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_SHIFT 29 /**< Shift value for USB_RXDPIDSUPCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1716 | #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MASK 0x60000000UL /**< Bit mask for USB_RXDPIDSUPCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 1717 | #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1718 | #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 0x00000000UL /**< Mode DATA0 for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1719 | #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 0x00000001UL /**< Mode DATA2 for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1720 | #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 0x00000002UL /**< Mode DATA1 for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1721 | #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA 0x00000003UL /**< Mode MDATA for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1722 | #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1723 | #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 << 29) /**< Shifted mode DATA0 for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1724 | #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 << 29) /**< Shifted mode DATA2 for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1725 | #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 << 29) /**< Shifted mode DATA1 for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1726 | #define USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA (_USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA << 29) /**< Shifted mode MDATA for USB_DOEP_TSIZ */ |
| AnnaBridge | 171:3a7713b1edbc | 1727 | |
| AnnaBridge | 171:3a7713b1edbc | 1728 | /* Bit fields for USB DOEP_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1729 | #define _USB_DOEP_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1730 | #define _USB_DOEP_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DOEP_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1731 | #define _USB_DOEP_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1732 | #define _USB_DOEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1733 | #define _USB_DOEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1734 | #define USB_DOEP_DMAADDR_DMAADDR_DEFAULT (_USB_DOEP_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_DMAADDR */ |
| AnnaBridge | 171:3a7713b1edbc | 1735 | |
| AnnaBridge | 171:3a7713b1edbc | 1736 | /* Bit fields for USB PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1737 | #define _USB_PCGCCTL_RESETVALUE 0x00000000UL /**< Default value for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1738 | #define _USB_PCGCCTL_MASK 0x0000004FUL /**< Mask for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1739 | #define USB_PCGCCTL_STOPPCLK (0x1UL << 0) /**< Stop PHY clock */ |
| AnnaBridge | 171:3a7713b1edbc | 1740 | #define _USB_PCGCCTL_STOPPCLK_SHIFT 0 /**< Shift value for USB_STOPPCLK */ |
| AnnaBridge | 171:3a7713b1edbc | 1741 | #define _USB_PCGCCTL_STOPPCLK_MASK 0x1UL /**< Bit mask for USB_STOPPCLK */ |
| AnnaBridge | 171:3a7713b1edbc | 1742 | #define _USB_PCGCCTL_STOPPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1743 | #define USB_PCGCCTL_STOPPCLK_DEFAULT (_USB_PCGCCTL_STOPPCLK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1744 | #define USB_PCGCCTL_GATEHCLK (0x1UL << 1) /**< Gate HCLK */ |
| AnnaBridge | 171:3a7713b1edbc | 1745 | #define _USB_PCGCCTL_GATEHCLK_SHIFT 1 /**< Shift value for USB_GATEHCLK */ |
| AnnaBridge | 171:3a7713b1edbc | 1746 | #define _USB_PCGCCTL_GATEHCLK_MASK 0x2UL /**< Bit mask for USB_GATEHCLK */ |
| AnnaBridge | 171:3a7713b1edbc | 1747 | #define _USB_PCGCCTL_GATEHCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1748 | #define USB_PCGCCTL_GATEHCLK_DEFAULT (_USB_PCGCCTL_GATEHCLK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1749 | #define USB_PCGCCTL_PWRCLMP (0x1UL << 2) /**< Power Clamp */ |
| AnnaBridge | 171:3a7713b1edbc | 1750 | #define _USB_PCGCCTL_PWRCLMP_SHIFT 2 /**< Shift value for USB_PWRCLMP */ |
| AnnaBridge | 171:3a7713b1edbc | 1751 | #define _USB_PCGCCTL_PWRCLMP_MASK 0x4UL /**< Bit mask for USB_PWRCLMP */ |
| AnnaBridge | 171:3a7713b1edbc | 1752 | #define _USB_PCGCCTL_PWRCLMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1753 | #define USB_PCGCCTL_PWRCLMP_DEFAULT (_USB_PCGCCTL_PWRCLMP_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1754 | #define USB_PCGCCTL_RSTPDWNMODULE (0x1UL << 3) /**< Reset Power-Down Modules */ |
| AnnaBridge | 171:3a7713b1edbc | 1755 | #define _USB_PCGCCTL_RSTPDWNMODULE_SHIFT 3 /**< Shift value for USB_RSTPDWNMODULE */ |
| AnnaBridge | 171:3a7713b1edbc | 1756 | #define _USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8UL /**< Bit mask for USB_RSTPDWNMODULE */ |
| AnnaBridge | 171:3a7713b1edbc | 1757 | #define _USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1758 | #define USB_PCGCCTL_RSTPDWNMODULE_DEFAULT (_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1759 | #define USB_PCGCCTL_PHYSLEEP (0x1UL << 6) /**< PHY In Sleep */ |
| AnnaBridge | 171:3a7713b1edbc | 1760 | #define _USB_PCGCCTL_PHYSLEEP_SHIFT 6 /**< Shift value for USB_PHYSLEEP */ |
| AnnaBridge | 171:3a7713b1edbc | 1761 | #define _USB_PCGCCTL_PHYSLEEP_MASK 0x40UL /**< Bit mask for USB_PHYSLEEP */ |
| AnnaBridge | 171:3a7713b1edbc | 1762 | #define _USB_PCGCCTL_PHYSLEEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1763 | #define USB_PCGCCTL_PHYSLEEP_DEFAULT (_USB_PCGCCTL_PHYSLEEP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_PCGCCTL */ |
| AnnaBridge | 171:3a7713b1edbc | 1764 | |
| AnnaBridge | 171:3a7713b1edbc | 1765 | /* Bit fields for USB FIFO0D */ |
| AnnaBridge | 171:3a7713b1edbc | 1766 | #define _USB_FIFO0D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO0D */ |
| AnnaBridge | 171:3a7713b1edbc | 1767 | #define _USB_FIFO0D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO0D */ |
| AnnaBridge | 171:3a7713b1edbc | 1768 | #define _USB_FIFO0D_FIFO0D_SHIFT 0 /**< Shift value for USB_FIFO0D */ |
| AnnaBridge | 171:3a7713b1edbc | 1769 | #define _USB_FIFO0D_FIFO0D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO0D */ |
| AnnaBridge | 171:3a7713b1edbc | 1770 | #define _USB_FIFO0D_FIFO0D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO0D */ |
| AnnaBridge | 171:3a7713b1edbc | 1771 | #define USB_FIFO0D_FIFO0D_DEFAULT (_USB_FIFO0D_FIFO0D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO0D */ |
| AnnaBridge | 171:3a7713b1edbc | 1772 | |
| AnnaBridge | 171:3a7713b1edbc | 1773 | /* Bit fields for USB FIFO1D */ |
| AnnaBridge | 171:3a7713b1edbc | 1774 | #define _USB_FIFO1D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO1D */ |
| AnnaBridge | 171:3a7713b1edbc | 1775 | #define _USB_FIFO1D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO1D */ |
| AnnaBridge | 171:3a7713b1edbc | 1776 | #define _USB_FIFO1D_FIFO1D_SHIFT 0 /**< Shift value for USB_FIFO1D */ |
| AnnaBridge | 171:3a7713b1edbc | 1777 | #define _USB_FIFO1D_FIFO1D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO1D */ |
| AnnaBridge | 171:3a7713b1edbc | 1778 | #define _USB_FIFO1D_FIFO1D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO1D */ |
| AnnaBridge | 171:3a7713b1edbc | 1779 | #define USB_FIFO1D_FIFO1D_DEFAULT (_USB_FIFO1D_FIFO1D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO1D */ |
| AnnaBridge | 171:3a7713b1edbc | 1780 | |
| AnnaBridge | 171:3a7713b1edbc | 1781 | /* Bit fields for USB FIFO2D */ |
| AnnaBridge | 171:3a7713b1edbc | 1782 | #define _USB_FIFO2D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO2D */ |
| AnnaBridge | 171:3a7713b1edbc | 1783 | #define _USB_FIFO2D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO2D */ |
| AnnaBridge | 171:3a7713b1edbc | 1784 | #define _USB_FIFO2D_FIFO2D_SHIFT 0 /**< Shift value for USB_FIFO2D */ |
| AnnaBridge | 171:3a7713b1edbc | 1785 | #define _USB_FIFO2D_FIFO2D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO2D */ |
| AnnaBridge | 171:3a7713b1edbc | 1786 | #define _USB_FIFO2D_FIFO2D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO2D */ |
| AnnaBridge | 171:3a7713b1edbc | 1787 | #define USB_FIFO2D_FIFO2D_DEFAULT (_USB_FIFO2D_FIFO2D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO2D */ |
| AnnaBridge | 171:3a7713b1edbc | 1788 | |
| AnnaBridge | 171:3a7713b1edbc | 1789 | /* Bit fields for USB FIFO3D */ |
| AnnaBridge | 171:3a7713b1edbc | 1790 | #define _USB_FIFO3D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO3D */ |
| AnnaBridge | 171:3a7713b1edbc | 1791 | #define _USB_FIFO3D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO3D */ |
| AnnaBridge | 171:3a7713b1edbc | 1792 | #define _USB_FIFO3D_FIFO3D_SHIFT 0 /**< Shift value for USB_FIFO3D */ |
| AnnaBridge | 171:3a7713b1edbc | 1793 | #define _USB_FIFO3D_FIFO3D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO3D */ |
| AnnaBridge | 171:3a7713b1edbc | 1794 | #define _USB_FIFO3D_FIFO3D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO3D */ |
| AnnaBridge | 171:3a7713b1edbc | 1795 | #define USB_FIFO3D_FIFO3D_DEFAULT (_USB_FIFO3D_FIFO3D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO3D */ |
| AnnaBridge | 171:3a7713b1edbc | 1796 | |
| AnnaBridge | 171:3a7713b1edbc | 1797 | /* Bit fields for USB FIFORAM */ |
| AnnaBridge | 171:3a7713b1edbc | 1798 | #define _USB_FIFORAM_RESETVALUE 0x00000000UL /**< Default value for USB_FIFORAM */ |
| AnnaBridge | 171:3a7713b1edbc | 1799 | #define _USB_FIFORAM_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFORAM */ |
| AnnaBridge | 171:3a7713b1edbc | 1800 | #define _USB_FIFORAM_FIFORAM_SHIFT 0 /**< Shift value for USB_FIFORAM */ |
| AnnaBridge | 171:3a7713b1edbc | 1801 | #define _USB_FIFORAM_FIFORAM_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFORAM */ |
| AnnaBridge | 171:3a7713b1edbc | 1802 | #define _USB_FIFORAM_FIFORAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFORAM */ |
| AnnaBridge | 171:3a7713b1edbc | 1803 | #define USB_FIFORAM_FIFORAM_DEFAULT (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */ |
| AnnaBridge | 171:3a7713b1edbc | 1804 | |
| AnnaBridge | 171:3a7713b1edbc | 1805 | /** @} End of group EFM32HG_USB */ |
| AnnaBridge | 171:3a7713b1edbc | 1806 | /** @} End of group Parts */ |
| AnnaBridge | 171:3a7713b1edbc | 1807 |
