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TARGET_EFM32GG_STK3700/TOOLCHAIN_GCC_ARM/efm32gg_adc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32gg_adc.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32GG_ADC register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32GG_ADC
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32GG_ADC Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IOM uint32_t CTRL; /**< Control Register */
AnnaBridge 171:3a7713b1edbc 44 __IOM uint32_t CMD; /**< Command Register */
AnnaBridge 171:3a7713b1edbc 45 __IM uint32_t STATUS; /**< Status Register */
AnnaBridge 171:3a7713b1edbc 46 __IOM uint32_t SINGLECTRL; /**< Single Sample Control Register */
AnnaBridge 171:3a7713b1edbc 47 __IOM uint32_t SCANCTRL; /**< Scan Control Register */
AnnaBridge 171:3a7713b1edbc 48 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 49 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 50 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 51 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 52 __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */
AnnaBridge 171:3a7713b1edbc 53 __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */
AnnaBridge 171:3a7713b1edbc 54 __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
AnnaBridge 171:3a7713b1edbc 55 __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
AnnaBridge 171:3a7713b1edbc 56 __IOM uint32_t CAL; /**< Calibration Register */
AnnaBridge 171:3a7713b1edbc 57
AnnaBridge 171:3a7713b1edbc 58 uint32_t RESERVED0[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 59 __IOM uint32_t BIASPROG; /**< Bias Programming Register */
AnnaBridge 171:3a7713b1edbc 60 } ADC_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 63 * @defgroup EFM32GG_ADC_BitFields
AnnaBridge 171:3a7713b1edbc 64 * @{
AnnaBridge 171:3a7713b1edbc 65 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /* Bit fields for ADC CTRL */
AnnaBridge 171:3a7713b1edbc 68 #define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 69 #define _ADC_CTRL_MASK 0x0F1F7F3BUL /**< Mask for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 70 #define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */
AnnaBridge 171:3a7713b1edbc 71 #define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */
AnnaBridge 171:3a7713b1edbc 72 #define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 73 #define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 74 #define _ADC_CTRL_WARMUPMODE_FASTBG 0x00000001UL /**< Mode FASTBG for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 75 #define _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 0x00000002UL /**< Mode KEEPSCANREFWARM for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 76 #define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 77 #define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 78 #define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 79 #define ADC_CTRL_WARMUPMODE_FASTBG (_ADC_CTRL_WARMUPMODE_FASTBG << 0) /**< Shifted mode FASTBG for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 80 #define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0) /**< Shifted mode KEEPSCANREFWARM for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 81 #define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 82 #define ADC_CTRL_TAILGATE (0x1UL << 3) /**< Conversion Tailgating */
AnnaBridge 171:3a7713b1edbc 83 #define _ADC_CTRL_TAILGATE_SHIFT 3 /**< Shift value for ADC_TAILGATE */
AnnaBridge 171:3a7713b1edbc 84 #define _ADC_CTRL_TAILGATE_MASK 0x8UL /**< Bit mask for ADC_TAILGATE */
AnnaBridge 171:3a7713b1edbc 85 #define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 86 #define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 87 #define _ADC_CTRL_LPFMODE_SHIFT 4 /**< Shift value for ADC_LPFMODE */
AnnaBridge 171:3a7713b1edbc 88 #define _ADC_CTRL_LPFMODE_MASK 0x30UL /**< Bit mask for ADC_LPFMODE */
AnnaBridge 171:3a7713b1edbc 89 #define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 90 #define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL /**< Mode BYPASS for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 91 #define _ADC_CTRL_LPFMODE_DECAP 0x00000001UL /**< Mode DECAP for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 92 #define _ADC_CTRL_LPFMODE_RCFILT 0x00000002UL /**< Mode RCFILT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 93 #define ADC_CTRL_LPFMODE_DEFAULT (_ADC_CTRL_LPFMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 94 #define ADC_CTRL_LPFMODE_BYPASS (_ADC_CTRL_LPFMODE_BYPASS << 4) /**< Shifted mode BYPASS for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 95 #define ADC_CTRL_LPFMODE_DECAP (_ADC_CTRL_LPFMODE_DECAP << 4) /**< Shifted mode DECAP for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 96 #define ADC_CTRL_LPFMODE_RCFILT (_ADC_CTRL_LPFMODE_RCFILT << 4) /**< Shifted mode RCFILT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 97 #define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */
AnnaBridge 171:3a7713b1edbc 98 #define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */
AnnaBridge 171:3a7713b1edbc 99 #define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 100 #define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 101 #define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 102 #define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 103 #define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 104 #define _ADC_CTRL_TIMEBASE_MASK 0x1F0000UL /**< Bit mask for ADC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 105 #define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 106 #define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 107 #define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */
AnnaBridge 171:3a7713b1edbc 108 #define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */
AnnaBridge 171:3a7713b1edbc 109 #define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 110 #define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 111 #define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 112 #define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 113 #define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 114 #define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 115 #define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 116 #define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 117 #define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 118 #define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 119 #define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 120 #define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 121 #define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 122 #define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 123 #define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 124 #define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 125 #define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 126 #define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 127 #define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 128 #define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 129 #define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 130 #define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 131 #define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 132 #define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 133 #define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 134 #define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136 /* Bit fields for ADC CMD */
AnnaBridge 171:3a7713b1edbc 137 #define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */
AnnaBridge 171:3a7713b1edbc 138 #define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */
AnnaBridge 171:3a7713b1edbc 139 #define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Conversion Start */
AnnaBridge 171:3a7713b1edbc 140 #define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */
AnnaBridge 171:3a7713b1edbc 141 #define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */
AnnaBridge 171:3a7713b1edbc 142 #define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
AnnaBridge 171:3a7713b1edbc 143 #define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */
AnnaBridge 171:3a7713b1edbc 144 #define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Conversion Stop */
AnnaBridge 171:3a7713b1edbc 145 #define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */
AnnaBridge 171:3a7713b1edbc 146 #define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */
AnnaBridge 171:3a7713b1edbc 147 #define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
AnnaBridge 171:3a7713b1edbc 148 #define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */
AnnaBridge 171:3a7713b1edbc 149 #define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */
AnnaBridge 171:3a7713b1edbc 150 #define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */
AnnaBridge 171:3a7713b1edbc 151 #define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */
AnnaBridge 171:3a7713b1edbc 152 #define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
AnnaBridge 171:3a7713b1edbc 153 #define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */
AnnaBridge 171:3a7713b1edbc 154 #define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */
AnnaBridge 171:3a7713b1edbc 155 #define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */
AnnaBridge 171:3a7713b1edbc 156 #define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */
AnnaBridge 171:3a7713b1edbc 157 #define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
AnnaBridge 171:3a7713b1edbc 158 #define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /* Bit fields for ADC STATUS */
AnnaBridge 171:3a7713b1edbc 161 #define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 162 #define _ADC_STATUS_MASK 0x07031303UL /**< Mask for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 163 #define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Conversion Active */
AnnaBridge 171:3a7713b1edbc 164 #define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */
AnnaBridge 171:3a7713b1edbc 165 #define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */
AnnaBridge 171:3a7713b1edbc 166 #define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 167 #define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 168 #define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */
AnnaBridge 171:3a7713b1edbc 169 #define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */
AnnaBridge 171:3a7713b1edbc 170 #define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */
AnnaBridge 171:3a7713b1edbc 171 #define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 172 #define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 173 #define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Reference Warmed Up */
AnnaBridge 171:3a7713b1edbc 174 #define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */
AnnaBridge 171:3a7713b1edbc 175 #define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */
AnnaBridge 171:3a7713b1edbc 176 #define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 177 #define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 178 #define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */
AnnaBridge 171:3a7713b1edbc 179 #define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */
AnnaBridge 171:3a7713b1edbc 180 #define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */
AnnaBridge 171:3a7713b1edbc 181 #define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 182 #define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 183 #define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */
AnnaBridge 171:3a7713b1edbc 184 #define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */
AnnaBridge 171:3a7713b1edbc 185 #define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */
AnnaBridge 171:3a7713b1edbc 186 #define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 187 #define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 188 #define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Sample Data Valid */
AnnaBridge 171:3a7713b1edbc 189 #define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */
AnnaBridge 171:3a7713b1edbc 190 #define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */
AnnaBridge 171:3a7713b1edbc 191 #define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 192 #define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 193 #define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */
AnnaBridge 171:3a7713b1edbc 194 #define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */
AnnaBridge 171:3a7713b1edbc 195 #define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */
AnnaBridge 171:3a7713b1edbc 196 #define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 197 #define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 198 #define _ADC_STATUS_SCANDATASRC_SHIFT 24 /**< Shift value for ADC_SCANDATASRC */
AnnaBridge 171:3a7713b1edbc 199 #define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL /**< Bit mask for ADC_SCANDATASRC */
AnnaBridge 171:3a7713b1edbc 200 #define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 201 #define _ADC_STATUS_SCANDATASRC_CH0 0x00000000UL /**< Mode CH0 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 202 #define _ADC_STATUS_SCANDATASRC_CH1 0x00000001UL /**< Mode CH1 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 203 #define _ADC_STATUS_SCANDATASRC_CH2 0x00000002UL /**< Mode CH2 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 204 #define _ADC_STATUS_SCANDATASRC_CH3 0x00000003UL /**< Mode CH3 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 205 #define _ADC_STATUS_SCANDATASRC_CH4 0x00000004UL /**< Mode CH4 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 206 #define _ADC_STATUS_SCANDATASRC_CH5 0x00000005UL /**< Mode CH5 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 207 #define _ADC_STATUS_SCANDATASRC_CH6 0x00000006UL /**< Mode CH6 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 208 #define _ADC_STATUS_SCANDATASRC_CH7 0x00000007UL /**< Mode CH7 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 209 #define ADC_STATUS_SCANDATASRC_DEFAULT (_ADC_STATUS_SCANDATASRC_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 210 #define ADC_STATUS_SCANDATASRC_CH0 (_ADC_STATUS_SCANDATASRC_CH0 << 24) /**< Shifted mode CH0 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 211 #define ADC_STATUS_SCANDATASRC_CH1 (_ADC_STATUS_SCANDATASRC_CH1 << 24) /**< Shifted mode CH1 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 212 #define ADC_STATUS_SCANDATASRC_CH2 (_ADC_STATUS_SCANDATASRC_CH2 << 24) /**< Shifted mode CH2 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 213 #define ADC_STATUS_SCANDATASRC_CH3 (_ADC_STATUS_SCANDATASRC_CH3 << 24) /**< Shifted mode CH3 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 214 #define ADC_STATUS_SCANDATASRC_CH4 (_ADC_STATUS_SCANDATASRC_CH4 << 24) /**< Shifted mode CH4 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 215 #define ADC_STATUS_SCANDATASRC_CH5 (_ADC_STATUS_SCANDATASRC_CH5 << 24) /**< Shifted mode CH5 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 216 #define ADC_STATUS_SCANDATASRC_CH6 (_ADC_STATUS_SCANDATASRC_CH6 << 24) /**< Shifted mode CH6 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 217 #define ADC_STATUS_SCANDATASRC_CH7 (_ADC_STATUS_SCANDATASRC_CH7 << 24) /**< Shifted mode CH7 for ADC_STATUS */
AnnaBridge 171:3a7713b1edbc 218
AnnaBridge 171:3a7713b1edbc 219 /* Bit fields for ADC SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 220 #define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 221 #define _ADC_SINGLECTRL_MASK 0xF1F70F37UL /**< Mask for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 222 #define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Sample Repetitive Mode */
AnnaBridge 171:3a7713b1edbc 223 #define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
AnnaBridge 171:3a7713b1edbc 224 #define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
AnnaBridge 171:3a7713b1edbc 225 #define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 226 #define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 227 #define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Sample Differential Mode */
AnnaBridge 171:3a7713b1edbc 228 #define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
AnnaBridge 171:3a7713b1edbc 229 #define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
AnnaBridge 171:3a7713b1edbc 230 #define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 231 #define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 232 #define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Sample Result Adjustment */
AnnaBridge 171:3a7713b1edbc 233 #define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
AnnaBridge 171:3a7713b1edbc 234 #define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
AnnaBridge 171:3a7713b1edbc 235 #define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 236 #define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 237 #define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 238 #define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 239 #define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 240 #define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 241 #define _ADC_SINGLECTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */
AnnaBridge 171:3a7713b1edbc 242 #define _ADC_SINGLECTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */
AnnaBridge 171:3a7713b1edbc 243 #define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 244 #define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 245 #define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 246 #define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 247 #define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 248 #define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 249 #define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 250 #define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 251 #define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 252 #define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 253 #define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 /**< Shift value for ADC_INPUTSEL */
AnnaBridge 171:3a7713b1edbc 254 #define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL /**< Bit mask for ADC_INPUTSEL */
AnnaBridge 171:3a7713b1edbc 255 #define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 256 #define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 257 #define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL /**< Mode CH0CH1 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 258 #define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 259 #define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL /**< Mode CH2CH3 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 260 #define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 261 #define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL /**< Mode CH4CH5 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 262 #define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL /**< Mode CH6CH7 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 263 #define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL /**< Mode CH3 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 264 #define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 265 #define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL /**< Mode DIFF0 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 266 #define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL /**< Mode CH5 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 267 #define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL /**< Mode CH6 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 268 #define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL /**< Mode CH7 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 269 #define _ADC_SINGLECTRL_INPUTSEL_TEMP 0x00000008UL /**< Mode TEMP for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 270 #define _ADC_SINGLECTRL_INPUTSEL_VDDDIV3 0x00000009UL /**< Mode VDDDIV3 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 271 #define _ADC_SINGLECTRL_INPUTSEL_VDD 0x0000000AUL /**< Mode VDD for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 272 #define _ADC_SINGLECTRL_INPUTSEL_VSS 0x0000000BUL /**< Mode VSS for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 273 #define _ADC_SINGLECTRL_INPUTSEL_VREFDIV2 0x0000000CUL /**< Mode VREFDIV2 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 274 #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 275 #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 276 #define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 277 #define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 278 #define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 279 #define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 280 #define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 281 #define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 282 #define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 283 #define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 284 #define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) /**< Shifted mode CH3 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 285 #define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 286 #define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) /**< Shifted mode DIFF0 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 287 #define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) /**< Shifted mode CH5 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 288 #define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) /**< Shifted mode CH6 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 289 #define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) /**< Shifted mode CH7 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 290 #define ADC_SINGLECTRL_INPUTSEL_TEMP (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 291 #define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8) /**< Shifted mode VDDDIV3 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 292 #define ADC_SINGLECTRL_INPUTSEL_VDD (_ADC_SINGLECTRL_INPUTSEL_VDD << 8) /**< Shifted mode VDD for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 293 #define ADC_SINGLECTRL_INPUTSEL_VSS (_ADC_SINGLECTRL_INPUTSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 294 #define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8) /**< Shifted mode VREFDIV2 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 295 #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 296 #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 297 #define _ADC_SINGLECTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */
AnnaBridge 171:3a7713b1edbc 298 #define _ADC_SINGLECTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */
AnnaBridge 171:3a7713b1edbc 299 #define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 300 #define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 301 #define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 302 #define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 303 #define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 304 #define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 305 #define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 306 #define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 307 #define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 308 #define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 309 #define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 310 #define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 311 #define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 312 #define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 313 #define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 314 #define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 315 #define _ADC_SINGLECTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */
AnnaBridge 171:3a7713b1edbc 316 #define _ADC_SINGLECTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */
AnnaBridge 171:3a7713b1edbc 317 #define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 318 #define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 319 #define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 320 #define _ADC_SINGLECTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 321 #define _ADC_SINGLECTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 322 #define _ADC_SINGLECTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 323 #define _ADC_SINGLECTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 324 #define _ADC_SINGLECTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 325 #define _ADC_SINGLECTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 326 #define _ADC_SINGLECTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 327 #define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 328 #define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 329 #define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 330 #define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 331 #define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 332 #define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 333 #define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 334 #define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 335 #define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 336 #define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 337 #define ADC_SINGLECTRL_PRSEN (0x1UL << 24) /**< Single Sample PRS Trigger Enable */
AnnaBridge 171:3a7713b1edbc 338 #define _ADC_SINGLECTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */
AnnaBridge 171:3a7713b1edbc 339 #define _ADC_SINGLECTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */
AnnaBridge 171:3a7713b1edbc 340 #define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 341 #define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 342 #define _ADC_SINGLECTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */
AnnaBridge 171:3a7713b1edbc 343 #define _ADC_SINGLECTRL_PRSSEL_MASK 0xF0000000UL /**< Bit mask for ADC_PRSSEL */
AnnaBridge 171:3a7713b1edbc 344 #define _ADC_SINGLECTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 345 #define _ADC_SINGLECTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 346 #define _ADC_SINGLECTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 347 #define _ADC_SINGLECTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 348 #define _ADC_SINGLECTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 349 #define _ADC_SINGLECTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 350 #define _ADC_SINGLECTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 351 #define _ADC_SINGLECTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 352 #define _ADC_SINGLECTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 353 #define _ADC_SINGLECTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 354 #define _ADC_SINGLECTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 355 #define _ADC_SINGLECTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 356 #define _ADC_SINGLECTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 357 #define ADC_SINGLECTRL_PRSSEL_DEFAULT (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 358 #define ADC_SINGLECTRL_PRSSEL_PRSCH0 (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 359 #define ADC_SINGLECTRL_PRSSEL_PRSCH1 (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 360 #define ADC_SINGLECTRL_PRSSEL_PRSCH2 (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 361 #define ADC_SINGLECTRL_PRSSEL_PRSCH3 (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 362 #define ADC_SINGLECTRL_PRSSEL_PRSCH4 (_ADC_SINGLECTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 363 #define ADC_SINGLECTRL_PRSSEL_PRSCH5 (_ADC_SINGLECTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 364 #define ADC_SINGLECTRL_PRSSEL_PRSCH6 (_ADC_SINGLECTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 365 #define ADC_SINGLECTRL_PRSSEL_PRSCH7 (_ADC_SINGLECTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 366 #define ADC_SINGLECTRL_PRSSEL_PRSCH8 (_ADC_SINGLECTRL_PRSSEL_PRSCH8 << 28) /**< Shifted mode PRSCH8 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 367 #define ADC_SINGLECTRL_PRSSEL_PRSCH9 (_ADC_SINGLECTRL_PRSSEL_PRSCH9 << 28) /**< Shifted mode PRSCH9 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 368 #define ADC_SINGLECTRL_PRSSEL_PRSCH10 (_ADC_SINGLECTRL_PRSSEL_PRSCH10 << 28) /**< Shifted mode PRSCH10 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 369 #define ADC_SINGLECTRL_PRSSEL_PRSCH11 (_ADC_SINGLECTRL_PRSSEL_PRSCH11 << 28) /**< Shifted mode PRSCH11 for ADC_SINGLECTRL */
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 /* Bit fields for ADC SCANCTRL */
AnnaBridge 171:3a7713b1edbc 372 #define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 373 #define _ADC_SCANCTRL_MASK 0xF1F7FF37UL /**< Mask for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 374 #define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */
AnnaBridge 171:3a7713b1edbc 375 #define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
AnnaBridge 171:3a7713b1edbc 376 #define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
AnnaBridge 171:3a7713b1edbc 377 #define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 378 #define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 379 #define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */
AnnaBridge 171:3a7713b1edbc 380 #define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
AnnaBridge 171:3a7713b1edbc 381 #define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
AnnaBridge 171:3a7713b1edbc 382 #define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 383 #define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 384 #define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */
AnnaBridge 171:3a7713b1edbc 385 #define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
AnnaBridge 171:3a7713b1edbc 386 #define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
AnnaBridge 171:3a7713b1edbc 387 #define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 388 #define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 389 #define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 390 #define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 391 #define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 392 #define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 393 #define _ADC_SCANCTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */
AnnaBridge 171:3a7713b1edbc 394 #define _ADC_SCANCTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */
AnnaBridge 171:3a7713b1edbc 395 #define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 396 #define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 397 #define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 398 #define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 399 #define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 400 #define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 401 #define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 402 #define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 403 #define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 404 #define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 405 #define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 /**< Shift value for ADC_INPUTMASK */
AnnaBridge 171:3a7713b1edbc 406 #define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL /**< Bit mask for ADC_INPUTMASK */
AnnaBridge 171:3a7713b1edbc 407 #define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 408 #define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 409 #define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL /**< Mode CH0CH1 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 410 #define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 411 #define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL /**< Mode CH2CH3 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 412 #define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 413 #define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL /**< Mode CH4CH5 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 414 #define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL /**< Mode CH6CH7 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 415 #define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL /**< Mode CH3 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 416 #define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL /**< Mode CH4 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 417 #define _ADC_SCANCTRL_INPUTMASK_CH5 0x00000020UL /**< Mode CH5 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 418 #define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL /**< Mode CH6 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 419 #define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL /**< Mode CH7 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 420 #define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 421 #define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 422 #define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 423 #define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 424 #define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 425 #define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 426 #define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 427 #define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 428 #define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) /**< Shifted mode CH3 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 429 #define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) /**< Shifted mode CH4 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 430 #define ADC_SCANCTRL_INPUTMASK_CH5 (_ADC_SCANCTRL_INPUTMASK_CH5 << 8) /**< Shifted mode CH5 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 431 #define ADC_SCANCTRL_INPUTMASK_CH6 (_ADC_SCANCTRL_INPUTMASK_CH6 << 8) /**< Shifted mode CH6 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 432 #define ADC_SCANCTRL_INPUTMASK_CH7 (_ADC_SCANCTRL_INPUTMASK_CH7 << 8) /**< Shifted mode CH7 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 433 #define _ADC_SCANCTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */
AnnaBridge 171:3a7713b1edbc 434 #define _ADC_SCANCTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */
AnnaBridge 171:3a7713b1edbc 435 #define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 436 #define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 437 #define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 438 #define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 439 #define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 440 #define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 441 #define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 442 #define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 443 #define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 444 #define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 445 #define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 446 #define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 447 #define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 448 #define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 449 #define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 450 #define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 451 #define _ADC_SCANCTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */
AnnaBridge 171:3a7713b1edbc 452 #define _ADC_SCANCTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */
AnnaBridge 171:3a7713b1edbc 453 #define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 454 #define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 455 #define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 456 #define _ADC_SCANCTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 457 #define _ADC_SCANCTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 458 #define _ADC_SCANCTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 459 #define _ADC_SCANCTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 460 #define _ADC_SCANCTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 461 #define _ADC_SCANCTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 462 #define _ADC_SCANCTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 463 #define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 464 #define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 465 #define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 466 #define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 467 #define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 468 #define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 469 #define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 470 #define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 471 #define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 472 #define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 473 #define ADC_SCANCTRL_PRSEN (0x1UL << 24) /**< Scan Sequence PRS Trigger Enable */
AnnaBridge 171:3a7713b1edbc 474 #define _ADC_SCANCTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */
AnnaBridge 171:3a7713b1edbc 475 #define _ADC_SCANCTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */
AnnaBridge 171:3a7713b1edbc 476 #define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 477 #define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 478 #define _ADC_SCANCTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */
AnnaBridge 171:3a7713b1edbc 479 #define _ADC_SCANCTRL_PRSSEL_MASK 0xF0000000UL /**< Bit mask for ADC_PRSSEL */
AnnaBridge 171:3a7713b1edbc 480 #define _ADC_SCANCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 481 #define _ADC_SCANCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 482 #define _ADC_SCANCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 483 #define _ADC_SCANCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 484 #define _ADC_SCANCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 485 #define _ADC_SCANCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 486 #define _ADC_SCANCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 487 #define _ADC_SCANCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 488 #define _ADC_SCANCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 489 #define _ADC_SCANCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 490 #define _ADC_SCANCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 491 #define _ADC_SCANCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 492 #define _ADC_SCANCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 493 #define ADC_SCANCTRL_PRSSEL_DEFAULT (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 494 #define ADC_SCANCTRL_PRSSEL_PRSCH0 (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 495 #define ADC_SCANCTRL_PRSSEL_PRSCH1 (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 496 #define ADC_SCANCTRL_PRSSEL_PRSCH2 (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 497 #define ADC_SCANCTRL_PRSSEL_PRSCH3 (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 498 #define ADC_SCANCTRL_PRSSEL_PRSCH4 (_ADC_SCANCTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 499 #define ADC_SCANCTRL_PRSSEL_PRSCH5 (_ADC_SCANCTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 500 #define ADC_SCANCTRL_PRSSEL_PRSCH6 (_ADC_SCANCTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 501 #define ADC_SCANCTRL_PRSSEL_PRSCH7 (_ADC_SCANCTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 502 #define ADC_SCANCTRL_PRSSEL_PRSCH8 (_ADC_SCANCTRL_PRSSEL_PRSCH8 << 28) /**< Shifted mode PRSCH8 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 503 #define ADC_SCANCTRL_PRSSEL_PRSCH9 (_ADC_SCANCTRL_PRSSEL_PRSCH9 << 28) /**< Shifted mode PRSCH9 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 504 #define ADC_SCANCTRL_PRSSEL_PRSCH10 (_ADC_SCANCTRL_PRSSEL_PRSCH10 << 28) /**< Shifted mode PRSCH10 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 505 #define ADC_SCANCTRL_PRSSEL_PRSCH11 (_ADC_SCANCTRL_PRSSEL_PRSCH11 << 28) /**< Shifted mode PRSCH11 for ADC_SCANCTRL */
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507 /* Bit fields for ADC IEN */
AnnaBridge 171:3a7713b1edbc 508 #define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */
AnnaBridge 171:3a7713b1edbc 509 #define _ADC_IEN_MASK 0x00000303UL /**< Mask for ADC_IEN */
AnnaBridge 171:3a7713b1edbc 510 #define ADC_IEN_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 511 #define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
AnnaBridge 171:3a7713b1edbc 512 #define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
AnnaBridge 171:3a7713b1edbc 513 #define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
AnnaBridge 171:3a7713b1edbc 514 #define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */
AnnaBridge 171:3a7713b1edbc 515 #define ADC_IEN_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 516 #define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
AnnaBridge 171:3a7713b1edbc 517 #define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
AnnaBridge 171:3a7713b1edbc 518 #define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
AnnaBridge 171:3a7713b1edbc 519 #define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */
AnnaBridge 171:3a7713b1edbc 520 #define ADC_IEN_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 521 #define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
AnnaBridge 171:3a7713b1edbc 522 #define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
AnnaBridge 171:3a7713b1edbc 523 #define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
AnnaBridge 171:3a7713b1edbc 524 #define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */
AnnaBridge 171:3a7713b1edbc 525 #define ADC_IEN_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 526 #define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
AnnaBridge 171:3a7713b1edbc 527 #define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
AnnaBridge 171:3a7713b1edbc 528 #define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
AnnaBridge 171:3a7713b1edbc 529 #define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */
AnnaBridge 171:3a7713b1edbc 530
AnnaBridge 171:3a7713b1edbc 531 /* Bit fields for ADC IF */
AnnaBridge 171:3a7713b1edbc 532 #define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */
AnnaBridge 171:3a7713b1edbc 533 #define _ADC_IF_MASK 0x00000303UL /**< Mask for ADC_IF */
AnnaBridge 171:3a7713b1edbc 534 #define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 535 #define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
AnnaBridge 171:3a7713b1edbc 536 #define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
AnnaBridge 171:3a7713b1edbc 537 #define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
AnnaBridge 171:3a7713b1edbc 538 #define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */
AnnaBridge 171:3a7713b1edbc 539 #define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 540 #define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
AnnaBridge 171:3a7713b1edbc 541 #define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
AnnaBridge 171:3a7713b1edbc 542 #define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
AnnaBridge 171:3a7713b1edbc 543 #define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */
AnnaBridge 171:3a7713b1edbc 544 #define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 545 #define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
AnnaBridge 171:3a7713b1edbc 546 #define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
AnnaBridge 171:3a7713b1edbc 547 #define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
AnnaBridge 171:3a7713b1edbc 548 #define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */
AnnaBridge 171:3a7713b1edbc 549 #define ADC_IF_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 550 #define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
AnnaBridge 171:3a7713b1edbc 551 #define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
AnnaBridge 171:3a7713b1edbc 552 #define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
AnnaBridge 171:3a7713b1edbc 553 #define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */
AnnaBridge 171:3a7713b1edbc 554
AnnaBridge 171:3a7713b1edbc 555 /* Bit fields for ADC IFS */
AnnaBridge 171:3a7713b1edbc 556 #define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */
AnnaBridge 171:3a7713b1edbc 557 #define _ADC_IFS_MASK 0x00000303UL /**< Mask for ADC_IFS */
AnnaBridge 171:3a7713b1edbc 558 #define ADC_IFS_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 559 #define _ADC_IFS_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
AnnaBridge 171:3a7713b1edbc 560 #define _ADC_IFS_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
AnnaBridge 171:3a7713b1edbc 561 #define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
AnnaBridge 171:3a7713b1edbc 562 #define ADC_IFS_SINGLE_DEFAULT (_ADC_IFS_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFS */
AnnaBridge 171:3a7713b1edbc 563 #define ADC_IFS_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 564 #define _ADC_IFS_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
AnnaBridge 171:3a7713b1edbc 565 #define _ADC_IFS_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
AnnaBridge 171:3a7713b1edbc 566 #define _ADC_IFS_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
AnnaBridge 171:3a7713b1edbc 567 #define ADC_IFS_SCAN_DEFAULT (_ADC_IFS_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFS */
AnnaBridge 171:3a7713b1edbc 568 #define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 569 #define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
AnnaBridge 171:3a7713b1edbc 570 #define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
AnnaBridge 171:3a7713b1edbc 571 #define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
AnnaBridge 171:3a7713b1edbc 572 #define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */
AnnaBridge 171:3a7713b1edbc 573 #define ADC_IFS_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 574 #define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
AnnaBridge 171:3a7713b1edbc 575 #define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
AnnaBridge 171:3a7713b1edbc 576 #define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
AnnaBridge 171:3a7713b1edbc 577 #define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */
AnnaBridge 171:3a7713b1edbc 578
AnnaBridge 171:3a7713b1edbc 579 /* Bit fields for ADC IFC */
AnnaBridge 171:3a7713b1edbc 580 #define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */
AnnaBridge 171:3a7713b1edbc 581 #define _ADC_IFC_MASK 0x00000303UL /**< Mask for ADC_IFC */
AnnaBridge 171:3a7713b1edbc 582 #define ADC_IFC_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 583 #define _ADC_IFC_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
AnnaBridge 171:3a7713b1edbc 584 #define _ADC_IFC_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
AnnaBridge 171:3a7713b1edbc 585 #define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
AnnaBridge 171:3a7713b1edbc 586 #define ADC_IFC_SINGLE_DEFAULT (_ADC_IFC_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFC */
AnnaBridge 171:3a7713b1edbc 587 #define ADC_IFC_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 588 #define _ADC_IFC_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
AnnaBridge 171:3a7713b1edbc 589 #define _ADC_IFC_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
AnnaBridge 171:3a7713b1edbc 590 #define _ADC_IFC_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
AnnaBridge 171:3a7713b1edbc 591 #define ADC_IFC_SCAN_DEFAULT (_ADC_IFC_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFC */
AnnaBridge 171:3a7713b1edbc 592 #define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 593 #define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
AnnaBridge 171:3a7713b1edbc 594 #define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
AnnaBridge 171:3a7713b1edbc 595 #define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
AnnaBridge 171:3a7713b1edbc 596 #define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */
AnnaBridge 171:3a7713b1edbc 597 #define ADC_IFC_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 598 #define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
AnnaBridge 171:3a7713b1edbc 599 #define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
AnnaBridge 171:3a7713b1edbc 600 #define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
AnnaBridge 171:3a7713b1edbc 601 #define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */
AnnaBridge 171:3a7713b1edbc 602
AnnaBridge 171:3a7713b1edbc 603 /* Bit fields for ADC SINGLEDATA */
AnnaBridge 171:3a7713b1edbc 604 #define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */
AnnaBridge 171:3a7713b1edbc 605 #define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */
AnnaBridge 171:3a7713b1edbc 606 #define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
AnnaBridge 171:3a7713b1edbc 607 #define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
AnnaBridge 171:3a7713b1edbc 608 #define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */
AnnaBridge 171:3a7713b1edbc 609 #define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */
AnnaBridge 171:3a7713b1edbc 610
AnnaBridge 171:3a7713b1edbc 611 /* Bit fields for ADC SCANDATA */
AnnaBridge 171:3a7713b1edbc 612 #define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */
AnnaBridge 171:3a7713b1edbc 613 #define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */
AnnaBridge 171:3a7713b1edbc 614 #define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
AnnaBridge 171:3a7713b1edbc 615 #define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
AnnaBridge 171:3a7713b1edbc 616 #define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */
AnnaBridge 171:3a7713b1edbc 617 #define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */
AnnaBridge 171:3a7713b1edbc 618
AnnaBridge 171:3a7713b1edbc 619 /* Bit fields for ADC SINGLEDATAP */
AnnaBridge 171:3a7713b1edbc 620 #define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */
AnnaBridge 171:3a7713b1edbc 621 #define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */
AnnaBridge 171:3a7713b1edbc 622 #define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
AnnaBridge 171:3a7713b1edbc 623 #define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
AnnaBridge 171:3a7713b1edbc 624 #define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */
AnnaBridge 171:3a7713b1edbc 625 #define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 /* Bit fields for ADC SCANDATAP */
AnnaBridge 171:3a7713b1edbc 628 #define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */
AnnaBridge 171:3a7713b1edbc 629 #define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */
AnnaBridge 171:3a7713b1edbc 630 #define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
AnnaBridge 171:3a7713b1edbc 631 #define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
AnnaBridge 171:3a7713b1edbc 632 #define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */
AnnaBridge 171:3a7713b1edbc 633 #define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */
AnnaBridge 171:3a7713b1edbc 634
AnnaBridge 171:3a7713b1edbc 635 /* Bit fields for ADC CAL */
AnnaBridge 171:3a7713b1edbc 636 #define _ADC_CAL_RESETVALUE 0x3F003F00UL /**< Default value for ADC_CAL */
AnnaBridge 171:3a7713b1edbc 637 #define _ADC_CAL_MASK 0x7F7F7F7FUL /**< Mask for ADC_CAL */
AnnaBridge 171:3a7713b1edbc 638 #define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */
AnnaBridge 171:3a7713b1edbc 639 #define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL /**< Bit mask for ADC_SINGLEOFFSET */
AnnaBridge 171:3a7713b1edbc 640 #define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
AnnaBridge 171:3a7713b1edbc 641 #define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */
AnnaBridge 171:3a7713b1edbc 642 #define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */
AnnaBridge 171:3a7713b1edbc 643 #define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */
AnnaBridge 171:3a7713b1edbc 644 #define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */
AnnaBridge 171:3a7713b1edbc 645 #define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */
AnnaBridge 171:3a7713b1edbc 646 #define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */
AnnaBridge 171:3a7713b1edbc 647 #define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL /**< Bit mask for ADC_SCANOFFSET */
AnnaBridge 171:3a7713b1edbc 648 #define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
AnnaBridge 171:3a7713b1edbc 649 #define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */
AnnaBridge 171:3a7713b1edbc 650 #define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */
AnnaBridge 171:3a7713b1edbc 651 #define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */
AnnaBridge 171:3a7713b1edbc 652 #define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */
AnnaBridge 171:3a7713b1edbc 653 #define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */
AnnaBridge 171:3a7713b1edbc 654
AnnaBridge 171:3a7713b1edbc 655 /* Bit fields for ADC BIASPROG */
AnnaBridge 171:3a7713b1edbc 656 #define _ADC_BIASPROG_RESETVALUE 0x00000747UL /**< Default value for ADC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 657 #define _ADC_BIASPROG_MASK 0x00000F4FUL /**< Mask for ADC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 658 #define _ADC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for ADC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 659 #define _ADC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for ADC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 660 #define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 661 #define ADC_BIASPROG_BIASPROG_DEFAULT (_ADC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 662 #define ADC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */
AnnaBridge 171:3a7713b1edbc 663 #define _ADC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for ADC_HALFBIAS */
AnnaBridge 171:3a7713b1edbc 664 #define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for ADC_HALFBIAS */
AnnaBridge 171:3a7713b1edbc 665 #define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 666 #define ADC_BIASPROG_HALFBIAS_DEFAULT (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 667 #define _ADC_BIASPROG_COMPBIAS_SHIFT 8 /**< Shift value for ADC_COMPBIAS */
AnnaBridge 171:3a7713b1edbc 668 #define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL /**< Bit mask for ADC_COMPBIAS */
AnnaBridge 171:3a7713b1edbc 669 #define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 670 #define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 671
AnnaBridge 171:3a7713b1edbc 672 /** @} End of group EFM32GG_ADC */
AnnaBridge 171:3a7713b1edbc 673 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 674