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TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/efm32gg_rmu.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32gg_rmu.h |
AnnaBridge | 171:3a7713b1edbc | 3 | * @brief EFM32GG_RMU register and bit field definitions |
AnnaBridge | 171:3a7713b1edbc | 4 | * @version 5.1.2 |
AnnaBridge | 171:3a7713b1edbc | 5 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 6 | * @section License |
AnnaBridge | 171:3a7713b1edbc | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * Permission is granted to anyone to use this software for any purpose, |
AnnaBridge | 171:3a7713b1edbc | 11 | * including commercial applications, and to alter it and redistribute it |
AnnaBridge | 171:3a7713b1edbc | 12 | * freely, subject to the following restrictions: |
AnnaBridge | 171:3a7713b1edbc | 13 | * |
AnnaBridge | 171:3a7713b1edbc | 14 | * 1. The origin of this software must not be misrepresented; you must not |
AnnaBridge | 171:3a7713b1edbc | 15 | * claim that you wrote the original software.@n |
AnnaBridge | 171:3a7713b1edbc | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
AnnaBridge | 171:3a7713b1edbc | 17 | * misrepresented as being the original software.@n |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. This notice may not be removed or altered from any source distribution. |
AnnaBridge | 171:3a7713b1edbc | 19 | * |
AnnaBridge | 171:3a7713b1edbc | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
AnnaBridge | 171:3a7713b1edbc | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
AnnaBridge | 171:3a7713b1edbc | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
AnnaBridge | 171:3a7713b1edbc | 23 | * kind, including, but not limited to, any implied warranties of |
AnnaBridge | 171:3a7713b1edbc | 24 | * merchantability or fitness for any particular purpose or warranties against |
AnnaBridge | 171:3a7713b1edbc | 25 | * infringement of any proprietary rights of a third party. |
AnnaBridge | 171:3a7713b1edbc | 26 | * |
AnnaBridge | 171:3a7713b1edbc | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
AnnaBridge | 171:3a7713b1edbc | 28 | * incidental, or special damages, or any other relief, or for any claim by |
AnnaBridge | 171:3a7713b1edbc | 29 | * any third party, arising from your use of this Software. |
AnnaBridge | 171:3a7713b1edbc | 30 | * |
AnnaBridge | 171:3a7713b1edbc | 31 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 32 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 33 | * @addtogroup Parts |
AnnaBridge | 171:3a7713b1edbc | 34 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 35 | ******************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 36 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 37 | * @defgroup EFM32GG_RMU |
AnnaBridge | 171:3a7713b1edbc | 38 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 39 | * @brief EFM32GG_RMU Register Declaration |
AnnaBridge | 171:3a7713b1edbc | 40 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 41 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 42 | { |
AnnaBridge | 171:3a7713b1edbc | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 44 | __IM uint32_t RSTCAUSE; /**< Reset Cause Register */ |
AnnaBridge | 171:3a7713b1edbc | 45 | __OM uint32_t CMD; /**< Command Register */ |
AnnaBridge | 171:3a7713b1edbc | 46 | } RMU_TypeDef; /** @} */ |
AnnaBridge | 171:3a7713b1edbc | 47 | |
AnnaBridge | 171:3a7713b1edbc | 48 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 49 | * @defgroup EFM32GG_RMU_BitFields |
AnnaBridge | 171:3a7713b1edbc | 50 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 51 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | /* Bit fields for RMU CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 54 | #define _RMU_CTRL_RESETVALUE 0x00000002UL /**< Default value for RMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 55 | #define _RMU_CTRL_MASK 0x00000003UL /**< Mask for RMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 56 | #define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) /**< Lockup Reset Disable */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /**< Shift value for RMU_LOCKUPRDIS */ |
AnnaBridge | 171:3a7713b1edbc | 58 | #define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /**< Bit mask for RMU_LOCKUPRDIS */ |
AnnaBridge | 171:3a7713b1edbc | 59 | #define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 61 | #define RMU_CTRL_BURSTEN (0x1UL << 1) /**< Backup domain reset enable */ |
AnnaBridge | 171:3a7713b1edbc | 62 | #define _RMU_CTRL_BURSTEN_SHIFT 1 /**< Shift value for RMU_BURSTEN */ |
AnnaBridge | 171:3a7713b1edbc | 63 | #define _RMU_CTRL_BURSTEN_MASK 0x2UL /**< Bit mask for RMU_BURSTEN */ |
AnnaBridge | 171:3a7713b1edbc | 64 | #define _RMU_CTRL_BURSTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for RMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 65 | #define RMU_CTRL_BURSTEN_DEFAULT (_RMU_CTRL_BURSTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 66 | |
AnnaBridge | 171:3a7713b1edbc | 67 | /* Bit fields for RMU RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 68 | #define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define _RMU_RSTCAUSE_MASK 0x0000FFFFUL /**< Mask for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 70 | #define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) /**< Brown Out Detector Unregulated Domain Reset */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /**< Shift value for RMU_BODUNREGRST */ |
AnnaBridge | 171:3a7713b1edbc | 77 | #define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /**< Bit mask for RMU_BODUNREGRST */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 80 | #define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) /**< Brown Out Detector Regulated Domain Reset */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /**< Shift value for RMU_BODREGRST */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /**< Bit mask for RMU_BODREGRST */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 84 | #define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define RMU_RSTCAUSE_EXTRST (0x1UL << 3) /**< External Pin Reset */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /**< Shift value for RMU_EXTRST */ |
AnnaBridge | 171:3a7713b1edbc | 87 | #define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /**< Bit mask for RMU_EXTRST */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) /**< Watchdog Reset */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /**< Shift value for RMU_WDOGRST */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /**< Bit mask for RMU_WDOGRST */ |
AnnaBridge | 171:3a7713b1edbc | 93 | #define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 94 | #define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 95 | #define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) /**< LOCKUP Reset */ |
AnnaBridge | 171:3a7713b1edbc | 96 | #define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /**< Shift value for RMU_LOCKUPRST */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /**< Bit mask for RMU_LOCKUPRST */ |
AnnaBridge | 171:3a7713b1edbc | 98 | #define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 99 | #define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 100 | #define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) /**< System Request Reset */ |
AnnaBridge | 171:3a7713b1edbc | 101 | #define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /**< Shift value for RMU_SYSREQRST */ |
AnnaBridge | 171:3a7713b1edbc | 102 | #define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /**< Bit mask for RMU_SYSREQRST */ |
AnnaBridge | 171:3a7713b1edbc | 103 | #define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 104 | #define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 105 | #define RMU_RSTCAUSE_EM4RST (0x1UL << 7) /**< EM4 Reset */ |
AnnaBridge | 171:3a7713b1edbc | 106 | #define _RMU_RSTCAUSE_EM4RST_SHIFT 7 /**< Shift value for RMU_EM4RST */ |
AnnaBridge | 171:3a7713b1edbc | 107 | #define _RMU_RSTCAUSE_EM4RST_MASK 0x80UL /**< Bit mask for RMU_EM4RST */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 109 | #define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 7) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 110 | #define RMU_RSTCAUSE_EM4WURST (0x1UL << 8) /**< EM4 Wake-up Reset */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #define _RMU_RSTCAUSE_EM4WURST_SHIFT 8 /**< Shift value for RMU_EM4WURST */ |
AnnaBridge | 171:3a7713b1edbc | 112 | #define _RMU_RSTCAUSE_EM4WURST_MASK 0x100UL /**< Bit mask for RMU_EM4WURST */ |
AnnaBridge | 171:3a7713b1edbc | 113 | #define _RMU_RSTCAUSE_EM4WURST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 114 | #define RMU_RSTCAUSE_EM4WURST_DEFAULT (_RMU_RSTCAUSE_EM4WURST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 115 | #define RMU_RSTCAUSE_BODAVDD0 (0x1UL << 9) /**< AVDD0 Bod Reset */ |
AnnaBridge | 171:3a7713b1edbc | 116 | #define _RMU_RSTCAUSE_BODAVDD0_SHIFT 9 /**< Shift value for RMU_BODAVDD0 */ |
AnnaBridge | 171:3a7713b1edbc | 117 | #define _RMU_RSTCAUSE_BODAVDD0_MASK 0x200UL /**< Bit mask for RMU_BODAVDD0 */ |
AnnaBridge | 171:3a7713b1edbc | 118 | #define _RMU_RSTCAUSE_BODAVDD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 119 | #define RMU_RSTCAUSE_BODAVDD0_DEFAULT (_RMU_RSTCAUSE_BODAVDD0_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 120 | #define RMU_RSTCAUSE_BODAVDD1 (0x1UL << 10) /**< AVDD1 Bod Reset */ |
AnnaBridge | 171:3a7713b1edbc | 121 | #define _RMU_RSTCAUSE_BODAVDD1_SHIFT 10 /**< Shift value for RMU_BODAVDD1 */ |
AnnaBridge | 171:3a7713b1edbc | 122 | #define _RMU_RSTCAUSE_BODAVDD1_MASK 0x400UL /**< Bit mask for RMU_BODAVDD1 */ |
AnnaBridge | 171:3a7713b1edbc | 123 | #define _RMU_RSTCAUSE_BODAVDD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 124 | #define RMU_RSTCAUSE_BODAVDD1_DEFAULT (_RMU_RSTCAUSE_BODAVDD1_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 125 | #define RMU_RSTCAUSE_BUBODVDDDREG (0x1UL << 11) /**< Backup Brown Out Detector, VDD_DREG */ |
AnnaBridge | 171:3a7713b1edbc | 126 | #define _RMU_RSTCAUSE_BUBODVDDDREG_SHIFT 11 /**< Shift value for RMU_BUBODVDDDREG */ |
AnnaBridge | 171:3a7713b1edbc | 127 | #define _RMU_RSTCAUSE_BUBODVDDDREG_MASK 0x800UL /**< Bit mask for RMU_BUBODVDDDREG */ |
AnnaBridge | 171:3a7713b1edbc | 128 | #define _RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 129 | #define RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT (_RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 130 | #define RMU_RSTCAUSE_BUBODBUVIN (0x1UL << 12) /**< Backup Brown Out Detector, BU_VIN */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #define _RMU_RSTCAUSE_BUBODBUVIN_SHIFT 12 /**< Shift value for RMU_BUBODBUVIN */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #define _RMU_RSTCAUSE_BUBODBUVIN_MASK 0x1000UL /**< Bit mask for RMU_BUBODBUVIN */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #define _RMU_RSTCAUSE_BUBODBUVIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 134 | #define RMU_RSTCAUSE_BUBODBUVIN_DEFAULT (_RMU_RSTCAUSE_BUBODBUVIN_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 135 | #define RMU_RSTCAUSE_BUBODUNREG (0x1UL << 13) /**< Backup Brown Out Detector Unregulated Domain */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #define _RMU_RSTCAUSE_BUBODUNREG_SHIFT 13 /**< Shift value for RMU_BUBODUNREG */ |
AnnaBridge | 171:3a7713b1edbc | 137 | #define _RMU_RSTCAUSE_BUBODUNREG_MASK 0x2000UL /**< Bit mask for RMU_BUBODUNREG */ |
AnnaBridge | 171:3a7713b1edbc | 138 | #define _RMU_RSTCAUSE_BUBODUNREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define RMU_RSTCAUSE_BUBODUNREG_DEFAULT (_RMU_RSTCAUSE_BUBODUNREG_DEFAULT << 13) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 140 | #define RMU_RSTCAUSE_BUBODREG (0x1UL << 14) /**< Backup Brown Out Detector Regulated Domain */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define _RMU_RSTCAUSE_BUBODREG_SHIFT 14 /**< Shift value for RMU_BUBODREG */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #define _RMU_RSTCAUSE_BUBODREG_MASK 0x4000UL /**< Bit mask for RMU_BUBODREG */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #define _RMU_RSTCAUSE_BUBODREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define RMU_RSTCAUSE_BUBODREG_DEFAULT (_RMU_RSTCAUSE_BUBODREG_DEFAULT << 14) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define RMU_RSTCAUSE_BUMODERST (0x1UL << 15) /**< Backup mode reset */ |
AnnaBridge | 171:3a7713b1edbc | 146 | #define _RMU_RSTCAUSE_BUMODERST_SHIFT 15 /**< Shift value for RMU_BUMODERST */ |
AnnaBridge | 171:3a7713b1edbc | 147 | #define _RMU_RSTCAUSE_BUMODERST_MASK 0x8000UL /**< Bit mask for RMU_BUMODERST */ |
AnnaBridge | 171:3a7713b1edbc | 148 | #define _RMU_RSTCAUSE_BUMODERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 149 | #define RMU_RSTCAUSE_BUMODERST_DEFAULT (_RMU_RSTCAUSE_BUMODERST_DEFAULT << 15) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
AnnaBridge | 171:3a7713b1edbc | 150 | |
AnnaBridge | 171:3a7713b1edbc | 151 | /* Bit fields for RMU CMD */ |
AnnaBridge | 171:3a7713b1edbc | 152 | #define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 154 | #define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */ |
AnnaBridge | 171:3a7713b1edbc | 156 | #define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */ |
AnnaBridge | 171:3a7713b1edbc | 157 | #define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 158 | #define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 159 | |
AnnaBridge | 171:3a7713b1edbc | 160 | /** @} End of group EFM32GG_RMU */ |
AnnaBridge | 171:3a7713b1edbc | 161 | /** @} End of group Parts */ |
AnnaBridge | 171:3a7713b1edbc | 162 |