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TARGET_EFM32GG11_STK3701/TOOLCHAIN_ARM_MICRO/efm32gg11b_cmu.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_EFM32GG11_STK3701/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/efm32gg11b_cmu.h@170:e95d10626187
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 170:e95d10626187 | 1 | /**************************************************************************//** |
| AnnaBridge | 170:e95d10626187 | 2 | * @file efm32gg11b_cmu.h |
| AnnaBridge | 170:e95d10626187 | 3 | * @brief EFM32GG11B_CMU register and bit field definitions |
| AnnaBridge | 170:e95d10626187 | 4 | * @version 5.3.2 |
| AnnaBridge | 170:e95d10626187 | 5 | ****************************************************************************** |
| AnnaBridge | 170:e95d10626187 | 6 | * # License |
| AnnaBridge | 170:e95d10626187 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| AnnaBridge | 170:e95d10626187 | 8 | ****************************************************************************** |
| AnnaBridge | 170:e95d10626187 | 9 | * |
| AnnaBridge | 170:e95d10626187 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| AnnaBridge | 170:e95d10626187 | 11 | * including commercial applications, and to alter it and redistribute it |
| AnnaBridge | 170:e95d10626187 | 12 | * freely, subject to the following restrictions: |
| AnnaBridge | 170:e95d10626187 | 13 | * |
| AnnaBridge | 170:e95d10626187 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| AnnaBridge | 170:e95d10626187 | 15 | * claim that you wrote the original software.@n |
| AnnaBridge | 170:e95d10626187 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| AnnaBridge | 170:e95d10626187 | 17 | * misrepresented as being the original software.@n |
| AnnaBridge | 170:e95d10626187 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| AnnaBridge | 170:e95d10626187 | 19 | * |
| AnnaBridge | 170:e95d10626187 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| AnnaBridge | 170:e95d10626187 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| AnnaBridge | 170:e95d10626187 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| AnnaBridge | 170:e95d10626187 | 23 | * kind, including, but not limited to, any implied warranties of |
| AnnaBridge | 170:e95d10626187 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| AnnaBridge | 170:e95d10626187 | 25 | * infringement of any proprietary rights of a third party. |
| AnnaBridge | 170:e95d10626187 | 26 | * |
| AnnaBridge | 170:e95d10626187 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| AnnaBridge | 170:e95d10626187 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| AnnaBridge | 170:e95d10626187 | 29 | * any third party, arising from your use of this Software. |
| AnnaBridge | 170:e95d10626187 | 30 | * |
| AnnaBridge | 170:e95d10626187 | 31 | *****************************************************************************/ |
| AnnaBridge | 170:e95d10626187 | 32 | |
| AnnaBridge | 170:e95d10626187 | 33 | #if defined(__ICCARM__) |
| AnnaBridge | 170:e95d10626187 | 34 | #pragma system_include /* Treat file as system include file. */ |
| AnnaBridge | 170:e95d10626187 | 35 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| AnnaBridge | 170:e95d10626187 | 36 | #pragma clang system_header /* Treat file as system include file. */ |
| AnnaBridge | 170:e95d10626187 | 37 | #endif |
| AnnaBridge | 170:e95d10626187 | 38 | |
| AnnaBridge | 170:e95d10626187 | 39 | /**************************************************************************//** |
| AnnaBridge | 170:e95d10626187 | 40 | * @addtogroup Parts |
| AnnaBridge | 170:e95d10626187 | 41 | * @{ |
| AnnaBridge | 170:e95d10626187 | 42 | ******************************************************************************/ |
| AnnaBridge | 170:e95d10626187 | 43 | /**************************************************************************//** |
| AnnaBridge | 170:e95d10626187 | 44 | * @defgroup EFM32GG11B_CMU CMU |
| AnnaBridge | 170:e95d10626187 | 45 | * @{ |
| AnnaBridge | 170:e95d10626187 | 46 | * @brief EFM32GG11B_CMU Register Declaration |
| AnnaBridge | 170:e95d10626187 | 47 | *****************************************************************************/ |
| AnnaBridge | 170:e95d10626187 | 48 | /** CMU Register Declaration */ |
| AnnaBridge | 170:e95d10626187 | 49 | typedef struct { |
| AnnaBridge | 170:e95d10626187 | 50 | __IOM uint32_t CTRL; /**< CMU Control Register */ |
| AnnaBridge | 170:e95d10626187 | 51 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 52 | __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ |
| AnnaBridge | 170:e95d10626187 | 53 | |
| AnnaBridge | 170:e95d10626187 | 54 | uint32_t RESERVED1[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 55 | __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ |
| AnnaBridge | 170:e95d10626187 | 56 | |
| AnnaBridge | 170:e95d10626187 | 57 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 58 | __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ |
| AnnaBridge | 170:e95d10626187 | 59 | |
| AnnaBridge | 170:e95d10626187 | 60 | uint32_t RESERVED3[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 61 | __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ |
| AnnaBridge | 170:e95d10626187 | 62 | __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ |
| AnnaBridge | 170:e95d10626187 | 63 | |
| AnnaBridge | 170:e95d10626187 | 64 | uint32_t RESERVED4[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 65 | __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ |
| AnnaBridge | 170:e95d10626187 | 66 | __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */ |
| AnnaBridge | 170:e95d10626187 | 67 | __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ |
| AnnaBridge | 170:e95d10626187 | 68 | __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ |
| AnnaBridge | 170:e95d10626187 | 69 | |
| AnnaBridge | 170:e95d10626187 | 70 | uint32_t RESERVED5[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 71 | __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ |
| AnnaBridge | 170:e95d10626187 | 72 | __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ |
| AnnaBridge | 170:e95d10626187 | 73 | uint32_t RESERVED6[2]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 74 | __IOM uint32_t CALCTRL; /**< Calibration Control Register */ |
| AnnaBridge | 170:e95d10626187 | 75 | __IOM uint32_t CALCNT; /**< Calibration Counter Register */ |
| AnnaBridge | 170:e95d10626187 | 76 | uint32_t RESERVED7[2]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 77 | __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ |
| AnnaBridge | 170:e95d10626187 | 78 | __IOM uint32_t CMD; /**< Command Register */ |
| AnnaBridge | 170:e95d10626187 | 79 | uint32_t RESERVED8[2]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 80 | __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ |
| AnnaBridge | 170:e95d10626187 | 81 | __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ |
| AnnaBridge | 170:e95d10626187 | 82 | uint32_t RESERVED9[2]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 83 | __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ |
| AnnaBridge | 170:e95d10626187 | 84 | __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ |
| AnnaBridge | 170:e95d10626187 | 85 | __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ |
| AnnaBridge | 170:e95d10626187 | 86 | __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ |
| AnnaBridge | 170:e95d10626187 | 87 | __IM uint32_t STATUS; /**< Status Register */ |
| AnnaBridge | 170:e95d10626187 | 88 | __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ |
| AnnaBridge | 170:e95d10626187 | 89 | uint32_t RESERVED10[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 90 | __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ |
| AnnaBridge | 170:e95d10626187 | 91 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| AnnaBridge | 170:e95d10626187 | 92 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| AnnaBridge | 170:e95d10626187 | 93 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| AnnaBridge | 170:e95d10626187 | 94 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| AnnaBridge | 170:e95d10626187 | 95 | __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ |
| AnnaBridge | 170:e95d10626187 | 96 | |
| AnnaBridge | 170:e95d10626187 | 97 | uint32_t RESERVED11[3]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 98 | __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ |
| AnnaBridge | 170:e95d10626187 | 99 | __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ |
| AnnaBridge | 170:e95d10626187 | 100 | |
| AnnaBridge | 170:e95d10626187 | 101 | uint32_t RESERVED12[6]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 102 | __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ |
| AnnaBridge | 170:e95d10626187 | 103 | uint32_t RESERVED13[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 104 | __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ |
| AnnaBridge | 170:e95d10626187 | 105 | __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ |
| AnnaBridge | 170:e95d10626187 | 106 | __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ |
| AnnaBridge | 170:e95d10626187 | 107 | uint32_t RESERVED14[3]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 108 | __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ |
| AnnaBridge | 170:e95d10626187 | 109 | __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ |
| AnnaBridge | 170:e95d10626187 | 110 | __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ |
| AnnaBridge | 170:e95d10626187 | 111 | __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ |
| AnnaBridge | 170:e95d10626187 | 112 | |
| AnnaBridge | 170:e95d10626187 | 113 | uint32_t RESERVED15[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 114 | __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ |
| AnnaBridge | 170:e95d10626187 | 115 | __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ |
| AnnaBridge | 170:e95d10626187 | 116 | __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ |
| AnnaBridge | 170:e95d10626187 | 117 | __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */ |
| AnnaBridge | 170:e95d10626187 | 118 | uint32_t RESERVED16[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 119 | __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ |
| AnnaBridge | 170:e95d10626187 | 120 | uint32_t RESERVED17[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 121 | __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect */ |
| AnnaBridge | 170:e95d10626187 | 122 | |
| AnnaBridge | 170:e95d10626187 | 123 | uint32_t RESERVED18[3]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 124 | __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
| AnnaBridge | 170:e95d10626187 | 125 | __IOM uint32_t FREEZE; /**< Freeze Register */ |
| AnnaBridge | 170:e95d10626187 | 126 | uint32_t RESERVED19[2]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 127 | __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ |
| AnnaBridge | 170:e95d10626187 | 128 | |
| AnnaBridge | 170:e95d10626187 | 129 | uint32_t RESERVED20[2]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 130 | __IOM uint32_t ADCCTRL; /**< ADC Control Register */ |
| AnnaBridge | 170:e95d10626187 | 131 | __IOM uint32_t SDIOCTRL; /**< SDIO Control Register */ |
| AnnaBridge | 170:e95d10626187 | 132 | __IOM uint32_t QSPICTRL; /**< QSPI Control Register */ |
| AnnaBridge | 170:e95d10626187 | 133 | uint32_t RESERVED21[2]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 134 | __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ |
| AnnaBridge | 170:e95d10626187 | 135 | __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ |
| AnnaBridge | 170:e95d10626187 | 136 | __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ |
| AnnaBridge | 170:e95d10626187 | 137 | uint32_t RESERVED22[1]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 138 | __IOM uint32_t LOCK; /**< Configuration Lock Register */ |
| AnnaBridge | 170:e95d10626187 | 139 | __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ |
| AnnaBridge | 170:e95d10626187 | 140 | |
| AnnaBridge | 170:e95d10626187 | 141 | uint32_t RESERVED23[26]; /**< Reserved for future use **/ |
| AnnaBridge | 170:e95d10626187 | 142 | __IOM uint32_t USBCTRL; /**< USB Control Register */ |
| AnnaBridge | 170:e95d10626187 | 143 | __IOM uint32_t USBCRCTRL; /**< USB Clock Recovery Control */ |
| AnnaBridge | 170:e95d10626187 | 144 | } CMU_TypeDef; /** @} */ |
| AnnaBridge | 170:e95d10626187 | 145 | |
| AnnaBridge | 170:e95d10626187 | 146 | /**************************************************************************//** |
| AnnaBridge | 170:e95d10626187 | 147 | * @addtogroup EFM32GG11B_CMU |
| AnnaBridge | 170:e95d10626187 | 148 | * @{ |
| AnnaBridge | 170:e95d10626187 | 149 | * @defgroup EFM32GG11B_CMU_BitFields CMU Bit Fields |
| AnnaBridge | 170:e95d10626187 | 150 | * @{ |
| AnnaBridge | 170:e95d10626187 | 151 | *****************************************************************************/ |
| AnnaBridge | 170:e95d10626187 | 152 | |
| AnnaBridge | 170:e95d10626187 | 153 | /* Bit fields for CMU CTRL */ |
| AnnaBridge | 170:e95d10626187 | 154 | #define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 155 | #define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 156 | #define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ |
| AnnaBridge | 170:e95d10626187 | 157 | #define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ |
| AnnaBridge | 170:e95d10626187 | 158 | #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 159 | #define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 160 | #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 161 | #define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 162 | #define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 163 | #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 164 | #define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 165 | #define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 166 | #define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 167 | #define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 168 | #define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 169 | #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 170 | #define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 171 | #define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 172 | #define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 173 | #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 174 | #define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 175 | #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 176 | #define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 177 | #define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 178 | #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 179 | #define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 180 | #define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 181 | #define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 182 | #define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 183 | #define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 184 | #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 185 | #define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 186 | #define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 187 | #define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 188 | #define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ |
| AnnaBridge | 170:e95d10626187 | 189 | #define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ |
| AnnaBridge | 170:e95d10626187 | 190 | #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 191 | #define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 192 | #define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 193 | #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 194 | #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 195 | #define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 196 | #define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 197 | #define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 198 | #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 199 | #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 200 | #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 201 | #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 202 | #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 203 | #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 204 | #define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 205 | #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 206 | #define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 207 | #define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 208 | #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 209 | #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 210 | #define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 211 | #define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 212 | #define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 213 | #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 214 | #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 215 | #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 216 | #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 217 | #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 218 | #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 219 | #define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 220 | #define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ |
| AnnaBridge | 170:e95d10626187 | 221 | #define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ |
| AnnaBridge | 170:e95d10626187 | 222 | #define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 223 | #define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 224 | #define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 225 | #define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 226 | #define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 227 | #define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 228 | #define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 229 | #define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 230 | #define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 231 | #define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 232 | #define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 233 | #define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 234 | #define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 235 | #define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 236 | #define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 237 | #define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 238 | #define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 239 | #define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 240 | #define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 241 | #define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 242 | #define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 243 | #define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 244 | #define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 245 | #define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 246 | #define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 247 | #define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 248 | #define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 249 | #define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 250 | #define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 251 | #define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 252 | #define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 253 | #define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 254 | #define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 255 | #define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 256 | #define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ |
| AnnaBridge | 170:e95d10626187 | 257 | #define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ |
| AnnaBridge | 170:e95d10626187 | 258 | #define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ |
| AnnaBridge | 170:e95d10626187 | 259 | #define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 260 | #define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 261 | #define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ |
| AnnaBridge | 170:e95d10626187 | 262 | #define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ |
| AnnaBridge | 170:e95d10626187 | 263 | #define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ |
| AnnaBridge | 170:e95d10626187 | 264 | #define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 265 | #define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ |
| AnnaBridge | 170:e95d10626187 | 266 | |
| AnnaBridge | 170:e95d10626187 | 267 | /* Bit fields for CMU USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 268 | #define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 269 | #define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 270 | #define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
| AnnaBridge | 170:e95d10626187 | 271 | #define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ |
| AnnaBridge | 170:e95d10626187 | 272 | #define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 273 | #define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 274 | #define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ |
| AnnaBridge | 170:e95d10626187 | 275 | #define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ |
| AnnaBridge | 170:e95d10626187 | 276 | #define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 277 | #define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 278 | #define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ |
| AnnaBridge | 170:e95d10626187 | 279 | #define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ |
| AnnaBridge | 170:e95d10626187 | 280 | #define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 281 | #define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 282 | #define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ |
| AnnaBridge | 170:e95d10626187 | 283 | #define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ |
| AnnaBridge | 170:e95d10626187 | 284 | #define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 285 | #define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 286 | #define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ |
| AnnaBridge | 170:e95d10626187 | 287 | #define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ |
| AnnaBridge | 170:e95d10626187 | 288 | #define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ |
| AnnaBridge | 170:e95d10626187 | 289 | #define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 290 | #define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 291 | #define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ |
| AnnaBridge | 170:e95d10626187 | 292 | #define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ |
| AnnaBridge | 170:e95d10626187 | 293 | #define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 294 | #define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 295 | #define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 296 | #define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 297 | #define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 298 | #define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 299 | #define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 300 | #define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 301 | #define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ |
| AnnaBridge | 170:e95d10626187 | 302 | #define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ |
| AnnaBridge | 170:e95d10626187 | 303 | #define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ |
| AnnaBridge | 170:e95d10626187 | 304 | #define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 305 | #define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 306 | #define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ |
| AnnaBridge | 170:e95d10626187 | 307 | #define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ |
| AnnaBridge | 170:e95d10626187 | 308 | #define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 309 | #define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 310 | |
| AnnaBridge | 170:e95d10626187 | 311 | /* Bit fields for CMU HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 312 | #define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 313 | #define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 314 | #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
| AnnaBridge | 170:e95d10626187 | 315 | #define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ |
| AnnaBridge | 170:e95d10626187 | 316 | #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 317 | #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 318 | #define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ |
| AnnaBridge | 170:e95d10626187 | 319 | #define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ |
| AnnaBridge | 170:e95d10626187 | 320 | #define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 321 | #define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 322 | #define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ |
| AnnaBridge | 170:e95d10626187 | 323 | #define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ |
| AnnaBridge | 170:e95d10626187 | 324 | #define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 325 | #define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 326 | #define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ |
| AnnaBridge | 170:e95d10626187 | 327 | #define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ |
| AnnaBridge | 170:e95d10626187 | 328 | #define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 329 | #define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 330 | #define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ |
| AnnaBridge | 170:e95d10626187 | 331 | #define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ |
| AnnaBridge | 170:e95d10626187 | 332 | #define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ |
| AnnaBridge | 170:e95d10626187 | 333 | #define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 334 | #define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 335 | #define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ |
| AnnaBridge | 170:e95d10626187 | 336 | #define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ |
| AnnaBridge | 170:e95d10626187 | 337 | #define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 338 | #define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 339 | #define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 340 | #define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 341 | #define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 342 | #define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 343 | #define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 344 | #define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 345 | #define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ |
| AnnaBridge | 170:e95d10626187 | 346 | #define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ |
| AnnaBridge | 170:e95d10626187 | 347 | #define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ |
| AnnaBridge | 170:e95d10626187 | 348 | #define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 349 | #define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 350 | #define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ |
| AnnaBridge | 170:e95d10626187 | 351 | #define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ |
| AnnaBridge | 170:e95d10626187 | 352 | #define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 353 | #define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 354 | |
| AnnaBridge | 170:e95d10626187 | 355 | /* Bit fields for CMU AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 356 | #define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 357 | #define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 358 | #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
| AnnaBridge | 170:e95d10626187 | 359 | #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ |
| AnnaBridge | 170:e95d10626187 | 360 | #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 361 | #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 362 | #define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ |
| AnnaBridge | 170:e95d10626187 | 363 | #define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ |
| AnnaBridge | 170:e95d10626187 | 364 | #define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 365 | #define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 366 | #define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ |
| AnnaBridge | 170:e95d10626187 | 367 | #define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ |
| AnnaBridge | 170:e95d10626187 | 368 | #define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 369 | #define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 370 | #define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ |
| AnnaBridge | 170:e95d10626187 | 371 | #define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ |
| AnnaBridge | 170:e95d10626187 | 372 | #define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 373 | #define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 374 | #define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ |
| AnnaBridge | 170:e95d10626187 | 375 | #define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ |
| AnnaBridge | 170:e95d10626187 | 376 | #define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ |
| AnnaBridge | 170:e95d10626187 | 377 | #define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 378 | #define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 379 | #define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ |
| AnnaBridge | 170:e95d10626187 | 380 | #define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ |
| AnnaBridge | 170:e95d10626187 | 381 | #define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 382 | #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 383 | #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 384 | #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 385 | #define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 386 | #define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 387 | #define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 388 | #define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 389 | #define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ |
| AnnaBridge | 170:e95d10626187 | 390 | #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ |
| AnnaBridge | 170:e95d10626187 | 391 | #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ |
| AnnaBridge | 170:e95d10626187 | 392 | #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 393 | #define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 394 | #define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ |
| AnnaBridge | 170:e95d10626187 | 395 | #define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ |
| AnnaBridge | 170:e95d10626187 | 396 | #define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 397 | #define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 398 | |
| AnnaBridge | 170:e95d10626187 | 399 | /* Bit fields for CMU LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 400 | #define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 401 | #define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 402 | #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
| AnnaBridge | 170:e95d10626187 | 403 | #define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ |
| AnnaBridge | 170:e95d10626187 | 404 | #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 405 | #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 406 | #define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable duty cycling of vref */ |
| AnnaBridge | 170:e95d10626187 | 407 | #define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ |
| AnnaBridge | 170:e95d10626187 | 408 | #define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ |
| AnnaBridge | 170:e95d10626187 | 409 | #define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 410 | #define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 411 | #define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable comparator chopping */ |
| AnnaBridge | 170:e95d10626187 | 412 | #define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ |
| AnnaBridge | 170:e95d10626187 | 413 | #define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ |
| AnnaBridge | 170:e95d10626187 | 414 | #define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 415 | #define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 416 | #define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable dynamic element matching */ |
| AnnaBridge | 170:e95d10626187 | 417 | #define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ |
| AnnaBridge | 170:e95d10626187 | 418 | #define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ |
| AnnaBridge | 170:e95d10626187 | 419 | #define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 420 | #define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 421 | #define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ |
| AnnaBridge | 170:e95d10626187 | 422 | #define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ |
| AnnaBridge | 170:e95d10626187 | 423 | #define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 424 | #define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 425 | #define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 426 | #define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 427 | #define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 428 | #define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 429 | #define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 430 | #define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 431 | #define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 432 | #define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 433 | #define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 434 | #define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 435 | #define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 436 | #define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 437 | #define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 438 | #define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 439 | #define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 440 | #define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 441 | #define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 442 | #define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 443 | #define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ |
| AnnaBridge | 170:e95d10626187 | 444 | #define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ |
| AnnaBridge | 170:e95d10626187 | 445 | #define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 446 | #define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 447 | |
| AnnaBridge | 170:e95d10626187 | 448 | /* Bit fields for CMU HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 449 | #define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 450 | #define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 451 | #define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ |
| AnnaBridge | 170:e95d10626187 | 452 | #define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ |
| AnnaBridge | 170:e95d10626187 | 453 | #define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 454 | #define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 455 | #define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 456 | #define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 457 | #define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 458 | #define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 459 | #define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 460 | #define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 461 | #define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 462 | #define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 463 | #define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable double frequency on HFXOX2 clock (compared to HFXO clock). */ |
| AnnaBridge | 170:e95d10626187 | 464 | #define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ |
| AnnaBridge | 170:e95d10626187 | 465 | #define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ |
| AnnaBridge | 170:e95d10626187 | 466 | #define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 467 | #define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 468 | #define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ |
| AnnaBridge | 170:e95d10626187 | 469 | #define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ |
| AnnaBridge | 170:e95d10626187 | 470 | #define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 471 | #define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 472 | #define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 473 | #define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 474 | #define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 475 | #define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 476 | #define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 477 | #define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 478 | #define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 479 | #define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 480 | #define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 481 | #define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 482 | #define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 483 | #define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 484 | #define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 485 | #define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 486 | #define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 487 | #define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 488 | #define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 489 | #define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 490 | #define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 491 | #define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 492 | #define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 493 | #define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 494 | #define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 495 | #define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 496 | #define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 497 | #define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 498 | #define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 499 | #define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 500 | #define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 */ |
| AnnaBridge | 170:e95d10626187 | 501 | #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ |
| AnnaBridge | 170:e95d10626187 | 502 | #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ |
| AnnaBridge | 170:e95d10626187 | 503 | #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 504 | #define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 505 | #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 */ |
| AnnaBridge | 170:e95d10626187 | 506 | #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ |
| AnnaBridge | 170:e95d10626187 | 507 | #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ |
| AnnaBridge | 170:e95d10626187 | 508 | #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 509 | #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 510 | |
| AnnaBridge | 170:e95d10626187 | 511 | /* Bit fields for CMU HFXOSTARTUPCTRL */ |
| AnnaBridge | 170:e95d10626187 | 512 | #define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ |
| AnnaBridge | 170:e95d10626187 | 513 | #define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ |
| AnnaBridge | 170:e95d10626187 | 514 | #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ |
| AnnaBridge | 170:e95d10626187 | 515 | #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ |
| AnnaBridge | 170:e95d10626187 | 516 | #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ |
| AnnaBridge | 170:e95d10626187 | 517 | #define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ |
| AnnaBridge | 170:e95d10626187 | 518 | #define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ |
| AnnaBridge | 170:e95d10626187 | 519 | #define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ |
| AnnaBridge | 170:e95d10626187 | 520 | #define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ |
| AnnaBridge | 170:e95d10626187 | 521 | #define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ |
| AnnaBridge | 170:e95d10626187 | 522 | |
| AnnaBridge | 170:e95d10626187 | 523 | /* Bit fields for CMU HFXOSTEADYSTATECTRL */ |
| AnnaBridge | 170:e95d10626187 | 524 | #define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ |
| AnnaBridge | 170:e95d10626187 | 525 | #define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ |
| AnnaBridge | 170:e95d10626187 | 526 | #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ |
| AnnaBridge | 170:e95d10626187 | 527 | #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ |
| AnnaBridge | 170:e95d10626187 | 528 | #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
| AnnaBridge | 170:e95d10626187 | 529 | #define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
| AnnaBridge | 170:e95d10626187 | 530 | #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ |
| AnnaBridge | 170:e95d10626187 | 531 | #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ |
| AnnaBridge | 170:e95d10626187 | 532 | #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
| AnnaBridge | 170:e95d10626187 | 533 | #define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
| AnnaBridge | 170:e95d10626187 | 534 | #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables oscillator peak detectors */ |
| AnnaBridge | 170:e95d10626187 | 535 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ |
| AnnaBridge | 170:e95d10626187 | 536 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ |
| AnnaBridge | 170:e95d10626187 | 537 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
| AnnaBridge | 170:e95d10626187 | 538 | #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
| AnnaBridge | 170:e95d10626187 | 539 | #define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically perform Peak Monitoring Algorithm on every rising edge of ULFRCO */ |
| AnnaBridge | 170:e95d10626187 | 540 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ |
| AnnaBridge | 170:e95d10626187 | 541 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ |
| AnnaBridge | 170:e95d10626187 | 542 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
| AnnaBridge | 170:e95d10626187 | 543 | #define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
| AnnaBridge | 170:e95d10626187 | 544 | |
| AnnaBridge | 170:e95d10626187 | 545 | /* Bit fields for CMU HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 546 | #define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D04EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 547 | #define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 548 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 549 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 550 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 551 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 552 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 553 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 554 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 555 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 556 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 557 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 558 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 559 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 560 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 561 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 562 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 563 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 564 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 565 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 566 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 567 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 568 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 569 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 570 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 571 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 572 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 573 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 574 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 575 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 576 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 577 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 578 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 579 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 580 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 581 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 582 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 583 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 584 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 585 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 586 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 587 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 588 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000004UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 589 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 590 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 591 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 592 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 593 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 594 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 595 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 596 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 597 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 598 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 599 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 600 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 601 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 602 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 603 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 604 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 605 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 606 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 607 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 608 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 609 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 610 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 611 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 612 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 613 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 614 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 615 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 616 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 617 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 618 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 619 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 620 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 621 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 622 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 623 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 624 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 625 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 626 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 627 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 628 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 629 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 630 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 631 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 632 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 633 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 634 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 635 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 636 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 637 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 638 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 639 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 640 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 641 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 642 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 643 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 644 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 645 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 646 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 647 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 648 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 649 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 650 | |
| AnnaBridge | 170:e95d10626187 | 651 | /* Bit fields for CMU LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 652 | #define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 653 | #define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 654 | #define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
| AnnaBridge | 170:e95d10626187 | 655 | #define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ |
| AnnaBridge | 170:e95d10626187 | 656 | #define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 657 | #define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 658 | #define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ |
| AnnaBridge | 170:e95d10626187 | 659 | #define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ |
| AnnaBridge | 170:e95d10626187 | 660 | #define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 661 | #define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 662 | #define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 663 | #define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 664 | #define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 665 | #define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 666 | #define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 667 | #define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 668 | #define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ |
| AnnaBridge | 170:e95d10626187 | 669 | #define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ |
| AnnaBridge | 170:e95d10626187 | 670 | #define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 671 | #define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 672 | #define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ |
| AnnaBridge | 170:e95d10626187 | 673 | #define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ |
| AnnaBridge | 170:e95d10626187 | 674 | #define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ |
| AnnaBridge | 170:e95d10626187 | 675 | #define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 676 | #define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 677 | #define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ |
| AnnaBridge | 170:e95d10626187 | 678 | #define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ |
| AnnaBridge | 170:e95d10626187 | 679 | #define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ |
| AnnaBridge | 170:e95d10626187 | 680 | #define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 681 | #define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 682 | #define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ |
| AnnaBridge | 170:e95d10626187 | 683 | #define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ |
| AnnaBridge | 170:e95d10626187 | 684 | #define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 685 | #define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 686 | #define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ |
| AnnaBridge | 170:e95d10626187 | 687 | #define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ |
| AnnaBridge | 170:e95d10626187 | 688 | #define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ |
| AnnaBridge | 170:e95d10626187 | 689 | #define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 690 | #define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 691 | #define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 692 | #define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ |
| AnnaBridge | 170:e95d10626187 | 693 | #define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 694 | #define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 695 | #define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 696 | #define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 697 | #define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 698 | #define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 699 | #define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 700 | #define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 701 | #define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 702 | #define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 703 | #define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 704 | #define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 705 | #define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 706 | #define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 707 | #define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 708 | #define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 709 | #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 710 | #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 711 | |
| AnnaBridge | 170:e95d10626187 | 712 | /* Bit fields for CMU DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 713 | #define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 714 | #define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 715 | #define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ |
| AnnaBridge | 170:e95d10626187 | 716 | #define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ |
| AnnaBridge | 170:e95d10626187 | 717 | #define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ |
| AnnaBridge | 170:e95d10626187 | 718 | #define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 719 | #define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 720 | #define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 721 | #define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 722 | #define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 723 | #define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 724 | #define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ |
| AnnaBridge | 170:e95d10626187 | 725 | #define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ |
| AnnaBridge | 170:e95d10626187 | 726 | #define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ |
| AnnaBridge | 170:e95d10626187 | 727 | #define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 728 | #define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 729 | #define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 730 | #define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 731 | #define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 732 | #define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 733 | #define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< automatic recovery ctrl */ |
| AnnaBridge | 170:e95d10626187 | 734 | #define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ |
| AnnaBridge | 170:e95d10626187 | 735 | #define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ |
| AnnaBridge | 170:e95d10626187 | 736 | #define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 737 | #define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 738 | #define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ |
| AnnaBridge | 170:e95d10626187 | 739 | #define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ |
| AnnaBridge | 170:e95d10626187 | 740 | #define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 741 | #define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 742 | #define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 743 | #define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 744 | #define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 745 | #define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 746 | #define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 747 | #define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 748 | #define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 749 | #define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 750 | #define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ |
| AnnaBridge | 170:e95d10626187 | 751 | #define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ |
| AnnaBridge | 170:e95d10626187 | 752 | #define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ |
| AnnaBridge | 170:e95d10626187 | 753 | #define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 754 | #define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ |
| AnnaBridge | 170:e95d10626187 | 755 | |
| AnnaBridge | 170:e95d10626187 | 756 | /* Bit fields for CMU DPLLCTRL1 */ |
| AnnaBridge | 170:e95d10626187 | 757 | #define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ |
| AnnaBridge | 170:e95d10626187 | 758 | #define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ |
| AnnaBridge | 170:e95d10626187 | 759 | #define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ |
| AnnaBridge | 170:e95d10626187 | 760 | #define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ |
| AnnaBridge | 170:e95d10626187 | 761 | #define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ |
| AnnaBridge | 170:e95d10626187 | 762 | #define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ |
| AnnaBridge | 170:e95d10626187 | 763 | #define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ |
| AnnaBridge | 170:e95d10626187 | 764 | #define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ |
| AnnaBridge | 170:e95d10626187 | 765 | #define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ |
| AnnaBridge | 170:e95d10626187 | 766 | #define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ |
| AnnaBridge | 170:e95d10626187 | 767 | |
| AnnaBridge | 170:e95d10626187 | 768 | /* Bit fields for CMU CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 769 | #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 770 | #define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 771 | #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ |
| AnnaBridge | 170:e95d10626187 | 772 | #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ |
| AnnaBridge | 170:e95d10626187 | 773 | #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 774 | #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 775 | #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 776 | #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 777 | #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 778 | #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 779 | #define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 780 | #define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 781 | #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 782 | #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 783 | #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 784 | #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 785 | #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 786 | #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 787 | #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 788 | #define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 789 | #define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ |
| AnnaBridge | 170:e95d10626187 | 790 | #define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ |
| AnnaBridge | 170:e95d10626187 | 791 | #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 792 | #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 793 | #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 794 | #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 795 | #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 796 | #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 797 | #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 798 | #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 799 | #define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 800 | #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 801 | #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 802 | #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 803 | #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 804 | #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 805 | #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 806 | #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 807 | #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 808 | #define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 809 | #define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ |
| AnnaBridge | 170:e95d10626187 | 810 | #define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ |
| AnnaBridge | 170:e95d10626187 | 811 | #define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ |
| AnnaBridge | 170:e95d10626187 | 812 | #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 813 | #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 814 | #define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ |
| AnnaBridge | 170:e95d10626187 | 815 | #define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ |
| AnnaBridge | 170:e95d10626187 | 816 | #define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 817 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 818 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 819 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 820 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 821 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 822 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 823 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 824 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 825 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 826 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 827 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 828 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 829 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 830 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 831 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 832 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 833 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 834 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 835 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 836 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 837 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 838 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 839 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 840 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 841 | #define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 842 | #define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 843 | #define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 844 | #define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 845 | #define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 846 | #define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 847 | #define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 848 | #define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 849 | #define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 850 | #define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 851 | #define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 852 | #define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 853 | #define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 854 | #define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 855 | #define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 856 | #define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 857 | #define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 858 | #define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 859 | #define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 860 | #define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 861 | #define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 862 | #define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 863 | #define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 864 | #define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 865 | #define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 866 | #define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ |
| AnnaBridge | 170:e95d10626187 | 867 | #define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ |
| AnnaBridge | 170:e95d10626187 | 868 | #define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 869 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 870 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 871 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 872 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 873 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 874 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 875 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 876 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 877 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 878 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 879 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 880 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 881 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 882 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 883 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 884 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 885 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 886 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 887 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 888 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 889 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 890 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 891 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 892 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 893 | #define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 894 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 895 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 896 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 897 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 898 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 899 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 900 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 901 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 902 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 903 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 904 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 905 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 906 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 907 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 908 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 909 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 910 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 911 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 912 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 913 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 914 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 915 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 916 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 917 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ |
| AnnaBridge | 170:e95d10626187 | 918 | |
| AnnaBridge | 170:e95d10626187 | 919 | /* Bit fields for CMU CALCNT */ |
| AnnaBridge | 170:e95d10626187 | 920 | #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ |
| AnnaBridge | 170:e95d10626187 | 921 | #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ |
| AnnaBridge | 170:e95d10626187 | 922 | #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ |
| AnnaBridge | 170:e95d10626187 | 923 | #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ |
| AnnaBridge | 170:e95d10626187 | 924 | #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ |
| AnnaBridge | 170:e95d10626187 | 925 | #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ |
| AnnaBridge | 170:e95d10626187 | 926 | |
| AnnaBridge | 170:e95d10626187 | 927 | /* Bit fields for CMU OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 928 | #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 929 | #define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 930 | #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ |
| AnnaBridge | 170:e95d10626187 | 931 | #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ |
| AnnaBridge | 170:e95d10626187 | 932 | #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ |
| AnnaBridge | 170:e95d10626187 | 933 | #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 934 | #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 935 | #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ |
| AnnaBridge | 170:e95d10626187 | 936 | #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 937 | #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 938 | #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 939 | #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 940 | #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ |
| AnnaBridge | 170:e95d10626187 | 941 | #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ |
| AnnaBridge | 170:e95d10626187 | 942 | #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ |
| AnnaBridge | 170:e95d10626187 | 943 | #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 944 | #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 945 | #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ |
| AnnaBridge | 170:e95d10626187 | 946 | #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ |
| AnnaBridge | 170:e95d10626187 | 947 | #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ |
| AnnaBridge | 170:e95d10626187 | 948 | #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 949 | #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 950 | #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ |
| AnnaBridge | 170:e95d10626187 | 951 | #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ |
| AnnaBridge | 170:e95d10626187 | 952 | #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ |
| AnnaBridge | 170:e95d10626187 | 953 | #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 954 | #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 955 | #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ |
| AnnaBridge | 170:e95d10626187 | 956 | #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 957 | #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 958 | #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 959 | #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 960 | #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ |
| AnnaBridge | 170:e95d10626187 | 961 | #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ |
| AnnaBridge | 170:e95d10626187 | 962 | #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ |
| AnnaBridge | 170:e95d10626187 | 963 | #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 964 | #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 965 | #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ |
| AnnaBridge | 170:e95d10626187 | 966 | #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 967 | #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 968 | #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 969 | #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 970 | #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ |
| AnnaBridge | 170:e95d10626187 | 971 | #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ |
| AnnaBridge | 170:e95d10626187 | 972 | #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ |
| AnnaBridge | 170:e95d10626187 | 973 | #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 974 | #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 975 | #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ |
| AnnaBridge | 170:e95d10626187 | 976 | #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ |
| AnnaBridge | 170:e95d10626187 | 977 | #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ |
| AnnaBridge | 170:e95d10626187 | 978 | #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 979 | #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 980 | #define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ |
| AnnaBridge | 170:e95d10626187 | 981 | #define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ |
| AnnaBridge | 170:e95d10626187 | 982 | #define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ |
| AnnaBridge | 170:e95d10626187 | 983 | #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 984 | #define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 985 | #define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ |
| AnnaBridge | 170:e95d10626187 | 986 | #define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 987 | #define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 988 | #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 989 | #define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 990 | #define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ |
| AnnaBridge | 170:e95d10626187 | 991 | #define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ |
| AnnaBridge | 170:e95d10626187 | 992 | #define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ |
| AnnaBridge | 170:e95d10626187 | 993 | #define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 994 | #define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 995 | #define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ |
| AnnaBridge | 170:e95d10626187 | 996 | #define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ |
| AnnaBridge | 170:e95d10626187 | 997 | #define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ |
| AnnaBridge | 170:e95d10626187 | 998 | #define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 999 | #define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
| AnnaBridge | 170:e95d10626187 | 1000 | |
| AnnaBridge | 170:e95d10626187 | 1001 | /* Bit fields for CMU CMD */ |
| AnnaBridge | 170:e95d10626187 | 1002 | #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ |
| AnnaBridge | 170:e95d10626187 | 1003 | #define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ |
| AnnaBridge | 170:e95d10626187 | 1004 | #define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ |
| AnnaBridge | 170:e95d10626187 | 1005 | #define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ |
| AnnaBridge | 170:e95d10626187 | 1006 | #define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ |
| AnnaBridge | 170:e95d10626187 | 1007 | #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
| AnnaBridge | 170:e95d10626187 | 1008 | #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ |
| AnnaBridge | 170:e95d10626187 | 1009 | #define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ |
| AnnaBridge | 170:e95d10626187 | 1010 | #define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ |
| AnnaBridge | 170:e95d10626187 | 1011 | #define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ |
| AnnaBridge | 170:e95d10626187 | 1012 | #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
| AnnaBridge | 170:e95d10626187 | 1013 | #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ |
| AnnaBridge | 170:e95d10626187 | 1014 | #define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ |
| AnnaBridge | 170:e95d10626187 | 1015 | #define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ |
| AnnaBridge | 170:e95d10626187 | 1016 | #define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ |
| AnnaBridge | 170:e95d10626187 | 1017 | #define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
| AnnaBridge | 170:e95d10626187 | 1018 | #define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ |
| AnnaBridge | 170:e95d10626187 | 1019 | |
| AnnaBridge | 170:e95d10626187 | 1020 | /* Bit fields for CMU DBGCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1021 | #define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1022 | #define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1023 | #define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ |
| AnnaBridge | 170:e95d10626187 | 1024 | #define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ |
| AnnaBridge | 170:e95d10626187 | 1025 | #define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1026 | #define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1027 | #define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1028 | #define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1029 | #define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1030 | #define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1031 | #define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1032 | #define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1033 | |
| AnnaBridge | 170:e95d10626187 | 1034 | /* Bit fields for CMU HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1035 | #define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1036 | #define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1037 | #define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ |
| AnnaBridge | 170:e95d10626187 | 1038 | #define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ |
| AnnaBridge | 170:e95d10626187 | 1039 | #define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1040 | #define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1041 | #define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1042 | #define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1043 | #define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1044 | #define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1045 | #define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1046 | #define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1047 | #define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1048 | #define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1049 | #define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1050 | #define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1051 | #define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1052 | #define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1053 | #define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1054 | #define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1055 | |
| AnnaBridge | 170:e95d10626187 | 1056 | /* Bit fields for CMU LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1057 | #define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1058 | #define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1059 | #define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ |
| AnnaBridge | 170:e95d10626187 | 1060 | #define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ |
| AnnaBridge | 170:e95d10626187 | 1061 | #define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1062 | #define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1063 | #define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1064 | #define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1065 | #define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1066 | #define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1067 | #define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1068 | #define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1069 | #define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1070 | #define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1071 | |
| AnnaBridge | 170:e95d10626187 | 1072 | /* Bit fields for CMU LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1073 | #define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1074 | #define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1075 | #define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ |
| AnnaBridge | 170:e95d10626187 | 1076 | #define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ |
| AnnaBridge | 170:e95d10626187 | 1077 | #define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1078 | #define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1079 | #define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1080 | #define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1081 | #define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1082 | #define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1083 | #define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1084 | #define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1085 | #define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1086 | #define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1087 | #define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1088 | #define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1089 | |
| AnnaBridge | 170:e95d10626187 | 1090 | /* Bit fields for CMU LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1091 | #define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1092 | #define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1093 | #define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ |
| AnnaBridge | 170:e95d10626187 | 1094 | #define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ |
| AnnaBridge | 170:e95d10626187 | 1095 | #define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1096 | #define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1097 | #define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1098 | #define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1099 | #define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1100 | #define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1101 | #define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1102 | #define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1103 | #define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1104 | #define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1105 | |
| AnnaBridge | 170:e95d10626187 | 1106 | /* Bit fields for CMU LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1107 | #define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1108 | #define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1109 | #define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ |
| AnnaBridge | 170:e95d10626187 | 1110 | #define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ |
| AnnaBridge | 170:e95d10626187 | 1111 | #define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1112 | #define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1113 | #define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1114 | #define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1115 | #define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1116 | #define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1117 | #define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1118 | #define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1119 | #define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1120 | #define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 1121 | |
| AnnaBridge | 170:e95d10626187 | 1122 | /* Bit fields for CMU STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1123 | #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1124 | #define _CMU_STATUS_MASK 0x3A473FFFUL /**< Mask for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1125 | #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ |
| AnnaBridge | 170:e95d10626187 | 1126 | #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ |
| AnnaBridge | 170:e95d10626187 | 1127 | #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ |
| AnnaBridge | 170:e95d10626187 | 1128 | #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1129 | #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1130 | #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ |
| AnnaBridge | 170:e95d10626187 | 1131 | #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1132 | #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1133 | #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1134 | #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1135 | #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ |
| AnnaBridge | 170:e95d10626187 | 1136 | #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ |
| AnnaBridge | 170:e95d10626187 | 1137 | #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ |
| AnnaBridge | 170:e95d10626187 | 1138 | #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1139 | #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1140 | #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ |
| AnnaBridge | 170:e95d10626187 | 1141 | #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1142 | #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1143 | #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1144 | #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1145 | #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ |
| AnnaBridge | 170:e95d10626187 | 1146 | #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ |
| AnnaBridge | 170:e95d10626187 | 1147 | #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ |
| AnnaBridge | 170:e95d10626187 | 1148 | #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1149 | #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1150 | #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ |
| AnnaBridge | 170:e95d10626187 | 1151 | #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1152 | #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1153 | #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1154 | #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1155 | #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ |
| AnnaBridge | 170:e95d10626187 | 1156 | #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ |
| AnnaBridge | 170:e95d10626187 | 1157 | #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ |
| AnnaBridge | 170:e95d10626187 | 1158 | #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1159 | #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1160 | #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ |
| AnnaBridge | 170:e95d10626187 | 1161 | #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1162 | #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1163 | #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1164 | #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1165 | #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ |
| AnnaBridge | 170:e95d10626187 | 1166 | #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ |
| AnnaBridge | 170:e95d10626187 | 1167 | #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ |
| AnnaBridge | 170:e95d10626187 | 1168 | #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1169 | #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1170 | #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ |
| AnnaBridge | 170:e95d10626187 | 1171 | #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1172 | #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1173 | #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1174 | #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1175 | #define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ |
| AnnaBridge | 170:e95d10626187 | 1176 | #define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ |
| AnnaBridge | 170:e95d10626187 | 1177 | #define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ |
| AnnaBridge | 170:e95d10626187 | 1178 | #define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1179 | #define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1180 | #define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ |
| AnnaBridge | 170:e95d10626187 | 1181 | #define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1182 | #define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1183 | #define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1184 | #define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1185 | #define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ |
| AnnaBridge | 170:e95d10626187 | 1186 | #define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ |
| AnnaBridge | 170:e95d10626187 | 1187 | #define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ |
| AnnaBridge | 170:e95d10626187 | 1188 | #define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1189 | #define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1190 | #define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ |
| AnnaBridge | 170:e95d10626187 | 1191 | #define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ |
| AnnaBridge | 170:e95d10626187 | 1192 | #define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ |
| AnnaBridge | 170:e95d10626187 | 1193 | #define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1194 | #define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1195 | #define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ |
| AnnaBridge | 170:e95d10626187 | 1196 | #define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ |
| AnnaBridge | 170:e95d10626187 | 1197 | #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ |
| AnnaBridge | 170:e95d10626187 | 1198 | #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1199 | #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1200 | #define CMU_STATUS_SDIOCLKENS (0x1UL << 17) /**< SDIO Clock Enabled Status */ |
| AnnaBridge | 170:e95d10626187 | 1201 | #define _CMU_STATUS_SDIOCLKENS_SHIFT 17 /**< Shift value for CMU_SDIOCLKENS */ |
| AnnaBridge | 170:e95d10626187 | 1202 | #define _CMU_STATUS_SDIOCLKENS_MASK 0x20000UL /**< Bit mask for CMU_SDIOCLKENS */ |
| AnnaBridge | 170:e95d10626187 | 1203 | #define _CMU_STATUS_SDIOCLKENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1204 | #define CMU_STATUS_SDIOCLKENS_DEFAULT (_CMU_STATUS_SDIOCLKENS_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1205 | #define CMU_STATUS_QSPI0CLKENS (0x1UL << 18) /**< QSPI0 Clock Enabled Status */ |
| AnnaBridge | 170:e95d10626187 | 1206 | #define _CMU_STATUS_QSPI0CLKENS_SHIFT 18 /**< Shift value for CMU_QSPI0CLKENS */ |
| AnnaBridge | 170:e95d10626187 | 1207 | #define _CMU_STATUS_QSPI0CLKENS_MASK 0x40000UL /**< Bit mask for CMU_QSPI0CLKENS */ |
| AnnaBridge | 170:e95d10626187 | 1208 | #define _CMU_STATUS_QSPI0CLKENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1209 | #define CMU_STATUS_QSPI0CLKENS_DEFAULT (_CMU_STATUS_QSPI0CLKENS_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1210 | #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ |
| AnnaBridge | 170:e95d10626187 | 1211 | #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ |
| AnnaBridge | 170:e95d10626187 | 1212 | #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ |
| AnnaBridge | 170:e95d10626187 | 1213 | #define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1214 | #define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1215 | #define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO amplitude tuning value too low */ |
| AnnaBridge | 170:e95d10626187 | 1216 | #define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ |
| AnnaBridge | 170:e95d10626187 | 1217 | #define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ |
| AnnaBridge | 170:e95d10626187 | 1218 | #define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1219 | #define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1220 | #define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO clock phase */ |
| AnnaBridge | 170:e95d10626187 | 1221 | #define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ |
| AnnaBridge | 170:e95d10626187 | 1222 | #define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ |
| AnnaBridge | 170:e95d10626187 | 1223 | #define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1224 | #define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1225 | #define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO clock phase */ |
| AnnaBridge | 170:e95d10626187 | 1226 | #define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ |
| AnnaBridge | 170:e95d10626187 | 1227 | #define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ |
| AnnaBridge | 170:e95d10626187 | 1228 | #define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1229 | #define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1230 | #define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO clock phase */ |
| AnnaBridge | 170:e95d10626187 | 1231 | #define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ |
| AnnaBridge | 170:e95d10626187 | 1232 | #define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ |
| AnnaBridge | 170:e95d10626187 | 1233 | #define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1234 | #define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ |
| AnnaBridge | 170:e95d10626187 | 1235 | |
| AnnaBridge | 170:e95d10626187 | 1236 | /* Bit fields for CMU HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1237 | #define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1238 | #define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1239 | #define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ |
| AnnaBridge | 170:e95d10626187 | 1240 | #define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ |
| AnnaBridge | 170:e95d10626187 | 1241 | #define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1242 | #define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1243 | #define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1244 | #define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1245 | #define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1246 | #define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1247 | #define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1248 | #define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1249 | #define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1250 | #define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1251 | #define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1252 | #define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1253 | #define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1254 | #define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1255 | #define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1256 | #define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1257 | |
| AnnaBridge | 170:e95d10626187 | 1258 | /* Bit fields for CMU HFXOTRIMSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1259 | #define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1260 | #define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1261 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ |
| AnnaBridge | 170:e95d10626187 | 1262 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ |
| AnnaBridge | 170:e95d10626187 | 1263 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1264 | #define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1265 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ |
| AnnaBridge | 170:e95d10626187 | 1266 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ |
| AnnaBridge | 170:e95d10626187 | 1267 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1268 | #define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1269 | #define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm found a value for IBTRIMXOCORE. If HFXO is started again with PEAKDETTMODE=ONCECMD the IBTRIMXOCORE value from CMU_HFXOTRIMSTATUS will be used and Peak Detection algorithm will be skipped. */ |
| AnnaBridge | 170:e95d10626187 | 1270 | #define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ |
| AnnaBridge | 170:e95d10626187 | 1271 | #define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ |
| AnnaBridge | 170:e95d10626187 | 1272 | #define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1273 | #define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1274 | #define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm found a value for IBTRIMXOCOREMON. */ |
| AnnaBridge | 170:e95d10626187 | 1275 | #define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ |
| AnnaBridge | 170:e95d10626187 | 1276 | #define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ |
| AnnaBridge | 170:e95d10626187 | 1277 | #define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1278 | #define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
| AnnaBridge | 170:e95d10626187 | 1279 | |
| AnnaBridge | 170:e95d10626187 | 1280 | /* Bit fields for CMU IF */ |
| AnnaBridge | 170:e95d10626187 | 1281 | #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1282 | #define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1283 | #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1284 | #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1285 | #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1286 | #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1287 | #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1288 | #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1289 | #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1290 | #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1291 | #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1292 | #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1293 | #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1294 | #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1295 | #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1296 | #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1297 | #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1298 | #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1299 | #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1300 | #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1301 | #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1302 | #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1303 | #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1304 | #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1305 | #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1306 | #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1307 | #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1308 | #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1309 | #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
| AnnaBridge | 170:e95d10626187 | 1310 | #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
| AnnaBridge | 170:e95d10626187 | 1311 | #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1312 | #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1313 | #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1314 | #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
| AnnaBridge | 170:e95d10626187 | 1315 | #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
| AnnaBridge | 170:e95d10626187 | 1316 | #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1317 | #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1318 | #define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1319 | #define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1320 | #define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1321 | #define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1322 | #define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1323 | #define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1324 | #define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ |
| AnnaBridge | 170:e95d10626187 | 1325 | #define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ |
| AnnaBridge | 170:e95d10626187 | 1326 | #define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1327 | #define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1328 | #define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1329 | #define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ |
| AnnaBridge | 170:e95d10626187 | 1330 | #define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ |
| AnnaBridge | 170:e95d10626187 | 1331 | #define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1332 | #define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1333 | #define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1334 | #define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ |
| AnnaBridge | 170:e95d10626187 | 1335 | #define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ |
| AnnaBridge | 170:e95d10626187 | 1336 | #define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1337 | #define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1338 | #define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1339 | #define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 1340 | #define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 1341 | #define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1342 | #define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1343 | #define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1344 | #define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ |
| AnnaBridge | 170:e95d10626187 | 1345 | #define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ |
| AnnaBridge | 170:e95d10626187 | 1346 | #define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1347 | #define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1348 | #define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1349 | #define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ |
| AnnaBridge | 170:e95d10626187 | 1350 | #define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ |
| AnnaBridge | 170:e95d10626187 | 1351 | #define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1352 | #define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1353 | #define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1354 | #define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ |
| AnnaBridge | 170:e95d10626187 | 1355 | #define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ |
| AnnaBridge | 170:e95d10626187 | 1356 | #define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1357 | #define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1358 | #define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1359 | #define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ |
| AnnaBridge | 170:e95d10626187 | 1360 | #define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ |
| AnnaBridge | 170:e95d10626187 | 1361 | #define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1362 | #define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1363 | #define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1364 | #define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1365 | #define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1366 | #define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1367 | #define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1368 | #define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1369 | #define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1370 | #define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1371 | #define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1372 | #define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1373 | #define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1374 | #define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1375 | #define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1376 | #define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1377 | #define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1378 | #define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1379 | #define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ |
| AnnaBridge | 170:e95d10626187 | 1380 | #define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ |
| AnnaBridge | 170:e95d10626187 | 1381 | #define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1382 | #define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ |
| AnnaBridge | 170:e95d10626187 | 1383 | |
| AnnaBridge | 170:e95d10626187 | 1384 | /* Bit fields for CMU IFS */ |
| AnnaBridge | 170:e95d10626187 | 1385 | #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1386 | #define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1387 | #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1388 | #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1389 | #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1390 | #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1391 | #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1392 | #define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1393 | #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1394 | #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1395 | #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1396 | #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1397 | #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1398 | #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1399 | #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1400 | #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1401 | #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1402 | #define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1403 | #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1404 | #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1405 | #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1406 | #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1407 | #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1408 | #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1409 | #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1410 | #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1411 | #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1412 | #define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1413 | #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
| AnnaBridge | 170:e95d10626187 | 1414 | #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
| AnnaBridge | 170:e95d10626187 | 1415 | #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1416 | #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1417 | #define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1418 | #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
| AnnaBridge | 170:e95d10626187 | 1419 | #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
| AnnaBridge | 170:e95d10626187 | 1420 | #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1421 | #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1422 | #define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1423 | #define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1424 | #define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1425 | #define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1426 | #define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1427 | #define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1428 | #define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ |
| AnnaBridge | 170:e95d10626187 | 1429 | #define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ |
| AnnaBridge | 170:e95d10626187 | 1430 | #define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1431 | #define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1432 | #define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1433 | #define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ |
| AnnaBridge | 170:e95d10626187 | 1434 | #define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ |
| AnnaBridge | 170:e95d10626187 | 1435 | #define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1436 | #define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1437 | #define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1438 | #define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ |
| AnnaBridge | 170:e95d10626187 | 1439 | #define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ |
| AnnaBridge | 170:e95d10626187 | 1440 | #define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1441 | #define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1442 | #define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1443 | #define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 1444 | #define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 1445 | #define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1446 | #define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1447 | #define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1448 | #define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ |
| AnnaBridge | 170:e95d10626187 | 1449 | #define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ |
| AnnaBridge | 170:e95d10626187 | 1450 | #define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1451 | #define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1452 | #define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1453 | #define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ |
| AnnaBridge | 170:e95d10626187 | 1454 | #define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ |
| AnnaBridge | 170:e95d10626187 | 1455 | #define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1456 | #define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1457 | #define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1458 | #define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ |
| AnnaBridge | 170:e95d10626187 | 1459 | #define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ |
| AnnaBridge | 170:e95d10626187 | 1460 | #define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1461 | #define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1462 | #define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1463 | #define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ |
| AnnaBridge | 170:e95d10626187 | 1464 | #define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ |
| AnnaBridge | 170:e95d10626187 | 1465 | #define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1466 | #define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1467 | #define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1468 | #define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1469 | #define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1470 | #define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1471 | #define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1472 | #define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1473 | #define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1474 | #define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1475 | #define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1476 | #define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1477 | #define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1478 | #define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1479 | #define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1480 | #define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1481 | #define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1482 | #define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1483 | #define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ |
| AnnaBridge | 170:e95d10626187 | 1484 | #define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ |
| AnnaBridge | 170:e95d10626187 | 1485 | #define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1486 | #define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ |
| AnnaBridge | 170:e95d10626187 | 1487 | |
| AnnaBridge | 170:e95d10626187 | 1488 | /* Bit fields for CMU IFC */ |
| AnnaBridge | 170:e95d10626187 | 1489 | #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1490 | #define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1491 | #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1492 | #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1493 | #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1494 | #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1495 | #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1496 | #define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1497 | #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1498 | #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1499 | #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1500 | #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1501 | #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1502 | #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1503 | #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1504 | #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1505 | #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1506 | #define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1507 | #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1508 | #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1509 | #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1510 | #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1511 | #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1512 | #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1513 | #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1514 | #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1515 | #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1516 | #define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1517 | #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
| AnnaBridge | 170:e95d10626187 | 1518 | #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
| AnnaBridge | 170:e95d10626187 | 1519 | #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1520 | #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1521 | #define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1522 | #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
| AnnaBridge | 170:e95d10626187 | 1523 | #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
| AnnaBridge | 170:e95d10626187 | 1524 | #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1525 | #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1526 | #define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1527 | #define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1528 | #define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1529 | #define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1530 | #define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1531 | #define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1532 | #define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ |
| AnnaBridge | 170:e95d10626187 | 1533 | #define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ |
| AnnaBridge | 170:e95d10626187 | 1534 | #define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1535 | #define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1536 | #define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1537 | #define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ |
| AnnaBridge | 170:e95d10626187 | 1538 | #define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ |
| AnnaBridge | 170:e95d10626187 | 1539 | #define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1540 | #define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1541 | #define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1542 | #define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ |
| AnnaBridge | 170:e95d10626187 | 1543 | #define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ |
| AnnaBridge | 170:e95d10626187 | 1544 | #define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1545 | #define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1546 | #define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1547 | #define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 1548 | #define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 1549 | #define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1550 | #define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1551 | #define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1552 | #define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ |
| AnnaBridge | 170:e95d10626187 | 1553 | #define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ |
| AnnaBridge | 170:e95d10626187 | 1554 | #define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1555 | #define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1556 | #define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1557 | #define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ |
| AnnaBridge | 170:e95d10626187 | 1558 | #define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ |
| AnnaBridge | 170:e95d10626187 | 1559 | #define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1560 | #define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1561 | #define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1562 | #define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ |
| AnnaBridge | 170:e95d10626187 | 1563 | #define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ |
| AnnaBridge | 170:e95d10626187 | 1564 | #define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1565 | #define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1566 | #define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1567 | #define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ |
| AnnaBridge | 170:e95d10626187 | 1568 | #define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ |
| AnnaBridge | 170:e95d10626187 | 1569 | #define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1570 | #define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1571 | #define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1572 | #define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1573 | #define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1574 | #define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1575 | #define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1576 | #define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1577 | #define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1578 | #define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1579 | #define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1580 | #define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1581 | #define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1582 | #define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1583 | #define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1584 | #define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1585 | #define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1586 | #define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ |
| AnnaBridge | 170:e95d10626187 | 1587 | #define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ |
| AnnaBridge | 170:e95d10626187 | 1588 | #define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ |
| AnnaBridge | 170:e95d10626187 | 1589 | #define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1590 | #define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ |
| AnnaBridge | 170:e95d10626187 | 1591 | |
| AnnaBridge | 170:e95d10626187 | 1592 | /* Bit fields for CMU IEN */ |
| AnnaBridge | 170:e95d10626187 | 1593 | #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1594 | #define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1595 | #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1596 | #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1597 | #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1598 | #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1599 | #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1600 | #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1601 | #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1602 | #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1603 | #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1604 | #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1605 | #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1606 | #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1607 | #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1608 | #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1609 | #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1610 | #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1611 | #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1612 | #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
| AnnaBridge | 170:e95d10626187 | 1613 | #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1614 | #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1615 | #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1616 | #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1617 | #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1618 | #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1619 | #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1620 | #define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1621 | #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
| AnnaBridge | 170:e95d10626187 | 1622 | #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
| AnnaBridge | 170:e95d10626187 | 1623 | #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1624 | #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1625 | #define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1626 | #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
| AnnaBridge | 170:e95d10626187 | 1627 | #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
| AnnaBridge | 170:e95d10626187 | 1628 | #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1629 | #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1630 | #define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1631 | #define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1632 | #define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ |
| AnnaBridge | 170:e95d10626187 | 1633 | #define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1634 | #define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1635 | #define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1636 | #define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ |
| AnnaBridge | 170:e95d10626187 | 1637 | #define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ |
| AnnaBridge | 170:e95d10626187 | 1638 | #define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1639 | #define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1640 | #define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1641 | #define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ |
| AnnaBridge | 170:e95d10626187 | 1642 | #define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ |
| AnnaBridge | 170:e95d10626187 | 1643 | #define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1644 | #define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1645 | #define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1646 | #define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ |
| AnnaBridge | 170:e95d10626187 | 1647 | #define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ |
| AnnaBridge | 170:e95d10626187 | 1648 | #define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1649 | #define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1650 | #define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1651 | #define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 1652 | #define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ |
| AnnaBridge | 170:e95d10626187 | 1653 | #define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1654 | #define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1655 | #define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1656 | #define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ |
| AnnaBridge | 170:e95d10626187 | 1657 | #define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ |
| AnnaBridge | 170:e95d10626187 | 1658 | #define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1659 | #define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1660 | #define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1661 | #define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ |
| AnnaBridge | 170:e95d10626187 | 1662 | #define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ |
| AnnaBridge | 170:e95d10626187 | 1663 | #define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1664 | #define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1665 | #define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1666 | #define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ |
| AnnaBridge | 170:e95d10626187 | 1667 | #define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ |
| AnnaBridge | 170:e95d10626187 | 1668 | #define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1669 | #define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1670 | #define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1671 | #define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ |
| AnnaBridge | 170:e95d10626187 | 1672 | #define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ |
| AnnaBridge | 170:e95d10626187 | 1673 | #define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1674 | #define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1675 | #define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1676 | #define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1677 | #define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1678 | #define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1679 | #define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1680 | #define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1681 | #define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1682 | #define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1683 | #define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1684 | #define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1685 | #define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1686 | #define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1687 | #define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ |
| AnnaBridge | 170:e95d10626187 | 1688 | #define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1689 | #define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1690 | #define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ |
| AnnaBridge | 170:e95d10626187 | 1691 | #define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ |
| AnnaBridge | 170:e95d10626187 | 1692 | #define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ |
| AnnaBridge | 170:e95d10626187 | 1693 | #define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1694 | #define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ |
| AnnaBridge | 170:e95d10626187 | 1695 | |
| AnnaBridge | 170:e95d10626187 | 1696 | /* Bit fields for CMU HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1697 | #define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1698 | #define _CMU_HFBUSCLKEN0_MASK 0x000007FFUL /**< Mask for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1699 | #define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1700 | #define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ |
| AnnaBridge | 170:e95d10626187 | 1701 | #define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ |
| AnnaBridge | 170:e95d10626187 | 1702 | #define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1703 | #define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1704 | #define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1705 | #define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ |
| AnnaBridge | 170:e95d10626187 | 1706 | #define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ |
| AnnaBridge | 170:e95d10626187 | 1707 | #define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1708 | #define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1709 | #define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1710 | #define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ |
| AnnaBridge | 170:e95d10626187 | 1711 | #define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ |
| AnnaBridge | 170:e95d10626187 | 1712 | #define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1713 | #define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1714 | #define CMU_HFBUSCLKEN0_ETH (0x1UL << 3) /**< Ethernet Controller Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1715 | #define _CMU_HFBUSCLKEN0_ETH_SHIFT 3 /**< Shift value for CMU_ETH */ |
| AnnaBridge | 170:e95d10626187 | 1716 | #define _CMU_HFBUSCLKEN0_ETH_MASK 0x8UL /**< Bit mask for CMU_ETH */ |
| AnnaBridge | 170:e95d10626187 | 1717 | #define _CMU_HFBUSCLKEN0_ETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1718 | #define CMU_HFBUSCLKEN0_ETH_DEFAULT (_CMU_HFBUSCLKEN0_ETH_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1719 | #define CMU_HFBUSCLKEN0_SDIO (0x1UL << 4) /**< SDIO Controller Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1720 | #define _CMU_HFBUSCLKEN0_SDIO_SHIFT 4 /**< Shift value for CMU_SDIO */ |
| AnnaBridge | 170:e95d10626187 | 1721 | #define _CMU_HFBUSCLKEN0_SDIO_MASK 0x10UL /**< Bit mask for CMU_SDIO */ |
| AnnaBridge | 170:e95d10626187 | 1722 | #define _CMU_HFBUSCLKEN0_SDIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1723 | #define CMU_HFBUSCLKEN0_SDIO_DEFAULT (_CMU_HFBUSCLKEN0_SDIO_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1724 | #define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1725 | #define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ |
| AnnaBridge | 170:e95d10626187 | 1726 | #define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ |
| AnnaBridge | 170:e95d10626187 | 1727 | #define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1728 | #define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1729 | #define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1730 | #define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ |
| AnnaBridge | 170:e95d10626187 | 1731 | #define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ |
| AnnaBridge | 170:e95d10626187 | 1732 | #define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1733 | #define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1734 | #define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1735 | #define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ |
| AnnaBridge | 170:e95d10626187 | 1736 | #define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ |
| AnnaBridge | 170:e95d10626187 | 1737 | #define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1738 | #define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1739 | #define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1740 | #define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ |
| AnnaBridge | 170:e95d10626187 | 1741 | #define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ |
| AnnaBridge | 170:e95d10626187 | 1742 | #define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1743 | #define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1744 | #define CMU_HFBUSCLKEN0_QSPI0 (0x1UL << 9) /**< Quad-SPI Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1745 | #define _CMU_HFBUSCLKEN0_QSPI0_SHIFT 9 /**< Shift value for CMU_QSPI0 */ |
| AnnaBridge | 170:e95d10626187 | 1746 | #define _CMU_HFBUSCLKEN0_QSPI0_MASK 0x200UL /**< Bit mask for CMU_QSPI0 */ |
| AnnaBridge | 170:e95d10626187 | 1747 | #define _CMU_HFBUSCLKEN0_QSPI0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1748 | #define CMU_HFBUSCLKEN0_QSPI0_DEFAULT (_CMU_HFBUSCLKEN0_QSPI0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1749 | #define CMU_HFBUSCLKEN0_USB (0x1UL << 10) /**< Universal Serial Bus Interface Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1750 | #define _CMU_HFBUSCLKEN0_USB_SHIFT 10 /**< Shift value for CMU_USB */ |
| AnnaBridge | 170:e95d10626187 | 1751 | #define _CMU_HFBUSCLKEN0_USB_MASK 0x400UL /**< Bit mask for CMU_USB */ |
| AnnaBridge | 170:e95d10626187 | 1752 | #define _CMU_HFBUSCLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1753 | #define CMU_HFBUSCLKEN0_USB_DEFAULT (_CMU_HFBUSCLKEN0_USB_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1754 | |
| AnnaBridge | 170:e95d10626187 | 1755 | /* Bit fields for CMU HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1756 | #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1757 | #define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1758 | #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1759 | #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ |
| AnnaBridge | 170:e95d10626187 | 1760 | #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ |
| AnnaBridge | 170:e95d10626187 | 1761 | #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1762 | #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1763 | #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1764 | #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ |
| AnnaBridge | 170:e95d10626187 | 1765 | #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ |
| AnnaBridge | 170:e95d10626187 | 1766 | #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1767 | #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1768 | #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1769 | #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ |
| AnnaBridge | 170:e95d10626187 | 1770 | #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ |
| AnnaBridge | 170:e95d10626187 | 1771 | #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1772 | #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1773 | #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1774 | #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ |
| AnnaBridge | 170:e95d10626187 | 1775 | #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ |
| AnnaBridge | 170:e95d10626187 | 1776 | #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1777 | #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1778 | #define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1779 | #define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ |
| AnnaBridge | 170:e95d10626187 | 1780 | #define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ |
| AnnaBridge | 170:e95d10626187 | 1781 | #define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1782 | #define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1783 | #define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1784 | #define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ |
| AnnaBridge | 170:e95d10626187 | 1785 | #define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ |
| AnnaBridge | 170:e95d10626187 | 1786 | #define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1787 | #define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1788 | #define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1789 | #define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ |
| AnnaBridge | 170:e95d10626187 | 1790 | #define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ |
| AnnaBridge | 170:e95d10626187 | 1791 | #define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1792 | #define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1793 | #define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1794 | #define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ |
| AnnaBridge | 170:e95d10626187 | 1795 | #define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ |
| AnnaBridge | 170:e95d10626187 | 1796 | #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1797 | #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1798 | #define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1799 | #define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ |
| AnnaBridge | 170:e95d10626187 | 1800 | #define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ |
| AnnaBridge | 170:e95d10626187 | 1801 | #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1802 | #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1803 | #define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1804 | #define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ |
| AnnaBridge | 170:e95d10626187 | 1805 | #define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ |
| AnnaBridge | 170:e95d10626187 | 1806 | #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1807 | #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1808 | #define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1809 | #define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ |
| AnnaBridge | 170:e95d10626187 | 1810 | #define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ |
| AnnaBridge | 170:e95d10626187 | 1811 | #define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1812 | #define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1813 | #define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1814 | #define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ |
| AnnaBridge | 170:e95d10626187 | 1815 | #define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ |
| AnnaBridge | 170:e95d10626187 | 1816 | #define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1817 | #define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1818 | #define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1819 | #define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ |
| AnnaBridge | 170:e95d10626187 | 1820 | #define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ |
| AnnaBridge | 170:e95d10626187 | 1821 | #define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1822 | #define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1823 | #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1824 | #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ |
| AnnaBridge | 170:e95d10626187 | 1825 | #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ |
| AnnaBridge | 170:e95d10626187 | 1826 | #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1827 | #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1828 | #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1829 | #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ |
| AnnaBridge | 170:e95d10626187 | 1830 | #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ |
| AnnaBridge | 170:e95d10626187 | 1831 | #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1832 | #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1833 | #define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1834 | #define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ |
| AnnaBridge | 170:e95d10626187 | 1835 | #define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ |
| AnnaBridge | 170:e95d10626187 | 1836 | #define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1837 | #define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1838 | #define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1839 | #define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ |
| AnnaBridge | 170:e95d10626187 | 1840 | #define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ |
| AnnaBridge | 170:e95d10626187 | 1841 | #define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1842 | #define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1843 | #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1844 | #define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ |
| AnnaBridge | 170:e95d10626187 | 1845 | #define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ |
| AnnaBridge | 170:e95d10626187 | 1846 | #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1847 | #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1848 | #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1849 | #define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ |
| AnnaBridge | 170:e95d10626187 | 1850 | #define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ |
| AnnaBridge | 170:e95d10626187 | 1851 | #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1852 | #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1853 | #define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1854 | #define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ |
| AnnaBridge | 170:e95d10626187 | 1855 | #define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ |
| AnnaBridge | 170:e95d10626187 | 1856 | #define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1857 | #define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1858 | #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1859 | #define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ |
| AnnaBridge | 170:e95d10626187 | 1860 | #define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ |
| AnnaBridge | 170:e95d10626187 | 1861 | #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1862 | #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1863 | #define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1864 | #define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ |
| AnnaBridge | 170:e95d10626187 | 1865 | #define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ |
| AnnaBridge | 170:e95d10626187 | 1866 | #define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1867 | #define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1868 | #define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CryoTimer Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1869 | #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ |
| AnnaBridge | 170:e95d10626187 | 1870 | #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ |
| AnnaBridge | 170:e95d10626187 | 1871 | #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1872 | #define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1873 | #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1874 | #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ |
| AnnaBridge | 170:e95d10626187 | 1875 | #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ |
| AnnaBridge | 170:e95d10626187 | 1876 | #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1877 | #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1878 | #define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1879 | #define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ |
| AnnaBridge | 170:e95d10626187 | 1880 | #define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ |
| AnnaBridge | 170:e95d10626187 | 1881 | #define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1882 | #define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1883 | |
| AnnaBridge | 170:e95d10626187 | 1884 | /* Bit fields for CMU HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1885 | #define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1886 | #define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1887 | #define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1888 | #define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ |
| AnnaBridge | 170:e95d10626187 | 1889 | #define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ |
| AnnaBridge | 170:e95d10626187 | 1890 | #define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1891 | #define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1892 | #define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1893 | #define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ |
| AnnaBridge | 170:e95d10626187 | 1894 | #define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ |
| AnnaBridge | 170:e95d10626187 | 1895 | #define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1896 | #define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1897 | #define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1898 | #define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ |
| AnnaBridge | 170:e95d10626187 | 1899 | #define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ |
| AnnaBridge | 170:e95d10626187 | 1900 | #define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1901 | #define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1902 | #define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1903 | #define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ |
| AnnaBridge | 170:e95d10626187 | 1904 | #define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ |
| AnnaBridge | 170:e95d10626187 | 1905 | #define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1906 | #define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1907 | #define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1908 | #define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ |
| AnnaBridge | 170:e95d10626187 | 1909 | #define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ |
| AnnaBridge | 170:e95d10626187 | 1910 | #define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1911 | #define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1912 | #define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1913 | #define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ |
| AnnaBridge | 170:e95d10626187 | 1914 | #define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ |
| AnnaBridge | 170:e95d10626187 | 1915 | #define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1916 | #define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1917 | #define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1918 | #define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ |
| AnnaBridge | 170:e95d10626187 | 1919 | #define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ |
| AnnaBridge | 170:e95d10626187 | 1920 | #define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1921 | #define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1922 | #define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1923 | #define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ |
| AnnaBridge | 170:e95d10626187 | 1924 | #define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ |
| AnnaBridge | 170:e95d10626187 | 1925 | #define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1926 | #define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1927 | #define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1928 | #define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ |
| AnnaBridge | 170:e95d10626187 | 1929 | #define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ |
| AnnaBridge | 170:e95d10626187 | 1930 | #define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1931 | #define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1932 | #define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1933 | #define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ |
| AnnaBridge | 170:e95d10626187 | 1934 | #define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ |
| AnnaBridge | 170:e95d10626187 | 1935 | #define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1936 | #define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
| AnnaBridge | 170:e95d10626187 | 1937 | |
| AnnaBridge | 170:e95d10626187 | 1938 | /* Bit fields for CMU LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1939 | #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1940 | #define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1941 | #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1942 | #define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ |
| AnnaBridge | 170:e95d10626187 | 1943 | #define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ |
| AnnaBridge | 170:e95d10626187 | 1944 | #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1945 | #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1946 | #define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1947 | #define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ |
| AnnaBridge | 170:e95d10626187 | 1948 | #define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ |
| AnnaBridge | 170:e95d10626187 | 1949 | #define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1950 | #define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1951 | #define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1952 | #define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ |
| AnnaBridge | 170:e95d10626187 | 1953 | #define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ |
| AnnaBridge | 170:e95d10626187 | 1954 | #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1955 | #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1956 | #define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1957 | #define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ |
| AnnaBridge | 170:e95d10626187 | 1958 | #define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ |
| AnnaBridge | 170:e95d10626187 | 1959 | #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1960 | #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1961 | #define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1962 | #define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ |
| AnnaBridge | 170:e95d10626187 | 1963 | #define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ |
| AnnaBridge | 170:e95d10626187 | 1964 | #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1965 | #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1966 | |
| AnnaBridge | 170:e95d10626187 | 1967 | /* Bit fields for CMU LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1968 | #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1969 | #define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1970 | #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1971 | #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ |
| AnnaBridge | 170:e95d10626187 | 1972 | #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ |
| AnnaBridge | 170:e95d10626187 | 1973 | #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1974 | #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1975 | #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1976 | #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ |
| AnnaBridge | 170:e95d10626187 | 1977 | #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ |
| AnnaBridge | 170:e95d10626187 | 1978 | #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1979 | #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1980 | #define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1981 | #define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ |
| AnnaBridge | 170:e95d10626187 | 1982 | #define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ |
| AnnaBridge | 170:e95d10626187 | 1983 | #define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1984 | #define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1985 | #define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1986 | #define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ |
| AnnaBridge | 170:e95d10626187 | 1987 | #define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ |
| AnnaBridge | 170:e95d10626187 | 1988 | #define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1989 | #define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1990 | |
| AnnaBridge | 170:e95d10626187 | 1991 | /* Bit fields for CMU LFCCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1992 | #define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1993 | #define _CMU_LFCCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFCCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1994 | #define CMU_LFCCLKEN0_USB (0x1UL << 0) /**< Universal Serial Bus Interface Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 1995 | #define _CMU_LFCCLKEN0_USB_SHIFT 0 /**< Shift value for CMU_USB */ |
| AnnaBridge | 170:e95d10626187 | 1996 | #define _CMU_LFCCLKEN0_USB_MASK 0x1UL /**< Bit mask for CMU_USB */ |
| AnnaBridge | 170:e95d10626187 | 1997 | #define _CMU_LFCCLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1998 | #define CMU_LFCCLKEN0_USB_DEFAULT (_CMU_LFCCLKEN0_USB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 1999 | |
| AnnaBridge | 170:e95d10626187 | 2000 | /* Bit fields for CMU LFECLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2001 | #define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2002 | #define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2003 | #define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 2004 | #define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ |
| AnnaBridge | 170:e95d10626187 | 2005 | #define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ |
| AnnaBridge | 170:e95d10626187 | 2006 | #define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2007 | #define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2008 | |
| AnnaBridge | 170:e95d10626187 | 2009 | /* Bit fields for CMU HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2010 | #define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2011 | #define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2012 | #define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2013 | #define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2014 | #define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2015 | #define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2016 | #define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2017 | #define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2018 | #define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2019 | #define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2020 | #define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2021 | #define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2022 | #define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2023 | #define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2024 | #define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2025 | #define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2026 | #define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2027 | #define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2028 | |
| AnnaBridge | 170:e95d10626187 | 2029 | /* Bit fields for CMU HFBUSPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2030 | #define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2031 | #define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2032 | #define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2033 | #define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2034 | #define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2035 | #define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2036 | #define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2037 | #define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2038 | |
| AnnaBridge | 170:e95d10626187 | 2039 | /* Bit fields for CMU HFCOREPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2040 | #define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2041 | #define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2042 | #define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2043 | #define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2044 | #define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2045 | #define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2046 | #define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2047 | #define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2048 | |
| AnnaBridge | 170:e95d10626187 | 2049 | /* Bit fields for CMU HFPERPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2050 | #define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2051 | #define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2052 | #define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2053 | #define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2054 | #define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2055 | #define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2056 | #define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2057 | #define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2058 | |
| AnnaBridge | 170:e95d10626187 | 2059 | /* Bit fields for CMU HFEXPPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2060 | #define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2061 | #define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2062 | #define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2063 | #define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2064 | #define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2065 | #define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2066 | #define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2067 | #define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ |
| AnnaBridge | 170:e95d10626187 | 2068 | |
| AnnaBridge | 170:e95d10626187 | 2069 | /* Bit fields for CMU HFPERPRESCB */ |
| AnnaBridge | 170:e95d10626187 | 2070 | #define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ |
| AnnaBridge | 170:e95d10626187 | 2071 | #define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ |
| AnnaBridge | 170:e95d10626187 | 2072 | #define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2073 | #define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2074 | #define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ |
| AnnaBridge | 170:e95d10626187 | 2075 | #define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ |
| AnnaBridge | 170:e95d10626187 | 2076 | #define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ |
| AnnaBridge | 170:e95d10626187 | 2077 | #define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ |
| AnnaBridge | 170:e95d10626187 | 2078 | |
| AnnaBridge | 170:e95d10626187 | 2079 | /* Bit fields for CMU HFPERPRESCC */ |
| AnnaBridge | 170:e95d10626187 | 2080 | #define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ |
| AnnaBridge | 170:e95d10626187 | 2081 | #define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ |
| AnnaBridge | 170:e95d10626187 | 2082 | #define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2083 | #define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ |
| AnnaBridge | 170:e95d10626187 | 2084 | #define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ |
| AnnaBridge | 170:e95d10626187 | 2085 | #define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ |
| AnnaBridge | 170:e95d10626187 | 2086 | #define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ |
| AnnaBridge | 170:e95d10626187 | 2087 | #define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ |
| AnnaBridge | 170:e95d10626187 | 2088 | |
| AnnaBridge | 170:e95d10626187 | 2089 | /* Bit fields for CMU LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2090 | #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2091 | #define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2092 | #define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ |
| AnnaBridge | 170:e95d10626187 | 2093 | #define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ |
| AnnaBridge | 170:e95d10626187 | 2094 | #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2095 | #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2096 | #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2097 | #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2098 | #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2099 | #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2100 | #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2101 | #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2102 | #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2103 | #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2104 | #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2105 | #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2106 | #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2107 | #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2108 | #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2109 | #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2110 | #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2111 | #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2112 | #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2113 | #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2114 | #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2115 | #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2116 | #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2117 | #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2118 | #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2119 | #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2120 | #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2121 | #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2122 | #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2123 | #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2124 | #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2125 | #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2126 | #define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ |
| AnnaBridge | 170:e95d10626187 | 2127 | #define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ |
| AnnaBridge | 170:e95d10626187 | 2128 | #define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2129 | #define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2130 | #define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2131 | #define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2132 | #define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2133 | #define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2134 | #define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2135 | #define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2136 | #define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2137 | #define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2138 | #define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2139 | #define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2140 | #define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2141 | #define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2142 | #define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2143 | #define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2144 | #define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2145 | #define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2146 | #define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2147 | #define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2148 | #define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2149 | #define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2150 | #define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2151 | #define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2152 | #define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2153 | #define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2154 | #define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2155 | #define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2156 | #define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2157 | #define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2158 | #define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2159 | #define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2160 | #define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ |
| AnnaBridge | 170:e95d10626187 | 2161 | #define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ |
| AnnaBridge | 170:e95d10626187 | 2162 | #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2163 | #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2164 | #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2165 | #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2166 | #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2167 | #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2168 | #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2169 | #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2170 | #define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ |
| AnnaBridge | 170:e95d10626187 | 2171 | #define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ |
| AnnaBridge | 170:e95d10626187 | 2172 | #define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2173 | #define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2174 | #define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2175 | #define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2176 | #define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2177 | #define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2178 | #define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2179 | #define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2180 | #define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2181 | #define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2182 | #define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2183 | #define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2184 | #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2185 | #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2186 | #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2187 | #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2188 | #define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ |
| AnnaBridge | 170:e95d10626187 | 2189 | #define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ |
| AnnaBridge | 170:e95d10626187 | 2190 | #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2191 | #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2192 | #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2193 | #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2194 | #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2195 | #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2196 | #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2197 | #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2198 | #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2199 | #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2200 | #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2201 | #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2202 | #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2203 | #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2204 | #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2205 | #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2206 | #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2207 | #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2208 | #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2209 | #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2210 | #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2211 | #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2212 | #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2213 | #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2214 | #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2215 | #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2216 | #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2217 | #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2218 | #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2219 | #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2220 | #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2221 | #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2222 | |
| AnnaBridge | 170:e95d10626187 | 2223 | /* Bit fields for CMU LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2224 | #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2225 | #define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2226 | #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ |
| AnnaBridge | 170:e95d10626187 | 2227 | #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ |
| AnnaBridge | 170:e95d10626187 | 2228 | #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2229 | #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2230 | #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2231 | #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2232 | #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2233 | #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2234 | #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2235 | #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2236 | #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ |
| AnnaBridge | 170:e95d10626187 | 2237 | #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ |
| AnnaBridge | 170:e95d10626187 | 2238 | #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2239 | #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2240 | #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2241 | #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2242 | #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2243 | #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2244 | #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2245 | #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2246 | #define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ |
| AnnaBridge | 170:e95d10626187 | 2247 | #define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ |
| AnnaBridge | 170:e95d10626187 | 2248 | #define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2249 | #define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2250 | #define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ |
| AnnaBridge | 170:e95d10626187 | 2251 | #define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ |
| AnnaBridge | 170:e95d10626187 | 2252 | #define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2253 | #define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2254 | #define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2255 | #define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2256 | #define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2257 | #define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2258 | #define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2259 | #define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2260 | |
| AnnaBridge | 170:e95d10626187 | 2261 | /* Bit fields for CMU LFEPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2262 | #define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2263 | #define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2264 | #define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ |
| AnnaBridge | 170:e95d10626187 | 2265 | #define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ |
| AnnaBridge | 170:e95d10626187 | 2266 | #define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2267 | #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2268 | #define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2269 | #define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2270 | #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2271 | #define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2272 | |
| AnnaBridge | 170:e95d10626187 | 2273 | /* Bit fields for CMU SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2274 | #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2275 | #define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2276 | #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */ |
| AnnaBridge | 170:e95d10626187 | 2277 | #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2278 | #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2279 | #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2280 | #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2281 | #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */ |
| AnnaBridge | 170:e95d10626187 | 2282 | #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2283 | #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2284 | #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2285 | #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2286 | #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ |
| AnnaBridge | 170:e95d10626187 | 2287 | #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2288 | #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2289 | #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2290 | #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2291 | #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ |
| AnnaBridge | 170:e95d10626187 | 2292 | #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2293 | #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2294 | #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2295 | #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2296 | #define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ |
| AnnaBridge | 170:e95d10626187 | 2297 | #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2298 | #define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2299 | #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2300 | #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2301 | #define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ |
| AnnaBridge | 170:e95d10626187 | 2302 | #define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2303 | #define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ |
| AnnaBridge | 170:e95d10626187 | 2304 | #define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2305 | #define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2306 | #define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ |
| AnnaBridge | 170:e95d10626187 | 2307 | #define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2308 | #define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ |
| AnnaBridge | 170:e95d10626187 | 2309 | #define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2310 | #define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2311 | #define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ |
| AnnaBridge | 170:e95d10626187 | 2312 | #define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2313 | #define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2314 | #define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2315 | #define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2316 | #define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ |
| AnnaBridge | 170:e95d10626187 | 2317 | #define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2318 | #define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2319 | #define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2320 | #define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2321 | #define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ |
| AnnaBridge | 170:e95d10626187 | 2322 | #define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2323 | #define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2324 | #define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2325 | #define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2326 | #define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ |
| AnnaBridge | 170:e95d10626187 | 2327 | #define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ |
| AnnaBridge | 170:e95d10626187 | 2328 | #define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ |
| AnnaBridge | 170:e95d10626187 | 2329 | #define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2330 | #define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2331 | #define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ |
| AnnaBridge | 170:e95d10626187 | 2332 | #define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2333 | #define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2334 | #define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2335 | #define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2336 | #define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ |
| AnnaBridge | 170:e95d10626187 | 2337 | #define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2338 | #define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2339 | #define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2340 | #define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2341 | #define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ |
| AnnaBridge | 170:e95d10626187 | 2342 | #define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2343 | #define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ |
| AnnaBridge | 170:e95d10626187 | 2344 | #define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2345 | #define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
| AnnaBridge | 170:e95d10626187 | 2346 | |
| AnnaBridge | 170:e95d10626187 | 2347 | /* Bit fields for CMU FREEZE */ |
| AnnaBridge | 170:e95d10626187 | 2348 | #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ |
| AnnaBridge | 170:e95d10626187 | 2349 | #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ |
| AnnaBridge | 170:e95d10626187 | 2350 | #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ |
| AnnaBridge | 170:e95d10626187 | 2351 | #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ |
| AnnaBridge | 170:e95d10626187 | 2352 | #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ |
| AnnaBridge | 170:e95d10626187 | 2353 | #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ |
| AnnaBridge | 170:e95d10626187 | 2354 | #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ |
| AnnaBridge | 170:e95d10626187 | 2355 | #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ |
| AnnaBridge | 170:e95d10626187 | 2356 | #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ |
| AnnaBridge | 170:e95d10626187 | 2357 | #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ |
| AnnaBridge | 170:e95d10626187 | 2358 | #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ |
| AnnaBridge | 170:e95d10626187 | 2359 | |
| AnnaBridge | 170:e95d10626187 | 2360 | /* Bit fields for CMU PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2361 | #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2362 | #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2363 | #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 2364 | #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ |
| AnnaBridge | 170:e95d10626187 | 2365 | #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ |
| AnnaBridge | 170:e95d10626187 | 2366 | #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2367 | #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2368 | #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ |
| AnnaBridge | 170:e95d10626187 | 2369 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2370 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2371 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2372 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2373 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2374 | #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2375 | #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2376 | #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2377 | #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 2378 | #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ |
| AnnaBridge | 170:e95d10626187 | 2379 | #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ |
| AnnaBridge | 170:e95d10626187 | 2380 | #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2381 | #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2382 | #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ |
| AnnaBridge | 170:e95d10626187 | 2383 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2384 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2385 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2386 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2387 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2388 | #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2389 | #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2390 | #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2391 | #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 2392 | #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ |
| AnnaBridge | 170:e95d10626187 | 2393 | #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ |
| AnnaBridge | 170:e95d10626187 | 2394 | #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2395 | #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2396 | #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ |
| AnnaBridge | 170:e95d10626187 | 2397 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2398 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2399 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2400 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2401 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2402 | #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2403 | #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2404 | #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2405 | |
| AnnaBridge | 170:e95d10626187 | 2406 | /* Bit fields for CMU ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2407 | #define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2408 | #define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2409 | #define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ |
| AnnaBridge | 170:e95d10626187 | 2410 | #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ |
| AnnaBridge | 170:e95d10626187 | 2411 | #define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2412 | #define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2413 | #define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2414 | #define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2415 | #define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2416 | #define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2417 | #define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2418 | #define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2419 | #define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2420 | #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2421 | #define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2422 | #define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2423 | #define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2424 | #define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2425 | #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2426 | #define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2427 | #define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert clock selected by ADC0CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2428 | #define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ |
| AnnaBridge | 170:e95d10626187 | 2429 | #define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ |
| AnnaBridge | 170:e95d10626187 | 2430 | #define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2431 | #define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2432 | #define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ |
| AnnaBridge | 170:e95d10626187 | 2433 | #define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ |
| AnnaBridge | 170:e95d10626187 | 2434 | #define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2435 | #define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2436 | #define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2437 | #define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2438 | #define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2439 | #define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2440 | #define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2441 | #define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2442 | #define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2443 | #define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2444 | #define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2445 | #define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2446 | #define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2447 | #define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2448 | #define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2449 | #define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2450 | #define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert clock selected by ADC1CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2451 | #define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ |
| AnnaBridge | 170:e95d10626187 | 2452 | #define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ |
| AnnaBridge | 170:e95d10626187 | 2453 | #define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2454 | #define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2455 | |
| AnnaBridge | 170:e95d10626187 | 2456 | /* Bit fields for CMU SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2457 | #define _CMU_SDIOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2458 | #define _CMU_SDIOCTRL_MASK 0x00000083UL /**< Mask for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2459 | #define _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT 0 /**< Shift value for CMU_SDIOCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2460 | #define _CMU_SDIOCTRL_SDIOCLKSEL_MASK 0x3UL /**< Bit mask for CMU_SDIOCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2461 | #define _CMU_SDIOCTRL_SDIOCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2462 | #define _CMU_SDIOCTRL_SDIOCLKSEL_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2463 | #define _CMU_SDIOCTRL_SDIOCLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2464 | #define _CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO 0x00000002UL /**< Mode AUXHFRCO for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2465 | #define _CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO 0x00000003UL /**< Mode USHFRCO for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2466 | #define CMU_SDIOCTRL_SDIOCLKSEL_DEFAULT (_CMU_SDIOCTRL_SDIOCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2467 | #define CMU_SDIOCTRL_SDIOCLKSEL_HFRCO (_CMU_SDIOCTRL_SDIOCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2468 | #define CMU_SDIOCTRL_SDIOCLKSEL_HFXO (_CMU_SDIOCTRL_SDIOCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2469 | #define CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO (_CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2470 | #define CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO (_CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2471 | #define CMU_SDIOCTRL_SDIOCLKDIS (0x1UL << 7) /**< SDIO Reference Clock Disable */ |
| AnnaBridge | 170:e95d10626187 | 2472 | #define _CMU_SDIOCTRL_SDIOCLKDIS_SHIFT 7 /**< Shift value for CMU_SDIOCLKDIS */ |
| AnnaBridge | 170:e95d10626187 | 2473 | #define _CMU_SDIOCTRL_SDIOCLKDIS_MASK 0x80UL /**< Bit mask for CMU_SDIOCLKDIS */ |
| AnnaBridge | 170:e95d10626187 | 2474 | #define _CMU_SDIOCTRL_SDIOCLKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2475 | #define CMU_SDIOCTRL_SDIOCLKDIS_DEFAULT (_CMU_SDIOCTRL_SDIOCLKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_SDIOCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2476 | |
| AnnaBridge | 170:e95d10626187 | 2477 | /* Bit fields for CMU QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2478 | #define _CMU_QSPICTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2479 | #define _CMU_QSPICTRL_MASK 0x00000083UL /**< Mask for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2480 | #define _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT 0 /**< Shift value for CMU_QSPI0CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2481 | #define _CMU_QSPICTRL_QSPI0CLKSEL_MASK 0x3UL /**< Bit mask for CMU_QSPI0CLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2482 | #define _CMU_QSPICTRL_QSPI0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2483 | #define _CMU_QSPICTRL_QSPI0CLKSEL_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2484 | #define _CMU_QSPICTRL_QSPI0CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2485 | #define _CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO 0x00000002UL /**< Mode AUXHFRCO for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2486 | #define _CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO 0x00000003UL /**< Mode USHFRCO for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2487 | #define CMU_QSPICTRL_QSPI0CLKSEL_DEFAULT (_CMU_QSPICTRL_QSPI0CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2488 | #define CMU_QSPICTRL_QSPI0CLKSEL_HFRCO (_CMU_QSPICTRL_QSPI0CLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2489 | #define CMU_QSPICTRL_QSPI0CLKSEL_HFXO (_CMU_QSPICTRL_QSPI0CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2490 | #define CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO (_CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2491 | #define CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO (_CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2492 | #define CMU_QSPICTRL_QSPI0CLKDIS (0x1UL << 7) /**< QSPI0 Reference Clock Disable */ |
| AnnaBridge | 170:e95d10626187 | 2493 | #define _CMU_QSPICTRL_QSPI0CLKDIS_SHIFT 7 /**< Shift value for CMU_QSPI0CLKDIS */ |
| AnnaBridge | 170:e95d10626187 | 2494 | #define _CMU_QSPICTRL_QSPI0CLKDIS_MASK 0x80UL /**< Bit mask for CMU_QSPI0CLKDIS */ |
| AnnaBridge | 170:e95d10626187 | 2495 | #define _CMU_QSPICTRL_QSPI0CLKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2496 | #define CMU_QSPICTRL_QSPI0CLKDIS_DEFAULT (_CMU_QSPICTRL_QSPI0CLKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_QSPICTRL */ |
| AnnaBridge | 170:e95d10626187 | 2497 | |
| AnnaBridge | 170:e95d10626187 | 2498 | /* Bit fields for CMU ROUTEPEN */ |
| AnnaBridge | 170:e95d10626187 | 2499 | #define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ |
| AnnaBridge | 170:e95d10626187 | 2500 | #define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ |
| AnnaBridge | 170:e95d10626187 | 2501 | #define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ |
| AnnaBridge | 170:e95d10626187 | 2502 | #define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ |
| AnnaBridge | 170:e95d10626187 | 2503 | #define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ |
| AnnaBridge | 170:e95d10626187 | 2504 | #define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ |
| AnnaBridge | 170:e95d10626187 | 2505 | #define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ |
| AnnaBridge | 170:e95d10626187 | 2506 | #define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ |
| AnnaBridge | 170:e95d10626187 | 2507 | #define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ |
| AnnaBridge | 170:e95d10626187 | 2508 | #define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ |
| AnnaBridge | 170:e95d10626187 | 2509 | #define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ |
| AnnaBridge | 170:e95d10626187 | 2510 | #define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ |
| AnnaBridge | 170:e95d10626187 | 2511 | #define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ |
| AnnaBridge | 170:e95d10626187 | 2512 | #define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ |
| AnnaBridge | 170:e95d10626187 | 2513 | #define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ |
| AnnaBridge | 170:e95d10626187 | 2514 | #define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ |
| AnnaBridge | 170:e95d10626187 | 2515 | #define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ |
| AnnaBridge | 170:e95d10626187 | 2516 | #define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ |
| AnnaBridge | 170:e95d10626187 | 2517 | #define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ |
| AnnaBridge | 170:e95d10626187 | 2518 | #define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ |
| AnnaBridge | 170:e95d10626187 | 2519 | #define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ |
| AnnaBridge | 170:e95d10626187 | 2520 | #define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ |
| AnnaBridge | 170:e95d10626187 | 2521 | |
| AnnaBridge | 170:e95d10626187 | 2522 | /* Bit fields for CMU ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2523 | #define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2524 | #define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2525 | #define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ |
| AnnaBridge | 170:e95d10626187 | 2526 | #define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ |
| AnnaBridge | 170:e95d10626187 | 2527 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2528 | #define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2529 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2530 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2531 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2532 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2533 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2534 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2535 | #define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2536 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2537 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2538 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2539 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2540 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2541 | #define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ |
| AnnaBridge | 170:e95d10626187 | 2542 | #define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ |
| AnnaBridge | 170:e95d10626187 | 2543 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2544 | #define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2545 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2546 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2547 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2548 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2549 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2550 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2551 | #define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2552 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2553 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2554 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2555 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2556 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2557 | #define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ |
| AnnaBridge | 170:e95d10626187 | 2558 | #define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ |
| AnnaBridge | 170:e95d10626187 | 2559 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2560 | #define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2561 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2562 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2563 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2564 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2565 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2566 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2567 | #define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2568 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2569 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2570 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2571 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2572 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ |
| AnnaBridge | 170:e95d10626187 | 2573 | |
| AnnaBridge | 170:e95d10626187 | 2574 | /* Bit fields for CMU ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2575 | #define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2576 | #define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2577 | #define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ |
| AnnaBridge | 170:e95d10626187 | 2578 | #define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ |
| AnnaBridge | 170:e95d10626187 | 2579 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2580 | #define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2581 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2582 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2583 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2584 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2585 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2586 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2587 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2588 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2589 | #define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2590 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2591 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2592 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2593 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2594 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2595 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2596 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ |
| AnnaBridge | 170:e95d10626187 | 2597 | |
| AnnaBridge | 170:e95d10626187 | 2598 | /* Bit fields for CMU LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2599 | #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2600 | #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2601 | #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ |
| AnnaBridge | 170:e95d10626187 | 2602 | #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ |
| AnnaBridge | 170:e95d10626187 | 2603 | #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2604 | #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2605 | #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2606 | #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2607 | #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2608 | #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2609 | #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2610 | #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2611 | #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2612 | #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ |
| AnnaBridge | 170:e95d10626187 | 2613 | |
| AnnaBridge | 170:e95d10626187 | 2614 | /* Bit fields for CMU HFRCOSS */ |
| AnnaBridge | 170:e95d10626187 | 2615 | #define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ |
| AnnaBridge | 170:e95d10626187 | 2616 | #define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ |
| AnnaBridge | 170:e95d10626187 | 2617 | #define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ |
| AnnaBridge | 170:e95d10626187 | 2618 | #define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ |
| AnnaBridge | 170:e95d10626187 | 2619 | #define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ |
| AnnaBridge | 170:e95d10626187 | 2620 | #define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ |
| AnnaBridge | 170:e95d10626187 | 2621 | #define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ |
| AnnaBridge | 170:e95d10626187 | 2622 | #define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ |
| AnnaBridge | 170:e95d10626187 | 2623 | #define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ |
| AnnaBridge | 170:e95d10626187 | 2624 | #define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ |
| AnnaBridge | 170:e95d10626187 | 2625 | |
| AnnaBridge | 170:e95d10626187 | 2626 | /* Bit fields for CMU USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2627 | #define _CMU_USBCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2628 | #define _CMU_USBCTRL_MASK 0x00000087UL /**< Mask for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2629 | #define _CMU_USBCTRL_USBCLKSEL_SHIFT 0 /**< Shift value for CMU_USBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2630 | #define _CMU_USBCTRL_USBCLKSEL_MASK 0x7UL /**< Bit mask for CMU_USBCLKSEL */ |
| AnnaBridge | 170:e95d10626187 | 2631 | #define _CMU_USBCTRL_USBCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2632 | #define _CMU_USBCTRL_USBCLKSEL_USHFRCO 0x00000000UL /**< Mode USHFRCO for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2633 | #define _CMU_USBCTRL_USBCLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2634 | #define _CMU_USBCTRL_USBCLKSEL_HFXOX2 0x00000002UL /**< Mode HFXOX2 for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2635 | #define _CMU_USBCTRL_USBCLKSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2636 | #define _CMU_USBCTRL_USBCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2637 | #define _CMU_USBCTRL_USBCLKSEL_LFRCO 0x00000005UL /**< Mode LFRCO for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2638 | #define CMU_USBCTRL_USBCLKSEL_DEFAULT (_CMU_USBCTRL_USBCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2639 | #define CMU_USBCTRL_USBCLKSEL_USHFRCO (_CMU_USBCTRL_USBCLKSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2640 | #define CMU_USBCTRL_USBCLKSEL_HFXO (_CMU_USBCTRL_USBCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2641 | #define CMU_USBCTRL_USBCLKSEL_HFXOX2 (_CMU_USBCTRL_USBCLKSEL_HFXOX2 << 0) /**< Shifted mode HFXOX2 for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2642 | #define CMU_USBCTRL_USBCLKSEL_HFRCO (_CMU_USBCTRL_USBCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2643 | #define CMU_USBCTRL_USBCLKSEL_LFXO (_CMU_USBCTRL_USBCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2644 | #define CMU_USBCTRL_USBCLKSEL_LFRCO (_CMU_USBCTRL_USBCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2645 | #define CMU_USBCTRL_USBCLKEN (0x1UL << 7) /**< USB Rate Clock Enable */ |
| AnnaBridge | 170:e95d10626187 | 2646 | #define _CMU_USBCTRL_USBCLKEN_SHIFT 7 /**< Shift value for CMU_USBCLKEN */ |
| AnnaBridge | 170:e95d10626187 | 2647 | #define _CMU_USBCTRL_USBCLKEN_MASK 0x80UL /**< Bit mask for CMU_USBCLKEN */ |
| AnnaBridge | 170:e95d10626187 | 2648 | #define _CMU_USBCTRL_USBCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2649 | #define CMU_USBCTRL_USBCLKEN_DEFAULT (_CMU_USBCTRL_USBCLKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_USBCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2650 | |
| AnnaBridge | 170:e95d10626187 | 2651 | /* Bit fields for CMU USBCRCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2652 | #define _CMU_USBCRCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCRCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2653 | #define _CMU_USBCRCTRL_MASK 0x00000003UL /**< Mask for CMU_USBCRCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2654 | #define CMU_USBCRCTRL_USBCREN (0x1UL << 0) /**< Clock Recovery Enable */ |
| AnnaBridge | 170:e95d10626187 | 2655 | #define _CMU_USBCRCTRL_USBCREN_SHIFT 0 /**< Shift value for CMU_USBCREN */ |
| AnnaBridge | 170:e95d10626187 | 2656 | #define _CMU_USBCRCTRL_USBCREN_MASK 0x1UL /**< Bit mask for CMU_USBCREN */ |
| AnnaBridge | 170:e95d10626187 | 2657 | #define _CMU_USBCRCTRL_USBCREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2658 | #define CMU_USBCRCTRL_USBCREN_DEFAULT (_CMU_USBCRCTRL_USBCREN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2659 | #define CMU_USBCRCTRL_USBLSCRMD (0x1UL << 1) /**< Low Speed Clock Recovery Mode */ |
| AnnaBridge | 170:e95d10626187 | 2660 | #define _CMU_USBCRCTRL_USBLSCRMD_SHIFT 1 /**< Shift value for CMU_USBLSCRMD */ |
| AnnaBridge | 170:e95d10626187 | 2661 | #define _CMU_USBCRCTRL_USBLSCRMD_MASK 0x2UL /**< Bit mask for CMU_USBLSCRMD */ |
| AnnaBridge | 170:e95d10626187 | 2662 | #define _CMU_USBCRCTRL_USBLSCRMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2663 | #define CMU_USBCRCTRL_USBLSCRMD_DEFAULT (_CMU_USBCRCTRL_USBLSCRMD_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */ |
| AnnaBridge | 170:e95d10626187 | 2664 | |
| AnnaBridge | 170:e95d10626187 | 2665 | /** @} */ |
| AnnaBridge | 170:e95d10626187 | 2666 | /** @} End of group EFM32GG11B_CMU */ |
| AnnaBridge | 170:e95d10626187 | 2667 | /** @} End of group Parts */ |
